diff --git a/bsp/bouffalolab/bl602/Kconfig b/bsp/bouffalolab/bl602/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..64247a3ac4a01426e99331309cb9998f31edf3ca --- /dev/null +++ b/bsp/bouffalolab/bl602/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_FE310 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/bouffalolab/bl602/SConscript b/bsp/bouffalolab/bl602/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..534ec8eb5a34d300b893b887a896b5e39e33b613 --- /dev/null +++ b/bsp/bouffalolab/bl602/SConscript @@ -0,0 +1,18 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = str(Dir('#')) +src = Glob('*.c') +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +group = DefineGroup('', src, depend = [''], CPPPATH = []) +#objs += group +Return('objs') diff --git a/bsp/bouffalolab/bl602/SConstruct b/bsp/bouffalolab/bl602/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..c3051306e4f69e0e62dcab10f2b97255602345d3 --- /dev/null +++ b/bsp/bouffalolab/bl602/SConstruct @@ -0,0 +1,31 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/bouffalolab/bl602/applications/SConscript b/bsp/bouffalolab/bl602/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..01eb940dfb35f92c503a78b0b49a4354590f9f3a --- /dev/null +++ b/bsp/bouffalolab/bl602/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/bouffalolab/bl602/applications/main.c b/bsp/bouffalolab/bl602/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..e3cd69f3035f67c1c30549c403e588ee973bb106 --- /dev/null +++ b/bsp/bouffalolab/bl602/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-30 Tanek first version + */ + +#include +#include +#include + +int main(void) +{ + return 0; +} diff --git a/bsp/bouffalolab/bl602/rtconfig.h b/bsp/bouffalolab/bl602/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..c3facdaad6f16875217955b24d2f3a9fdb5191aa --- /dev/null +++ b/bsp/bouffalolab/bl602/rtconfig.h @@ -0,0 +1,127 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 32 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +// #define RT_USING_HOOK +// #define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 1 +#define IDLE_THREAD_STACK_SIZE 512 +// #define RT_DEBUG +// #define RT_DEBUG_COLOR +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +// #define RT_USING_MEMPOOL +// #define RT_USING_SMALL_MEM +// #define RT_USING_MEMTRACE +// #define RT_USING_HEAP + +/* Kernel Device Object */ + +// #define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +// #define RT_CONSOLE_DEVICE_NAME "dusart" + +/* RT-Thread Components */ + +// #define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 512 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 2048 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +/* Device Drivers */ + +/* Using WiFi */ + +/* Using USB */ + +/* POSIX layer and C standard library */ + +/* Network */ + +/* Socket abstraction layer */ + +/* light weight TCP/IP stack */ + +/* Modbus master and slave stack */ + +/* AT commands */ + +/* VBUS(Virtual Software BUS) */ + +/* Utilities */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* Wiced WiFi */ + +/* IoT Cloud */ + +/* security packages */ + +/* language packages */ + +/* multimedia packages */ + +/* tools packages */ + +/* system packages */ + +/* peripheral libraries and drivers */ + +/* miscellaneous packages */ + +/* sample package */ + +/* samples: kernel and components samples */ + +/* example package: hello */ + +/* Privated Packages of RealThread */ + +/* Network Utilities */ + +#endif diff --git a/bsp/bouffalolab/bl602/rtconfig.py b/bsp/bouffalolab/bl602/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..b5e2259dfc2c2870a63fa5224970e2aac3144afb --- /dev/null +++ b/bsp/bouffalolab/bl602/rtconfig.py @@ -0,0 +1,63 @@ +import os +ARCH = 'risc-v' +CPU = 'e310' +# toolchains options +CROSS_TOOL = 'gcc' + +#------- toolchains path ------------------------------------------------------- +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/unknown-gcc/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +CORE = 'risc-v' +MAP_FILE = 'rtthread.map' +LINK_FILE = './freedom-e-sdk/bsp/env/freedom-e300-hifive1/flash.lds' +TARGET_NAME = 'rtthread.bin' + +#------- GCC settings ---------------------------------------------------------- +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'riscv-none-embed-' + CC = PREFIX + 'gcc' + CXX= PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L. -nostartfiles -lc ' + CFLAGS = DEVICE + CFLAGS += ' -save-temps=obj' + AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp' + AFLAGS += ' -Iplatform -Ifreedom-e-sdk/bsp/include -Ifreedom-e-sdk/bsp/env' + LFLAGS = DEVICE + LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE + LFLAGS += ' -T ' + LINK_FILE + LFLAGS += ' -Wl,-wrap=memset' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -g3' + AFLAGS += ' -g3' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' + POST_ACTION += SIZE + ' $TARGET\n' diff --git a/bsp/bouffalolab/bl702/Kconfig b/bsp/bouffalolab/bl702/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..64247a3ac4a01426e99331309cb9998f31edf3ca --- /dev/null +++ b/bsp/bouffalolab/bl702/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_FE310 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/bouffalolab/bl702/SConscript b/bsp/bouffalolab/bl702/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..534ec8eb5a34d300b893b887a896b5e39e33b613 --- /dev/null +++ b/bsp/bouffalolab/bl702/SConscript @@ -0,0 +1,18 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = str(Dir('#')) +src = Glob('*.c') +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +group = DefineGroup('', src, depend = [''], CPPPATH = []) +#objs += group +Return('objs') diff --git a/bsp/bouffalolab/bl702/SConstruct b/bsp/bouffalolab/bl702/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..c3051306e4f69e0e62dcab10f2b97255602345d3 --- /dev/null +++ b/bsp/bouffalolab/bl702/SConstruct @@ -0,0 +1,31 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/bouffalolab/bl702/applications/SConscript b/bsp/bouffalolab/bl702/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..01eb940dfb35f92c503a78b0b49a4354590f9f3a --- /dev/null +++ b/bsp/bouffalolab/bl702/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/bouffalolab/bl702/applications/main.c b/bsp/bouffalolab/bl702/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..e3cd69f3035f67c1c30549c403e588ee973bb106 --- /dev/null +++ b/bsp/bouffalolab/bl702/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-30 Tanek first version + */ + +#include +#include +#include + +int main(void) +{ + return 0; +} diff --git a/bsp/bouffalolab/bl702/rtconfig.h b/bsp/bouffalolab/bl702/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..c3facdaad6f16875217955b24d2f3a9fdb5191aa --- /dev/null +++ b/bsp/bouffalolab/bl702/rtconfig.h @@ -0,0 +1,127 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 32 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +// #define RT_USING_HOOK +// #define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 1 +#define IDLE_THREAD_STACK_SIZE 512 +// #define RT_DEBUG +// #define RT_DEBUG_COLOR +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +// #define RT_USING_MEMPOOL +// #define RT_USING_SMALL_MEM +// #define RT_USING_MEMTRACE +// #define RT_USING_HEAP + +/* Kernel Device Object */ + +// #define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +// #define RT_CONSOLE_DEVICE_NAME "dusart" + +/* RT-Thread Components */ + +// #define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 512 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 2048 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +/* Device Drivers */ + +/* Using WiFi */ + +/* Using USB */ + +/* POSIX layer and C standard library */ + +/* Network */ + +/* Socket abstraction layer */ + +/* light weight TCP/IP stack */ + +/* Modbus master and slave stack */ + +/* AT commands */ + +/* VBUS(Virtual Software BUS) */ + +/* Utilities */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* Wiced WiFi */ + +/* IoT Cloud */ + +/* security packages */ + +/* language packages */ + +/* multimedia packages */ + +/* tools packages */ + +/* system packages */ + +/* peripheral libraries and drivers */ + +/* miscellaneous packages */ + +/* sample package */ + +/* samples: kernel and components samples */ + +/* example package: hello */ + +/* Privated Packages of RealThread */ + +/* Network Utilities */ + +#endif diff --git a/bsp/bouffalolab/bl702/rtconfig.py b/bsp/bouffalolab/bl702/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..b5e2259dfc2c2870a63fa5224970e2aac3144afb --- /dev/null +++ b/bsp/bouffalolab/bl702/rtconfig.py @@ -0,0 +1,63 @@ +import os +ARCH = 'risc-v' +CPU = 'e310' +# toolchains options +CROSS_TOOL = 'gcc' + +#------- toolchains path ------------------------------------------------------- +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/unknown-gcc/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +CORE = 'risc-v' +MAP_FILE = 'rtthread.map' +LINK_FILE = './freedom-e-sdk/bsp/env/freedom-e300-hifive1/flash.lds' +TARGET_NAME = 'rtthread.bin' + +#------- GCC settings ---------------------------------------------------------- +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'riscv-none-embed-' + CC = PREFIX + 'gcc' + CXX= PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L. -nostartfiles -lc ' + CFLAGS = DEVICE + CFLAGS += ' -save-temps=obj' + AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp' + AFLAGS += ' -Iplatform -Ifreedom-e-sdk/bsp/include -Ifreedom-e-sdk/bsp/env' + LFLAGS = DEVICE + LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE + LFLAGS += ' -T ' + LINK_FILE + LFLAGS += ' -Wl,-wrap=memset' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -g3' + AFLAGS += ' -g3' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' + POST_ACTION += SIZE + ' $TARGET\n' diff --git a/bsp/bouffalolab/figures/bl602_iot.png b/bsp/bouffalolab/figures/bl602_iot.png new file mode 100644 index 0000000000000000000000000000000000000000..f520f39ca5cbcb7667a4a935f9c9097b894d5d84 Binary files /dev/null and b/bsp/bouffalolab/figures/bl602_iot.png differ diff --git a/bsp/bouffalolab/figures/bl602_iot_3S.png b/bsp/bouffalolab/figures/bl602_iot_3S.png new file mode 100644 index 0000000000000000000000000000000000000000..f8bb63f959d3194e2779fba4fbde95b3998df02b Binary files /dev/null and b/bsp/bouffalolab/figures/bl602_iot_3S.png differ diff --git a/bsp/bouffalolab/figures/bl706_avb.png b/bsp/bouffalolab/figures/bl706_avb.png new file mode 100644 index 0000000000000000000000000000000000000000..b5a5422c95058554b0c2a1b9fc2a1dbade51d718 Binary files /dev/null and b/bsp/bouffalolab/figures/bl706_avb.png differ diff --git a/bsp/bouffalolab/figures/bl706_iot.png b/bsp/bouffalolab/figures/bl706_iot.png new file mode 100644 index 0000000000000000000000000000000000000000..04119f5559588bc6cefc10bba73528a3ee77e3bd Binary files /dev/null and b/bsp/bouffalolab/figures/bl706_iot.png differ diff --git a/bsp/bouffalolab/figures/bl_604e.png b/bsp/bouffalolab/figures/bl_604e.png new file mode 100644 index 0000000000000000000000000000000000000000..d8e4e36531b4514f416f61de3adb986193becfd1 Binary files /dev/null and b/bsp/bouffalolab/figures/bl_604e.png differ diff --git a/bsp/bouffalolab/figures/bl_hwc_g1.png b/bsp/bouffalolab/figures/bl_hwc_g1.png new file mode 100644 index 0000000000000000000000000000000000000000..4a7545b1fae11b4bf68293dd62d9eaf0dafe7649 Binary files /dev/null and b/bsp/bouffalolab/figures/bl_hwc_g1.png differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/.cproject b/bsp/bouffalolab/libraries/bl_mcu_sdk/.cproject new file mode 100644 index 0000000000000000000000000000000000000000..1a6d3e884017cbdffbbb219c57bd5772132e153b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/.cproject @@ -0,0 +1,180 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + build BOARD=bl706_iot + APP=helloworld + true + false + true + + + make + + clean + true + false + true + + + make + INTERFACE=uart + download + true + false + true + + + + \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/.gitignore b/bsp/bouffalolab/libraries/bl_mcu_sdk/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..841555f42cedf30e7715de1fbeac40b3ae7cf4fe --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/.gitignore @@ -0,0 +1,33 @@ +out/* +build/* +.vscode/settings.json +.settings +*.pyc + +**/.cdk +**/Lst +**/Obj + +examples/*.txt +examples/**/*.mk +examples/**/*.cdkws +examples/**/*.bin +examples/**/*.mk +examples/**/*.bat +examples/**/cdk/*.txt + +tools/bflb_flash_tool/chips/bl702/eflash_loader/eflash_loader_cfg.ini +tools/bflb_flash_tool/chips/bl702/efuse_bootheader/flash_para.bin +tools/bflb_flash_tool/chips/bl702/img_create_mcu/bootinfo.bin +tools/bflb_flash_tool/chips/bl702/img_create_mcu/bootheader.bin +tools/bflb_flash_tool/chips/bl702/img_create_mcu/bootheader_cfg.ini +tools/bflb_flash_tool/chips/bl702/img_create_mcu/efusedata.bin +tools/bflb_flash_tool/chips/bl702/img_create_mcu/efusedata_mask.bin +tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg.ini +tools/bflb_flash_tool/chips/bl702/img_create_mcu/img.bin +tools/bflb_flash_tool/chips/bl702/img_create_mcu/whole_img.bin +tools/bflb_flash_tool/chips/bl702/img_create_mcu/whole_img.pack +tools/bflb_flash_tool/img/project.bin +tools/bflb_flash_tool/log/* + +submodule_commit_info.* \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/.project b/bsp/bouffalolab/libraries/bl_mcu_sdk/.project new file mode 100644 index 0000000000000000000000000000000000000000..3ba4b7def42db56a160fb3e34bf9bebe76d2087f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/.project @@ -0,0 +1,27 @@ + + + bl_mcu_sdk + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/Jlink_bl_mcu_sdk.launch b/bsp/bouffalolab/libraries/bl_mcu_sdk/Jlink_bl_mcu_sdk.launch new file mode 100644 index 0000000000000000000000000000000000000000..2347562b02692362c103ecaca4d28dabb3b8230a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/Jlink_bl_mcu_sdk.launch @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/LICENSE b/bsp/bouffalolab/libraries/bl_mcu_sdk/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..85f48b2176218bada44674517d793677581521e8 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [2020] [BOUFFALO LAB (NANJING) CO., LTD.] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/Makefile b/bsp/bouffalolab/libraries/bl_mcu_sdk/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..c8b91f22e467a2442120539219e845bdef086268 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/Makefile @@ -0,0 +1,45 @@ +BOARD?=bl706_iot +CHIP?=bl702 +APP_DIR?=examples +APP?=helloworld +CPU_ID?=none +COMx?= +BOOTROM?=n + +SUPPORT_FLOAT?=n +SUPPORT_ROMAPI?=y + +INTERFACE?=uart +BAUDRATE ?=2000000 + +FORMAT_DIR?=. + +export BOARD +export CHIP +export APP_DIR +export APP +export BOOTROM +export CPU_ID +export SUPPORT_FLOAT +export SUPPORT_ROMAPI + +# The command to remove a file. +RM = cmake -E remove_directory + +build: + cmake -E make_directory build + cmake -E copy project.build build + make -C ./build -f ./project.build + +download: + ./tools/bflb_flash_tool/bflb_mcu_tool --chipname=$(CHIP) --interface=$(INTERFACE) --port=$(COMx) --baudrate=$(BAUDRATE) + +format: + find $(FORMAT_DIR)/ -name "*.c" -o -name "*.h" -o -name "*.cc" -o -name "*.cpp"| xargs clang-format -style=file -i + +clean: + $(RM) out + $(RM) build + +.PHONY:build clean download format + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/Preload.cmake b/bsp/bouffalolab/libraries/bl_mcu_sdk/Preload.cmake new file mode 100644 index 0000000000000000000000000000000000000000..6c16e9913671d6de3f21cf5bb381b7aede959f0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/Preload.cmake @@ -0,0 +1 @@ +set(CMAKE_GENERATOR "Unix Makefiles" CACHE INTERNAL "" FORCE) \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/README.md b/bsp/bouffalolab/libraries/bl_mcu_sdk/README.md new file mode 100644 index 0000000000000000000000000000000000000000..ee1ab685317f0e7bd8895684195d907c3e3db9e6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/README.md @@ -0,0 +1,210 @@ +[![License](https://img.shields.io/badge/License-Apache--2.0-brightgreen)](LICENSE) +[![Release](https://img.shields.io/github/v/tag/bouffalolab/bl_mcu_sdk?color=s&label=release)]() + +[中文版](README_zh.md) + +# Introduction + +**bl mcu sdk** is an MCU software development kit provided by the Bouffalo Lab Team for BL602/BL604, BL702/BL704/BL706 and other series of chips in the future. + +## Code Framework + +``` + +bl_mcu_sdk +├── bsp +│ ├── board +│ │ ├── bl706_avb +│ │ ├── bl706_iot +│ │ └── bl602_xxx +│ └── bsp_common +├── common +│ ├── device +│ ├── list +│ ├── memheap +│ ├── misc +│ ├── partition +│ ├── ring_buffer +│ └── soft_crc +├── components +│ ├── ble +│ ├── fatfs +│ ├── freertos +│ ├── shell +│ └── usb_stack +├── docs +│ ├── bl70x_docs +│ ├── development_guide +├── drivers +│ ├── bl602_driver +│ └── bl702_driver +├── examples +│ ├── adc +│ ├── audio +│ ├── camera +│ ├── dac +│ ├── dma +│ ├── gpio +│ ├── hellowd +│ ├── i2c +│ ├── i2s +│ ├── memheap +│ ├── spi +│ ├── uart +│ └── usb +├── out +└── tools + ├── bflb_flash_tool + ├── cdk_flashloader + ├── cmake + └── openocd + +``` + +- bsp/bsp_common : stores some common peripheral driver codes related to the board +- bsp/board : stores the board-level description file such as `clock_config.h` (describes the clock configuration file) `pinmux_config.h` (describes the io function file) `peripheral_config.h` (describes the default configuration file of the peripheral) , These files together describe the board hardware information. +- common : stores some common algorithm function libraries that have nothing to do with hardware +- components : store the third-party library public component library +- drivers store the public chip underlying driver library provided by Boliu Intelligence +- examples : store the official sample code +- out : intermediate file, used to store the bin file generated after compiling and linking +- tools : store toolkits related to compiling and downloading +- docs : store tutorial documents and other help information + +For more file directory reference information, please refer to [bl mcu sdk documentation tutorial](http://bouffalolab.gitee.io/bl_mcu_sdk) + +## Hierarchy + +[![Hierarchy](https://z3.ax1x.com/2021/06/18/RpUVoj.png)](https://imgtu.com/i/RpUVoj) + +# Resources + +## Hardware Resources + +- BL706 IOT Development board +[![BL706_IOT](https://z3.ax1x.com/2021/08/06/fnPcLT.png)](https://imgtu.com/i/fnPcLT) + +- BL706 AVB Development Board +[![BL706_AVB](https://z3.ax1x.com/2021/06/18/Rpa7DO.jpg)](https://imgtu.com/i/Rpa7DO) + + +There is currently no official purchase channel. If you want to get the above development board, you can apply for it in any open source community. + +## Chip Manual + +[Chip Reference Manual](https://dev.bouffalolab.com/media/upload/doc/BL702_BL704_706_RM_zh_CN_1.1.pdf) | [Chip Data Manual](https://dev.bouffalolab.com/media/upload/doc/BL702_BL704_BL706_DS_zh_CN_Combo_2.0.pdf) + +For more information, please visit the BouffaloLab developer website: [https://dev.bouffalolab.com/](https://dev.bouffalolab.com/) + + +## Documentation Tutorial + +Contains a quick start tutorial for bl mcu sdk development, api manual and a detailed introduction to the driver framework, etc. + +- [bl mcu sdk documentation tutorial](https://htmlpreview.github.io/?https://github.com/bouffalolab/bl_mcu_sdk/blob/master/docs/development_guide_en/build/html/index.html) + +## Video Tutorial + +- [BL706 MCU Development Series Video Tutorial](https://www.bilibili.com/video/BV1xK4y1P7ur) + +## Development Tools + +### Command Line Development + +For the tools needed for command line development, please refer to [linux development guide](http://bouffalolab.gitee.io/bl_mcu_sdk/get_started/Linux_quick_start_ubuntu.html) + +- [cmake 3.19](https://cmake.org/files/v3.19/), cmake compilation tool, it is recommended to use cmake v3.15 or above +- [riscv64-unknown-elf-gcc](https://gitee.com/bouffalolab/toolchain_gcc_sifive_linux), risc-v linux toolchain,download command: + +``` + +git clone https://gitee.com/bouffalolab/toolchain_gcc_sifive_linux.git + +``` + +### Eclipse Development + +For the tools needed for Eclipse development, please refer to [Eclipse Development Guide](http://bouffalolab.gitee.io/bl_mcu_sdk/get_started/Windows_quick_start_eclipse.html) + +- [Eclipse](https://dev.bouffalolab.com/media/upload/download/BouffaloLab_eclipse_x86_64_win.zip) eclipse development free installation package under Windows +- [riscv64-unknown-elf-gcc](https://gitee.com/bouffalolab/toolchain_gcc_sifive_windows), risc-v windows toolchain,download command: + +``` + +git clone https://gitee.com/bouffalolab/toolchain_gcc_sifive_windows.git + +``` + +- [J-Link v10](https://www.segger.com/downloads/jlink), J-Link debugger, used to debug the chip online, it is recommended to use the hardware of J-Link V10 or above, and the software driver is recommended to use V6 .98 version + +### CDK Development + +For tools needed for CDK development, please refer to [CDK Development Guide](http://bouffalolab.gitee.io/bl_mcu_sdk/get_started/Windows_quick_start_cdk.html) + +- [CDK](https://occ.t-head.cn/development/activities/cdk), Jianchi CDK integrated development environment of T-Head , it is recommended to use CDK v2.8.4 or above + +### Flash Tool + +In addition to using CK-link, J-link and command line programming, it also supports graphical programming tools. +Graphical programming tools provided by Bouffalolab: + +- [Bouffalo Lab Dev Cube For Windows](https://dev.bouffalolab.com/media/upload/download/BouffaloLabDevCube-1.5.3-win32.zip) +- [Bouffalo Lab Dev Cube For Ubuntu](https://dev.bouffalolab.com/media/upload/download/BouffaloLabDevCube-1.5.3-linux-x86.tar.gz) + +## How to make sdk as submodule + +First add bl_mcu_sdk to your own project using the add submodule command, and then commit the gitmodules file to the remote repo. + + +``` + +git submodule add https://gitee.com/bouffalolab/bl_mcu_sdk.git bl_mcu_sdk +cd bl_mcu_sdk +git pull --rebase +cd .. +git add .gitmodules +git add bl_mcu_sdk +git commit -m "xxx" +git push + +``` + +The final catalog presents the following results: + +``` +. +├── hardware +├── xxxx +├── xxxx +├── xxxx +├── bl_mcu_sdk +├── user_code +│ └── gpio +│ ├── gpio_blink +│ ├── gpio_dht11 +│ └── gpio_int + +``` + +### Command Line compile + +``` + cd bl_mcu_sdk + make APP=xxx APP_DIR=../user_code +``` + +## Forum + +Bouffalolab Developer Forum: [https://bbs.bouffalolab.com/](https://bbs.bouffalolab.com/) + +# License + +**bl mcu sdk** is completely open source and follows the Apache License 2.0 open source license agreement. It can be used in commercial products for free and does not require public private code. + +``` +/* + * Copyright (c) 2021 Bouffalolab team + * + * SPDX-License-Identifier: Apache-2.0 + */ + ``` \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/README_zh.md b/bsp/bouffalolab/libraries/bl_mcu_sdk/README_zh.md new file mode 100644 index 0000000000000000000000000000000000000000..96e42f6270dc97ad1e540466ffdc84586e4b73e9 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/README_zh.md @@ -0,0 +1,206 @@ +[![License](https://img.shields.io/badge/License-Apache--2.0-brightgreen)](LICENSE) +[![Release](https://img.shields.io/github/v/tag/bouffalolab/bl_mcu_sdk?color=s&label=release)]() + +[English Version](README.md) + +# 简介 + +**bl mcu sdk** 是博流智能科技团队专为 BL602/BL604,BL702/BL704/BL706 以及未来其他系列芯片提供的 MCU 软件开发包。 + +## 代码框架 + +``` + +bl_mcu_sdk +├── bsp +│ ├── board +│ │ ├── bl706_avb +│ │ ├── bl706_iot +│ │ └── bl602_xxx +│ └── bsp_common +├── common +│ ├── device +│ ├── list +│ ├── memheap +│ ├── misc +│ ├── partition +│ ├── ring_buffer +│ └── soft_crc +├── components +│ ├── ble +│ ├── fatfs +│ ├── freertos +│ ├── shell +│ └── usb_stack +├── docs +│ ├── bl70x_docs +│ ├── development_guide +├── drivers +│ ├── bl602_driver +│ └── bl702_driver +├── examples +│ ├── adc +│ ├── audio +│ ├── camera +│ ├── dac +│ ├── dma +│ ├── gpio +│ ├── hellowd +│ ├── i2c +│ ├── i2s +│ ├── memheap +│ ├── spi +│ ├── uart +│ └── usb +├── out +└── tools + ├── bflb_flash_tool + ├── cdk_flashloader + ├── cmake + └── openocd + +``` + +- bsp/bsp_common : 存放一些板级相关的常用外设驱动代码 +- bsp/board : 存放板级描述文件 `clock_config.h`(描述时钟配置文件) `pinmux_config.h`(描述io功能文件) `peripheral_config.h` (描述外设默认配置文件) 这几个文件共同形成 board 文件夹描述特定应用的所有硬件信息。 +- common : 存放一些常见的与硬件无关的算法函数库 +- components : 存放第三方库公共组件库 +- drivers : 存放博流智能提供的公共芯片底层驱动库 +- examples : 存放官方提供的示例代码 +- out : 中间文件,用来存放编译链接后的产生的bin文件 +- tools : 存放编译下载相关的工具包 +- docs : 存放教程文档以及其他帮助信息 + +更多文件目录参考信息,请查阅 [bl mcu sdk 文档教程](http://bouffalolab.gitee.io/bl_mcu_sdk) +## 层次结构 + +[![层次结构](https://z3.ax1x.com/2021/06/18/RpUVoj.png)](https://imgtu.com/i/RpUVoj) + +# 资源 + +## 硬件资源 + +- BL706 IOT 开发板 +[![BL706_IOT](https://z3.ax1x.com/2021/08/06/fnPcLT.png)](https://imgtu.com/i/fnPcLT) + +- BL706 AVB 开发板 +[![BL706_AVB](https://z3.ax1x.com/2021/06/18/Rpa7DO.jpg)](https://imgtu.com/i/Rpa7DO) + + +目前暂时没有提供官方的购买渠道,如果想获得上述开发板,可到任意开源社区留言申请。 +## 芯片手册 + +[芯片参考手册](https://dev.bouffalolab.com/media/upload/doc/BL702_BL704_706_RM_zh_CN_1.1.pdf)|[芯片数据手册](https://dev.bouffalolab.com/media/upload/doc/BL702_BL704_BL706_DS_zh_CN_Combo_2.0.pdf) + +更多资料请访问 BouffaloLab 开发者网站: [https://dev.bouffalolab.com/](https://dev.bouffalolab.com/) + +## 文档教程 + +包含 bl mcu sdk 开发的快速入门教程, api 手册以及驱动框架等详细介绍 + +- [bl mcu sdk 文档教程](http://bouffalolab.gitee.io/bl_mcu_sdk) + +## 视频教程 + +- [BL706 MCU 开发系列视频教程](https://www.bilibili.com/video/BV1xK4y1P7ur) + +## 开发工具 + +### 命令行开发 + +命令行开发需要的工具,具体使用方法参考 [linux 开发指南](http://bouffalolab.gitee.io/bl_mcu_sdk/get_started/Linux_quick_start_ubuntu.html) + +- [cmake 3.19](https://cmake.org/files/v3.19/), cmake 编译工具,建议使用 cmake v3.15 以上版本 +- [riscv64-unknown-elf-gcc](https://gitee.com/bouffalolab/toolchain_gcc_sifive_linux), risc-v linux 端工具链,下载方式: + +``` + +git clone https://gitee.com/bouffalolab/toolchain_gcc_sifive_linux.git + +``` + +### Eclipse开发 + +Eclipse 开发需要的工具,具体使用方法参考 [Eclipse 开发指南](http://bouffalolab.gitee.io/bl_mcu_sdk/get_started/Windows_quick_start_eclipse.html) + +- [Eclipse](https://dev.bouffalolab.com/media/upload/download/BouffaloLab_eclipse_x86_64_win.zip) Windows 下 eclipse 开发免安装包 +- [riscv64-unknown-elf-gcc](https://gitee.com/bouffalolab/toolchain_gcc_sifive_windows), risc-v windows 端工具链,下载方式: + +``` + +git clone https://gitee.com/bouffalolab/toolchain_gcc_sifive_windows.git + +``` + +- [J-Link v10](https://www.segger.com/downloads/jlink), J-Link 调试器,用于在线调试芯片,建议使用 J-Link V10 以上版本硬件,软件驱动建议使用 V6.98 版本 + +### CDK开发 + +CDK 开发需要的工具,具体使用方法参考 [CDK 开发指南](http://bouffalolab.gitee.io/bl_mcu_sdk/get_started/Windows_quick_start_cdk.html) + +- [CDK](https://occ.t-head.cn/development/activities/cdk),平头哥剑池 CDK 集成开发环境,建议使用 CDK v2.8.4 以上版本 + +### 烧写工具 + +除了可以使用 CK-link、J-link 以及命令行烧写以外,还支持图形化的烧写工具。 +博流提供的图形化烧写工具: + +- [Bouffalo Lab Dev Cube For Windows](https://dev.bouffalolab.com/media/upload/download/BouffaloLabDevCube-1.5.3-win32.zip) +- [Bouffalo Lab Dev Cube For Ubuntu](https://dev.bouffalolab.com/media/upload/download/BouffaloLabDevCube-1.5.3-linux-x86.tar.gz) + +## 如何将 SDK 作为 submodule 使用 + +首先使用添加子模块的命令添加到你自己的工程下,然后将 gitmodules 文件提交到远程仓库。 + +``` + +git submodule add https://gitee.com/bouffalolab/bl_mcu_sdk.git bl_mcu_sdk +cd bl_mcu_sdk +git pull --rebase +cd .. +git add .gitmodules +git add bl_mcu_sdk +git commit -m "xxx" +git push + +``` + +最终目录呈现的结果如下: + +``` +. +├── hardware +├── xxxx +├── xxxx +├── xxxx +├── bl_mcu_sdk +├── user_code +│ └── gpio +│ ├── gpio_blink +│ ├── gpio_dht11 +│ └── gpio_int + +``` + +### 命令行编译方式 + +``` + cd bl_mcu_sdk + make APP=xxx APP_DIR=../user_code +``` + +## 论坛 + +博流开发者交流论坛: [https://bbs.bouffalolab.com/](https://bbs.bouffalolab.com/) + +# 许可协议 + +**bl mcu sdk** 完全开源,遵循 Apache License 2.0 开源许可协议,可以免费在商业产品中使用,并且不需要公开私有代码。 + +``` +/* + * Copyright (c) 2021 Bouffalolab team + * + * SPDX-License-Identifier: Apache-2.0 + */ + ``` \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bl_mcu_flash.launch b/bsp/bouffalolab/libraries/bl_mcu_sdk/bl_mcu_flash.launch new file mode 100644 index 0000000000000000000000000000000000000000..b3fe8bb26b325b83c5afd7dc773e7c883b5aef6a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bl_mcu_flash.launch @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bl_mcu_ram.launch b/bsp/bouffalolab/libraries/bl_mcu_sdk/bl_mcu_ram.launch new file mode 100644 index 0000000000000000000000000000000000000000..100ae6a083cfcf3a6850ddbec9e3b1e33fe5cfa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bl_mcu_ram.launch @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_config.h new file mode 100644 index 0000000000000000000000000000000000000000..ec76db5b983c2ddbb311993b2f9a979f6df70af4 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_config.h @@ -0,0 +1,39 @@ +/** + * @file bl602_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __BL602_CONFIG_H__ +#define __BL602_CONFIG_H__ + +#if defined(bl602_iot) +#include "bl602_iot/clock_config.h" +#include "bl602_iot/peripheral_config.h" +#include "bl602_iot/pinmux_config.h" + +#else +#include "bl602_custom/clock_config.h" +#include "bl602_custom/peripheral_config.h" +#include "bl602_custom/pinmux_config.h" + +#endif + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/clock_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/clock_config.h new file mode 100644 index 0000000000000000000000000000000000000000..ca683c33c81cd3116e2e7fbc47f275ef8de1fe92 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/clock_config.h @@ -0,0 +1,54 @@ +/** + * @file clock_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _CLOCK_CONFIG_H +#define _CLOCK_CONFIG_H + +#define XTAL_TYPE EXTERNAL_XTAL_40M +#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M + +#define BSP_FCLK_DIV 0 +#define BSP_BCLK_DIV 1 + +#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) +#define BSP_UART_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M +#define BSP_UART_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_I2C0) +#define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK +#define BSP_I2C_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_SPI0) +#define BSP_SPI_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK +#define BSP_SPI_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_ADC0) +#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK +#define BSP_ADC_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_DAC0) +#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL +#define BSP_DAC_CLOCK_DIV 1 +#endif + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/peripheral_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/peripheral_config.h new file mode 100644 index 0000000000000000000000000000000000000000..a2767b343a33a039b238b849d5dce13555100fa8 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/peripheral_config.h @@ -0,0 +1,305 @@ +/** + * @file peripheral_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _PERIPHERAL_CONFIG_H_ +#define _PERIPHERAL_CONFIG_H_ + +/* PERIPHERAL USING LIST */ +#define BSP_USING_UART0 +#define BSP_USING_UART1 +/* ----------------------*/ + +/* PERIPHERAL With DMA LIST */ + +#define BSP_USING_DMA0_CH0 +#define BSP_USING_DMA0_CH1 +#define BSP_USING_DMA0_CH2 +#define BSP_USING_DMA0_CH3 +#define BSP_USING_DMA0_CH4 +#define BSP_USING_DMA0_CH5 +#define BSP_USING_DMA0_CH6 +#define BSP_USING_DMA0_CH7 + +/* PERIPHERAL CONFIG */ +#if defined(BSP_USING_ADC0) +#ifndef ADC0_CONFIG +#define ADC0_CONFIG \ + { \ + .clk_div = ADC_CLOCK_DIV_32, \ + .vref = ADC_VREF_3P2V, \ + .continuous_conv_mode = DISABLE, \ + .differential_mode = DISABLE, \ + .data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \ + .fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE, \ + .gain = ADC_GAIN_1 \ + } +#endif +#endif + +#if defined(BSP_USING_DAC0) +#ifndef DAC_CONFIG +#define DAC_CONFIG \ + { \ + .clk = DAC_CLK_500KHZ, \ + .pin.dac0 = GLB_GPIO_PIN_11, \ + .pin.pin_num = 1, \ + } +#endif +#endif + +#if defined(BSP_USING_UART0) +#ifndef UART0_CONFIG +#define UART0_CONFIG \ + { \ + .id = 0, \ + .baudrate = 2000000, \ + .databits = UART_DATA_LEN_8, \ + .stopbits = UART_STOP_ONE, \ + .parity = UART_PAR_NONE, \ + .fifo_threshold = 1, \ + } +#endif +#endif + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .id = 1, \ + .baudrate = 2000000, \ + .databits = UART_DATA_LEN_8, \ + .stopbits = UART_STOP_ONE, \ + .parity = UART_PAR_NONE, \ + .fifo_threshold = 64, \ + } +#endif +#endif + +#if defined(BSP_USING_SPI0) +#ifndef SPI0_CONFIG +#define SPI0_CONFIG \ + { \ + .id = 0, \ + .clk = 18000000, \ + .mode = SPI_MASTER_MODE, \ + .direction = SPI_MSB_BYTE0_DIRECTION_FIRST, \ + .clk_polaraity = SPI_POLARITY_LOW, \ + .clk_phase = SPI_PHASE_1EDGE, \ + .datasize = SPI_DATASIZE_8BIT, \ + .fifo_threshold = 1, \ + } +#endif +#endif + +#if defined(BSP_USING_PWM_CH2) +#ifndef PWM_CH2_CONFIG +#define PWM_CH2_CONFIG \ + { \ + .ch = 2, \ + .frequency = 1000000, \ + .dutycycle = 0, \ + .it_pulse_count = 0, \ + } +#endif +#endif + +#if defined(BSP_USING_I2S0) +#ifndef I2S0_CONFIG +#define I2S0_CONFIG \ + { \ + .id = 0, \ + .iis_mode = I2S_MODE_MASTER, \ + .interface_mode = I2S_MODE_LEFT, \ + .sampl_freq_hz = 16 * 1000, \ + .channel_num = I2S_FS_CHANNELS_NUM_MONO, \ + .frame_size = I2S_FRAME_LEN_16, \ + .data_size = I2S_DATA_LEN_16, \ + .fifo_threshold = 8, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH0) +#ifndef DMA0_CH0_CONFIG +#define DMA0_CH0_CONFIG \ + { \ + .id = 0, \ + .ch = 0, \ + .direction = DMA_MEMORY_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_32BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_32BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH1) +#ifndef DMA0_CH1_CONFIG +#define DMA0_CH1_CONFIG \ + { \ + .id = 0, \ + .ch = 1, \ + .direction = DMA_MEMORY_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH2) +#ifndef DMA0_CH2_CONFIG +#define DMA0_CH2_CONFIG \ + { \ + .id = 0, \ + .ch = 2, \ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_UART1_TX, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH3) +#ifndef DMA0_CH3_CONFIG +#define DMA0_CH3_CONFIG \ + { \ + .id = 0, \ + .ch = 3, \ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_SPI0_TX, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH4) +#ifndef DMA0_CH4_CONFIG +#define DMA0_CH4_CONFIG \ + { \ + .id = 0, \ + .ch = 4, \ + .direction = DMA_PERIPH_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_SPI0_RX, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH5) +#ifndef DMA0_CH5_CONFIG +#define DMA0_CH5_CONFIG \ + { \ + .id = 0, \ + .ch = 5, \ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_CYCLE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_I2S_TX, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH6) +#ifndef DMA0_CH6_CONFIG +#define DMA0_CH6_CONFIG \ + { \ + .id = 0, \ + .ch = 6, \ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_CYCLE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_I2S_TX, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH7) +#ifndef DMA0_CH7_CONFIG +#define DMA0_CH7_CONFIG \ + { \ + .id = 0, \ + .ch = 0, \ + .direction = DMA_MEMORY_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_32BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_32BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_I2C0) +#ifndef I2C0_CONFIG +#define I2C0_CONFIG \ + { \ + .id = 0, \ + .mode = I2C_HW_MODE, \ + .phase = 15, \ + } +#endif +#endif + +#if defined(BSP_USING_TIMER_CH0) +#ifndef TIMER_CH0_CONFIG +#define TIMER_CH0_CONFIG \ + { \ + .id = 0, \ + .ch = 0, \ + .cnt_mode = TIMER_CNT_PRELOAD, \ + .pl_trig_src = TIMER_PL_TRIG_COMP0, \ + } +#endif +#endif + +#if defined(BSP_USING_TIMER_CH1) +#ifndef TIMER_CH1_CONFIG +#define TIMER_CH1_CONFIG \ + { \ + .id = 0, \ + .ch = 1, \ + .cnt_mode = TIMER_CNT_PRELOAD, \ + .pl_trig_src = TIMER_PL_TRIG_COMP0, \ + } +#endif +#endif + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/pinmux_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/pinmux_config.h new file mode 100644 index 0000000000000000000000000000000000000000..4f528edd8bbc02865a2b6193bcc49eec40a8fae7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/bl602_iot/pinmux_config.h @@ -0,0 +1,144 @@ +/** + * @file pinmux_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _PINMUX_CONFIG_H +#define _PINMUX_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// GPIO0 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio0 function +#define CONFIG_GPIO0_FUNC GPIO_FUN_UNUSED + +// GPIO1 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio1 function +#define CONFIG_GPIO1_FUNC GPIO_FUN_UNUSED + +// GPIO2 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio2 function +#define CONFIG_GPIO2_FUNC GPIO_FUN_UNUSED + +// GPIO3 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_QDEC] +// config gpio3 function +#define CONFIG_GPIO3_FUNC GPIO_FUN_UNUSED + +// GPIO4 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio4 function +#define CONFIG_GPIO4_FUNC GPIO_FUN_UNUSED + +// GPIO5 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_QDEC] +// config gpio5 function +#define CONFIG_GPIO5_FUNC GPIO_FUN_UNUSED + +// GPIO6 <2> [GPIO_FUN_UNUSED//GPIO_FUN_CLK_OUT//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_QDEC] +// config gpio6 function +#define CONFIG_GPIO6_FUNC GPIO_FUN_UNUSED + +// GPIO7 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_USB//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio7 function +#define CONFIG_GPIO7_FUNC GPIO_FUN_UART0_RX + +// GPIO8 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_USB//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio8 function +#define CONFIG_GPIO8_FUNC GPIO_FUN_UNUSED + +// GPIO9 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio9 function +#define CONFIG_GPIO9_FUNC GPIO_FUN_UNUSED + +// GPIO10 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio10 function +#define CONFIG_GPIO10_FUNC GPIO_FUN_UNUSED + +// GPIO11 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio11 function +#define CONFIG_GPIO11_FUNC GPIO_FUN_UNUSED + +// GPIO12 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio12 function +#define CONFIG_GPIO12_FUNC GPIO_FUN_UNUSED + +// GPIO13 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio13 function +#define CONFIG_GPIO13_FUNC GPIO_FUN_UNUSED + +// GPIO14 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio14 function +#define CONFIG_GPIO14_FUNC GPIO_FUN_UNUSED + +// GPIO15 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio15 function +#define CONFIG_GPIO15_FUNC GPIO_FUN_UNUSED + +// GPIO16 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio16 function +#define CONFIG_GPIO16_FUNC GPIO_FUN_UART0_TX + +// GPIO17 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio17 function +#define CONFIG_GPIO17_FUNC GPIO_FUN_UNUSED + +// GPIO18 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio18 function +#define CONFIG_GPIO18_FUNC GPIO_FUN_UNUSED + +// GPIO19 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio19 function +#define CONFIG_GPIO19_FUNC GPIO_FUN_UNUSED + +// GPIO20 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio20 function +#define CONFIG_GPIO20_FUNC GPIO_FUN_UNUSED + +// GPIO21 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio21 function +#define CONFIG_GPIO21_FUNC GPIO_FUN_UNUSED + +// GPIO22 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio22 function +#define CONFIG_GPIO22_FUNC GPIO_FUN_UNUSED + +// GPIO23 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio23 function +#define CONFIG_GPIO23_FUNC GPIO_FUN_UNUSED + +// GPIO24 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio24 function +#define CONFIG_GPIO24_FUNC GPIO_FUN_UNUSED + +// GPIO25 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio25 function +#define CONFIG_GPIO25_FUNC GPIO_FUN_UNUSED + +// GPIO26 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio26 function +#define CONFIG_GPIO26_FUNC GPIO_FUN_UNUSED + +// GPIO27 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio27 function +#define CONFIG_GPIO27_FUNC GPIO_FUN_UNUSED + +// GPIO28 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio28 function +#define CONFIG_GPIO28_FUNC GPIO_FUN_UNUSED + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/board.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/board.c new file mode 100644 index 0000000000000000000000000000000000000000..deacfabc52f62bece5aa882c9d838e5ec49cfbe6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl602/board.c @@ -0,0 +1,220 @@ +/** + * @file board.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "hal_gpio.h" +#include "hal_clock.h" +#include "bl602_glb.h" +#include "bl602_config.h" + +struct pin_mux_cfg { + uint8_t pin; + uint16_t func; +}; + +static const struct pin_mux_cfg af_pin_table[] = { +#ifdef CONFIG_GPIO0_FUNC + { .pin = GPIO_PIN_0, + .func = CONFIG_GPIO0_FUNC }, +#endif +#ifdef CONFIG_GPIO1_FUNC + { .pin = GPIO_PIN_1, + .func = CONFIG_GPIO1_FUNC }, +#endif +#ifdef CONFIG_GPIO2_FUNC + { .pin = GPIO_PIN_2, + .func = CONFIG_GPIO2_FUNC }, +#endif +#ifdef CONFIG_GPIO3_FUNC + { .pin = GPIO_PIN_3, + .func = CONFIG_GPIO3_FUNC }, +#endif +#ifdef CONFIG_GPIO4_FUNC + { .pin = GPIO_PIN_4, + .func = CONFIG_GPIO4_FUNC }, +#endif +#ifdef CONFIG_GPIO5_FUNC + { .pin = GPIO_PIN_5, + .func = CONFIG_GPIO5_FUNC }, +#endif +#ifdef CONFIG_GPIO6_FUNC + { .pin = GPIO_PIN_6, + .func = CONFIG_GPIO6_FUNC }, +#endif +#ifdef CONFIG_GPIO7_FUNC + { .pin = GPIO_PIN_7, + .func = CONFIG_GPIO7_FUNC }, +#endif +#ifdef CONFIG_GPIO8_FUNC + { .pin = GPIO_PIN_8, + .func = CONFIG_GPIO8_FUNC }, +#endif +#ifdef CONFIG_GPIO9_FUNC + { .pin = GPIO_PIN_9, + .func = CONFIG_GPIO9_FUNC }, +#endif +#ifdef CONFIG_GPIO10_FUNC + { .pin = GPIO_PIN_10, + .func = CONFIG_GPIO10_FUNC }, +#endif +#ifdef CONFIG_GPIO11_FUNC + { .pin = GPIO_PIN_11, + .func = CONFIG_GPIO11_FUNC }, +#endif +#ifdef CONFIG_GPIO12_FUNC + { .pin = GPIO_PIN_12, + .func = CONFIG_GPIO12_FUNC }, +#endif +#ifdef CONFIG_GPIO13_FUNC + { .pin = GPIO_PIN_13, + .func = CONFIG_GPIO13_FUNC }, +#endif +#ifdef CONFIG_GPIO14_FUNC + { .pin = GPIO_PIN_14, + .func = CONFIG_GPIO14_FUNC }, +#endif +#ifdef CONFIG_GPIO15_FUNC + { .pin = GPIO_PIN_15, + .func = CONFIG_GPIO15_FUNC }, +#endif +#ifdef CONFIG_GPIO16_FUNC + { .pin = GPIO_PIN_16, + .func = CONFIG_GPIO16_FUNC }, +#endif +#ifdef CONFIG_GPIO17_FUNC + { .pin = GPIO_PIN_17, + .func = CONFIG_GPIO17_FUNC }, +#endif +#ifdef CONFIG_GPIO18_FUNC + { .pin = GPIO_PIN_18, + .func = CONFIG_GPIO18_FUNC }, +#endif +#ifdef CONFIG_GPIO19_FUNC + { .pin = GPIO_PIN_19, + .func = CONFIG_GPIO19_FUNC }, +#endif +#ifdef CONFIG_GPIO20_FUNC + { .pin = GPIO_PIN_20, + .func = CONFIG_GPIO20_FUNC }, +#endif +#ifdef CONFIG_GPIO21_FUNC + { .pin = GPIO_PIN_21, + .func = CONFIG_GPIO21_FUNC }, +#endif +#ifdef CONFIG_GPIO22_FUNC + { .pin = GPIO_PIN_22, + .func = CONFIG_GPIO22_FUNC }, +#endif +#ifdef CONFIG_GPIO23_FUNC + { .pin = GPIO_PIN_23, + .func = CONFIG_GPIO23_FUNC }, +#endif +#ifdef CONFIG_GPIO24_FUNC + { .pin = GPIO_PIN_24, + .func = CONFIG_GPIO24_FUNC }, +#endif +#ifdef CONFIG_GPIO25_FUNC + { .pin = GPIO_PIN_25, + .func = CONFIG_GPIO25_FUNC }, +#endif +#ifdef CONFIG_GPIO26_FUNC + { .pin = GPIO_PIN_26, + .func = CONFIG_GPIO26_FUNC }, +#endif +#ifdef CONFIG_GPIO27_FUNC + { .pin = GPIO_PIN_27, + .func = CONFIG_GPIO27_FUNC }, +#endif +#ifdef CONFIG_GPIO28_FUNC + { .pin = GPIO_PIN_28, + .func = CONFIG_GPIO28_FUNC }, +#endif +}; + +static void board_pin_mux_init(void) +{ + GLB_GPIO_Cfg_Type gpio_cfg; + + gpio_cfg.drive = 0; + gpio_cfg.smtCtrl = 1; + + for (int i = 0; i < sizeof(af_pin_table) / sizeof(af_pin_table[0]); i++) { + gpio_cfg.gpioMode = GPIO_MODE_AF; + gpio_cfg.pullType = GPIO_PULL_UP; + gpio_cfg.gpioPin = af_pin_table[i].pin; + gpio_cfg.gpioFun = af_pin_table[i].func; + + if (af_pin_table[i].func == GPIO_FUN_UNUSED) { + continue; + } else if (af_pin_table[i].func == GPIO_FUN_PWM) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + } + // else if((af_pin_table[i].func == GPIO_FUN_DAC)|| (af_pin_table[i].func == GPIO_FUN_ADC)) + // { + // gpio_cfg.gpioFun = GPIO_FUN_ANALOG; + // gpio_cfg.gpioMode = GPIO_MODE_ANALOG; + // } + else if ((af_pin_table[i].func & 0x70) == 0x70) { + gpio_cfg.gpioFun = GPIO_FUN_UART; + uint8_t sig = af_pin_table[i].func & 0x07; + GLB_UART_Fun_Sel((gpio_cfg.gpioPin % 8), sig); + } + + GLB_GPIO_Init(&gpio_cfg); + } +} + +static void board_clock_init(void) +{ + system_clock_init(); + peripheral_clock_init(); +} + +void bl_show_info(void) +{ + MSG("\r\n"); + MSG(" ____ __ __ _ _ _ \r\n"); + MSG(" | _ \\ / _|/ _| | | | | | | \r\n"); + MSG(" | |_) | ___ _ _| |_| |_ __ _| | ___ | | __ _| |__ \r\n"); + MSG(" | _ < / _ \\| | | | _| _/ _` | |/ _ \\| |/ _` | '_ \\ \r\n"); + MSG(" | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |\r\n"); + MSG(" |____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/|_|\\__,_|_.__/ \r\n"); + MSG("\r\n"); + MSG("Build:%s,%s\r\n", __TIME__, __DATE__); + MSG("Copyright (c) 2021 Bouffalolab team\r\n"); + +#if 0 + MSG("root clock:%dM\r\n", system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / 1000000); + MSG("fclk clock:%dM\r\n", system_clock_get(SYSTEM_CLOCK_FCLK) / 1000000); + MSG("bclk clock:%dM\r\n", system_clock_get(SYSTEM_CLOCK_BCLK) / 1000000); + + MSG("uart clock:%dM\r\n", peripheral_clock_get(PERIPHERAL_CLOCK_UART) / 1000000); + MSG("spi clock:%dM\r\n", peripheral_clock_get(PERIPHERAL_CLOCK_SPI) / 1000000); + MSG("i2c clock:%dM\r\n", peripheral_clock_get(PERIPHERAL_CLOCK_I2C) / 1000000); +#endif +} + +void board_init(void) +{ + board_clock_init(); + board_pin_mux_init(); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl702_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl702_config.h new file mode 100644 index 0000000000000000000000000000000000000000..781e603acca677b9414073db5f3cf443c614ce9d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl702_config.h @@ -0,0 +1,39 @@ +/** + * @file bl702_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __BL702_CONFIG_H__ +#define __BL702_CONFIG_H__ + +#if defined(bl706_iot) +#include "bl706_iot/clock_config.h" +#include "bl706_iot/peripheral_config.h" +#include "bl706_iot/pinmux_config.h" + +#else +#include "bl702_custom/clock_config.h" +#include "bl702_custom/peripheral_config.h" +#include "bl702_custom/pinmux_config.h" + +#endif + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/clock_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/clock_config.h new file mode 100644 index 0000000000000000000000000000000000000000..d7dd2b10759f4c0fc1cd472afe67adef9cdd4bae --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/clock_config.h @@ -0,0 +1,86 @@ +/** + * @file clock_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _CLOCK_CONFIG_H +#define _CLOCK_CONFIG_H + +#define XTAL_TYPE EXTERNAL_XTAL_32M +#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_144M +#define BSP_AUDIO_PLL_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ + +#define BSP_FCLK_DIV 0 +#define BSP_BCLK_DIV 1 + +#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) +#define BSP_UART_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M +#define BSP_UART_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_I2C0) +#define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK +#define BSP_I2C_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_SPI0) +#define BSP_SPI_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK +#define BSP_SPI_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_TIMER0) +#define BSP_TIMER0_CLOCK_SOURCE ROOT_CLOCK_SOURCE_FCLK +#define BSP_TIMER0_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_TIMER1) +#define BSP_TIMER1_CLOCK_SOURCE ROOT_CLOCK_SOURCE_FCLK +#define BSP_TIMER1_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_WDT) +#define BSP_WDT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_FCLK +#define BSP_WDT_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || \ + defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || \ + defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5) +#define BSP_PWM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK +#define BSP_PWM_CLOCK_DIV 32 +#endif +#if defined(BSP_USING_IR) +#define BSP_IR_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK +#define BSP_IR_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_ADC0) +#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK +#define BSP_ADC_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_DAC0) +#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ +#define BSP_DAC_CLOCK_DIV 1 +#endif +#if defined(BSP_USING_CAM) +#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M +#define BSP_CAM_CLOCK_DIV 3 +#endif +#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || \ + defined(BSP_USING_QDEC2) || defined(BSP_USING_KEYSCAN) +#define BSP_QDEC_KEYSCAN_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK +#define BSP_QDEC_KEYSCAN_CLOCK_DIV 31 +#endif + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/peripheral_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/peripheral_config.h new file mode 100644 index 0000000000000000000000000000000000000000..690e0d0a2cf48460c29a4c28e3d369cae1884016 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/peripheral_config.h @@ -0,0 +1,450 @@ +/** + * @file peripheral_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _PERIPHERAL_CONFIG_H_ +#define _PERIPHERAL_CONFIG_H_ + +/* PERIPHERAL USING LIST */ +#define BSP_USING_ADC0 +#define BSP_USING_DAC0 +#define BSP_USING_UART0 +#define BSP_USING_UART1 +#define BSP_USING_SPI0 +#define BSP_USING_I2C0 +#define BSP_USING_I2S0 +#define BSP_USING_USB +#define BSP_USING_PWM_CH0 +#define BSP_USING_PWM_CH1 +#define BSP_USING_PWM_CH2 +#define BSP_USING_PWM_CH3 +#define BSP_USING_TIMER0 +#define BSP_USING_TIMER1 +#define BSP_USING_KEYSCAN +#define BSP_USING_QDEC0 +#define BSP_USING_QDEC1 +#define BSP_USING_QDEC2 +#define BSP_USING_WDT +/* ----------------------*/ + +/* PERIPHERAL With DMA LIST */ + +#define BSP_USING_DMA0_CH0 +#define BSP_USING_DMA0_CH1 +#define BSP_USING_DMA0_CH2 +#define BSP_USING_DMA0_CH3 +#define BSP_USING_DMA0_CH4 +#define BSP_USING_DMA0_CH5 +#define BSP_USING_DMA0_CH6 +#define BSP_USING_DMA0_CH7 + +/* PERIPHERAL CONFIG */ +#if defined(BSP_USING_ADC0) +#ifndef ADC0_CONFIG +#define ADC0_CONFIG \ + { \ + .clk_div = ADC_CLOCK_DIV_32, \ + .vref = ADC_VREF_3V2, \ + .continuous_conv_mode = DISABLE, \ + .differential_mode = DISABLE, \ + .data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \ + .fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE, \ + .gain = ADC_GAIN_1 \ + } +#endif +#endif + +#if defined(BSP_USING_DAC0) +#ifndef DAC_CONFIG +#define DAC_CONFIG \ + { \ + .clk = DAC_CLK_500KHZ, \ + .pin.dac0 = GLB_GPIO_PIN_11, \ + .pin.pin_num = 1, \ + } +#endif +#endif + +#if defined(BSP_USING_UART0) +#ifndef UART0_CONFIG +#define UART0_CONFIG \ + { \ + .id = 0, \ + .baudrate = 2000000, \ + .databits = UART_DATA_LEN_8, \ + .stopbits = UART_STOP_ONE, \ + .parity = UART_PAR_NONE, \ + .fifo_threshold = 1, \ + } +#endif +#endif + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .id = 1, \ + .baudrate = 2000000, \ + .databits = UART_DATA_LEN_8, \ + .stopbits = UART_STOP_ONE, \ + .parity = UART_PAR_NONE, \ + .fifo_threshold = 64, \ + } +#endif +#endif + +#if defined(BSP_USING_SPI0) +#ifndef SPI0_CONFIG +#define SPI0_CONFIG \ + { \ + .id = 0, \ + .clk = 18000000, \ + .mode = SPI_MASTER_MODE, \ + .direction = SPI_MSB_BYTE0_DIRECTION_FIRST, \ + .clk_polaraity = SPI_POLARITY_LOW, \ + .clk_phase = SPI_PHASE_1EDGE, \ + .datasize = SPI_DATASIZE_8BIT, \ + .fifo_threshold = 1, \ + } +#endif +#endif + +#if defined(BSP_USING_PWM_CH0) +#ifndef PWM_CH0_CONFIG +#define PWM_CH0_CONFIG \ + { \ + .ch = 0, \ + .polarity_invert_mode = DISABLE, \ + .period = 0, \ + .threshold_low = 0, \ + .threshold_high = 0, \ + .it_pulse_count = 0, \ + } +#endif +#endif + +#if defined(BSP_USING_PWM_CH1) +#ifndef PWM_CH1_CONFIG +#define PWM_CH1_CONFIG \ + { \ + .ch = 1, \ + .polarity_invert_mode = DISABLE, \ + .period = 0, \ + .threshold_low = 0, \ + .threshold_high = 0, \ + .it_pulse_count = 0, \ + } +#endif +#endif + +#if defined(BSP_USING_PWM_CH2) +#ifndef PWM_CH2_CONFIG +#define PWM_CH2_CONFIG \ + { \ + .ch = 2, \ + .polarity_invert_mode = DISABLE, \ + .period = 0, \ + .threshold_low = 0, \ + .threshold_high = 0, \ + .it_pulse_count = 0, \ + } +#endif +#endif + +#if defined(BSP_USING_PWM_CH3) +#ifndef PWM_CH3_CONFIG +#define PWM_CH3_CONFIG \ + { \ + .ch = 3, \ + .polarity_invert_mode = DISABLE, \ + .period = 0, \ + .threshold_low = 0, \ + .threshold_high = 0, \ + .it_pulse_count = 0, \ + } +#endif +#endif + +#if defined(BSP_USING_I2S0) +#ifndef I2S0_CONFIG +#define I2S0_CONFIG \ + { \ + .id = 0, \ + .iis_mode = I2S_MODE_MASTER, \ + .interface_mode = I2S_MODE_LEFT, \ + .sampl_freq_hz = 16 * 1000, \ + .channel_num = I2S_FS_CHANNELS_NUM_MONO, \ + .frame_size = I2S_FRAME_LEN_16, \ + .data_size = I2S_DATA_LEN_16, \ + .fifo_threshold = 8, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH0) +#ifndef DMA0_CH0_CONFIG +#define DMA0_CH0_CONFIG \ + { \ + .id = 0, \ + .ch = 0, \ + .direction = DMA_MEMORY_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_32BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_32BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH1) +#ifndef DMA0_CH1_CONFIG +#define DMA0_CH1_CONFIG \ + { \ + .id = 0, \ + .ch = 1, \ + .direction = DMA_MEMORY_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH2) +#ifndef DMA0_CH2_CONFIG +#define DMA0_CH2_CONFIG \ + { \ + .id = 0, \ + .ch = 2, \ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_UART1_TX, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH3) +#ifndef DMA0_CH3_CONFIG +#define DMA0_CH3_CONFIG \ + { \ + .id = 0, \ + .ch = 3, \ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_SPI0_TX, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH4) +#ifndef DMA0_CH4_CONFIG +#define DMA0_CH4_CONFIG \ + { \ + .id = 0, \ + .ch = 4, \ + .direction = DMA_PERIPH_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_SPI0_RX, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH5) +#ifndef DMA0_CH5_CONFIG +#define DMA0_CH5_CONFIG \ + { \ + .id = 0, \ + .ch = 5, \ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_CYCLE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_I2S_TX, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH6) +#ifndef DMA0_CH6_CONFIG +#define DMA0_CH6_CONFIG \ + { \ + .id = 0, \ + .ch = 6, \ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_CYCLE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_I2S_TX, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_DMA0_CH7) +#ifndef DMA0_CH7_CONFIG +#define DMA0_CH7_CONFIG \ + { \ + .id = 0, \ + .ch = 0, \ + .direction = DMA_MEMORY_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_32BIT, \ + .dst_width = DMA_TRANSFER_WIDTH_32BIT, \ + } +#endif +#endif + +#if defined(BSP_USING_I2C0) +#ifndef I2C0_CONFIG +#define I2C0_CONFIG \ + { \ + .id = 0, \ + .mode = I2C_HW_MODE, \ + .phase = 15, \ + } +#endif +#endif + +#if defined(BSP_USING_TIMER0) +#ifndef TIMER0_CONFIG +#define TIMER0_CONFIG \ + { \ + .id = 0, \ + .cnt_mode = TIMER_CNT_PRELOAD, \ + .trigger = TIMER_PRELOAD_TRIGGER_COMP2, \ + .reload = 0, \ + .timeout1 = 1000000, \ + .timeout2 = 2000000, \ + .timeout3 = 3000000, \ + } +#endif +#endif + +#if defined(BSP_USING_TIMER1) +#ifndef TIMER1_CONFIG +#define TIMER1_CONFIG \ + { \ + .id = 1, \ + .cnt_mode = TIMER_CNT_PRELOAD, \ + .trigger = TIMER_PRELOAD_TRIGGER_COMP0, \ + .reload = 0, \ + .timeout1 = 1000000, \ + .timeout2 = 2000000, \ + .timeout3 = 3000000, \ + } +#endif +#endif + +#if defined(BSP_USING_WDT) +#ifndef WDT_CONFIG +#define WDT_CONFIG \ + { \ + .id = 0, \ + .wdt_timeout = 6000, \ + } +#endif +#endif + +#if defined(BSP_USING_KEYSCAN) +#ifndef KEYSCAN_CONFIG +#define KEYSCAN_CONFIG \ + { \ + .col_num = COL_NUM_4, \ + .row_num = ROW_NUM_4, \ + .deglitch_count = 0, \ + } +#endif +#endif + +#if defined(BSP_USING_QDEC0) +#ifndef QDEC0_CONFIG +#define QDEC0_CONFIG \ + { \ + .id = 0, \ + .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, \ + .sample_mode = QDEC_SAMPLE_SINGLE_MOD, \ + .sample_period = QDEC_SAMPLE_PERIOD_256US, \ + .report_mode = QDEC_REPORT_TIME_MOD, \ + .report_period = 2000, \ + .led_en = ENABLE, \ + .led_swap = DISABLE, \ + .led_period = 7, \ + .deglitch_en = DISABLE, \ + .deglitch_strength = 0x0, \ + } +#endif +#endif + +#if defined(BSP_USING_QDEC1) +#ifndef QDEC1_CONFIG +#define QDEC1_CONFIG \ + { \ + .id = 1, \ + .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, \ + .sample_mode = QDEC_SAMPLE_SINGLE_MOD, \ + .sample_period = QDEC_SAMPLE_PERIOD_256US, \ + .report_mode = QDEC_REPORT_TIME_MOD, \ + .report_period = 2000, \ + .led_en = ENABLE, \ + .led_swap = DISABLE, \ + .led_period = 7, \ + .deglitch_en = DISABLE, \ + .deglitch_strength = 0x0, \ + } +#endif +#endif + +#if defined(BSP_USING_QDEC2) +#ifndef QDEC2_CONFIG +#define QDEC2_CONFIG \ + { \ + .id = 2, \ + .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, \ + .sample_mode = QDEC_SAMPLE_SINGLE_MOD, \ + .sample_period = QDEC_SAMPLE_PERIOD_256US, \ + .report_mode = QDEC_REPORT_TIME_MOD, \ + .report_period = 2000, \ + .led_en = ENABLE, \ + .led_swap = DISABLE, \ + .led_period = 7, \ + .deglitch_en = DISABLE, \ + .deglitch_strength = 0x0, \ + } +#endif +#endif + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/pinmux_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/pinmux_config.h new file mode 100644 index 0000000000000000000000000000000000000000..45e55088364ba6e1dffb5b6a47ab2c90b315651e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/bl706_iot/pinmux_config.h @@ -0,0 +1,156 @@ +/** + * @file pinmux_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _PINMUX_CONFIG_H +#define _PINMUX_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// GPIO0 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio0 function +#define CONFIG_GPIO0_FUNC GPIO_FUN_UNUSED + +// GPIO1 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio1 function +#define CONFIG_GPIO1_FUNC GPIO_FUN_UNUSED + +// GPIO2 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC_LED] +// config gpio2 function +#define CONFIG_GPIO2_FUNC GPIO_FUN_UNUSED + +// GPIO3 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_QDEC] +// config gpio3 function +#define CONFIG_GPIO3_FUNC GPIO_FUN_UNUSED + +// GPIO4 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio4 function +#define CONFIG_GPIO4_FUNC GPIO_FUN_UNUSED + +// GPIO5 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_QDEC_LED] +// config gpio5 function +#define CONFIG_GPIO5_FUNC GPIO_FUN_UNUSED + +// GPIO6 <2> [GPIO_FUN_UNUSED//GPIO_FUN_CLK_OUT//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_QDEC] +// config gpio6 function +#define CONFIG_GPIO6_FUNC GPIO_FUN_UNUSED + +// GPIO7 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_USB//GPIO_FUN_ADC//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio7 function +#define CONFIG_GPIO7_FUNC GPIO_FUN_USB + +// GPIO8 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_USB//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC_LED] +// config gpio8 function +#define CONFIG_GPIO8_FUNC GPIO_FUN_USB + +// GPIO9 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio9 function +#define CONFIG_GPIO9_FUNC GPIO_FUN_UNUSED + +// GPIO10 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio10 function +#define CONFIG_GPIO10_FUNC GPIO_FUN_UNUSED + +// GPIO11 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC_LED] +// config gpio11 function +#define CONFIG_GPIO11_FUNC GPIO_FUN_ADC + +// GPIO12 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio12 function +#define CONFIG_GPIO12_FUNC GPIO_FUN_ADC + +// GPIO13 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio13 function +#define CONFIG_GPIO13_FUNC GPIO_FUN_UNUSED + +// GPIO14 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC_LED] +// config gpio14 function +#define CONFIG_GPIO14_FUNC GPIO_FUN_UART0_TX + +// GPIO15 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio15 function +#define CONFIG_GPIO15_FUNC GPIO_FUN_UART0_RX + +// GPIO16 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio16 function +#define CONFIG_GPIO16_FUNC GPIO_FUN_UNUSED + +// GPIO17 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC_LED] +// config gpio17 function +#define CONFIG_GPIO17_FUNC GPIO_FUN_UNUSED + +// GPIO18 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio18 function +#define CONFIG_GPIO18_FUNC GPIO_FUN_UNUSED + +// GPIO19 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio19 function +#define CONFIG_GPIO19_FUNC GPIO_FUN_UNUSED + +// GPIO20 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC_LED] +// config gpio20 function +#define CONFIG_GPIO20_FUNC GPIO_FUN_UNUSED + +// GPIO21 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ADC//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio21 function +#define CONFIG_GPIO21_FUNC GPIO_FUN_UNUSED + +// GPIO22 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio22 function +#define CONFIG_GPIO22_FUNC GPIO_FUN_UNUSED + +// GPIO23 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC_LED] +// config gpio23 function +#define CONFIG_GPIO23_FUNC GPIO_FUN_UNUSED + +// GPIO24 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio24 function +#define CONFIG_GPIO24_FUNC GPIO_FUN_UNUSED + +// GPIO25 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio25 function +#define CONFIG_GPIO25_FUNC GPIO_FUN_UNUSED + +// GPIO26 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC_LED] +// config gpio26 function +#define CONFIG_GPIO26_FUNC GPIO_FUN_UNUSED + +// GPIO27 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio27 function +#define CONFIG_GPIO27_FUNC GPIO_FUN_UNUSED + +// GPIO28 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio28 function +#define CONFIG_GPIO28_FUNC GPIO_FUN_UNUSED + +// GPIO29 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC_LED] +// config gpio29 function +#define CONFIG_GPIO29_FUNC GPIO_FUN_UNUSED + +// GPIO30 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio30 function +#define CONFIG_GPIO30_FUNC GPIO_FUN_UNUSED + +// GPIO31 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio31 function +#define CONFIG_GPIO31_FUNC GPIO_FUN_UNUSED + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/board.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/board.c new file mode 100644 index 0000000000000000000000000000000000000000..48ca03c57421cb33e1cb15f127a39608a642e88f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/board/bl702/board.c @@ -0,0 +1,331 @@ +/** + * @file board.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "hal_gpio.h" +#include "hal_clock.h" +#include "bl702_glb.h" +#include "bl702_config.h" + +struct pin_mux_cfg { + uint8_t pin; + uint16_t func; +}; + +static const struct pin_mux_cfg af_pin_table[] = { +#ifdef CONFIG_GPIO0_FUNC + { .pin = GPIO_PIN_0, + .func = CONFIG_GPIO0_FUNC }, +#endif +#ifdef CONFIG_GPIO1_FUNC + { .pin = GPIO_PIN_1, + .func = CONFIG_GPIO1_FUNC }, +#endif +#ifdef CONFIG_GPIO2_FUNC + { .pin = GPIO_PIN_2, + .func = CONFIG_GPIO2_FUNC }, +#endif +#ifdef CONFIG_GPIO3_FUNC + { .pin = GPIO_PIN_3, + .func = CONFIG_GPIO3_FUNC }, +#endif +#ifdef CONFIG_GPIO4_FUNC + { .pin = GPIO_PIN_4, + .func = CONFIG_GPIO4_FUNC }, +#endif +#ifdef CONFIG_GPIO5_FUNC + { .pin = GPIO_PIN_5, + .func = CONFIG_GPIO5_FUNC }, +#endif +#ifdef CONFIG_GPIO6_FUNC + { .pin = GPIO_PIN_6, + .func = CONFIG_GPIO6_FUNC }, +#endif +#ifdef CONFIG_GPIO7_FUNC + { .pin = GPIO_PIN_7, + .func = CONFIG_GPIO7_FUNC }, +#endif +#ifdef CONFIG_GPIO8_FUNC + { .pin = GPIO_PIN_8, + .func = CONFIG_GPIO8_FUNC }, +#endif +#ifdef CONFIG_GPIO9_FUNC + { .pin = GPIO_PIN_9, + .func = CONFIG_GPIO9_FUNC }, +#endif +#ifdef CONFIG_GPIO10_FUNC + { .pin = GPIO_PIN_10, + .func = CONFIG_GPIO10_FUNC }, +#endif +#ifdef CONFIG_GPIO11_FUNC + { .pin = GPIO_PIN_11, + .func = CONFIG_GPIO11_FUNC }, +#endif +#ifdef CONFIG_GPIO12_FUNC + { .pin = GPIO_PIN_12, + .func = CONFIG_GPIO12_FUNC }, +#endif +#ifdef CONFIG_GPIO13_FUNC + { .pin = GPIO_PIN_13, + .func = CONFIG_GPIO13_FUNC }, +#endif +#ifdef CONFIG_GPIO14_FUNC + { .pin = GPIO_PIN_14, + .func = CONFIG_GPIO14_FUNC }, +#endif +#ifdef CONFIG_GPIO15_FUNC + { .pin = GPIO_PIN_15, + .func = CONFIG_GPIO15_FUNC }, +#endif +#ifdef CONFIG_GPIO16_FUNC + { .pin = GPIO_PIN_16, + .func = CONFIG_GPIO16_FUNC }, +#endif +#ifdef CONFIG_GPIO17_FUNC + { .pin = GPIO_PIN_17, + .func = CONFIG_GPIO17_FUNC }, +#endif +#ifdef CONFIG_GPIO18_FUNC + { .pin = GPIO_PIN_18, + .func = CONFIG_GPIO18_FUNC }, +#endif +#ifdef CONFIG_GPIO19_FUNC + { .pin = GPIO_PIN_19, + .func = CONFIG_GPIO19_FUNC }, +#endif +#ifdef CONFIG_GPIO20_FUNC + { .pin = GPIO_PIN_20, + .func = CONFIG_GPIO20_FUNC }, +#endif +#ifdef CONFIG_GPIO21_FUNC + { .pin = GPIO_PIN_21, + .func = CONFIG_GPIO21_FUNC }, +#endif +#ifdef CONFIG_GPIO22_FUNC + { .pin = GPIO_PIN_22, + .func = CONFIG_GPIO22_FUNC }, +#endif +#ifdef CONFIG_GPIO23_FUNC + { .pin = GPIO_PIN_23, + .func = CONFIG_GPIO23_FUNC }, +#endif +#ifdef CONFIG_GPIO24_FUNC + { .pin = GPIO_PIN_24, + .func = CONFIG_GPIO24_FUNC }, +#endif +#ifdef CONFIG_GPIO25_FUNC + { .pin = GPIO_PIN_25, + .func = CONFIG_GPIO25_FUNC }, +#endif +#ifdef CONFIG_GPIO26_FUNC + { .pin = GPIO_PIN_26, + .func = CONFIG_GPIO26_FUNC }, +#endif +#ifdef CONFIG_GPIO27_FUNC + { .pin = GPIO_PIN_27, + .func = CONFIG_GPIO27_FUNC }, +#endif +#ifdef CONFIG_GPIO28_FUNC + { .pin = GPIO_PIN_28, + .func = CONFIG_GPIO28_FUNC }, +#endif +#ifdef CONFIG_GPIO29_FUNC + { .pin = GPIO_PIN_29, + .func = CONFIG_GPIO29_FUNC }, +#endif +#ifdef CONFIG_GPIO30_FUNC + { .pin = GPIO_PIN_30, + .func = CONFIG_GPIO30_FUNC }, +#endif +#ifdef CONFIG_GPIO31_FUNC + { .pin = GPIO_PIN_31, + .func = CONFIG_GPIO31_FUNC }, +#endif +}; + +static void board_pin_mux_init(void) +{ + GLB_GPIO_Cfg_Type gpio_cfg; + uint32_t tmpVal; + gpio_cfg.drive = 0; + gpio_cfg.smtCtrl = 1; + uint8_t hbn_gpio_mask = 0x1f; + uint8_t hbn_aon_ie = 0; + + for (int i = 0; i < sizeof(af_pin_table) / sizeof(af_pin_table[0]); i++) { + gpio_cfg.gpioMode = GPIO_MODE_AF; + gpio_cfg.pullType = GPIO_PULL_UP; + gpio_cfg.gpioPin = af_pin_table[i].pin; + gpio_cfg.gpioFun = af_pin_table[i].func; + + /*if using gpio9-gpio12 input mode or wakeup,should set reg_aon_pad_ie_smt corresponding bit = 1*/ + if ((af_pin_table[i].pin > GPIO_PIN_8) && (af_pin_table[i].pin < GPIO_PIN_13) && (af_pin_table[i].func >= GPIO_FUN_GPIO_INPUT_UP) && (af_pin_table[i].func <= GPIO_FUN_WAKEUP)) { + hbn_aon_ie |= (1 << (af_pin_table[i].pin - 9)); + } + + /*if reset state*/ + if (af_pin_table[i].func == GPIO_FUN_UNUSED) { + continue; + } else if (af_pin_table[i].func == GPIO_FUN_WAKEUP) { + /*if hbn or pds gpio wakeup func*/ + if (af_pin_table[i].pin < GPIO_PIN_8) { + /*enable pds gpio wakeup and irq unmask*/ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, af_pin_table[i].pin); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK); + BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); + } else if ((af_pin_table[i].pin > GPIO_PIN_8) && (af_pin_table[i].pin < GPIO_PIN_13)) { + hbn_gpio_mask &= ~(1 << (af_pin_table[i].pin - 9)); + } + continue; + } else if (af_pin_table[i].func == GPIO_FUN_PWM) { + /*if pwm func*/ + gpio_cfg.pullType = GPIO_PULL_DOWN; + } else if (af_pin_table[i].func == GPIO_FUN_QDEC) { + /* if qdec a/b */ + gpio_cfg.pullType = GPIO_PULL_NONE; + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.gpioFun = GPIO_FUN_QDEC; + } else if (af_pin_table[i].func == GPIO_FUN_QDEC_LED) { + /* if qdec led */ + gpio_cfg.pullType = GPIO_PULL_NONE; + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.gpioFun = GPIO_FUN_QDEC; + } else if ((af_pin_table[i].func == GPIO_FUN_USB) || (af_pin_table[i].func == GPIO_FUN_DAC) || (af_pin_table[i].func == GPIO_FUN_ADC)) { + /*if analog func , for usb、adc、dac*/ + gpio_cfg.gpioFun = GPIO_FUN_ANALOG; + gpio_cfg.gpioMode = GPIO_MODE_ANALOG; + gpio_cfg.pullType = GPIO_PULL_NONE; + } else if ((af_pin_table[i].func & 0x70) == 0x70) { + /*if uart func*/ + gpio_cfg.gpioFun = GPIO_FUN_UART; + uint8_t sig = af_pin_table[i].func & 0x07; + /*link to one uart sig*/ + GLB_UART_Fun_Sel((gpio_cfg.gpioPin % 8), sig); + } else if (af_pin_table[i].func == GPIO_FUN_CLK_OUT) { + if (af_pin_table[i].pin % 2) { + /*odd gpio output clock*/ + GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK); + } else { + /*even gpio output clock*/ + GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK); + } + } else if ((af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_UP) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_FALLING_EDGE) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_LOW_LEVEL)) { + /*if common gpio func,include input、output and exti*/ + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_UP; + + if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_FALLING_EDGE) { + GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE); + } else if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_LOW_LEVEL) { + GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL); + } + } else if ((af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_DOWN) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_RISING_EDGE) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_HIGH_LEVEL)) { + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_DOWN; + + if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_RISING_EDGE) { + GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE); + } else if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_HIGH_LEVEL) { + GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL); + } + } else if (af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_NONE) { + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_NONE; + } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_UP) { + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_UP; + } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_DOWN) { + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_DOWN; + } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_NONE) { + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_NONE; + } + GLB_GPIO_Init(&gpio_cfg); + } + /*disable unused reg_aon_pad_ie_smt bits and hbn_pin_wakeup_mask bits*/ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, hbn_gpio_mask); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, hbn_aon_ie); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); +} + +static void board_clock_init(void) +{ + system_clock_init(); + peripheral_clock_init(); +} + +void bl_show_info(void) +{ + MSG("\r\n"); + MSG(" ____ __ __ _ _ _ \r\n"); + MSG(" | _ \\ / _|/ _| | | | | | | \r\n"); + MSG(" | |_) | ___ _ _| |_| |_ __ _| | ___ | | __ _| |__ \r\n"); + MSG(" | _ < / _ \\| | | | _| _/ _` | |/ _ \\| |/ _` | '_ \\ \r\n"); + MSG(" | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |\r\n"); + MSG(" |____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/|_|\\__,_|_.__/ \r\n"); + MSG("\r\n"); + MSG("Build:%s,%s\r\n", __TIME__, __DATE__); + MSG("Copyright (c) 2021 Bouffalolab team\r\n"); + +#if 0 + MSG("root clock:%dM\r\n", system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / 1000000); /*root clock before f_div*/ + MSG("fclk clock:%dM\r\n", system_clock_get(SYSTEM_CLOCK_FCLK) / 1000000); /*after f_div,this is system core clock*/ + MSG("bclk clock:%dM\r\n", system_clock_get(SYSTEM_CLOCK_BCLK) / 1000000); + + MSG("uart clock:%dM\r\n", peripheral_clock_get(PERIPHERAL_CLOCK_UART) / 1000000); + MSG("spi clock:%dM\r\n", peripheral_clock_get(PERIPHERAL_CLOCK_SPI) / 1000000); + MSG("i2c clock:%dM\r\n", peripheral_clock_get(PERIPHERAL_CLOCK_I2C) / 1000000); +#endif +} + +void board_init(void) +{ + HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P10V); + + board_clock_init(); + board_pin_mux_init(); +} + +int bflb_get_board_config(uint8_t func, uint8_t *pinlist) +{ + uint16_t i = 0; + int len = 0; + + for (i = 0; i < sizeof(af_pin_table) / sizeof(struct pin_mux_cfg); i++) { + if (af_pin_table[i].func == func) { + pinlist[len] = af_pin_table[i].pin; + len++; + } + } + return len; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.c new file mode 100644 index 0000000000000000000000000000000000000000..691fde23de1e54106d93c04c26d09f39a060c6c2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.c @@ -0,0 +1,279 @@ +/** + * @file bflb_platform.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "hal_uart.h" +#include "hal_mtimer.h" +#include "drv_mmheap.h" +#include "ring_buffer.h" + +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +static uint8_t uart_dbg_disable = 0; + +__WEAK__ void board_init(void) +{ +} +__WEAK__ void bl_show_info(void) +{ +} + +__WEAK__ int bflb_get_board_config(uint8_t func, uint8_t *pinlist) +{ + return 0; +} + +__WEAK__ enum uart_index_type board_get_debug_uart_index(void) +{ + return 0; +} + +void bflb_platform_init(uint32_t baudrate) +{ + __disable_irq(); + + board_init(); + + uint8_t ret = 0; + + if (mmheap_init_with_pool(&__HeapBase, (size_t)&__HeapLimit - (size_t)&__HeapBase)) { + ret = 1; + } + + if (!uart_dbg_disable) { + uart_register(board_get_debug_uart_index(), "debug_log"); + struct device *uart = device_find("debug_log"); + + if (uart) { + device_open(uart, DEVICE_OFLAG_STREAM_TX | DEVICE_OFLAG_INT_RX); + device_set_callback(uart, NULL); + device_control(uart, DEVICE_CTRL_CLR_INT, (void *)(UART_RX_FIFO_IT)); + } + + bl_show_info(); + } + + if (!ret) + MSG("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1000); + else + MSG("dynamic memory init error\r\n"); + + __enable_irq(); +} + +#if ((defined BOOTROM) || (defined BFLB_EFLASH_LOADER)) +static uint8_t eflash_loader_logbuf[2048] __attribute__((section(".system_ram_noinit"))); +static uint32_t log_len = 0; +uint32_t bflb_platform_get_log(uint8_t *data, uint32_t maxlen) +{ + uint32_t len = log_len; + if (len > maxlen) { + len = maxlen; + } + memcpy(data, eflash_loader_logbuf, len); + return len; +} +#endif + +void bflb_platform_printf(char *fmt, ...) +{ + struct device *uart = device_find("debug_log"); + char print_buf[128]; + va_list ap; + + if (!uart_dbg_disable) { + va_start(ap, fmt); + vsnprintf(print_buf, sizeof(print_buf) - 1, fmt, ap); + va_end(ap); +#if ((defined BOOTROM) || (defined BFLB_EFLASH_LOADER)) + uint32_t len = strlen(print_buf); + if (log_len + len < sizeof(eflash_loader_logbuf)) { + memcpy(eflash_loader_logbuf + log_len, print_buf, len); + log_len += len; + } +#endif + device_write(uart, 0, (uint8_t *)print_buf, strlen(print_buf)); + } +} + +void bflb_platform_print_set(uint8_t disable) +{ + uart_dbg_disable = disable; +} + +uint8_t bflb_platform_print_get(void) +{ + return uart_dbg_disable; +} + +void bflb_platform_deinit(void) +{ + struct device *uart = device_find("debug_log"); + + if (uart) { + device_close(uart); + } +} + +void bflb_platform_dump(uint8_t *data, uint32_t len) +{ + uint32_t i = 0; + + if (!uart_dbg_disable) { + for (i = 0; i < len; i++) { + if (i % 16 == 0) { + bflb_platform_printf("\r\n"); + } + + bflb_platform_printf("%02x ", data[i]); + } + + bflb_platform_printf("\r\n"); + } +} + +void bflb_platform_reg_dump(uint32_t addr) +{ + bflb_platform_printf("%0x08x[31:0]=%0x08x\r\n", addr, *(volatile uint32_t *)(addr)); +} + +void bflb_platform_init_time() +{ +} + +void bflb_platform_deinit_time() +{ +} + +void bflb_platform_set_alarm_time(uint64_t time, void (*interruptFun)(void)) +{ + mtimer_set_alarm_time(time, interruptFun); +} + +void bflb_platform_clear_time() +{ +} + +void bflb_platform_start_time() +{ +} + +void bflb_platform_stop_time() +{ +} + +uint64_t bflb_platform_get_time_ms() +{ + return mtimer_get_time_ms(); +} + +uint64_t bflb_platform_get_time_us() +{ + return mtimer_get_time_us(); +} + +void bflb_platform_delay_ms(uint32_t ms) +{ + mtimer_delay_ms(ms); +} +void bflb_platform_delay_us(uint32_t us) +{ + mtimer_delay_us(us); +} + +void bflb_print_device_list(void) +{ + struct device *dev; + dlist_t *node; + uint8_t device_index = 0; + + MSG("Device List Print\r\n"); + + dlist_for_each(node, device_get_list_header()) + { + dev = dlist_entry(node, struct device, list); + + MSG("Index %d\r\nDevice Name = %s \r\n", device_index, dev->name); + + switch (dev->type) { + case DEVICE_CLASS_GPIO: + MSG("Device Type = %s \r\n", "GPIO"); + break; + + case DEVICE_CLASS_UART: + MSG("Device Type = %s \r\n", "UART"); + break; + + case DEVICE_CLASS_SPI: + MSG("Device Type = %s \r\n", "SPI"); + break; + + case DEVICE_CLASS_I2C: + MSG("Device Type = %s \r\n", "I2C"); + break; + + case DEVICE_CLASS_ADC: + MSG("Device Type = %s \r\n", "ADC"); + break; + + case DEVICE_CLASS_DMA: + MSG("Device Type = %s \r\n", "DMA"); + break; + + case DEVICE_CLASS_TIMER: + MSG("Device Type = %s \r\n", "TIMER"); + break; + + case DEVICE_CLASS_PWM: + MSG("Device Type = %s \r\n", "PWM"); + break; + + case DEVICE_CLASS_SDIO: + MSG("Device Type = %s \r\n", "SDIO"); + break; + + case DEVICE_CLASS_USB: + MSG("Device Type = %s \r\n", "USB"); + break; + + case DEVICE_CLASS_I2S: + MSG("Device Type = %s \r\n", "I2S"); + break; + + case DEVICE_CLASS_CAMERA: + MSG("Device Type = %s \r\n", "CAMERA"); + break; + + case DEVICE_CLASS_NONE: + break; + + default: + break; + } + + MSG("Device Handle = 0x%x \r\n", dev); + MSG("---------------------\r\n", dev); + + device_index++; + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.h new file mode 100644 index 0000000000000000000000000000000000000000..2bab04c10b706edeb18ba12ba7caf09bb9389e3e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.h @@ -0,0 +1,109 @@ +/** + * @file bflb_platform.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _BFLB_PLATFORM_H +#define _BFLB_PLATFORM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "misc.h" +//#include "mcu_sdk_version.h" + +#define MSG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define MSG_DBG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define MSG_ERR(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define BL_CASE_FAIL \ + { MSG("case fail\r\n"); } +#define BL_CASE_SUCCESS \ + { MSG("case success\r\n"); } + +/* compatible with old version */ +#ifndef DBG_TAG +#define DBG_TAG "DEBUG" +#endif + +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ +#define _DBG_COLOR(n) bflb_platform_printf("\033[" #n "m") +#define _DBG_LOG_HDR(lvl_name, color_n) \ + bflb_platform_printf("\033[" #color_n "m[" lvl_name "/" DBG_TAG "] ") +#define _DBG_LOG_X_END bflb_platform_printf("\033[0m\n") + +#define dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + _DBG_LOG_HDR(lvl, color_n); \ + bflb_platform_printf(fmt, ##__VA_ARGS__); \ + _DBG_LOG_X_END; \ + } while (0) + +#define LOG_D(fmt, ...) dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#define LOG_I(fmt, ...) dbg_log_line("I", 35, fmt, ##__VA_ARGS__) +#define LOG_W(fmt, ...) dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#define LOG_E(fmt, ...) dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#define LOG_RAW(...) bflb_platform_printf(__VA_ARGS__) + +#ifdef DEBUG +void check_failed(uint8_t *file, uint32_t line); +#define CHECK_PARAM(expr) \ + ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define CHECK_PARAM(expr) ((void)0) +#endif /* DEBUG */ + +void bflb_platform_init(uint32_t baudrate); +void bflb_platform_printf(char *fmt, ...); +void bflb_platform_print_set(uint8_t disable); +uint8_t bflb_platform_print_get(void); +void bflb_platform_dump(uint8_t *data, uint32_t len); +void bflb_platform_reg_dump(uint32_t addr); +uint32_t bflb_platform_get_log(uint8_t *data, uint32_t maxlen); +void bflb_platform_deinit(void); + +void bflb_platform_init_time(void); +void bflb_platform_clear_time(void); +uint64_t bflb_platform_get_time_ms(void); +uint64_t bflb_platform_get_time_us(void); +void bflb_platform_start_time(void); +void bflb_platform_stop_time(void); +void bflb_platform_set_alarm_time(uint64_t time, void (*interruptFun)(void)); +void bflb_platform_deinit_time(void); +void bflb_platform_delay_ms(uint32_t ms); +void bflb_platform_delay_us(uint32_t us); + +void bflb_print_device_list(void); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/cpp_new.cpp b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/cpp_new.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ab9d40159583996ce6a66087165268019d499dd --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/cpp_new.cpp @@ -0,0 +1,11 @@ +#include +#include + + +void *operator new(size_t size) { return malloc(size); } + +void *operator new[](size_t size) { return malloc(size); } + +void operator delete(void *ptr) { free(ptr); } + +void operator delete[](void *ptr) { free(ptr); } diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/syscalls.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/syscalls.c new file mode 100644 index 0000000000000000000000000000000000000000..fbaf771889b3c69e9f574ffd5f39b1a53a689f69 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/platform/syscalls.c @@ -0,0 +1,290 @@ +#include +#include +#include +#include "drv_mmheap.h" +#include "drv_device.h" + +#ifdef CONF_VFS_ENABLE +#include +#endif + +/* Reentrant versions of system calls. */ + +/* global errno in RT-Thread */ +static volatile int _sys_errno = 0; + +#ifndef _REENT_ONLY +int *__errno() +{ + // #if (configUSE_POSIX_ERRNO == 1) + // { + // extern int FreeRTOS_errno; + + // return &FreeRTOS_errno; + // } + // #endif + return (int *)&_sys_errno; +} +#endif + +int _getpid_r(struct _reent *ptr) +{ + return 0; +} + +int _execve_r(struct _reent *ptr, const char *name, char *const *argv, char *const *env) +{ + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _fcntl_r(struct _reent *ptr, int fd, int cmd, int arg) +{ + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _fork_r(struct _reent *ptr) +{ + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _fstat_r(struct _reent *ptr, int fd, struct stat *pstat) +{ + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _isatty_r(struct _reent *ptr, int fd) +{ + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _kill_r(struct _reent *ptr, int pid, int sig) +{ + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _link_r(struct _reent *ptr, const char *old, const char *new) +{ + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +_off_t _lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) +{ +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + _off_t rc; + + rc = aos_lseek(fd, pos, whence); + return rc; +#endif +} + +int _mkdir_r(struct _reent *ptr, const char *name, int mode) +{ +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + int rc; + + rc = aos_mkdir(name); + return rc; +#endif +} + +int _open_r(struct _reent *ptr, const char *file, int flags, int mode) +{ +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + int rc; + + rc = aos_open(file, flags); + return rc; +#endif +} + +int _close_r(struct _reent *ptr, int fd) +{ +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + return aos_close(fd); +#endif +} + +_ssize_t _read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) +{ +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + _ssize_t rc; + + rc = aos_read(fd, buf, nbytes); + return rc; +#endif +} + +int _rename_r(struct _reent *ptr, const char *old, const char *new) +{ +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + int rc; + + rc = aos_rename(old, new); + return rc; +#endif +} + +int _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) +{ +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + int rc; + + rc = aos_stat(file, pstat); + return rc; +#endif +} + +int _unlink_r(struct _reent *ptr, const char *file) +{ +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + return aos_unlink(file); +#endif +} + +int _wait_r(struct _reent *ptr, int *status) +{ + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +_ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) +{ +#ifndef CONF_VFS_ENABLE + struct device *uart = device_find("debug_log"); + if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd)) { + device_write(uart, 0, (uint8_t *)buf, nbytes); + } + return 0; +#else + _ssize_t rc; + + rc = aos_write(fd, buf, nbytes); + return rc; +#endif +} + +void *_malloc_r(struct _reent *ptr, size_t size) +{ + void *result; + + result = (void *)mmheap_alloc(size); + if (result == NULL) { + ptr->_errno = -ENOMEM; + } + + return result; +} + +void *_realloc_r(struct _reent *ptr, void *old, size_t newlen) +{ + void *result; + + result = (void *)mmheap_realloc(old, newlen); + if (result == NULL) { + ptr->_errno = -ENOMEM; + } + + return result; +} + +void *_calloc_r(struct _reent *ptr, size_t size, size_t len) +{ + void *result; + + result = (void *)mmheap_calloc(size, len); + if (result == NULL) { + ptr->_errno = -ENOMEM; + } + + return result; +} + +void _free_r(struct _reent *ptr, void *addr) +{ + mmheap_free(addr); +} + +void *_sbrk_r(struct _reent *ptr, ptrdiff_t incr) +{ + return 0; +} + +/* for exit() and abort() */ +void __attribute__((noreturn)) +_exit(int status) +{ + while (1) { + } +} + +void _system(const char *s) +{ +} + +void __libc_init_array(void) +{ + /* we not use __libc init_aray to initialize C++ objects */ +} + +mode_t umask(mode_t mask) +{ + return 022; +} + +int flock(int fd, int operation) +{ + return 0; +} + +/* +These functions are implemented and replaced by the 'common/time.c' file +int _gettimeofday_r(struct _reent *ptr, struct timeval *__tp, void *__tzp); +_CLOCK_T_ _times_r(struct _reent *ptr, struct tms *ptms); +*/ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/psram/bsp_sf_psram.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/psram/bsp_sf_psram.c new file mode 100644 index 0000000000000000000000000000000000000000..7eaf5087288d6df254743be8df82d73b84997fa1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/psram/bsp_sf_psram.c @@ -0,0 +1,144 @@ +/** + * @file bsp_sf_psram.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "bsp_sf_psram.h" +#include "bflb_platform.h" +#include "bl702_psram.h" +#include "bl702_l1c.h" +#include "bl702_sec_eng.h" +#include "bl702_glb.h" + +/* bsp sf psram private variables */ + +SPI_Psram_Cfg_Type apMemory1604 = { + .readIdCmd = 0x9F, + .readIdDmyClk = 0, + .burstToggleCmd = 0xC0, + .resetEnableCmd = 0x66, + .resetCmd = 0x99, + .enterQuadModeCmd = 0x35, + .exitQuadModeCmd = 0xF5, + .readRegCmd = 0xB5, + .readRegDmyClk = 1, + .writeRegCmd = 0xB1, + .readCmd = 0x03, + .readDmyClk = 0, + .fReadCmd = 0x0B, + .fReadDmyClk = 1, + .fReadQuadCmd = 0xEB, + .fReadQuadDmyClk = 3, + .writeCmd = 0x02, + .quadWriteCmd = 0x38, + .pageSize = 512, + .ctrlMode = PSRAM_SPI_CTRL_MODE, + .driveStrength = PSRAM_DRIVE_STRENGTH_50_OHMS, + .burstLength = PSRAM_BURST_LENGTH_512_BYTES, +}; + +SF_Ctrl_Cmds_Cfg cmdsCfg = { + .cmdsEn = ENABLE, + .burstToggleEn = ENABLE, + .wrapModeEn = DISABLE, + .wrapLen = SF_CTRL_WRAP_LEN_512, +}; +SF_Ctrl_Psram_Cfg sfCtrlPsramCfg = { + .owner = SF_CTRL_OWNER_SAHB, + .padSel = SF_CTRL_PAD_SEL_DUAL_CS_SF2, + .bankSel = SF_CTRL_SEL_PSRAM, + .psramRxClkInvertSrc = ENABLE, + .psramRxClkInvertSel = DISABLE, + .psramDelaySrc = ENABLE, + .psramClkDelay = 1, +}; + +/* bsp sf psram gpio init */ +/** + * @brief + * + * @return None + * + */ +void ATTR_TCM_SECTION bsp_sf_psram_gpio_init(void) +{ + GLB_GPIO_Cfg_Type cfg; + uint8_t gpiopins[7]; + uint8_t i = 0; + + cfg.gpioMode = GPIO_MODE_AF; + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 3; + cfg.smtCtrl = 1; + cfg.gpioFun = GPIO_FUN_FLASH_PSRAM; + + gpiopins[0] = BFLB_EXTPSRAM_CLK_GPIO; + gpiopins[1] = BFLB_EXTPSRAM_CS_GPIO; + gpiopins[2] = BFLB_EXTPSRAM_DATA0_GPIO; + gpiopins[3] = BFLB_EXTPSRAM_DATA1_GPIO; + gpiopins[4] = BFLB_EXTPSRAM_DATA2_GPIO; + gpiopins[5] = BFLB_EXTPSRAM_DATA3_GPIO; + gpiopins[6] = BFLB_EXTFLASH_CS_GPIO; + + for (i = 0; i < sizeof(gpiopins); i++) { + cfg.gpioPin = gpiopins[i]; + + if (i == 0 || i == 1 || i == 6) { + /*flash clk and cs is output*/ + cfg.gpioMode = GPIO_MODE_OUTPUT; + } else { + /*data are bidir*/ + cfg.gpioMode = GPIO_MODE_AF; + } + + GLB_GPIO_Init(&cfg); + } +} + +/* bsp sf psram init */ +/** + * @brief + * + * @param sw_reset + * + * @return None + * + */ +void ATTR_TCM_SECTION bsp_sf_psram_init(uint8_t sw_reset) +{ + uint8_t psramId[8] = { 0 }; + bsp_sf_psram_gpio_init(); + + Psram_Init(&apMemory1604, &cmdsCfg, &sfCtrlPsramCfg); + + if (sw_reset) { + Psram_SoftwareReset(&apMemory1604, apMemory1604.ctrlMode); + } + + Psram_ReadId(&apMemory1604, psramId); + Psram_Cache_Write_Set(&apMemory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE); + L1C_Cache_Enable_Set(L1C_WAY_DISABLE_NONE); +} + +void ATTR_TCM_SECTION bsp_sf_psram_read_id(uint8_t *data) +{ + Psram_ReadId(&apMemory1604, data); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/psram/bsp_sf_psram.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/psram/bsp_sf_psram.h new file mode 100644 index 0000000000000000000000000000000000000000..9047f712c9d825cd77ef13bf6a5d52e86fc079f9 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/psram/bsp_sf_psram.h @@ -0,0 +1,45 @@ +/** + * @file bsp_sf_psram.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __BSP_SF_PSRAM_H__ +#define __BSP_SF_PSRAM_H__ + +#include "bl702.h" + +#define BSP_PSRAM_BASE BL702_PSRAM_XIP_BASE + +#define PSRAM_SIZE (2 * 1024 * 1024) + +#define BFLB_EXTFLASH_CS_GPIO GLB_GPIO_PIN_25 +#define BFLB_EXTPSRAM_CLK_GPIO GLB_GPIO_PIN_27 +#define BFLB_EXTPSRAM_CS_GPIO GLB_GPIO_PIN_17 +#define BFLB_EXTPSRAM_DATA0_GPIO GLB_GPIO_PIN_28 +#define BFLB_EXTPSRAM_DATA1_GPIO GLB_GPIO_PIN_24 +#define BFLB_EXTPSRAM_DATA2_GPIO GLB_GPIO_PIN_23 +#define BFLB_EXTPSRAM_DATA3_GPIO GLB_GPIO_PIN_26 + +void bsp_sf_psram_gpio_init(void); +void bsp_sf_psram_init(uint8_t sw_reset); +void bsp_sf_psram_read_id(uint8_t *data); + +#endif /* __BSP_SF_PSRAM_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.c new file mode 100644 index 0000000000000000000000000000000000000000..cc03a10a97575514737399d956144e2b238b40ab --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.c @@ -0,0 +1,161 @@ +/** + * @file uart_interface.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "uart_interface.h" +#include "hal_dma.h" +#include "hal_gpio.h" +#include "hal_usb.h" + + +#define USB_OUT_RINGBUFFER_SIZE (8 * 1024) +#define UART_RX_RINGBUFFER_SIZE (8 * 1024) +#define UART_TX_DMA_SIZE (4095) + +uint8_t usb_rx_mem[USB_OUT_RINGBUFFER_SIZE] + __attribute__((section(".system_ram"))); +uint8_t uart_rx_mem[UART_RX_RINGBUFFER_SIZE] + __attribute__((section(".system_ram"))); + +uint8_t src_buffer[UART_TX_DMA_SIZE] __attribute__((section(".tcm_code"))); + +struct device *uart1; +struct device *dma_ch2; + +Ring_Buffer_Type usb_rx_rb; +Ring_Buffer_Type uart1_rx_rb; + +void uart_irq_callback(struct device *dev, void *args, uint32_t size, + uint32_t state) { + if (state == UART_EVENT_RX_FIFO) { + if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) { + Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size); + } else { + MSG("RF OV\r\n"); + } + } else if (state == UART_EVENT_RTO) { + if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) { + Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size); + } else { + MSG("RTO OV\r\n"); + } + } else if (state == UART_RX_FER_IT) { + MSG("RX ERR\r\n"); + } +} +void uart1_init(void) { + uart_register(UART1_INDEX, "uart1"); + uart1 = device_find("uart1"); + + if (uart1) { + // device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX); + // device_set_callback(uart1, uart_irq_callback); + // device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | + // UART_RTO_IT)); + } + + dma_register(DMA0_CH2_INDEX, "ch2"); + dma_ch2 = device_find("ch2"); + + if (dma_ch2) { + device_open(dma_ch2, 0); + } +} + +void uart1_config(uint32_t baudrate, uart_databits_t databits, + uart_parity_t parity, uart_stopbits_t stopbits) { + device_close(uart1); + UART_DEV(uart1)->baudrate = baudrate; + UART_DEV(uart1)->stopbits = stopbits; + UART_DEV(uart1)->parity = parity; + UART_DEV(uart1)->databits = (databits - 5); + device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX); + device_set_callback(uart1, uart_irq_callback); + device_control(uart1, DEVICE_CTRL_SET_INT, + (void *)(UART_RX_FIFO_IT | UART_RTO_IT)); + Ring_Buffer_Reset(&usb_rx_rb); + Ring_Buffer_Reset(&uart1_rx_rb); +} + +static uint8_t uart1_dtr; +static uint8_t uart1_rts; + +void uart1_set_dtr_rts(uint8_t dtr, uint8_t rts) { + uart1_dtr = dtr; + uart1_rts = rts; +} + +void uart1_dtr_init(void) { gpio_set_mode(uart1_dtr, GPIO_OUTPUT_MODE); } +void uart1_rts_init(void) { gpio_set_mode(uart1_rts, GPIO_OUTPUT_MODE); } +void uart1_dtr_deinit(void) { gpio_set_mode(uart1_dtr, GPIO_INPUT_MODE); } +void uart1_rts_deinit(void) { gpio_set_mode(uart1_rts, GPIO_INPUT_MODE); } +void dtr_pin_set(uint8_t status) { gpio_write(uart1_dtr, status); } +void rts_pin_set(uint8_t status) { gpio_write(uart1_rts, status); } +void ringbuffer_lock() { __disable_irq(); } +void ringbuffer_unlock() { __enable_irq(); } + +void uart_ringbuffer_init(void) { + /* init mem for ring_buffer */ + memset(usb_rx_mem, 0, USB_OUT_RINGBUFFER_SIZE); + memset(uart_rx_mem, 0, UART_RX_RINGBUFFER_SIZE); + + /* init ring_buffer */ + Ring_Buffer_Init(&usb_rx_rb, usb_rx_mem, USB_OUT_RINGBUFFER_SIZE, + ringbuffer_lock, ringbuffer_unlock); + Ring_Buffer_Init(&uart1_rx_rb, uart_rx_mem, UART_RX_RINGBUFFER_SIZE, + ringbuffer_lock, ringbuffer_unlock); +} + +static dma_control_data_t uart_dma_ctrl_cfg = { + .bits.fix_cnt = 0, + .bits.dst_min_mode = 0, + .bits.dst_add_mode = 0, + .bits.SI = 1, + .bits.DI = 0, + .bits.SWidth = DMA_TRANSFER_WIDTH_8BIT, + .bits.DWidth = DMA_TRANSFER_WIDTH_8BIT, + .bits.SBSize = 0, + .bits.DBSize = 0, + .bits.I = 0, + .bits.TransferSize = 4095}; +static dma_lli_ctrl_t uart_lli_list = {.src_addr = (uint32_t)src_buffer, + .dst_addr = DMA_ADDR_UART1_TDR, + .nextlli = 0}; + +void uart_send_from_ringbuffer(void) { + if (Ring_Buffer_Get_Length(&usb_rx_rb)) { + if (!device_control(dma_ch2, DMA_CHANNEL_GET_STATUS, NULL)) { + uint32_t avalibleCnt = + Ring_Buffer_Read(&usb_rx_rb, src_buffer, UART_TX_DMA_SIZE); + + if (avalibleCnt) { + dma_channel_stop(dma_ch2); + uart_dma_ctrl_cfg.bits.TransferSize = avalibleCnt; + memcpy(&uart_lli_list.cfg, &uart_dma_ctrl_cfg, + sizeof(dma_control_data_t)); + device_control(dma_ch2, DMA_CHANNEL_UPDATE, + (void *)((uint32_t)&uart_lli_list)); + dma_channel_start(dma_ch2); + } + } + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.h new file mode 100644 index 0000000000000000000000000000000000000000..730509e79a9c474f0183974b46780b20b57a7730 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.h @@ -0,0 +1,45 @@ +/** + * @file uart_interface.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __UART_IF_H__ +#define __UART_IF_H__ + +#include "hal_uart.h" +#include "ring_buffer.h" + +extern Ring_Buffer_Type usb_rx_rb; +extern Ring_Buffer_Type uart1_rx_rb; + +void uart1_init(void); +void uart1_config(uint32_t baudrate, uart_databits_t databits, + uart_parity_t parity, uart_stopbits_t stopbits); +void uart1_set_dtr_rts(uint8_t dtr, uint8_t rts); +void uart1_dtr_init(void); +void uart1_rts_init(void); +void uart1_dtr_deinit(void); +void uart1_rts_deinit(void); +void dtr_pin_set(uint8_t status); +void rts_pin_set(uint8_t status); +void uart_ringbuffer_init(void); +void uart_send_from_ringbuffer(void); +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/usb_dc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/usb_dc.c new file mode 100644 index 0000000000000000000000000000000000000000..a4f02b5183ebe2906afc7739b5c583d8ee41e01c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/bsp/bsp_common/usb/usb_dc.c @@ -0,0 +1,112 @@ +/** + * @file usb_dc.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "hal_usb.h" +#include "stdbool.h" +#include "usbd_core.h" + +struct device *usb; + +static void usb_dc_event_callback(struct device *dev, void *args, uint32_t size, uint32_t state) +{ + switch (state) { + case USB_DC_EVENT_ERROR: + usbd_event_notify_handler(USB_EVENT_ERROR, NULL); + break; + + case USB_DC_EVENT_RESET: + usbd_event_notify_handler(USB_EVENT_RESET, NULL); + break; + + case USB_DC_EVENT_SOF: + usbd_event_notify_handler(USB_EVENT_SOF, NULL); + break; + + case USB_DC_EVENT_SETUP_NOTIFY: + usbd_event_notify_handler(USB_EVENT_SETUP_NOTIFY, NULL); + break; + + case USB_DC_EVENT_EP0_IN_NOTIFY: + usbd_event_notify_handler(USB_EVENT_EP0_IN_NOTIFY, NULL); + break; + + case USB_DC_EVENT_EP0_OUT_NOTIFY: + usbd_event_notify_handler(USB_EVENT_EP0_OUT_NOTIFY, NULL); + break; + + case USB_DC_EVENT_EP_IN_NOTIFY: + usbd_event_notify_handler(USB_EVENT_EP_IN_NOTIFY, args); + break; + + case USB_DC_EVENT_EP_OUT_NOTIFY: + usbd_event_notify_handler(USB_EVENT_EP_OUT_NOTIFY, args); + break; + + default: + break; + } +} +struct device *usb_dc_init(void) +{ + usb_dc_register(USB_INDEX, "usb"); + usb = device_find("usb"); + device_set_callback(usb, usb_dc_event_callback); + device_open(usb, 0); + return usb; +} + +int usbd_set_address(const uint8_t addr) +{ + return usb_dc_set_dev_address(addr); +} + +int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg) +{ + return usb_dc_ep_open(usb, (const struct usb_dc_ep_cfg *)ep_cfg); +} +int usbd_ep_close(const uint8_t ep) +{ + return usb_dc_ep_close(ep); +} +int usbd_ep_set_stall(const uint8_t ep) +{ + return usb_dc_ep_set_stall(ep); +} +int usbd_ep_clear_stall(const uint8_t ep) +{ + return usb_dc_ep_clear_stall(ep); +} +int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled) +{ + return usb_dc_ep_is_stalled(usb, ep, stalled); +} + +int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) +{ + return usb_dc_ep_write(usb, ep, data, data_len, ret_bytes); +} + +int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes) +{ + return usb_dc_ep_read(usb, ep, data, max_data_len, read_bytes); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..05c627927f6f09a72e87e82d0af726a4334613f8 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.c @@ -0,0 +1,50 @@ +/** + * @file arm_dsp_wrapper.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "arm_dsp_wrapper.h" + +void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize) +{ + uint32_t blkCnt = blockSize >> 2u; + + float32_t in1 = value; + float32_t in2 = value; + float32_t in3 = value; + float32_t in4 = value; + + while (blkCnt > 0u) { + *pDst++ = in1; + *pDst++ = in2; + *pDst++ = in3; + *pDst++ = in4; + + blkCnt--; + } + + blkCnt = blockSize % 0x4u; + + while (blkCnt > 0u) { + *pDst++ = value; + blkCnt--; + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.h new file mode 100644 index 0000000000000000000000000000000000000000..29373b35ff25298aabc5412f9f559b99e28c4931 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.h @@ -0,0 +1,44 @@ +/** + * @file arm_dsp_wrapper.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __MY_MATH_F_H__ +#define __MY_MATH_F_H__ + +#include "bflb_platform.h" +#include "math.h" + +typedef float float32_t; + +__INLINE__ float32_t arm_sqrt_f32(float32_t x) +{ + return sqrtf(x); +} + +__INLINE__ float32_t arm_cos_f32(float32_t x) +{ + return cosf(x); +} + +void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/device/drv_device.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/device/drv_device.c new file mode 100644 index 0000000000000000000000000000000000000000..6fba96bfc1c368e27aa2ade0c6a3fde805240821 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/device/drv_device.c @@ -0,0 +1,271 @@ +/** + * @file drv_device.c + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "drv_device.h" +#include "string.h" + +#define dev_open (dev->open) +#define dev_close (dev->close) +#define dev_read (dev->read) +#define dev_write (dev->write) +#define dev_control (dev->control) + +dlist_t device_head = DLIST_OBJECT_INIT(device_head); + +/** + * This function registers a device driver with specified name. + * + * @param dev the pointer of device driver structure + * @param name the device driver's name + * @param flags the capabilities flag of device + * + * @return the error code, DEVICE_EOK on initialization successfully. + */ +int device_register(struct device *dev, const char *name) +{ + dlist_t *node; + + dlist_for_each(node, &device_head) + { + struct device *dev_obj; + dev_obj = dlist_entry(node, struct device, list); + + if (dev_obj == dev) { + return -DEVICE_EEXIST; + } + } + + strncpy(dev->name, name, DEVICE_NAME_MAX); + + dlist_insert_after(&device_head, &(dev->list)); + dev->status = DEVICE_REGISTERED; + return DEVICE_EOK; +} +/** + * This function get device list header + * + * @param None + * + * @return device header + */ +dlist_t *device_get_list_header(void) +{ + return &device_head; +} +/** + * This function unregisters a device driver with specified name. + * + * @param dev the pointer of device driver structure + * @param name the device driver's name + * @param flags the capabilities flag of device + * + * @return the error code, DEVICE_EOK on initialization successfully. + */ +int device_unregister(const char *name) +{ + struct device *dev = device_find(name); + + if (!dev) { + return -DEVICE_ENODEV; + } + dev->status = DEVICE_UNREGISTER; + /* remove from old list */ + dlist_remove(&(dev->list)); + return DEVICE_EOK; +} + +/** + * This function finds a device driver by specified name. + * + * @param name the device driver's name + * + * @return the registered device driver on successful, or NULL on failure. + */ +struct device *device_find(const char *name) +{ + struct device *dev; + dlist_t *node; + + dlist_for_each(node, &device_head) + { + dev = dlist_entry(node, struct device, list); + + if (strncmp(dev->name, name, DEVICE_NAME_MAX) == 0) { + return dev; + } + } + return NULL; +} + +/** + * This function will open a device + * + * @param dev the pointer of device driver structure + * @param oflag the flags for device open + * + * @return the result + */ +int device_open(struct device *dev, uint16_t oflag) +{ + int retval = DEVICE_EOK; + + if ((dev->status == DEVICE_REGISTERED) || (dev->status == DEVICE_CLOSED)) { + if (dev_open != NULL) { + retval = dev_open(dev, oflag); + dev->status = DEVICE_OPENED; + dev->oflag |= oflag; + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +} +/** + * This function will close a device + * + * @param dev the pointer of device driver structure + * + * @return the result + */ +int device_close(struct device *dev) +{ + int retval = DEVICE_EOK; + + if (dev->status == DEVICE_OPENED) { + if (dev_close != NULL) { + retval = dev_close(dev); + dev->status = DEVICE_CLOSED; + dev->oflag = 0; + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +} +/** + * This function will perform a variety of control functions on devices. + * + * @param dev the pointer of device driver structure + * @param cmd the command sent to device + * @param arg the argument of command + * + * @return the result + */ +int device_control(struct device *dev, int cmd, void *args) +{ + int retval = DEVICE_EOK; + + if (dev->status > DEVICE_UNREGISTER) { + if (dev_control != NULL) { + retval = dev_control(dev, cmd, args); + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +} +/** + * This function will write some data to a device. + * + * @param dev the pointer of device driver structure + * @param pos the position of written + * @param buffer the data buffer to be written to device + * @param size the size of buffer + * + * @return the actually written size on successful, otherwise negative returned. + */ +int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + int retval = DEVICE_EOK; + + if (dev->status == DEVICE_OPENED) { + if (dev_write != NULL) { + retval = dev_write(dev, pos, buffer, size); + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +} +/** + * This function will read some data from a device. + * + * @param dev the pointer of device driver structure + * @param pos the position of reading + * @param buffer the data buffer to save read data + * @param size the size of buffer + * + * @return the actually read size on successful, otherwise negative returned. + */ +int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + int retval = DEVICE_EOK; + + if (dev->status == DEVICE_OPENED) { + if (dev_read != NULL) { + retval = dev_read(dev, pos, buffer, size); + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +} +/** + * This function will read some data from a device. + * + * @param dev the pointer of device driver structure + * @param pos the position of reading + * @param buffer the data buffer to save read data + * @param size the size of buffer + * + * @return the actually read size on successful, otherwise negative returned. + */ +int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)) +{ + int retval = DEVICE_EOK; + + if (dev->status > DEVICE_UNREGISTER) { + if (callback != NULL) { + dev->callback = callback; + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/device/drv_device.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/device/drv_device.h new file mode 100644 index 0000000000000000000000000000000000000000..101d1cfa42849d7ab3e4708480c3bb941d08c615 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/device/drv_device.h @@ -0,0 +1,135 @@ +/** + * @file drv_device.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __DRV_DEVICE_H__ +#define __DRV_DEVICE_H__ + +#include "drv_list.h" +#include "bflb_platform.h" + +#define DEVICE_NAME_MAX 20 /* max device name*/ + +#define DEVICE_OFLAG_DEFAULT 0x000 /* open with default */ +#define DEVICE_OFLAG_STREAM_TX 0x001 /* open with poll tx */ +#define DEVICE_OFLAG_STREAM_RX 0x002 /* open with poll rx */ +#define DEVICE_OFLAG_INT_TX 0x004 /* open with interrupt tx */ +#define DEVICE_OFLAG_INT_RX 0x008 /* open with interrupt rx */ +#define DEVICE_OFLAG_DMA_TX 0x010 /* open with dma tx */ +#define DEVICE_OFLAG_DMA_RX 0x020 /* open with dma rx */ + +#define DEVICE_CTRL_SET_INT 0x01 /* set interrupt */ +#define DEVICE_CTRL_CLR_INT 0x02 /* clear interrupt */ +#define DEVICE_CTRL_GET_INT 0x03 /* get interrupt status*/ +#define DEVICE_CTRL_RESUME 0x04 /* resume device */ +#define DEVICE_CTRL_SUSPEND 0x05 /* suspend device */ +#define DEVICE_CTRL_CONFIG 0x06 /* config device */ +#define DEVICE_CTRL_GET_CONFIG 0x07 /* get device configuration */ +#define DEVICE_CTRL_ATTACH_TX_DMA 0x08 /* deivce link tx dma */ +#define DEVICE_CTRL_ATTACH_RX_DMA 0x09 /* deivce link rx dma */ +#define DEVICE_CTRL_TX_DMA_SUSPEND 0x0a /* deivce suspend tx dma */ +#define DEVICE_CTRL_RX_DMA_SUSPEND 0x0b /* deivce suspend rx dma */ +#define DEVICE_CTRL_TX_DMA_RESUME 0x0c /* deivce resume tx dma */ +#define DEVICE_CTRL_RX_DMA_RESUME 0x0d /* deivce resume rx dma */ +#define DEVICE_CTRL_RESVD1 0x0E +#define DEVICE_CTRL_RESVD2 0x0F + +/* + * POSIX Error codes + */ + +#define DEVICE_EOK 0 +#define DEVICE_EFAULT 14 /* Bad address */ +#define DEVICE_EEXIST 17 /* device exists */ +#define DEVICE_ENODEV 19 /* No such device */ +#define DEVICE_EINVAL 22 /* Invalid argument */ +#define DEVICE_ENOSPACE 23 /* No more Device for Allocate */ + +#define __ASSERT_PRINT(fmt, ...) bflb_platform_printf(fmt, ##__VA_ARGS__) + +#define __ASSERT_LOC(test) \ + __ASSERT_PRINT("ASSERTION FAIL [%s] @ %s:%d\n", \ + #test, \ + __FILE__, __LINE__) + +#define DEVICE_ASSERT(test, fmt, ...) \ + do { \ + if (!(test)) { \ + __ASSERT_LOC(test); \ + __ASSERT_PRINT(fmt, ##__VA_ARGS__); \ + } \ + } while (0) + +enum device_class_type { + DEVICE_CLASS_NONE = 0, + DEVICE_CLASS_GPIO, + DEVICE_CLASS_UART, + DEVICE_CLASS_SPI, + DEVICE_CLASS_I2C, + DEVICE_CLASS_ADC, + DEVICE_CLASS_DAC, + DEVICE_CLASS_DMA, + DEVICE_CLASS_TIMER, + DEVICE_CLASS_PWM, + DEVICE_CLASS_QDEC, + DEVICE_CLASS_SDIO, + DEVICE_CLASS_USB, + DEVICE_CLASS_RMII, + DEVICE_CLASS_I2S, + DEVICE_CLASS_CAMERA, + DEVICE_CLASS_SEC_HASH, + DEVICE_CLASS_KEYSCAN, +}; + +enum device_status_type { + DEVICE_UNREGISTER = 0, + DEVICE_REGISTERED, + DEVICE_OPENED, + DEVICE_CLOSED +}; + +struct device { + char name[DEVICE_NAME_MAX]; /*name of device */ + dlist_t list; /*list node of device */ + enum device_status_type status; /*status of device */ + enum device_class_type type; /*type of device */ + uint16_t oflag; /*oflag of device */ + + int (*open)(struct device *dev, uint16_t oflag); + int (*close)(struct device *dev); + int (*control)(struct device *dev, int cmd, void *args); + int (*write)(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); + int (*read)(struct device *dev, uint32_t pos, void *buffer, uint32_t size); + void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event); + void *handle; +}; + +int device_register(struct device *dev, const char *name); +int device_unregister(const char *name); +struct device *device_find(const char *name); +int device_open(struct device *dev, uint16_t oflag); +int device_close(struct device *dev); +int device_control(struct device *dev, int cmd, void *args); +int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); +int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size); +int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)); +dlist_t *device_get_list_header(void); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/list/drv_list.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/list/drv_list.h new file mode 100644 index 0000000000000000000000000000000000000000..c84c8a3f6c338f3aa7ea8e59655810382075e4fd --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/list/drv_list.h @@ -0,0 +1,472 @@ +/** + * @file drv_list.h + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __DRV_LIST_H__ +#define __DRV_LIST_H__ + +#include "string.h" +#include "stdint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * Double List structure + */ +struct dlist_node { + struct dlist_node *next; /**< point to next node. */ + struct dlist_node *prev; /**< point to prev node. */ +}; +typedef struct dlist_node dlist_t; /**< Type for lists. */ + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +static inline void dlist_init(dlist_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +static inline void dlist_insert_after(dlist_t *l, dlist_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +static inline void dlist_insert_before(dlist_t *l, dlist_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +static inline void dlist_remove(dlist_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void dlist_move_head(dlist_t *l, dlist_t *n) +{ + dlist_remove(n); + dlist_insert_after(l, n); +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void dlist_move_tail(dlist_t *l, dlist_t *n) +{ + dlist_remove(n); + dlist_insert_before(l, n); +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +static inline int dlist_isempty(const dlist_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +static inline unsigned int dlist_len(const dlist_t *l) +{ + unsigned int len = 0; + const dlist_t *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief initialize a dlist object + */ +#define DLIST_OBJECT_INIT(object) \ + { \ + &(object), &(object) \ + } +/** + * @brief initialize a dlist object + */ +#define DLIST_DEFINE(list) \ + dlist_t list = { &(list), &(list) } + +/** + * dlist_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define dlist_first_entry(ptr, type, member) \ + dlist_entry((ptr)->next, type, member) +/** + * dlist_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define dlist_first_entry_or_null(ptr, type, member) \ + (dlist_isempty(ptr) ? NULL : dlist_first_entry(ptr, type, member)) + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define dlist_entry(node, type, member) \ + container_of(node, type, member) + +/** + * dlist_for_each - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * dlist_for_each_prev - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define dlist_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * dlist_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the dlist_t * to use as a loop cursor. + * @n: another dlist_t * to use as temporary storage + * @head: the head for your list. + */ +#define dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +#define dlist_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) +/** + * dlist_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define dlist_for_each_entry(pos, head, member) \ + for (pos = dlist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = dlist_entry(pos->member.next, typeof(*pos), member)) + +/** + * dlist_for_each_entry_reverse - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define dlist_for_each_entry_reverse(pos, head, member) \ + for (pos = dlist_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define dlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = dlist_entry((head)->next, typeof(*pos), member), \ + n = dlist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = dlist_entry(n->member.next, typeof(*n), member)) + +/** + * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define dlist_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = dlist_entry((head)->prev, typeof(*pos), field), \ + n = dlist_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * Single List structure + */ +struct slist_node { + struct slist_node *next; /**< point to next node. */ +}; +typedef struct slist_node slist_t; /**< Type for single list. */ + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +static inline void slist_init(slist_t *l) +{ + l->next = NULL; +} + +static inline void slist_add_head(slist_t *l, slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +static inline void slist_add_tail(slist_t *l, slist_t *n) +{ + while (l->next) { + l = l->next; + } + + /* append the node to the tail */ + l->next = n; + n->next = NULL; +} + +static inline void slist_insert(slist_t *l, slist_t *next, slist_t *n) +{ + if (!next) { + slist_add_tail(next, l); + return; + } + + while (l->next) { + if (l->next == next) { + l->next = n; + n->next = next; + } + + l = l->next; + } +} + +static inline slist_t *slist_remove(slist_t *l, slist_t *n) +{ + /* remove slist head */ + while (l->next && l->next != n) { + l = l->next; + } + + /* remove node */ + if (l->next != (slist_t *)0) { + l->next = l->next->next; + } + + return l; +} + +static inline unsigned int slist_len(const slist_t *l) +{ + unsigned int len = 0; + const slist_t *list = l->next; + + while (list != NULL) { + list = list->next; + len++; + } + + return len; +} + +static inline unsigned int slist_contains(slist_t *l, slist_t *n) +{ + while (l->next) { + if (l->next == n) { + return 0; + } + + l = l->next; + } + + return 1; +} + +static inline slist_t *slist_head(slist_t *l) +{ + return l->next; +} + +static inline slist_t *slist_tail(slist_t *l) +{ + while (l->next) { + l = l->next; + } + + return l; +} + +static inline slist_t *slist_next(slist_t *n) +{ + return n->next; +} + +static inline int slist_isempty(slist_t *l) +{ + return l->next == NULL; +} + +/** + * @brief initialize a slist object + */ +#define SLIST_OBJECT_INIT(object) \ + { \ + NULL \ + } + +/** + * @brief initialize a slist object + */ +#define SLIST_DEFINE(slist) \ + slist_t slist = { NULL } + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define slist_entry(node, type, member) \ + container_of(node, type, member) + +/** + * slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define slist_first_entry(ptr, type, member) \ + slist_entry((ptr)->next, type, member) + +/** + * slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define slist_tail_entry(ptr, type, member) \ + slist_entry(slist_tail(ptr), type, member) + +/** + * slist_first_entry_or_null - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define slist_first_entry_or_null(ptr, type, member) \ + (slist_isempty(ptr) ? NULL : slist_first_entry(ptr, type, member)) + +/** + * slist_for_each - iterate over a single list + * @pos: the slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define slist_for_each(pos, head) \ + for (pos = (head)->next; pos != NULL; pos = pos->next) + +#define slist_for_each_safe(pos, next, head) \ + for (pos = (head)->next, next = pos->next; pos; \ + pos = next, next = pos->next) + +/** + * slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define slist_for_each_entry(pos, head, member) \ + for (pos = slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = slist_entry(pos->member.next, typeof(*pos), member)) + +#define slist_for_each_entry_safe(pos, n, head, member) \ + for (pos = slist_entry((head)->next, typeof(*pos), member), \ + n = slist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = n, n = slist_entry(pos->member.next, typeof(*pos), member)) + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/memheap/drv_mmheap.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/memheap/drv_mmheap.c new file mode 100644 index 0000000000000000000000000000000000000000..f4a08baeb767e7d721449679e5be6814f5d96d20 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/memheap/drv_mmheap.c @@ -0,0 +1,794 @@ +/** + * @file drv_mmheap.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "drv_mmheap.h" + +mmheap_ctl_t mmheap_ctl; + +static int generic_fls(uint32_t x) +{ + int r = 32; + + if (!x) { + return 0; + } + + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + + return r; +} + +static int __ffs(uint32_t word) +{ + return generic_fls(word & (~word + 1)) - 1; +} + +static int __fls(uint32_t word) +{ + return generic_fls(word) - 1; +} + +static inline size_t blk_size(const mmheap_blk_t *blk) +{ + return blk->size & MMHEAP_BLOCK_SIZE_MASK; +} + +static inline void blk_set_size(mmheap_blk_t *blk, size_t size) +{ + blk->size = size | (blk->size & MMHEAP_BLOCK_STATE_MASK); +} + +static inline int blk_is_last(const mmheap_blk_t *blk) +{ + return blk_size(blk) == 0; +} + +static inline int blk_is_free(const mmheap_blk_t *blk) +{ + return blk->size & MMHEAP_BLOCK_CURR_FREE; +} + +static inline void blk_set_free(mmheap_blk_t *blk) +{ + blk->size |= MMHEAP_BLOCK_CURR_FREE; +} + +static inline void blk_set_used(mmheap_blk_t *blk) +{ + blk->size &= ~MMHEAP_BLOCK_CURR_FREE; +} + +static inline int blk_is_prev_free(const mmheap_blk_t *blk) +{ + return blk->size & MMHEAP_BLOCK_PREV_FREE; +} + +static inline void blk_set_prev_free(mmheap_blk_t *blk) +{ + blk->size |= MMHEAP_BLOCK_PREV_FREE; +} + +static void blk_set_prev_used(mmheap_blk_t *blk) +{ + blk->size &= ~MMHEAP_BLOCK_PREV_FREE; +} + +static inline mmheap_blk_t *blk_from_ptr(const void *ptr) +{ + return (mmheap_blk_t *)((uint32_t)(uintptr_t)ptr - MMHEAP_BLK_START_OFFSET); +} + +static inline void *blk_to_ptr(const mmheap_blk_t *blk) +{ + return (void *)((uint32_t)(uintptr_t)blk + MMHEAP_BLK_START_OFFSET); +} + +/* Return location of next block after block of given size. */ +static inline mmheap_blk_t *offset_to_blk(const void *ptr, int diff) +{ + return (mmheap_blk_t *)(uintptr_t)((uint32_t)(uintptr_t)ptr + diff); +} + +/* Return location of previous block. */ +static inline mmheap_blk_t *blk_prev(const mmheap_blk_t *blk) +{ + return blk->prev_phys_blk; +} + +/* Return location of next existing block. */ +static mmheap_blk_t *blk_next(const mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + next_blk = offset_to_blk(blk_to_ptr(blk), blk_size(blk) - MMHEAP_BLK_HEADER_OVERHEAD); + return next_blk; +} + +/* Link a new block with its physical neighbor, return the neighbor. */ +static mmheap_blk_t *blk_link_next(mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + next_blk = blk_next(blk); + next_blk->prev_phys_blk = blk; + return next_blk; +} + +static void blk_mark_as_free(mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + /* Link the block to the next block, first. */ + next_blk = blk_link_next(blk); + blk_set_prev_free(next_blk); + blk_set_free(blk); +} + +static void blk_mark_as_used(mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + next_blk = blk_next(blk); + blk_set_prev_used(next_blk); + blk_set_used(blk); +} + +static inline size_t align_up(size_t x, size_t align) +{ + return (x + (align - 1)) & ~(align - 1); +} + +static inline size_t align_down(size_t x, size_t align) +{ + return x - (x & (align - 1)); +} + +static inline void *align_ptr(const void *ptr, size_t align) +{ + return (void *)(((uint32_t)(uintptr_t)ptr + (align - 1)) & ~(align - 1)); +} + +/* +** Adjust an allocation size to be aligned to word size, and no smaller +** than internal minimum. +*/ +static size_t adjust_request_size(size_t size, size_t align) +{ + size_t adjust_size = 0; + + if (!size) { + return 0; + } + + adjust_size = align_up(size, align); + + if (adjust_size > MMHEAP_BLK_SIZE_MAX) { + return 0; + } + + /* aligned sized must not exceed block_size_max or we'll go out of bounds on sl_bitmap */ + return adjust_size > MMHEAP_BLK_SIZE_MIN ? adjust_size : MMHEAP_BLK_SIZE_MIN; +} + +/* +** TLSF utility functions. In most cases, these are direct translations of +** the documentation found in the white paper. +*/ +static void mapping_insert(size_t size, int *fli, int *sli) +{ + int fl, sl; + + if (size < MMHEAP_SMALL_BLOCK_SIZE) { + /* Store small blocks in first list. */ + fl = 0; + sl = (int)size / (MMHEAP_SMALL_BLOCK_SIZE / MMHEAP_SL_INDEX_COUNT); + } else { + fl = __fls(size); + sl = ((int)size >> (fl - MMHEAP_SL_INDEX_COUNT_LOG2)) ^ (1 << MMHEAP_SL_INDEX_COUNT_LOG2); + fl -= (MMHEAP_FL_INDEX_SHIFT - 1); + } + + *fli = fl; + *sli = sl; +} + +/* This version rounds up to the next block size (for allocations) */ +static void mapping_search(size_t size, int *fli, int *sli) +{ + size_t round; + + if (size >= MMHEAP_SMALL_BLOCK_SIZE) { + round = (1 << (__fls(size) - MMHEAP_SL_INDEX_COUNT_LOG2)) - 1; + size += round; + } + + mapping_insert(size, fli, sli); +} + +static mmheap_blk_t *blk_search_suitable(int *fli, int *sli) +{ + int fl, sl; + uint32_t sl_map, fl_map; + + fl = *fli; + sl = *sli; + + /* + ** First, search for a block in the list associated with the given + ** fl/sl index. + */ + sl_map = mmheap_ctl.sl_bitmap[fl] & (~0U << sl); + + if (!sl_map) { + /* No block exists. Search in the next largest first-level list. */ + fl_map = mmheap_ctl.fl_bitmap & (~0U << (fl + 1)); + + if (!fl_map) { + /* No free blocks available, memory has been exhausted. */ + return 0; + } + + fl = __ffs(fl_map); + *fli = fl; + sl_map = mmheap_ctl.sl_bitmap[fl]; + } + + sl = __ffs(sl_map); + *sli = sl; + + /* Return the first block in the free list. */ + return mmheap_ctl.blocks[fl][sl]; +} + +/* Insert a free block into the free block list. */ +static void insert_free_block(mmheap_blk_t *blk, int fl, int sl) +{ + mmheap_blk_t *curr; + + curr = mmheap_ctl.blocks[fl][sl]; + blk->next_free = curr; + blk->prev_free = &mmheap_ctl.block_null; + curr->prev_free = blk; + + /* + ** Insert the new block at the head of the list, and mark the first- + ** and second-level bitmaps appropriately. + */ + mmheap_ctl.blocks[fl][sl] = blk; + mmheap_ctl.fl_bitmap |= (1 << fl); + mmheap_ctl.sl_bitmap[fl] |= (1 << sl); +} + +/* Remove a free block from the free list.*/ +static void remove_free_block(mmheap_blk_t *blk, int fl, int sl) +{ + mmheap_blk_t *prev_blk; + mmheap_blk_t *next_blk; + + prev_blk = blk->prev_free; + next_blk = blk->next_free; + next_blk->prev_free = prev_blk; + prev_blk->next_free = next_blk; + + /* If this block is the head of the free list, set new head. */ + if (mmheap_ctl.blocks[fl][sl] == blk) { + mmheap_ctl.blocks[fl][sl] = next_blk; + + /* If the new head is null, clear the bitmap. */ + if (next_blk == &mmheap_ctl.block_null) { + mmheap_ctl.sl_bitmap[fl] &= ~(1 << sl); + + /* If the second bitmap is now empty, clear the fl bitmap. */ + if (!mmheap_ctl.sl_bitmap[fl]) { + mmheap_ctl.fl_bitmap &= ~(1 << fl); + } + } + } +} + +/* Remove a given block from the free list. */ +static void blk_remove(mmheap_blk_t *blk) +{ + int fl, sl; + + mapping_insert(blk_size(blk), &fl, &sl); + remove_free_block(blk, fl, sl); +} + +/* Insert a given block into the free list. */ +static void blk_insert(mmheap_blk_t *blk) +{ + int fl, sl; + + mapping_insert(blk_size(blk), &fl, &sl); + insert_free_block(blk, fl, sl); +} + +static int blk_can_split(mmheap_blk_t *blk, size_t size) +{ + return blk_size(blk) >= sizeof(mmheap_blk_t) + size; +} + +/* Split a block into two, the second of which is free. */ +static mmheap_blk_t *blk_split(mmheap_blk_t *blk, size_t size) +{ + mmheap_blk_t *remaining; + size_t remain_size; + + /* Calculate the amount of space left in the remaining block. */ + remaining = offset_to_blk(blk_to_ptr(blk), size - MMHEAP_BLK_HEADER_OVERHEAD); + remain_size = blk_size(blk) - (size + MMHEAP_BLK_HEADER_OVERHEAD); + + blk_set_size(remaining, remain_size); + + blk_set_size(blk, size); + blk_mark_as_free(remaining); + + return remaining; +} + +/* Absorb a free block's storage into an adjacent previous free block. */ +static mmheap_blk_t *blk_absorb(mmheap_blk_t *prev_blk, mmheap_blk_t *blk) +{ + prev_blk->size += blk_size(blk) + MMHEAP_BLK_HEADER_OVERHEAD; + blk_link_next(prev_blk); + return prev_blk; +} + +/* Merge a just-freed block with an adjacent previous free block. */ +static mmheap_blk_t *blk_merge_prev(mmheap_blk_t *blk) +{ + mmheap_blk_t *prev_blk; + + if (blk_is_prev_free(blk)) { + prev_blk = blk_prev(blk); + blk_remove(prev_blk); + blk = blk_absorb(prev_blk, blk); + } + + return blk; +} + +/* Merge a just-freed block with an adjacent free block. */ +static mmheap_blk_t *blk_merge_next(mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + next_blk = blk_next(blk); + + if (blk_is_free(next_blk)) { + blk_remove(next_blk); + blk = blk_absorb(blk, next_blk); + } + + return blk; +} + +/* Trim any trailing block space off the end of a block, return to pool. */ +static void blk_trim_free(mmheap_blk_t *blk, size_t size) +{ + mmheap_blk_t *remaining_blk; + + if (blk_can_split(blk, size)) { + remaining_blk = blk_split(blk, size); + blk_link_next(blk); + blk_set_prev_free(remaining_blk); + blk_insert(remaining_blk); + } +} + +/* Trim any trailing block space off the end of a used block, return to pool. */ +static void blk_trim_used(mmheap_blk_t *blk, size_t size) +{ + mmheap_blk_t *remaining_blk; + + if (blk_can_split(blk, size)) { + /* If the next block is free, we must coalesce. */ + remaining_blk = blk_split(blk, size); + blk_set_prev_used(remaining_blk); + + remaining_blk = blk_merge_next(remaining_blk); + blk_insert(remaining_blk); + } +} + +static mmheap_blk_t *blk_trim_free_leading(mmheap_blk_t *blk, size_t size) +{ + mmheap_blk_t *remaining_blk; + + remaining_blk = blk; + + if (blk_can_split(blk, size)) { + /* We want the 2nd block. */ + remaining_blk = blk_split(blk, size - MMHEAP_BLK_HEADER_OVERHEAD); + blk_set_prev_free(remaining_blk); + + blk_link_next(blk); + blk_insert(blk); + } + + return remaining_blk; +} + +static mmheap_blk_t *blk_locate_free(size_t size) +{ + int fl = 0, sl = 0; + mmheap_blk_t *blk = NULL; + + if (!size) { + return NULL; + } + + mapping_search(size, &fl, &sl); + + /* + ** mapping_search can futz with the size, so for excessively large sizes it can sometimes wind up + ** with indices that are off the end of the block array. + ** So, we protect against that here, since this is the only callsite of mapping_search. + ** Note that we don't need to check sl, since it comes from a modulo operation that guarantees it's always in range. + */ + if (fl < MMHEAP_FL_INDEX_COUNT) { + blk = blk_search_suitable(&fl, &sl); + } + + if (blk) { + remove_free_block(blk, fl, sl); + } + + return blk; +} + +static void *blk_prepare_used(mmheap_blk_t *blk, size_t size) +{ + if (!blk) { + return NULL; + } + + blk_trim_free(blk, size); + blk_mark_as_used(blk); + return blk_to_ptr(blk); +} + +static void control_construct(void) +{ + int i, j; + + mmheap_ctl.pool_cnt = 0u; + + for (i = 0; i < MMHEAP_POOL_MAX; ++i) { + mmheap_ctl.pool_start[i] = (void *)NULL; + } + + mmheap_ctl.block_null.next_free = &mmheap_ctl.block_null; + mmheap_ctl.block_null.prev_free = &mmheap_ctl.block_null; + + mmheap_ctl.fl_bitmap = 0; + + for (i = 0; i < MMHEAP_FL_INDEX_COUNT; ++i) { + mmheap_ctl.sl_bitmap[i] = 0; + + for (j = 0; j < MMHEAP_SL_INDEX_COUNT; ++j) { + mmheap_ctl.blocks[i][j] = &mmheap_ctl.block_null; + } + } +} + +static inline int mmheap_pool_is_full(void) +{ + return mmheap_ctl.pool_cnt == MMHEAP_POOL_MAX; +} + +static int mmheap_pool_is_exist(void *pool_start) +{ + int i = 0; + + for (i = 0; i < mmheap_ctl.pool_cnt; ++i) { + if (mmheap_ctl.pool_start[i] == pool_start) { + return 1; + } + } + + return 0; +} + +static inline void mmheap_pool_record(void *pool_start) +{ + mmheap_ctl.pool_start[mmheap_ctl.pool_cnt++] = pool_start; +} + +static void mmheap_pool_unrecord(void *pool_start) +{ + int i = 0; + + for (i = 0; i < mmheap_ctl.pool_cnt; ++i) { + if (mmheap_ctl.pool_start[i] == pool_start) { + break; + } + } + + if (i != mmheap_ctl.pool_cnt - 1) { + mmheap_ctl.pool_start[i] = mmheap_ctl.pool_start[mmheap_ctl.pool_cnt - 1]; + } + + --mmheap_ctl.pool_cnt; +} + +int mmheap_init_with_pool(void *pool_start, size_t pool_size) +{ + control_construct(); + + return mmheap_pool_add(pool_start, pool_size); +} + +void *mmheap_alloc(size_t size) +{ + size_t adjust_size; + mmheap_blk_t *blk; + + adjust_size = adjust_request_size(size, MMHEAP_ALIGN_SIZE); + blk = blk_locate_free(adjust_size); + + if (!blk) { + return NULL; + } + + return blk_prepare_used(blk, adjust_size); +} + +void *mmheap_calloc(size_t num, size_t size) +{ + void *ptr; + + ptr = mmheap_alloc(num * size); + + if (ptr) { + memset(ptr, 0, num * size); + } + + return ptr; +} + +void *mmheap_aligned_alloc(size_t size, size_t align) +{ + mmheap_blk_t *blk; + void *ptr, *aligned, *next_aligned; + size_t adjust_size, aligned_size; + size_t gap_minimum, size_with_gap, gap, gap_remain, offset; + + adjust_size = adjust_request_size(size, MMHEAP_ALIGN_SIZE); + gap_minimum = sizeof(mmheap_blk_t); + size_with_gap = adjust_request_size(adjust_size + align + gap_minimum, align); + aligned_size = (adjust_size && align > MMHEAP_ALIGN_SIZE) ? size_with_gap : adjust_size; + + blk = blk_locate_free(aligned_size); + + if (!blk) { + return NULL; + } + + ptr = blk_to_ptr(blk); + aligned = align_ptr(ptr, align); + gap = (size_t)((uint32_t)(uintptr_t)aligned - (uint32_t)(uintptr_t)ptr); + + if (gap && gap < gap_minimum) { + gap_remain = gap_minimum - gap; + offset = gap_remain > align ? gap_remain : align; + next_aligned = (void *)((uint32_t)(uintptr_t)aligned + offset); + + aligned = align_ptr(next_aligned, align); + gap = (size_t)((uint32_t)(uintptr_t)aligned - (uint32_t)(uintptr_t)ptr); + } + + if (gap) { + blk = blk_trim_free_leading(blk, gap); + } + + return blk_prepare_used(blk, adjust_size); +} + +void mmheap_free(void *ptr) +{ + mmheap_blk_t *blk; + + if (!ptr) { + return; + } + + blk = blk_from_ptr(ptr); + blk_mark_as_free(blk); + blk = blk_merge_prev(blk); + blk = blk_merge_next(blk); + blk_insert(blk); +} + +void *mmheap_realloc(void *ptr, size_t size) +{ + void *p = 0; + mmheap_blk_t *curr_blk, *next_blk; + size_t curr_size, combined_size, adjust_size, min_size; + + if (ptr && size == 0) { + mmheap_free(ptr); + return NULL; + } + + if (!ptr) { + return mmheap_alloc(size); + } + + curr_blk = blk_from_ptr(ptr); + next_blk = blk_next(curr_blk); + + curr_size = blk_size(curr_blk); + combined_size = curr_size + blk_size(next_blk) + MMHEAP_BLK_HEADER_OVERHEAD; + adjust_size = adjust_request_size(size, MMHEAP_ALIGN_SIZE); + + if (adjust_size > curr_size && (!blk_is_free(next_blk) || adjust_size > combined_size)) { + p = mmheap_alloc(size); + + if (p) { + min_size = curr_size < size ? curr_size : size; + memcpy(p, ptr, min_size); + mmheap_free(ptr); + } + } else { + if (adjust_size > curr_size) { + blk_merge_next(curr_blk); + blk_mark_as_used(curr_blk); + } + + blk_trim_used(curr_blk, adjust_size); + p = ptr; + } + + return p; +} + +int mmheap_pool_add(void *pool_start, size_t pool_size) +{ + mmheap_blk_t *curr_blk; + mmheap_blk_t *next_blk; + size_t size_aligned; + + if (mmheap_pool_is_full()) { + return MEMHEAP_STATUS_OVERFLOW; + } + + if (mmheap_pool_is_exist(pool_start)) { + return MEMHEAP_STATUS_ALREADY_EXIST; + } + + size_aligned = align_down(pool_size - 2 * MMHEAP_BLK_HEADER_OVERHEAD, MMHEAP_ALIGN_SIZE); + + if (((uint32_t)(uintptr_t)pool_start % MMHEAP_ALIGN_SIZE) != 0u) { + return MEMHEAP_STATUS_INVALID_ADDR; + } + + if (size_aligned < MMHEAP_BLK_SIZE_MIN || + size_aligned > MMHEAP_BLK_SIZE_MAX) { + return MEMHEAP_STATUS_INVALID_SIZE; + } + + /* + ** Create the main free block. Offset the start of the block slightly + ** so that the prev_phys_block field falls outside of the pool - + ** it will never be used. + */ + curr_blk = offset_to_blk(pool_start, -(int)MMHEAP_BLK_HEADER_OVERHEAD); + blk_set_size(curr_blk, size_aligned); + blk_set_free(curr_blk); + blk_set_prev_used(curr_blk); + blk_insert(curr_blk); + + /* Split the block to create a zero-size sentinel block. */ + next_blk = blk_link_next(curr_blk); + blk_set_size(next_blk, 0); + blk_set_used(next_blk); + blk_set_prev_free(next_blk); + + mmheap_pool_record(pool_start); + + return MEMHEAP_STATUS_OK; +} + +int mmheap_pool_rmv(void *pool_start) +{ + int fl = 0, sl = 0; + mmheap_blk_t *blk; + + if (!mmheap_pool_is_exist(pool_start)) { + return MEMHEAP_STATUS_ALREADY_NOT_EXIST; + } + + blk = offset_to_blk(pool_start, -(int)MMHEAP_BLK_HEADER_OVERHEAD); + mapping_insert(blk_size(blk), &fl, &sl); + remove_free_block(blk, fl, sl); + + mmheap_pool_unrecord(pool_start); + return MEMHEAP_STATUS_OK; +} + +int mmheap_pool_check(void *pool_start, mmheap_info_t *info) +{ + mmheap_blk_t *blk; + + memset(info, 0, sizeof(mmheap_info_t)); + + blk = offset_to_blk(pool_start, -(int)MMHEAP_BLK_HEADER_OVERHEAD); + + while (blk && !blk_is_last(blk)) { + if (blk_is_free(blk)) { + info->free += blk_size(blk); + } else { + info->used += blk_size(blk); + } + + blk = blk_next(blk); + } + + return MEMHEAP_STATUS_OK; +} + +int mmheap_check(mmheap_info_t *info) +{ + int i; + int err; + mmheap_info_t pool_info; + + memset(info, 0, sizeof(mmheap_info_t)); + + for (i = 0; i < mmheap_ctl.pool_cnt; ++i) { + err = mmheap_pool_check(mmheap_ctl.pool_start[i], &pool_info); + + if (err != MEMHEAP_STATUS_OK) { + return err; + } + + info->free += pool_info.free; + info->used += pool_info.used; + } + + return 0; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/memheap/drv_mmheap.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/memheap/drv_mmheap.h new file mode 100644 index 0000000000000000000000000000000000000000..df76969fb769e37e05f5ccf6edb481bf69a3708b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/memheap/drv_mmheap.h @@ -0,0 +1,194 @@ +/** + * @file drv_mmheap.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _DRV_MMHEAP_H_ +#define _DRV_MMHEAP_H_ + +#include "stdint.h" +#include "string.h" + +#define MEMHEAP_STATUS_OK 0 +#define MEMHEAP_STATUS_INVALID_ADDR -1 +#define MEMHEAP_STATUS_INVALID_SIZE -2 +#define MEMHEAP_STATUS_OVERFLOW -3 +#define MEMHEAP_STATUS_ALREADY_NOT_EXIST -4 +#define MEMHEAP_STATUS_ALREADY_EXIST -5 + +/** + * log2 of number of linear subdivisions of block sizes. Larger + * values require more memory in the control structure. Values of + * 4 or 5 are typical. + */ +#define MMHEAP_SL_INDEX_COUNT_LOG2 5 + +/* All allocation sizes and addresses are aligned to 4 bytes. */ +#define MMHEAP_ALIGN_SIZE_LOG2 2 +#define MMHEAP_ALIGN_SIZE (1 << MMHEAP_ALIGN_SIZE_LOG2) + +/* + * We support allocations of sizes up to (1 << MMHEAP_FL_INDEX_MAX) bits. + * However, because we linearly subdivide the second-level lists, and + * our minimum size granularity is 4 bytes, it doesn't make sense to + * create first-level lists for sizes smaller than MMHEAP_SL_INDEX_COUNT * 4, + * or (1 << (K_MMHEAP_SL_INDEX_COUNT_LOG2 + 2)) bytes, as there we will be + * trying to split size ranges into more slots than we have available. + * Instead, we calculate the minimum threshold size, and place all + * blocks below that size into the 0th first-level list. + */ +#define MMHEAP_FL_INDEX_MAX 30 +#define MMHEAP_SL_INDEX_COUNT (1 << MMHEAP_SL_INDEX_COUNT_LOG2) +#define MMHEAP_FL_INDEX_SHIFT (MMHEAP_SL_INDEX_COUNT_LOG2 + MMHEAP_ALIGN_SIZE_LOG2) +#define MMHEAP_FL_INDEX_COUNT (MMHEAP_FL_INDEX_MAX - MMHEAP_FL_INDEX_SHIFT + 1) + +#define MMHEAP_SMALL_BLOCK_SIZE (1 << MMHEAP_FL_INDEX_SHIFT) + +#define MMHEAP_BLOCK_CURR_FREE (1 << 0) +#define MMHEAP_BLOCK_PREV_FREE (1 << 1) +#define MMHEAP_BLOCK_SIZE_MASK ~(MMHEAP_BLOCK_CURR_FREE | MMHEAP_BLOCK_PREV_FREE) +#define MMHEAP_BLOCK_STATE_MASK (MMHEAP_BLOCK_CURR_FREE | MMHEAP_BLOCK_PREV_FREE) + +typedef struct +{ + uint32_t used; /* space is used */ + uint32_t free; /* space is free */ +} mmheap_info_t; + +/** + * Block structure. + * + * There are several implementation subtleties involved: + * - The prev_phys_block field is only valid if the previous block is free. + * - The prev_phys_block field is actually stored at the end of the + * previous block. It appears at the beginning of this structure only to + * simplify the implementation. + * - The next_free / prev_free fields are only valid if the block is free. + */ +typedef struct mmheap_blk_st { + struct mmheap_blk_st *prev_phys_blk; + + size_t size; + + struct mmheap_blk_st *next_free; + struct mmheap_blk_st *prev_free; +} mmheap_blk_t; + +/** + * A free block must be large enough to store its header minus the size of + * the prev_phys_block field, and no larger than the number of addressable + * bits for FL_INDEX. + */ +#define MMHEAP_BLK_SIZE_MIN (sizeof(mmheap_blk_t) - sizeof(mmheap_blk_t *)) +#define MMHEAP_BLK_SIZE_MAX (1 << MMHEAP_FL_INDEX_MAX) + +#define MMHEAP_BLK_HEADER_OVERHEAD (sizeof(size_t)) +#define MMHEAP_BLK_START_OFFSET (((uint32_t)(uintptr_t) & (((mmheap_blk_t *)0)->size)) + sizeof(size_t)) + +#define MMHEAP_POOL_MAX 3 + +/** + * memory heap control + */ +typedef struct +{ + int pool_cnt; + void *pool_start[MMHEAP_POOL_MAX]; + + mmheap_blk_t block_null; /**< Empty lists point at this block to indicate they are free. */ + + uint32_t fl_bitmap; /**< Bitmaps for free lists. */ + uint32_t sl_bitmap[MMHEAP_FL_INDEX_COUNT]; + + mmheap_blk_t *blocks[MMHEAP_FL_INDEX_COUNT][MMHEAP_SL_INDEX_COUNT]; /**< Head of free lists. */ +} mmheap_ctl_t; + +/** + * @brief Add a pool. + * Add addtional pool to the heap. + * + * @attention None + * + * @param[in] pool_start start address of the pool. + * @param[in] pool_size size of the pool. + * + * @return errcode + */ +int mmheap_pool_add(void *pool_start, size_t pool_size); + +/** + * @brief Alloc memory. + * Allocate size bytes and returns a pointer to the allocated memory. + * + * @attention size should no bigger than MMHEAP_BLK_SIZE_MAX. + * + * @param[in] size size of the memory. + * + * @return the pointer to the allocated memory. + */ +void *mmheap_alloc(size_t size); + +void *mmheap_calloc(size_t num, size_t size); + +/** + * @brief Alloc start address aligned memory from the heap. + * Alloc aligned address and specified size memory from the heap. + * + * @attention + * + * @param[in] size size of the memory. + * @param[in] align address align mask of the memory. + * + * @return the pointer to the allocated memory. + */ +void *mmheap_aligned_alloc(size_t size, size_t align); + +/** + * @brief Realloc memory from the heap. + * Change the size of the memory block pointed to by ptr to size bytes. + * + * @attention + *
    + *
  • if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size. + *
  • if ptr is if size is equal to zero, and ptr is not K_NULL, then the call is equivalent to mmheap_free(ptr). + *
+ * + * @param[in] ptr old pointer to the memory space. + * @param[in] size new size of the memory space. + * + * @return the new pointer to the allocated memory. + */ +void *mmheap_realloc(void *ptr, size_t size); + +/** + * @brief Free the memory. + * Free the memory space pointed to by ptr, which must have been returned by a previous call to mmheap_alloc(), mmheap_aligned_alloc(), or mmheap_realloc(). + * + * @attention + * + * @param[in] ptr pointer to the memory. + * + * @return None. + */ +void mmheap_free(void *ptr); + +int mmheap_init_with_pool(void *pool_start, size_t pool_size); + +#endif /* _DRV_MMHEAP_H_ */ \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/gcc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..807e1dcacc9dd49035aeff307179a532d56d898c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/gcc.h @@ -0,0 +1,80 @@ +/** + * @file gcc.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _GCC_H +#define _GCC_H + +/*------------------ RealView Compiler -----------------*/ +#if defined(__GNUC__) + +#define __ASM__ __asm +#define __VOLATILE__ volatile + +#define __INLINE__ inline +#define __STATIC__ static +#define __STATIC_INLINE__ static inline + +#ifndef likely +#define likely(x) __builtin_expect(!!(x), 1) +#endif +#ifndef likely +#define unlikely(x) __builtin_expect(!!(x), 0) +#endif +#define __UNUSED__ __attribute__((__unused__)) +#define __USED__ __attribute__((__used__)) +#define __PACKED__ __attribute__((packed)) +#define __ALIGNED__(x) __attribute__((aligned(x))) +#define __PURE__ __attribute__((__pure__)) +#define __CONST__ __attribute__((__const__)) +#define __NO_RETURN__ __attribute__((__noreturn__)) +#define __NAKED__ __attribute__((naked)) +#define __WEAK__ __attribute__((weak)) +#define SECTION(x) __attribute__((section(x))) +#define __API__ __declspec(dllexport) + +#endif + +#ifdef __GNUC__ + +#define WARN_UNUSED_RET __attribute__((warn_unused_result)) +#define WEAK __attribute__((weak)) + +#ifndef PACK_START +#define PACK_START +#endif +#ifndef PACK_END +#define PACK_END __attribute__((packed)) +#endif +#define NORETURN __attribute__((noreturn)) + +#else /* __GNUC__ */ + +#define WARN_UNUSED_RET +#define WEAK __weak + +#define PACK_START __packed +#define PACK_END +#define NORETURN + +#endif /* __GNUC__ */ + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/misc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/misc.c new file mode 100644 index 0000000000000000000000000000000000000000..bffa5fae5d116d45ad18c8ca736369fab70d5a2b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/misc.c @@ -0,0 +1,219 @@ +/** + * @file misc.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "misc.h" + +#ifndef BFLB_USE_ROM_DRIVER +/****************************************************************************/ /** + * @brief Char memcpy + * + * @param dst: Destination + * @param src: Source + * @param n: Count of char + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ +void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n) +{ + const uint8_t *p = src; + uint8_t *q = dst; + + while (n--) { + *q++ = *p++; + } + + return dst; +} + +/****************************************************************************/ /** + * @brief Word memcpy + * + * @param dst: Destination + * @param src: Source + * @param n: Count of words + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ +uint32_t *ATTR_TCM_SECTION arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n) +{ + const uint32_t *p = src; + uint32_t *q = dst; + + while (n--) { + *q++ = *p++; + } + + return dst; +} + +/****************************************************************************/ /** + * @brief Fast memcpy + * + * @param dst: Destination + * @param src: Source + * @param n: Count of bytes + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ +void *ATTR_TCM_SECTION arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n) +{ + uint32_t left, done, i = 0; + uint8_t *dst = (uint8_t *)pdst; + uint8_t *src = (uint8_t *)psrc; + + if (((uint32_t)(uintptr_t)dst & 0x3) == 0 && ((uint32_t)(uintptr_t)src & 0x3) == 0) { + arch_memcpy4((uint32_t *)dst, (const uint32_t *)src, n >> 2); + left = n % 4; + done = n - left; + + while (i < left) { + dst[done + i] = src[done + i]; + i++; + } + } else { + arch_memcpy(dst, src, n); + } + + return dst; +} + +/****************************************************************************/ /** + * @brief char memset + * + * @param dst: Destination + * @param val: Value to set + * @param n: Count of char + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ +void *ATTR_TCM_SECTION arch_memset(void *s, uint8_t c, uint32_t n) +{ + uint8_t *p = (uint8_t *)s; + + while (n > 0) { + *p++ = (uint8_t)c; + --n; + } + + return s; +} +/****************************************************************************/ /** + * @brief Word memset + * + * @param dst: Destination + * @param val: Value to set + * @param n: Count of words + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ +uint32_t *ATTR_TCM_SECTION arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n) +{ + uint32_t *q = dst; + + while (n--) { + *q++ = val; + } + + return dst; +} + +/****************************************************************************/ /** + * @brief string compare + * + * @param s1: string 1 + * @param s2: string 2 + * @param n: Count of chars + * + * @return compare result + * + *******************************************************************************/ +__WEAK__ +int ATTR_TCM_SECTION arch_memcmp(const void *s1, const void *s2, uint32_t n) +{ + const unsigned char *c1 = s1, *c2 = s2; + int d = 0; + + while (n--) { + d = (int)*c1++ - (int)*c2++; + + if (d) { + break; + } + } + + return d; +} +#endif + +void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length) +{ + uint8_t *p = (uint8_t *)fifo_addr; + uint8_t *q = data; + + while (length--) { + *p = *q++; + } +} + +void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length) +{ + uint8_t *p = (uint8_t *)fifo_addr; + uint8_t *q = data; + + while (length--) { + *q++ = *p; + } +} + +#ifdef DEBUG +/******************************************************************************* +* @brief Reports the name of the source file and the source line number +* where the CHECK_PARAM error has occurred. + +* @param file: Pointer to the source file name +* @param line: assert_param error line source number + +* @return None +*******************************************************************************/ +void check_failed(uint8_t *file, uint32_t line) +{ + /* Infinite loop */ + while (1) + ; +} +#endif /* DEBUG */ + +/*@} end of group DRIVER_Public_Functions */ + +/*@} end of group DRIVER_COMMON */ + +/*@} end of group BL602_Periph_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/misc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/misc.h new file mode 100644 index 0000000000000000000000000000000000000000..c4d4dd881ff621135c8bc83e3290fb0d96f4b601 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/misc/misc.h @@ -0,0 +1,210 @@ +/** + * @file misc.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _MISC_H +#define _MISC_H + +#include +#include +#include +#include +#include +#include +#include "gcc.h" +#include "cmsis_compatible_gcc.h" + +/*@} end of group COMMON_Public_Types */ + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** + * @brief Memory access macro + */ +#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr))) +#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr))) +#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr))) +#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val)) +#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) + +#define BL_WRWD_TO_BYTEP(p, val) \ + { \ + p[0] = val & 0xff; \ + p[1] = (val >> 8) & 0xff; \ + p[2] = (val >> 16) & 0xff; \ + p[3] = (val >> 24) & 0xff; \ + } +/** + * @brief Register access macro + */ +#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) +#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val) +#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) +#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) +#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) +#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK) +#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) +#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) +#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) +#define BL_DRV_DUMMY \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/* Std driver attribute macro*/ +#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code"))) +#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const"))) +#define ATTR_TCM_SECTION __attribute__((section(".tcm_code"))) +#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const"))) +#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data"))) +#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code"))) +#define ATTR_DMA_RAM_SECTION __attribute__((section(".system_ram"))) +#define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code"))) +#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_ram_data"))) +#define ATTR_EALIGN(x) __attribute((aligned(x))) +#define ATTR_FALLTHROUGH() __attribute__((fallthrough)) +#define ATTR_USED __attribute__((__used__)) + +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +/** + * @brief Error type definition + */ +typedef enum { + SUCCESS = 0, + ERROR = 1, + TIMEOUT = 2, + INVALID = 3, /* invalid arguments */ + NORESC = 4 /* no resource or resource temperary unavailable */ +} BL_Err_Type; + +/** + * @brief Functional type definition + */ +typedef enum { + DISABLE = 0, + ENABLE = 1, +} BL_Fun_Type; + +/** + * @brief Status type definition + */ +typedef enum { + RESET = 0, + SET = 1, +} BL_Sts_Type; + +/** + * @brief Mask type definition + */ +typedef enum { + UNMASK = 0, + MASK = 1 +} BL_Mask_Type; + +/** + * @brief Logical status Type definition + */ +typedef enum { + LOGIC_LO = 0, + LOGIC_HI = !LOGIC_LO +} LogicalStatus; + +/** + * @brief Active status Type definition + */ +typedef enum { + DEACTIVE = 0, + ACTIVE = !DEACTIVE +} ActiveStatus; + +/** + * @brief Interrupt callback function type + */ +typedef void(intCallback_Type)(void); +typedef void (*pFunc)(void); + +/** + * @brief Null Type definition + */ +#ifndef NULL +#define NULL 0 +#endif + +/*@} end of group COMMON_Public_Constants */ + +/** @defgroup COMMON_Public_Macros + * @{ + */ + +#define BL602_MemCpy arch_memcpy +#define BL602_MemSet arch_memset +#define BL602_MemCmp arch_memcmp +#define BL602_MemCpy4 arch_memcpy4 +#define BL602_MemCpy_Fast arch_memcpy_fast +#define BL602_MemSet4 arch_memset4 + +#define BL702_MemCpy arch_memcpy +#define BL702_MemSet arch_memset +#define BL702_MemCmp arch_memcmp +#define BL702_MemCpy4 arch_memcpy4 +#define BL702_MemCpy_Fast arch_memcpy_fast +#define BL702_MemSet4 arch_memset4 + +#define ARCH_MemCpy_Fast arch_memcpy_fast + +/** + * @brief Null Type definition + */ +#ifndef NULL +#define NULL 0 +#endif + +/*@} end of group DRIVER_Public_Macro */ + +/** @defgroup DRIVER_Public_FunctionDeclaration + * @brief DRIVER functions declaration + * @{ + */ +void *arch_memcpy(void *dst, const void *src, uint32_t n); +void *arch_memset(void *s, uint8_t c, uint32_t n); +int arch_memcmp(const void *s1, const void *s2, uint32_t n); +uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n); +void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n); +uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n); +void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length); +void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length); + +/*@} end of group DRIVER_COMMON */ + +#endif /* __BL602_COMMON_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/partition/partition.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/partition/partition.c new file mode 100644 index 0000000000000000000000000000000000000000..673dcbe88ba9a16acd2cfde6885bb0583f1990a3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/partition/partition.c @@ -0,0 +1,544 @@ +/** + ****************************************************************************** + * @file partition.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "partition.h" +#include "softcrc.h" +#include "bflb_platform.h" + +/** @addtogroup BFLB_Common_Driver + * @{ + */ + +/** @addtogroup PARTITION + * @{ + */ + +/** @defgroup PARTITION_Private_Macros + * @{ + */ + +/*@} end of group PARTITION_Private_Macros */ + +/** @defgroup PARTITION_Private_Types + * @{ + */ + +/*@} end of group PARTITION_Private_Types */ + +/** @defgroup PARTITION_Private_Variables + * @{ + */ +p_pt_table_flash_erase gp_pt_table_flash_erase = NULL; +p_pt_table_flash_write gp_pt_table_flash_write = NULL; +p_pt_table_flash_read gp_pt_table_flash_read = NULL; +pt_table_iap_param_type p_iap_param; + +/*@} end of group PARTITION_Private_Variables */ + +/** @defgroup PARTITION_Global_Variables + * @{ + */ +extern int main(void); + +/*@} end of group PARTITION_Global_Variables */ + +/** @defgroup PARTITION_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PARTITION_Private_Fun_Declaration */ + +/** @defgroup PARTITION_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Judge partition table valid + * + * @param ptStuff: Partition table stuff pointer + * + * @return 0 for invalid and 1 for valid + * +*******************************************************************************/ +static uint8_t pt_table_valid(pt_table_stuff_config *pt_stuff) +{ + pt_table_config *pt_table = &pt_stuff->pt_table; + pt_table_entry_config *pt_entries = pt_stuff->pt_entries; + uint32_t *p_crc32; + uint32_t entriesLen = sizeof(pt_table_entry_config) * pt_table->entryCnt; + + if (pt_table->magicCode == BFLB_PT_MAGIC_CODE) { + if (pt_table->entryCnt > PT_ENTRY_MAX) { + MSG("PT Entry Count Error\r\n"); + return 0; + } + + if (pt_table->crc32 != + BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4)) { + MSG("PT CRC Error\r\n"); + return 0; + } + + /* ToDo it is a trap here, when entryCnt > 8, crc32 will overflow, comment by zhangcheng */ + p_crc32 = (uint32_t *)((uintptr_t)pt_entries + entriesLen); + + if (*p_crc32 != BFLB_Soft_CRC32((uint8_t *)pt_entries, entriesLen)) { + MSG("PT Entry CRC Error\r\n"); + return 0; + } + + return 1; + } + + return 0; +} + +/*@} end of group PARTITION_Private_Functions */ + +/** @defgroup PARTITION_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Register partition flash read write erase fucntion + * + * @param erase: Flash erase function + * @param write: Flash write function + * @param read: Flash read function + * + * @return None + * +*******************************************************************************/ +void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read) +{ + gp_pt_table_flash_erase = erase; + gp_pt_table_flash_write = write; + gp_pt_table_flash_read = read; +} + +/****************************************************************************/ /** + * @brief Get active partition table whole stuff + * + * @param ptStuff[2]: Partition table stuff pointer + * + * @return Active partition table ID + * +*******************************************************************************/ +pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]) +{ + uint32_t pt_valid[2] = { 0, 0 }; + pt_table_id_type activePtID; + + if (ptStuff == NULL) { + return PT_TABLE_ID_INVALID; + } + + activePtID = PT_TABLE_ID_INVALID; + + gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&ptStuff[0], sizeof(pt_table_stuff_config)); + pt_valid[0] = pt_table_valid(&ptStuff[0]); + + gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&ptStuff[1], sizeof(pt_table_stuff_config)); + pt_valid[1] = pt_table_valid(&ptStuff[1]); + + if (pt_valid[0] == 1 && pt_valid[1] == 1) { + if (ptStuff[0].pt_table.age >= ptStuff[1].pt_table.age) { + activePtID = PT_TABLE_ID_0; + } else { + activePtID = PT_TABLE_ID_1; + } + } else if (pt_valid[0] == 1) { + activePtID = PT_TABLE_ID_0; + } else if (pt_valid[1] == 1) { + activePtID = PT_TABLE_ID_1; + } + + return activePtID; +} + +/****************************************************************************/ /** + * @brief Get partition entry according to entry ID + * + * @param ptStuff: Partition table stuff pointer + * @param type: Type of partition entry + * @param ptEntry: Partition entry pointer to store read data + * + * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER + * +*******************************************************************************/ +pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, + pt_table_entry_type type, + pt_table_entry_config *pt_entry) +{ + uint32_t i = 0; + + if (pt_stuff == NULL || pt_entry == NULL) { + return PT_ERROR_PARAMETER; + } + + for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { + if (pt_stuff->pt_entries[i].type == type) { + ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); + return PT_ERROR_SUCCESS; + } + } + + return PT_ERROR_ENTRY_NOT_FOUND; +} + +/****************************************************************************/ /** + * @brief Get partition entry according to entry name + * + * @param ptStuff: Partition table stuff pointer + * @param name: Name of partition entry + * @param ptEntry: Partition entry pointer to store read data + * + * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER + * +*******************************************************************************/ +pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, + uint8_t *name, + pt_table_entry_config *pt_entry) +{ + uint32_t i = 0; + uint32_t len = strlen((char *)name); + + if (pt_stuff == NULL || pt_entry == NULL) { + return PT_ERROR_PARAMETER; + } + + for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { + if (strlen((char *)pt_stuff->pt_entries[i].name) == len && + memcmp((char *)pt_stuff->pt_entries[i].name, (char *)name, len) == 0) { + ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); + return PT_ERROR_SUCCESS; + } + } + + return PT_ERROR_ENTRY_NOT_FOUND; +} + +/****************************************************************************/ /** + * @brief Update partition entry + * + * @param targetTableID: Target partition table to update + * @param ptStuff: Partition table stuff pointer + * @param ptEntry: Partition entry pointer to update + * + * @return Partition update result + * +*******************************************************************************/ +pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, + pt_table_stuff_config *pt_stuff, + pt_table_entry_config *pt_entry) +{ + uint32_t i = 0; + BL_Err_Type ret; + uint32_t write_addr; + uint32_t entries_len; + pt_table_config *pt_table; + pt_table_entry_config *pt_entries; + uint32_t *crc32; + + if (pt_entry == NULL || pt_stuff == NULL) { + return PT_ERROR_PARAMETER; + } + + pt_table = &pt_stuff->pt_table; + pt_entries = pt_stuff->pt_entries; + + if (target_table_id == PT_TABLE_ID_INVALID) { + return PT_ERROR_TABLE_NOT_VALID; + } + + if (target_table_id == PT_TABLE_ID_0) { + write_addr = BFLB_PT_TABLE0_ADDRESS; + } else { + write_addr = BFLB_PT_TABLE1_ADDRESS; + } + + for (i = 0; i < pt_table->entryCnt; i++) { + if (pt_entries[i].type == pt_entry->type) { + ARCH_MemCpy_Fast(&pt_entries[i], pt_entry, sizeof(pt_table_entry_config)); + break; + } + } + + if (i == pt_table->entryCnt) { + /* Not found this entry ,add new one */ + if (pt_table->entryCnt < PT_ENTRY_MAX) { + ARCH_MemCpy_Fast(&pt_entries[pt_table->entryCnt], pt_entry, sizeof(pt_table_entry_config)); + pt_table->entryCnt++; + } else { + return PT_ERROR_ENTRY_UPDATE_FAIL; + } + } + + /* Prepare write back to flash */ + /* Update age */ + pt_table->age++; + pt_table->crc32 = BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4); + + /* Update entries CRC */ + entries_len = pt_table->entryCnt * sizeof(pt_table_entry_config); + crc32 = (uint32_t *)((uintptr_t)pt_entries + entries_len); + *crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_entries[0], entries_len); + + /* Write back to flash */ + /* Erase flash first */ + //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) + entries_len + 4 - 1); + ret = gp_pt_table_flash_erase(write_addr, sizeof(pt_table_config) + entries_len + 4); + + if (ret != SUCCESS) { + MSG_ERR("Flash Erase error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + + /* Write flash */ + ret = gp_pt_table_flash_write(write_addr, (uint8_t *)pt_stuff, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Write error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + + return PT_ERROR_SUCCESS; +} + +/****************************************************************************/ /** + * @brief Create partition entry + * + * @param ptID: Partition table ID + * + * @return Partition create result + * +*******************************************************************************/ +pt_table_error_type pt_table_create(pt_table_id_type pt_id) +{ + uint32_t write_addr; + BL_Err_Type ret; + pt_table_config pt_table; + + if (pt_id == PT_TABLE_ID_INVALID) { + return PT_ERROR_TABLE_NOT_VALID; + } + + if (pt_id == PT_TABLE_ID_0) { + write_addr = BFLB_PT_TABLE0_ADDRESS; + } else { + write_addr = BFLB_PT_TABLE1_ADDRESS; + } + + /* Prepare write back to flash */ + pt_table.magicCode = BFLB_PT_MAGIC_CODE; + pt_table.version = 0; + pt_table.entryCnt = 0; + pt_table.age = 0; + pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_table, sizeof(pt_table_config) - 4); + /* Write back to flash */ + //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) - 1); + ret = gp_pt_table_flash_erase(write_addr,sizeof(pt_table_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Erase error\r\n"); + return PT_ERROR_FALSH_ERASE; + } + + ret = gp_pt_table_flash_write(write_addr, (uint8_t *)&pt_table, sizeof(pt_table_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Write error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + + return PT_ERROR_SUCCESS; +} + +pt_table_error_type pt_table_dump(void) +{ + uint32_t pt_valid[2] = { 0, 0 }; + pt_table_stuff_config pt_stuff[2]; + + gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); + pt_valid[0] = pt_table_valid(&pt_stuff[0]); + + gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); + pt_valid[1] = pt_table_valid(&pt_stuff[1]); + + if (pt_valid[0]) { + MSG("PT TABLE0 valid\r\n"); + } else { + MSG("PT TABLE0 invalid\r\n"); + } + + if (pt_valid[1]) { + MSG("PT TABLE1 valid\r\n"); + } else { + MSG("PT TABLE1 invalid\r\n"); + } + + for (int i = 0; i < 2; i++) { + if (pt_valid[i] == 1) { + MSG("ptStuff[%d].pt_table.magicCode 0x%08x\r\n", i, pt_stuff[i].pt_table.magicCode); + MSG("ptStuff[%d].pt_table.version 0x%08x\r\n", i, pt_stuff[i].pt_table.version); + MSG("ptStuff[%d].pt_table.entryCnt 0x%08x\r\n", i, pt_stuff[i].pt_table.entryCnt); + MSG("ptStuff[%d].pt_table.age 0x%08x\r\n", i, pt_stuff[i].pt_table.age); + MSG("ptStuff[%d].pt_table.crc32 0x%08x\r\n", i, pt_stuff[i].pt_table.crc32); + + for (int j = 0; j < pt_stuff[i].pt_table.entryCnt; j++) { + MSG("ptStuff[%d].pt_entries[%d].type 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].type); + MSG("ptStuff[%d].pt_entries[%d].device 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].device); + MSG("ptStuff[%d].pt_entries[%d].active_index 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].active_index); + MSG("ptStuff[%d].pt_entries[%d].Address[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[0]); + MSG("ptStuff[%d].pt_entries[%d].Address[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[1]); + MSG("ptStuff[%d].pt_entries[%d].maxLen[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[0]); + MSG("ptStuff[%d].pt_entries[%d].maxLen[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[1]); + MSG("ptStuff[%d].pt_entries[%d].len 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].len); + MSG("ptStuff[%d].pt_entries[%d].age 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].age); + } + } + } + + return PT_ERROR_SUCCESS; +} + +pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para) +{ + uint32_t pt_valid[2] = { 0, 0 }; + pt_table_stuff_config pt_stuff[2]; + uint8_t active_index; + + gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); + pt_valid[0] = pt_table_valid(&pt_stuff[0]); + + gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); + pt_valid[1] = pt_table_valid(&pt_stuff[1]); + + if ((pt_valid[0] == 1) && (pt_valid[1] == 1)) { + if (pt_stuff[0].pt_table.age >= pt_stuff[1].pt_table.age) { + active_index = pt_stuff[0].pt_entries[0].active_index; + para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; + para->inactive_index = !(active_index & 0x01); + para->inactive_table_index = 1; + + } else { + active_index = pt_stuff[1].pt_entries[0].active_index; + para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; + para->inactive_index = !(active_index & 0x01); + para->inactive_table_index = 0; + } + + } else if (pt_valid[1] == 1) { + active_index = pt_stuff[1].pt_entries[0].active_index; + para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; + para->inactive_index = !(active_index & 0x01); + para->inactive_table_index = 0; + } else if (pt_valid[0] == 1) { + active_index = pt_stuff[0].pt_entries[0].active_index; + para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; + para->inactive_index = !(active_index & 0x01); + para->inactive_table_index = 1; + } else { + return PT_ERROR_TABLE_NOT_VALID; + } + + MSG("inactive_table_index %d, inactive index %d , IAP start addr %08x \r\n", para->inactive_table_index, para->inactive_index, para->iap_start_addr); + return PT_ERROR_SUCCESS; +} + +pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para) +{ + pt_table_stuff_config pt_stuff, pt_stuff_write; + int32_t ret; + uint32_t *p_crc32; + uint32_t entries_len; + + if (para->inactive_table_index == 1) { + gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); + } else if (para->inactive_table_index == 0) { + gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); + } + + ARCH_MemCpy_Fast((void *)&pt_stuff_write, (void *)&pt_stuff, sizeof(pt_table_stuff_config)); + pt_stuff_write.pt_table.age += 1; + pt_stuff_write.pt_entries[0].active_index = !(pt_stuff_write.pt_entries[0].active_index & 0x01); + pt_stuff_write.pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_stuff_write, sizeof(pt_table_config) - 4); + entries_len = sizeof(pt_table_entry_config) * pt_stuff_write.pt_table.entryCnt; + //pt_stuff_write.crc32 = BFLB_Soft_CRC32((uint8_t*)pt_stuff_write.pt_entries,entries_len); + p_crc32 = (uint32_t *)((uintptr_t)pt_stuff_write.pt_entries + entries_len); + *p_crc32 = BFLB_Soft_CRC32((uint8_t *)pt_stuff_write.pt_entries, entries_len); + + if (para->inactive_table_index == 1) { + //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, BFLB_PT_TABLE1_ADDRESS + sizeof(pt_table_stuff_config) - 1); + ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Erase error\r\n"); + return PT_ERROR_FALSH_ERASE; + } + + ret = gp_pt_table_flash_write(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Write error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + } else if (para->inactive_table_index == 0) { + //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, BFLB_PT_TABLE0_ADDRESS + sizeof(pt_table_stuff_config) - 1); + ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Erase error\r\n"); + return PT_ERROR_FALSH_ERASE; + } + + ret = gp_pt_table_flash_write(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Write error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + } + + MSG("Update pt_table suss\r\n"); + return PT_ERROR_SUCCESS; +} + +/*@} end of group PARTITION_Public_Functions */ + +/*@} end of group PARTITION */ + +/*@} end of group BFLB_Common_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/partition/partition.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/partition/partition.h new file mode 100644 index 0000000000000000000000000000000000000000..9446436c0728217f7196a9280f412ac01aa218ca --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/partition/partition.h @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file partition.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PARTITION_H__ +#define __PARTITION_H__ + +#include "stdint.h" +#include "string.h" +#include "misc.h" +//#include "bflb_bsp_driver_glue.h" + +/** @addtogroup BFLB_Common_Driver + * @{ + */ + +/** @addtogroup PARTITION + * @{ + */ + +/** @defgroup PARTITION_Public_Types + * @{ + */ + +/** + * @brief Partition table error type definition + */ +typedef enum { + PT_ERROR_SUCCESS, /*!< Partition table error type:success */ + PT_ERROR_TABLE_NOT_VALID, /*!< Partition table error type:table not found */ + PT_ERROR_ENTRY_NOT_FOUND, /*!< Partition table error type:entry not found */ + PT_ERROR_ENTRY_UPDATE_FAIL, /*!< Partition table error type:entry update fail */ + PT_ERROR_CRC32, /*!< Partition table error type:crc32 error */ + PT_ERROR_PARAMETER, /*!< Partition table error type:input parameter error */ + PT_ERROR_FALSH_READ, /*!< Partition table error type:flash read error */ + PT_ERROR_FALSH_WRITE, /*!< Partition table error type:flash write error */ + PT_ERROR_FALSH_ERASE, /*!< Partition table error type:flash erase error */ +} pt_table_error_type; + +/** + * @brief Partition id type definition + */ +typedef enum { + PT_TABLE_ID_0, /*!< Partition table ID 0 */ + PT_TABLE_ID_1, /*!< Partition table ID 1 */ + PT_TABLE_ID_INVALID, /*!< Partition table ID invalid */ +} pt_table_id_type; + +/** + * @brief Partition id type definition + */ +typedef enum { + PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ + PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ + PT_ENTRY_MAX = 16, /*!< Partition entry type:Max */ +} pt_table_entry_type; + +/** + * @brief Partition table config definition + */ +typedef struct +{ + uint32_t magicCode; /*!< Partition table magic code */ + uint16_t version; /*!< Partition table verdion */ + uint16_t entryCnt; /*!< Partition table entry count */ + uint32_t age; /*!< Partition table age */ + uint32_t crc32; /*!< Partition table CRC32 value */ +} pt_table_config; + +/** + * @brief Partition table entry config definition + */ +typedef struct +{ + uint8_t type; /*!< Partition entry type */ + uint8_t device; /*!< Partition entry device */ + uint8_t active_index; /*!< Partition entry active index */ + uint8_t name[9]; /*!< Partition entry name */ + uint32_t start_address[2]; /*!< Partition entry start address */ + uint32_t max_len[2]; /*!< Partition entry max length */ + uint32_t len; /*!< Partition entry length */ + uint32_t age; /*!< Partition entry age */ +} pt_table_entry_config; + +/** + * @brief Partition table stuff config definition + */ +typedef struct +{ + pt_table_config pt_table; /*!< Partition table */ + pt_table_entry_config pt_entries[PT_ENTRY_MAX]; /*!< Partition entries */ + uint32_t crc32; /*!< Partition entries crc32 */ +} pt_table_stuff_config; + +/** + * @brief Partition table iap param definition + */ +typedef struct +{ + uint32_t iap_start_addr; + uint32_t iap_write_addr; + uint32_t iap_img_len; + uint8_t inactive_index; + uint8_t inactive_table_index; +} pt_table_iap_param_type; + +/*@} end of group PARTITION_Public_Types */ + +/** @defgroup PARTITION_Public_Constants + * @{ + */ + +/** @defgroup pt_table_error_type + * @{ + */ +#define IS_PTTABLE_ERROR_TYPE(type) (((type) == PT_ERROR_SUCCESS) || \ + ((type) == PT_ERROR_TABLE_NOT_VALID) || \ + ((type) == PT_ERROR_ENTRY_NOT_FOUND) || \ + ((type) == PT_ERROR_ENTRY_UPDATE_FAIL) || \ + ((type) == PT_ERROR_CRC32) || \ + ((type) == PT_ERROR_PARAMETER) || \ + ((type) == PT_ERROR_FALSH_READ) || \ + ((type) == PT_ERROR_FALSH_WRITE) || \ + ((type) == PT_ERROR_FALSH_ERASE)) + +/** @defgroup pt_table_id_type + * @{ + */ +#define IS_PTTABLE_ID_TYPE(type) (((type) == PT_TABLE_ID_0) || \ + ((type) == PT_TABLE_ID_1) || \ + ((type) == PT_TABLE_ID_INVALID)) + +/** @defgroup pt_table_entry_type + * @{ + */ +#define IS_PTTABLE_ENTRY_TYPE(type) (((type) == PT_ENTRY_FW_CPU0) || \ + ((type) == PT_ENTRY_FW_CPU1) || \ + ((type) == PT_ENTRY_MAX)) + +/*@} end of group PARTITION_Public_Constants */ + +/** @defgroup PARTITION_Public_Macros + * @{ + */ +#define BFLB_PT_TABLE0_ADDRESS 0xE000 +#define BFLB_PT_TABLE1_ADDRESS 0xF000 +#define BFLB_PT_MAGIC_CODE 0x54504642 +typedef BL_Err_Type (*p_pt_table_flash_erase)(uint32_t startaddr, uint32_t endaddr); +typedef BL_Err_Type (*p_pt_table_flash_write)(uint32_t addr, uint8_t *data, uint32_t len); +typedef BL_Err_Type (*p_pt_table_flash_read)(uint32_t addr, uint8_t *data, uint32_t len); + +/*@} end of group PARTITION_Public_Macros */ + +/** @defgroup PARTITION_Public_Functions + * @{ + */ +void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read); +pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]); +pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, + pt_table_entry_type type, + pt_table_entry_config *pt_entry); +pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, + uint8_t *name, + pt_table_entry_config *pt_entry); +pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, + pt_table_stuff_config *pt_stuff, + pt_table_entry_config *pt_entry); +pt_table_error_type pt_table_create(pt_table_id_type pt_id); +pt_table_error_type pt_table_dump(void); +pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para); +pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para); + +/*@} end of group PARTITION_Public_Functions */ + +/*@} end of group PARTITION */ + +/*@} end of group BFLB_Common_Driver */ + +extern pt_table_iap_param_type p_iap_param; + +#endif /* __PARTITION_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/pid/pid.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/pid/pid.c new file mode 100644 index 0000000000000000000000000000000000000000..c7d6da85939c5d45d078fdc4b56cde96cdda553e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/pid/pid.c @@ -0,0 +1,68 @@ +/** + * @file pid.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "pid.h" + +void pid_init(pid_alg_t *pid) +{ + pid->set_val = 0.0f; + pid->out_val = 0.0f; + + pid->last_error = 0.0f; + pid->prev_error = 0.0f; + + pid->kp = 3.0f; + pid->ki = 0.0f; + pid->kd = 0.0f; + + pid->i_error = 0.0f; + pid->sum_error = 0.0f; + + pid->max_val = 32; + pid->min_val = -32; +} + +// standard pid +float standard_pid_cal(pid_alg_t *pid, float next_val) +{ + pid->set_val = next_val; + pid->i_error = pid->set_val - pid->out_val; + pid->sum_error += pid->i_error; + pid->out_val = pid->kp * pid->i_error + pid->ki * pid->sum_error + pid->kd * (pid->i_error - pid->last_error); + pid->last_error = pid->i_error; + + return pid->out_val; +} + +// increment pid +float increment_pid_cal(pid_alg_t *pid, float next_val) +{ + pid->set_val = next_val; + pid->i_error = pid->set_val - pid->out_val; + float increment = pid->kp * (pid->i_error - pid->prev_error) + pid->ki * pid->i_error + pid->kd * (pid->i_error - 2 * pid->prev_error + pid->last_error); + pid->out_val += increment; + pid->last_error = pid->prev_error; + pid->prev_error = pid->i_error; + + return pid->out_val; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/pid/pid.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/pid/pid.h new file mode 100644 index 0000000000000000000000000000000000000000..afbaddd11c70bc03cd6660a6500bf4b8c437b194 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/pid/pid.h @@ -0,0 +1,50 @@ +/** + * @file pid.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __PID_H__ +#define __PID_H__ + +#include "stdio.h" + +typedef struct pid_alg { + float set_val; + float out_val; + + float kp; + float ki; + float kd; + + float i_error; + float last_error; + float prev_error; + float sum_error; + + int max_val; + int min_val; +} pid_alg_t; + +void pid_init(pid_alg_t *pid); +float standard_pid_cal(pid_alg_t *pid, float next_val); +float increment_pid_cal(pid_alg_t *pid, float next_val); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/ring_buffer/ring_buffer.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/ring_buffer/ring_buffer.c new file mode 100644 index 0000000000000000000000000000000000000000..ec91c715789c15606ebb6d80f3a389bcd70caad6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/ring_buffer/ring_buffer.c @@ -0,0 +1,679 @@ +/** + * @file ring_buffer.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "ring_buffer.h" + +/** @addtogroup BL_Common_Component + * @{ + */ + +/** @addtogroup RING_BUFFER + * @{ + */ + +/** @defgroup RING_BUFFER_Private_Macros + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Macros */ + +/** @defgroup RING_BUFFER_Private_Types + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Types */ + +/** @defgroup RING_BUFFER_Private_Fun_Declaration + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Fun_Declaration */ + +/** @defgroup RING_BUFFER_Private_Variables + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Variables */ + +/** @defgroup RING_BUFFER_Global_Variables + * @{ + */ + +/*@} end of group RING_BUFFER_Global_Variables */ + +/** @defgroup RING_BUFFER_Private_Functions + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Functions */ + +/** @defgroup RING_BUFFER_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Ring buffer init function + * + * @param rbType: Ring buffer type structure pointer + * @param buffer: Pointer of ring buffer + * @param size: Size of ring buffer + * @param lockCb: Ring buffer lock callback function pointer + * @param unlockCb: Ring buffer unlock callback function pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, ringBuffer_Lock_Callback *unlockCb) +{ + /* Init ring buffer pointer */ + rbType->pointer = buffer; + + /* Init read/write mirror and index */ + rbType->readMirror = 0; + rbType->readIndex = 0; + rbType->writeMirror = 0; + rbType->writeIndex = 0; + + /* Set ring buffer size */ + rbType->size = size; + + /* Set lock and unlock callback function */ + rbType->lock = lockCb; + rbType->unlock = unlockCb; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Ring buffer reset function + * + * @param rbType: Ring buffer type structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Clear read/write mirror and index */ + rbType->readMirror = 0; + rbType->readIndex = 0; + rbType->writeMirror = 0; + rbType->writeIndex = 0; + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Use callback function to write ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param length: Length of data want to write + * @param writeCb: Callback function pointer + * @param parameter: Parameter that callback function may use + * + * @return Length of data actually write + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, void *parameter) +{ + uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); + + if (writeCb == NULL) { + return 0; + } + + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no space for new data */ + if (sizeRemained == 0) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Drop part of data when length out of space remained */ + if (length > sizeRemained) { + length = sizeRemained; + } + + /* Get size of space remained in current mirror */ + sizeRemained = rbType->size - rbType->writeIndex; + + if (sizeRemained > length) { + /* Space remained is enough for data in current mirror */ + writeCb(parameter, &rbType->pointer[rbType->writeIndex], length); + rbType->writeIndex += length; + } else { + /* Data is divided to two parts with different mirror */ + writeCb(parameter, &rbType->pointer[rbType->writeIndex], sizeRemained); + writeCb(parameter, &rbType->pointer[0], length - sizeRemained); + rbType->writeIndex = length - sizeRemained; + rbType->writeMirror = ~rbType->writeMirror; + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return length; +} + +/****************************************************************************/ /** + * @brief Copy data from data buffer to ring buffer function + * + * @param parameter: Pointer to source pointer + * @param dest: Ring buffer to write + * @param length: Length of data to write + * + * @return None + * +*******************************************************************************/ +static void Ring_Buffer_Write_Copy(void *parameter, uint8_t *dest, uint32_t length) +{ + uint8_t **src = (uint8_t **)parameter; + + ARCH_MemCpy_Fast(dest, *src, length); + *src += length; +} + +/****************************************************************************/ /** + * @brief Write ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data to write + * @param length: Length of data + * + * @return Length of data writted actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) +{ + return Ring_Buffer_Write_Callback(rbType, length, Ring_Buffer_Write_Copy, &data); +} + +/****************************************************************************/ /** + * @brief Write 1 byte to ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data to write + * + * @return Length of data writted actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no space for new data */ + if (!Ring_Buffer_Get_Empty_Length(rbType)) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + rbType->pointer[rbType->writeIndex] = data; + + /* Judge to change index and mirror */ + if (rbType->writeIndex != (rbType->size - 1)) { + rbType->writeIndex++; + } else { + rbType->writeIndex = 0; + rbType->writeMirror = ~rbType->writeMirror; + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Write ring buffer function, old data will be covered by new data when ring buffer is + * full + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data to write + * @param length: Length of data + * + * @return Length of data writted actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) +{ + uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); + uint32_t indexRemained = rbType->size - rbType->writeIndex; + + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Drop extra data when data length is large than size of ring buffer */ + if (length > rbType->size) { + data = &data[length - rbType->size]; + length = rbType->size; + } + + if (indexRemained > length) { + /* Space remained is enough for data in current mirror */ + ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, length); + rbType->writeIndex += length; + + /* Update read index */ + if (length > sizeRemained) { + rbType->readIndex = rbType->writeIndex; + } + } else { + /* Data is divided to two parts with different mirror */ + ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, indexRemained); + ARCH_MemCpy_Fast(&rbType->pointer[0], &data[indexRemained], length - indexRemained); + rbType->writeIndex = length - indexRemained; + rbType->writeMirror = ~rbType->writeMirror; + + /* Update read index and mirror */ + if (length > sizeRemained) { + rbType->readIndex = rbType->writeIndex; + rbType->readMirror = ~rbType->readMirror; + } + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return length; +} + +/****************************************************************************/ /** + * @brief Write 1 byte to ring buffer function, old data will be covered by new data when ring + * buffer is full + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data to write + * + * @return Length of data writted actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data) +{ + Ring_Buffer_Status_Type status = Ring_Buffer_Get_Status(rbType); + + if (rbType->lock != NULL) { + rbType->lock(); + } + + rbType->pointer[rbType->writeIndex] = data; + + /* Judge to change index and mirror */ + if (rbType->writeIndex == rbType->size - 1) { + rbType->writeIndex = 0; + rbType->writeMirror = ~rbType->writeMirror; + + /* Update read index and mirror */ + if (status == RING_BUFFER_FULL) { + rbType->readIndex = rbType->writeIndex; + rbType->readMirror = ~rbType->readMirror; + } + } else { + rbType->writeIndex++; + + /* Update read index */ + if (status == RING_BUFFER_FULL) { + rbType->readIndex = rbType->writeIndex; + } + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Use callback function to read ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param length: Length of data want to read + * @param readCb: Callback function pointer + * @param parameter: Parameter that callback function may use + * + * @return Length of data actually read + * +*******************************************************************************/ +uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, void *parameter) +{ + uint32_t size = Ring_Buffer_Get_Length(rbType); + + if (readCb == NULL) { + return 0; + } + + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no data */ + if (!size) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Ring buffer do not have enough data */ + if (size < length) { + length = size; + } + + /* Get size of space remained in current mirror */ + size = rbType->size - rbType->readIndex; + + if (size > length) { + /* Read all data needed */ + readCb(parameter, &rbType->pointer[rbType->readIndex], length); + rbType->readIndex += length; + } else { + /* Read two part of data in different mirror */ + readCb(parameter, &rbType->pointer[rbType->readIndex], size); + readCb(parameter, &rbType->pointer[0], length - size); + rbType->readIndex = length - size; + rbType->readMirror = ~rbType->readMirror; + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return length; +} + +/****************************************************************************/ /** + * @brief Copy data from ring buffer to data buffer function + * + * @param parameter: Pointer to destination pointer + * @param data: Data buffer to copy + * @param length: Length of data to copy + * + * @return None + * +*******************************************************************************/ +static void Ring_Buffer_Read_Copy(void *parameter, uint8_t *data, uint32_t length) +{ + uint8_t **dest = (uint8_t **)parameter; + + ARCH_MemCpy_Fast(*dest, data, length); + *dest += length; +} + +/****************************************************************************/ /** + * @brief Read ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param data: Buffer for data read + * @param length: Length of data to read + * + * @return Length of data read actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) +{ + return Ring_Buffer_Read_Callback(rbType, length, Ring_Buffer_Read_Copy, &data); +} + +/****************************************************************************/ /** + * @brief Read 1 byte from ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data read + * + * @return Length of data actually read + * +*******************************************************************************/ +uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no data */ + if (!Ring_Buffer_Get_Length(rbType)) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Read data */ + *data = rbType->pointer[rbType->readIndex]; + + /* Update read index and mirror */ + if (rbType->readIndex == rbType->size - 1) { + rbType->readIndex = 0; + rbType->readMirror = ~rbType->readMirror; + } else { + rbType->readIndex++; + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Read ring buffer function, do not remove from buffer actually + * + * @param rbType: Ring buffer type structure pointer + * @param data: Buffer for data read + * @param length: Length of data to read + * + * @return Length of data read actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) +{ + uint32_t size = Ring_Buffer_Get_Length(rbType); + + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no data */ + if (!size) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Ring buffer do not have enough data */ + if (size < length) { + length = size; + } + + /* Get size of space remained in current mirror */ + size = rbType->size - rbType->readIndex; + + if (size > length) { + /* Read all data needed */ + ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], length); + } else { + /* Read two part of data in different mirror */ + ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], size); + ARCH_MemCpy_Fast(&data[size], &rbType->pointer[0], length - size); + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return length; +} + +/****************************************************************************/ /** + * @brief Read 1 byte from ring buffer function, do not remove from buffer actually + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data read + * + * @return Length of data actually read + * +*******************************************************************************/ +uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no data */ + if (!Ring_Buffer_Get_Length(rbType)) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Read data */ + *data = rbType->pointer[rbType->readIndex]; + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Get length of data in ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * + * @return Length of data + * +*******************************************************************************/ +uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType) +{ + uint32_t readMirror = 0; + uint32_t writeMirror = 0; + uint32_t readIndex = 0; + uint32_t writeIndex = 0; + uint32_t size = 0; + + if (rbType->lock != NULL) { + rbType->lock(); + } + + readMirror = rbType->readMirror; + writeMirror = rbType->writeMirror; + readIndex = rbType->readIndex; + writeIndex = rbType->writeIndex; + size = rbType->size; + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + if (readMirror == writeMirror) { + return writeIndex - readIndex; + } else { + return size - (readIndex - writeIndex); + } +} + +/****************************************************************************/ /** + * @brief Get space remained in ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * + * @return Length of space remained + * +*******************************************************************************/ +uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType) +{ + return (rbType->size - Ring_Buffer_Get_Length(rbType)); +} + +/****************************************************************************/ /** + * @brief Get ring buffer status function + * + * @param rbType: Ring buffer type structure pointer + * + * @return Status of ring buffer + * +*******************************************************************************/ +Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Judge empty or full */ + if (rbType->readIndex == rbType->writeIndex) { + if (rbType->readMirror == rbType->writeMirror) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return RING_BUFFER_EMPTY; + } else { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return RING_BUFFER_FULL; + } + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return RING_BUFFER_PARTIAL; +} + +/*@} end of group RING_BUFFER_Public_Functions */ + +/*@} end of group RING_BUFFER */ + +/*@} end of group BL_Common_Component */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/ring_buffer/ring_buffer.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/ring_buffer/ring_buffer.h new file mode 100644 index 0000000000000000000000000000000000000000..dbc66819944c38b27653059a23897139a6b6a432 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/ring_buffer/ring_buffer.h @@ -0,0 +1,116 @@ +/** + * @file ring_buffer.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __RING_BUFFER_H__ +#define __RING_BUFFER_H__ + +#include "misc.h" + +/** @addtogroup BL_Common_Component + * @{ + */ + +/** @addtogroup RING_BUFFER + * @{ + */ + +/** @defgroup RING_BUFFER_Public_Types + * @{ + */ + +/** + * @brief Ring buffer status type definition + */ +typedef enum { + RING_BUFFER_EMPTY, /*!< Ring buffer is empty */ + RING_BUFFER_PARTIAL, /*!< Ring buffer has partial data */ + RING_BUFFER_FULL, /*!< Ring buffer is full */ +} Ring_Buffer_Status_Type; + +/** + * @brief Ring buffer structure definition + */ +typedef struct +{ + uint8_t *pointer; /*!< Pointer of ring buffer */ + uint8_t readMirror; /*!< Read mirror,used to judge empty or full */ + uint32_t readIndex; /*!< Index of read address */ + uint8_t writeMirror; /*!< Write mirror,used to judge empty or full */ + uint32_t writeIndex; /*!< Index of write address */ + uint32_t size; /*!< Size of ring buffer */ + void (*lock)(void); /*!< Lock ring buffer */ + void (*unlock)(void); /*!< Unlock ring buffer */ +} Ring_Buffer_Type; + +/*@} end of group RING_BUFFER_Public_Types */ + +/** @defgroup RING_BUFFER_Public_Constants + * @{ + */ + +/** @defgroup RING_BUFFER_STATUS_TYPE + * @{ + */ +#define IS_RING_BUFFER_STATUS_TYPE(type) (((type) == RING_BUFFER_EMPTY) || \ + ((type) == RING_BUFFER_PARTIAL) || \ + ((type) == RING_BUFFER_FULL)) + +/*@} end of group RING_BUFFER_Public_Constants */ + +/** @defgroup RING_BUFFER_Public_Macros + * @{ + */ +typedef void(ringBuffer_Lock_Callback)(void); +typedef void(ringBuffer_Read_Callback)(void *, uint8_t *, uint32_t); +typedef void(ringBuffer_Write_Callback)(void *, uint8_t *, uint32_t); + +/*@} end of group RING_BUFFER_Public_Macros */ + +/** @defgroup RING_BUFFER_Public_Functions + * @{ + */ +BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, + ringBuffer_Lock_Callback *unlockCb); +BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType); +uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, + void *parameter); +uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); +uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data); +uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); +uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data); +uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, + void *parameter); +uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); +uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data); +uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); +uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data); +uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType); +uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType); +Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType); + +/*@} end of group RING_BUFFER_Public_Functions */ + +/*@} end of group RING_BUFFER */ + +/*@} end of group BL_Common_Component */ + +#endif /* __RING_BUFFER_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/soft_crc/softcrc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/soft_crc/softcrc.c new file mode 100644 index 0000000000000000000000000000000000000000..4c4cbe55cb518700a698870c959e200d9b008085 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/soft_crc/softcrc.c @@ -0,0 +1,194 @@ +/** + * @file softcrc.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "softcrc.h" +#include "misc.h" +// ---------------- POPULAR POLYNOMIALS ---------------- +// CCITT: x^16 + x^12 + x^5 + x^0 (0x1021,init 0x0000) +// CRC-16: x^16 + x^15 + x^2 + x^0 (0x8005,init 0xFFFF) +// we use 0x8005 here and + +const uint8_t chCRCHTalbe[] = { + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40 +}; + +const uint8_t chCRCLTalbe[] = { + 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, + 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, + 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, + 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, + 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3, + 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, + 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, + 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, + 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, + 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26, + 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, + 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, + 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, + 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, + 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5, + 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, + 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, + 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, + 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, + 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C, + 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, + 0x41, 0x81, 0x80, 0x40 +}; + +uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len) +{ + uint8_t chCRCHi = 0xFF; + uint8_t chCRCLo = 0xFF; + uint16_t wIndex; + uint8_t *data = (uint8_t *)dataIn; + + while (len--) { + wIndex = chCRCLo ^ *data++; + chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex]; + chCRCHi = chCRCLTalbe[wIndex]; + } + + return ((chCRCHi << 8) | chCRCLo); +} + +/* +x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 +*/ +const uint32_t crc32Tab[256] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +uint32_t BFLB_Soft_CRC32_Table(void *dataIn, uint32_t len) +{ + uint32_t crc = 0; + uint8_t *data = (uint8_t *)dataIn; + + crc = crc ^ 0xffffffff; + + while (len--) { + crc = crc32Tab[(crc ^ *data++) & 0xFF] ^ (crc >> 8); + } + + return crc ^ 0xffffffff; +} + +/****************************************************************************** +* Name: CRC-32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 +* Poly: 0x4C11DB7 +* Init: 0xFFFFFFF +* Refin: True +* Refout: True +* Xorout: 0xFFFFFFF +* Alias: CRC_32/ADCCP +* Use: WinRAR,ect. +*****************************************************************************/ +uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len) +{ + uint8_t i; + uint32_t crc = ~initial; // Initial value + uint8_t *data=(uint8_t *)dataIn; + + while(len--){ + crc ^= *data++; // crc ^= *data; data++; + for (i = 0; i < 8; ++i){ + if (crc & 1){ + crc = (crc >> 1) ^ 0xEDB88320;// 0xEDB88320= reverse 0x04C11DB7 + }else{ + crc = (crc >> 1); + } + } + } + return ~crc; +} + +#ifndef BFLB_USE_ROM_DRIVER +__WEAK__ +uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len) +{ + return BFLB_Soft_CRC32_Ex(0,dataIn,len); +} +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/soft_crc/softcrc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/soft_crc/softcrc.h new file mode 100644 index 0000000000000000000000000000000000000000..c56ab26d23d906eb853b94e51b95d983268cec74 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/soft_crc/softcrc.h @@ -0,0 +1,32 @@ +/** + * @file softcrc.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __SOFTCRC_H__ +#define __SOFTCRC_H__ + +#include "stdint.h" + +uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len); +uint32_t BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len); +uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/timestamp/timestamp.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/timestamp/timestamp.c new file mode 100644 index 0000000000000000000000000000000000000000..606bafd177fce6a574591c873a3a6c219664f783 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/timestamp/timestamp.c @@ -0,0 +1,137 @@ +/** + * @file timestamp.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "timestamp.h" +#include "misc.h" + +#define FOUR_YEAR_DAY ((365 << 2) + 1) //The total number of days in a 4-year cycle +#define TIMEZONE (8) //Beijing time Zone adjustment + +#define SEC_NUM_PER_DAY (24 * 60 * 60) +#define SEC_NUM_PER_HOUR (60 * 60) +#define SEC_NUM_PER_MINUTE (60) + +static uint8_t month_day[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //平年 +static uint8_t Leap_month_day[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //闰年 + +/** +* @bref judge if it is a leap year +* @para year to be judge +* @return 1:leap year 0: nonleap year +*/ +bool check_leap_year(uint16_t year) +{ + if (year % 4) { + return false; + } else { + if ((year % 100 == 0) && (year % 400 != 0)) { + return false; + } else { + return true; + } + } +} + +void cal_weekday(rtc_time *beijing_time) +{ + uint32_t y,m,d,w; + + y=beijing_time->year; + m=beijing_time->month; + d=beijing_time->day; + + if((m==1)||(m==2)) + { + m+=12; + y--; + } + /* + 把一月和二月看成是上一年的十三月和十四月,例:如果是2004-1-10则换算成:2003-13-10来代入公式计算。 + 以公元元年为参考,公元元年1月1日为星期一
程序如下:
+	利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)
+	*/
+	w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400+1)%7;
+
+	beijing_time->week=(uint8_t)w;
+}
+
+void unixtime2bejingtime(uint32_t unixtime, rtc_time *beijing_time)
+{
+    uint32_t totle_day_num;
+    uint32_t current_sec_num;
+
+    uint16_t remain_day;
+
+    uint16_t temp_year;
+
+    uint8_t *p = NULL;
+
+    totle_day_num = unixtime / SEC_NUM_PER_DAY;   //The total number of days
+    current_sec_num = unixtime % SEC_NUM_PER_DAY; //The number of seconds this day
+
+    /* use the number of seconds this day, To calculate hour\minute\second */
+    beijing_time->hour = current_sec_num / SEC_NUM_PER_HOUR;
+    beijing_time->minute = (current_sec_num % SEC_NUM_PER_HOUR) / SEC_NUM_PER_MINUTE;
+    beijing_time->second = (current_sec_num % SEC_NUM_PER_HOUR) % SEC_NUM_PER_MINUTE;
+
+    /* Adjust the time zone and check whether the date is +1 */
+    beijing_time->hour += 8;
+    if (beijing_time->hour > 23) {
+        beijing_time->hour -= 24;
+        totle_day_num++;
+    }
+
+
+    /* calculate year */
+    beijing_time->year = 1970 + (totle_day_num / FOUR_YEAR_DAY) * 4; // 4-year as a cycle
+    remain_day = totle_day_num % FOUR_YEAR_DAY;                      //remaining day nym( < 4 year )
+
+    /* calculate year & day */
+    temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
+    while (remain_day >= temp_year) {
+        beijing_time->year++;
+        remain_day -= temp_year;
+        temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
+    }
+
+    /* Calculate specific dates(month\day)*/
+    p = check_leap_year(beijing_time->year) ? Leap_month_day : month_day;
+    remain_day++; //The actual day starts at 1
+    beijing_time->month = 0;
+    while (remain_day > *(p + beijing_time->month)) {
+        remain_day -= *(p + beijing_time->month);
+        beijing_time->month++;
+    }
+
+    beijing_time->month++; //The actual month starts at 1
+    beijing_time->day = remain_day;
+
+
+	
+	/*利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)*/
+
+	beijing_time->week = beijing_time->day + 2*beijing_time->month + 3*(beijing_time->month+1)/5 + \
+	beijing_time->year + beijing_time->year/4 - beijing_time->year/100 +beijing_time->year/400 ;
+
+	cal_weekday(beijing_time);
+}
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/common/timestamp/timestamp.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/timestamp/timestamp.h
new file mode 100644
index 0000000000000000000000000000000000000000..2522d0f33b3e8397e061e53e18dda80d8800762a
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/common/timestamp/timestamp.h
@@ -0,0 +1,43 @@
+/**
+ * @file timestamp.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _TIMESTAMP_
+#define _TIMESTAMP_
+
+#include "stdint.h"
+#include "stdbool.h" 
+
+typedef struct _rtc_time_t
+{
+	uint16_t year;
+	uint8_t month;
+	uint8_t day;
+	uint8_t week;
+	uint8_t hour;
+	uint8_t minute;
+	uint8_t second;
+}rtc_time;
+void unixtime2bejingtime(uint32_t unixtime,rtc_time* beijing_time);
+
+#endif
+
+
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.c
new file mode 100644
index 0000000000000000000000000000000000000000..df59f393d44c43c8a8020de2f212cbe7908d654c
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.c
@@ -0,0 +1,105 @@
+#include "usbd_core.h"
+#include "usbd_audio.h"
+
+struct usbd_audio_control_info audio_control_info = { 0xdb00, 0x0000, 0x0100, 0xf600, 0 };
+
+int audio_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("Class request:"
+                 "bRequest 0x%02x, bmRequestType 0x%02x len %d",
+                 setup->bRequest, setup->bmRequestType, *len);
+
+    switch (setup->bRequest) {
+        case AUDIO_REQUEST_SET_CUR:
+
+            if (setup->wValueL == 0x01) {
+                if (setup->wValueH == AUDIO_FU_CONTROL_MUTE) {
+                    memcpy(&audio_control_info.mute, *data, *len);
+                } else if (setup->wValueH == AUDIO_FU_CONTROL_VOLUME) {
+                    memcpy(&audio_control_info.vol_current, *data, *len);
+                    uint32_t vol;
+                    if (audio_control_info.vol_current == 0) {
+                        vol = 100;
+                    } else {
+                        vol = (audio_control_info.vol_current - 0xDB00 + 1) * 100 / (0xFFFF - 0xDB00);
+                    }
+                    usbd_audio_set_volume(vol);
+                    USBD_LOG_WRN("vol:%d\r\n", vol);
+                }
+            }
+
+            break;
+
+        case AUDIO_REQUEST_GET_CUR:
+            if (setup->wValueH == AUDIO_FU_CONTROL_MUTE) {
+                *data = (uint8_t *)&audio_control_info.mute;
+                *len = 1;
+            } else if (setup->wValueH == AUDIO_FU_CONTROL_VOLUME) {
+                *data = (uint8_t *)&audio_control_info.vol_current;
+                *len = 2;
+            }
+
+            break;
+
+        case AUDIO_REQUEST_SET_RES:
+            break;
+
+        case AUDIO_REQUEST_GET_MIN:
+            *data = (uint8_t *)&audio_control_info.vol_min;
+            *len = 2;
+            break;
+
+        case AUDIO_REQUEST_GET_MAX:
+            *data = (uint8_t *)&audio_control_info.vol_max;
+            *len = 2;
+            break;
+
+        case AUDIO_REQUEST_GET_RES:
+            *data = (uint8_t *)&audio_control_info.vol_res;
+            *len = 2;
+            break;
+
+        default:
+            USBD_LOG_ERR("Unhandled request 0x%02x", setup->bRequest);
+            break;
+    }
+
+    return 0;
+}
+
+void audio_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+
+            break;
+
+        case USB_EVENT_SOF:
+            break;
+
+        case USB_EVENT_SET_INTERFACE:
+            usbd_audio_set_interface_callback(((uint8_t *)arg)[3]);
+            break;
+
+        default:
+            break;
+    }
+}
+__weak void usbd_audio_set_volume(uint8_t vol)
+{
+}
+void usbd_audio_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = audio_class_request_handler;
+    intf->custom_handler = NULL;
+    intf->vendor_handler = NULL;
+    intf->notify_handler = audio_notify_handler;
+    usbd_class_add_interface(class, intf);
+}
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.h
new file mode 100644
index 0000000000000000000000000000000000000000..35f3fe25f2a5eb57eb50d47ebf3264b236221d8b
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.h
@@ -0,0 +1,277 @@
+/**
+ * @file
+ * @brief USB Audio Device Class public header
+ *
+ * Header follows below documentation:
+ * - USB Device Class Definition for Audio Devices (audio10.pdf)
+ *
+ * Additional documentation considered a part of USB Audio v1.0:
+ * - USB Device Class Definition for Audio Data Formats (frmts10.pdf)
+ * - USB Device Class Definition for Terminal Types (termt10.pdf)
+ */
+
+#ifndef _USBD_AUDIO_H_
+#define _USBD_AUDIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Audio Interface Subclass Codes
+ * Refer to Table A-2 from audio10.pdf
+ */
+#define AUDIO_SUBCLASS_UNDEFINED      0x00
+#define AUDIO_SUBCLASS_AUDIOCONTROL   0x01
+#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02
+#define AUDIO_SUBCLASS_MIDISTREAMING  0x03
+
+#define AUDIO_PROTOCOL_UNDEFINED 0x00U
+
+#define AUDIO_ENDPOINT_GENERAL 0x01U
+
+/** Audio Class-Specific Control Interface Descriptor Subtypes
+ * Refer to Table A-5 from audio10.pdf
+ */
+#define AUDIO_CONTROL_UNDEFINED       0x01U
+#define AUDIO_CONTROL_HEADER          0x01U
+#define AUDIO_CONTROL_INPUT_TERMINAL  0x02U
+#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03U
+#define AUDIO_CONTROL_MIXER_UNIT      0x04U
+#define AUDIO_CONTROL_SELECTOR_UNIT   0x05U
+#define AUDIO_CONTROL_FEATURE_UNIT    0x06U
+#define AUDIO_CONTROL_PROCESSING_UNIT 0x07U
+#define AUDIO_CONTROL_EXTENSION_UNIT  0x08U
+
+/** Audio Class-Specific AS Interface Descriptor Subtypes
+ * Refer to Table A-6 from audio10.pdf
+ */
+#define AUDIO_STREAMING_UNDEFINED       0x00U
+#define AUDIO_STREAMING_GENERAL         0x01U
+#define AUDIO_STREAMING_FORMAT_TYPE     0x02U
+#define AUDIO_STREAMING_FORMAT_SPECIFIC 0x03U
+
+/** Audio Class-Specific Request Codes
+ * Refer to Table A-9 from audio10.pdf
+ */
+#define AUDIO_REQUEST_UNDEFINED 0x00
+#define AUDIO_REQUEST_SET_CUR   0x01
+#define AUDIO_REQUEST_GET_CUR   0x81
+#define AUDIO_REQUEST_SET_MIN   0x02
+#define AUDIO_REQUEST_GET_MIN   0x82
+#define AUDIO_REQUEST_SET_MAX   0x03
+#define AUDIO_REQUEST_GET_MAX   0x83
+#define AUDIO_REQUEST_SET_RES   0x04
+#define AUDIO_REQUEST_GET_RES   0x84
+#define AUDIO_REQUEST_SET_MEM   0x05
+#define AUDIO_REQUEST_GET_MEM   0x85
+#define AUDIO_REQUEST_GET_STAT  0xFF
+
+/* Feature Unit Control Bits */
+#define AUDIO_CONTROL_MUTE              0x0001
+#define AUDIO_CONTROL_VOLUME            0x0002
+#define AUDIO_CONTROL_BASS              0x0004
+#define AUDIO_CONTROL_MID               0x0008
+#define AUDIO_CONTROL_TREBLE            0x0010
+#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020
+#define AUDIO_CONTROL_AUTOMATIC_GAIN    0x0040
+#define AUDIO_CONTROL_DEALY             0x0080
+#define AUDIO_CONTROL_BASS_BOOST        0x0100
+#define AUDIO_CONTROL_LOUDNESS          0x0200
+
+/** Feature Unit Control Selectors
+ * Refer to Table A-11 from audio10.pdf
+ */
+#define AUDIO_FU_CONTROL_MUTE              0x01
+#define AUDIO_FU_CONTROL_VOLUME            0x02
+#define AUDIO_FU_CONTROL_BASS              0x03
+#define AUDIO_FU_CONTROL_MID               0x04
+#define AUDIO_FU_CONTROL_TREBLE            0x05
+#define AUDIO_FU_CONTROL_GRAPHIC_EQUALIZER 0x06
+#define AUDIO_FU_CONTROL_AUTOMATIC_GAIN    0x07
+#define AUDIO_FU_CONTROL_DELAY             0x08
+#define AUDIO_FU_CONTROL_BASS_BOOST        0x09
+#define AUDIO_FU_CONTROL_LOUDNESS          0x0A
+
+/* Audio Descriptor Types */
+#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE     0x20
+#define AUDIO_DEVICE_DESCRIPTOR_TYPE        0x21
+#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22
+#define AUDIO_STRING_DESCRIPTOR_TYPE        0x23
+#define AUDIO_INTERFACE_DESCRIPTOR_TYPE     0x24
+#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE      0x25
+
+/* Audio Data Format Type I Codes */
+#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0000
+#define AUDIO_FORMAT_PCM              0x0001
+#define AUDIO_FORMAT_PCM8             0x0002
+#define AUDIO_FORMAT_IEEE_FLOAT       0x0003
+#define AUDIO_FORMAT_ALAW             0x0004
+#define AUDIO_FORMAT_MULAW            0x0005
+
+/* Predefined Audio Channel Configuration Bits */
+#define AUDIO_CHANNEL_M   0x0000 /* Mono */
+#define AUDIO_CHANNEL_L   0x0001 /* Left Front */
+#define AUDIO_CHANNEL_R   0x0002 /* Right Front */
+#define AUDIO_CHANNEL_C   0x0004 /* Center Front */
+#define AUDIO_CHANNEL_LFE 0x0008 /* Low Freq. Enhance. */
+#define AUDIO_CHANNEL_LS  0x0010 /* Left Surround */
+#define AUDIO_CHANNEL_RS  0x0020 /* Right Surround */
+#define AUDIO_CHANNEL_LC  0x0040 /* Left of Center */
+#define AUDIO_CHANNEL_RC  0x0080 /* Right of Center */
+#define AUDIO_CHANNEL_S   0x0100 /* Surround */
+#define AUDIO_CHANNEL_SL  0x0200 /* Side Left */
+#define AUDIO_CHANNEL_SR  0x0400 /* Side Right */
+#define AUDIO_CHANNEL_T   0x0800 /* Top */
+
+#define AUDIO_FORMAT_TYPE_I   0x01
+#define AUDIO_FORMAT_TYPE_II  0x02
+#define AUDIO_FORMAT_TYPE_III 0x03
+
+/** USB Terminal Types
+ * Refer to Table 2-1 - Table 2-4 from termt10.pdf
+ */
+enum usb_audio_terminal_types {
+    /* USB Terminal Types */
+    USB_AUDIO_USB_UNDEFINED = 0x0100,
+    USB_AUDIO_USB_STREAMING = 0x0101,
+    USB_AUDIO_USB_VENDOR_SPEC = 0x01FF,
+
+    /* Input Terminal Types */
+    USB_AUDIO_IN_UNDEFINED = 0x0200,
+    USB_AUDIO_IN_MICROPHONE = 0x0201,
+    USB_AUDIO_IN_DESKTOP_MIC = 0x0202,
+    USB_AUDIO_IN_PERSONAL_MIC = 0x0203,
+    USB_AUDIO_IN_OM_DIR_MIC = 0x0204,
+    USB_AUDIO_IN_MIC_ARRAY = 0x0205,
+    USB_AUDIO_IN_PROC_MIC_ARRAY = 0x0205,
+
+    /* Output Terminal Types */
+    USB_AUDIO_OUT_UNDEFINED = 0x0300,
+    USB_AUDIO_OUT_SPEAKER = 0x0301,
+    USB_AUDIO_OUT_HEADPHONES = 0x0302,
+    USB_AUDIO_OUT_HEAD_AUDIO = 0x0303,
+    USB_AUDIO_OUT_DESKTOP_SPEAKER = 0x0304,
+    USB_AUDIO_OUT_ROOM_SPEAKER = 0x0305,
+    USB_AUDIO_OUT_COMM_SPEAKER = 0x0306,
+    USB_AUDIO_OUT_LOW_FREQ_SPEAKER = 0x0307,
+
+    /* Bi-directional Terminal Types */
+    USB_AUDIO_IO_UNDEFINED = 0x0400,
+    USB_AUDIO_IO_HANDSET = 0x0401,
+    USB_AUDIO_IO_HEADSET = 0x0402,
+    USB_AUDIO_IO_SPEAKERPHONE_ECHO_NONE = 0x0403,
+    USB_AUDIO_IO_SPEAKERPHONE_ECHO_SUP = 0x0404,
+    USB_AUDIO_IO_SPEAKERPHONE_ECHO_CAN = 0x0405,
+};
+
+/**
+ * @warning Size of baInterface is 2 just to make it useable
+ * for all kind of devices: headphones, microphone and headset.
+ * Actual size of the struct should be checked by reading
+ * .bLength.
+ */
+struct cs_ac_if_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint16_t bcdADC;
+    uint16_t wTotalLength;
+    uint8_t bInCollection;
+    uint8_t baInterfaceNr[2];
+} __packed;
+
+struct input_terminal_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bTerminalID;
+    uint16_t wTerminalType;
+    uint8_t bAssocTerminal;
+    uint8_t bNrChannels;
+    uint16_t wChannelConfig;
+    uint8_t iChannelNames;
+    uint8_t iTerminal;
+} __packed;
+
+/**
+ * @note Size of Feature unit descriptor is not fixed.
+ * This structure is just a helper not a common type.
+ */
+struct feature_unit_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bUnitID;
+    uint8_t bSourceID;
+    uint8_t bControlSize;
+    uint16_t bmaControls[1];
+} __packed;
+
+struct output_terminal_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bTerminalID;
+    uint16_t wTerminalType;
+    uint8_t bAssocTerminal;
+    uint8_t bSourceID;
+    uint8_t iTerminal;
+} __packed;
+
+struct as_cs_interface_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bTerminalLink;
+    uint8_t bDelay;
+    uint16_t wFormatTag;
+} __packed;
+
+struct format_type_i_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bFormatType;
+    uint8_t bNrChannels;
+    uint8_t bSubframeSize;
+    uint8_t bBitResolution;
+    uint8_t bSamFreqType;
+    uint8_t tSamFreq[3];
+} __packed;
+
+struct std_as_ad_endpoint_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bEndpointAddress;
+    uint8_t bmAttributes;
+    uint16_t wMaxPacketSize;
+    uint8_t bInterval;
+    uint8_t bRefresh;
+    uint8_t bSynchAddress;
+} __packed;
+
+struct cs_as_ad_ep_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bmAttributes;
+    uint8_t bLockDelayUnits;
+    uint16_t wLockDelay;
+} __packed;
+
+struct usbd_audio_control_info {
+    uint16_t vol_min;
+    uint16_t vol_max;
+    uint16_t vol_res;
+    uint16_t vol_current;
+    uint8_t mute;
+};
+
+void usbd_audio_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+void usbd_audio_set_interface_callback(uint8_t value);
+void usbd_audio_set_volume(uint8_t vol);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _USB_AUDIO_H_ */
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.c
new file mode 100644
index 0000000000000000000000000000000000000000..cd9f49ca029ccae9fee9491e235bce0ce582c4dc
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.c
@@ -0,0 +1,168 @@
+/**
+ * @file usbd_cdc.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_cdc.h"
+
+const char *stop_name[] = { "1", "1.5", "2" };
+const char *parity_name[] = { "N", "O", "E", "M", "S" };
+
+/* Device data structure */
+struct cdc_acm_cfg_private {
+    /* CDC ACM line coding properties. LE order */
+    struct cdc_line_coding line_coding;
+    /* CDC ACM line state bitmap, DTE side */
+    uint8_t line_state;
+    /* CDC ACM serial state bitmap, DCE side */
+    uint8_t serial_state;
+    /* CDC ACM notification sent status */
+    uint8_t notification_sent;
+    /* CDC ACM configured flag */
+    bool configured;
+    /* CDC ACM suspended flag */
+    bool suspended;
+    uint32_t uart_first_init_flag;
+
+} usbd_cdc_acm_cfg;
+
+static void usbd_cdc_acm_reset(void)
+{
+    usbd_cdc_acm_cfg.line_coding.dwDTERate = 2000000;
+    usbd_cdc_acm_cfg.line_coding.bDataBits = 8;
+    usbd_cdc_acm_cfg.line_coding.bParityType = 0;
+    usbd_cdc_acm_cfg.line_coding.bCharFormat = 0;
+    usbd_cdc_acm_cfg.configured = false;
+    usbd_cdc_acm_cfg.uart_first_init_flag = 0;
+}
+
+/**
+ * @brief Handler called for Class requests not handled by the USB stack.
+ *
+ * @param pSetup    Information about the request to execute.
+ * @param len       Size of the buffer.
+ * @param data      Buffer containing the request result.
+ *
+ * @return  0 on success, negative errno code on fail.
+ */
+static int cdc_acm_class_request_handler(struct usb_setup_packet *pSetup, uint8_t **data, uint32_t *len)
+{
+    switch (pSetup->bRequest) {
+        case CDC_REQUEST_SET_LINE_CODING:
+
+            /*******************************************************************************/
+            /* Line Coding Structure                                                       */
+            /*-----------------------------------------------------------------------------*/
+            /* Offset | Field       | Size | Value  | Description                          */
+            /* 0      | dwDTERate   |   4  | Number |Data terminal rate, in bits per second*/
+            /* 4      | bCharFormat |   1  | Number | Stop bits                            */
+            /*                                        0 - 1 Stop bit                       */
+            /*                                        1 - 1.5 Stop bits                    */
+            /*                                        2 - 2 Stop bits                      */
+            /* 5      | bParityType |  1   | Number | Parity                               */
+            /*                                        0 - None                             */
+            /*                                        1 - Odd                              */
+            /*                                        2 - Even                             */
+            /*                                        3 - Mark                             */
+            /*                                        4 - Space                            */
+            /* 6      | bDataBits  |   1   | Number Data bits (5, 6, 7, 8 or 16).          */
+            /*******************************************************************************/
+            if (usbd_cdc_acm_cfg.uart_first_init_flag == 0) {
+                usbd_cdc_acm_cfg.uart_first_init_flag = 1;
+                return 0;
+            }
+
+            memcpy(&usbd_cdc_acm_cfg.line_coding, *data, sizeof(usbd_cdc_acm_cfg.line_coding));
+            USBD_LOG_DBG("CDC_SET_LINE_CODING <%d %d %s %s>\r\n",
+                         usbd_cdc_acm_cfg.line_coding.dwDTERate,
+                         usbd_cdc_acm_cfg.line_coding.bDataBits,
+                         parity_name[usbd_cdc_acm_cfg.line_coding.bParityType],
+                         stop_name[usbd_cdc_acm_cfg.line_coding.bCharFormat]);
+            usbd_cdc_acm_set_line_coding(usbd_cdc_acm_cfg.line_coding.dwDTERate, usbd_cdc_acm_cfg.line_coding.bDataBits,
+                                         usbd_cdc_acm_cfg.line_coding.bParityType, usbd_cdc_acm_cfg.line_coding.bCharFormat);
+            break;
+
+        case CDC_REQUEST_SET_CONTROL_LINE_STATE:
+            usbd_cdc_acm_cfg.line_state = (uint8_t)pSetup->wValue;
+            bool dtr = (pSetup->wValue & 0x01);
+            bool rts = (pSetup->wValue & 0x02);
+            USBD_LOG_DBG("DTR 0x%x,RTS 0x%x\r\n",
+                         dtr, rts);
+            usbd_cdc_acm_set_dtr(dtr);
+            usbd_cdc_acm_set_rts(rts);
+            break;
+
+        case CDC_REQUEST_GET_LINE_CODING:
+            *data = (uint8_t *)(&usbd_cdc_acm_cfg.line_coding);
+            *len = sizeof(usbd_cdc_acm_cfg.line_coding);
+            USBD_LOG_DBG("CDC_GET_LINE_CODING %d %d %d %d\r\n",
+                         usbd_cdc_acm_cfg.line_coding.dwDTERate,
+                         usbd_cdc_acm_cfg.line_coding.bCharFormat,
+                         usbd_cdc_acm_cfg.line_coding.bParityType,
+                         usbd_cdc_acm_cfg.line_coding.bDataBits);
+            break;
+
+        default:
+            USBD_LOG_DBG("CDC ACM request 0x%x, value 0x%x\r\n",
+                         pSetup->bRequest, pSetup->wValue);
+            return -1;
+    }
+
+    return 0;
+}
+
+static void cdc_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_cdc_acm_reset();
+            break;
+
+        default:
+            break;
+    }
+}
+
+__weak void usbd_cdc_acm_set_line_coding(uint32_t baudrate, uint8_t databits, uint8_t parity, uint8_t stopbits)
+{
+}
+__weak void usbd_cdc_acm_set_dtr(bool dtr)
+{
+}
+__weak void usbd_cdc_acm_set_rts(bool rts)
+{
+}
+
+void usbd_cdc_add_acm_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = cdc_acm_class_request_handler;
+    intf->custom_handler = NULL;
+    intf->vendor_handler = NULL;
+    intf->notify_handler = cdc_notify_handler;
+    usbd_class_add_interface(class, intf);
+}
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.h
new file mode 100644
index 0000000000000000000000000000000000000000..335cd3236d221bdf21ff21f4de2d7edaccb580be
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.h
@@ -0,0 +1,440 @@
+/**
+ * @file
+ * @brief USB Communications Device Class (CDC) public header
+ *
+ * Header follows the Class Definitions for
+ * Communications Devices Specification (CDC120-20101103-track.pdf),
+ * PSTN Devices Specification (PSTN120.pdf) and
+ * Ethernet Control Model Devices Specification (ECM120.pdf).
+ * Header is limited to ACM and ECM Subclasses.
+ */
+
+#ifndef _USBD_CDC_H
+#define _USBD_CDC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ *      Definitions  based on usbcdc11.pdf (www.usb.org)
+ *----------------------------------------------------------------------------*/
+/* Communication device class specification version 1.10 */
+#define CDC_V1_10 0x0110U
+// Communication device class specification version 1.2
+#define CDC_V1_2_0 0x0120U
+
+/* Communication interface class code */
+/* (usbcdc11.pdf, 4.2, Table 15) */
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U
+
+/* Communication interface class subclass codes */
+/* (usbcdc11.pdf, 4.3, Table 16) */
+#define CDC_DIRECT_LINE_CONTROL_MODEL         0x01U
+#define CDC_ABSTRACT_CONTROL_MODEL            0x02U
+#define CDC_TELEPHONE_CONTROL_MODEL           0x03U
+#define CDC_MULTI_CHANNEL_CONTROL_MODEL       0x04U
+#define CDC_CAPI_CONTROL_MODEL                0x05U
+#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06U
+#define CDC_ATM_NETWORKING_CONTROL_MODEL      0x07U
+#define CDC_WIRELESS_HANDSET_CONTROL_MODEL    0x08U
+#define CDC_DEVICE_MANAGEMENT                 0x09U
+#define CDC_MOBILE_DIRECT_LINE_MODEL          0x0AU
+#define CDC_OBEX                              0x0BU
+#define CDC_ETHERNET_EMULATION_MODEL          0x0CU
+#define CDC_NETWORK_CONTROL_MODEL             0x0DU
+
+/* Communication interface class control protocol codes */
+/* (usbcdc11.pdf, 4.4, Table 17) */
+#define CDC_COMMON_PROTOCOL_NONE                            0x00U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS                     0x01U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101            0x02U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO 0x03U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_GSM_707             0x04U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_3GPP_27007          0x05U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_CDMA                0x06U
+#define CDC_COMMON_PROTOCOL_ETHERNET_EMULATION_MODEL        0x07U
+// NCM Communication Interface Protocol Codes
+// (usbncm10.pdf, 4.2, Table 4-2)
+#define CDC_NCM_PROTOCOL_NONE 0x00U
+#define CDC_NCM_PROTOCOL_OEM  0xFEU
+
+/* Data interface class code */
+/* (usbcdc11.pdf, 4.5, Table 18) */
+#define CDC_DATA_INTERFACE_CLASS 0x0A
+
+/* Data interface class protocol codes */
+/* (usbcdc11.pdf, 4.7, Table 19) */
+#define CDC_DATA_PROTOCOL_ISDN_BRI            0x30
+#define CDC_DATA_PROTOCOL_HDLC                0x31
+#define CDC_DATA_PROTOCOL_TRANSPARENT         0x32
+#define CDC_DATA_PROTOCOL_Q921_MANAGEMENT     0x50
+#define CDC_DATA_PROTOCOL_Q921_DATA_LINK      0x51
+#define CDC_DATA_PROTOCOL_Q921_MULTIPLEXOR    0x52
+#define CDC_DATA_PROTOCOL_V42                 0x90
+#define CDC_DATA_PROTOCOL_EURO_ISDN           0x91
+#define CDC_DATA_PROTOCOL_V24_RATE_ADAPTATION 0x92
+#define CDC_DATA_PROTOCOL_CAPI                0x93
+#define CDC_DATA_PROTOCOL_HOST_BASED_DRIVER   0xFD
+#define CDC_DATA_PROTOCOL_DESCRIBED_IN_PUFD   0xFE
+
+/* Type values for bDescriptorType field of functional descriptors */
+/* (usbcdc11.pdf, 5.2.3, Table 24) */
+#define CDC_CS_INTERFACE 0x24
+#define CDC_CS_ENDPOINT  0x25
+
+/* Type values for bDescriptorSubtype field of functional descriptors */
+/* (usbcdc11.pdf, 5.2.3, Table 25) */
+#define CDC_FUNC_DESC_HEADER                          0x00
+#define CDC_FUNC_DESC_CALL_MANAGEMENT                 0x01
+#define CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT     0x02
+#define CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT          0x03
+#define CDC_FUNC_DESC_TELEPHONE_RINGER                0x04
+#define CDC_FUNC_DESC_REPORTING_CAPABILITIES          0x05
+#define CDC_FUNC_DESC_UNION                           0x06
+#define CDC_FUNC_DESC_COUNTRY_SELECTION               0x07
+#define CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES     0x08
+#define CDC_FUNC_DESC_USB_TERMINAL                    0x09
+#define CDC_FUNC_DESC_NETWORK_CHANNEL                 0x0A
+#define CDC_FUNC_DESC_PROTOCOL_UNIT                   0x0B
+#define CDC_FUNC_DESC_EXTENSION_UNIT                  0x0C
+#define CDC_FUNC_DESC_MULTI_CHANNEL_MANAGEMENT        0x0D
+#define CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT         0x0E
+#define CDC_FUNC_DESC_ETHERNET_NETWORKING             0x0F
+#define CDC_FUNC_DESC_ATM_NETWORKING                  0x10
+#define CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL  0x11
+#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL        0x12
+#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL 0x13
+#define CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL         0x14
+#define CDC_FUNC_DESC_OBEX                            0x15
+#define CDC_FUNC_DESC_COMMAND_SET                     0x16
+#define CDC_FUNC_DESC_COMMAND_SET_DETAIL              0x17
+#define CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL         0x18
+#define CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER         0x19
+
+/* CDC class-specific request codes */
+/* (usbcdc11.pdf, 6.2, Table 46) */
+/* see Table 45 for info about the specific requests. */
+#define CDC_REQUEST_SEND_ENCAPSULATED_COMMAND      0x00
+#define CDC_REQUEST_GET_ENCAPSULATED_RESPONSE      0x01
+#define CDC_REQUEST_SET_COMM_FEATURE               0x02
+#define CDC_REQUEST_GET_COMM_FEATURE               0x03
+#define CDC_REQUEST_CLEAR_COMM_FEATURE             0x04
+#define CDC_REQUEST_SET_AUX_LINE_STATE             0x10
+#define CDC_REQUEST_SET_HOOK_STATE                 0x11
+#define CDC_REQUEST_PULSE_SETUP                    0x12
+#define CDC_REQUEST_SEND_PULSE                     0x13
+#define CDC_REQUEST_SET_PULSE_TIME                 0x14
+#define CDC_REQUEST_RING_AUX_JACK                  0x15
+#define CDC_REQUEST_SET_LINE_CODING                0x20
+#define CDC_REQUEST_GET_LINE_CODING                0x21
+#define CDC_REQUEST_SET_CONTROL_LINE_STATE         0x22
+#define CDC_REQUEST_SEND_BREAK                     0x23
+#define CDC_REQUEST_SET_RINGER_PARMS               0x30
+#define CDC_REQUEST_GET_RINGER_PARMS               0x31
+#define CDC_REQUEST_SET_OPERATION_PARMS            0x32
+#define CDC_REQUEST_GET_OPERATION_PARMS            0x33
+#define CDC_REQUEST_SET_LINE_PARMS                 0x34
+#define CDC_REQUEST_GET_LINE_PARMS                 0x35
+#define CDC_REQUEST_DIAL_DIGITS                    0x36
+#define CDC_REQUEST_SET_UNIT_PARAMETER             0x37
+#define CDC_REQUEST_GET_UNIT_PARAMETER             0x38
+#define CDC_REQUEST_CLEAR_UNIT_PARAMETER           0x39
+#define CDC_REQUEST_GET_PROFILE                    0x3A
+#define CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS 0x40
+#define CDC_REQUEST_SET_ETHERNET_PMP_FILTER        0x41
+#define CDC_REQUEST_GET_ETHERNET_PMP_FILTER        0x42
+#define CDC_REQUEST_SET_ETHERNET_PACKET_FILTER     0x43
+#define CDC_REQUEST_GET_ETHERNET_STATISTIC         0x44
+#define CDC_REQUEST_SET_ATM_DATA_FORMAT            0x50
+#define CDC_REQUEST_GET_ATM_DEVICE_STATISTICS      0x51
+#define CDC_REQUEST_SET_ATM_DEFAULT_VC             0x52
+#define CDC_REQUEST_GET_ATM_VC_STATISTICS          0x53
+
+/* Communication feature selector codes */
+/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */
+#define CDC_ABSTRACT_STATE  0x01
+#define CDC_COUNTRY_SETTING 0x02
+
+/** Control Signal Bitmap Values for SetControlLineState */
+#define SET_CONTROL_LINE_STATE_RTS 0x02
+#define SET_CONTROL_LINE_STATE_DTR 0x01
+
+/* Feature Status returned for ABSTRACT_STATE Selector */
+/* (usbcdc11.pdf, 6.2.3, Table 48) */
+#define CDC_IDLE_SETTING          (1 << 0)
+#define CDC_DATA_MULTPLEXED_STATE (1 << 1)
+
+/* Control signal bitmap values for the SetControlLineState request */
+/* (usbcdc11.pdf, 6.2.14, Table 51) */
+#define CDC_DTE_PRESENT      (1 << 0)
+#define CDC_ACTIVATE_CARRIER (1 << 1)
+
+/* CDC class-specific notification codes */
+/* (usbcdc11.pdf, 6.3, Table 68) */
+/* see Table 67 for Info about class-specific notifications */
+#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00
+#define CDC_RESPONSE_AVAILABLE              0x01
+#define CDC_AUX_JACK_HOOK_STATE             0x08
+#define CDC_RING_DETECT                     0x09
+#define CDC_NOTIFICATION_SERIAL_STATE       0x20
+#define CDC_CALL_STATE_CHANGE               0x28
+#define CDC_LINE_STATE_CHANGE               0x29
+#define CDC_CONNECTION_SPEED_CHANGE         0x2A
+
+/* UART state bitmap values (Serial state notification). */
+/* (usbcdc11.pdf, 6.3.5, Table 69) */
+#define CDC_SERIAL_STATE_OVERRUN        (1 << 6) /* receive data overrun error has occurred */
+#define CDC_SERIAL_STATE_OVERRUN_Pos    (6)
+#define CDC_SERIAL_STATE_OVERRUN_Msk    (1 << CDC_SERIAL_STATE_OVERRUN_Pos)
+#define CDC_SERIAL_STATE_PARITY         (1 << 5) /* parity error has occurred */
+#define CDC_SERIAL_STATE_PARITY_Pos     (5)
+#define CDC_SERIAL_STATE_PARITY_Msk     (1 << CDC_SERIAL_STATE_PARITY_Pos)
+#define CDC_SERIAL_STATE_FRAMING        (1 << 4) /* framing error has occurred */
+#define CDC_SERIAL_STATE_FRAMING_Pos    (4)
+#define CDC_SERIAL_STATE_FRAMING_Msk    (1 << CDC_SERIAL_STATE_FRAMING_Pos)
+#define CDC_SERIAL_STATE_RING           (1 << 3) /* state of ring signal detection */
+#define CDC_SERIAL_STATE_RING_Pos       (3)
+#define CDC_SERIAL_STATE_RING_Msk       (1 << CDC_SERIAL_STATE_RING_Pos)
+#define CDC_SERIAL_STATE_BREAK          (1 << 2) /* state of break detection */
+#define CDC_SERIAL_STATE_BREAK_Pos      (2)
+#define CDC_SERIAL_STATE_BREAK_Msk      (1 << CDC_SERIAL_STATE_BREAK_Pos)
+#define CDC_SERIAL_STATE_TX_CARRIER     (1 << 1) /* state of transmission carrier */
+#define CDC_SERIAL_STATE_TX_CARRIER_Pos (1)
+#define CDC_SERIAL_STATE_TX_CARRIER_Msk (1 << CDC_SERIAL_STATE_TX_CARRIER_Pos)
+#define CDC_SERIAL_STATE_RX_CARRIER     (1 << 0) /* state of receiver carrier */
+#define CDC_SERIAL_STATE_RX_CARRIER_Pos (0)
+#define CDC_SERIAL_STATE_RX_CARRIER_Msk (1 << CDC_SERIAL_STATE_RX_CARRIER_Pos)
+
+/*------------------------------------------------------------------------------
+ *      Structures  based on usbcdc11.pdf (www.usb.org)
+ *----------------------------------------------------------------------------*/
+
+/* Header functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.1) */
+/* This header must precede any list of class-specific descriptors. */
+struct cdc_header_descriptor {
+    uint8_t bFunctionLength;    /* size of this descriptor in bytes */
+    uint8_t bDescriptorType;    /* CS_INTERFACE descriptor type */
+    uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */
+    uint16_t bcdCDC;            /* USB CDC specification release version */
+} __packed;
+
+/* Call management functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.2) */
+/* Describes the processing of calls for the communication class interface. */
+struct cdc_call_management_descriptor {
+    uint8_t bFunctionLength;    /* size of this descriptor in bytes */
+    uint8_t bDescriptorType;    /* CS_INTERFACE descriptor type */
+    uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */
+    uint8_t bmCapabilities;     /* capabilities that this configuration supports */
+    uint8_t bDataInterface;     /* interface number of the data class interface used for call management (optional) */
+} __packed;
+
+/* Abstract control management functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.3) */
+/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */
+struct cdc_abstract_control_management_descriptor {
+    uint8_t bFunctionLength;    /* size of this descriptor in bytes */
+    uint8_t bDescriptorType;    /* CS_INTERFACE descriptor type */
+    uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */
+    uint8_t bmCapabilities;     /* capabilities supported by this configuration */
+} __packed;
+
+/* Union functional descriptors */
+/* (usbcdc11.pdf, 5.2.3.8) */
+/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */
+struct cdc_union_descriptor {
+    uint8_t bFunctionLength;    /* size of this descriptor in bytes */
+    uint8_t bDescriptorType;    /* CS_INTERFACE descriptor type */
+    uint8_t bDescriptorSubtype; /* union functional descriptor subtype */
+    uint8_t bMasterInterface;   /* interface number designated as master */
+} __packed;
+
+/* Union functional descriptors with one slave interface */
+/* (usbcdc11.pdf, 5.2.3.8) */
+struct cdc_union_1slave_descriptor {
+    uint8_t bFunctionLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bControlInterface;
+    uint8_t bSubordinateInterface0;
+} __packed;
+
+/* Line coding structure for GET_LINE_CODING / SET_LINE_CODING class requests*/
+/* Format of the data returned when a GetLineCoding request is received */
+/* (usbcdc11.pdf, 6.2.13) */
+struct cdc_line_coding {
+    uint32_t dwDTERate;  /* Data terminal rate in bits per second */
+    uint8_t bCharFormat; /* Number of stop bits */
+    uint8_t bParityType; /* Parity bit type */
+    uint8_t bDataBits;   /* Number of data bits */
+} __packed;
+
+/** Data structure for the notification about SerialState */
+struct cdc_acm_notification {
+    uint8_t bmRequestType;
+    uint8_t bNotificationType;
+    uint16_t wValue;
+    uint16_t wIndex;
+    uint16_t wLength;
+    uint16_t data;
+} __packed;
+
+/** Ethernet Networking Functional Descriptor */
+struct cdc_ecm_descriptor {
+    uint8_t bFunctionLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t iMACAddress;
+    uint32_t bmEthernetStatistics;
+    uint16_t wMaxSegmentSize;
+    uint16_t wNumberMCFilters;
+    uint8_t bNumberPowerFilters;
+} __packed;
+
+/*Length of template descriptor: 66 bytes*/
+#define CDC_ACM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7)
+// clang-format off
+#define CDC_ACM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, str_idx)                   \
+    /* Interface Associate */                                                                      \
+    0x08,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION,             /* bDescriptorType */               \
+    bFirstInterface,                                       /* bFirstInterface */               \
+    0x02,                                                  /* bInterfaceCount */               \
+    USB_DEVICE_CLASS_CDC,                                  /* bFunctionClass */                \
+    CDC_ABSTRACT_CONTROL_MODEL,                            /* bFunctionSubClass */             \
+    CDC_COMMON_PROTOCOL_AT_COMMANDS,                       /* bFunctionProtocol */             \
+    0x00, /* iFunction */                                  /* CDC Control Interface */         \
+    0x09,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE,                         /* bDescriptorType */               \
+    bFirstInterface,                                       /* bInterfaceNumber */              \
+    0x00,                                                  /* bAlternateSetting */             \
+    0x01,                                                  /* bNumEndpoints */                 \
+    USB_DEVICE_CLASS_CDC,                                  /* bInterfaceClass */               \
+    CDC_ABSTRACT_CONTROL_MODEL,                            /* bInterfaceSubClass */            \
+    CDC_COMMON_PROTOCOL_AT_COMMANDS,                       /* bInterfaceProtocol */            \
+    str_idx, /* iInterface */                              /* CDC Header */                    \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_HEADER,                                  /* bDescriptorSubtype */            \
+    WBVAL(CDC_V1_10), /* bcdCDC */                         /* CDC Call */                      \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_CALL_MANAGEMENT,                         /* bDescriptorSubtype */            \
+    bFirstInterface,                                       /* bmCapabilities */                \
+    (uint8_t)(bFirstInterface + 1), /* bDataInterface */   /* CDC ACM: support line request */ \
+    0x04,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT,             /* bDescriptorSubtype */            \
+    0x02, /* bmCapabilities */                             /* CDC Union */                     \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_UNION,                                   /* bDescriptorSubtype */            \
+    bFirstInterface,                                       /* bMasterInterface */              \
+    (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ /* Endpoint Notification */         \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    int_ep,                                                /* bEndpointAddress */              \
+    0x03,                                                  /* bmAttributes */                  \
+    0x40, 0x00,                                            /* wMaxPacketSize */                \
+    0x01, /* bInterval */                                  /* CDC Data Interface */            \
+    0x09,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE,                         /* bDescriptorType */               \
+    (uint8_t)(bFirstInterface + 1),                        /* bInterfaceNumber */              \
+    0x00,                                                  /* bAlternateSetting */             \
+    0x02,                                                  /* bNumEndpoints */                 \
+    CDC_DATA_INTERFACE_CLASS,                              /* bInterfaceClass */               \
+    0x00,                                                  /* bInterfaceSubClass */            \
+    0x00,                                                  /* bInterfaceProtocol */            \
+    0x00, /* iInterface */                                 /* Endpoint Out */                  \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    out_ep,                                                /* bEndpointAddress */              \
+    0x02,                                                  /* bmAttributes */                  \
+    0x40, 0x00,                                            /* wMaxPacketSize */                \
+    0x01, /* bInterval */                                  /* Endpoint In */                   \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    in_ep,                                                 /* bEndpointAddress */              \
+    0x02,                                                  /* bmAttributes */                  \
+    0x40, 0x00,                                            /* wMaxPacketSize */                \
+    0x01                                                   /* bInterval */
+
+#define CDC_ACM_HS_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, str_idx)                   \
+    /* Interface Associate */                                                                      \
+    0x08,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION,             /* bDescriptorType */               \
+    bFirstInterface,                                       /* bFirstInterface */               \
+    0x02,                                                  /* bInterfaceCount */               \
+    USB_DEVICE_CLASS_CDC,                                  /* bFunctionClass */                \
+    CDC_ABSTRACT_CONTROL_MODEL,                            /* bFunctionSubClass */             \
+    CDC_COMMON_PROTOCOL_AT_COMMANDS,                       /* bFunctionProtocol */             \
+    0x00, /* iFunction */                                  /* CDC Control Interface */         \
+    0x09,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE,                         /* bDescriptorType */               \
+    bFirstInterface,                                       /* bInterfaceNumber */              \
+    0x00,                                                  /* bAlternateSetting */             \
+    0x01,                                                  /* bNumEndpoints */                 \
+    USB_DEVICE_CLASS_CDC,                                  /* bInterfaceClass */               \
+    CDC_ABSTRACT_CONTROL_MODEL,                            /* bInterfaceSubClass */            \
+    CDC_COMMON_PROTOCOL_AT_COMMANDS,                       /* bInterfaceProtocol */            \
+    str_idx, /* iInterface */                              /* CDC Header */                    \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_HEADER,                                  /* bDescriptorSubtype */            \
+    WBVAL(CDC_V1_10), /* bcdCDC */                         /* CDC Call */                      \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_CALL_MANAGEMENT,                         /* bDescriptorSubtype */            \
+    bFirstInterface,                                       /* bmCapabilities */                \
+    (uint8_t)(bFirstInterface + 1), /* bDataInterface */   /* CDC ACM: support line request */ \
+    0x04,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT,             /* bDescriptorSubtype */            \
+    0x02, /* bmCapabilities */                             /* CDC Union */                     \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_UNION,                                   /* bDescriptorSubtype */            \
+    bFirstInterface,                                       /* bMasterInterface */              \
+    (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ /* Endpoint Notification */         \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    int_ep,                                                /* bEndpointAddress */              \
+    0x03,                                                  /* bmAttributes */                  \
+    0x02, 0x00,                                            /* wMaxPacketSize */                \
+    0x01, /* bInterval */                                  /* CDC Data Interface */            \
+    0x09,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE,                         /* bDescriptorType */               \
+    (uint8_t)(bFirstInterface + 1),                        /* bInterfaceNumber */              \
+    0x00,                                                  /* bAlternateSetting */             \
+    0x02,                                                  /* bNumEndpoints */                 \
+    CDC_DATA_INTERFACE_CLASS,                              /* bInterfaceClass */               \
+    0x00,                                                  /* bInterfaceSubClass */            \
+    0x00,                                                  /* bInterfaceProtocol */            \
+    0x00, /* iInterface */                                 /* Endpoint Out */                  \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    out_ep,                                                /* bEndpointAddress */              \
+    0x02,                                                  /* bmAttributes */                  \
+    0x02, 0x00,                                            /* wMaxPacketSize */                \
+    0x01, /* bInterval */                                  /* Endpoint In */                   \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    in_ep,                                                 /* bEndpointAddress */              \
+    0x02,                                                  /* bmAttributes */                  \
+    0x02, 0x00,                                            /* wMaxPacketSize */                \
+    0x01                                                   /* bInterval */
+// clang-format on
+
+void usbd_cdc_add_acm_interface(usbd_class_t *class, usbd_interface_t *intf);
+
+void usbd_cdc_acm_set_line_coding(uint32_t baudrate, uint8_t databits, uint8_t parity, uint8_t stopbits);
+void usbd_cdc_acm_set_dtr(bool dtr);
+void usbd_cdc_acm_set_rts(bool rts);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_CDC_H_ */
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.c
new file mode 100644
index 0000000000000000000000000000000000000000..5c0caaf8c04ef5116c4296c84bc0db516da4942d
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.c
@@ -0,0 +1,286 @@
+/**
+ * @file usbd_hid.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_hid.h"
+
+#define HID_STATE_IDLE 0
+#define HID_STATE_BUSY 1
+
+struct usbd_hid_cfg_private {
+    const uint8_t *hid_descriptor;
+    const uint8_t *hid_report_descriptor;
+    uint32_t hid_report_descriptor_len;
+    uint8_t current_intf_num;
+    uint8_t hid_state;
+    uint8_t report;
+    uint8_t idle_state;
+    uint8_t protocol;
+
+    uint8_t (*get_report_callback)(uint8_t report_id, uint8_t report_type);
+    void (*set_report_callback)(uint8_t report_id, uint8_t report_type, uint8_t *report, uint8_t report_len);
+    uint8_t (*get_idle_callback)(uint8_t report_id);
+    void (*set_idle_callback)(uint8_t report_id, uint8_t duration);
+    void (*set_protocol_callback)(uint8_t protocol);
+    uint8_t (*get_protocol_callback)(void);
+
+    usb_slist_t list;
+} usbd_hid_cfg[4];
+
+static usb_slist_t usbd_hid_class_head = USB_SLIST_OBJECT_INIT(usbd_hid_class_head);
+
+static void usbd_hid_reset(void)
+{
+    usb_slist_t *i;
+    usb_slist_for_each(i, &usbd_hid_class_head)
+    {
+        struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+        hid_intf->hid_state = HID_STATE_IDLE;
+        hid_intf->report = 0;
+        hid_intf->idle_state = 0;
+        hid_intf->protocol = 0;
+    }
+}
+
+int hid_custom_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("Standard request:"
+                 "bmRequestType 0x%02x, bRequest 0x%02x, len %d\r\n",
+                 setup->bmRequestType, setup->bRequest, *len);
+
+    if (REQTYPE_GET_DIR(setup->bmRequestType) == USB_REQUEST_DEVICE_TO_HOST &&
+        setup->bRequest == USB_REQUEST_GET_DESCRIPTOR) {
+        uint8_t value = (uint8_t)(setup->wValue >> 8);
+        uint8_t intf_num = (uint8_t)setup->wIndex;
+
+        struct usbd_hid_cfg_private *current_hid_intf = NULL;
+        usb_slist_t *i;
+        usb_slist_for_each(i, &usbd_hid_class_head)
+        {
+            struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+
+            if (hid_intf->current_intf_num == intf_num) {
+                current_hid_intf = hid_intf;
+                break;
+            }
+        }
+
+        if (current_hid_intf == NULL) {
+            return -2;
+        }
+
+        switch (value) {
+            case HID_DESCRIPTOR_TYPE_HID:
+                USBD_LOG("get HID Descriptor\r\n");
+                *data = (uint8_t *)current_hid_intf->hid_descriptor;
+                *len = current_hid_intf->hid_descriptor[0];
+                break;
+
+            case HID_DESCRIPTOR_TYPE_HID_REPORT:
+                USBD_LOG("get Report Descriptor\r\n");
+                *data = (uint8_t *)current_hid_intf->hid_report_descriptor;
+                *len = current_hid_intf->hid_report_descriptor_len;
+                break;
+
+            case HID_DESCRIPTOR_TYPE_HID_PHYSICAL:
+                USBD_LOG_DBG("get PHYSICAL Descriptor\r\n");
+
+                break;
+
+            default:
+                return -2;
+        }
+
+        return 0;
+    }
+
+    return -1;
+}
+
+int hid_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG("Class request:"
+             "bmRequestType 0x%02x bRequest 0x%02x,  len %d\r\n",
+             setup->bmRequestType, setup->bRequest, *len);
+
+    struct usbd_hid_cfg_private *current_hid_intf = NULL;
+    usb_slist_t *i;
+    usb_slist_for_each(i, &usbd_hid_class_head)
+    {
+        struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+        uint8_t intf_num = (uint8_t)setup->wIndex;
+        if (hid_intf->current_intf_num == intf_num) {
+            current_hid_intf = hid_intf;
+            break;
+        }
+    }
+
+    if (current_hid_intf == NULL) {
+        return -2;
+    }
+
+    switch (setup->bRequest) {
+        case HID_REQUEST_GET_REPORT:
+            if (current_hid_intf->get_report_callback)
+                current_hid_intf->report = current_hid_intf->get_report_callback(setup->wValueL, setup->wValueH); /*report id ,report type*/
+
+            *data = (uint8_t *)¤t_hid_intf->report;
+            *len = 1;
+            break;
+        case HID_REQUEST_GET_IDLE:
+            if (current_hid_intf->get_idle_callback)
+                current_hid_intf->idle_state = current_hid_intf->get_idle_callback(setup->wValueL);
+
+            *data = (uint8_t *)¤t_hid_intf->idle_state;
+            *len = 1;
+            break;
+        case HID_REQUEST_GET_PROTOCOL:
+            if (current_hid_intf->get_protocol_callback)
+                current_hid_intf->protocol = current_hid_intf->get_protocol_callback();
+
+            *data = (uint8_t *)¤t_hid_intf->protocol;
+            *len = 1;
+            break;
+        case HID_REQUEST_SET_REPORT:
+            if (current_hid_intf->set_report_callback)
+                current_hid_intf->set_report_callback(setup->wValueL, setup->wValueH, *data, *len); /*report id ,report type,report,report len*/
+
+            current_hid_intf->report = **data;
+            break;
+        case HID_REQUEST_SET_IDLE:
+            if (current_hid_intf->set_idle_callback)
+                current_hid_intf->set_idle_callback(setup->wValueL, setup->wIndexH); /*report id ,duration*/
+
+            current_hid_intf->idle_state = setup->wIndexH;
+            break;
+        case HID_REQUEST_SET_PROTOCOL:
+            if (current_hid_intf->set_protocol_callback)
+                current_hid_intf->set_protocol_callback(setup->wValueL); /*protocol*/
+
+            current_hid_intf->protocol = setup->wValueL;
+            break;
+
+        default:
+            USBD_LOG_ERR("Unhandled request 0x%02x\r\n", setup->bRequest);
+            break;
+    }
+
+    return 0;
+}
+
+static void hid_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_hid_reset();
+            break;
+
+        default:
+            break;
+    }
+}
+
+void usbd_hid_reset_state(void)
+{
+    // usbd_hid_cfg.hid_state = HID_STATE_IDLE;
+}
+
+void usbd_hid_send_report(uint8_t ep, uint8_t *data, uint8_t len)
+{
+    // if(usbd_hid_cfg.hid_state == HID_STATE_IDLE)
+    // {
+    //     usbd_hid_cfg.hid_state = HID_STATE_BUSY;
+    //     usbd_ep_write(ep, data, len, NULL);
+    // }
+}
+
+void usbd_hid_descriptor_register(uint8_t intf_num, const uint8_t *desc)
+{
+    // usbd_hid_cfg.hid_descriptor = desc;
+}
+
+void usbd_hid_report_descriptor_register(uint8_t intf_num, const uint8_t *desc, uint32_t desc_len)
+{
+    usb_slist_t *i;
+    usb_slist_for_each(i, &usbd_hid_class_head)
+    {
+        struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+
+        if (hid_intf->current_intf_num == intf_num) {
+            hid_intf->hid_report_descriptor = desc;
+            hid_intf->hid_report_descriptor_len = desc_len;
+            return;
+        }
+    }
+}
+// clang-format off
+void usbd_hid_set_request_callback( uint8_t intf_num,
+                                    uint8_t (*get_report_callback)(uint8_t report_id, uint8_t report_type),
+                                    void (*set_report_callback)(uint8_t report_id, uint8_t report_type, uint8_t *report, uint8_t report_len),
+                                    uint8_t (*get_idle_callback)(uint8_t report_id),
+                                    void (*set_idle_callback)(uint8_t report_id, uint8_t duration),
+                                    void (*set_protocol_callback)(uint8_t protocol),
+                                    uint8_t (*get_protocol_callback)(void))
+// clang-format on
+{
+    usb_slist_t *i;
+    usb_slist_for_each(i, &usbd_hid_class_head)
+    {
+        struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+
+        if (hid_intf->current_intf_num == intf_num) {
+            if (get_report_callback)
+                hid_intf->get_report_callback = get_report_callback;
+            if (set_report_callback)
+                hid_intf->set_report_callback = set_report_callback;
+            if (get_idle_callback)
+                hid_intf->get_idle_callback = get_idle_callback;
+            if (set_idle_callback)
+                hid_intf->set_idle_callback = set_idle_callback;
+            if (set_protocol_callback)
+                hid_intf->set_protocol_callback = set_protocol_callback;
+            if (get_protocol_callback)
+                hid_intf->get_protocol_callback = get_protocol_callback;
+            return;
+        }
+    }
+}
+
+void usbd_hid_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+    static uint8_t hid_num = 0;
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = hid_class_request_handler;
+    intf->custom_handler = hid_custom_request_handler;
+    intf->vendor_handler = NULL;
+    intf->notify_handler = hid_notify_handler;
+    usbd_class_add_interface(class, intf);
+
+    usbd_hid_cfg[hid_num].current_intf_num = intf->intf_num;
+    usb_slist_add_tail(&usbd_hid_class_head, &usbd_hid_cfg[hid_num].list);
+    hid_num++;
+}
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.h
new file mode 100644
index 0000000000000000000000000000000000000000..03d4a88cdcb9bccac6de42673dc4c7bddacad37c
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.h
@@ -0,0 +1,352 @@
+/**
+ * @file
+ * @brief USB Human Interface Device (HID) Class public header
+ *
+ * Header follows Device Class Definition for Human Interface Devices (HID)
+ * Version 1.11 document (HID1_11-1.pdf).
+ */
+#ifndef _USBD_HID_H_
+#define _USBD_HID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* HID Class Descriptor Types */
+#define HID_DESCRIPTOR_TYPE_HID          0x21
+#define HID_DESCRIPTOR_TYPE_HID_REPORT   0x22
+#define HID_DESCRIPTOR_TYPE_HID_PHYSICAL 0x23
+
+/* HID Class Specific Requests */
+#define HID_REQUEST_GET_REPORT   0x01
+#define HID_REQUEST_GET_IDLE     0x02
+#define HID_REQUEST_GET_PROTOCOL 0x03
+#define HID_REQUEST_SET_REPORT   0x09
+#define HID_REQUEST_SET_IDLE     0x0A
+#define HID_REQUEST_SET_PROTOCOL 0x0B
+
+/* HID Report Definitions */
+struct usb_hid_class_subdescriptor {
+    uint8_t bDescriptorType;
+    uint16_t wDescriptorLength;
+} __packed;
+
+struct usb_hid_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t bcdHID;
+    uint8_t bCountryCode;
+    uint8_t bNumDescriptors;
+
+    /*
+     * Specification says at least one Class Descriptor needs to
+     * be present (Report Descriptor).
+     */
+    struct usb_hid_class_subdescriptor subdesc[1];
+} __packed;
+
+/* HID Items types */
+#define ITEM_MAIN   0x0
+#define ITEM_GLOBAL 0x1
+#define ITEM_LOCAL  0x2
+
+/* HID Main Items tags */
+#define ITEM_TAG_INPUT          0x8
+#define ITEM_TAG_OUTPUT         0x9
+#define ITEM_TAG_COLLECTION     0xA
+#define ITEM_TAG_COLLECTION_END 0xC
+
+/* HID Global Items tags */
+#define ITEM_TAG_USAGE_PAGE   0x0
+#define ITEM_TAG_LOGICAL_MIN  0x1
+#define ITEM_TAG_LOGICAL_MAX  0x2
+#define ITEM_TAG_REPORT_SIZE  0x7
+#define ITEM_TAG_REPORT_ID    0x8
+#define ITEM_TAG_REPORT_COUNT 0x9
+
+/* HID Local Items tags */
+#define ITEM_TAG_USAGE     0x0
+#define ITEM_TAG_USAGE_MIN 0x1
+#define ITEM_TAG_USAGE_MAX 0x2
+
+#define HID_ITEM(bTag, bType, bSize) (((bTag & 0xF) << 4) | \
+                                      ((bType & 0x3) << 2) | (bSize & 0x3))
+
+#define HID_MAIN_ITEM(bTag, bSize)   HID_ITEM(bTag, ITEM_MAIN, bSize)
+#define HID_GLOBAL_ITEM(bTag, bSize) HID_ITEM(bTag, ITEM_GLOBAL, bSize)
+#define HID_LOCAL_ITEM(bTag, bSize)  HID_ITEM(bTag, ITEM_LOCAL, bSize)
+
+#define HID_MI_COLLECTION     HID_MAIN_ITEM(ITEM_TAG_COLLECTION, 1)
+#define HID_MI_COLLECTION_END HID_MAIN_ITEM(ITEM_TAG_COLLECTION_END, \
+                                            0)
+#define HID_MI_INPUT  HID_MAIN_ITEM(ITEM_TAG_INPUT, 1)
+#define HID_MI_OUTPUT HID_MAIN_ITEM(ITEM_TAG_OUTPUT, 1)
+
+#define HID_GI_USAGE_PAGE        HID_GLOBAL_ITEM(ITEM_TAG_USAGE_PAGE, 1)
+#define HID_GI_LOGICAL_MIN(size) HID_GLOBAL_ITEM(ITEM_TAG_LOGICAL_MIN, \
+                                                 size)
+#define HID_GI_LOGICAL_MAX(size) HID_GLOBAL_ITEM(ITEM_TAG_LOGICAL_MAX, \
+                                                 size)
+#define HID_GI_REPORT_SIZE HID_GLOBAL_ITEM(ITEM_TAG_REPORT_SIZE, \
+                                           1)
+#define HID_GI_REPORT_ID HID_GLOBAL_ITEM(ITEM_TAG_REPORT_ID, \
+                                         1)
+#define HID_GI_REPORT_COUNT HID_GLOBAL_ITEM(ITEM_TAG_REPORT_COUNT, \
+                                            1)
+
+#define HID_LI_USAGE           HID_LOCAL_ITEM(ITEM_TAG_USAGE, 1)
+#define HID_LI_USAGE_MIN(size) HID_LOCAL_ITEM(ITEM_TAG_USAGE_MIN, \
+                                              size)
+#define HID_LI_USAGE_MAX(size) HID_LOCAL_ITEM(ITEM_TAG_USAGE_MAX, \
+                                              size)
+
+/* Defined in Universal Serial Bus HID Usage Tables version 1.11 */
+#define USAGE_GEN_DESKTOP  0x01
+#define USAGE_GEN_KEYBOARD 0x07
+#define USAGE_GEN_LEDS     0x08
+#define USAGE_GEN_BUTTON   0x09
+
+/* Generic Desktop Page usages */
+#define USAGE_GEN_DESKTOP_UNDEFINED 0x00
+#define USAGE_GEN_DESKTOP_POINTER   0x01
+#define USAGE_GEN_DESKTOP_MOUSE     0x02
+#define USAGE_GEN_DESKTOP_JOYSTICK  0x04
+#define USAGE_GEN_DESKTOP_GAMEPAD   0x05
+#define USAGE_GEN_DESKTOP_KEYBOARD  0x06
+#define USAGE_GEN_DESKTOP_KEYPAD    0x07
+#define USAGE_GEN_DESKTOP_X         0x30
+#define USAGE_GEN_DESKTOP_Y         0x31
+#define USAGE_GEN_DESKTOP_WHEEL     0x38
+
+/* Collection types */
+#define COLLECTION_PHYSICAL    0x00
+#define COLLECTION_APPLICATION 0x01
+
+/* Protocols */
+#define HID_PROTOCOL_BOOT   0x00
+#define HID_PROTOCOL_REPORT 0x01
+
+/* Example HID report descriptors */
+/**
+ * @brief Simple HID mouse report descriptor for n button mouse.
+ *
+ * @param bcnt  Button count. Allowed values from 1 to 8.
+ */
+#define HID_MOUSE_REPORT_DESC(bcnt)                                                                                          \
+    {                                                                                                                        \
+        /* USAGE_PAGE (Generic Desktop) */                                                                                   \
+        HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP,                                             /* USAGE (Mouse) */                \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_MOUSE,                                        /* COLLECTION (Application) */     \
+            HID_MI_COLLECTION, COLLECTION_APPLICATION,                                    /* USAGE (Pointer) */              \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_POINTER,                                      /* COLLECTION (Physical) */        \
+            HID_MI_COLLECTION, COLLECTION_PHYSICAL, /* Bits used for button signalling */ /* USAGE_PAGE (Button) */          \
+            HID_GI_USAGE_PAGE, USAGE_GEN_BUTTON,                                          /* USAGE_MINIMUM (Button 1) */     \
+            HID_LI_USAGE_MIN(1), 0x01,                                                    /* USAGE_MAXIMUM (Button bcnt) */  \
+            HID_LI_USAGE_MAX(1), bcnt,                                                    /* LOGICAL_MINIMUM (0) */          \
+            HID_GI_LOGICAL_MIN(1), 0x00,                                                  /* LOGICAL_MAXIMUM (1) */          \
+            HID_GI_LOGICAL_MAX(1), 0x01,                                                  /* REPORT_SIZE (1) */              \
+            HID_GI_REPORT_SIZE, 0x01,                                                     /* REPORT_COUNT (bcnt) */          \
+            HID_GI_REPORT_COUNT, bcnt,                                                    /* INPUT (Data,Var,Abs) */         \
+            HID_MI_INPUT, 0x02, /* Unused bits */                                         /* REPORT_SIZE (8 - bcnt) */       \
+            HID_GI_REPORT_SIZE, (8 - bcnt),                                               /* REPORT_COUNT (1) */             \
+            HID_GI_REPORT_COUNT, 0x01,                                                    /* INPUT (Cnst,Ary,Abs) */         \
+            HID_MI_INPUT, 0x01, /* X and Y axis, scroll */                                /* USAGE_PAGE (Generic Desktop) */ \
+            HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP,                                         /* USAGE (X) */                    \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_X,                                            /* USAGE (Y) */                    \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_Y,                                            /* USAGE (WHEEL) */                \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_WHEEL,                                        /* LOGICAL_MINIMUM (-127) */       \
+            HID_GI_LOGICAL_MIN(1), -127,                                                  /* LOGICAL_MAXIMUM (127) */        \
+            HID_GI_LOGICAL_MAX(1), 127,                                                   /* REPORT_SIZE (8) */              \
+            HID_GI_REPORT_SIZE, 0x08,                                                     /* REPORT_COUNT (3) */             \
+            HID_GI_REPORT_COUNT, 0x03,                                                    /* INPUT (Data,Var,Rel) */         \
+            HID_MI_INPUT, 0x06,                                                           /* END_COLLECTION */               \
+            HID_MI_COLLECTION_END,                                                        /* END_COLLECTION */               \
+            HID_MI_COLLECTION_END,                                                                                           \
+    }
+
+/**
+ * @brief Simple HID keyboard report descriptor.
+ */
+#define HID_KEYBOARD_REPORT_DESC()                                                                  \
+    {                                                                                               \
+        /* USAGE_PAGE (Generic Desktop) */                                                          \
+        HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP,            /* USAGE (Keyboard) */                     \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_KEYBOARD,    /* COLLECTION (Application) */             \
+            HID_MI_COLLECTION, COLLECTION_APPLICATION,   /* USAGE_PAGE (Keypad) */                  \
+            HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP_KEYPAD, /* USAGE_MINIMUM (Keyboard LeftControl) */ \
+            HID_LI_USAGE_MIN(1), 0xE0,                   /* USAGE_MAXIMUM (Keyboard Right GUI) */   \
+            HID_LI_USAGE_MAX(1), 0xE7,                   /* LOGICAL_MINIMUM (0) */                  \
+            HID_GI_LOGICAL_MIN(1), 0x00,                 /* LOGICAL_MAXIMUM (1) */                  \
+            HID_GI_LOGICAL_MAX(1), 0x01,                 /* REPORT_SIZE (1) */                      \
+            HID_GI_REPORT_SIZE, 0x01,                    /* REPORT_COUNT (8) */                     \
+            HID_GI_REPORT_COUNT, 0x08,                   /* INPUT (Data,Var,Abs) */                 \
+            HID_MI_INPUT, 0x02,                          /* REPORT_SIZE (8) */                      \
+            HID_GI_REPORT_SIZE, 0x08,                    /* REPORT_COUNT (1) */                     \
+            HID_GI_REPORT_COUNT, 0x01,                   /* INPUT (Cnst,Var,Abs) */                 \
+            HID_MI_INPUT, 0x03,                          /* REPORT_SIZE (1) */                      \
+            HID_GI_REPORT_SIZE, 0x01,                    /* REPORT_COUNT (5) */                     \
+            HID_GI_REPORT_COUNT, 0x05,                   /* USAGE_PAGE (LEDs) */                    \
+            HID_GI_USAGE_PAGE, USAGE_GEN_LEDS,           /* USAGE_MINIMUM (Num Lock) */             \
+            HID_LI_USAGE_MIN(1), 0x01,                   /* USAGE_MAXIMUM (Kana) */                 \
+            HID_LI_USAGE_MAX(1), 0x05,                   /* OUTPUT (Data,Var,Abs) */                \
+            HID_MI_OUTPUT, 0x02,                         /* REPORT_SIZE (3) */                      \
+            HID_GI_REPORT_SIZE, 0x03,                    /* REPORT_COUNT (1) */                     \
+            HID_GI_REPORT_COUNT, 0x01,                   /* OUTPUT (Cnst,Var,Abs) */                \
+            HID_MI_OUTPUT, 0x03,                         /* REPORT_SIZE (8) */                      \
+            HID_GI_REPORT_SIZE, 0x08,                    /* REPORT_COUNT (6) */                     \
+            HID_GI_REPORT_COUNT, 0x06,                   /* LOGICAL_MINIMUM (0) */                  \
+            HID_GI_LOGICAL_MIN(1), 0x00,                 /* LOGICAL_MAXIMUM (101) */                \
+            HID_GI_LOGICAL_MAX(1), 0x65,                 /* USAGE_PAGE (Keypad) */                  \
+            HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP_KEYPAD, /* USAGE_MINIMUM (Reserved) */             \
+            HID_LI_USAGE_MIN(1), 0x00,                   /* USAGE_MAXIMUM (Keyboard Application) */ \
+            HID_LI_USAGE_MAX(1), 0x65,                   /* INPUT (Data,Ary,Abs) */                 \
+            HID_MI_INPUT, 0x00,                          /* END_COLLECTION */                       \
+            HID_MI_COLLECTION_END,                                                                  \
+    }
+
+/**
+ * @brief HID keyboard button codes.
+ */
+enum hid_kbd_code {
+    HID_KEY_A = 4,
+    HID_KEY_B = 5,
+    HID_KEY_C = 6,
+    HID_KEY_D = 7,
+    HID_KEY_E = 8,
+    HID_KEY_F = 9,
+    HID_KEY_G = 10,
+    HID_KEY_H = 11,
+    HID_KEY_I = 12,
+    HID_KEY_J = 13,
+    HID_KEY_K = 14,
+    HID_KEY_L = 15,
+    HID_KEY_M = 16,
+    HID_KEY_N = 17,
+    HID_KEY_O = 18,
+    HID_KEY_P = 19,
+    HID_KEY_Q = 20,
+    HID_KEY_R = 21,
+    HID_KEY_S = 22,
+    HID_KEY_T = 23,
+    HID_KEY_U = 24,
+    HID_KEY_V = 25,
+    HID_KEY_W = 26,
+    HID_KEY_X = 27,
+    HID_KEY_Y = 28,
+    HID_KEY_Z = 29,
+    HID_KEY_1 = 30,
+    HID_KEY_2 = 31,
+    HID_KEY_3 = 32,
+    HID_KEY_4 = 33,
+    HID_KEY_5 = 34,
+    HID_KEY_6 = 35,
+    HID_KEY_7 = 36,
+    HID_KEY_8 = 37,
+    HID_KEY_9 = 38,
+    HID_KEY_0 = 39,
+    HID_KEY_ENTER = 40,
+    HID_KEY_ESC = 41,
+    HID_KEY_BACKSPACE = 42,
+    HID_KEY_TAB = 43,
+    HID_KEY_SPACE = 44,
+    HID_KEY_MINUS = 45,
+    HID_KEY_EQUAL = 46,
+    HID_KEY_LEFTBRACE = 47,
+    HID_KEY_RIGHTBRACE = 48,
+    HID_KEY_BACKSLASH = 49,
+    HID_KEY_HASH = 50, /* Non-US # and ~ */
+    HID_KEY_SEMICOLON = 51,
+    HID_KEY_APOSTROPHE = 52,
+    HID_KEY_GRAVE = 53,
+    HID_KEY_COMMA = 54,
+    HID_KEY_DOT = 55,
+    HID_KEY_SLASH = 56,
+    HID_KEY_CAPSLOCK = 57,
+    HID_KEY_F1 = 58,
+    HID_KEY_F2 = 59,
+    HID_KEY_F3 = 60,
+    HID_KEY_F4 = 61,
+    HID_KEY_F5 = 62,
+    HID_KEY_F6 = 63,
+    HID_KEY_F7 = 64,
+    HID_KEY_F8 = 65,
+    HID_KEY_F9 = 66,
+    HID_KEY_F10 = 67,
+    HID_KEY_F11 = 68,
+    HID_KEY_F12 = 69,
+    HID_KEY_SYSRQ = 70, /* PRINTSCREEN */
+    HID_KEY_SCROLLLOCK = 71,
+    HID_KEY_PAUSE = 72,
+    HID_KEY_INSERT = 73,
+    HID_KEY_HOME = 74,
+    HID_KEY_PAGEUP = 75,
+    HID_KEY_DELETE = 76,
+    HID_KEY_END = 77,
+    HID_KEY_PAGEDOWN = 78,
+    HID_KEY_RIGHT = 79,
+    HID_KEY_LEFT = 80,
+    HID_KEY_DOWN = 81,
+    HID_KEY_UP = 82,
+    HID_KEY_NUMLOCK = 83,
+    HID_KEY_KPSLASH = 84,    /* NUMPAD DIVIDE */
+    HID_KEY_KPASTERISK = 85, /* NUMPAD MULTIPLY */
+    HID_KEY_KPMINUS = 86,
+    HID_KEY_KPPLUS = 87,
+    HID_KEY_KPENTER = 88,
+    HID_KEY_KP_1 = 89,
+    HID_KEY_KP_2 = 90,
+    HID_KEY_KP_3 = 91,
+    HID_KEY_KP_4 = 92,
+    HID_KEY_KP_5 = 93,
+    HID_KEY_KP_6 = 94,
+    HID_KEY_KP_7 = 95,
+    HID_KEY_KP_8 = 96,
+    HID_KEY_KP_9 = 97,
+    HID_KEY_KP_0 = 98,
+};
+
+/**
+ * @brief HID keyboard modifiers.
+ */
+enum hid_kbd_modifier {
+    HID_KBD_MODIFIER_NONE = 0x00,
+    HID_KBD_MODIFIER_LEFT_CTRL = 0x01,
+    HID_KBD_MODIFIER_LEFT_SHIFT = 0x02,
+    HID_KBD_MODIFIER_LEFT_ALT = 0x04,
+    HID_KBD_MODIFIER_LEFT_UI = 0x08,
+    HID_KBD_MODIFIER_RIGHT_CTRL = 0x10,
+    HID_KBD_MODIFIER_RIGHT_SHIFT = 0x20,
+    HID_KBD_MODIFIER_RIGHT_ALT = 0x40,
+    HID_KBD_MODIFIER_RIGHT_UI = 0x80,
+};
+
+/**
+ * @brief HID keyboard LEDs.
+ */
+enum hid_kbd_led {
+    HID_KBD_LED_NUM_LOCK = 0x01,
+    HID_KBD_LED_CAPS_LOCK = 0x02,
+    HID_KBD_LED_SCROLL_LOCK = 0x04,
+    HID_KBD_LED_COMPOSE = 0x08,
+    HID_KBD_LED_KANA = 0x10,
+};
+
+void usbd_hid_descriptor_register(uint8_t intf_num, const uint8_t *desc);
+void usbd_hid_report_descriptor_register(uint8_t intf_num, const uint8_t *desc, uint32_t desc_len);
+void usbd_hid_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+void usbd_hid_reset_state(void);
+void usbd_hid_send_report(uint8_t ep, uint8_t *data, uint8_t len);
+// clang-format off
+void usbd_hid_set_request_callback( uint8_t intf_num,
+                                    uint8_t (*get_report_callback)(uint8_t report_id, uint8_t report_type),
+                                    void (*set_report_callback)(uint8_t report_id, uint8_t report_type, uint8_t *report, uint8_t report_len),
+                                    uint8_t (*get_idle_callback)(uint8_t report_id),
+                                    void (*set_idle_callback)(uint8_t report_id, uint8_t duration),
+                                    void (*set_protocol_callback)(uint8_t protocol),
+                                    uint8_t (*get_protocol_callback)(void));
+// clang-format on
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _USB_HID_H_ */
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.c
new file mode 100644
index 0000000000000000000000000000000000000000..3e4ae1d5fe5b00e87157178e2d98baaf40cacef4
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.c
@@ -0,0 +1,838 @@
+/**
+ * @file usbd_msc.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_scsi.h"
+#include "usbd_msc.h"
+
+/* max USB packet size */
+#define MASS_STORAGE_BULK_EP_MPS 64
+#define MASS_STORAGE_BLOCK_SIZE  512
+
+#define MSD_OUT_EP_IDX 0
+#define MSD_IN_EP_IDX  1
+
+/* Describe EndPoints configuration */
+static usbd_endpoint_t mass_ep_data[2];
+
+/* MSC Bulk-only Stage */
+enum Stage {
+    /* MSC Bulk-only Stage */
+    MSC_BS_CBW = 0,                /* Command Block Wrapper */
+    MSC_BS_DATA_OUT = 1,           /* Data Out Phase */
+    MSC_BS_DATA_IN = 2,            /* Data In Phase */
+    MSC_BS_DATA_IN_LAST = 3,       /* Data In Last Phase */
+    MSC_BS_DATA_IN_LAST_STALL = 4, /* Data In Last Phase with Stall */
+    MSC_BS_CSW = 5,                /* Command Status Wrapper */
+    MSC_BS_ERROR = 6,              /* Error */
+    MSC_BS_RESET = 7,              /* Bulk-Only Mass Storage Reset */
+};
+
+/* Device data structure */
+struct usbd_msc_cfg_private {
+    /* state of the bulk-only state machine */
+    enum Stage stage;
+    struct CBW cbw;
+    struct CSW csw;
+
+    uint8_t max_lun_count;
+    uint16_t scsi_blk_size;
+    uint32_t scsi_blk_nbr;
+
+    uint32_t scsi_blk_addr;
+    uint32_t scsi_blk_len;
+    uint8_t block_buffer[MASS_STORAGE_BLOCK_SIZE];
+
+} usbd_msc_cfg;
+
+/*memory OK (after a usbd_msc_memory_verify)*/
+static bool memOK;
+
+static void usbd_msc_reset(void)
+{
+    usbd_msc_cfg.stage = MSC_BS_CBW;
+    (void)memset((void *)&usbd_msc_cfg.cbw, 0, sizeof(struct CBW));
+    (void)memset((void *)&usbd_msc_cfg.csw, 0, sizeof(struct CSW));
+    usbd_msc_cfg.scsi_blk_addr = 0U;
+    usbd_msc_cfg.scsi_blk_len = 0U;
+    usbd_msc_get_cap(0, &usbd_msc_cfg.scsi_blk_nbr, &usbd_msc_cfg.scsi_blk_size);
+    usbd_msc_cfg.max_lun_count = 0;
+}
+
+/**
+ * @brief Handler called for Class requests not handled by the USB stack.
+ *
+ * @param pSetup    Information about the request to execute.
+ * @param len       Size of the buffer.
+ * @param data      Buffer containing the request result.
+ *
+ * @return  0 on success, negative errno code on fail.
+ */
+static int msc_storage_class_request_handler(struct usb_setup_packet *pSetup, uint8_t **data, uint32_t *len)
+{
+    switch (pSetup->bRequest) {
+        case MSC_REQUEST_RESET:
+            USBD_LOG_DBG("MSC_REQUEST_RESET");
+
+            if (pSetup->wLength) {
+                USBD_LOG_WRN("Invalid length");
+                return -1;
+            }
+
+            usbd_msc_reset();
+            break;
+
+        case MSC_REQUEST_GET_MAX_LUN:
+            USBD_LOG_DBG("MSC_REQUEST_GET_MAX_LUN");
+
+            if (pSetup->wLength != 1) {
+                USBD_LOG_WRN("Invalid length");
+                return -1;
+            }
+
+            *data = (uint8_t *)(&usbd_msc_cfg.max_lun_count);
+            *len = 1;
+            break;
+
+        default:
+            USBD_LOG_WRN("Unknown request 0x%02x, value 0x%02x",
+                         pSetup->bRequest, pSetup->wValue);
+            return -1;
+    }
+
+    return 0;
+}
+
+static void usbd_msc_send_csw(void)
+{
+    usbd_msc_cfg.csw.Signature = MSC_CSW_Signature;
+
+    if (usbd_ep_write(mass_ep_data[MSD_IN_EP_IDX].ep_addr, (uint8_t *)&usbd_msc_cfg.csw,
+                      sizeof(struct CSW), NULL) != 0) {
+        USBD_LOG_ERR("usb write failure");
+    }
+
+    usbd_msc_cfg.stage = MSC_BS_CSW;
+}
+
+static bool usbd_msc_datain_check(void)
+{
+    if (!usbd_msc_cfg.cbw.DataLength) {
+        USBD_LOG_WRN("Zero length in CBW");
+        //SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
+        usbd_msc_cfg.csw.Status = CSW_STATUS_PHASE_ERROR;
+        usbd_msc_send_csw();
+        return false;
+    }
+
+    if ((usbd_msc_cfg.cbw.Flags & 0x80) == 0) {
+        usbd_ep_set_stall(mass_ep_data[MSD_OUT_EP_IDX].ep_addr);
+        usbd_msc_cfg.csw.Status = CSW_STATUS_PHASE_ERROR;
+        usbd_msc_send_csw();
+        return false;
+    }
+
+    return true;
+}
+
+static bool usbd_msc_send_to_host(uint8_t *buffer, uint16_t size)
+{
+    if (size >= usbd_msc_cfg.cbw.DataLength) {
+        size = usbd_msc_cfg.cbw.DataLength;
+        usbd_msc_cfg.stage = MSC_BS_DATA_IN_LAST;
+    } else {
+        usbd_msc_cfg.stage = MSC_BS_DATA_IN_LAST_STALL;
+    }
+
+    if (usbd_ep_write(mass_ep_data[MSD_IN_EP_IDX].ep_addr, buffer, size, NULL)) {
+        USBD_LOG_ERR("USB write failed\r\n");
+        return false;
+    }
+
+    usbd_msc_cfg.csw.DataResidue -= size;
+    usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_PASSED;
+
+    return true;
+}
+
+static void usbd_msc_memory_verify(uint8_t *buf, uint16_t size)
+{
+    uint32_t n;
+
+    if ((usbd_msc_cfg.scsi_blk_addr + size) > (usbd_msc_cfg.scsi_blk_nbr * usbd_msc_cfg.scsi_blk_size)) {
+        size = usbd_msc_cfg.scsi_blk_nbr * usbd_msc_cfg.scsi_blk_size - usbd_msc_cfg.scsi_blk_addr;
+        usbd_msc_cfg.stage = MSC_BS_ERROR;
+        usbd_ep_set_stall(mass_ep_data[MSD_OUT_EP_IDX].ep_addr);
+        USBD_LOG_WRN("addr overflow,verify error\r\n");
+    }
+
+    /* beginning of a new block -> load a whole block in RAM */
+    if (!(usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size)) {
+        USBD_LOG_DBG("Disk READ sector %d", usbd_msc_cfg.scsi_blk_addr / usbd_msc_cfg.scsi_blk_size);
+        // if (disk_access_read(disk_pdrv, page, addr / BLOCK_SIZE, 1))
+        // {
+        //  USBD_LOG_ERR("---- Disk Read Error %d", addr / BLOCK_SIZE);
+        // }
+    }
+
+    /* info are in RAM -> no need to re-read memory */
+    for (n = 0U; n < size; n++) {
+        if (usbd_msc_cfg.block_buffer[usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size + n] != buf[n]) {
+            USBD_LOG_DBG("Mismatch sector %d offset %d",
+                         usbd_msc_cfg.scsi_blk_addr / usbd_msc_cfg.scsi_blk_size, n);
+            memOK = false;
+            break;
+        }
+    }
+
+    usbd_msc_cfg.scsi_blk_addr += size;
+    usbd_msc_cfg.scsi_blk_len -= size;
+    usbd_msc_cfg.csw.DataResidue -= size;
+
+    if (!usbd_msc_cfg.scsi_blk_len || (usbd_msc_cfg.stage == MSC_BS_CSW)) {
+        usbd_msc_cfg.csw.Status = (memOK) ? CSW_STATUS_CMD_PASSED : CSW_STATUS_CMD_FAILED;
+        usbd_msc_send_csw();
+    }
+}
+
+static void usbd_msc_memory_write(uint8_t *buf, uint16_t size)
+{
+    USBD_LOG_DBG("w:%d\r\n", usbd_msc_cfg.scsi_blk_addr);
+
+    if ((usbd_msc_cfg.scsi_blk_addr + size) > (usbd_msc_cfg.scsi_blk_nbr * usbd_msc_cfg.scsi_blk_size)) {
+        size = usbd_msc_cfg.scsi_blk_nbr * usbd_msc_cfg.scsi_blk_size - usbd_msc_cfg.scsi_blk_addr;
+        usbd_msc_cfg.stage = MSC_BS_ERROR;
+        usbd_ep_set_stall(mass_ep_data[MSD_OUT_EP_IDX].ep_addr);
+        USBD_LOG_WRN("addr overflow,write error\r\n");
+    }
+
+    /* we fill an array in RAM of 1 block before writing it in memory */
+    for (int i = 0; i < size; i++) {
+        usbd_msc_cfg.block_buffer[usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size + i] = buf[i];
+    }
+
+    /* if the array is filled, write it in memory */
+    if ((usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size) + size >= usbd_msc_cfg.scsi_blk_size) {
+        usbd_msc_sector_write((usbd_msc_cfg.scsi_blk_addr / usbd_msc_cfg.scsi_blk_size), usbd_msc_cfg.block_buffer, usbd_msc_cfg.scsi_blk_size);
+    }
+
+    usbd_msc_cfg.scsi_blk_addr += size;
+    usbd_msc_cfg.scsi_blk_len -= size;
+    usbd_msc_cfg.csw.DataResidue -= size;
+
+    if ((!usbd_msc_cfg.scsi_blk_len) || (usbd_msc_cfg.stage == MSC_BS_CSW)) {
+        usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_PASSED;
+        usbd_msc_send_csw();
+    }
+}
+
+static void usbd_msc_memory_read(void)
+{
+    uint32_t transfer_len;
+
+    transfer_len = MIN(usbd_msc_cfg.scsi_blk_len, MASS_STORAGE_BULK_EP_MPS);
+
+    /* we read an entire block */
+    if (!(usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size)) {
+        usbd_msc_sector_read((usbd_msc_cfg.scsi_blk_addr / usbd_msc_cfg.scsi_blk_size), usbd_msc_cfg.block_buffer, usbd_msc_cfg.scsi_blk_size);
+    }
+
+    USBD_LOG_DBG("addr:%d\r\n", usbd_msc_cfg.scsi_blk_addr);
+
+    usbd_ep_write(mass_ep_data[MSD_IN_EP_IDX].ep_addr,
+                  &usbd_msc_cfg.block_buffer[usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size], transfer_len, NULL);
+
+    usbd_msc_cfg.scsi_blk_addr += transfer_len;
+    usbd_msc_cfg.scsi_blk_len -= transfer_len;
+    usbd_msc_cfg.csw.DataResidue -= transfer_len;
+
+    if (!usbd_msc_cfg.scsi_blk_len) {
+        usbd_msc_cfg.stage = MSC_BS_DATA_IN_LAST;
+        usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_PASSED;
+    }
+}
+
+/*********************************SCSI CMD*******************************************************************/
+static bool scsi_test_unit_ready(void)
+{
+    if (usbd_msc_cfg.cbw.DataLength != 0U) {
+        if ((usbd_msc_cfg.cbw.Flags & 0x80) != 0U) {
+            USBD_LOG_WRN("Stall IN endpoint\r\n");
+            usbd_ep_set_stall(mass_ep_data[MSD_IN_EP_IDX].ep_addr);
+        } else {
+            USBD_LOG_WRN("Stall OUT endpoint\r\n");
+            usbd_ep_set_stall(mass_ep_data[MSD_OUT_EP_IDX].ep_addr);
+        }
+
+        return false;
+    }
+
+    usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_PASSED;
+    usbd_msc_send_csw();
+    return true;
+}
+
+static bool scsi_request_sense(void)
+{
+    if (!usbd_msc_datain_check()) {
+        return false;
+    }
+
+    scsi_sense_fixed_resp_t sense_rsp = {
+        .response_code = 0x70,
+        .valid = 1
+    };
+
+    sense_rsp.add_sense_len = sizeof(scsi_sense_fixed_resp_t) - 8;
+    sense_rsp.sense_key = 0x00;
+    sense_rsp.add_sense_code = 0x00;
+    sense_rsp.add_sense_qualifier = 0x00;
+
+    /* Win host requests maximum number of bytes but as all we have is 4 bytes we have
+       to tell host back that it is all we have, that's why we correct residue */
+    if (usbd_msc_cfg.csw.DataResidue > sizeof(sense_rsp)) {
+        usbd_msc_cfg.cbw.DataLength = sizeof(sense_rsp);
+        usbd_msc_cfg.csw.DataResidue = sizeof(sense_rsp);
+    }
+
+#if 0
+    request_sense[ 2] = 0x06;           /* UNIT ATTENTION */
+    request_sense[12] = 0x28;           /* Additional Sense Code: Not ready to ready transition */
+    request_sense[13] = 0x00;           /* Additional Sense Code Qualifier */
+#endif
+#if 0
+    request_sense[ 2] = 0x02;           /* NOT READY */
+    request_sense[12] = 0x3A;           /* Additional Sense Code: Medium not present */
+    request_sense[13] = 0x00;           /* Additional Sense Code Qualifier */
+#endif
+#if 0
+    request_sense[ 2] = 0x05;         /* ILLEGAL REQUEST */
+    request_sense[12] = 0x20;         /* Additional Sense Code: Invalid command */
+    request_sense[13] = 0x00;         /* Additional Sense Code Qualifier */
+#endif
+#if 0
+    request_sense[ 2] = 0x00;         /* NO SENSE */
+    request_sense[12] = 0x00;         /* Additional Sense Code: No additional code */
+    request_sense[13] = 0x00;         /* Additional Sense Code Qualifier */
+#endif
+
+    return usbd_msc_send_to_host((uint8_t *)&sense_rsp, sizeof(sense_rsp));
+}
+
+static bool scsi_inquiry_request(void)
+{
+    if (!usbd_msc_datain_check()) {
+        return false;
+    }
+
+    scsi_inquiry_resp_t inquiry_rsp = {
+        .is_removable = 1, /* RMB = 1: Removable Medium */
+        .version = 2,
+        .response_data_format = 2,
+        .additional_length = 31
+    };
+    // vendor_id, product_id, product_rev is space padded string
+    memcpy(inquiry_rsp.vendor_id, "BL702USB", sizeof(inquiry_rsp.vendor_id));
+    memcpy(inquiry_rsp.product_id, "FAT16 RAM DEMO  ", sizeof(inquiry_rsp.product_id));
+    memcpy(inquiry_rsp.product_rev, "1.0 ", sizeof(inquiry_rsp.product_rev));
+
+    /* Win host requests maximum number of bytes but as all we have is 4 bytes we have
+       to tell host back that it is all we have, that's why we correct residue */
+    if (usbd_msc_cfg.csw.DataResidue > sizeof(inquiry_rsp)) {
+        usbd_msc_cfg.cbw.DataLength = sizeof(inquiry_rsp);
+        usbd_msc_cfg.csw.DataResidue = sizeof(inquiry_rsp);
+    }
+
+    return usbd_msc_send_to_host((uint8_t *)&inquiry_rsp, sizeof(inquiry_rsp));
+}
+
+static bool scsi_mode_sense_6(void)
+{
+    if (!usbd_msc_datain_check()) {
+        return false;
+    }
+
+    scsi_mode_sense6_resp_t mode_resp = {
+        .data_len = 3,
+        .medium_type = 0,
+        .write_protected = false,
+        .reserved = 0,
+        .block_descriptor_len = 0 // no block descriptor are included
+    };
+
+    /* Win host requests maximum number of bytes but as all we have is 4 bytes we have
+       to tell host back that it is all we have, that's why we correct residue */
+    if (usbd_msc_cfg.csw.DataResidue > sizeof(mode_resp)) {
+        usbd_msc_cfg.cbw.DataLength = sizeof(mode_resp);
+        usbd_msc_cfg.csw.DataResidue = sizeof(mode_resp);
+    }
+
+    return usbd_msc_send_to_host((uint8_t *)&mode_resp, sizeof(mode_resp));
+}
+
+static bool scsi_start_stop_unit(void)
+{
+    // if (!cbw.CB[3]) {               /* If power condition modifier is 0 */
+    //     USBD_MSC_MediaReady  = cbw.CB[4] & 0x01;   /* Media ready = START bit value */
+    //     usbd_msc_start_stop(USBD_MSC_MediaReady);
+    //     cbw.bStatus = CSW_CMD_PASSED; /* Start Stop Unit -> pass */
+    //     USBD_MSC_SetCSW();
+    //     return;
+    // }
+
+    // cbw.bStatus = CSW_CMD_FAILED;   /* Start Stop Unit -> fail */
+    // usbd_msc_send_csw();
+    usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_PASSED;
+    usbd_msc_send_csw();
+    return true;
+}
+/*
+ *  USB Device MSC SCSI Media Removal Callback
+ *    Parameters:      None
+ *    Return Value:    None
+ */
+
+static bool scsi_media_removal(void)
+{
+    // if (USBD_MSC_CBW.CB[4] & 1) {            /* If prevent */
+    //     USBD_MSC_CSW.bStatus = CSW_CMD_FAILED;    /* Prevent media removal -> fail */
+    // } else {                                 /* If allow */
+    //     USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;    /* Allow media removal -> pass */
+    // }
+
+    // USBD_MSC_SetCSW();
+    usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_PASSED;
+    usbd_msc_send_csw();
+    return true;
+}
+
+static bool scsi_read_format_capacity(void)
+{
+    if (!usbd_msc_datain_check()) {
+        return false;
+    }
+
+    scsi_read_format_capacity_resp_t read_fmt_capa = {
+        .list_length = 8, /* Capacity List Length */
+        .block_num = 0,
+        .descriptor_type = 2, /* Descriptor Code: Formatted Media */
+        .block_size_u16 = 0
+    };
+    /* Block Count */
+    read_fmt_capa.block_num = BSWAP32(usbd_msc_cfg.scsi_blk_nbr);
+    /* Block Length */
+    read_fmt_capa.block_size_u16 = BSWAP16(usbd_msc_cfg.scsi_blk_size);
+
+    /* Win host requests maximum number of bytes but as all we have is 4 bytes we have
+       to tell host back that it is all we have, that's why we correct residue */
+    if (usbd_msc_cfg.csw.DataResidue > sizeof(read_fmt_capa)) {
+        usbd_msc_cfg.cbw.DataLength = sizeof(read_fmt_capa);
+        usbd_msc_cfg.csw.DataResidue = sizeof(read_fmt_capa);
+    }
+
+    return usbd_msc_send_to_host((uint8_t *)&read_fmt_capa, sizeof(read_fmt_capa));
+}
+
+static bool scsi_read_capacity(void)
+{
+    if (!usbd_msc_datain_check()) {
+        return false;
+    }
+
+    scsi_read_capacity10_resp_t read_capa10;
+    /* Last Logical Block */
+    read_capa10.last_lba = BSWAP32((usbd_msc_cfg.scsi_blk_nbr - 1));
+    /* Block Length */
+    read_capa10.block_size = BSWAP32(usbd_msc_cfg.scsi_blk_size);
+
+    /* Win host requests maximum number of bytes but as all we have is 4 bytes we have
+       to tell host back that it is all we have, that's why we correct residue */
+    if (usbd_msc_cfg.csw.DataResidue > sizeof(read_capa10)) {
+        usbd_msc_cfg.cbw.DataLength = sizeof(read_capa10);
+        usbd_msc_cfg.csw.DataResidue = sizeof(read_capa10);
+    }
+
+    return usbd_msc_send_to_host((uint8_t *)&read_capa10, sizeof(read_capa10));
+}
+
+static bool usbd_msc_read_write_process(void)
+{
+    /* Logical Block Address of First Block */
+    uint32_t lba;
+    uint32_t len = 0;
+
+    if (!usbd_msc_cfg.cbw.DataLength) {
+        USBD_LOG_WRN("Zero length in CBW\r\n");
+        //SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
+        usbd_msc_cfg.csw.Status = CSW_STATUS_PHASE_ERROR;
+        usbd_msc_send_csw();
+        return false;
+    }
+
+    lba = GET_BE32(&usbd_msc_cfg.cbw.CB[2]);
+
+    USBD_LOG_DBG("LBA (block) : 0x%x\r\n", lba);
+    usbd_msc_cfg.scsi_blk_addr = lba * usbd_msc_cfg.scsi_blk_size;
+
+    /* Number of Blocks to transfer */
+    switch (usbd_msc_cfg.cbw.CB[0]) {
+        case SCSI_READ10:
+        case SCSI_WRITE10:
+        case SCSI_VERIFY10:
+            len = GET_BE16(&usbd_msc_cfg.cbw.CB[7]);
+            break;
+
+        case SCSI_READ12:
+        case SCSI_WRITE12:
+            len = GET_BE32(&usbd_msc_cfg.cbw.CB[6]);
+            break;
+
+        default:
+            break;
+    }
+
+    USBD_LOG_DBG("len (block) : 0x%x\r\n", len);
+    usbd_msc_cfg.scsi_blk_len = len * usbd_msc_cfg.scsi_blk_size;
+
+    if ((lba + len) > usbd_msc_cfg.scsi_blk_nbr) {
+        USBD_LOG_ERR("LBA out of range\r\n");
+        usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_FAILED;
+        usbd_msc_send_csw();
+        return false;
+    }
+
+    if (usbd_msc_cfg.cbw.DataLength != usbd_msc_cfg.scsi_blk_len) {
+        if ((usbd_msc_cfg.cbw.Flags & 0x80) != 0U) {
+            USBD_LOG_WRN("read write process error\r\n");
+            usbd_ep_set_stall(mass_ep_data[MSD_IN_EP_IDX].ep_addr);
+        } else {
+            USBD_LOG_WRN("read write process error\r\n");
+            usbd_ep_set_stall(mass_ep_data[MSD_OUT_EP_IDX].ep_addr);
+        }
+
+        usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_FAILED;
+        usbd_msc_send_csw();
+        return false;
+    }
+
+    return true;
+}
+
+static bool scsi_mode_sense_10(void)
+{
+    if (!usbd_msc_datain_check()) {
+        return false;
+    }
+
+    scsi_mode_10_resp_t mode10_resp = {
+        .mode_data_length_low = 0x06,
+        .write_protect = 1,
+    };
+
+    /* Win host requests maximum number of bytes but as all we have is 4 bytes we have
+       to tell host back that it is all we have, that's why we correct residue */
+    if (usbd_msc_cfg.csw.DataResidue > sizeof(mode10_resp)) {
+        usbd_msc_cfg.cbw.DataLength = sizeof(mode10_resp);
+        usbd_msc_cfg.csw.DataResidue = sizeof(mode10_resp);
+    }
+
+    return usbd_msc_send_to_host((uint8_t *)&mode10_resp, sizeof(mode10_resp));
+}
+
+static void usbd_msc_cbw_decode(uint8_t *buf, uint16_t size)
+{
+    if (size != sizeof(usbd_msc_cfg.cbw)) {
+        USBD_LOG_ERR("size != sizeof(cbw)");
+        return;
+    }
+
+    memcpy((uint8_t *)&usbd_msc_cfg.cbw, buf, size);
+
+    if (usbd_msc_cfg.cbw.Signature != MSC_CBW_Signature) {
+        USBD_LOG_ERR("CBW Signature Mismatch");
+        return;
+    }
+
+    usbd_msc_cfg.csw.Tag = usbd_msc_cfg.cbw.Tag;
+    usbd_msc_cfg.csw.DataResidue = usbd_msc_cfg.cbw.DataLength;
+
+    if ((usbd_msc_cfg.cbw.CBLength < 1) || (usbd_msc_cfg.cbw.CBLength > 16) || (usbd_msc_cfg.cbw.LUN != 0U)) {
+        USBD_LOG_WRN("cbw.CBLength %d", usbd_msc_cfg.cbw.CBLength);
+        /* Stall data stage */
+        usbd_ep_set_stall(mass_ep_data[MSD_IN_EP_IDX].ep_addr);
+        usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_FAILED;
+        usbd_msc_send_csw();
+    } else {
+        switch (usbd_msc_cfg.cbw.CB[0]) {
+            case SCSI_TEST_UNIT_READY:
+                USBD_LOG_DBG(">> TUR");
+                scsi_test_unit_ready();
+                break;
+
+            case SCSI_REQUEST_SENSE:
+                USBD_LOG_DBG(">> REQ_SENSE");
+                scsi_request_sense();
+                break;
+
+            case SCSI_INQUIRY:
+                USBD_LOG_DBG(">> INQ");
+                scsi_inquiry_request();
+                break;
+
+            case SCSI_START_STOP_UNIT:
+                scsi_start_stop_unit();
+                break;
+
+            case SCSI_MEDIA_REMOVAL:
+                scsi_media_removal();
+                break;
+
+            case SCSI_MODE_SENSE6:
+                USBD_LOG_DBG(">> MODE_SENSE6");
+                scsi_mode_sense_6();
+                break;
+
+            case SCSI_MODE_SENSE10:
+                USBD_LOG_DBG(">> MODE_SENSE10");
+                scsi_mode_sense_10();
+                break;
+
+            case SCSI_READ_FORMAT_CAPACITIES:
+                USBD_LOG_DBG(">> READ_FORMAT_CAPACITY");
+                scsi_read_format_capacity();
+                break;
+
+            case SCSI_READ_CAPACITY:
+                USBD_LOG_DBG(">> READ_CAPACITY");
+                scsi_read_capacity();
+                break;
+
+            case SCSI_READ10:
+            case SCSI_READ12:
+                USBD_LOG_DBG(">> READ");
+
+                if (usbd_msc_read_write_process()) {
+                    if ((usbd_msc_cfg.cbw.Flags & 0x80)) {
+                        usbd_msc_cfg.stage = MSC_BS_DATA_IN;
+                        usbd_msc_memory_read();
+                    } else {
+                        usbd_ep_set_stall(
+                            mass_ep_data[MSD_OUT_EP_IDX].ep_addr);
+                        USBD_LOG_WRN("Stall OUT endpoint");
+                        usbd_msc_cfg.csw.Status = CSW_STATUS_PHASE_ERROR;
+                        usbd_msc_send_csw();
+                    }
+                }
+
+                break;
+
+            case SCSI_WRITE10:
+            case SCSI_WRITE12:
+                USBD_LOG_DBG(">> WRITE");
+
+                if (usbd_msc_read_write_process()) {
+                    if (!(usbd_msc_cfg.cbw.Flags & 0x80)) {
+                        usbd_msc_cfg.stage = MSC_BS_DATA_OUT;
+                    } else {
+                        usbd_ep_set_stall(
+                            mass_ep_data[MSD_IN_EP_IDX].ep_addr);
+                        USBD_LOG_WRN("Stall IN endpoint");
+                        usbd_msc_cfg.csw.Status = CSW_STATUS_PHASE_ERROR;
+                        usbd_msc_send_csw();
+                    }
+                }
+
+                break;
+
+            case SCSI_VERIFY10:
+                USBD_LOG_DBG(">> VERIFY10");
+
+                if (!(usbd_msc_cfg.cbw.CB[1] & 0x02)) {
+                    usbd_msc_cfg.csw.Status = CSW_STATUS_CMD_PASSED;
+                    usbd_msc_send_csw();
+                    break;
+                }
+
+                if (usbd_msc_read_write_process()) {
+                    if (!(usbd_msc_cfg.cbw.Flags & 0x80)) {
+                        usbd_msc_cfg.stage = MSC_BS_DATA_OUT;
+                        memOK = true;
+                    } else {
+                        usbd_ep_set_stall(
+                            mass_ep_data[MSD_IN_EP_IDX].ep_addr);
+                        USBD_LOG_WRN("Stall IN endpoint");
+                        usbd_msc_cfg.csw.Status = CSW_STATUS_PHASE_ERROR;
+                        usbd_msc_send_csw();
+                    }
+                }
+
+                break;
+
+            default:
+                USBD_LOG_WRN(">> default CB[0] %x", usbd_msc_cfg.cbw.CB[0]);
+                /* Stall data stage */
+                usbd_ep_set_stall(mass_ep_data[MSD_IN_EP_IDX].ep_addr);
+                usbd_msc_cfg.stage = MSC_BS_ERROR;
+                break;
+        }
+    }
+}
+
+static void mass_storage_bulk_out(uint8_t ep)
+{
+    uint32_t bytes_read = 0U;
+    uint8_t bo_buf[MASS_STORAGE_BULK_EP_MPS];
+
+    usbd_ep_read(ep, bo_buf, MASS_STORAGE_BULK_EP_MPS,
+                 &bytes_read);
+
+    switch (usbd_msc_cfg.stage) {
+        /*the device has to decode the CBW received*/
+        case MSC_BS_CBW:
+            USBD_LOG_DBG("> BO - MSC_BS_CBW\r\n");
+            usbd_msc_cbw_decode(bo_buf, bytes_read);
+            break;
+
+        /*the device has to receive data from the host*/
+        case MSC_BS_DATA_OUT:
+            switch (usbd_msc_cfg.cbw.CB[0]) {
+                case SCSI_WRITE10:
+                case SCSI_WRITE12:
+                    /* USBD_LOG_DBG("> BO - PROC_CBW WR");*/
+                    usbd_msc_memory_write(bo_buf, bytes_read);
+                    break;
+
+                case SCSI_VERIFY10:
+                    USBD_LOG_DBG("> BO - PROC_CBW VER\r\n");
+                    usbd_msc_memory_verify(bo_buf, bytes_read);
+                    break;
+
+                default:
+                    USBD_LOG_ERR("> BO - PROC_CBW default <>\r\n");
+                    break;
+            }
+
+            break;
+
+        case MSC_BS_CSW:
+            break;
+
+        /*an error has occurred: stall endpoint and send CSW*/
+        default:
+            USBD_LOG_WRN("Stall OUT endpoint, stage: %d\r\n", usbd_msc_cfg.stage);
+            // usbd_ep_set_stall(ep);
+            // usbd_msc_cfg.csw.Status = CSW_STATUS_PHASE_ERROR;
+            // usbd_msc_send_csw();
+            break;
+    }
+
+    /*set ep ack to recv next data*/
+    usbd_ep_read(ep, NULL, 0, NULL);
+}
+
+/**
+ * @brief EP Bulk IN handler, used to send data to the Host
+ *
+ * @param ep        Endpoint address.
+ * @param ep_status Endpoint status code.
+ *
+ * @return  N/A.
+ */
+static void mass_storage_bulk_in(uint8_t ep)
+{
+    USBD_LOG_DBG("I:%d\r\n", usbd_msc_cfg.stage);
+
+    switch (usbd_msc_cfg.stage) {
+        /*the device has to send data to the host*/
+        case MSC_BS_DATA_IN:
+            switch (usbd_msc_cfg.cbw.CB[0]) {
+                case SCSI_READ10:
+                case SCSI_READ12:
+                    /* USBD_LOG_DBG("< BI - PROC_CBW  READ"); */
+                    usbd_msc_memory_read();
+                    break;
+
+                default:
+                    USBD_LOG_ERR("< BI-PROC_CBW default <>\r\n");
+                    break;
+            }
+
+            break;
+
+        /*the device has to send a CSW*/
+        case MSC_BS_DATA_IN_LAST:
+            USBD_LOG_DBG("< BI - MSC_BS_DATA_IN_LAST\r\n");
+            usbd_msc_send_csw();
+            break;
+
+        case MSC_BS_DATA_IN_LAST_STALL:
+            USBD_LOG_WRN("Stall IN endpoint, stage: %d\r\n", usbd_msc_cfg.stage);
+            //usbd_ep_set_stall(mass_ep_data[MSD_IN_EP_IDX].ep_addr);
+            usbd_msc_send_csw();
+            break;
+
+        /*the host has received the CSW -> we wait a CBW*/
+        case MSC_BS_CSW:
+            USBD_LOG_DBG("< BI - MSC_BS_CSW\r\n");
+            usbd_msc_cfg.stage = MSC_BS_CBW;
+            break;
+
+        default:
+            break;
+    }
+}
+
+void msc_storage_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_msc_reset();
+            break;
+
+        default:
+            break;
+    }
+}
+
+static usbd_class_t msc_class;
+
+static usbd_interface_t msc_intf = {
+    .class_handler = msc_storage_class_request_handler,
+    .vendor_handler = NULL,
+    .notify_handler = msc_storage_notify_handler,
+};
+
+void usbd_msc_class_init(uint8_t out_ep, uint8_t in_ep)
+{
+    msc_class.name = "usbd_msc";
+
+    usbd_class_register(&msc_class);
+    usbd_class_add_interface(&msc_class, &msc_intf);
+
+    mass_ep_data[0].ep_addr = out_ep;
+    mass_ep_data[0].ep_cb = mass_storage_bulk_out;
+    mass_ep_data[1].ep_addr = in_ep;
+    mass_ep_data[1].ep_cb = mass_storage_bulk_in;
+
+    usbd_interface_add_endpoint(&msc_intf, &mass_ep_data[0]);
+    usbd_interface_add_endpoint(&msc_intf, &mass_ep_data[1]);
+}
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.h
new file mode 100644
index 0000000000000000000000000000000000000000..f10096313fc846a96256b6daca90d786b093104c
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.h
@@ -0,0 +1,126 @@
+/**
+ * @file
+ * @brief USB Mass Storage Class public header
+ *
+ * Header follows the Mass Storage Class Specification
+ * (Mass_Storage_Specification_Overview_v1.4_2-19-2010.pdf) and
+ * Mass Storage Class Bulk-Only Transport Specification
+ * (usbmassbulk_10.pdf).
+ * Header is limited to Bulk-Only Transfer protocol.
+ */
+
+#ifndef _USBD_MSC_H__
+#define _USBD_MSC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MSC Subclass Codes */
+#define MSC_SUBCLASS_RBC           0x01
+#define MSC_SUBCLASS_SFF8020I_MMC2 0x02
+#define MSC_SUBCLASS_QIC157        0x03
+#define MSC_SUBCLASS_UFI           0x04
+#define MSC_SUBCLASS_SFF8070I      0x05
+#define MSC_SUBCLASS_SCSI          0x06
+
+/* MSC Protocol Codes */
+#define MSC_PROTOCOL_CBI_INT   0x00
+#define MSC_PROTOCOL_CBI_NOINT 0x01
+#define MSC_PROTOCOL_BULK_ONLY 0x50
+
+/* MSC Request Codes */
+#define MSC_REQUEST_RESET       0xFF
+#define MSC_REQUEST_GET_MAX_LUN 0xFE
+
+/** MSC Command Block Wrapper (CBW) Signature */
+#define MSC_CBW_Signature 0x43425355
+/** Bulk-only Command Status Wrapper (CSW) Signature */
+#define MSC_CSW_Signature 0x53425355
+
+/** MSC Command Block Status Values */
+#define CSW_STATUS_CMD_PASSED  0x00
+#define CSW_STATUS_CMD_FAILED  0x01
+#define CSW_STATUS_PHASE_ERROR 0x02
+
+/** MSC Bulk-Only Command Block Wrapper (CBW) */
+struct CBW {
+    uint32_t Signature;
+    uint32_t Tag;
+    uint32_t DataLength;
+    uint8_t Flags;
+    uint8_t LUN;
+    uint8_t CBLength;
+    uint8_t CB[16];
+} __packed;
+
+/** MSC Bulk-Only Command Status Wrapper (CSW) */
+struct CSW {
+    uint32_t Signature;
+    uint32_t Tag;
+    uint32_t DataResidue;
+    uint8_t Status;
+} __packed;
+
+/*Length of template descriptor: 23 bytes*/
+#define MSC_DESCRIPTOR_LEN (9 + 7 + 7)
+// clang-format off
+#define MSC_DESCRIPTOR_INIT(bFirstInterface, out_ep, in_ep,str_idx) \
+    /* Interface */                                                  \
+    0x09,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */         \
+    bFirstInterface,               /* bInterfaceNumber */        \
+    0x00,                          /* bAlternateSetting */       \
+    0x02,                          /* bNumEndpoints */           \
+    USB_DEVICE_CLASS_MASS_STORAGE, /* bInterfaceClass */         \
+    MSC_SUBCLASS_SCSI,             /* bInterfaceSubClass */      \
+    MSC_PROTOCOL_BULK_ONLY,        /* bInterfaceProtocol */      \
+    str_idx, /* iInterface */      /* Endpoint Out */            \
+    0x07,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,  /* bDescriptorType */         \
+    out_ep,                        /* bEndpointAddress */        \
+    0x02,                          /* bmAttributes */            \
+    0x40, 0x00,                    /* wMaxPacketSize */          \
+    0x01, /* bInterval */          /* Endpoint In */             \
+    0x07,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,  /* bDescriptorType */         \
+    in_ep,                         /* bEndpointAddress */        \
+    0x02,                          /* bmAttributes */            \
+    0x40, 0x00,                    /* wMaxPacketSize */          \
+    0x01                           /* bInterval */
+
+#define MSC_HS_DESCRIPTOR_INIT(bFirstInterface, out_ep, in_ep,str_idx) \
+    /* Interface */                                                  \
+    0x09,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */         \
+    bFirstInterface,               /* bInterfaceNumber */        \
+    0x00,                          /* bAlternateSetting */       \
+    0x02,                          /* bNumEndpoints */           \
+    USB_DEVICE_CLASS_MASS_STORAGE, /* bInterfaceClass */         \
+    MSC_SUBCLASS_SCSI,             /* bInterfaceSubClass */      \
+    MSC_PROTOCOL_BULK_ONLY,        /* bInterfaceProtocol */      \
+    str_idx, /* iInterface */      /* Endpoint Out */            \
+    0x07,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,  /* bDescriptorType */         \
+    out_ep,                        /* bEndpointAddress */        \
+    0x02,                          /* bmAttributes */            \
+    0x02, 0x00,                    /* wMaxPacketSize */          \
+    0x01, /* bInterval */          /* Endpoint In */             \
+    0x07,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,  /* bDescriptorType */         \
+    in_ep,                         /* bEndpointAddress */        \
+    0x02,                          /* bmAttributes */            \
+    0x02, 0x00,                    /* wMaxPacketSize */          \
+    0x01                           /* bInterval */
+// clang-format on
+
+void usbd_msc_class_init(uint8_t out_ep, uint8_t in_ep);
+void usbd_msc_get_cap(uint8_t lun, uint32_t *block_num, uint16_t *block_size);
+int usbd_msc_sector_read(uint32_t sector, uint8_t *buffer, uint32_t length);
+int usbd_msc_sector_write(uint32_t sector, uint8_t *buffer, uint32_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_MSC_H_ */
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_scsi.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_scsi.h
new file mode 100644
index 0000000000000000000000000000000000000000..6dc5ffe3c61cdfc4a503ad0ac108edd123deb967
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/msc/usbd_scsi.h
@@ -0,0 +1,302 @@
+/**
+ * @file
+ * @brief USB Mass Storage Class SCSI public header
+ *
+ * Header follows the Mass Storage Class Specification
+ * (Mass_Storage_Specification_Overview_v1.4_2-19-2010.pdf) and
+ * Mass Storage Class Bulk-Only Transport Specification
+ * (usbmassbulk_10.pdf).
+ * Header is limited to Bulk-Only Transfer protocol.
+ */
+
+#ifndef _USBD_SCSI_H_
+#define _USBD_SCSI_H_
+
+/* SCSI Commands */
+#define SCSI_TEST_UNIT_READY            0x00
+#define SCSI_REQUEST_SENSE              0x03
+#define SCSI_FORMAT_UNIT                0x04
+#define SCSI_INQUIRY                    0x12
+#define SCSI_MODE_SELECT6               0x15
+#define SCSI_MODE_SENSE6                0x1A
+#define SCSI_START_STOP_UNIT            0x1B
+#define SCSI_SEND_DIAGNOSTIC            0x1D
+#define SCSI_MEDIA_REMOVAL              0x1E
+#define SCSI_READ_FORMAT_CAPACITIES     0x23
+#define SCSI_READ_CAPACITY              0x25
+#define SCSI_READ10                     0x28
+#define SCSI_WRITE10                    0x2A
+#define SCSI_VERIFY10                   0x2F
+#define SCSI_SYNC_CACHE10               0x35
+#define SCSI_READ12                     0xA8
+#define SCSI_WRITE12                    0xAA
+#define SCSI_MODE_SELECT10              0x55
+#define SCSI_MODE_SENSE10               0x5A
+#define SCSI_ATA_COMMAND_PASS_THROUGH16 0x85
+#define SCSI_READ16                     0x88
+#define SCSI_WRITE16                    0x8A
+#define SCSI_VERIFY16                   0x8F
+#define SCSI_SYNC_CACHE16               0x91
+#define SCSI_SERVICE_ACTION_IN16        0x9E
+#define SCSI_READ_CAPACITY16            0x9E
+#define SCSI_SERVICE_ACTION_OUT16       0x9F
+#define SCSI_ATA_COMMAND_PASS_THROUGH12 0xA1
+#define SCSI_REPORT_ID_INFO             0xA3
+#define SCSI_READ12                     0xA8
+#define SCSI_SERVICE_ACTION_OUT12       0xA9
+#define SCSI_SERVICE_ACTION_IN12        0xAB
+#define SCSI_VERIFY12                   0xAF
+
+/* SCSI Sense Key */
+#define SCSI_SENSE_NONE            0x00
+#define SCSI_SENSE_RECOVERED_ERROR 0x01
+#define SCSI_SENSE_NOT_READY       0x02
+#define SCSI_SENSE_MEDIUM_ERROR    0x03
+#define SCSI_SENSE_HARDWARE_ERROR  0x04
+#define SCSI_SENSE_ILLEGAL_REQUEST 0x05
+#define SCSI_SENSE_UNIT_ATTENTION  0x06
+#define SCSI_SENSE_DATA_PROTECT    0x07
+#define SCSI_SENSE_FIRMWARE_ERROR  0x08
+#define SCSI_SENSE_ABORTED_COMMAND 0x0b
+#define SCSI_SENSE_EQUAL           0x0c
+#define SCSI_SENSE_VOLUME_OVERFLOW 0x0d
+#define SCSI_SENSE_MISCOMPARE      0x0e
+
+//--------------------------------------------------------------------+
+// SCSI Primary Command (SPC-4)
+//--------------------------------------------------------------------+
+
+/// SCSI Test Unit Ready Command
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_TEST_UNIT_READY
+    uint8_t lun;      ///< Logical Unit
+    uint8_t reserved[3];
+    uint8_t control;
+} scsi_test_unit_ready_cmd_t;
+
+/// SCSI Inquiry Command
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_INQUIRY
+    uint8_t reserved1;
+    uint8_t page_code;
+    uint8_t reserved2;
+    uint8_t alloc_length; ///< specifies the maximum number of bytes that USB host has allocated in the Data-In Buffer. An allocation length of zero specifies that no data shall be transferred.
+    uint8_t control;
+} scsi_inquiry_cmd_t, scsi_request_sense_cmd_t;
+
+/// SCSI Inquiry Response Data
+typedef struct __packed {
+    uint8_t peripheral_device_type : 5;
+    uint8_t peripheral_qualifier   : 3;
+
+    uint8_t              : 7;
+    uint8_t is_removable : 1;
+
+    uint8_t version;
+
+    uint8_t response_data_format : 4;
+    uint8_t hierarchical_support : 1;
+    uint8_t normal_aca           : 1;
+    uint8_t                      : 2;
+
+    uint8_t additional_length;
+
+    uint8_t protect                    : 1;
+    uint8_t                            : 2;
+    uint8_t third_party_copy           : 1;
+    uint8_t target_port_group_support  : 2;
+    uint8_t access_control_coordinator : 1;
+    uint8_t scc_support                : 1;
+
+    uint8_t addr16            : 1;
+    uint8_t                   : 3;
+    uint8_t multi_port        : 1;
+    uint8_t                   : 1; // vendor specific
+    uint8_t enclosure_service : 1;
+    uint8_t                   : 1;
+
+    uint8_t         : 1; // vendor specific
+    uint8_t cmd_que : 1;
+    uint8_t         : 2;
+    uint8_t sync    : 1;
+    uint8_t wbus16  : 1;
+    uint8_t         : 2;
+
+    uint8_t vendor_id[8];   ///< 8 bytes of ASCII data identifying the vendor of the product.
+    uint8_t product_id[16]; ///< 16 bytes of ASCII data defined by the vendor.
+    uint8_t product_rev[4]; ///< 4 bytes of ASCII data defined by the vendor.
+} scsi_inquiry_resp_t;
+
+typedef struct __packed {
+    uint8_t response_code : 7; ///< 70h - current errors, Fixed Format 71h - deferred errors, Fixed Format
+    uint8_t valid         : 1;
+
+    uint8_t reserved;
+
+    uint8_t sense_key     : 4;
+    uint8_t               : 1;
+    uint8_t ili           : 1; ///< Incorrect length indicator
+    uint8_t end_of_medium : 1;
+    uint8_t filemark      : 1;
+
+    uint32_t information;
+    uint8_t add_sense_len;
+    uint32_t command_specific_info;
+    uint8_t add_sense_code;
+    uint8_t add_sense_qualifier;
+    uint8_t field_replaceable_unit_code;
+
+    uint8_t sense_key_specific[3]; ///< sense key specific valid bit is bit 7 of key[0], aka MSB in Big Endian layout
+
+} scsi_sense_fixed_resp_t;
+
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_MODE_SENSE_6
+
+    uint8_t                          : 3;
+    uint8_t disable_block_descriptor : 1;
+    uint8_t                          : 4;
+
+    uint8_t page_code    : 6;
+    uint8_t page_control : 2;
+
+    uint8_t subpage_code;
+    uint8_t alloc_length;
+    uint8_t control;
+} scsi_mode_sense6_cmd_t;
+
+// This is only a Mode parameter header(6).
+typedef struct __packed {
+    uint8_t data_len;
+    uint8_t medium_type;
+
+    uint8_t reserved     : 7;
+    bool write_protected : 1;
+
+    uint8_t block_descriptor_len;
+} scsi_mode_sense6_resp_t;
+
+typedef struct
+{
+    uint8_t cmd_code;
+
+    uint8_t reserved1                : 3;
+    uint8_t disable_block_descriptor : 1;
+    uint8_t long_LBA                 : 1;
+    uint8_t reserved2                : 3;
+
+    uint8_t page_code    : 6;
+    uint8_t page_control : 2;
+
+    uint8_t subpage_code;
+
+    uint8_t reserved3;
+    uint8_t reserved4;
+    uint8_t reserved5;
+
+    uint8_t length[2];
+
+    uint8_t control;
+} scsi_mode_sense_10_cmd_t;
+
+typedef struct
+{
+    uint8_t mode_data_length_high;
+    uint8_t mode_data_length_low;
+    uint8_t medium_type;
+
+    uint8_t reserved1     : 4;
+    uint8_t DPO_FUA       : 1; /**< [Disable Page Out] and [Force Unit Access] in the SCSI_READ10 command is valid or not */
+    uint8_t reserved2     : 2;
+    uint8_t write_protect : 1;
+
+    uint8_t long_LBA  : 1;
+    uint8_t reserved3 : 7;
+
+    uint8_t reserved4;
+    uint8_t block_desc_length[2];
+} scsi_mode_10_resp_t;
+
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL
+    uint8_t reserved[3];
+    uint8_t prohibit_removal;
+    uint8_t control;
+} scsi_prevent_allow_medium_removal_t;
+
+typedef struct __packed {
+    uint8_t cmd_code;
+
+    uint8_t immded : 1;
+    uint8_t        : 7;
+
+    uint8_t TU_RESERVED;
+
+    uint8_t power_condition_mod : 4;
+    uint8_t                     : 4;
+
+    uint8_t start           : 1;
+    uint8_t load_eject      : 1;
+    uint8_t no_flush        : 1;
+    uint8_t                 : 1;
+    uint8_t power_condition : 4;
+
+    uint8_t control;
+} scsi_start_stop_unit_cmd_t;
+
+//--------------------------------------------------------------------+
+// SCSI MMC
+//--------------------------------------------------------------------+
+/// SCSI Read Format Capacity: Write Capacity
+typedef struct __packed {
+    uint8_t cmd_code;
+    uint8_t reserved[6];
+    uint16_t alloc_length;
+    uint8_t control;
+} scsi_read_format_capacity_cmd_t;
+
+typedef struct __packed {
+    uint8_t reserved[3];
+    uint8_t list_length; /// must be 8*n, length in bytes of formattable capacity descriptor followed it.
+
+    uint32_t block_num;      /// Number of Logical Blocks
+    uint8_t descriptor_type; // 00: reserved, 01 unformatted media , 10 Formatted media, 11 No media present
+
+    uint8_t reserved2;
+    uint16_t block_size_u16;
+
+} scsi_read_format_capacity_resp_t;
+
+//--------------------------------------------------------------------+
+// SCSI Block Command (SBC-3)
+// NOTE: All data in SCSI command are in Big Endian
+//--------------------------------------------------------------------+
+
+/// SCSI Read Capacity 10 Command: Read Capacity
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_READ_CAPACITY_10
+    uint8_t reserved1;
+    uint32_t lba; ///< The first Logical Block Address (LBA) accessed by this command
+    uint16_t reserved2;
+    uint8_t partial_medium_indicator;
+    uint8_t control;
+} scsi_read_capacity10_cmd_t;
+
+/// SCSI Read Capacity 10 Response Data
+typedef struct
+{
+    uint32_t last_lba;   ///< The last Logical Block Address of the device
+    uint32_t block_size; ///< Block size in bytes
+} scsi_read_capacity10_resp_t;
+
+/// SCSI Read 10 Command
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode
+    uint8_t reserved; // has LUN according to wiki
+    uint32_t lba;     ///< The first Logical Block Address (LBA) accessed by this command
+    uint8_t reserved2;
+    uint16_t block_count; ///< Number of Blocks used by this command
+    uint8_t control;
+} scsi_read10_t, scsi_write10_t, scsi_read_write_10_t;
+
+#endif /* ZEPHYR_INCLUDE_USB_CLASS_USB_CDC_H_ */
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/vendor/usbd_ftdi.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/vendor/usbd_ftdi.c
new file mode 100644
index 0000000000000000000000000000000000000000..d117ebc9e4de13b92aca069232619f143219a2b5
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/vendor/usbd_ftdi.c
@@ -0,0 +1,274 @@
+/**
+ * @file usbd_ftdi.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_ftdi.h"
+
+extern const uint16_t ftdi_eeprom_info[];
+static volatile uint32_t sof_tick = 0;
+
+const char *stop_name[] = { "1", "1.5", "2" };
+const char *parity_name[] = { "N", "O", "E", "M", "S" };
+
+struct usbd_ftdi_line_coding {
+    uint32_t dwDTERate;  /* Data terminal rate in bits per second */
+    uint8_t bCharFormat; /* Number of stop bits */
+    uint8_t bParityType; /* Parity bit type */
+    uint8_t bDataBits;   /* Number of data bits */
+};
+
+struct usbd_ftdi_cfg_priv {
+    struct usbd_ftdi_line_coding line_coding;
+    uint8_t latency_timer1;
+    uint8_t latency_timer2;
+} usbd_ftdi_cfg;
+
+static void usbd_ftdi_init(void)
+{
+    sof_tick = 0;
+    usbd_ftdi_cfg.line_coding.dwDTERate = 1200;
+    usbd_ftdi_cfg.line_coding.bDataBits = 8;
+    usbd_ftdi_cfg.line_coding.bParityType = 0;
+    usbd_ftdi_cfg.line_coding.bCharFormat = 0;
+    usbd_ftdi_cfg.latency_timer1 = 0x10;
+    usbd_ftdi_cfg.latency_timer2 = 0x10;
+    usbd_ftdi_reset();
+}
+
+static void ftdi_set_baudrate(uint32_t itdf_divisor, uint32_t *actual_baudrate)
+{
+#define FTDI_USB_CLK 48000000
+    int baudrate;
+    uint8_t frac[] = { 0, 8, 4, 2, 6, 10, 12, 14 };
+    int divisor = itdf_divisor & 0x3fff;
+    divisor <<= 4;
+    divisor |= frac[(itdf_divisor >> 14) & 0x07];
+
+    if (itdf_divisor == 0x01) {
+        baudrate = 2000000;
+    } else if (itdf_divisor == 0x00) {
+        baudrate = 3000000;
+    } else {
+        baudrate = FTDI_USB_CLK / divisor;
+    }
+
+    if (baudrate > 100000 && baudrate < 12000) {
+        *actual_baudrate = (baudrate - 100000) * 100000;
+    } else {
+        *actual_baudrate = baudrate;
+    }
+}
+static int ftdi_vendor_request_handler(struct usb_setup_packet *pSetup, uint8_t **data, uint32_t *len)
+{
+    switch (pSetup->bRequest) {
+        case SIO_READ_EEPROM_REQUEST:
+            *data = (uint8_t *)&ftdi_eeprom_info[pSetup->wIndexL];
+            *len = 2;
+            break;
+
+        case SIO_RESET_REQUEST:
+            usbd_ftdi_init();
+            break;
+
+        case SIO_SET_MODEM_CTRL_REQUEST:
+            if (pSetup->wValue == SIO_SET_DTR_HIGH) {
+                USBD_LOG_DBG("DTR 1\r\n");
+                usbd_ftdi_set_dtr(true);
+            } else if (pSetup->wValue == SIO_SET_DTR_LOW) {
+                USBD_LOG_DBG("DTR 0\r\n");
+                usbd_ftdi_set_dtr(false);
+            } else if (pSetup->wValue == SIO_SET_RTS_HIGH) {
+                USBD_LOG_DBG("RTS 1\r\n");
+                usbd_ftdi_set_rts(true);
+            } else if (pSetup->wValue == SIO_SET_RTS_LOW) {
+                USBD_LOG_DBG("RTS 0\r\n");
+                usbd_ftdi_set_rts(false);
+            }
+
+            break;
+
+        case SIO_SET_FLOW_CTRL_REQUEST:
+
+            break;
+
+        case SIO_SET_BAUDRATE_REQUEST: //wValue,2个字节波特率
+        {
+            uint8_t baudrate_high = (pSetup->wIndex >> 8);
+
+            ftdi_set_baudrate(pSetup->wValue | (baudrate_high << 16), &usbd_ftdi_cfg.line_coding.dwDTERate);
+            if (usbd_ftdi_cfg.line_coding.dwDTERate != 1200) {
+                USBD_LOG_DBG("CDC Baudrate:%d\r\n", usbd_ftdi_cfg.line_coding.dwDTERate);
+                usbd_ftdi_set_line_coding(usbd_ftdi_cfg.line_coding.dwDTERate, usbd_ftdi_cfg.line_coding.bDataBits, usbd_ftdi_cfg.line_coding.bParityType, usbd_ftdi_cfg.line_coding.bCharFormat);
+            }
+            break;
+        }
+
+        case SIO_SET_DATA_REQUEST:
+
+            /**
+             * D0-D7 databits  BITS_7=7, BITS_8=8
+             * D8-D10 parity  NONE=0, ODD=1, EVEN=2, MARK=3, SPACE=4
+             * D11-D12      STOP_BIT_1=0, STOP_BIT_15=1, STOP_BIT_2=2
+             * D14          BREAK_OFF=0, BREAK_ON=1
+             **/
+            USBD_LOG_DBG(" CDC DATA REQUEST < %d %s %s>\r\n", (uint8_t)pSetup->wValue, parity_name[(uint8_t)(pSetup->wValue >> 8)], stop_name[(uint8_t)(pSetup->wValue >> 11)]);
+            usbd_ftdi_cfg.line_coding.bDataBits = (uint8_t)pSetup->wValue;
+            usbd_ftdi_cfg.line_coding.bParityType = (uint8_t)(pSetup->wValue >> 8);
+            usbd_ftdi_cfg.line_coding.bCharFormat = (uint8_t)(pSetup->wValue >> 11);
+
+            break;
+
+        case SIO_POLL_MODEM_STATUS_REQUEST:
+            /*     Poll modem status information
+
+                This function allows the retrieve the two status bytes of the device.
+                The device sends these bytes also as a header for each read access
+                where they are discarded by ftdi_read_data(). The chip generates
+                the two stripped status bytes in the absence of data every 40 ms.
+
+                Layout of the first byte:
+                - B0..B3 - must be 0
+                - B4       Clear to send (CTS)
+                            0 = inactive
+                            1 = active
+                - B5       Data set ready (DTS)
+                            0 = inactive
+                            1 = active
+                - B6       Ring indicator (RI)
+                            0 = inactive
+                            1 = active
+                - B7       Receive line signal detect (RLSD)
+                            0 = inactive
+                            1 = active
+
+                Layout of the second byte:
+                - B0       Data ready (DR)
+                - B1       Overrun error (OE)
+                - B2       Parity error (PE)
+                - B3       Framing error (FE)
+                - B4       Break interrupt (BI)
+                - B5       Transmitter holding register (THRE)
+                - B6       Transmitter empty (TEMT)
+                - B7       Error in RCVR FIFO */
+            *data = (uint8_t *)&ftdi_eeprom_info[2];
+            *len = 2;
+            break;
+
+        case SIO_SET_EVENT_CHAR_REQUEST:
+
+            break;
+
+        case SIO_SET_ERROR_CHAR_REQUEST:
+
+            break;
+
+        case SIO_SET_LATENCY_TIMER_REQUEST:
+            if (pSetup->wIndexL == 1) {
+                usbd_ftdi_cfg.latency_timer1 = pSetup->wValueL;
+            } else {
+                usbd_ftdi_cfg.latency_timer2 = pSetup->wValueL;
+            }
+
+            break;
+
+        case SIO_GET_LATENCY_TIMER_REQUEST:
+            if (pSetup->wIndexL == 1) {
+                *data = &usbd_ftdi_cfg.latency_timer1;
+            } else {
+                *data = &usbd_ftdi_cfg.latency_timer2;
+            }
+
+            *len = 1;
+            //USBD_LOG("get latency:%d,len:%d\r\n",Latency_Timer1,*len);
+            break;
+
+        case SIO_SET_BITMODE_REQUEST:
+
+            break;
+
+        default:
+            USBD_LOG_DBG("CDC ACM request 0x%x, value 0x%x\r\n",
+                         pSetup->bRequest, pSetup->wValue);
+            return -1;
+    }
+
+    return 0;
+}
+static void ftdi_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_ftdi_init();
+            break;
+
+        case USB_EVENT_SOF:
+            sof_tick++;
+            USBD_LOG_DBG("tick: %d\r\n", sof_tick);
+            break;
+
+        default:
+            break;
+    }
+}
+
+__weak void usbd_ftdi_reset(void)
+{
+}
+__weak void usbd_ftdi_set_line_coding(uint32_t baudrate, uint8_t databits, uint8_t parity, uint8_t stopbits)
+{
+}
+__weak void usbd_ftdi_set_dtr(bool dtr)
+{
+}
+__weak void usbd_ftdi_set_rts(bool rts)
+{
+}
+uint32_t usbd_ftdi_get_sof_tick(void)
+{
+    return sof_tick;
+}
+
+uint32_t usbd_ftdi_get_latency_timer1(void)
+{
+    return usbd_ftdi_cfg.latency_timer1;
+}
+
+uint32_t usbd_ftdi_get_latency_timer2(void)
+{
+    return usbd_ftdi_cfg.latency_timer2;
+}
+
+void usbd_ftdi_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = NULL;
+    intf->custom_handler = NULL;
+    intf->vendor_handler = ftdi_vendor_request_handler;
+    intf->notify_handler = ftdi_notify_handler;
+    usbd_class_add_interface(class, intf);
+}
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/vendor/usbd_ftdi.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/vendor/usbd_ftdi.h
new file mode 100644
index 0000000000000000000000000000000000000000..45657cb05dd0310a7c22502f353d139e2ac1658b
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/vendor/usbd_ftdi.h
@@ -0,0 +1,66 @@
+/**
+ * @file usbd_ftdi.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _USBD_FTDI_H
+#define _USBD_FTDI_H
+
+/* Requests */
+#define SIO_RESET_REQUEST             0x00 /* Reset the port */
+#define SIO_SET_MODEM_CTRL_REQUEST    0x01 /* Set the modem control register */
+#define SIO_SET_FLOW_CTRL_REQUEST     0x02 /* Set flow control register */
+#define SIO_SET_BAUDRATE_REQUEST      0x03 /* Set baud rate */
+#define SIO_SET_DATA_REQUEST          0x04 /* Set the data characteristics of the port */
+#define SIO_POLL_MODEM_STATUS_REQUEST 0x05
+#define SIO_SET_EVENT_CHAR_REQUEST    0x06
+#define SIO_SET_ERROR_CHAR_REQUEST    0x07
+#define SIO_SET_LATENCY_TIMER_REQUEST 0x09
+#define SIO_GET_LATENCY_TIMER_REQUEST 0x0A
+#define SIO_SET_BITMODE_REQUEST       0x0B
+#define SIO_READ_PINS_REQUEST         0x0C
+#define SIO_READ_EEPROM_REQUEST       0x90
+#define SIO_WRITE_EEPROM_REQUEST      0x91
+#define SIO_ERASE_EEPROM_REQUEST      0x92
+
+#define SIO_DISABLE_FLOW_CTRL 0x0
+#define SIO_RTS_CTS_HS        (0x1 << 8)
+#define SIO_DTR_DSR_HS        (0x2 << 8)
+#define SIO_XON_XOFF_HS       (0x4 << 8)
+
+#define SIO_SET_DTR_MASK 0x1
+#define SIO_SET_DTR_HIGH (1 | (SIO_SET_DTR_MASK << 8))
+#define SIO_SET_DTR_LOW  (0 | (SIO_SET_DTR_MASK << 8))
+#define SIO_SET_RTS_MASK 0x2
+#define SIO_SET_RTS_HIGH (2 | (SIO_SET_RTS_MASK << 8))
+#define SIO_SET_RTS_LOW  (0 | (SIO_SET_RTS_MASK << 8))
+
+#define SIO_RTS_CTS_HS (0x1 << 8)
+
+void usbd_ftdi_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+
+void usbd_ftdi_reset(void);
+void usbd_ftdi_set_line_coding(uint32_t baudrate, uint8_t databits, uint8_t parity, uint8_t stopbits);
+void usbd_ftdi_set_dtr(bool dtr);
+void usbd_ftdi_set_rts(bool rts);
+uint32_t usbd_ftdi_get_sof_tick(void);
+uint32_t usbd_ftdi_get_latency_timer1(void);
+uint32_t usbd_ftdi_get_latency_timer2(void);
+#endif /* USB_FTDI_H_ */
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.c
new file mode 100644
index 0000000000000000000000000000000000000000..732d220d018288f0075de2969263a0a23f4c450c
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.c
@@ -0,0 +1,134 @@
+/**
+ * @file usbd_video.c
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_video.h"
+
+extern struct video_probe_and_commit_controls probe;
+extern struct video_probe_and_commit_controls commit;
+
+int video_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("Class request:"
+                 "bRequest 0x%02x, bmRequestType 0x%02x len %d",
+                 setup->bRequest, setup->bmRequestType, *len);
+
+    switch (setup->bRequest) {
+        case VIDEO_REQUEST_SET_CUR:
+            if (setup->wValue == 256) {
+                memcpy((uint8_t *)&probe, *data, setup->wLength);
+            } else if (setup->wValue == 512) {
+                memcpy((uint8_t *)&commit, *data, setup->wLength);
+            }
+
+            break;
+
+        case VIDEO_REQUEST_GET_CUR:
+            if (setup->wValue == 256) {
+                *data = (uint8_t *)&probe;
+            } else if (setup->wValue == 512) {
+                *data = (uint8_t *)&commit;
+            }
+
+            break;
+
+        case VIDEO_REQUEST_GET_MIN:
+            if (setup->wValue == 256) {
+                *data = (uint8_t *)&probe;
+            } else if (setup->wValue == 512) {
+                *data = (uint8_t *)&commit;
+            }
+
+            break;
+
+        case VIDEO_REQUEST_GET_MAX:
+            if (setup->wValue == 256) {
+                *data = (uint8_t *)&probe;
+            } else if (setup->wValue == 512) {
+                *data = (uint8_t *)&commit;
+            }
+
+            break;
+
+        case VIDEO_REQUEST_GET_RES:
+
+            break;
+
+        case VIDEO_REQUEST_GET_LEN:
+
+            break;
+
+        case VIDEO_REQUEST_GET_INFO:
+
+            break;
+
+        case VIDEO_REQUEST_GET_DEF:
+            if (setup->wLength == 256) {
+                *data = (uint8_t *)&probe;
+            } else if (setup->wLength == 512) {
+                *data = (uint8_t *)&commit;
+            }
+
+            break;
+
+        default:
+            USBD_LOG_ERR("Unhandled request 0x%02x", setup->bRequest);
+            break;
+    }
+
+    return 0;
+}
+
+void video_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+
+            break;
+
+        case USB_EVENT_SOF:
+            usbd_video_sof_callback();
+            break;
+
+        case USB_EVENT_SET_INTERFACE:
+            usbd_video_set_interface_callback(((uint8_t *)arg)[3]);
+            break;
+
+        default:
+            break;
+    }
+}
+
+void usbd_video_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = video_class_request_handler;
+    intf->custom_handler = NULL;
+    intf->vendor_handler = NULL;
+    intf->notify_handler = video_notify_handler;
+    usbd_class_add_interface(class, intf);
+}
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.h
new file mode 100644
index 0000000000000000000000000000000000000000..09c452f5f79434a4de3df4903b1d029e4be15a80
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.h
@@ -0,0 +1,821 @@
+/**
+ * @file
+ * @brief USB Video Device Class public header
+ *
+ * Header follows below documentation:
+ * - USB Device Class Definition for Video Devices UVC 1.5 Class specification.pdf
+ */
+
+#ifndef _USBD_VIDEO_H_
+#define _USBD_VIDEO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_DEVICE_VIDEO_CLASS_VERSION_1_5 0
+
+/*! @brief Video device subclass code */
+#define VIDEO_SC_UNDEFINED                  0x00U
+#define VIDEO_SC_VIDEOCONTROL               0x01U
+#define VIDEO_SC_VIDEOSTREAMING             0x02U
+#define VIDEO_SC_VIDEO_INTERFACE_COLLECTION 0x03U
+
+/*! @brief Video device protocol code */
+#define VIDEO_PC_PROTOCOL_UNDEFINED 0x00U
+#define VIDEO_PC_PROTOCOL_15        0x01U
+
+/*! @brief Video device class-specific descriptor type */
+#define VIDEO_CS_UNDEFINED_DESCRIPTOR_TYPE     0x20U
+#define VIDEO_CS_DEVICE_DESCRIPTOR_TYPE        0x21U
+#define VIDEO_CS_CONFIGURATION_DESCRIPTOR_TYPE 0x22U
+#define VIDEO_CS_STRING_DESCRIPTOR_TYPE        0x23U
+#define VIDEO_CS_INTERFACE_DESCRIPTOR_TYPE     0x24U
+#define VIDEO_CS_ENDPOINT_DESCRIPTOR_TYPE      0x25U
+
+/*! @brief Video device class-specific VC interface descriptor subtype */
+#define VIDEO_VC_DESCRIPTOR_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U
+#define VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE               0x01U
+#define VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE       0x02U
+#define VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE      0x03U
+#define VIDEO_VC_SELECTOR_UNIT_DESCRIPTOR_SUBTYPE        0x04U
+#define VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE      0x05U
+#define VIDEO_VC_EXTENSION_UNIT_DESCRIPTOR_SUBTYPE       0x06U
+#define VIDEO_VC_ENCODING_UNIT_DESCRIPTOR_SUBTYPE        0x07U
+
+/*! @brief Video device class-specific VS interface descriptor subtype */
+#define VIDEO_VS_UNDEFINED_DESCRIPTOR_SUBTYPE             0x00U
+#define VIDEO_VS_INPUT_HEADER_DESCRIPTOR_SUBTYPE          0x01U
+#define VIDEO_VS_OUTPUT_HEADER_DESCRIPTOR_SUBTYPE         0x02U
+#define VIDEO_VS_STILL_IMAGE_FRAME_DESCRIPTOR_SUBTYPE     0x03U
+#define VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_SUBTYPE   0x04U
+#define VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_SUBTYPE    0x05U
+#define VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_SUBTYPE          0x06U
+#define VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE           0x07U
+#define VIDEO_VS_FORMAT_MPEG2TS_DESCRIPTOR_SUBTYPE        0x0AU
+#define VIDEO_VS_FORMAT_DV_DESCRIPTOR_SUBTYPE             0x0CU
+#define VIDEO_VS_COLORFORMAT_DESCRIPTOR_SUBTYPE           0x0DU
+#define VIDEO_VS_FORMAT_FRAME_BASED_DESCRIPTOR_SUBTYPE    0x10U
+#define VIDEO_VS_FRAME_FRAME_BASED_DESCRIPTOR_SUBTYPE     0x11U
+#define VIDEO_VS_FORMAT_STREAM_BASED_DESCRIPTOR_SUBTYPE   0x12U
+#define VIDEO_VS_FORMAT_H264_DESCRIPTOR_SUBTYPE           0x13U
+#define VIDEO_VS_FRAME_H264_DESCRIPTOR_SUBTYPE            0x14U
+#define VIDEO_VS_FORMAT_H264_SIMULCAST_DESCRIPTOR_SUBTYPE 0x15U
+#define VIDEO_VS_FORMAT_VP8_DESCRIPTOR_SUBTYPE            0x16U
+#define VIDEO_VS_FRAME_VP8_DESCRIPTOR_SUBTYPE             0x17U
+#define VIDEO_VS_FORMAT_VP8_SIMULCAST_DESCRIPTOR_SUBTYPE  0x18U
+
+/*! @brief Video device class-specific VC endpoint descriptor subtype */
+#define VIDEO_EP_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U
+#define VIDEO_EP_GENERAL_DESCRIPTOR_SUBTYPE   0x01U
+#define VIDEO_EP_ENDPOINT_DESCRIPTOR_SUBTYPE  0x02U
+#define VIDEO_EP_INTERRUPT_DESCRIPTOR_SUBTYPE 0x03U
+
+/*! @brief Video device class-specific request code */
+#define VIDEO_REQUEST_UNDEFINED   0x00U
+#define VIDEO_REQUEST_SET_CUR     0x01U
+#define VIDEO_REQUEST_SET_CUR_ALL 0x11U
+#define VIDEO_REQUEST_GET_CUR     0x81U
+#define VIDEO_REQUEST_GET_MIN     0x82U
+#define VIDEO_REQUEST_GET_MAX     0x83U
+#define VIDEO_REQUEST_GET_RES     0x84U
+#define VIDEO_REQUEST_GET_LEN     0x85U
+#define VIDEO_REQUEST_GET_INFO    0x86U
+#define VIDEO_REQUEST_GET_DEF     0x87U
+#define VIDEO_REQUEST_GET_CUR_ALL 0x91U
+#define VIDEO_REQUEST_GET_MIN_ALL 0x92U
+#define VIDEO_REQUEST_GET_MAX_ALL 0x93U
+#define VIDEO_REQUEST_GET_RES_ALL 0x94U
+#define VIDEO_REQUEST_GET_DEF_ALL 0x97U
+
+/*! @brief Video device class-specific VideoControl interface control selector */
+#define VIDEO_VC_CONTROL_UNDEFINED          0x00U
+#define VIDEO_VC_VIDEO_POWER_MODE_CONTROL   0x01U
+#define VIDEO_VC_REQUEST_ERROR_CODE_CONTROL 0x02U
+
+/*! @brief Video device class-specific Terminal control selector */
+#define VIDEO_TE_CONTROL_UNDEFINED 0x00U
+
+/*! @brief Video device class-specific Selector Unit control selector */
+#define VIDEO_SU_CONTROL_UNDEFINED    0x00U
+#define VIDEO_SU_INPUT_SELECT_CONTROL 0x01U
+
+/*! @brief Video device class-specific Camera Terminal control selector */
+#define VIDEO_CT_CONTROL_UNDEFINED              0x00U
+#define VIDEO_CT_SCANNING_MODE_CONTROL          0x01U
+#define VIDEO_CT_AE_MODE_CONTROL                0x02U
+#define VIDEO_CT_AE_PRIORITY_CONTROL            0x03U
+#define VIDEO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04U
+#define VIDEO_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05U
+#define VIDEO_CT_FOCUS_ABSOLUTE_CONTROL         0x06U
+#define VIDEO_CT_FOCUS_RELATIVE_CONTROL         0x07U
+#define VIDEO_CT_FOCUS_AUTO_CONTROL             0x08U
+#define VIDEO_CT_IRIS_ABSOLUTE_CONTROL          0x09U
+#define VIDEO_CT_IRIS_RELATIVE_CONTROL          0x0AU
+#define VIDEO_CT_ZOOM_ABSOLUTE_CONTROL          0x0BU
+#define VIDEO_CT_ZOOM_RELATIVE_CONTROL          0x0CU
+#define VIDEO_CT_PANTILT_ABSOLUTE_CONTROL       0x0DU
+#define VIDEO_CT_PANTILT_RELATIVE_CONTROL       0x0EU
+#define VIDEO_CT_ROLL_ABSOLUTE_CONTROL          0x0FU
+#define VIDEO_CT_ROLL_RELATIVE_CONTROL          0x10U
+#define VIDEO_CT_PRIVACY_CONTROL                0x11U
+#define VIDEO_CT_FOCUS_SIMPLE_CONTROL           0x12U
+#define VIDEO_CT_WINDOW_CONTROL                 0x13U
+#define VIDEO_CT_REGION_OF_INTEREST_CONTROL     0x14U
+
+/*! @brief Video device class-specific Processing Unit control selector */
+#define VIDEO_PU_CONTROL_UNDEFINED                      0x00U
+#define VIDEO_PU_BACKLIGHT_COMPENSATION_CONTROL         0x01U
+#define VIDEO_PU_BRIGHTNESS_CONTROL                     0x02U
+#define VIDEO_PU_CONTRAST_CONTROL                       0x03U
+#define VIDEO_PU_GAIN_CONTROL                           0x04U
+#define VIDEO_PU_POWER_LINE_FREQUENCY_CONTROL           0x05U
+#define VIDEO_PU_HUE_CONTROL                            0x06U
+#define VIDEO_PU_SATURATION_CONTROL                     0x07U
+#define VIDEO_PU_SHARPNESS_CONTROL                      0x08U
+#define VIDEO_PU_GAMMA_CONTROL                          0x09U
+#define VIDEO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x0AU
+#define VIDEO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0BU
+#define VIDEO_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x0CU
+#define VIDEO_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x0DU
+#define VIDEO_PU_DIGITAL_MULTIPLIER_CONTROL             0x0EU
+#define VIDEO_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x0FU
+#define VIDEO_PU_HUE_AUTO_CONTROL                       0x10U
+#define VIDEO_PU_ANALOG_VIDEO_STANDARD_CONTROL          0x11U
+#define VIDEO_PU_ANALOG_LOCK_STATUS_CONTROL             0x12U
+#define VIDEO_PU_CONTRAST_AUTO_CONTROL                  0x13U
+
+/*! @brief Video device class-specific Encoding Unit control selector */
+#define VIDEO_EU_CONTROL_UNDEFINED           0x00U
+#define VIDEO_EU_SELECT_LAYER_CONTROL        0x01U
+#define VIDEO_EU_PROFILE_TOOLSET_CONTROL     0x02U
+#define VIDEO_EU_VIDEO_RESOLUTION_CONTROL    0x03U
+#define VIDEO_EU_MIN_FRAME_INTERVAL_CONTROL  0x04U
+#define VIDEO_EU_SLICE_MODE_CONTROL          0x05U
+#define VIDEO_EU_RATE_CONTROL_MODE_CONTROL   0x06U
+#define VIDEO_EU_AVERAGE_BITRATE_CONTROL     0x07U
+#define VIDEO_EU_CPB_SIZE_CONTROL            0x08U
+#define VIDEO_EU_PEAK_BIT_RATE_CONTROL       0x09U
+#define VIDEO_EU_QUANTIZATION_PARAMS_CONTROL 0x0AU
+#define VIDEO_EU_SYNC_REF_FRAME_CONTROL      0x0BU
+#define VIDEO_EU_LTR_BUFFER_                 CONTROL0x0CU
+#define VIDEO_EU_LTR_PICTURE_CONTROL         0x0DU
+#define VIDEO_EU_LTR_VALIDATION_CONTROL      0x0EU
+#define VIDEO_EU_LEVEL_IDC_LIMIT_CONTROL     0x0FU
+#define VIDEO_EU_SEI_PAYLOADTYPE_CONTROL     0x10U
+#define VIDEO_EU_QP_RANGE_CONTROL            0x11U
+#define VIDEO_EU_PRIORITY_CONTROL            0x12U
+#define VIDEO_EU_START_OR_STOP_LAYER_CONTROL 0x13U
+#define VIDEO_EU_ERROR_RESILIENCY_CONTROL    0x14U
+
+/*! @brief Video device class-specific Extension Unit control selector */
+#define VIDEO_XU_CONTROL_UNDEFINED 0x00U
+
+/*! @brief Video device class-specific VideoStreaming Interface control selector */
+#define VIDEO_VS_CONTROL_UNDEFINED            0x00U
+#define VIDEO_VS_PROBE_CONTROL                0x01U
+#define VIDEO_VS_COMMIT_CONTROL               0x02U
+#define VIDEO_VS_STILL_PROBE_CONTROL          0x03U
+#define VIDEO_VS_STILL_COMMIT_CONTROL         0x04U
+#define VIDEO_VS_STILL_IMAGE_TRIGGER_CONTROL  0x05U
+#define VIDEO_VS_STREAM_ERROR_CODE_CONTROL    0x06U
+#define VIDEO_VS_GENERATE_KEY_FRAME_CONTROL   0x07U
+#define VIDEO_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08U
+#define VIDEO_VS_SYNCH_DELAY_CONTROL          0x09U
+
+/*! @}*/
+
+/*!
+ * @name USB Video class terminal types
+ * @{
+ */
+
+/*! @brief Video device USB terminal type */
+#define VIDEO_TT_VENDOR_SPECIFIC 0x0100U
+#define VIDEO_TT_STREAMING       0x0101U
+
+/*! @brief Video device input terminal type */
+#define VIDEO_ITT_VENDOR_SPECIFIC       0x0200U
+#define VIDEO_ITT_CAMERA                0x0201U
+#define VIDEO_ITT_MEDIA_TRANSPORT_INPUT 0x0202U
+
+/*! @brief Video device output terminal type */
+#define VIDEO_OTT_VENDOR_SPECIFIC        0x0300U
+#define VIDEO_OTT_DISPLAY                0x0301U
+#define VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT 0x0302U
+
+/*! @brief Video device external terminal type */
+#define VIDEO_ET_VENDOR_SPECIFIC     0x0400U
+#define VIDEO_ET_COMPOSITE_CONNECTOR 0x0401U
+#define VIDEO_ET_SVIDEO_CONNECTOR    0x0402U
+#define VIDEO_ET_COMPONENT_CONNECTOR 0x0403U
+
+/*! @}*/
+
+/*!
+ * @name USB Video class setup request types
+ * @{
+ */
+
+/*! @brief Video device class setup request set type */
+#define VIDEO_SET_REQUEST_INTERFACE 0x21U
+#define VIDEO_SET_REQUEST_ENDPOINT  0x22U
+
+/*! @brief Video device class setup request get type */
+#define VIDEO_GET_REQUEST_INTERFACE 0xA1U
+#define VIDEO_GET_REQUEST_ENDPOINT  0xA2U
+
+/*! @}*/
+
+/*! @brief Video device still image trigger control */
+#define VIDEO_STILL_IMAGE_TRIGGER_NORMAL_OPERATION                            0x00U
+#define VIDEO_STILL_IMAGE_TRIGGER_TRANSMIT_STILL_IMAGE                        0x01U
+#define VIDEO_STILL_IMAGE_TRIGGER_TRANSMIT_STILL_IMAGE_VS_DEDICATED_BULK_PIPE 0x02U
+#define VIDEO_STILL_IMAGE_TRIGGER_ABORT_STILL_IMAGE_TRANSMISSION              0x03U
+
+/*!
+ * @name USB Video device class-specific request commands
+ * @{
+ */
+
+/*! @brief Video device class-specific request GET CUR COMMAND */
+#define VIDEO_GET_CUR_VC_POWER_MODE_CONTROL 0x8101U
+#define VIDEO_GET_CUR_VC_ERROR_CODE_CONTROL 0x8102U
+
+#define VIDEO_GET_CUR_PU_BACKLIGHT_COMPENSATION_CONTROL         0x8121U
+#define VIDEO_GET_CUR_PU_BRIGHTNESS_CONTROL                     0x8122U
+#define VIDEO_GET_CUR_PU_CONTRACT_CONTROL                       0x8123U
+#define VIDEO_GET_CUR_PU_GAIN_CONTROL                           0x8124U
+#define VIDEO_GET_CUR_PU_POWER_LINE_FREQUENCY_CONTROL           0x8125U
+#define VIDEO_GET_CUR_PU_HUE_CONTROL                            0x8126U
+#define VIDEO_GET_CUR_PU_SATURATION_CONTROL                     0x8127U
+#define VIDEO_GET_CUR_PU_SHARRNESS_CONTROL                      0x8128U
+#define VIDEO_GET_CUR_PU_GAMMA_CONTROL                          0x8129U
+#define VIDEO_GET_CUR_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x812AU
+#define VIDEO_GET_CUR_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x812BU
+#define VIDEO_GET_CUR_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x812CU
+#define VIDEO_GET_CUR_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x812DU
+#define VIDEO_GET_CUR_PU_DIGITAL_MULTIPLIER_CONTROL             0x812EU
+#define VIDEO_GET_CUR_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x812FU
+#define VIDEO_GET_CUR_PU_HUE_AUTO_CONTROL                       0x8130U
+#define VIDEO_GET_CUR_PU_ANALOG_VIDEO_STANDARD_CONTROL          0x8131U
+#define VIDEO_GET_CUR_PU_ANALOG_LOCK_STATUS_CONTROL             0x8132U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_CUR_PU_CONTRAST_AUTO_CONTROL 0x8133U
+#endif
+
+#define VIDEO_GET_CUR_CT_SCANNING_MODE_CONTROL          0x8141U
+#define VIDEO_GET_CUR_CT_AE_MODE_CONTROL                0x8142U
+#define VIDEO_GET_CUR_CT_AE_PRIORITY_CONTROL            0x8143U
+#define VIDEO_GET_CUR_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8144U
+#define VIDEO_GET_CUR_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x8145U
+#define VIDEO_GET_CUR_CT_FOCUS_ABSOLUTE_CONTROL         0x8146U
+#define VIDEO_GET_CUR_CT_FOCUS_RELATIVE_CONTROL         0x8147U
+#define VIDEO_GET_CUR_CT_FOCUS_AUTO_CONTROL             0x8148U
+#define VIDEO_GET_CUR_CT_IRIS_ABSOLUTE_CONTROL          0x8149U
+#define VIDEO_GET_CUR_CT_IRIS_RELATIVE_CONTROL          0x814AU
+#define VIDEO_GET_CUR_CT_ZOOM_ABSOLUTE_CONTROL          0x814BU
+#define VIDEO_GET_CUR_CT_ZOOM_RELATIVE_CONTROL          0x814CU
+#define VIDEO_GET_CUR_CT_PANTILT_ABSOLUTE_CONTROL       0x814DU
+#define VIDEO_GET_CUR_CT_PANTILT_RELATIVE_CONTROL       0x814EU
+#define VIDEO_GET_CUR_CT_ROLL_ABSOLUTE_CONTROL          0x814FU
+#define VIDEO_GET_CUR_CT_ROLL_RELATIVE_CONTROL          0x8150U
+#define VIDEO_GET_CUR_CT_PRIVACY_CONTROL                0x8151U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_CUR_CT_FOCUS_SIMPLE_CONTROL       0x8152U
+#define VIDEO_GET_CUR_CT_DIGITAL_WINDOW_CONTROL     0x8153U
+#define VIDEO_GET_CUR_CT_REGION_OF_INTEREST_CONTROL 0x8154U
+#endif
+
+#define VIDEO_GET_CUR_VS_PROBE_CONTROL                0x8161U
+#define VIDEO_GET_CUR_VS_COMMIT_CONTROL               0x8162U
+#define VIDEO_GET_CUR_VS_STILL_PROBE_CONTROL          0x8163U
+#define VIDEO_GET_CUR_VS_STILL_COMMIT_CONTROL         0x8164U
+#define VIDEO_GET_CUR_VS_STILL_IMAGE_TRIGGER_CONTROL  0x8165U
+#define VIDEO_GET_CUR_VS_STREAM_ERROR_CODE_CONTROL    0x8166U
+#define VIDEO_GET_CUR_VS_GENERATE_KEY_FRAME_CONTROL   0x8167U
+#define VIDEO_GET_CUR_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8168U
+#define VIDEO_GET_CUR_VS_SYNCH_DELAY_CONTROL          0x8169U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_CUR_EU_SELECT_LAYER_CONTROL        0x8181U
+#define VIDEO_GET_CUR_EU_PROFILE_TOOLSET_CONTROL     0x8182U
+#define VIDEO_GET_CUR_EU_VIDEO_RESOLUTION_CONTROL    0x8183U
+#define VIDEO_GET_CUR_EU_MIN_FRAME_INTERVAL_CONTROL  0x8184U
+#define VIDEO_GET_CUR_EU_SLICE_MODE_CONTROL          0x8185U
+#define VIDEO_GET_CUR_EU_RATE_CONTROL_MODE_CONTROL   0x8186U
+#define VIDEO_GET_CUR_EU_AVERAGE_BITRATE_CONTROL     0x8187U
+#define VIDEO_GET_CUR_EU_CPB_SIZE_CONTROL            0x8188U
+#define VIDEO_GET_CUR_EU_PEAK_BIT_RATE_CONTROL       0x8189U
+#define VIDEO_GET_CUR_EU_QUANTIZATION_PARAMS_CONTROL 0x818AU
+#define VIDEO_GET_CUR_EU_SYNC_REF_FRAME_CONTROL      0x818BU
+#define VIDEO_GET_CUR_EU_LTR_BUFFER_CONTROL          0x818CU
+#define VIDEO_GET_CUR_EU_LTR_PICTURE_CONTROL         0x818DU
+#define VIDEO_GET_CUR_EU_LTR_VALIDATION_CONTROL      0x818EU
+#define VIDEO_GET_CUR_EU_LEVEL_IDC_LIMIT_CONTROL     0x818FU
+#define VIDEO_GET_CUR_EU_SEI_PAYLOADTYPE_CONTROL     0x8190U
+#define VIDEO_GET_CUR_EU_QP_RANGE_CONTROL            0x8191U
+#define VIDEO_GET_CUR_EU_PRIORITY_CONTROL            0x8192U
+#define VIDEO_GET_CUR_EU_START_OR_STOP_LAYER_CONTROL 0x8193U
+#define VIDEO_GET_CUR_EU_ERROR_RESILIENCY_CONTROL    0x8194U
+#endif
+
+/*! @brief Video device class-specific request GET MIN COMMAND */
+#define VIDEO_GET_MIN_PU_BACKLIGHT_COMPENSATION_CONTROL    0x8221U
+#define VIDEO_GET_MIN_PU_BRIGHTNESS_CONTROL                0x8222U
+#define VIDEO_GET_MIN_PU_CONTRACT_CONTROL                  0x8223U
+#define VIDEO_GET_MIN_PU_GAIN_CONTROL                      0x8224U
+#define VIDEO_GET_MIN_PU_HUE_CONTROL                       0x8226U
+#define VIDEO_GET_MIN_PU_SATURATION_CONTROL                0x8227U
+#define VIDEO_GET_MIN_PU_SHARRNESS_CONTROL                 0x8228U
+#define VIDEO_GET_MIN_PU_GAMMA_CONTROL                     0x8229U
+#define VIDEO_GET_MIN_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x822AU
+#define VIDEO_GET_MIN_PU_WHITE_BALANCE_COMPONENT_CONTROL   0x822CU
+#define VIDEO_GET_MIN_PU_DIGITAL_MULTIPLIER_CONTROL        0x822EU
+#define VIDEO_GET_MIN_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL  0x822FU
+
+#define VIDEO_GET_MIN_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8244U
+#define VIDEO_GET_MIN_CT_FOCUS_ABSOLUTE_CONTROL         0x8246U
+#define VIDEO_GET_MIN_CT_FOCUS_RELATIVE_CONTROL         0x8247U
+#define VIDEO_GET_MIN_CT_IRIS_ABSOLUTE_CONTROL          0x8249U
+#define VIDEO_GET_MIN_CT_ZOOM_ABSOLUTE_CONTROL          0x824BU
+#define VIDEO_GET_MIN_CT_ZOOM_RELATIVE_CONTROL          0x824CU
+#define VIDEO_GET_MIN_CT_PANTILT_ABSOLUTE_CONTROL       0x824DU
+#define VIDEO_GET_MIN_CT_PANTILT_RELATIVE_CONTROL       0x824EU
+#define VIDEO_GET_MIN_CT_ROLL_ABSOLUTE_CONTROL          0x824FU
+#define VIDEO_GET_MIN_CT_ROLL_RELATIVE_CONTROL          0x8250U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_MIN_CT_DIGITAL_WINDOW_CONTROL     0x8251U
+#define VIDEO_GET_MIN_CT_REGION_OF_INTEREST_CONTROL 0x8252U
+#endif
+
+#define VIDEO_GET_MIN_VS_PROBE_CONTROL                0x8261U
+#define VIDEO_GET_MIN_VS_STILL_PROBE_CONTROL          0x8263U
+#define VIDEO_GET_MIN_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8268U
+#define VIDEO_GET_MIN_VS_SYNCH_DELAY_CONTROL          0x8269U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_MIN_EU_VIDEO_RESOLUTION_CONTROL    0x8283U
+#define VIDEO_GET_MIN_EU_MIN_FRAME_INTERVAL_CONTROL  0x8284U
+#define VIDEO_GET_MIN_EU_SLICE_MODE_CONTROL          0x8285U
+#define VIDEO_GET_MIN_EU_AVERAGE_BITRATE_CONTROL     0x8287U
+#define VIDEO_GET_MIN_EU_CPB_SIZE_CONTROL            0x8288U
+#define VIDEO_GET_MIN_EU_PEAK_BIT_RATE_CONTROL       0x8289U
+#define VIDEO_GET_MIN_EU_QUANTIZATION_PARAMS_CONTROL 0x828AU
+#define VIDEO_GET_MIN_EU_SYNC_REF_FRAME_CONTROL      0x828BU
+#define VIDEO_GET_MIN_EU_LEVEL_IDC_LIMIT_CONTROL     0x828FU
+#define VIDEO_GET_MIN_EU_SEI_PAYLOADTYPE_CONTROL     0x8290U
+#define VIDEO_GET_MIN_EU_QP_RANGE_CONTROL            0x8291U
+#endif
+
+/*! @brief Video device class-specific request GET MAX COMMAND */
+#define VIDEO_GET_MAX_PU_BACKLIGHT_COMPENSATION_CONTROL    0x8321U
+#define VIDEO_GET_MAX_PU_BRIGHTNESS_CONTROL                0x8322U
+#define VIDEO_GET_MAX_PU_CONTRACT_CONTROL                  0x8323U
+#define VIDEO_GET_MAX_PU_GAIN_CONTROL                      0x8324U
+#define VIDEO_GET_MAX_PU_HUE_CONTROL                       0x8326U
+#define VIDEO_GET_MAX_PU_SATURATION_CONTROL                0x8327U
+#define VIDEO_GET_MAX_PU_SHARRNESS_CONTROL                 0x8328U
+#define VIDEO_GET_MAX_PU_GAMMA_CONTROL                     0x8329U
+#define VIDEO_GET_MAX_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x832AU
+#define VIDEO_GET_MAX_PU_WHITE_BALANCE_COMPONENT_CONTROL   0x832CU
+#define VIDEO_GET_MAX_PU_DIGITAL_MULTIPLIER_CONTROL        0x832EU
+#define VIDEO_GET_MAX_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL  0x832FU
+
+#define VIDEO_GET_MAX_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8344U
+#define VIDEO_GET_MAX_CT_FOCUS_ABSOLUTE_CONTROL         0x8346U
+#define VIDEO_GET_MAX_CT_FOCUS_RELATIVE_CONTROL         0x8347U
+#define VIDEO_GET_MAX_CT_IRIS_ABSOLUTE_CONTROL          0x8349U
+#define VIDEO_GET_MAX_CT_ZOOM_ABSOLUTE_CONTROL          0x834BU
+#define VIDEO_GET_MAX_CT_ZOOM_RELATIVE_CONTROL          0x834CU
+#define VIDEO_GET_MAX_CT_PANTILT_ABSOLUTE_CONTROL       0x834DU
+#define VIDEO_GET_MAX_CT_PANTILT_RELATIVE_CONTROL       0x834EU
+#define VIDEO_GET_MAX_CT_ROLL_ABSOLUTE_CONTROL          0x834FU
+#define VIDEO_GET_MAX_CT_ROLL_RELATIVE_CONTROL          0x8350U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_MAX_CT_DIGITAL_WINDOW_CONTROL     0x8351U
+#define VIDEO_GET_MAX_CT_REGION_OF_INTEREST_CONTROL 0x8352U
+#endif
+
+#define VIDEO_GET_MAX_VS_PROBE_CONTROL                0x8361U
+#define VIDEO_GET_MAX_VS_STILL_PROBE_CONTROL          0x8363U
+#define VIDEO_GET_MAX_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8368U
+#define VIDEO_GET_MAX_VS_SYNCH_DELAY_CONTROL          0x8369U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_MAX_EU_VIDEO_RESOLUTION_CONTROL    0x8383U
+#define VIDEO_GET_MAX_EU_MIN_FRAME_INTERVAL_CONTROL  0x8384U
+#define VIDEO_GET_MAX_EU_SLICE_MODE_CONTROL          0x8385U
+#define VIDEO_GET_MAX_EU_AVERAGE_BITRATE_CONTROL     0x8387U
+#define VIDEO_GET_MAX_EU_CPB_SIZE_CONTROL            0x8388U
+#define VIDEO_GET_MAX_EU_PEAK_BIT_RATE_CONTROL       0x8389U
+#define VIDEO_GET_MAX_EU_QUANTIZATION_PARAMS_CONTROL 0x838AU
+#define VIDEO_GET_MAX_EU_SYNC_REF_FRAME_CONTROL      0x838BU
+#define VIDEO_GET_MAX_EU_LTR_BUFFER_CONTROL          0x838CU
+#define VIDEO_GET_MAX_EU_LEVEL_IDC_LIMIT_CONTROL     0x838FU
+#define VIDEO_GET_MAX_EU_SEI_PAYLOADTYPE_CONTROL     0x8390U
+#define VIDEO_GET_MAX_EU_QP_RANGE_CONTROL            0x8391U
+#endif
+
+/*! @brief Video device class-specific request GET RES COMMAND */
+#define VIDEO_GET_RES_PU_BACKLIGHT_COMPENSATION_CONTROL    0x8421U
+#define VIDEO_GET_RES_PU_BRIGHTNESS_CONTROL                0x8422U
+#define VIDEO_GET_RES_PU_CONTRACT_CONTROL                  0x8423U
+#define VIDEO_GET_RES_PU_GAIN_CONTROL                      0x8424U
+#define VIDEO_GET_RES_PU_HUE_CONTROL                       0x8426U
+#define VIDEO_GET_RES_PU_SATURATION_CONTROL                0x8427U
+#define VIDEO_GET_RES_PU_SHARRNESS_CONTROL                 0x8428U
+#define VIDEO_GET_RES_PU_GAMMA_CONTROL                     0x8429U
+#define VIDEO_GET_RES_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x842AU
+#define VIDEO_GET_RES_PU_WHITE_BALANCE_COMPONENT_CONTROL   0x842CU
+#define VIDEO_GET_RES_PU_DIGITAL_MULTIPLIER_CONTROL        0x842EU
+#define VIDEO_GET_RES_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL  0x842FU
+
+#define VIDEO_GET_RES_CT_AE_MODE_CONTROL                0x8442U
+#define VIDEO_GET_RES_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8444U
+#define VIDEO_GET_RES_CT_FOCUS_ABSOLUTE_CONTROL         0x8446U
+#define VIDEO_GET_RES_CT_FOCUS_RELATIVE_CONTROL         0x8447U
+#define VIDEO_GET_RES_CT_IRIS_ABSOLUTE_CONTROL          0x8449U
+#define VIDEO_GET_RES_CT_ZOOM_ABSOLUTE_CONTROL          0x844BU
+#define VIDEO_GET_RES_CT_ZOOM_RELATIVE_CONTROL          0x844CU
+#define VIDEO_GET_RES_CT_PANTILT_ABSOLUTE_CONTROL       0x844DU
+#define VIDEO_GET_RES_CT_PANTILT_RELATIVE_CONTROL       0x844EU
+#define VIDEO_GET_RES_CT_ROLL_ABSOLUTE_CONTROL          0x844FU
+#define VIDEO_GET_RES_CT_ROLL_RELATIVE_CONTROL          0x8450U
+
+#define VIDEO_GET_RES_VS_PROBE_CONTROL                0x8461U
+#define VIDEO_GET_RES_VS_STILL_PROBE_CONTROL          0x8463U
+#define VIDEO_GET_RES_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8468U
+#define VIDEO_GET_RES_VS_SYNCH_DELAY_CONTROL          0x8469U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_RES_EU_AVERAGE_BITRATE_CONTROL     0x8487U
+#define VIDEO_GET_RES_EU_CPB_SIZE_CONTROL            0x8488U
+#define VIDEO_GET_RES_EU_PEAK_BIT_RATE_CONTROL       0x8489U
+#define VIDEO_GET_RES_EU_QUANTIZATION_PARAMS_CONTROL 0x848AU
+#define VIDEO_GET_RES_EU_ERROR_RESILIENCY_CONTROL    0x8494U
+#endif
+
+/*! @brief Video device class-specific request GET LEN COMMAND */
+
+#define VIDEO_GET_LEN_VS_PROBE_CONTROL        0x8561U
+#define VIDEO_GET_LEN_VS_COMMIT_CONTROL       0x8562U
+#define VIDEO_GET_LEN_VS_STILL_PROBE_CONTROL  0x8563U
+#define VIDEO_GET_LEN_VS_STILL_COMMIT_CONTROL 0x8564U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_LEN_EU_SELECT_LAYER_CONTROL        0x8581U
+#define VIDEO_GET_LEN_EU_PROFILE_TOOLSET_CONTROL     0x8582U
+#define VIDEO_GET_LEN_EU_VIDEO_RESOLUTION_CONTROL    0x8583U
+#define VIDEO_GET_LEN_EU_MIN_FRAME_INTERVAL_CONTROL  0x8584U
+#define VIDEO_GET_LEN_EU_SLICE_MODE_CONTROL          0x8585U
+#define VIDEO_GET_LEN_EU_RATE_CONTROL_MODE_CONTROL   0x8586U
+#define VIDEO_GET_LEN_EU_AVERAGE_BITRATE_CONTROL     0x8587U
+#define VIDEO_GET_LEN_EU_CPB_SIZE_CONTROL            0x8588U
+#define VIDEO_GET_LEN_EU_PEAK_BIT_RATE_CONTROL       0x8589U
+#define VIDEO_GET_LEN_EU_QUANTIZATION_PARAMS_CONTROL 0x858AU
+#define VIDEO_GET_LEN_EU_SYNC_REF_FRAME_CONTROL      0x858BU
+#define VIDEO_GET_LEN_EU_LTR_BUFFER_CONTROL          0x858CU
+#define VIDEO_GET_LEN_EU_LTR_PICTURE_CONTROL         0x858DU
+#define VIDEO_GET_LEN_EU_LTR_VALIDATION_CONTROL      0x858EU
+#define VIDEO_GET_LEN_EU_QP_RANGE_CONTROL            0x8591U
+#define VIDEO_GET_LEN_EU_PRIORITY_CONTROL            0x8592U
+#define VIDEO_GET_LEN_EU_START_OR_STOP_LAYER_CONTROL 0x8593U
+#endif
+
+/*! @brief Video device class-specific request GET INFO COMMAND */
+#define VIDEO_GET_INFO_VC_POWER_MODE_CONTROL 0x8601U
+#define VIDEO_GET_INFO_VC_ERROR_CODE_CONTROL 0x8602U
+
+#define VIDEO_GET_INFO_PU_BACKLIGHT_COMPENSATION_CONTROL         0x8621U
+#define VIDEO_GET_INFO_PU_BRIGHTNESS_CONTROL                     0x8622U
+#define VIDEO_GET_INFO_PU_CONTRACT_CONTROL                       0x8623U
+#define VIDEO_GET_INFO_PU_GAIN_CONTROL                           0x8624U
+#define VIDEO_GET_INFO_PU_POWER_LINE_FREQUENCY_CONTROL           0x8625U
+#define VIDEO_GET_INFO_PU_HUE_CONTROL                            0x8626U
+#define VIDEO_GET_INFO_PU_SATURATION_CONTROL                     0x8627U
+#define VIDEO_GET_INFO_PU_SHARRNESS_CONTROL                      0x8628U
+#define VIDEO_GET_INFO_PU_GAMMA_CONTROL                          0x8629U
+#define VIDEO_GET_INFO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x862AU
+#define VIDEO_GET_INFO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x862BU
+#define VIDEO_GET_INFO_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x862CU
+#define VIDEO_GET_INFO_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x862DU
+#define VIDEO_GET_INFO_PU_DIGITAL_MULTIPLIER_CONTROL             0x862EU
+#define VIDEO_GET_INFO_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x862FU
+#define VIDEO_GET_INFO_PU_HUE_AUTO_CONTROL                       0x8630U
+#define VIDEO_GET_INFO_PU_ANALOG_VIDEO_STANDARD_CONTROL          0x8631U
+#define VIDEO_GET_INFO_PU_ANALOG_LOCK_STATUS_CONTROL             0x8632U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_INFO_PU_CONTRAST_AUTO_CONTROL 0x8633U
+#endif
+
+#define VIDEO_GET_INFO_CT_SCANNING_MODE_CONTROL          0x8641U
+#define VIDEO_GET_INFO_CT_AE_MODE_CONTROL                0x8642U
+#define VIDEO_GET_INFO_CT_AE_PRIORITY_CONTROL            0x8643U
+#define VIDEO_GET_INFO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8644U
+#define VIDEO_GET_INFO_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x8645U
+#define VIDEO_GET_INFO_CT_FOCUS_ABSOLUTE_CONTROL         0x8646U
+#define VIDEO_GET_INFO_CT_FOCUS_RELATIVE_CONTROL         0x8647U
+#define VIDEO_GET_INFO_CT_FOCUS_AUTO_CONTROL             0x8648U
+#define VIDEO_GET_INFO_CT_IRIS_ABSOLUTE_CONTROL          0x8649U
+#define VIDEO_GET_INFO_CT_IRIS_RELATIVE_CONTROL          0x864AU
+#define VIDEO_GET_INFO_CT_ZOOM_ABSOLUTE_CONTROL          0x864BU
+#define VIDEO_GET_INFO_CT_ZOOM_RELATIVE_CONTROL          0x864CU
+#define VIDEO_GET_INFO_CT_PANTILT_ABSOLUTE_CONTROL       0x864DU
+#define VIDEO_GET_INFO_CT_PANTILT_RELATIVE_CONTROL       0x864EU
+#define VIDEO_GET_INFO_CT_ROLL_ABSOLUTE_CONTROL          0x864FU
+#define VIDEO_GET_INFO_CT_ROLL_RELATIVE_CONTROL          0x8650U
+#define VIDEO_GET_INFO_CT_PRIVACY_CONTROL                0x8651U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_INFO_CT_FOCUS_SIMPLE_CONTROL 0x8652U
+#endif
+
+#define VIDEO_GET_INFO_VS_PROBE_CONTROL                0x8661U
+#define VIDEO_GET_INFO_VS_COMMIT_CONTROL               0x8662U
+#define VIDEO_GET_INFO_VS_STILL_PROBE_CONTROL          0x8663U
+#define VIDEO_GET_INFO_VS_STILL_COMMIT_CONTROL         0x8664U
+#define VIDEO_GET_INFO_VS_STILL_IMAGE_TRIGGER_CONTROL  0x8665U
+#define VIDEO_GET_INFO_VS_STREAM_ERROR_CODE_CONTROL    0x8666U
+#define VIDEO_GET_INFO_VS_GENERATE_KEY_FRAME_CONTROL   0x8667U
+#define VIDEO_GET_INFO_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8668U
+#define VIDEO_GET_INFO_VS_SYNCH_DELAY_CONTROL          0x8669U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_INFO_EU_SELECT_LAYER_CONTROL        0x8681U
+#define VIDEO_GET_INFO_EU_PROFILE_TOOLSET_CONTROL     0x8682U
+#define VIDEO_GET_INFO_EU_VIDEO_RESOLUTION_CONTROL    0x8683U
+#define VIDEO_GET_INFO_EU_MIN_FRAME_INTERVAL_CONTROL  0x8684U
+#define VIDEO_GET_INFO_EU_SLICE_MODE_CONTROL          0x8685U
+#define VIDEO_GET_INFO_EU_RATE_CONTROL_MODE_CONTROL   0x8686U
+#define VIDEO_GET_INFO_EU_AVERAGE_BITRATE_CONTROL     0x8687U
+#define VIDEO_GET_INFO_EU_CPB_SIZE_CONTROL            0x8688U
+#define VIDEO_GET_INFO_EU_PEAK_BIT_RATE_CONTROL       0x8689U
+#define VIDEO_GET_INFO_EU_QUANTIZATION_PARAMS_CONTROL 0x868AU
+#define VIDEO_GET_INFO_EU_SYNC_REF_FRAME_CONTROL      0x868BU
+#define VIDEO_GET_INFO_EU_LTR_BUFFER_CONTROL          0x868CU
+#define VIDEO_GET_INFO_EU_LTR_PICTURE_CONTROL         0x868DU
+#define VIDEO_GET_INFO_EU_LTR_VALIDATION_CONTROL      0x868EU
+#define VIDEO_GET_INFO_EU_SEI_PAYLOADTYPE_CONTROL     0x8690U
+#define VIDEO_GET_INFO_EU_QP_RANGE_CONTROL            0x8691U
+#define VIDEO_GET_INFO_EU_PRIORITY_CONTROL            0x8692U
+#define VIDEO_GET_INFO_EU_START_OR_STOP_LAYER_CONTROL 0x8693U
+#endif
+
+/*! @brief Video device class-specific request GET DEF COMMAND */
+#define VIDEO_GET_DEF_PU_BACKLIGHT_COMPENSATION_CONTROL         0x8721U
+#define VIDEO_GET_DEF_PU_BRIGHTNESS_CONTROL                     0x8722U
+#define VIDEO_GET_DEF_PU_CONTRACT_CONTROL                       0x8723U
+#define VIDEO_GET_DEF_PU_GAIN_CONTROL                           0x8724U
+#define VIDEO_GET_DEF_PU_POWER_LINE_FREQUENCY_CONTROL           0x8725U
+#define VIDEO_GET_DEF_PU_HUE_CONTROL                            0x8726U
+#define VIDEO_GET_DEF_PU_SATURATION_CONTROL                     0x8727U
+#define VIDEO_GET_DEF_PU_SHARRNESS_CONTROL                      0x8728U
+#define VIDEO_GET_DEF_PU_GAMMA_CONTROL                          0x8729U
+#define VIDEO_GET_DEF_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x872AU
+#define VIDEO_GET_DEF_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x872BU
+#define VIDEO_GET_DEF_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x872CU
+#define VIDEO_GET_DEF_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x872DU
+#define VIDEO_GET_DEF_PU_DIGITAL_MULTIPLIER_CONTROL             0x872EU
+#define VIDEO_GET_DEF_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x872FU
+#define VIDEO_GET_DEF_PU_HUE_AUTO_CONTROL                       0x8730U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_DEF_PU_CONTRAST_AUTO_CONTROL 0x8731U
+#endif
+
+#define VIDEO_GET_DEF_CT_AE_MODE_CONTROL                0x8742U
+#define VIDEO_GET_DEF_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8744U
+#define VIDEO_GET_DEF_CT_FOCUS_ABSOLUTE_CONTROL         0x8746U
+#define VIDEO_GET_DEF_CT_FOCUS_RELATIVE_CONTROL         0x8747U
+#define VIDEO_GET_DEF_CT_FOCUS_AUTO_CONTROL             0x8748U
+#define VIDEO_GET_DEF_CT_IRIS_ABSOLUTE_CONTROL          0x8749U
+#define VIDEO_GET_DEF_CT_ZOOM_ABSOLUTE_CONTROL          0x874BU
+#define VIDEO_GET_DEF_CT_ZOOM_RELATIVE_CONTROL          0x874CU
+#define VIDEO_GET_DEF_CT_PANTILT_ABSOLUTE_CONTROL       0x874DU
+#define VIDEO_GET_DEF_CT_PANTILT_RELATIVE_CONTROL       0x874EU
+#define VIDEO_GET_DEF_CT_ROLL_ABSOLUTE_CONTROL          0x874FU
+#define VIDEO_GET_DEF_CT_ROLL_RELATIVE_CONTROL          0x8750U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_DEF_CT_FOCUS_SIMPLE_CONTROL       0x8751U
+#define VIDEO_GET_DEF_CT_DIGITAL_WINDOW_CONTROL     0x8752U
+#define VIDEO_GET_DEF_CT_REGION_OF_INTEREST_CONTROL 0x8753U
+#endif
+
+#define VIDEO_GET_DEF_VS_PROBE_CONTROL                0x8761U
+#define VIDEO_GET_DEF_VS_STILL_PROBE_CONTROL          0x8763U
+#define VIDEO_GET_DEF_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8768U
+#define VIDEO_GET_DEF_VS_SYNCH_DELAY_CONTROL          0x8769U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_DEF_EU_PROFILE_TOOLSET_CONTROL     0x8782U
+#define VIDEO_GET_DEF_EU_VIDEO_RESOLUTION_CONTROL    0x8783U
+#define VIDEO_GET_DEF_EU_MIN_FRAME_INTERVAL_CONTROL  0x8784U
+#define VIDEO_GET_DEF_EU_SLICE_MODE_CONTROL          0x8785U
+#define VIDEO_GET_DEF_EU_RATE_CONTROL_MODE_CONTROL   0x8786U
+#define VIDEO_GET_DEF_EU_AVERAGE_BITRATE_CONTROL     0x8787U
+#define VIDEO_GET_DEF_EU_CPB_SIZE_CONTROL            0x8788U
+#define VIDEO_GET_DEF_EU_PEAK_BIT_RATE_CONTROL       0x8789U
+#define VIDEO_GET_DEF_EU_QUANTIZATION_PARAMS_CONTROL 0x878AU
+#define VIDEO_GET_DEF_EU_LTR_BUFFER_CONTROL          0x878CU
+#define VIDEO_GET_DEF_EU_LTR_PICTURE_CONTROL         0x878DU
+#define VIDEO_GET_DEF_EU_LTR_VALIDATION_CONTROL      0x878EU
+#define VIDEO_GET_DEF_EU_LEVEL_IDC_LIMIT_CONTROL     0x878FU
+#define VIDEO_GET_DEF_EU_SEI_PAYLOADTYPE_CONTROL     0x8790U
+#define VIDEO_GET_DEF_EU_QP_RANGE_CONTROL            0x8791U
+#define VIDEO_GET_DEF_EU_ERROR_RESILIENCY_CONTROL    0x8794U
+#endif
+
+/*! @brief Video device class-specific request SET CUR COMMAND */
+#define VIDEO_SET_CUR_VC_POWER_MODE_CONTROL 0x0101U
+
+#define VIDEO_SET_CUR_PU_BACKLIGHT_COMPENSATION_CONTROL         0x0121U
+#define VIDEO_SET_CUR_PU_BRIGHTNESS_CONTROL                     0x0122U
+#define VIDEO_SET_CUR_PU_CONTRACT_CONTROL                       0x0123U
+#define VIDEO_SET_CUR_PU_GAIN_CONTROL                           0x0124U
+#define VIDEO_SET_CUR_PU_POWER_LINE_FREQUENCY_CONTROL           0x0125U
+#define VIDEO_SET_CUR_PU_HUE_CONTROL                            0x0126U
+#define VIDEO_SET_CUR_PU_SATURATION_CONTROL                     0x0127U
+#define VIDEO_SET_CUR_PU_SHARRNESS_CONTROL                      0x0128U
+#define VIDEO_SET_CUR_PU_GAMMA_CONTROL                          0x0129U
+#define VIDEO_SET_CUR_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x012AU
+#define VIDEO_SET_CUR_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x012BU
+#define VIDEO_SET_CUR_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x012CU
+#define VIDEO_SET_CUR_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x012DU
+#define VIDEO_SET_CUR_PU_DIGITAL_MULTIPLIER_CONTROL             0x012EU
+#define VIDEO_SET_CUR_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x012FU
+#define VIDEO_SET_CUR_PU_HUE_AUTO_CONTROL                       0x0130U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_SET_CUR_PU_CONTRAST_AUTO_CONTROL 0x0131U
+#endif
+
+#define VIDEO_SET_CUR_CT_SCANNING_MODE_CONTROL          0x0141U
+#define VIDEO_SET_CUR_CT_AE_MODE_CONTROL                0x0142U
+#define VIDEO_SET_CUR_CT_AE_PRIORITY_CONTROL            0x0143U
+#define VIDEO_SET_CUR_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x0144U
+#define VIDEO_SET_CUR_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x0145U
+#define VIDEO_SET_CUR_CT_FOCUS_ABSOLUTE_CONTROL         0x0146U
+#define VIDEO_SET_CUR_CT_FOCUS_RELATIVE_CONTROL         0x0147U
+#define VIDEO_SET_CUR_CT_FOCUS_AUTO_CONTROL             0x0148U
+#define VIDEO_SET_CUR_CT_IRIS_ABSOLUTE_CONTROL          0x0149U
+#define VIDEO_SET_CUR_CT_IRIS_RELATIVE_CONTROL          0x014AU
+#define VIDEO_SET_CUR_CT_ZOOM_ABSOLUTE_CONTROL          0x014BU
+#define VIDEO_SET_CUR_CT_ZOOM_RELATIVE_CONTROL          0x014CU
+#define VIDEO_SET_CUR_CT_PANTILT_ABSOLUTE_CONTROL       0x014DU
+#define VIDEO_SET_CUR_CT_PANTILT_RELATIVE_CONTROL       0x014EU
+#define VIDEO_SET_CUR_CT_ROLL_ABSOLUTE_CONTROL          0x014FU
+#define VIDEO_SET_CUR_CT_ROLL_RELATIVE_CONTROL          0x0150U
+#define VIDEO_SET_CUR_CT_PRIVACY_CONTROL                0x0151U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_SET_CUR_CT_FOCUS_SIMPLE_CONTROL       0x0152U
+#define VIDEO_SET_CUR_CT_DIGITAL_WINDOW_CONTROL     0x0153U
+#define VIDEO_SET_CUR_CT_REGION_OF_INTEREST_CONTROL 0x0154U
+#endif
+
+#define VIDEO_SET_CUR_VS_PROBE_CONTROL                0x0161U
+#define VIDEO_SET_CUR_VS_COMMIT_CONTROL               0x0162U
+#define VIDEO_SET_CUR_VS_STILL_PROBE_CONTROL          0x0163U
+#define VIDEO_SET_CUR_VS_STILL_COMMIT_CONTROL         0x0164U
+#define VIDEO_SET_CUR_VS_STILL_IMAGE_TRIGGER_CONTROL  0x0165U
+#define VIDEO_SET_CUR_VS_STREAM_ERROR_CODE_CONTROL    0x0166U
+#define VIDEO_SET_CUR_VS_GENERATE_KEY_FRAME_CONTROL   0x0167U
+#define VIDEO_SET_CUR_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x0168U
+#define VIDEO_SET_CUR_VS_SYNCH_DELAY_CONTROL          0x0169U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_SET_CUR_EU_SELECT_LAYER_CONTROL        0x0181U
+#define VIDEO_SET_CUR_EU_PROFILE_TOOLSET_CONTROL     0x0182U
+#define VIDEO_SET_CUR_EU_VIDEO_RESOLUTION_CONTROL    0x0183U
+#define VIDEO_SET_CUR_EU_MIN_FRAME_INTERVAL_CONTROL  0x0184U
+#define VIDEO_SET_CUR_EU_SLICE_MODE_CONTROL          0x0185U
+#define VIDEO_SET_CUR_EU_RATE_CONTROL_MODE_CONTROL   0x0186U
+#define VIDEO_SET_CUR_EU_AVERAGE_BITRATE_CONTROL     0x0187U
+#define VIDEO_SET_CUR_EU_CPB_SIZE_CONTROL            0x0188U
+#define VIDEO_SET_CUR_EU_PEAK_BIT_RATE_CONTROL       0x0189U
+#define VIDEO_SET_CUR_EU_QUANTIZATION_PARAMS_CONTROL 0x018AU
+#define VIDEO_SET_CUR_EU_SYNC_REF_FRAME_CONTROL      0x018BU
+#define VIDEO_SET_CUR_EU_LTR_BUFFER_CONTROL          0x018CU
+#define VIDEO_SET_CUR_EU_LTR_PICTURE_CONTROL         0x018DU
+#define VIDEO_SET_CUR_EU_LTR_VALIDATION_CONTROL      0x018EU
+#define VIDEO_SET_CUR_EU_LEVEL_IDC_LIMIT_CONTROL     0x018FU
+#define VIDEO_SET_CUR_EU_SEI_PAYLOADTYPE_CONTROL     0x0190U
+#define VIDEO_SET_CUR_EU_QP_RANGE_CONTROL            0x0191U
+#define VIDEO_SET_CUR_EU_PRIORITY_CONTROL            0x0192U
+#define VIDEO_SET_CUR_EU_START_OR_STOP_LAYER_CONTROL 0x0193U
+#define VIDEO_SET_CUR_EU_ERROR_RESILIENCY_CONTROL    0x0194U
+#endif
+
+/*! @brief The payload header structure for MJPEG payload format. */
+struct video_mjpeg_payload_header {
+    uint8_t bHeaderLength; /*!< The payload header length. */
+    union {
+        uint8_t bmheaderInfo; /*!< The payload header bitmap field. */
+        struct
+        {
+            uint8_t frameIdentifier : 1U; /*!< Frame Identifier. This bit toggles at each frame start boundary and stays
+                                             constant for the rest of the frame.*/
+            uint8_t endOfFrame      : 1U; /*!< End of Frame. This bit indicates the end of a video frame and is set in the
+                                        last video sample that belongs to a frame.*/
+            uint8_t
+                presentationTimeStamp    : 1U; /*!< Presentation Time Stamp. This bit, when set, indicates the presence of
+                                               a PTS field.*/
+            uint8_t sourceClockReference : 1U; /*!< Source Clock Reference. This bit, when set, indicates the presence
+                                                  of a SCR field.*/
+            uint8_t reserved             : 1U; /*!< Reserved. Set to 0. */
+            uint8_t stillImage           : 1U; /*!< Still Image. This bit, when set, identifies a video sample that belongs to a
+                                         still image.*/
+            uint8_t errorBit             : 1U; /*!< Error Bit. This bit, when set, indicates an error in the device streaming.*/
+            uint8_t endOfHeader          : 1U; /*!< End of Header. This bit, when set, indicates the end of the BFH fields.*/
+        } headerInfoBits;
+        struct
+        {
+            uint8_t FID : 1U; /*!< Frame Identifier. This bit toggles at each frame start boundary and stays constant
+                                 for the rest of the frame.*/
+            uint8_t EOI : 1U; /*!< End of Frame. This bit indicates the end of a video frame and is set in the last
+                                 video sample that belongs to a frame.*/
+            uint8_t PTS : 1U; /*!< Presentation Time Stamp. This bit, when set, indicates the presence of a PTS field.*/
+            uint8_t SCR : 1U; /*!< Source Clock Reference. This bit, when set, indicates the presence of a SCR field.*/
+            uint8_t RES : 1U; /*!< Reserved. Set to 0. */
+            uint8_t STI : 1U; /*!< Still Image. This bit, when set, identifies a video sample that belongs to a still
+                                 image.*/
+            uint8_t ERR : 1U; /*!< Error Bit. This bit, when set, indicates an error in the device streaming.*/
+            uint8_t EOH : 1U; /*!< End of Header. This bit, when set, indicates the end of the BFH fields.*/
+        } headerInfoBitmap;
+    } headerInfoUnion;
+    uint32_t dwPresentationTime;      /*!< Presentation time stamp (PTS) field.*/
+    uint8_t bSourceClockReference[6]; /*!< Source clock reference (SCR) field.*/
+} __packed;
+
+/*! @brief The Video probe and commit controls structure.*/
+struct video_probe_and_commit_controls {
+    union {
+        uint8_t bmHint; /*!< Bit-field control indicating to the function what fields shall be kept fixed. */
+        struct
+        {
+            uint8_t dwFrameInterval : 1U; /*!< dwFrameInterval field.*/
+            uint8_t wKeyFrameRate   : 1U; /*!< wKeyFrameRate field.*/
+            uint8_t wPFrameRate     : 1U; /*!< wPFrameRate field.*/
+            uint8_t wCompQuality    : 1U; /*!< wCompQuality field.*/
+            uint8_t wCompWindowSize : 1U; /*!< wCompWindowSize field.*/
+            uint8_t reserved        : 3U; /*!< Reserved field.*/
+        } hintBitmap;
+    } hintUnion;
+    union {
+        uint8_t bmHint; /*!< Bit-field control indicating to the function what fields shall be kept fixed. */
+        struct
+        {
+            uint8_t reserved : 8U; /*!< Reserved field.*/
+        } hintBitmap;
+    } hintUnion1;
+    uint8_t bFormatIndex;              /*!< Video format index from a format descriptor.*/
+    uint8_t bFrameIndex;               /*!< Video frame index from a frame descriptor.*/
+    uint32_t dwFrameInterval;          /*!< Frame interval in 100ns units.*/
+    uint16_t wKeyFrameRate;            /*!< Key frame rate in key-frame per video-frame units.*/
+    uint16_t wPFrameRate;              /*!< PFrame rate in PFrame/key frame units.*/
+    uint16_t wCompQuality;             /*!< Compression quality control in abstract units 0U (lowest) to 10000U (highest).*/
+    uint16_t wCompWindowSize;          /*!< Window size for average bit rate control.*/
+    uint16_t wDelay;                   /*!< Internal video streaming interface latency in ms from video data capture to presentation on
+                        the USB.*/
+    uint32_t dwMaxVideoFrameSize;      /*!< Maximum video frame or codec-specific segment size in bytes.*/
+    uint32_t dwMaxPayloadTransferSize; /*!< Specifies the maximum number of bytes that the device can transmit or
+                                          receive in a single payload transfer.*/
+    uint32_t dwClockFrequency;         /*!< The device clock frequency in Hz for the specified format. This specifies the
+                                  units used for the time information fields in the Video Payload Headers in the data
+                                  stream.*/
+    uint8_t bmFramingInfo;             /*!< Bit-field control supporting the following values: D0 Frame ID, D1 EOF.*/
+    uint8_t bPreferedVersion;          /*!< The preferred payload format version supported by the host or device for the
+                                  specified bFormatIndex value.*/
+    uint8_t bMinVersion;               /*!< The minimum payload format version supported by the device for the specified bFormatIndex
+                            value.*/
+    uint8_t bMaxVersion;               /*!< The maximum payload format version supported by the device for the specified bFormatIndex
+                            value.*/
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+    uint8_t bUsage; /*!< This bitmap enables features reported by the bmUsages field of the Video Frame Descriptor.*/
+    uint8_t
+        bBitDepthLuma;                  /*!< Represents bit_depth_luma_minus8 + 8U, which must be the same as bit_depth_chroma_minus8 +
+                           8.*/
+    uint8_t bmSettings;                 /*!< A bitmap of flags that is used to discover and control specific features of a temporally
+                           encoded video stream.*/
+    uint8_t bMaxNumberOfRefFramesPlus1; /*!< Host indicates the maximum number of frames stored for use as references.*/
+    uint16_t bmRateControlModes;        /*!< This field contains 4U sub-fields, each of which is a 4U bit number.*/
+    uint64_t bmLayoutPerStream;         /*!< This field contains 4U sub-fields, each of which is a 2U byte number.*/
+#endif
+} __packed;
+
+/*! @brief The Video still probe and still commit controls structure.*/
+struct video_still_probe_and_commit_controls {
+    uint8_t bFormatIndex;              /*!< Video format index from a format descriptor.*/
+    uint8_t bFrameIndex;               /*!< Video frame index from a frame descriptor.*/
+    uint8_t bCompressionIndex;         /*!< Compression index from a frame descriptor.*/
+    uint32_t dwMaxVideoFrameSize;      /*!< Maximum still image size in bytes.*/
+    uint32_t dwMaxPayloadTransferSize; /*!< Specifies the maximum number of bytes that the device can transmit or
+                                          receive in a single payload transfer.*/
+} __packed;
+
+void usbd_video_sof_callback(void);
+void usbd_video_set_interface_callback(uint8_t value);
+void usbd_video_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_VIDEO_H_ */
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/webusb/usbd_webusb.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/webusb/usbd_webusb.h
new file mode 100644
index 0000000000000000000000000000000000000000..a74f7380cc0440639faefe56396997efe71b414d
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/webusb/usbd_webusb.h
@@ -0,0 +1,37 @@
+#ifndef _USBD_WEBUSB_H
+#define _USBD_WEBUSB_H
+
+/* WebUSB Descriptor Types */
+#define WEBUSB_DESCRIPTOR_SET_HEADER_TYPE       0x00
+#define WEBUSB_CONFIGURATION_SUBSET_HEADER_TYPE 0x01
+#define WEBUSB_FUNCTION_SUBSET_HEADER_TYPE      0x02
+#define WEBUSB_URL_TYPE                         0x03
+
+/* WebUSB Request Codes */
+#define WEBUSB_REQUEST_GET_URL 0x02
+
+/* bScheme in URL descriptor */
+#define WEBUSB_URL_SCHEME_HTTP  0x00
+#define WEBUSB_URL_SCHEME_HTTPS 0x01
+
+/* WebUSB Descriptor sizes */
+#define WEBUSB_DESCRIPTOR_SET_HEADER_SIZE       5
+#define WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE 4
+#define WEBUSB_FUNCTION_SUBSET_HEADER_SIZE      3
+
+/* BOS Capability webusb */
+struct usb_bos_webusb_platform_capability_descriptor {
+    struct usb_bos_capability_descriptor webusb_platform;
+    uint16_t bcdVersion;
+    uint8_t bVendorCode;
+    uint8_t iLandingPage;
+} __packed;
+
+struct webusb_url_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bScheme;
+    char URL[];
+} __packed;
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/winusb/usbd_winusb.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/winusb/usbd_winusb.h
new file mode 100644
index 0000000000000000000000000000000000000000..007f5380bf46a4b059181ccee2ff0d6595b7903c
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/class/winusb/usbd_winusb.h
@@ -0,0 +1,35 @@
+#ifndef _USBD_WINUSB_H
+#define _USBD_WINUSB_H
+
+/* WinUSB Microsoft OS 2.0 descriptor request codes */
+#define WINUSB_REQUEST_GET_DESCRIPTOR_SET 0x07
+#define WINUSB_REQUEST_SET_ALT_ENUM       0x08
+
+/* WinUSB Microsoft OS 2.0 descriptor sizes */
+#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE  10
+#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8
+#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE  20
+
+/* WinUSB Microsoft OS 2.0 Descriptor Types */
+#define WINUSB_SET_HEADER_DESCRIPTOR_TYPE       0x00
+#define WINUSB_SUBSET_HEADER_CONFIGURATION_TYPE 0x01
+#define WINUSB_SUBSET_HEADER_FUNCTION_TYPE      0x02
+#define WINUSB_FEATURE_COMPATIBLE_ID_TYPE       0x03
+#define WINUSB_FEATURE_REG_PROPERTY_TYPE        0x04
+#define WINUSB_FEATURE_MIN_RESUME_TIME_TYPE     0x05
+#define WINUSB_FEATURE_MODEL_ID_TYPE            0x06
+#define WINUSB_FEATURE_CCGP_DEVICE_TYPE         0x07
+
+#define WINUSB_PROP_DATA_TYPE_REG_SZ       0x01
+#define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07
+
+/* WinUSB Microsoft OS 2.0 descriptor Platform Capability Descriptor */
+struct usb_bos_winusb_platform_capability_descriptor {
+    struct usb_bos_capability_descriptor winusb_platform;
+    uint32_t dwWindowsVersion;
+    uint16_t wMSOSDescriptorSetTotalLength;
+    uint8_t bMS_VendorCode;
+    uint8_t bAltEnumCode;
+} __packed;
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_dc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_dc.h
new file mode 100644
index 0000000000000000000000000000000000000000..48dd2224e0b1772df0396bdac80bb2080dd01309
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_dc.h
@@ -0,0 +1,179 @@
+#ifndef _USB_DC_H
+#define _USB_DC_H
+
+#include "stdint.h"
+#include "bflb_platform.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief USB Device Controller API
+ * @defgroup _usb_device_controller_api USB Device Controller API
+ * @{
+ */
+/**< maximum packet size (MPS) for EP 0 */
+#define USB_CTRL_EP_MPS 64
+/**
+ * USB endpoint Transfer Type mask.
+ */
+#define USBD_EP_TYPE_CTRL 0
+#define USBD_EP_TYPE_ISOC 1
+#define USBD_EP_TYPE_BULK 2
+#define USBD_EP_TYPE_INTR 3
+#define USBD_EP_TYPE_MASK 3
+
+/* Default USB control EP, always 0 and 0x80 */
+#define USB_CONTROL_OUT_EP0 0
+#define USB_CONTROL_IN_EP0  0x80
+
+/**
+ * @brief USB Endpoint Transfer Type
+ */
+enum usb_dc_ep_transfer_type {
+    /** Control type endpoint */
+    USB_DC_EP_CONTROL = 0,
+    /** Isochronous type endpoint */
+    USB_DC_EP_ISOCHRONOUS,
+    /** Bulk type endpoint */
+    USB_DC_EP_BULK,
+    /** Interrupt type endpoint  */
+    USB_DC_EP_INTERRUPT
+};
+
+/**
+ * @brief USB Endpoint Configuration.
+ *
+ * Structure containing the USB endpoint configuration.
+ */
+struct usbd_endpoint_cfg {
+    /** The number associated with the EP in the device
+     *  configuration structure
+     *       IN  EP = 0x80 | \
+     *       OUT EP = 0x00 | \
+     */
+    uint8_t ep_addr;
+    /** Endpoint max packet size */
+    uint16_t ep_mps;
+    /** Endpoint Transfer Type.
+     * May be Bulk, Interrupt, Control or Isochronous
+     */
+    enum usb_dc_ep_transfer_type ep_type;
+};
+
+/**
+ * @brief USB Device Core Layer API
+ * @defgroup _usb_device_core_api USB Device Core API
+ * @{
+ */
+
+/**
+ * @brief Set USB device address
+ *
+ * @param[in] addr Device address
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_set_address(const uint8_t addr);
+
+/*
+ * @brief configure and enable endpoint
+ *
+ * This function sets endpoint configuration according to one specified in USB
+ * endpoint descriptor and then enables it for data transfers.
+ *
+ * @param [in]  ep_desc Endpoint descriptor byte array
+ *
+ * @return true if successfully configured and enabled
+ */
+int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg);
+/**
+ * @brief Disable the selected endpoint
+ *
+ * Function to disable the selected endpoint. Upon success interrupts are
+ * disabled for the corresponding endpoint and the endpoint is no longer able
+ * for transmitting/receiving data.
+ *
+ * @param[in] ep Endpoint address corresponding to the one
+ *               listed in the device configuration table
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_close(const uint8_t ep);
+/**
+ * @brief Set stall condition for the selected endpoint
+ *
+ * @param[in] ep Endpoint address corresponding to the one
+ *               listed in the device configuration table
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_set_stall(const uint8_t ep);
+/**
+ * @brief Clear stall condition for the selected endpoint
+ *
+ * @param[in] ep Endpoint address corresponding to the one
+ *               listed in the device configuration table
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_clear_stall(const uint8_t ep);
+/**
+ * @brief Check if the selected endpoint is stalled
+ *
+ * @param[in]  ep       Endpoint address corresponding to the one
+ *                      listed in the device configuration table
+ * @param[out] stalled  Endpoint stall status
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled);
+/**
+ * @brief Write data to the specified endpoint
+ *
+ * This function is called to write data to the specified endpoint. The
+ * supplied usbd_endpoint_callback function will be called when data is transmitted
+ * out.
+ *
+ * @param[in]  ep        Endpoint address corresponding to the one
+ *                       listed in the device configuration table
+ * @param[in]  data      Pointer to data to write
+ * @param[in]  data_len  Length of the data requested to write. This may
+ *                       be zero for a zero length status packet.
+ * @param[out] ret_bytes Bytes scheduled for transmission. This value
+ *                       may be NULL if the application expects all
+ *                       bytes to be written
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes);
+/**
+ * @brief Read data from the specified endpoint
+ *
+ * This is similar to usb_dc_ep_read, the difference being that, it doesn't
+ * clear the endpoint NAKs so that the consumer is not bogged down by further
+ * upcalls till he is done with the processing of the data. The caller should
+ * reactivate ep by invoking usb_dc_ep_read_continue() do so.
+ *
+ * @param[in]  ep           Endpoint address corresponding to the one
+ *                          listed in the device configuration table
+ * @param[in]  data         Pointer to data buffer to write to
+ * @param[in]  max_data_len Max length of data to read
+ * @param[out] read_bytes   Number of bytes read. If data is NULL and
+ *                          max_data_len is 0 the number of bytes
+ *                          available for read should be returned.
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_def.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_def.h
new file mode 100644
index 0000000000000000000000000000000000000000..ecee08865015cd08fcd556451349497a570ba171
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_def.h
@@ -0,0 +1,522 @@
+#ifndef USB_REQUEST_H
+#define USB_REQUEST_H
+
+/* Useful define */
+#define USB_1_1 0x0110
+#define USB_2_0 0x0200
+/* Set USB version to 2.1 so that the host will request the BOS descriptor */
+#define USB_2_1 0x0210
+
+// USB Speed
+#define USB_SPEED_LOW  0U
+#define USB_SPEED_FULL 1U
+#define USB_SPEED_HIGH 2U
+
+// USB PID Types
+#define USB_PID_RESERVED 0U
+#define USB_PID_OUT      1U
+#define USB_PID_ACK      2U
+#define USB_PID_DATA0    3U
+#define USB_PID_PING     4U
+#define USB_PID_SOF      5U
+#define USB_PID_DATA2    7U
+#define USB_PID_NYET     6U
+#define USB_PID_SPLIT    8U
+#define USB_PID_IN       9U
+#define USB_PID_NAK      10U
+#define USB_PID_DATA1    11U
+#define USB_PID_PRE      12U
+#define USB_PID_ERR      12U
+#define USB_PID_SETUP    13U
+#define USB_PID_STALL    14U
+#define USB_PID_MDATA    15U
+
+// bmRequestType.Dir
+#define USB_REQUEST_HOST_TO_DEVICE 0U
+#define USB_REQUEST_DEVICE_TO_HOST 1U
+
+// bmRequestType.Type
+#define USB_REQUEST_STANDARD 0U
+#define USB_REQUEST_CLASS    1U
+#define USB_REQUEST_VENDOR   2U
+#define USB_REQUEST_RESERVED 3U
+
+// bmRequestType.Recipient
+#define USB_REQUEST_TO_DEVICE    0U
+#define USB_REQUEST_TO_INTERFACE 1U
+#define USB_REQUEST_TO_ENDPOINT  2U
+#define USB_REQUEST_TO_OTHER     3U
+
+/* USB Standard Request Codes */
+#define USB_REQUEST_GET_STATUS          0x00
+#define USB_REQUEST_CLEAR_FEATURE       0x01
+#define USB_REQUEST_SET_FEATURE         0x03
+#define USB_REQUEST_SET_ADDRESS         0x05
+#define USB_REQUEST_GET_DESCRIPTOR      0x06
+#define USB_REQUEST_SET_DESCRIPTOR      0x07
+#define USB_REQUEST_GET_CONFIGURATION   0x08
+#define USB_REQUEST_SET_CONFIGURATION   0x09
+#define USB_REQUEST_GET_INTERFACE       0x0A
+#define USB_REQUEST_SET_INTERFACE       0x0B
+#define USB_REQUEST_SYNCH_FRAME         0x0C
+#define USB_REQUEST_SET_ENCRYPTION      0x0D
+#define USB_REQUEST_GET_ENCRYPTION      0x0E
+#define USB_REQUEST_RPIPE_ABORT         0x0E
+#define USB_REQUEST_SET_HANDSHAKE       0x0F
+#define USB_REQUEST_RPIPE_RESET         0x0F
+#define USB_REQUEST_GET_HANDSHAKE       0x10
+#define USB_REQUEST_SET_CONNECTION      0x11
+#define USB_REQUEST_SET_SECURITY_DATA   0x12
+#define USB_REQUEST_GET_SECURITY_DATA   0x13
+#define USB_REQUEST_SET_WUSB_DATA       0x14
+#define USB_REQUEST_LOOPBACK_DATA_WRITE 0x15
+#define USB_REQUEST_LOOPBACK_DATA_READ  0x16
+#define USB_REQUEST_SET_INTERFACE_DS    0x17
+
+/* USB GET_STATUS Bit Values */
+#define USB_GETSTATUS_SELF_POWERED   0x01
+#define USB_GETSTATUS_REMOTE_WAKEUP  0x02
+#define USB_GETSTATUS_ENDPOINT_STALL 0x01
+
+/* USB Standard Feature selectors */
+#define USB_FEATURE_ENDPOINT_STALL 0
+#define USB_FEATURE_REMOTE_WAKEUP  1
+#define USB_FEATURE_TEST_MODE      2
+
+/* Descriptor size in bytes */
+#define USB_DEVICE_DESC_SIZE          0x12
+#define USB_CONFIGURATION_DESC_SIZE   0x09
+#define USB_INTERFACE_DESC_SIZE       0x09
+#define USB_ENDPOINT_DESC_SIZE        0x07
+#define USB_LANGID_STRING_DESC_SIZE   0x04
+#define USB_OTHER_SPEED_DESC_SIZE     0x09
+#define USB_DEVICE_QUAL_DESC_SIZE     0x0A
+#define USB_INTERFACE_ASSOC_DESC_SIZE 0x08
+#define USB_FUNCTION_DESC_SIZE        0x03
+#define USB_OTG_DESC_SIZE             0x03
+
+/* USB Descriptor Types */
+#define USB_DESCRIPTOR_TYPE_DEVICE                0x01U
+#define USB_DESCRIPTOR_TYPE_CONFIGURATION         0x02U
+#define USB_DESCRIPTOR_TYPE_STRING                0x03U
+#define USB_DESCRIPTOR_TYPE_INTERFACE             0x04U
+#define USB_DESCRIPTOR_TYPE_ENDPOINT              0x05U
+#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER      0x06U
+#define USB_DESCRIPTOR_TYPE_OTHER_SPEED           0x07U
+#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER       0x08U
+#define USB_DESCRIPTOR_TYPE_OTG                   0x09U
+#define USB_DESCRIPTOR_TYPE_DEBUG                 0x0AU
+#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION 0x0BU
+#define USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE   0x0FU
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY     0x10U
+
+#define USB_DESCRIPTOR_TYPE_FUNCTIONAL 0x21U
+
+// Class Specific Descriptor
+#define USB_CS_DESCRIPTOR_TYPE_DEVICE        0x21U
+#define USB_CS_DESCRIPTOR_TYPE_CONFIGURATION 0x22U
+#define USB_CS_DESCRIPTOR_TYPE_STRING        0x23U
+#define USB_CS_DESCRIPTOR_TYPE_INTERFACE     0x24U
+#define USB_CS_DESCRIPTOR_TYPE_ENDPOINT      0x25U
+
+#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ENDPOINT_COMPANION     0x30U
+#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ISO_ENDPOINT_COMPANION 0x31U
+
+/* USB Device Classes */
+#define USB_DEVICE_CLASS_RESERVED      0x00
+#define USB_DEVICE_CLASS_AUDIO         0x01
+#define USB_DEVICE_CLASS_CDC           0x02
+#define USB_DEVICE_CLASS_HID           0x03
+#define USB_DEVICE_CLASS_MONITOR       0x04
+#define USB_DEVICE_CLASS_PHYSICAL      0x05
+#define USB_DEVICE_CLASS_IMAGE         0x06
+#define USB_DEVICE_CLASS_PRINTER       0x07
+#define USB_DEVICE_CLASS_MASS_STORAGE  0x08
+#define USB_DEVICE_CLASS_HUB           0x09
+#define USB_DEVICE_CLASS_CDC_DATA      0x0a
+#define USB_DEVICE_CLASS_SMART_CARD    0x0b
+#define USB_DEVICE_CLASS_SECURITY      0x0d
+#define USB_DEVICE_CLASS_VIDEO         0x0e
+#define USB_DEVICE_CLASS_HEALTHCARE    0x0f
+#define USB_DEVICE_CLASS_DIAG_DEVICE   0xdc
+#define USB_DEVICE_CLASS_WIRELESS      0xe0
+#define USB_DEVICE_CLASS_MISC          0xef
+#define USB_DEVICE_CLASS_APP_SPECIFIC  0xfe
+#define USB_DEVICE_CLASS_VEND_SPECIFIC 0xff
+
+/* usb string index define */
+#define USB_STRING_LANGID_INDEX    0x00
+#define USB_STRING_MFC_INDEX       0x01
+#define USB_STRING_PRODUCT_INDEX   0x02
+#define USB_STRING_SERIAL_INDEX    0x03
+#define USB_STRING_CONFIG_INDEX    0x04
+#define USB_STRING_INTERFACE_INDEX 0x05
+#define USB_STRING_OS_INDEX        0x06
+#define USB_STRING_MAX             USB_STRING_OS_INDEX
+/*
+ * Devices supporting Microsoft OS Descriptors store special string
+ * descriptor at fixed index (0xEE). It is read when a new device is
+ * attached to a computer for the first time.
+ */
+#define USB_OSDESC_STRING_DESC_INDEX 0xEE
+
+/* bmAttributes in Configuration Descriptor */
+#define USB_CONFIG_POWERED_MASK  0x40
+#define USB_CONFIG_BUS_POWERED   0x80
+#define USB_CONFIG_SELF_POWERED  0xC0
+#define USB_CONFIG_REMOTE_WAKEUP 0x20
+
+/* bMaxPower in Configuration Descriptor */
+#define USB_CONFIG_POWER_MA(mA) ((mA) / 2)
+
+/* bEndpointAddress in Endpoint Descriptor */
+#define USB_ENDPOINT_DIRECTION_MASK 0x80
+#define USB_ENDPOINT_OUT(addr)      ((addr) | 0x00)
+#define USB_ENDPOINT_IN(addr)       ((addr) | 0x80)
+
+/* bmAttributes in Endpoint Descriptor */
+#define USB_ENDPOINT_TYPE_MASK               0x03
+#define USB_ENDPOINT_TYPE_CONTROL            0x00
+#define USB_ENDPOINT_TYPE_ISOCHRONOUS        0x01
+#define USB_ENDPOINT_TYPE_BULK               0x02
+#define USB_ENDPOINT_TYPE_INTERRUPT          0x03
+#define USB_ENDPOINT_SYNC_MASK               0x0C
+#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00
+#define USB_ENDPOINT_SYNC_ASYNCHRONOUS       0x04
+#define USB_ENDPOINT_SYNC_ADAPTIVE           0x08
+#define USB_ENDPOINT_SYNC_SYNCHRONOUS        0x0C
+#define USB_ENDPOINT_USAGE_MASK              0x30
+#define USB_ENDPOINT_USAGE_DATA              0x00
+#define USB_ENDPOINT_USAGE_FEEDBACK          0x10
+#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20
+#define USB_ENDPOINT_USAGE_RESERVED          0x30
+
+/* bDevCapabilityType in Device Capability Descriptor */
+#define USB_DEVICE_CAPABILITY_WIRELESS_USB                1
+#define USB_DEVICE_CAPABILITY_USB_2_0_EXTENSION           2
+#define USB_DEVICE_CAPABILITY_SUPERSPEED_USB              3
+#define USB_DEVICE_CAPABILITY_CONTAINER_ID                4
+#define USB_DEVICE_CAPABILITY_PLATFORM                    5
+#define USB_DEVICE_CAPABILITY_POWER_DELIVERY_CAPABILITY   6
+#define USB_DEVICE_CAPABILITY_BATTERY_INFO_CAPABILITY     7
+#define USB_DEVICE_CAPABILITY_PD_CONSUMER_PORT_CAPABILITY 8
+#define USB_DEVICE_CAPABILITY_PD_PROVIDER_PORT_CAPABILITY 9
+#define USB_DEVICE_CAPABILITY_SUPERSPEED_PLUS             10
+#define USB_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT  11
+#define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT            12
+
+#define USB_BOS_CAPABILITY_EXTENSION 0x02
+#define USB_BOS_CAPABILITY_PLATFORM  0x05
+
+/* Setup packet definition used to read raw data from USB line */
+struct usb_setup_packet {
+    __packed union {
+        uint8_t bmRequestType; /* bmRequestType */
+        struct
+        {
+            uint8_t Recipient : 5; /* D4..0: Recipient */
+            uint8_t Type      : 2; /* D6..5: Type */
+            uint8_t Dir       : 1; /* D7:    Data Phase Txsfer Direction */
+        } bmRequestType_b;
+    };
+    uint8_t bRequest;
+    __packed union {
+        uint16_t wValue; /* wValue */
+        struct
+        {
+            uint8_t wValueL;
+            uint8_t wValueH;
+        };
+    };
+    __packed union {
+        uint16_t wIndex; /* wIndex */
+        struct
+        {
+            uint8_t wIndexL;
+            uint8_t wIndexH;
+        };
+    };
+    uint16_t wLength;
+} __packed;
+
+/** Standard Device Descriptor */
+struct usb_device_descriptor {
+    uint8_t bLength;            /* Descriptor size in bytes = 18 */
+    uint8_t bDescriptorType;    /* DEVICE descriptor type = 1 */
+    uint16_t bcdUSB;            /* USB spec in BCD, e.g. 0x0200 */
+    uint8_t bDeviceClass;       /* Class code, if 0 see interface */
+    uint8_t bDeviceSubClass;    /* Sub-Class code, 0 if class = 0 */
+    uint8_t bDeviceProtocol;    /* Protocol, if 0 see interface */
+    uint8_t bMaxPacketSize0;    /* Endpoint 0 max. size */
+    uint16_t idVendor;          /* Vendor ID per USB-IF */
+    uint16_t idProduct;         /* Product ID per manufacturer */
+    uint16_t bcdDevice;         /* Device release # in BCD */
+    uint8_t iManufacturer;      /* Index to manufacturer string */
+    uint8_t iProduct;           /* Index to product string */
+    uint8_t iSerialNumber;      /* Index to serial number string */
+    uint8_t bNumConfigurations; /* Number of possible configurations */
+} __packed;
+
+/** USB device_qualifier descriptor */
+struct usb_device_qualifier_descriptor {
+    uint8_t bLength;            /* Descriptor size in bytes = 10 */
+    uint8_t bDescriptorType;    /* DEVICE QUALIFIER type = 6 */
+    uint16_t bcdUSB;            /* USB spec in BCD, e.g. 0x0200 */
+    uint8_t bDeviceClass;       /* Class code, if 0 see interface */
+    uint8_t bDeviceSubClass;    /* Sub-Class code, 0 if class = 0 */
+    uint8_t bDeviceProtocol;    /* Protocol, if 0 see interface */
+    uint8_t bMaxPacketSize;     /* Endpoint 0 max. size */
+    uint8_t bNumConfigurations; /* Number of possible configurations */
+    uint8_t bReserved;          /* Reserved = 0 */
+} __packed;
+
+/** Standard Configuration Descriptor */
+struct usb_configuration_descriptor {
+    uint8_t bLength;             /* Descriptor size in bytes = 9 */
+    uint8_t bDescriptorType;     /* CONFIGURATION type = 2 or 7 */
+    uint16_t wTotalLength;       /* Length of concatenated descriptors */
+    uint8_t bNumInterfaces;      /* Number of interfaces, this config. */
+    uint8_t bConfigurationValue; /* Value to set this config. */
+    uint8_t iConfiguration;      /* Index to configuration string */
+    uint8_t bmAttributes;        /* Config. characteristics */
+    uint8_t bMaxPower;           /* Max.power from bus, 2mA units */
+} __packed;
+
+/** Standard Interface Descriptor */
+struct usb_interface_descriptor {
+    uint8_t bLength;            /* Descriptor size in bytes = 9 */
+    uint8_t bDescriptorType;    /* INTERFACE descriptor type = 4 */
+    uint8_t bInterfaceNumber;   /* Interface no.*/
+    uint8_t bAlternateSetting;  /* Value to select this IF */
+    uint8_t bNumEndpoints;      /* Number of endpoints excluding 0 */
+    uint8_t bInterfaceClass;    /* Class code, 0xFF = vendor */
+    uint8_t bInterfaceSubClass; /* Sub-Class code, 0 if class = 0 */
+    uint8_t bInterfaceProtocol; /* Protocol, 0xFF = vendor */
+    uint8_t iInterface;         /* Index to interface string */
+} __packed;
+
+/** Standard Endpoint Descriptor */
+struct usb_endpoint_descriptor {
+    uint8_t bLength;          /* Descriptor size in bytes = 7 */
+    uint8_t bDescriptorType;  /* ENDPOINT descriptor type = 5 */
+    uint8_t bEndpointAddress; /* Endpoint # 0 - 15 | IN/OUT */
+    uint8_t bmAttributes;     /* Transfer type */
+    uint16_t wMaxPacketSize;  /* Bits 10:0 = max. packet size */
+    uint8_t bInterval;        /* Polling interval in (micro) frames */
+} __packed;
+
+/** Unicode (UTF16LE) String Descriptor */
+struct usb_string_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t bString;
+} __packed;
+
+/* USB Interface Association Descriptor */
+struct usb_interface_association_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bFirstInterface;
+    uint8_t bInterfaceCount;
+    uint8_t bFunctionClass;
+    uint8_t bFunctionSubClass;
+    uint8_t bFunctionProtocol;
+    uint8_t iFunction;
+} __packed;
+
+/* MS OS 1.0 string descriptor */
+struct usb_msosv1_string_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bString[14];
+    uint8_t bMS_VendorCode; /* Vendor Code, used for a control request */
+    uint8_t bPad;           /* Padding byte for VendorCode look as UTF16 */
+} __packed;
+
+/* MS OS 1.0 Header descriptor */
+struct usb_msosv1_compat_id_header_descriptor {
+    uint32_t dwLength;
+    uint16_t bcdVersion;
+    uint16_t wIndex;
+    uint8_t bCount;
+    uint8_t reserved[7];
+} __packed;
+
+/* MS OS 1.0 Function descriptor */
+struct usb_msosv1_comp_id_function_descriptor {
+    uint8_t bFirstInterfaceNumber;
+    uint8_t reserved1;
+    uint8_t compatibleID[8];
+    uint8_t subCompatibleID[8];
+    uint8_t reserved2[6];
+} __packed;
+
+#define usb_msosv1_comp_id_property_create(x)                                \
+    struct usb_msosv1_comp_id_property {                                     \
+        struct usb_msosv1_compat_id_header_descriptor compat_id_header;      \
+        struct usb_msosv1_comp_id_function_descriptor compat_id_function[x]; \
+    };
+
+struct usb_msosv1_descriptor {
+    uint8_t *string;
+    uint8_t string_len;
+    uint8_t vendor_code;
+    uint8_t *compat_id;
+    uint16_t compat_id_len;
+    uint8_t *comp_id_property;
+    uint16_t comp_id_property_len;
+};
+
+/* MS OS 2.0 Header descriptor */
+struct usb_msosv2_property_header_descriptor {
+    uint32_t dwLength;
+    uint16_t bcdVersion;
+    uint16_t wIndex;
+    uint8_t bCount;
+} __packed;
+
+/* WinUSB Microsoft OS 2.0 descriptor set header */
+struct winusb_header_descriptor {
+    uint16_t wLength;
+    uint16_t wDescriptorType;
+    uint32_t dwWindowsVersion;
+    uint16_t wDescriptorSetTotalLength;
+} __packed;
+
+/* WinUSB Microsoft OS 2.0 subset function descriptor  */
+struct winusb_subset_function_descriptor {
+    uint16_t wLength;
+    uint16_t wDescriptorType;
+    uint8_t bFirstInterface;
+    uint8_t bReserved;
+    uint16_t wSubsetLength;
+} __packed;
+
+/* MS OS 2.0 Function Section */
+struct usb_msosv2_comp_id_function_descriptor {
+    uint16_t wLength;
+    uint16_t wDescriptorType;
+    uint8_t compatibleID[8];
+    uint8_t subCompatibleID[8];
+} __packed;
+
+/* MS OS 2.0 property descriptor */
+struct usb_msosv2_proerty_descriptor {
+    uint16_t wLength;
+    uint16_t wDescriptorType;
+    uint32_t dwPropertyDataType;
+    uint16_t wPropertyNameLength;
+    const char *bPropertyName;
+    uint32_t dwPropertyDataLength;
+    const char *bPropertyData;
+};
+
+struct usb_msosv2_descriptor {
+    uint8_t *compat_id;
+    uint16_t compat_id_len;
+};
+
+/* BOS Descriptor */
+struct usb_bos_header_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t wTotalLength;
+    uint8_t bNumDeviceCaps;
+} __packed;
+
+/* BOS Capability Descriptor */
+struct usb_bos_capability_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDevCapabilityType;
+    uint8_t bReserved;
+    uint8_t PlatformCapabilityUUID[16];
+} __packed;
+
+struct usb_bos_capability_lpm {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDevCapabilityType;
+    uint32_t bmAttributes;
+} __packed;
+
+struct usb_bos_descriptor {
+    uint8_t *bos_id;
+    uint8_t bos_id_len;
+};
+
+/* USB Device Capability Descriptor */
+struct usb_device_capability__descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDevCapabilityType;
+} __packed;
+
+/** USB descriptor header */
+struct usb_desc_header {
+    uint8_t bLength;         /**< descriptor length */
+    uint8_t bDescriptorType; /**< descriptor type */
+};
+
+#define USB_DEVICE_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, idVendor, idProduct, bcdDevice, bNumConfigurations) \
+    0x12,                           /* bLength */                                                                                              \
+        USB_DESCRIPTOR_TYPE_DEVICE, /* bDescriptorType */                                                                                      \
+        WBVAL(bcdUSB),              /* bcdUSB */                                                                                               \
+        bDeviceClass,               /* bDeviceClass */                                                                                         \
+        bDeviceSubClass,            /* bDeviceSubClass */                                                                                      \
+        bDeviceProtocol,            /* bDeviceProtocol */                                                                                      \
+        0x40,                       /* bMaxPacketSize */                                                                                       \
+        WBVAL(idVendor),            /* idVendor */                                                                                             \
+        WBVAL(idProduct),           /* idProduct */                                                                                            \
+        WBVAL(bcdDevice),           /* bcdDevice */                                                                                            \
+        USB_STRING_MFC_INDEX,       /* iManufacturer */                                                                                        \
+        USB_STRING_PRODUCT_INDEX,   /* iProduct */                                                                                             \
+        USB_STRING_SERIAL_INDEX,    /* iSerial */                                                                                              \
+        bNumConfigurations          /* bNumConfigurations */
+
+#define USB_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \
+    0x09,                                  /* bLength */                                                       \
+        USB_DESCRIPTOR_TYPE_CONFIGURATION, /* bDescriptorType */                                               \
+        WBVAL(wTotalLength),               /* wTotalLength */                                                  \
+        bNumInterfaces,                    /* bNumInterfaces */                                                \
+        bConfigurationValue,               /* bConfigurationValue */                                           \
+        0x00,                              /* iConfiguration */                                                \
+        bmAttributes,                      /* bmAttributes */                                                  \
+        USB_CONFIG_POWER_MA(bMaxPower)     /* bMaxPower */
+
+#define USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints,                  \
+                                      bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, iInterface) \
+    0x09,                              /* bLength */                                                       \
+        USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */                                               \
+        bInterfaceNumber,              /* bInterfaceNumber */                                              \
+        bAlternateSetting,             /* bAlternateSetting */                                             \
+        bNumEndpoints,                 /* bNumEndpoints */                                                 \
+        bInterfaceClass,               /* bInterfaceClass */                                               \
+        bInterfaceSubClass,            /* bInterfaceSubClass */                                            \
+        bInterfaceProtocol,            /* bInterfaceProtocol */                                            \
+        iInterface                     /* iInterface */
+
+#define USB_ENDPOINT_DESCRIPTOR_INIT(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \
+    0x07,                             /* bLength */                                             \
+        USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */                                     \
+        bEndpointAddress,             /* bEndpointAddress */                                    \
+        bmAttributes,                 /* bmAttributes */                                        \
+        WBVAL(wMaxPacketSize),        /* wMaxPacketSize */                                      \
+        bInterval                     /* bInterval */
+
+#define USB_IAD_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \
+    0x08,                                          /* bLength */                                             \
+        USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */                                     \
+        bFirstInterface,                           /* bFirstInterface */                                     \
+        bInterfaceCount,                           /* bInterfaceCount */                                     \
+        bFunctionClass,                            /* bFunctionClass */                                      \
+        bFunctionSubClass,                         /* bFunctionSubClass */                                   \
+        bFunctionProtocol,                         /* bFunctionProtocol */                                   \
+        0x00                                       /* iFunction */
+
+#define USB_LANGID_INIT(id)                               \
+    0x04,                           /* bLength */         \
+        USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \
+        WBVAL(id)                   /* wLangID0 */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_slist.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_slist.h
new file mode 100644
index 0000000000000000000000000000000000000000..2c29347c79214d73a71eb231ea6f4ff70e93a40c
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_slist.h
@@ -0,0 +1,224 @@
+#ifndef __USB_SLIST_H__
+#define __USB_SLIST_H__
+
+#include "string.h"
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * usb_container_of - return the member address of ptr, if the type of ptr is the
+ * struct type.
+ */
+#define usb_container_of(ptr, type, member) \
+    ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
+
+/**
+ * Single List structure
+ */
+struct usb_slist_node {
+    struct usb_slist_node *next; /**< point to next node. */
+};
+typedef struct usb_slist_node usb_slist_t; /**< Type for single list. */
+
+/**
+ * @brief initialize a single list
+ *
+ * @param l the single list to be initialized
+ */
+static inline void usb_slist_init(usb_slist_t *l)
+{
+    l->next = NULL;
+}
+
+static inline void usb_slist_add_head(usb_slist_t *l, usb_slist_t *n)
+{
+    n->next = l->next;
+    l->next = n;
+}
+
+static inline void usb_slist_add_tail(usb_slist_t *l, usb_slist_t *n)
+{
+    while (l->next) {
+        l = l->next;
+    }
+
+    /* append the node to the tail */
+    l->next = n;
+    n->next = NULL;
+}
+
+static inline void usb_slist_insert(usb_slist_t *l, usb_slist_t *next, usb_slist_t *n)
+{
+    if (!next) {
+        usb_slist_add_tail(next, l);
+        return;
+    }
+
+    while (l->next) {
+        if (l->next == next) {
+            l->next = n;
+            n->next = next;
+        }
+
+        l = l->next;
+    }
+}
+
+static inline usb_slist_t *usb_slist_remove(usb_slist_t *l, usb_slist_t *n)
+{
+    /* remove slist head */
+    while (l->next && l->next != n) {
+        l = l->next;
+    }
+
+    /* remove node */
+    if (l->next != (usb_slist_t *)0) {
+        l->next = l->next->next;
+    }
+
+    return l;
+}
+
+static inline unsigned int usb_slist_len(const usb_slist_t *l)
+{
+    unsigned int len = 0;
+    const usb_slist_t *list = l->next;
+
+    while (list != NULL) {
+        list = list->next;
+        len++;
+    }
+
+    return len;
+}
+
+static inline unsigned int usb_slist_contains(usb_slist_t *l, usb_slist_t *n)
+{
+    while (l->next) {
+        if (l->next == n) {
+            return 0;
+        }
+
+        l = l->next;
+    }
+
+    return 1;
+}
+
+static inline usb_slist_t *usb_slist_head(usb_slist_t *l)
+{
+    return l->next;
+}
+
+static inline usb_slist_t *usb_slist_tail(usb_slist_t *l)
+{
+    while (l->next) {
+        l = l->next;
+    }
+
+    return l;
+}
+
+static inline usb_slist_t *usb_slist_next(usb_slist_t *n)
+{
+    return n->next;
+}
+
+static inline int usb_slist_isempty(usb_slist_t *l)
+{
+    return l->next == NULL;
+}
+
+/**
+ * @brief initialize a slist object
+ */
+#define USB_SLIST_OBJECT_INIT(object) \
+    {                                 \
+        NULL                          \
+    }
+
+/**
+ * @brief initialize a slist object
+ */
+#define USB_SLIST_DEFINE(slist) \
+    usb_slist_t slist = { NULL }
+
+/**
+ * @brief get the struct for this single list node
+ * @param node the entry point
+ * @param type the type of structure
+ * @param member the name of list in structure
+ */
+#define usb_slist_entry(node, type, member) \
+    usb_container_of(node, type, member)
+
+/**
+ * usb_slist_first_entry - get the first element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define usb_slist_first_entry(ptr, type, member) \
+    usb_slist_entry((ptr)->next, type, member)
+
+/**
+ * usb_slist_tail_entry - get the tail element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define usb_slist_tail_entry(ptr, type, member) \
+    usb_slist_entry(usb_slist_tail(ptr), type, member)
+
+/**
+ * usb_slist_first_entry_or_null - get the first element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define usb_slist_first_entry_or_null(ptr, type, member) \
+    (usb_slist_isempty(ptr) ? NULL : usb_slist_first_entry(ptr, type, member))
+
+/**
+ * usb_slist_for_each - iterate over a single list
+ * @pos:    the usb_slist_t * to use as a loop cursor.
+ * @head:   the head for your single list.
+ */
+#define usb_slist_for_each(pos, head) \
+    for (pos = (head)->next; pos != NULL; pos = pos->next)
+
+#define usb_slist_for_each_safe(pos, next, head)    \
+    for (pos = (head)->next, next = pos->next; pos; \
+         pos = next, next = pos->next)
+
+/**
+ * usb_slist_for_each_entry  -   iterate over single list of given type
+ * @pos:    the type * to use as a loop cursor.
+ * @head:   the head for your single list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define usb_slist_for_each_entry(pos, head, member)                 \
+    for (pos = usb_slist_entry((head)->next, typeof(*pos), member); \
+         &pos->member != (NULL);                                    \
+         pos = usb_slist_entry(pos->member.next, typeof(*pos), member))
+
+#define usb_slist_for_each_entry_safe(pos, n, head, member)          \
+    for (pos = usb_slist_entry((head)->next, typeof(*pos), member),  \
+        n = usb_slist_entry(pos->member.next, typeof(*pos), member); \
+         &pos->member != (NULL);                                     \
+         pos = n, n = usb_slist_entry(pos->member.next, typeof(*pos), member))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_util.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_util.h
new file mode 100644
index 0000000000000000000000000000000000000000..f8d214600ac0fb870f4ae7d74348d5c45323a90b
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/common/usb_util.h
@@ -0,0 +1,140 @@
+#ifndef _USB_UTIL_H
+#define _USB_UTIL_H
+
+#include "stdbool.h"
+#include "string.h"
+#include "stdint.h"
+#include "stdio.h"
+#include "usb_slist.h"
+
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif
+#ifndef __aligned
+#define __aligned(x) __attribute__((__aligned__(x)))
+#endif
+#define __may_alias __attribute__((__may_alias__))
+#ifndef __printf_like
+#define __printf_like(f, a) __attribute__((format(printf, f, a)))
+#endif
+#define __used __attribute__((__used__))
+#ifndef __deprecated
+#define __deprecated __attribute__((deprecated))
+#endif
+#define ARG_UNUSED(x) (void)(x)
+
+// #define likely(x)   __builtin_expect((bool)!!(x), true)
+// #define unlikely(x) __builtin_expect((bool)!!(x), false)
+
+#define popcount(x) __builtin_popcount(x)
+
+#ifndef __no_optimization
+#define __no_optimization __attribute__((optimize("-O0")))
+#endif
+
+#ifndef __weak
+#define __weak __attribute__((__weak__))
+#endif
+#define __unused __attribute__((__unused__))
+
+#define __ALIGN_END __attribute__((aligned(4)))
+#define __ALIGN_BEGIN
+
+#ifndef LO_BYTE
+#define LO_BYTE(x) ((uint8_t)(x & 0x00FF))
+#endif
+
+#ifndef HI_BYTE
+#define HI_BYTE(x) ((uint8_t)((x & 0xFF00) >> 8))
+#endif
+
+/**
+ * @def MAX
+ * @brief The larger value between @p a and @p b.
+ * @note Arguments are evaluated twice.
+ */
+#ifndef MAX
+/* Use Z_MAX for a GCC-only, single evaluation version */
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+/**
+ * @def MIN
+ * @brief The smaller value between @p a and @p b.
+ * @note Arguments are evaluated twice.
+ */
+#ifndef MIN
+/* Use Z_MIN for a GCC-only, single evaluation version */
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef BCD
+#define BCD(x) ((((x) / 10) << 4) | ((x) % 10))
+#endif
+
+#ifdef BIT
+#undef BIT
+#define BIT(n) (1UL << (n))
+#else
+#define BIT(n) (1UL << (n))
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(array) \
+    ((int)((sizeof(array) / sizeof((array)[0]))))
+#endif
+
+#define USB_DESC_SECTION __attribute__((section("usb_desc"))) __used __aligned(1)
+
+#define BSWAP16(u16) (__builtin_bswap16(u16))
+#define BSWAP32(u32) (__builtin_bswap32(u32))
+
+#define GET_BE16(field) \
+    (((uint16_t)(field)[0] << 8) | ((uint16_t)(field)[1]))
+
+#define GET_BE32(field) \
+    (((uint32_t)(field)[0] << 24) | ((uint32_t)(field)[1] << 16) | ((uint32_t)(field)[2] << 8) | ((uint32_t)(field)[3] << 0))
+
+#define SET_BE16(field, value)                \
+    do {                                      \
+        (field)[0] = (uint8_t)((value) >> 8); \
+        (field)[1] = (uint8_t)((value) >> 0); \
+    } while (0)
+
+#define SET_BE24(field, value)                 \
+    do {                                       \
+        (field)[0] = (uint8_t)((value) >> 16); \
+        (field)[1] = (uint8_t)((value) >> 8);  \
+        (field)[2] = (uint8_t)((value) >> 0);  \
+    } while (0)
+
+#define SET_BE32(field, value)                 \
+    do {                                       \
+        (field)[0] = (uint8_t)((value) >> 24); \
+        (field)[1] = (uint8_t)((value) >> 16); \
+        (field)[2] = (uint8_t)((value) >> 8);  \
+        (field)[3] = (uint8_t)((value) >> 0);  \
+    } while (0)
+
+#define REQTYPE_GET_DIR(x)   (((x) >> 7) & 0x01)
+#define REQTYPE_GET_TYPE(x)  (((x) >> 5) & 0x03U)
+#define REQTYPE_GET_RECIP(x) ((x)&0x1F)
+
+#define GET_DESC_TYPE(x)  (((x) >> 8) & 0xFFU)
+#define GET_DESC_INDEX(x) ((x)&0xFFU)
+
+#define WBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF)
+#define DBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF), ((x >> 16) & 0xFF), ((x >> 24) & 0xFF)
+
+#if 0
+#define USBD_LOG_WRN(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#define USBD_LOG_DBG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#define USBD_LOG_ERR(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#else
+#define USBD_LOG_WRN(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#define USBD_LOG_DBG(a, ...)
+#define USBD_LOG_ERR(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#define USBD_LOG(a, ...)     bflb_platform_printf(a, ##__VA_ARGS__)
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/core/usbd_core.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/core/usbd_core.c
new file mode 100644
index 0000000000000000000000000000000000000000..c5a978d039e1d3732d17a71d43cf67b0ace537c7
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/core/usbd_core.c
@@ -0,0 +1,1239 @@
+/**
+ * @file usbd_core.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+
+#define USBD_EP_CALLBACK_LIST_SEARCH   0
+#define USBD_EP_CALLBACK_ARR_SEARCH    1
+#define USBD_EP_CALLBACK_SEARCH_METHOD USBD_EP_CALLBACK_ARR_SEARCH
+
+/* general descriptor field offsets */
+#define DESC_bLength         0 /** Length offset */
+#define DESC_bDescriptorType 1 /** Descriptor type offset */
+
+/* config descriptor field offsets */
+#define CONF_DESC_wTotalLength        2 /** Total length offset */
+#define CONF_DESC_bConfigurationValue 5 /** Configuration value offset */
+#define CONF_DESC_bmAttributes        7 /** configuration characteristics */
+
+/* interface descriptor field offsets */
+#define INTF_DESC_bInterfaceNumber  2 /** Interface number offset */
+#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */
+
+#define USB_REQUEST_BUFFER_SIZE 256
+#define USB_EP_OUT_NUM          8
+#define USB_EP_IN_NUM           8
+
+static struct usbd_core_cfg_priv {
+    /** Setup packet */
+    struct usb_setup_packet setup;
+    /** Pointer to data buffer */
+    uint8_t *ep0_data_buf;
+    /** Remaining bytes in buffer */
+    uint32_t ep0_data_buf_residue;
+    /** Total length of control transfer */
+    uint32_t ep0_data_buf_len;
+    /** Zero length packet flag of control transfer */
+    bool zlp_flag;
+    /** Pointer to registered descriptors */
+    const uint8_t *descriptors;
+    /* Buffer used for storing standard, class and vendor request data */
+    uint8_t req_data[USB_REQUEST_BUFFER_SIZE];
+
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 1
+    usbd_endpoint_callback in_ep_cb[USB_EP_IN_NUM];
+    usbd_endpoint_callback out_ep_cb[USB_EP_OUT_NUM];
+#endif
+    /** Variable to check whether the usb has been enabled */
+    bool enabled;
+    /** Variable to check whether the usb has been configured */
+    bool configured;
+    /** Currently selected configuration */
+    uint8_t configuration;
+    /** Remote wakeup feature status */
+    uint16_t remote_wakeup;
+    uint8_t reserved;
+} usbd_core_cfg;
+
+static usb_slist_t usbd_class_head = USB_SLIST_OBJECT_INIT(usbd_class_head);
+static struct usb_msosv1_descriptor *msosv1_desc;
+static struct usb_bos_descriptor *bos_desc;
+
+/**
+ * @brief print the contents of a setup packet
+ *
+ * @param [in] setup The setup packet
+ *
+ */
+static void usbd_print_setup(struct usb_setup_packet *setup)
+{
+    USBD_LOG_ERR("Setup: "
+                 "bmRequestType 0x%02x, bRequest 0x%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\r\n",
+                 setup->bmRequestType,
+                 setup->bRequest,
+                 setup->wValue,
+                 setup->wIndex,
+                 setup->wLength);
+}
+
+/**
+ * @brief Check if the device is in Configured state
+ *
+ * @return true if Configured, false otherwise.
+ */
+static bool is_device_configured(void)
+{
+    return (usbd_core_cfg.configuration != 0);
+}
+/**
+ * @brief Check if the interface of given number is valid
+ *
+ * @param [in] interface Number of the addressed interface
+ *
+ * This function searches through descriptor and checks
+ * is the Host has addressed valid interface.
+ *
+ * @return true if interface exists - valid
+ */
+static bool is_interface_valid(uint8_t interface)
+{
+    const uint8_t *p = (uint8_t *)usbd_core_cfg.descriptors;
+    const struct usb_configuration_descriptor *cfg_descr;
+
+    /* Search through descriptor for matching interface */
+    while (p[DESC_bLength] != 0U) {
+        if (p[DESC_bDescriptorType] == USB_DESCRIPTOR_TYPE_CONFIGURATION) {
+            cfg_descr = (const struct usb_configuration_descriptor *)p;
+
+            if (interface < cfg_descr->bNumInterfaces) {
+                return true;
+            }
+        }
+
+        p += p[DESC_bLength];
+    }
+
+    return false;
+}
+/**
+ * @brief Check if the endpoint of given address is valid
+ *
+ * @param [in] ep Address of the Endpoint
+ *
+ * This function checks if the Endpoint of given address
+ * is valid for the configured device. Valid Endpoint is
+ * either Control Endpoint or one used by the device.
+ *
+ * @return true if endpoint exists - valid
+ */
+static bool is_ep_valid(uint8_t ep)
+{
+    /* Check if its Endpoint 0 */
+    if ((ep & 0x7f) == 0) {
+        return true;
+    }
+
+    return true;
+}
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 1
+static void usbd_ep_callback_register(void)
+{
+    usb_slist_t *i, *j, *k;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            usb_slist_for_each(k, &intf->ep_list)
+            {
+                usbd_endpoint_t *ept = usb_slist_entry(k, struct usbd_endpoint, list);
+
+                if (ept->ep_cb) {
+                    if (ept->ep_addr & 0x80) {
+                        usbd_core_cfg.in_ep_cb[ept->ep_addr & 0x7f] = ept->ep_cb;
+                    } else {
+                        usbd_core_cfg.out_ep_cb[ept->ep_addr & 0x7f] = ept->ep_cb;
+                    }
+                }
+            }
+        }
+    }
+}
+#endif
+/**
+ * @brief configure and enable endpoint
+ *
+ * This function sets endpoint configuration according to one specified in USB
+ * endpoint descriptor and then enables it for data transfers.
+ *
+ * @param [in]  ep_desc Endpoint descriptor byte array
+ *
+ * @return true if successfully configured and enabled
+ */
+static bool usbd_set_endpoint(const struct usb_endpoint_descriptor *ep_desc)
+{
+    struct usbd_endpoint_cfg ep_cfg;
+
+    ep_cfg.ep_addr = ep_desc->bEndpointAddress;
+    ep_cfg.ep_mps = ep_desc->wMaxPacketSize;
+    ep_cfg.ep_type = ep_desc->bmAttributes & USBD_EP_TYPE_MASK;
+
+    USBD_LOG("Open endpoint:0x%x type:%u mps:%u\r\n",
+             ep_cfg.ep_addr, ep_cfg.ep_type, ep_cfg.ep_mps);
+
+    usbd_ep_open(&ep_cfg);
+    usbd_core_cfg.configured = true;
+
+    return true;
+}
+/**
+ * @brief Disable endpoint for transferring data
+ *
+ * This function cancels transfers that are associated with endpoint and
+ * disabled endpoint itself.
+ *
+ * @param [in]  ep_desc Endpoint descriptor byte array
+ *
+ * @return true if successfully deconfigured and disabled
+ */
+static bool usbd_reset_endpoint(const struct usb_endpoint_descriptor *ep_desc)
+{
+    struct usbd_endpoint_cfg ep_cfg;
+
+    ep_cfg.ep_addr = ep_desc->bEndpointAddress;
+    ep_cfg.ep_mps = ep_desc->wMaxPacketSize;
+    ep_cfg.ep_type = ep_desc->bmAttributes & USBD_EP_TYPE_MASK;
+
+    USBD_LOG("Close endpoint:0x%x type:%u\r\n",
+             ep_cfg.ep_addr, ep_cfg.ep_type);
+
+    usbd_ep_close(ep_cfg.ep_addr);
+
+    return true;
+}
+
+/**
+ * @brief get specified USB descriptor
+ *
+ * This function parses the list of installed USB descriptors and attempts
+ * to find the specified USB descriptor.
+ *
+ * @param [in]  type_index Type and index of the descriptor
+ * @param [in]  lang_id    Language ID of the descriptor (currently unused)
+ * @param [out] len        Descriptor length
+ * @param [out] data       Descriptor data
+ *
+ * @return true if the descriptor was found, false otherwise
+ */
+static bool usbd_get_descriptor(uint16_t type_index, uint8_t **data, uint32_t *len)
+{
+    uint8_t type = 0U;
+    uint8_t index = 0U;
+    uint8_t *p = NULL;
+    uint32_t cur_index = 0U;
+    bool found = false;
+
+    type = GET_DESC_TYPE(type_index);
+    index = GET_DESC_INDEX(type_index);
+
+    if ((type == USB_DESCRIPTOR_TYPE_STRING) && (index == USB_OSDESC_STRING_DESC_INDEX)) {
+        USBD_LOG("MS OS Descriptor string read\r\n");
+
+        if (!msosv1_desc) {
+            return false;
+        }
+
+        *data = (uint8_t *)msosv1_desc->string;
+        *len = sizeof(struct usb_msosv1_string_descriptor);
+
+        return true;
+    } else if (type == USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE) {
+        USBD_LOG("BOS descriptor string read\r\n");
+
+        if (!bos_desc) {
+            return false;
+        }
+
+        *data = bos_desc->bos_id;
+        *len = bos_desc->bos_id_len;
+        return true;
+    }
+    /*
+     * Invalid types of descriptors,
+     * see USB Spec. Revision 2.0, 9.4.3 Get Descriptor
+     */
+    else if ((type == USB_DESCRIPTOR_TYPE_INTERFACE) || (type == USB_DESCRIPTOR_TYPE_ENDPOINT) ||
+             (type > USB_DESCRIPTOR_TYPE_OTHER_SPEED)) {
+        return false;
+    }
+
+    p = (uint8_t *)usbd_core_cfg.descriptors;
+
+    cur_index = 0U;
+
+    while (p[DESC_bLength] != 0U) {
+        if (p[DESC_bDescriptorType] == type) {
+            if (cur_index == index) {
+                found = true;
+                break;
+            }
+
+            cur_index++;
+        }
+
+        /* skip to next descriptor */
+        p += p[DESC_bLength];
+    }
+
+    if (found) {
+        /* set data pointer */
+        *data = p;
+
+        /* get length from structure */
+        if (type == USB_DESCRIPTOR_TYPE_CONFIGURATION) {
+            /* configuration descriptor is an
+             * exception, length is at offset
+             * 2 and 3
+             */
+            *len = (p[CONF_DESC_wTotalLength]) |
+                   (p[CONF_DESC_wTotalLength + 1] << 8);
+        } else {
+            /* normally length is at offset 0 */
+            *len = p[DESC_bLength];
+        }
+    } else {
+        /* nothing found */
+        USBD_LOG_ERR("descriptor  not found!\r\n", type, index);
+    }
+
+    return found;
+}
+
+/**
+ * @brief set USB configuration
+ *
+ * This function configures the device according to the specified configuration
+ * index and alternate setting by parsing the installed USB descriptor list.
+ * A configuration index of 0 unconfigures the device.
+ *
+ * @param [in] config_index Configuration index
+ * @param [in] alt_setting  Alternate setting number
+ *
+ * @return true if successfully configured false if error or unconfigured
+ */
+static bool usbd_set_configuration(uint8_t config_index, uint8_t alt_setting)
+{
+    uint8_t *p = (uint8_t *)usbd_core_cfg.descriptors;
+    uint8_t cur_alt_setting = 0xFF;
+    uint8_t cur_config = 0xFF;
+    bool found = false;
+
+    if (config_index == 0U) {
+        /* TODO: unconfigure device */
+        USBD_LOG_ERR("Device not configured - invalid configuration\r\n");
+        return true;
+    }
+
+    /* configure endpoints for this configuration/altsetting */
+    while (p[DESC_bLength] != 0U) {
+        switch (p[DESC_bDescriptorType]) {
+            case USB_DESCRIPTOR_TYPE_CONFIGURATION:
+                /* remember current configuration index */
+                cur_config = p[CONF_DESC_bConfigurationValue];
+
+                if (cur_config == config_index) {
+                    found = true;
+                }
+
+                break;
+
+            case USB_DESCRIPTOR_TYPE_INTERFACE:
+                /* remember current alternate setting */
+                cur_alt_setting =
+                    p[INTF_DESC_bAlternateSetting];
+                break;
+
+            case USB_DESCRIPTOR_TYPE_ENDPOINT:
+                if ((cur_config != config_index) ||
+                    (cur_alt_setting != alt_setting)) {
+                    break;
+                }
+
+                found = usbd_set_endpoint((struct usb_endpoint_descriptor *)p);
+                break;
+
+            default:
+                break;
+        }
+
+        /* skip to next descriptor */
+        p += p[DESC_bLength];
+    }
+
+    return found;
+}
+
+/**
+ * @brief set USB interface
+ *
+ * @param [in] iface Interface index
+ * @param [in] alt_setting  Alternate setting number
+ *
+ * @return true if successfully configured false if error or unconfigured
+ */
+static bool usbd_set_interface(uint8_t iface, uint8_t alt_setting)
+{
+    const uint8_t *p = usbd_core_cfg.descriptors;
+    const uint8_t *if_desc = NULL;
+    struct usb_endpoint_descriptor *ep_desc;
+    uint8_t cur_alt_setting = 0xFF;
+    uint8_t cur_iface = 0xFF;
+    bool ret = false;
+
+    USBD_LOG_DBG("iface %u alt_setting %u\r\n", iface, alt_setting);
+
+    while (p[DESC_bLength] != 0U) {
+        switch (p[DESC_bDescriptorType]) {
+            case USB_DESCRIPTOR_TYPE_INTERFACE:
+                /* remember current alternate setting */
+                cur_alt_setting = p[INTF_DESC_bAlternateSetting];
+                cur_iface = p[INTF_DESC_bInterfaceNumber];
+
+                if (cur_iface == iface &&
+                    cur_alt_setting == alt_setting) {
+                    if_desc = (void *)p;
+                }
+
+                USBD_LOG_DBG("Current iface %u alt setting %u",
+                             cur_iface, cur_alt_setting);
+                break;
+
+            case USB_DESCRIPTOR_TYPE_ENDPOINT:
+                if (cur_iface == iface) {
+                    ep_desc = (struct usb_endpoint_descriptor *)p;
+
+                    if (cur_alt_setting != alt_setting) {
+                        ret = usbd_reset_endpoint(ep_desc);
+                    } else {
+                        ret = usbd_set_endpoint(ep_desc);
+                    }
+                }
+
+                break;
+
+            default:
+                break;
+        }
+
+        /* skip to next descriptor */
+        p += p[DESC_bLength];
+    }
+
+    usbd_event_notify_handler(USB_EVENT_SET_INTERFACE, (void *)if_desc);
+
+    return ret;
+}
+
+/**
+ * @brief handle a standard device request
+ *
+ * @param [in]     setup    The setup packet
+ * @param [in,out] len      Pointer to data length
+ * @param [in,out] ep0_data_buf Data buffer
+ *
+ * @return true if the request was handled successfully
+ */
+static bool usbd_std_device_req_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    uint16_t value = setup->wValue;
+    // uint16_t index = setup->wIndex;
+    bool ret = true;
+
+    switch (setup->bRequest) {
+        case USB_REQUEST_GET_STATUS:
+            USBD_LOG_DBG("REQ_GET_STATUS\r\n");
+            /* bit 0: self-powered */
+            /* bit 1: remote wakeup */
+            *data = (uint8_t *)&usbd_core_cfg.remote_wakeup;
+
+            *len = 2;
+            break;
+
+        case USB_REQUEST_CLEAR_FEATURE:
+            USBD_LOG_DBG("REQ_CLEAR_FEATURE\r\n");
+            ret = false;
+
+            if (value == USB_FEATURE_REMOTE_WAKEUP) {
+                usbd_core_cfg.remote_wakeup = 0;
+                usbd_event_notify_handler(USB_EVENT_CLEAR_REMOTE_WAKEUP, NULL);
+                ret = true;
+            }
+
+            break;
+
+        case USB_REQUEST_SET_FEATURE:
+            USBD_LOG_DBG("REQ_SET_FEATURE\r\n");
+            ret = false;
+
+            if (value == USB_FEATURE_REMOTE_WAKEUP) {
+                usbd_core_cfg.remote_wakeup = 1;
+                usbd_event_notify_handler(USB_EVENT_SET_REMOTE_WAKEUP, NULL);
+                ret = true;
+            }
+
+            if (value == USB_FEATURE_TEST_MODE) {
+                /* put TEST_MODE code here */
+            }
+
+            break;
+
+        case USB_REQUEST_SET_ADDRESS:
+            USBD_LOG_DBG("REQ_SET_ADDRESS, addr 0x%x\r\n", value);
+            usbd_set_address(value);
+            break;
+
+        case USB_REQUEST_GET_DESCRIPTOR:
+            USBD_LOG_DBG("REQ_GET_DESCRIPTOR\r\n");
+            ret = usbd_get_descriptor(value, data, len);
+            break;
+
+        case USB_REQUEST_SET_DESCRIPTOR:
+            USBD_LOG_DBG("Device req 0x%02x not implemented\r\n", setup->bRequest);
+            ret = false;
+            break;
+
+        case USB_REQUEST_GET_CONFIGURATION:
+            USBD_LOG_DBG("REQ_GET_CONFIGURATION\r\n");
+            /* indicate if we are configured */
+            *data = (uint8_t *)&usbd_core_cfg.configuration;
+            *len = 1;
+            break;
+
+        case USB_REQUEST_SET_CONFIGURATION:
+            value &= 0xFF;
+            USBD_LOG_DBG("REQ_SET_CONFIGURATION, conf 0x%x\r\n", value);
+
+            if (!usbd_set_configuration(value, 0)) {
+                USBD_LOG_DBG("USB Set Configuration failed\r\n");
+                ret = false;
+            } else {
+                /* configuration successful,
+                 * update current configuration
+                 */
+                usbd_core_cfg.configuration = value;
+                usbd_event_notify_handler(USB_EVENT_CONFIGURED, NULL);
+            }
+
+            break;
+
+        case USB_REQUEST_GET_INTERFACE:
+            break;
+
+        case USB_REQUEST_SET_INTERFACE:
+            break;
+
+        default:
+            USBD_LOG_ERR("Illegal device req 0x%02x\r\n", setup->bRequest);
+            ret = false;
+            break;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief handle a standard interface request
+ *
+ * @param [in]     setup    The setup packet
+ * @param [in,out] len      Pointer to data length
+ * @param [in]     ep0_data_buf Data buffer
+ *
+ * @return true if the request was handled successfully
+ */
+static bool usbd_std_interface_req_handler(struct usb_setup_packet *setup,
+                                           uint8_t **data, uint32_t *len)
+{
+    /** The device must be configured to accept standard interface
+     * requests and the addressed Interface must be valid.
+     */
+    if (!is_device_configured() ||
+        (!is_interface_valid((uint8_t)setup->wIndex))) {
+        return false;
+    }
+
+    switch (setup->bRequest) {
+        case USB_REQUEST_GET_STATUS:
+            /* no bits specified */
+            *data = (uint8_t *)&usbd_core_cfg.remote_wakeup;
+
+            *len = 2;
+            break;
+
+        case USB_REQUEST_CLEAR_FEATURE:
+        case USB_REQUEST_SET_FEATURE:
+            /* not defined for interface */
+            return false;
+
+        case USB_REQUEST_GET_INTERFACE:
+            /** This handler is called for classes that does not support
+             * alternate Interfaces so always return 0. Classes that
+             * support alternative interfaces handles GET_INTERFACE
+             * in custom_handler.
+             */
+            *data = (uint8_t *)&usbd_core_cfg.reserved;
+
+            *len = 1;
+            break;
+
+        case USB_REQUEST_SET_INTERFACE:
+            USBD_LOG_DBG("REQ_SET_INTERFACE\r\n");
+            usbd_set_interface(setup->wIndex, setup->wValue);
+            break;
+
+        default:
+            USBD_LOG_ERR("Illegal interface req 0x%02x\r\n", setup->bRequest);
+            return false;
+    }
+
+    return true;
+}
+
+/**
+ * @brief handle a standard endpoint request
+ *
+ * @param [in]     setup    The setup packet
+ * @param [in,out] len      Pointer to data length
+ * @param [in]     ep0_data_buf Data buffer
+ *
+ * @return true if the request was handled successfully
+ */
+static bool usbd_std_endpoint_req_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    uint8_t ep = (uint8_t)setup->wIndex;
+
+    /* Check if request addresses valid Endpoint */
+    if (!is_ep_valid(ep)) {
+        return false;
+    }
+
+    switch (setup->bRequest) {
+        case USB_REQUEST_GET_STATUS:
+
+            /** This request is valid for Control Endpoints when
+             * the device is not yet configured. For other
+             * Endpoints the device must be configured.
+             * Firstly check if addressed ep is Control Endpoint.
+             * If no then the device must be in Configured state
+             * to accept the request.
+             */
+            if (((ep & 0x7f) == 0) || is_device_configured()) {
+                /* bit 0 - Endpoint halted or not */
+                usbd_ep_is_stalled(ep, (uint8_t *)&usbd_core_cfg.remote_wakeup);
+                *data = (uint8_t *)&usbd_core_cfg.remote_wakeup;
+
+                *len = 2;
+                break;
+            }
+
+            return false;
+
+        case USB_REQUEST_CLEAR_FEATURE:
+            if (setup->wValue == USB_FEATURE_ENDPOINT_STALL) {
+                /** This request is valid for Control Endpoints when
+                 * the device is not yet configured. For other
+                 * Endpoints the device must be configured.
+                 * Firstly check if addressed ep is Control Endpoint.
+                 * If no then the device must be in Configured state
+                 * to accept the request.
+                 */
+                if (((ep & 0x7f) == 0) || is_device_configured()) {
+                    USBD_LOG_ERR("ep:%x clear halt\r\n", ep);
+                    usbd_ep_clear_stall(ep);
+                    usbd_event_notify_handler(USB_EVENT_CLEAR_HALT, NULL);
+                    break;
+                }
+            }
+
+            /* only ENDPOINT_HALT defined for endpoints */
+            return false;
+
+        case USB_REQUEST_SET_FEATURE:
+            if (setup->wValue == USB_FEATURE_ENDPOINT_STALL) {
+                /** This request is valid for Control Endpoints when
+                 * the device is not yet configured. For other
+                 * Endpoints the device must be configured.
+                 * Firstly check if addressed ep is Control Endpoint.
+                 * If no then the device must be in Configured state
+                 * to accept the request.
+                 */
+                if (((ep & 0x7f) == 0) || is_device_configured()) {
+                    /* set HALT by stalling */
+                    USBD_LOG_ERR("ep:%x set halt\r\n", ep);
+                    usbd_ep_set_stall(ep);
+                    usbd_event_notify_handler(USB_EVENT_SET_HALT, NULL);
+                    break;
+                }
+            }
+
+            /* only ENDPOINT_HALT defined for endpoints */
+            return false;
+
+        case USB_REQUEST_SYNCH_FRAME:
+
+            /* For Synch Frame request the device must be configured */
+            if (is_device_configured()) {
+                /* Not supported, return false anyway */
+                USBD_LOG_DBG("ep req 0x%02x not implemented\r\n", setup->bRequest);
+            }
+
+            return false;
+
+        default:
+            USBD_LOG_ERR("Illegal ep req 0x%02x\r\n", setup->bRequest);
+            return false;
+    }
+
+    return true;
+}
+
+/**
+ * @brief default handler for standard ('chapter 9') requests
+ *
+ * If a custom request handler was installed, this handler is called first.
+ *
+ * @param [in]     setup    The setup packet
+ * @param [in]     ep0_data_buf Data buffer
+ * @param [in,out] len      Pointer to data length
+ *
+ * @return true if the request was handled successfully
+ */
+static int usbd_standard_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    int rc = 0;
+
+    switch (setup->bmRequestType_b.Recipient) {
+        case USB_REQUEST_TO_DEVICE:
+            if (usbd_std_device_req_handler(setup, data, len) == false) {
+                rc = -1;
+            }
+
+            break;
+
+        case USB_REQUEST_TO_INTERFACE:
+            if (usbd_std_interface_req_handler(setup, data, len) == false) {
+                rc = -1;
+            }
+
+            break;
+
+        case USB_REQUEST_TO_ENDPOINT:
+            if (usbd_std_endpoint_req_handler(setup, data, len) == false) {
+                rc = -1;
+            }
+
+            break;
+
+        default:
+            rc = -1;
+    }
+
+    return rc;
+}
+
+/*
+ * The functions usbd_class_request_handler(), usbd_custom_request_handler() and usbd_vendor_request_handler()
+ * go through the interfaces one after the other and compare the
+ * bInterfaceNumber with the wIndex and and then call the appropriate
+ * callback of the USB function.
+ * Note, a USB function can have more than one interface and the
+ * request does not have to be directed to the first interface (unlikely).
+ * These functions can be simplified and moved to usb_handle_request()
+ * when legacy initialization throgh the usb_set_config() and
+ * usb_enable() is no longer needed.
+ */
+static int usbd_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("bRequest 0x%02x, wIndex 0x%04x", setup->bRequest, setup->wIndex);
+
+    if (setup->bmRequestType_b.Recipient != USB_REQUEST_TO_INTERFACE) {
+        return -1;
+    }
+
+    usb_slist_t *i, *j;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            if (intf->class_handler && (intf->intf_num == (setup->wIndex & 0xFF))) {
+                return intf->class_handler(setup, data, len);
+            }
+        }
+    }
+    return -1;
+}
+
+static int usbd_vendor_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("bRequest 0x%02x, wValue0x%04x, wIndex 0x%04x", setup->bRequest, setup->wValue, setup->wIndex);
+
+    // if(setup->bmRequestType_b.Recipient != USB_REQUEST_TO_DEVICE)
+    // {
+    //     return -1;
+    // }
+
+    if (msosv1_desc) {
+        if (setup->bRequest == msosv1_desc->vendor_code) {
+            switch (setup->wIndex) {
+                case 0x04:
+                    USBD_LOG("Handle Compat ID\r\n");
+                    *data = (uint8_t *)msosv1_desc->compat_id;
+                    *len = msosv1_desc->compat_id_len;
+
+                    return 0;
+                case 0x05:
+                    USBD_LOG("Handle Compat properties\r\n");
+                    *data = (uint8_t *)msosv1_desc->comp_id_property;
+                    *len = msosv1_desc->comp_id_property_len;
+
+                    return 0;
+                default:
+                    break;
+            }
+        }
+    }
+
+    usb_slist_t *i, *j;
+
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            if (intf->vendor_handler && !intf->vendor_handler(setup, data, len)) {
+                return 0;
+            }
+        }
+    }
+
+    return -1;
+}
+
+static int usbd_custom_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("bRequest 0x%02x, wIndex 0x%04x", setup->bRequest, setup->wIndex);
+
+    if (setup->bmRequestType_b.Recipient != USB_REQUEST_TO_INTERFACE) {
+        return -1;
+    }
+
+    usb_slist_t *i, *j;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            if (intf->custom_handler && (intf->intf_num == (setup->wIndex & 0xFF))) {
+                return intf->custom_handler(setup, data, len);
+            }
+        }
+    }
+
+    return -1;
+}
+
+/**
+ * @brief handle a request by calling one of the installed request handlers
+ *
+ * Local function to handle a request by calling one of the installed request
+ * handlers. In case of data going from host to device, the data is at *ppbData.
+ * In case of data going from device to host, the handler can either choose to
+ * write its data at *ppbData or update the data pointer.
+ *
+ * @param [in]     setup The setup packet
+ * @param [in,out] data  Data buffer
+ * @param [in,out] len   Pointer to data length
+ *
+ * @return true if the request was handles successfully
+ */
+static bool usbd_setup_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    uint8_t type = setup->bmRequestType_b.Type;
+
+    if (type == USB_REQUEST_STANDARD) {
+        if (!usbd_custom_request_handler(setup, data, len)) {
+            return true;
+        }
+
+        if (usbd_standard_request_handler(setup, data, len) < 0) {
+            USBD_LOG_ERR("Handler Error %d\r\n", type);
+            usbd_print_setup(setup);
+            return false;
+        }
+    } else if (type == USB_REQUEST_CLASS) {
+        if (usbd_class_request_handler(setup, data, len) < 0) {
+            USBD_LOG_ERR("Handler Error %d\r\n", type);
+            usbd_print_setup(setup);
+            return false;
+        }
+    } else if (type == USB_REQUEST_VENDOR) {
+        if (usbd_vendor_request_handler(setup, data, len) < 0) {
+            USBD_LOG_ERR("Handler Error %d\r\n", type);
+            usbd_print_setup(setup);
+            return false;
+        }
+    } else {
+        return false;
+    }
+
+    return true;
+}
+/**
+ * @brief send data or status to host
+ *
+ * @return N/A
+ */
+static void usbd_send_to_host(uint16_t len)
+{
+    uint32_t chunk = 0U;
+
+    if (usbd_core_cfg.zlp_flag == false) {
+        chunk = usbd_core_cfg.ep0_data_buf_residue;
+
+        if (usbd_ep_write(USB_CONTROL_IN_EP0, usbd_core_cfg.ep0_data_buf, usbd_core_cfg.ep0_data_buf_residue, &chunk) < 0) {
+            USBD_LOG_ERR("USB write data failed\r\n");
+            return;
+        }
+
+        usbd_core_cfg.ep0_data_buf += chunk;
+        usbd_core_cfg.ep0_data_buf_residue -= chunk;
+
+        /*
+         * Set ZLP flag when host asks for a bigger length and the
+         * last chunk is wMaxPacketSize long, to indicate the last
+         * packet.
+         */
+        /* Send less data as requested during the Setup stage */
+        if ((!usbd_core_cfg.ep0_data_buf_residue) && !(usbd_core_cfg.ep0_data_buf_len % USB_CTRL_EP_MPS)) {
+            /* Transfers a zero-length packet */
+            // USBD_LOG("ZLP, requested %u , length %u ",
+            //  len, usb_dev.ep0_data_buf_len);
+            usbd_core_cfg.zlp_flag = true;
+        }
+    } else {
+        usbd_core_cfg.zlp_flag = false;
+        if (usbd_ep_write(USB_CONTROL_IN_EP0, NULL, 0, NULL) < 0) {
+            USBD_LOG_ERR("USB write zlp failed\r\n");
+            return;
+        }
+    }
+}
+
+static void usbd_ep0_setup_handler(void)
+{
+    struct usb_setup_packet *setup = &usbd_core_cfg.setup;
+
+    /*
+    * OUT transfer, Setup packet,
+    * reset request message state machine
+    */
+    if (usbd_ep_read(USB_CONTROL_OUT_EP0, (uint8_t *)setup,
+                     sizeof(struct usb_setup_packet), NULL) < 0) {
+        USBD_LOG_ERR("Read Setup Packet failed\r\n");
+        usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+        return;
+    }
+
+    //usbd_print_setup(setup);
+
+    if (setup->wLength > USB_REQUEST_BUFFER_SIZE) {
+        if (setup->bmRequestType_b.Dir != USB_REQUEST_DEVICE_TO_HOST) {
+            USBD_LOG_ERR("Request buffer too small\r\n");
+            usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+            return;
+        }
+    }
+
+    // usbd_core_cfg.ep0_data_buf = usbd_core_cfg.req_data;
+    usbd_core_cfg.ep0_data_buf_residue = setup->wLength;
+    usbd_core_cfg.ep0_data_buf_len = setup->wLength;
+    usbd_core_cfg.zlp_flag = false;
+
+    /* this maybe set code in class request code  */
+    if (setup->wLength &&
+        setup->bmRequestType_b.Dir == USB_REQUEST_HOST_TO_DEVICE) {
+        USBD_LOG_DBG("prepare to out data\r\n");
+        /*set ep ack to recv next data*/
+        usbd_ep_read(USB_CONTROL_OUT_EP0, NULL, 0, NULL);
+        return;
+    }
+
+    /* Ask installed handler to process request */
+    if (!usbd_setup_request_handler(setup, &usbd_core_cfg.ep0_data_buf, &usbd_core_cfg.ep0_data_buf_len)) {
+        USBD_LOG_ERR("usbd_setup_request_handler failed\r\n");
+        usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+        return;
+    }
+
+    /* Send smallest of requested and offered length */
+    usbd_core_cfg.ep0_data_buf_residue = MIN(usbd_core_cfg.ep0_data_buf_len,
+                                             setup->wLength);
+    /*Send data or status to host*/
+    usbd_send_to_host(setup->wLength);
+}
+
+static void usbd_ep0_out_handler(void)
+{
+    uint32_t chunk = 0U;
+    struct usb_setup_packet *setup = &usbd_core_cfg.setup;
+
+    /* OUT transfer, status packets */
+    if (usbd_core_cfg.ep0_data_buf_residue == 0) {
+        /* absorb zero-length status message */
+        USBD_LOG_DBG("recv status\r\n");
+
+        if (usbd_ep_read(USB_CONTROL_OUT_EP0,
+                         NULL,
+                         0, NULL) < 0) {
+            USBD_LOG_ERR("Read DATA Packet failed\r\n");
+            usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+        }
+
+        return;
+    }
+
+    usbd_core_cfg.ep0_data_buf = usbd_core_cfg.req_data;
+
+    /* OUT transfer, data packets */
+    if (usbd_ep_read(USB_CONTROL_OUT_EP0,
+                     usbd_core_cfg.ep0_data_buf,
+                     usbd_core_cfg.ep0_data_buf_residue, &chunk) < 0) {
+        USBD_LOG_ERR("Read DATA Packet failed\r\n");
+        usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+        return;
+    }
+
+    usbd_core_cfg.ep0_data_buf += chunk;
+    usbd_core_cfg.ep0_data_buf_residue -= chunk;
+
+    if (usbd_core_cfg.ep0_data_buf_residue == 0) {
+        /* Received all, send data to handler */
+        usbd_core_cfg.ep0_data_buf = usbd_core_cfg.req_data;
+
+        if (!usbd_setup_request_handler(setup, &usbd_core_cfg.ep0_data_buf, &usbd_core_cfg.ep0_data_buf_len)) {
+            USBD_LOG_ERR("usbd_setup_request_handler1 failed\r\n");
+            usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+            return;
+        }
+
+        /*Send status to host*/
+        usbd_send_to_host(setup->wLength);
+    } else {
+        USBD_LOG_ERR("ep0_data_buf_residue is not zero\r\n");
+    }
+}
+static void usbd_ep0_in_handler(void)
+{
+    struct usb_setup_packet *setup = &usbd_core_cfg.setup;
+
+    /* Send more data if available */
+    if (usbd_core_cfg.ep0_data_buf_residue != 0 || usbd_core_cfg.zlp_flag == true) {
+        usbd_send_to_host(setup->wLength);
+    }
+}
+
+static void usbd_ep_out_handler(uint8_t ep)
+{
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 0
+    usb_slist_t *i, *j, *k;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            usb_slist_for_each(k, &intf->ep_list)
+            {
+                usbd_endpoint_t *ept = usb_slist_entry(k, struct usbd_endpoint, list);
+
+                if ((ept->ep_addr == ep) && ept->ep_cb) {
+                    ept->ep_cb(ep);
+                }
+            }
+        }
+    }
+#else
+
+    if (usbd_core_cfg.out_ep_cb[ep & 0x7f]) {
+        usbd_core_cfg.out_ep_cb[ep & 0x7f](ep);
+    }
+
+#endif
+}
+
+static void usbd_ep_in_handler(uint8_t ep)
+{
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 0
+    usb_slist_t *i, *j, *k;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            usb_slist_for_each(k, &intf->ep_list)
+            {
+                usbd_endpoint_t *ept = usb_slist_entry(k, struct usbd_endpoint, list);
+
+                if ((ept->ep_addr == ep) && ept->ep_cb) {
+                    ept->ep_cb(ep);
+                }
+            }
+        }
+    }
+#else
+
+    if (usbd_core_cfg.in_ep_cb[ep & 0x7f]) {
+        usbd_core_cfg.in_ep_cb[ep & 0x7f](ep);
+    }
+
+#endif
+}
+
+static void usbd_class_event_notify_handler(uint8_t event, void *arg)
+{
+    usb_slist_t *i, *j;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            if (intf->notify_handler) {
+                intf->notify_handler(event, arg);
+            }
+        }
+    }
+}
+
+void usbd_event_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_set_address(0);
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 1
+            usbd_ep_callback_register();
+#endif
+
+        case USB_EVENT_ERROR:
+        case USB_EVENT_SOF:
+        case USB_EVENT_CONNECTED:
+        case USB_EVENT_CONFIGURED:
+        case USB_EVENT_SUSPEND:
+        case USB_EVENT_DISCONNECTED:
+        case USB_EVENT_RESUME:
+        case USB_EVENT_SET_INTERFACE:
+        case USB_EVENT_SET_REMOTE_WAKEUP:
+        case USB_EVENT_CLEAR_REMOTE_WAKEUP:
+        case USB_EVENT_SET_HALT:
+        case USB_EVENT_CLEAR_HALT:
+            usbd_class_event_notify_handler(event, arg);
+            break;
+
+        case USB_EVENT_SETUP_NOTIFY:
+            usbd_ep0_setup_handler();
+            break;
+
+        case USB_EVENT_EP0_IN_NOTIFY:
+            usbd_ep0_in_handler();
+            break;
+
+        case USB_EVENT_EP0_OUT_NOTIFY:
+            usbd_ep0_out_handler();
+            break;
+
+        case USB_EVENT_EP_IN_NOTIFY:
+            usbd_ep_in_handler((uint32_t)arg);
+            break;
+
+        case USB_EVENT_EP_OUT_NOTIFY:
+            usbd_ep_out_handler((uint32_t)arg);
+            break;
+
+        default:
+            USBD_LOG_ERR("USB unknown event: %d", event);
+            break;
+    }
+}
+
+void usbd_desc_register(const uint8_t *desc)
+{
+    usbd_core_cfg.descriptors = desc;
+}
+/* Register MS OS Descriptors version 1 */
+void usbd_msosv1_desc_register(struct usb_msosv1_descriptor *desc)
+{
+    msosv1_desc = desc;
+}
+
+void usbd_class_register(usbd_class_t *class)
+{
+    usb_slist_add_tail(&usbd_class_head, &class->list);
+    usb_slist_init(&class->intf_list);
+}
+
+void usbd_class_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static uint8_t intf_offset = 0;
+    intf->intf_num = intf_offset;
+    usb_slist_add_tail(&class->intf_list, &intf->list);
+    usb_slist_init(&intf->ep_list);
+    intf_offset++;
+}
+
+void usbd_interface_add_endpoint(usbd_interface_t *intf, usbd_endpoint_t *ep)
+{
+    usb_slist_add_tail(&intf->ep_list, &ep->list);
+}
+
+bool usb_device_is_configured(void)
+{
+    return usbd_core_cfg.configured;
+}
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/core/usbd_core.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/core/usbd_core.h
new file mode 100644
index 0000000000000000000000000000000000000000..20fd07727301e4c6de14600c47da2dfa77e01744
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/components/usb_stack/core/usbd_core.h
@@ -0,0 +1,136 @@
+/**
+ * @file usbd_core.h
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _USBD_CORE_H
+#define _USBD_CORE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_util.h"
+#include "usb_def.h"
+#include "usb_dc.h"
+
+enum usb_event_type {
+    /** USB error reported by the controller */
+    USB_EVENT_ERROR,
+    /** USB reset */
+    USB_EVENT_RESET,
+    /** Start of Frame received */
+    USB_EVENT_SOF,
+    /** USB connection established, hardware enumeration is completed */
+    USB_EVENT_CONNECTED,
+    /** USB configuration done */
+    USB_EVENT_CONFIGURED,
+    /** USB connection suspended by the HOST */
+    USB_EVENT_SUSPEND,
+    /** USB connection lost */
+    USB_EVENT_DISCONNECTED,
+    /** USB connection resumed by the HOST */
+    USB_EVENT_RESUME,
+
+    /** USB interface selected */
+    USB_EVENT_SET_INTERFACE,
+    /** USB interface selected */
+    USB_EVENT_SET_REMOTE_WAKEUP,
+    /** USB interface selected */
+    USB_EVENT_CLEAR_REMOTE_WAKEUP,
+    /** Set Feature ENDPOINT_HALT received */
+    USB_EVENT_SET_HALT,
+    /** Clear Feature ENDPOINT_HALT received */
+    USB_EVENT_CLEAR_HALT,
+    /** setup packet received */
+    USB_EVENT_SETUP_NOTIFY,
+    /** ep0 in packet received */
+    USB_EVENT_EP0_IN_NOTIFY,
+    /** ep0 out packet received */
+    USB_EVENT_EP0_OUT_NOTIFY,
+    /** ep in packet except ep0 received */
+    USB_EVENT_EP_IN_NOTIFY,
+    /** ep out packet except ep0 received */
+    USB_EVENT_EP_OUT_NOTIFY,
+    /** Initial USB connection status */
+    USB_EVENT_UNKNOWN
+};
+
+/**
+ * @brief Callback function signature for the USB Endpoint status
+ */
+typedef void (*usbd_endpoint_callback)(uint8_t ep);
+
+/**
+ * @brief Callback function signature for class specific requests
+ *
+ * Function which handles Class specific requests corresponding to an
+ * interface number specified in the device descriptor table. For host
+ * to device direction the 'len' and 'payload_data' contain the length
+ * of the received data and the pointer to the received data respectively.
+ * For device to host class requests, 'len' and 'payload_data' should be
+ * set by the callback function with the length and the address of the
+ * data to be transmitted buffer respectively.
+ */
+typedef int (*usbd_request_handler)(struct usb_setup_packet *setup,
+                                    uint8_t **data, uint32_t *transfer_len);
+
+/* callback function pointer structure for Application to handle events */
+typedef void (*usbd_notify_handler)(uint8_t event, void *arg);
+
+typedef struct usbd_endpoint {
+    usb_slist_t list;
+    uint8_t ep_addr;
+    usbd_endpoint_callback ep_cb;
+} usbd_endpoint_t;
+
+typedef struct usbd_interface {
+    usb_slist_t list;
+    /** Handler for USB Class specific Control (EP 0) communications */
+    usbd_request_handler class_handler;
+    /** Handler for USB Vendor specific commands */
+    usbd_request_handler vendor_handler;
+    /** Handler for USB custom specific commands */
+    usbd_request_handler custom_handler;
+    /** Handler for USB event notify commands */
+    usbd_notify_handler notify_handler;
+    uint8_t intf_num;
+    usb_slist_t ep_list;
+} usbd_interface_t;
+
+typedef struct usbd_class {
+    usb_slist_t list;
+    const char *name;
+    usb_slist_t intf_list;
+} usbd_class_t;
+
+void usbd_event_notify_handler(uint8_t event, void *arg);
+
+void usbd_desc_register(const uint8_t *desc);
+void usbd_class_register(usbd_class_t *class);
+void usbd_msosv1_desc_register(struct usb_msosv1_descriptor *desc);
+void usbd_class_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+void usbd_interface_add_endpoint(usbd_interface_t *intf, usbd_endpoint_t *ep);
+bool usb_device_is_configured(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/bl602_flash.ld b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/bl602_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..7047d866b5fca2d0a5dafaa03951def1e4f57a0a
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/bl602_flash.ld
@@ -0,0 +1,227 @@
+/****************************************************************************************
+* @file map.txt
+*
+* @brief This file is the map file (gnuarm or armgcc).
+*
+* Copyright (C) BouffaloLab 2018
+*
+****************************************************************************************
+*/
+
+/* configure the CPU type */
+OUTPUT_ARCH( "riscv" )
+/* link with the standard c library */
+/*INPUT(-lc)*/
+/* link with the standard GCC library */
+/*INPUT(-lgcc)*/
+/* configure the entry point */
+ENTRY(_enter)
+
+StackSize = 0x0400; /*  1KB */
+HeapSize  = 0x1000; /*  4KB */
+
+MEMORY
+{
+    xip_memory  (rx)  : ORIGIN = 0x23000000, LENGTH = 1024K
+    itcm_memory (rx)  : ORIGIN = 0x22010000, LENGTH = 16K
+    dtcm_memory (rx)  : ORIGIN = 0x42014000, LENGTH = 48K
+    ram_memory  (!rx) : ORIGIN = 0x42020000, LENGTH = 176K
+}
+
+SECTIONS
+{
+    PROVIDE(__metal_chicken_bit = 0);
+
+    .text :
+    {
+        . = ALIGN(4);
+        __text_code_start__ = .;
+
+        KEEP (*(.text.metal.init.enter))
+        KEEP (*(SORT_NONE(.init)))
+
+        /* section information for shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        *(.text)
+        *(.text.*)
+
+        /*put .rodata**/
+        *(EXCLUDE_FILE( *bl602_glb.o \
+                        *bl602_pds.o \
+                        *bl602_common.o \
+                        *bl602_sf_cfg.o \
+                        *bl602_sf_ctrl.o \
+                        *bl602_sflash.o \
+                        *bl602_xip_sflash.o \
+                        *bl602_ef_ctrl.o) .rodata*)
+        *(.rodata)
+        *(.rodata.*)
+
+        *(.srodata)
+        *(.srodata.*)
+
+        . = ALIGN(4);
+        __text_code_end__ = .;
+
+    } > xip_memory
+
+    . = ALIGN(4);
+    __itcm_load_addr = .;
+
+    .itcm_region : AT (__itcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_code_start__ = .;
+
+        *(.tcm_code)
+        *(.tcm_const)
+        *(.sclock_rlt_code)
+        *(.sclock_rlt_const)
+
+        *bl602_glb.o*(.rodata*)
+        *bl602_pds.o*(.rodata*)
+        *bl602_common.o*(.rodata*)
+        *bl602_sf_cfg.o*(.rodata*)
+        *bl602_sf_ctrl.o*(.rodata*)
+        *bl602_sflash.o*(.rodata*)
+        *bl602_xip_sflash.o*(.rodata*)
+        *bl602_ef_ctrl.o*(.rodata*)
+
+        . = ALIGN(4);
+        __tcm_code_end__ = .;
+    } > itcm_memory
+
+    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
+
+    .dtcm_region : AT (__dtcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_data_start__ = .;
+
+        *(.tcm_data)
+
+        . = ALIGN(4);
+        __tcm_data_end__ = .;
+    } > dtcm_memory
+
+
+    /* .heap_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of heap sections, and assign
+     * values to heap symbols later */
+    .heap_dummy (NOLOAD):
+    {
+        . = ALIGN(0x4);
+        . = . + HeapSize;
+        . = ALIGN(0x4);
+    } > dtcm_memory
+
+    _HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;
+    _HeapSize = HeapSize;
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(_HeapBase >= __tcm_data_end__, "region RAM overflowed with stack")
+
+    /*************************************************************************/
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(0x4);
+        . = . + StackSize;
+        . = ALIGN(0x4);
+    } > dtcm_memory
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
+    PROVIDE( __freertos_irq_stack_top = __StackTop);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
+    /*************************************************************************/
+
+    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
+
+    .system_ram_data_region : AT (__system_ram_load_addr)
+    {
+        . = ALIGN(4);
+        __system_ram_data_start__ = .;
+
+        *(.system_ram)
+
+        . = ALIGN(4);
+        __system_ram_data_end__ = .;
+    } > ram_memory
+
+    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
+
+    /* Data section */
+    RAM_DATA : AT (__ram_load_addr)
+    {
+        . = ALIGN(4);
+        __ram_data_start__ = .;
+
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.data)
+        *(.data.*)
+        *(.sdata)
+        *(.sdata.*)
+        *(.sdata2)
+        *(.sdata2.*)
+
+        . = ALIGN(4);
+        __ram_data_end__ = .;
+    } > ram_memory
+
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+
+        *(.bss*)
+        *(.sbss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram_memory
+
+    .noinit_data (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __noinit_data_start__ = .;
+
+        *(.noinit_data*)
+
+        . = ALIGN(4);
+        __noinit_data_end__ = .;
+    } > ram_memory
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(4);
+        __HeapBase = .;
+
+        /*__end__ = .;*/
+        /*end = __end__;*/
+        KEEP(*(.heap*))
+
+        . = ALIGN(4);
+        __HeapLimit = .;
+    } > ram_memory
+    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
+
+}
+
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/blsp_boot2_iap_flash.ld b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/blsp_boot2_iap_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..78cd3f1ae53872f0665abf6813636f8f16d51134
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/blsp_boot2_iap_flash.ld
@@ -0,0 +1,193 @@
+/****************************************************************************************
+* @file map.txt
+*
+* @brief This file is the map file (gnuarm or armgcc).
+*
+* Copyright (C) BouffaloLab 2018
+*
+****************************************************************************************
+*/
+
+/* configure the CPU type */
+OUTPUT_ARCH( "riscv" )
+/* link with the standard c library */
+INPUT(-lc)
+/* link with the standard GCC library */
+INPUT(-lgcc)
+/* configure the entry point */
+ENTRY(_enter)
+
+StackSize = 0x1000; /*  4KB */
+HeapSize  = 0x0;    /*  0KB */
+PROVIDE(__boot2_pass_param_addr = 0x42049C00);/* 0x42030000+103*1024 */
+MEMORY
+{
+	xip_memory (rx) : 		ORIGIN = 0x23000000, LENGTH = 48K
+    itcm_memory (rx) : 		ORIGIN = 0x2201c000, LENGTH = 16K
+    dtcm_memory (rx)  : 	ORIGIN = 0x42020000, LENGTH = 4K
+    ram_memory (!rx) :   	ORIGIN = 0x42021000, LENGTH = 156K
+}
+
+SECTIONS
+{
+    PROVIDE(__metal_chicken_bit = 0);
+
+    .text :
+    {
+        . = ALIGN(4);
+        __text_code_start__ = .;
+
+        KEEP (*(.text.metal.init.enter))
+        KEEP (*(SORT_NONE(.init)))
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        _shell_command_start = .;
+        KEEP(*(shellCommand))
+        _shell_command_end = .;
+
+        *(EXCLUDE_FILE ( *bl602_uart.c.obj* *hal_uart.c.obj* ) .text*)
+
+        *(.rodata)
+        *(.rodata.*)
+        *(.srodata)
+        *(.srodata.*)
+
+        . = ALIGN(4);
+        __text_code_end__ = .;
+    } > xip_memory
+
+    . = ALIGN(4);
+    __itcm_load_addr = .;
+
+    .itcm_region : AT (__itcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_code_start__ = .;
+        *(.tcm_code)
+        *(.tcm_const)
+        *(.sclock_rlt_code)
+        *(.sclock_rlt_const)
+        *bl602_romapi.o(.text)
+        *bl602_romapi.o(.text.*)
+        *bl602_romapi.o(.rodata)
+        *bl602_romapi.o(.rodata.*)
+        *bl602_romapi.o(.srodata)
+        *bl602_romapi.o(.srodata.*)
+        *bl602_uart.c.obj* (.text*)
+        *hal_uart.c.obj* (.text*)
+        . = ALIGN(4);
+        __tcm_code_end__ = .;
+
+    } > itcm_memory
+
+    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
+
+    .dtcm_region : AT (__dtcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_data_start__ = .;
+
+        *(.tcm_data)
+        /* *finger_print.o(.data*) */
+
+        . = ALIGN(4);
+        __tcm_data_end__ = .;
+    } > dtcm_memory
+
+	/* .heap_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of heap sections, and assign
+     * values to heap symbols later */
+    .heap_dummy (NOLOAD):
+    {
+        . = ALIGN(0x4);
+        . = . + HeapSize;
+        . = ALIGN(0x4);
+    } > dtcm_memory
+
+    __HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;
+    __HeapSize = HeapSize;
+    __HeapLimit = __HeapBase + __HeapSize;
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__HeapBase >= __tcm_data_end__, "region RAM overflowed with stack")
+
+    /*************************************************************************/
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(0x4);
+        . = . + StackSize;
+        . = ALIGN(0x4);
+    } > dtcm_memory
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
+    /*************************************************************************/
+
+    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
+
+    .system_ram_data_region : AT (__system_ram_load_addr)
+    {
+        . = ALIGN(4);
+        __system_ram_data_start__ = .;
+
+        *(.system_ram)
+
+        . = ALIGN(4);
+        __system_ram_data_end__ = .;
+    } > ram_memory
+
+    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
+
+    /* Data section */
+    RAM_DATA : AT (__ram_load_addr)
+    {
+        . = ALIGN(4);
+        __ram_data_start__ = .;
+
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.data)
+        *(.data.*)
+        *(.sdata)
+        *(.sdata.*)
+        *(.sdata2)
+        *(.sdata2.*)
+
+        . = ALIGN(4);
+        __ram_data_end__ = .;
+    } > ram_memory
+
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+
+        *(.bss*)
+        *(.sbss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram_memory
+
+    .noinit_data (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __noinit_data_start__ = .;
+
+        *(.noinit_data*)
+
+        . = ALIGN(4);
+        __noinit_data_end__ = .;
+    } > ram_memory
+
+
+}
+
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/cpu_flags.cmake b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/cpu_flags.cmake
new file mode 100644
index 0000000000000000000000000000000000000000..a23da8024ef2467f9d0033e6844cbe4f443de69f
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/cpu_flags.cmake
@@ -0,0 +1,10 @@
+SET(CPU_ARCH "RISCV")
+SET(MCPU "e24")
+SET(MARCH "rv32imafc")
+SET(MABI "ilp32f")
+
+list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI})
+list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI})
+
+SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl602_flash.ld)
+SET(BOOT2_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/blsp_boot2_iap_flash.ld)
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/adc_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/adc_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..51b53b949547e53d067e4944543d7eb36afc48fd
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/adc_config.h
@@ -0,0 +1,4 @@
+#ifndef _ADC_CONFIG_H
+#define _ADC_CONFIG_H
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/spi_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/spi_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..16dbed2baafa1c86f3e11ae095929cae07b0531f
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/spi_config.h
@@ -0,0 +1,6 @@
+#ifndef _SPI_CONFIG_H
+#define _SPI_CONFIG_H
+
+#define SPI_DEGLITCH_ENABLE          (0)
+#define SPI_CONTINUE_TRANSFER_ENABLE (1)
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/uart_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/uart_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..1c633326df422fa26a3ce62a4637e360bb032982
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/default_config/uart_config.h
@@ -0,0 +1,12 @@
+#ifndef _UART_CONFIG_H
+#define _UART_CONFIG_H
+
+#define UART_CLOCK_SOURCE_160M_ENABLE (1)
+#define UART_CTS_FLOWCONTROL_ENABLE   (0)
+#define UART_RTS_FLOWCONTROL_ENABLE   (0)
+#define UART_RX_DEGLITCH_ENABLE       (0)
+#define UART_MSB_FIRST_ENABLE         (0)
+
+#define UART_FIFO_MAX_LEN        32
+#define UART_DEFAULT_RTO_TIMEOUT 255
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_boot2.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_boot2.h
new file mode 100644
index 0000000000000000000000000000000000000000..9ca614d551588af610431ff0180468b7c500a060
--- /dev/null
+++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_boot2.h
@@ -0,0 +1,106 @@
+/**
+ * *****************************************************************************
+ * @file hal_boot2_custom.h
+ * @version 0.1
+ * @date 2021-07-17
+ * @brief
+ * *****************************************************************************
+ * @attention
+ *
+ *  

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __HAL_BOOT2_H__ +#define __HAL_BOOT2_H__ + +#include "drv_device.h" +#include "bl602_sflash.h" +#include "bl602_glb.h" + +#define BL_TCM_BASE BL602_TCM_BASE +#define BL_SYS_CLK_PLL GLB_SYS_CLK_PLL160M +#define BL_SFLASH_CLK GLB_SFLASH_CLK_80M +#define HAL_PLL_CFG_MAGICCODE "PCFG" + +#define HAL_EFUSE_CPU_MAX 2 +#define HAL_EFUSE_PK_HASH_SIZE 256 / 8 +#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support decompress, 0 not support */ + +typedef struct +{ + uint8_t encrypted[HAL_EFUSE_CPU_MAX]; + uint8_t sign[HAL_EFUSE_CPU_MAX]; + uint8_t hbn_check_sign; + uint8_t rsvd[3]; + uint8_t chip_id[8]; + uint8_t pk_hash_cpu0[HAL_EFUSE_PK_HASH_SIZE]; + uint8_t pk_hash_cpu1[HAL_EFUSE_PK_HASH_SIZE]; +} boot2_efuse_hw_config; + +typedef struct +{ + uint8_t xtal_type; + uint8_t pll_clk; + uint8_t hclk_div; + uint8_t bclk_div; + + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t rsvd[2]; +} hal_sys_clk_config; + +typedef struct +{ + uint32_t magicCode; /*'PCFG'*/ + hal_sys_clk_config cfg; + uint32_t crc32; +} hal_pll_config; + +typedef struct +{ + uint32_t magicCode; /*'FCFG'*/ + SPI_Flash_Cfg_Type cfg; + uint32_t crc32; +} hal_flash_config; + +uint32_t hal_boot2_custom(void); +void hal_boot2_reset_sec_eng(void); +void hal_boot2_sw_system_reset(void); +void hal_boot2_set_psmode_status(uint32_t flag); +uint32_t hal_boot2_get_psmode_status(void); +uint32_t hal_boot2_get_user_fw(void); +void hal_boot2_clr_user_fw(void); +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg); +int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg); +void hal_boot2_sboot_finish(void); +void hal_boot2_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_deinit(void); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_clock.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_clock.h new file mode 100644 index 0000000000000000000000000000000000000000..a8ee5dc1f06ebdd269370564ef3d23981b82c749 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_clock.h @@ -0,0 +1,77 @@ +/** + * @file hal_clock.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_CLOCK__H__ +#define __HAL_CLOCK__H__ + +#include "drv_device.h" +#include "bl602_config.h" + +/*XTAL_TYPE*/ +#define XTAL_NONE 0 +#define EXTERNAL_XTAL_24M 1 +#define EXTERNAL_XTAL_32M 2 +#define EXTERNAL_XTAL_38P4M 3 +#define EXTERNAL_XTAL_40M 4 +#define EXTERNAL_XTAL_26M 5 +#define INTERNAL_RC_32M 6 + +/*CLOCK_32K_XTAL*/ +#define EXTERNAL_XTAL_32K 1 +#define INTERNAL_RC_32K 0 + +/*BSP_ROOT_CLOCK_SOURCE*/ +#if (XTAL_TYPE == INTERNAL_RC_32M) || (XTAL_TYPE == XTAL_NONE) +#define ROOT_CLOCK_SOURCE_XCLK 0 +#else +#define ROOT_CLOCK_SOURCE_XCLK 1 +#endif +#define ROOT_CLOCK_SOURCE_PLL_48M 2 +#define ROOT_CLOCK_SOURCE_PLL_120M 3 +#define ROOT_CLOCK_SOURCE_PLL_160M 4 +#define ROOT_CLOCK_SOURCE_PLL_192M 5 + +/*BSP_XXX_CLOCK_SOURCE*/ +#define ROOT_CLOCK_SOURCE_FCLK 6 +#define ROOT_CLOCK_SOURCE_BCLK 7 + +enum system_clock_type { + SYSTEM_CLOCK_ROOT_CLOCK = 0, + SYSTEM_CLOCK_FCLK, + SYSTEM_CLOCK_BCLK, + SYSTEM_CLOCK_XCLK, +}; +enum peripheral_clock_type { + PERIPHERAL_CLOCK_UART = 0, + PERIPHERAL_CLOCK_SPI, + PERIPHERAL_CLOCK_I2C, + PERIPHERAL_CLOCK_ADC, + PERIPHERAL_CLOCK_DAC, +}; + +void system_clock_init(void); +void system_mtimer_clock_init(void); +void system_mtimer_clock_reinit(void); +void peripheral_clock_init(void); +uint32_t system_clock_get(enum system_clock_type type); +uint32_t peripheral_clock_get(enum peripheral_clock_type type); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_dma.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..86d466c01425d17bfd51cfe8311e8e536c79fe6b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_dma.h @@ -0,0 +1,191 @@ +/** + * @file hal_dma.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_DMA__H__ +#define __HAL_DMA__H__ + +#include "drv_device.h" +#include "bl602_config.h" + +#define DMA_CHANNEL_GET_STATUS 0x10 +#define DMA_CHANNEL_START 0x11 +#define DMA_CHANNEL_STOP 0x12 +#define DMA_CHANNEL_UPDATE 0x13 + +enum dma_index_type { +#ifdef BSP_USING_DMA0_CH0 + DMA0_CH0_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH1 + DMA0_CH1_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH2 + DMA0_CH2_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH3 + DMA0_CH3_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH4 + DMA0_CH4_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH5 + DMA0_CH5_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH6 + DMA0_CH6_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH7 + DMA0_CH7_INDEX, +#endif + DMA_MAX_INDEX +}; + +#define dma_channel_start(dev) device_control(dev, DMA_CHANNEL_START, NULL) +#define dma_channel_stop(dev) device_control(dev, DMA_CHANNEL_STOP, NULL) +#define dma_channel_update(dev, list) device_control(dev, DMA_CHANNEL_UPDATE, list) +#define dma_channel_check_busy(dev) device_control(dev, DMA_CHANNEL_GET_STATUS, NULL) + +#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88) +#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C) +#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88) +#define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C) +#define DMA_ADDR_I2C_TDR (0x4000A300 + 0x88) +#define DMA_ADDR_I2C_RDR (0x4000A300 + 0x8C) +#define DMA_ADDR_SPI_TDR (0x4000A200 + 0x88) +#define DMA_ADDR_SPI_RDR (0x4000A200 + 0x8C) +#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88) +#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C) +#define DMA_ADDR_ADC0_DR (0x40002000 + 0x04) +#define DMA_ADDR_ADC1_DR (0x40002000 + 0x04) +#define DMA_ADDR_DAC_TDR (0x40002048) + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE 1 /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0 /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE 1 /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0 /*!< Memory increment mode disable */ + +#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */ +#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */ +#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX */ +#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX */ +#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX */ +#define DMA_REQUEST_I2C0_RX 0x00000006 /*!< DMA request peripheral:I2C RX */ +#define DMA_REQUEST_I2C0_TX 0x00000007 /*!< DMA request peripheral:I2C TX */ +#define DMA_REQUEST_SPI0_RX 0x0000000A /*!< DMA request peripheral:SPI RX */ +#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI TX */ +#define DMA_REQUEST_I2S_RX 0x00000014 /*!< DMA request peripheral:I2S RX */ +#define DMA_REQUEST_I2S_TX 0x00000015 /*!< DMA request peripheral:I2S TX */ +#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:GPADC0 */ +#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:GPADC1 */ + +#define DMA_BURST_1BYTE 0 +#define DMA_BURST_4BYTE 1 +#define DMA_BURST_8BYTE 2 +#define DMA_BURST_16BYTE 3 + +#define DMA_TRANSFER_WIDTH_8BIT 0 +#define DMA_TRANSFER_WIDTH_16BIT 1 +#define DMA_TRANSFER_WIDTH_32BIT 2 + +#define DMA_LLI_ONCE_MODE 0 +#define DMA_LLI_CYCLE_MODE 1 + +/** + * @brief DMA transfer direction type definition + */ +typedef enum { + DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer tyep:memory to memory */ + DMA_MEMORY_TO_PERIPH, /*!< DMA transfer tyep:memory to peripheral */ + DMA_PERIPH_TO_MEMORY, /*!< DMA transfer tyep:peripheral to memory */ + DMA_PERIPH_TO_PERIPH, /*!< DMA transfer tyep:peripheral to peripheral */ +} dma_transfer_dir_type; + +typedef union { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } bits; + uint32_t WORD; +} dma_control_data_t; + +typedef struct +{ + uint32_t src_addr; + uint32_t dst_addr; + uint32_t nextlli; + dma_control_data_t cfg; +} dma_lli_ctrl_t; + +typedef struct +{ + uint8_t direction; + uint32_t src_req; + uint32_t dst_req; +} dma_ctrl_param_t; + +typedef struct dma_device { + struct device parent; + uint8_t id; + uint8_t ch; + uint8_t direction; + uint8_t transfer_mode; + uint32_t src_req; + uint32_t dst_req; + uint8_t src_burst_size; + uint8_t dst_burst_size; + uint8_t src_width; + uint8_t dst_width; + dma_lli_ctrl_t *lli_cfg; +} dma_device_t; + +#define DMA_DEV(dev) ((dma_device_t *)dev) + +int dma_register(enum dma_index_type, const char *name); +int dma_allocate_register(const char *name); +int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_flash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..c2b6038e5518629e623430ddea0e2db2e9c57c6d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_flash.h @@ -0,0 +1,41 @@ +/** + * @file hal_flash.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_FLASH__H__ +#define __HAL_FLASH__H__ + +#include "drv_device.h" + + +#define BL_FLASH_XIP_BASE BL602_FLASH_XIP_BASE +#define FLASH_NOT_DETECT 0x10 + +BL_Err_Type flash_init(void); +BL_Err_Type flash_read_jedec_id(uint8_t *data); +BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type flash_read(uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len); +BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset); +BL_Err_Type flash_get_cfg(uint8_t **cfg_addr,uint32_t *len); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_gpio.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..24a9318aca814b67055ab062acfdf42d23ca4d76 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_gpio.h @@ -0,0 +1,95 @@ +/** + * ***************************************************************************** + * @file hal_gpio.h + * @version 0.1 + * @date 2021-03-01 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __HAL_GPIO__H__ +#define __HAL_GPIO__H__ + +#include "drv_device.h" + +typedef enum { + GPIO_PIN_0 = 0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, + GPIO_PIN_8, + GPIO_PIN_9, + GPIO_PIN_10, + GPIO_PIN_11, + GPIO_PIN_12, + GPIO_PIN_13, + GPIO_PIN_14, + GPIO_PIN_15, + GPIO_PIN_16, + GPIO_PIN_17, + GPIO_PIN_18, + GPIO_PIN_19, + GPIO_PIN_20, + GPIO_PIN_21, + GPIO_PIN_22, + GPIO_PIN_23, + GPIO_PIN_24, + GPIO_PIN_25, + GPIO_PIN_26, + GPIO_PIN_27, + GPIO_PIN_28, + GPIO_PIN_MAX, +} gpio_pin_type; + +#define GPIO_OUTPUT_MODE 0 +#define GPIO_OUTPUT_PP_MODE 1 +#define GPIO_OUTPUT_PD_MODE 2 +#define GPIO_INPUT_MODE 3 +#define GPIO_INPUT_PP_MODE 4 +#define GPIO_INPUT_PD_MODE 5 +#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6 +#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7 +#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8 +#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9 +#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10 +#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11 +#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 12 +#define GPIO_SYNC_LOW_LEVEL_INT_MODE 13 + +void gpio_set_mode(uint32_t pin, uint32_t mode); +void gpio_write(uint32_t pin, uint32_t value); +void gpio_toggle(uint32_t pin); +int gpio_read(uint32_t pin); +void gpio_attach_irq(uint32_t pin, void (*cbFun)(void)); +void gpio_irq_enable(uint32_t pin, uint8_t enabled); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_mtimer.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_mtimer.h new file mode 100644 index 0000000000000000000000000000000000000000..e547994cdfb90c17562ea4390bb9ad60c3e4d9b8 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_mtimer.h @@ -0,0 +1,12 @@ +#ifndef __HAL_MTIMER__H__ +#define __HAL_MTIMER__H__ + +#include "stdint.h" + +void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)); +uint32_t mtimer_get_clk_src_div(void); +uint64_t mtimer_get_time_ms(); +uint64_t mtimer_get_time_us(); +void mtimer_delay_ms(uint32_t time); +void mtimer_delay_us(uint32_t time); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_sec_ecdsa.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_sec_ecdsa.h new file mode 100644 index 0000000000000000000000000000000000000000..e38745c797581cad30dd7f51ed38556dc52a5058 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_sec_ecdsa.h @@ -0,0 +1,62 @@ +/** + * @file hal_sec_ecdsa.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_ECDSA__H__ +#define __HAL_SEC_ECDSA__H__ + +#include "drv_device.h" +#include "bl602_config.h" + +typedef enum { + ECP_SECP256R1 = 0, +} sec_ecp_type; + +typedef struct +{ + sec_ecp_type ecpId; + uint32_t *privateKey; + uint32_t *publicKeyx; + uint32_t *publicKeyy; +} sec_ecdsa_handle_t; + +typedef struct +{ + sec_ecp_type ecpId; +} sec_ecdh_handle_t; + +int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id); +int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle); +int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s); +int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s); +int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key); +int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); + +int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id); +int sec_ecdh_deinit(sec_ecdh_handle_t *handle); +int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); +int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); +int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size); +int sec_eng_trng_enable(void); +void sec_eng_trng_disable(void); +int sec_eng_trng_read(uint8_t data[32]); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_sec_hash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_sec_hash.h new file mode 100644 index 0000000000000000000000000000000000000000..295192c8ecbf740e9fd133b5d011f22d5574442f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_sec_hash.h @@ -0,0 +1,53 @@ +/** + * @file hal_sec_hash.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_HASH__H__ +#define __HAL_SEC_HASH__H__ + +#include "drv_device.h" +#include "bl602_config.h" + +enum sec_hash_index_type { + SEC_HASH0_INDEX, + SEC_HASH_MAX_INDEX +}; + +enum sec_hash_type { + SEC_HASH_SHA1, + SEC_HASH_SHA224, + SEC_HASH_SHA256, + SEC_HASH_SHA384, + SEC_HASH_SHA512, + SEC_HASH_UNKNOWN +}; + +typedef struct sec_hash_device { + struct device parent; + uint32_t shaBuf[64 / 4]; /*!< Data not processed but in this temp buffer */ + uint32_t shaPadding[64 / 4]; /*!< Padding data */ + uint8_t type; /*!< Sha has feed data */ +} sec_hash_device_t; + +int sec_hash_register(enum sec_hash_index_type index, const char *name); +int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_uart.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..4cc5adcb574d3c6b8aa437a4aabe3dba4b36ab27 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/inc/hal_uart.h @@ -0,0 +1,156 @@ +/** + * ***************************************************************************** + * @file hal_uart.h + * @version 0.1 + * @date 2021-03-01 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __HAL_UART__H__ +#define __HAL_UART__H__ + +#include "drv_device.h" +#include "bl602_config.h" + +#define UART_FIFO_LEN 32 + +#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10 +#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11 +#define DEVICE_CTRL_UART_ATTACH_TX_DMA 0x12 +#define DEVICE_CTRL_UART_ATTACH_RX_DMA 0x13 + +enum uart_index_type { +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif + UART_MAX_INDEX +}; + +/*! + * @brief UART data length settings + * + * This enumeration defines the UART data lengths. + */ +typedef enum { + UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */ + UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */ + UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */ + UART_DATA_LEN_8 = 3 /*!< Data length is 8 bits */ +} uart_databits_t; + +/*! + * @brief UART stop bit settings + * + * This enumeration defines the UART stop bits. + */ +typedef enum { + UART_STOP_ZERO_D_FIVE = 0, /*!< One stop bit */ + UART_STOP_ONE = 1, /*!< One stop bit */ + UART_STOP_ONE_D_FIVE = 2, /*!< 1.5 stop bit */ + UART_STOP_TWO = 3 /*!< Two stop bits */ +} uart_stopbits_t; + +/*! + * @brief UART parity type settings + * + * This enumeration defines the UART parity types. + */ +typedef enum { + UART_PAR_NONE = 0, /*!< No parity */ + UART_PAR_ODD = 1, /*!< Parity bit is odd */ + UART_PAR_EVEN = 2, /*!< Parity bit is even */ +} uart_parity_t; + +enum uart_event_type { + UART_EVENT_TX_END, + UART_EVENT_TX_FIFO, + UART_EVENT_RX_END, + UART_EVENT_RX_FIFO, + UART_EVENT_RTO, + UART_EVENT_UNKNOWN +}; + +typedef struct +{ + uint8_t tx; + uint8_t rx; + uint8_t cts; + uint8_t rts; +} uart_pin_t; + +enum uart_it_type { + UART_TX_END_IT = 1 << 0, + UART_RX_END_IT = 1 << 1, + UART_TX_FIFO_IT = 1 << 2, + UART_RX_FIFO_IT = 1 << 3, + UART_RTO_IT = 1 << 4, + UART_PCE_IT = 1 << 5, + UART_TX_FER_IT = 1 << 6, + UART_RX_FER_IT = 1 << 7, + UART_ALL_IT = 1 << 8 +}; + +typedef struct +{ + uint32_t baudrate; + uart_databits_t databits; + uart_stopbits_t stopbits; + uart_parity_t parity; +} uart_param_cfg_t; + +typedef struct uart_device { + struct device parent; + uint8_t id; + uint32_t baudrate; + uart_databits_t databits; + uart_stopbits_t stopbits; + uart_parity_t parity; + uint8_t fifo_threshold; + uart_pin_t pin; + void *tx_dma; + void *rx_dma; +} uart_device_t; + +#define UART_DEV(dev) ((uart_device_t *)dev) +int uart_register(enum uart_index_type index, const char *name); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_boot2.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_boot2.c new file mode 100644 index 0000000000000000000000000000000000000000..09ff50a2a7881b32060999ffb326539d6fd46bd1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_boot2.c @@ -0,0 +1,205 @@ +#include "hal_boot2.h" +#include "hal_gpio.h" +#include "hal_flash.h" +#include "bl602_glb.h" +#include "bl602_ef_ctrl.h" +#include "bl602_hbn.h" +#include "bl602_xip_sflash.h" +#include "bl602_sf_cfg.h" +#include "bl602_sf_cfg_ext.h" +#include "bl602_glb.h" +#include "bl602_xip_sflash_ext.h" +#include "tzc_sec_reg.h" + +/** + * @brief boot2 custom + * + * @param None + * @return uint32 + */ +uint32_t hal_boot2_custom(void) +{ + uint32_t sw_cfg, flash_pin_cfg; + EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&sw_cfg); + /* flash_pin_cfg + * 0:internal flash with io switch, + * 1:internal flash no io switch, + * 2:GPIO 17-22 + * 3:GPIO 0-2 & 20-22 + */ + flash_pin_cfg = ((sw_cfg>>16)&0x3); + if((flash_pin_cfg == 0)||(flash_pin_cfg == 1)){ + gpio_set_mode(GPIO_PIN_20, GPIO_OUTPUT_MODE); + gpio_write(GPIO_PIN_20, 0); + } + + + return 0; +} + +/** + * @brief get efuse Boot2 config + * + * @param g_efuse_cfg + * @param + * @param + * @return None + */ +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg) +{ + uint32_t tmp; + uint32_t rootClk; + uint8_t hdiv = 0, bdiv = 0; + + /* save bclk fclk div and root clock sel */ + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + rootClk = BL_RD_REG(HBN_BASE, HBN_GLB); + + /* change root clock to rc32m for efuse operation */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + + /* Get sign and aes type*/ + EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)g_efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)g_efuse_cfg->encrypted); + /* Get hash:aes key slot 0 and slot1*/ + EF_Ctrl_Read_AES_Key(0, (uint32_t *)g_efuse_cfg->pk_hash_cpu0, 8); + EF_Ctrl_Read_Chip_ID(g_efuse_cfg->chip_id); + /* Get HBN check sign config */ + EF_Ctrl_Read_Sw_Usage(0, &tmp); + g_efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01; + + /* restore bclk fclk div and root clock sel */ + GLB_Set_System_CLK_Div(hdiv, bdiv); + BL_WR_REG(HBN_BASE, HBN_GLB,rootClk); + __NOP();__NOP();__NOP();__NOP(); +} + +/** + * @brief reset sec eng clock + * + * @return + */ +void hal_boot2_reset_sec_eng(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC); +} + +/** + * @brief system soft reset + * + * @return + */ +void hal_boot2_sw_system_reset(void) +{ + GLB_SW_System_Reset(); +} + + +/** + * @brief + * + * @param flag + * @param + * @param + * @return + */ +void hal_boot2_set_psmode_status(uint32_t flag) +{ + HBN_Set_Status_Flag(flag); +} + +/** + * @brief + * + * @param + * @param + * @param + * @return flag + */ +uint32_t hal_boot2_get_psmode_status(void) +{ + return HBN_Get_Status_Flag(); +} + +/** + * @brief + * + * @param + * @param + * @param + * @return user define flag + */ +uint32_t hal_boot2_get_user_fw(void) +{ + return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); +} + +/** + * @brief clr user define flag + * + * @param + * @param + * @param + * @return + */ +void hal_boot2_clr_user_fw(void) +{ + uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET); + *p = 0; +} + +/** + * @brief hal_boot2_sboot_finish + * + * @return + */ +void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) +{ + uint32_t tmp_val; + + tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val); +} +/** + * @brief hal_boot2_uart_gpio_init + * + * @return + */ +void hal_boot2_uart_gpio_init(void) +{ + GLB_GPIO_Type gpios[]={GPIO_PIN_7,GPIO_PIN_16}; + + GLB_GPIO_Func_Init(GPIO_FUN_UART,gpios,2); + + GLB_UART_Fun_Sel((GPIO_PIN_7 % 8), GLB_UART_SIG_FUN_UART0_RXD); + GLB_UART_Fun_Sel((GPIO_PIN_16 % 8), GLB_UART_SIG_FUN_UART0_TXD); +} + +/** + * @brief hal_boot2_debug_uart_gpio_init + * + * @return + */ +void hal_boot2_debug_uart_gpio_init(void) +{ + GLB_GPIO_Type gpios[]={GPIO_PIN_8}; + + GLB_GPIO_Func_Init(GPIO_FUN_UART,gpios,1); + + GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_GPIO8_GPIO15); + GLB_UART_Fun_Sel(GLB_UART_SIG_4, GLB_UART_SIG_FUN_UART1_TXD); +} +/** + * @brief hal_boot2_debug_uart_gpio_deinit + * + * @return + */ +void hal_boot2_debug_uart_gpio_deinit(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0); + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1); + GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_clock.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..353e2d1ea76188f73f74ee93e896476b75e6bf68 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_clock.c @@ -0,0 +1,171 @@ +#include "bl602_glb.h" +#include "hal_clock.h" + +static uint32_t mtimer_get_clk_src_div(void) +{ + return ((SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1)) / 1000 / 1000 - 1); +} + +void system_clock_init(void) +{ + /*select root clock*/ + GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE); + /*set fclk/hclk and bclk clock*/ + GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); +#if 1 + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); +#else + HBN_32K_Sel(HBN_32K_XTAL); + HBN_Power_On_Xtal_32K(); +#endif + if ((XTAL_TYPE == INTERNAL_RC_32M) || (XTAL_TYPE == XTAL_NONE)) { + HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M); + } else { + HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL); + } +} + +void system_mtimer_clock_init(void) +{ + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); +} + +void system_mtimer_clock_reinit(void) +{ + /* reinit clock to 10M */ + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7); +} + +void peripheral_clock_init(void) +{ +#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) +#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_160M + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, BSP_UART_CLOCK_DIV); +#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_FCLK, BSP_UART_CLOCK_DIV); +#endif +#endif + +#if defined(BSP_USING_I2C0) + GLB_Set_I2C_CLK(ENABLE, BSP_I2C_CLOCK_DIV); +#endif + +#if defined(BSP_USING_SPI0) + GLB_Set_SPI_CLK(ENABLE, BSP_SPI_CLOCK_DIV); +#endif + +#if defined(BSP_USING_PWM) +#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K + +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + +#endif +#endif + +#if defined(BSP_USING_IR) + GLB_Set_IR_CLK(ENABLE, 0, BSP_IR_CLOCK_DIV); +#endif + +#if defined(BSP_USING_ADC0) +#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV); +#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV); +#endif + +#endif + +#if defined(BSP_USING_DAC0) +#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL + GLB_Set_DAC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV); +#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_Set_DAC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_DAC_CLOCK_DIV); +#endif +#endif +} +uint32_t system_clock_get(enum system_clock_type type) +{ + switch (type) { + case SYSTEM_CLOCK_ROOT_CLOCK: + return SystemCoreClockGet() * (GLB_Get_HCLK_Div() + 1); + + case SYSTEM_CLOCK_FCLK: + return SystemCoreClockGet(); + + case SYSTEM_CLOCK_BCLK: + return (SystemCoreClockGet() / ((GLB_Get_HCLK_Div() + 1) * (GLB_Get_BCLK_Div() + 1))); + + case SYSTEM_CLOCK_XCLK: + switch (XTAL_TYPE) { + case XTAL_NONE: + return 32000000; + case EXTERNAL_XTAL_24M: + return 24000000; + case EXTERNAL_XTAL_32M: + return 32000000; + case EXTERNAL_XTAL_38P4M: + return 38400000; + case EXTERNAL_XTAL_40M: + return 40000000; + case EXTERNAL_XTAL_26M: + return 26000000; + case INTERNAL_RC_32M: + return 32000000; + default: + break; + } + + default: + break; + } + + return 0; +} +uint32_t peripheral_clock_get(enum peripheral_clock_type type) +{ + uint32_t tmpVal; + uint32_t div; + + switch (type) { + case PERIPHERAL_CLOCK_UART: +#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) +#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_160M + return 160000000; +#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + return system_clock_get(SYSTEM_CLOCK_FCLK) / (GLB_Get_HCLK_Div() + 1)); +#endif +#endif + + case PERIPHERAL_CLOCK_SPI: +#if defined(BSP_USING_SPI0) +#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1); +#endif +#endif + + case PERIPHERAL_CLOCK_I2C: +#if defined(BSP_USING_I2C0) +#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1); +#endif +#endif + + case PERIPHERAL_CLOCK_ADC: + return 32000000; + + default: + break; + } + + (void)(tmpVal); + (void)(div); + return 0; +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_dma.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..344666a41e0d33f26f6de032b3b3bc8e2a9acbbf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_dma.c @@ -0,0 +1,469 @@ +/** + * @file hal_dma.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_dma.h" +#include "drv_mmheap.h" +#include "bl602_dma.h" + +dma_control_data_t dma_ctrl_cfg; + +void DMA0_IRQ(void); + +dma_device_t dmax_device[DMA_MAX_INDEX] = { +#ifdef BSP_USING_DMA0_CH0 + DMA0_CH0_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH1 + DMA0_CH1_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH2 + DMA0_CH2_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH3 + DMA0_CH3_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH4 + DMA0_CH4_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH5 + DMA0_CH5_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH6 + DMA0_CH6_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH7 + DMA0_CH7_CONFIG, +#endif +}; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int dma_open(struct device *dev, uint16_t oflag) +{ + dma_device_t *dma_device = (dma_device_t *)dev; + + DMA_LLI_Cfg_Type lliCfg = { 0 }; + + /* Disable all interrupt */ + DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK); + /* Enable uart interrupt*/ + CPU_Interrupt_Disable(DMA_ALL_IRQn); + + DMA_Disable(); + + DMA_Channel_Disable(dma_device->ch); + + lliCfg.dir = dma_device->direction; + lliCfg.srcPeriph = dma_device->src_req; + lliCfg.dstPeriph = dma_device->dst_req; + + DMA_LLI_Init(dma_device->ch, &lliCfg); + + dma_ctrl_cfg.bits.fix_cnt = 0; + dma_ctrl_cfg.bits.dst_min_mode = 0; + dma_ctrl_cfg.bits.dst_add_mode = 0; + + DMA_Enable(); + + Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ); + + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int dma_control(struct device *dev, int cmd, void *args) +{ + dma_device_t *dma_device = (dma_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: + /* Dma interrupt configuration */ + DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK); + DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK); + + /* Enable uart interrupt*/ + CPU_Interrupt_Enable(DMA_ALL_IRQn); + break; + + case DEVICE_CTRL_CLR_INT /* constant-expression */: + /* Dma interrupt configuration */ + DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK); + DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK); + + /* Enable uart interrupt*/ + CPU_Interrupt_Disable(DMA_ALL_IRQn); + break; + + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_CONFIG /* constant-expression */: { + dma_ctrl_param_t *cfg = (dma_ctrl_param_t *)args; + DMA_LLI_Cfg_Type lliCfg = { 0 }; + + lliCfg.dir = cfg->direction; + lliCfg.srcPeriph = cfg->src_req; + lliCfg.dstPeriph = cfg->dst_req; + + DMA_LLI_Init(dma_device->ch, &lliCfg); + + break; + } + + case DMA_CHANNEL_UPDATE: + DMA_LLI_Update(dma_device->ch, (uint32_t)args); + break; + + case DMA_CHANNEL_GET_STATUS /* constant-expression */: + return DMA_Channel_Is_Busy(dma_device->ch); + + case DMA_CHANNEL_START /* constant-expression */: + DMA_Channel_Enable(dma_device->ch); + break; + + case DMA_CHANNEL_STOP /* constant-expression */: + DMA_Channel_Disable(dma_device->ch); + break; + + default: + break; + } + + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int dma_close(struct device *dev) +{ + DMA_Disable(); + return 0; +} + +int dma_register(enum dma_index_type index, const char *name) +{ + struct device *dev; + + if (DMA_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(dmax_device[index].parent); + + dev->open = dma_open; + dev->close = dma_close; + dev->control = dma_control; + // dev->write = dma_write; + // dev->read = dma_read; + + dev->status = DEVICE_UNREGISTER; + dev->type = DEVICE_CLASS_DMA; + dev->handle = NULL; + + return device_register(dev, name); +} + +static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index) +{ + struct device *dev; + dlist_t *node; + uint8_t dma_index = 0; + uint32_t dma_handle[DMA_MAX_INDEX]; + + for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) { + dma_handle[dma_index] = 0xff; + } + + /* get registered dma handle list*/ + dlist_for_each(node, device_get_list_header()) + { + dev = dlist_entry(node, struct device, list); + + if (dev->type == DEVICE_CLASS_DMA) { + dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET; + } + } + + for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) { + if (dma_handle[dma_index] == 0xff) { + *allocate_index = dma_index; + return SUCCESS; + } + } + + return ERROR; +} + +int dma_allocate_register(const char *name) +{ + struct device *dev; + uint8_t index; + + if (DMA_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + if (dma_scan_unregister_device(&index) == ERROR) { + return -DEVICE_ENOSPACE; + } + + dev = &(dmax_device[index].parent); + + dev->open = dma_open; + dev->close = dma_close; + dev->control = dma_control; + // dev->write = dma_write; + // dev->read = dma_read; + + dev->type = DEVICE_CLASS_DMA; + dev->handle = NULL; + + return device_register(dev, name); +} + +/** + * @brief + * + * @param dev + * @param src_addr + * @param dst_addr + * @param transfer_size + * @return int + */ +int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size) +{ + uint32_t malloc_count; + uint32_t remain_len; + uint32_t actual_transfer_len = 0; + uint32_t actual_transfer_offset = 0; + + dma_device_t *dma_device = (dma_device_t *)dev; + + DMA_Channel_Disable(dma_device->ch); + + if (dma_device->direction == DMA_MEMORY_TO_MEMORY) { + dma_ctrl_cfg.bits.SI = 1; + dma_ctrl_cfg.bits.DI = 1; + } else if (dma_device->direction == DMA_MEMORY_TO_PERIPH) { + dma_ctrl_cfg.bits.SI = 1; + dma_ctrl_cfg.bits.DI = 0; + } else if (dma_device->direction == DMA_PERIPH_TO_MEMORY) { + dma_ctrl_cfg.bits.SI = 0; + dma_ctrl_cfg.bits.DI = 1; + } else if (dma_device->direction == DMA_PERIPH_TO_PERIPH) { + dma_ctrl_cfg.bits.SI = 0; + dma_ctrl_cfg.bits.DI = 0; + } + + dma_ctrl_cfg.bits.SBSize = dma_device->src_burst_size; + dma_ctrl_cfg.bits.DBSize = dma_device->dst_burst_size; + dma_ctrl_cfg.bits.SWidth = dma_device->src_width; + dma_ctrl_cfg.bits.DWidth = dma_device->dst_width; + + if (dma_device->src_width == DMA_TRANSFER_WIDTH_8BIT) { + actual_transfer_offset = 4095; + actual_transfer_len = transfer_size; + } else if (dma_device->src_width == DMA_TRANSFER_WIDTH_16BIT) { + if (transfer_size % 2) { + return -1; + } + + actual_transfer_offset = (4095 * 2); + actual_transfer_len = transfer_size / 2; + } else if (dma_device->src_width == DMA_TRANSFER_WIDTH_32BIT) { + if (transfer_size % 4) { + return -1; + } + + actual_transfer_offset = (4095 * 4); + actual_transfer_len = transfer_size / 4; + } + + malloc_count = actual_transfer_len / 4095; + remain_len = actual_transfer_len % 4095; + + if (remain_len) { + malloc_count++; + } + + if (dma_device->lli_cfg) { + free(dma_device->lli_cfg); + dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count); + } else { + dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count); + } + + if (dma_device->lli_cfg) { + /*transfer_size will be 4095 or 4095*2 or 4095*4 in different transfer width*/ + if ((!remain_len) && (malloc_count == 1)) { + dma_device->lli_cfg[0].src_addr = src_addr; + dma_device->lli_cfg[0].dst_addr = dst_addr; + dma_device->lli_cfg[0].nextlli = 0; + dma_ctrl_cfg.bits.TransferSize = remain_len; + dma_ctrl_cfg.bits.I = 1; + memcpy(&dma_device->lli_cfg[0].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + /*transfer_size will be 4095*n or 4095*2*n or 4095*4*n,(n>1) in different transfer width*/ + else if ((!remain_len) && (malloc_count > 1)) { + for (uint32_t i = 0; i < malloc_count; i++) { + dma_device->lli_cfg[i].src_addr = src_addr; + dma_device->lli_cfg[i].dst_addr = dst_addr; + dma_device->lli_cfg[i].nextlli = 0; + + dma_ctrl_cfg.bits.TransferSize = 4095; + dma_ctrl_cfg.bits.I = 0; + + if (dma_ctrl_cfg.bits.SI) { + src_addr += actual_transfer_offset; + } + + if (dma_ctrl_cfg.bits.DI) { + dst_addr += actual_transfer_offset; + } + + if (i == malloc_count - 1) { + dma_ctrl_cfg.bits.I = 1; + + if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) { + dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0]; + } + } + + if (i) { + dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i]; + } + + memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + } else { + for (uint32_t i = 0; i < malloc_count; i++) { + dma_device->lli_cfg[i].src_addr = src_addr; + dma_device->lli_cfg[i].dst_addr = dst_addr; + dma_device->lli_cfg[i].nextlli = 0; + + dma_ctrl_cfg.bits.TransferSize = 4095; + dma_ctrl_cfg.bits.I = 0; + + if (dma_ctrl_cfg.bits.SI) { + src_addr += actual_transfer_offset; + } + + if (dma_ctrl_cfg.bits.DI) { + dst_addr += actual_transfer_offset; + } + + if (i == malloc_count - 1) { + dma_ctrl_cfg.bits.TransferSize = remain_len; + dma_ctrl_cfg.bits.I = 1; + + if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) { + dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0]; + } + } + + if (i) { + dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i]; + } + + memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + } + + DMA_LLI_Update(dma_device->ch, (uint32_t)dma_device->lli_cfg); + } else { + return -2; + } + + return 0; +} +/** + * @brief + * + * @param handle + */ +void dma_isr(dma_device_t *handle) +{ + uint32_t tmpVal; + uint32_t intClr; + + /* Get DMA register */ + if (handle->id == 0) { + uint32_t DMAChs = DMA_BASE; + + for (uint8_t i = 0; i < DMA_CH_MAX; i++) { + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); + + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle[i].ch)) != 0) { + /* Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); + intClr |= (1 << handle[i].ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); + BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); + + if (handle[i].parent.callback) { + handle[i].parent.callback(&handle[i].parent, NULL, 0, DMA_INT_TCOMPLETED); + } + } + } + + for (uint8_t i = 0; i < DMA_CH_MAX; i++) { + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); + + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle[i].ch)) != 0) { + /*Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); + intClr |= (1 << handle[i].ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); + BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); + + if (handle[i].parent.callback) { + handle[i].parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR); + } + } + } + } else { + } +} +/** + * @brief + * + */ +void DMA0_IRQ(void) +{ + dma_isr(&dmax_device[0]); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_flash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..a3cdde60411fc5fe4a5b4170ffcd469555237dd0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_flash.c @@ -0,0 +1,291 @@ +/** + * @file hal_flash.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl602_glb.h" +#include "bl602_xip_sflash.h" +#include "bl602_xip_sflash_ext.h" +#include "bl602_sf_cfg.h" +#include "bl602_sf_cfg_ext.h" +#include "hal_flash.h" + +static SPI_Flash_Cfg_Type g_flash_cfg; + +/** + * @brief flash_get_cfg + * + * @return BL_Err_Type + */ +BL_Err_Type flash_get_cfg(uint8_t **cfg_addr,uint32_t *len) +{ + *cfg_addr = (uint8_t *)&g_flash_cfg; + *len = sizeof(SPI_Flash_Cfg_Type); + + return SUCCESS; +} + +/** + * @brief flash_set_qspi_enable + * + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) +{ + if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { + SFlash_Qspi_Enable(p_flash_cfg); + } + + return SUCCESS; +} + +/** + * @brief flash_set_l1c_wrap + * + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) +{ + if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) { + L1C_Set_Wrap(DISABLE); + } else { + L1C_Set_Wrap(ENABLE); + if((p_flash_cfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (p_flash_cfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) { + SFlash_SetBurstWrap(p_flash_cfg); + } + } + + return SUCCESS; +} + +/** + * @brief flash_config_init + * + * @return BL_Err_Type + */ +static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) +{ + BL_Err_Type ret = ERROR; + uint8_t isAesEnable = 0; + uint32_t jid = 0; + uint32_t offset = 0; + + __disable_irq(); + XIP_SFlash_Opt_Enter(&isAesEnable); + XIP_SFlash_State_Save(p_flash_cfg, &offset); + SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid); + arch_memcpy(jedec_id, (uint8_t *)&jid, 3); + jid &= 0xFFFFFF; + ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg); + if (ret == SUCCESS) { + p_flash_cfg->mid = (jid&0xff); + } + + /* Set flash controler from p_flash_cfg */ + flash_set_qspi_enable(p_flash_cfg); + flash_set_l1c_wrap(p_flash_cfg); + XIP_SFlash_State_Restore_Ext(p_flash_cfg, offset); + XIP_SFlash_Opt_Exit(isAesEnable); + __enable_irq(); + + return ret; +} + +/** + * @brief multi flash adapter + * + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_init(void) +{ + BL_Err_Type ret = ERROR; + uint8_t clkDelay = 1; + uint8_t clkInvert = 1; + uint32_t jedec_id = 0; + + __disable_irq(); + SFlash_Cache_Flush(); + SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg); + SFlash_Cache_Flush(); + __enable_irq(); + if (g_flash_cfg.mid != 0xff) { + return SUCCESS; + } + clkDelay = g_flash_cfg.clkDelay; + clkInvert = g_flash_cfg.clkInvert; + g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f; + + ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); + MSG("flash ID = %08x\r\n", jedec_id); + bflb_platform_dump((uint8_t *)&g_flash_cfg, sizeof(g_flash_cfg)); + if (ret != SUCCESS) { + MSG("flash config init fail!\r\n"); + } + g_flash_cfg.clkDelay = clkDelay; + g_flash_cfg.clkInvert = clkInvert; + + return ret; +} + +/** + * @brief read jedec id + * + * @param data + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data) +{ + uint8_t isAesEnable = 0; + uint32_t jid = 0; + + __disable_irq(); + XIP_SFlash_Opt_Enter(&isAesEnable); + XIP_SFlash_GetJedecId_Need_Lock_Ext(&g_flash_cfg /*, g_flash_cfg.ioMode & 0x0f*/, (uint8_t *)&jid); + XIP_SFlash_Opt_Exit(isAesEnable); + __enable_irq(); + jid &= 0xFFFFFF; + arch_memcpy(data, (void *)&jid, 4); + + return SUCCESS; +} + +/** + * @brief read flash data via xip + * + * @param addr + * @param data + * @param len + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len) +{ + __disable_irq(); + SFlash_Cache_Flush(); + XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len); + SFlash_Cache_Flush(); + __enable_irq(); + + return SUCCESS; +} + +/** + * @brief flash read data + * + * @param addr + * @param data + * @param len + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t len) +{ + BL_Err_Type ret = ERROR; + uint8_t isAesEnable = 0; + + XIP_SFlash_Opt_Enter(&isAesEnable); + ret = XIP_SFlash_Read_With_Lock_Ext(&g_flash_cfg, addr, data, len); + XIP_SFlash_Opt_Exit(isAesEnable); + + return ret; +} + +/** + * @brief flash write data + * + * @param addr + * @param data + * @param len + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t len) +{ + BL_Err_Type ret = ERROR; + uint8_t isAesEnable = 0; + + XIP_SFlash_Opt_Enter(&isAesEnable); + ret = XIP_SFlash_Write_With_Lock_Ext(&g_flash_cfg, addr, data, len); + XIP_SFlash_Opt_Exit(isAesEnable); + + return ret; +} + +/** + * @brief flash erase + * + * @param startaddr + * @param endaddr + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len) +{ + BL_Err_Type ret = ERROR; + uint8_t isAesEnable = 0; + + XIP_SFlash_Opt_Enter(&isAesEnable); + ret = XIP_SFlash_Erase_With_Lock_Ext(&g_flash_cfg, startaddr, len); + XIP_SFlash_Opt_Exit(isAesEnable); + + return ret; +} + +/** + * @brief set flash cache + * + * @param cont_read + * @param cache_enable + * @param cache_way_disable + * @param flash_offset + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) +{ + uint8_t isAesEnable = 0; + uint32_t tmp[1]; + BL_Err_Type stat; + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + + XIP_SFlash_Opt_Enter(&isAesEnable); + /* To make it simple, exit cont read anyway */ + SFlash_Reset_Continue_Read(&g_flash_cfg); + + if (g_flash_cfg.cReadSupport == 0) { + cont_read = 0; + } + + if (cont_read == 1) { + stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); + + if (SUCCESS != stat) { + XIP_SFlash_Opt_Exit(isAesEnable); + return ERROR; + } + } + + /* Set default value */ + SFlash_Cache_Enable_Set(0xf); + + if (cache_enable) { + SF_Ctrl_Set_Flash_Image_Offset(flash_offset); + SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable); + } + XIP_SFlash_Opt_Exit(isAesEnable); + + return SUCCESS; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_gpio.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..8d22222450049f272c29afb31efd6062fa91ab0a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_gpio.c @@ -0,0 +1,195 @@ +/** + * ***************************************************************************** + * @file hal_gpio.c + * @version 0.1 + * @date 2021-03-01 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#include "bl602_glb.h" +#include "bl602_gpio.h" +#include "hal_gpio.h" + +/** + * @brief + * + * @param pin + * @param mode + */ +void gpio_set_mode(uint32_t pin, uint32_t mode) +{ + GLB_GPIO_Cfg_Type gpio_cfg; + + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioPin = pin; + gpio_cfg.drive = 0; + gpio_cfg.smtCtrl = 1; + + switch (mode) { + case GPIO_OUTPUT_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_NONE; + break; + + case GPIO_OUTPUT_PP_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_UP; + break; + + case GPIO_OUTPUT_PD_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_DOWN; + break; + + case GPIO_INPUT_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_NONE; + break; + + case GPIO_INPUT_PP_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_UP; + break; + + case GPIO_INPUT_PD_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_DOWN; + break; + + default: + CPU_Interrupt_Disable(GPIO_INT0_IRQn); + GLB_GPIO_IntMask(pin, MASK); + + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + + GLB_GPIO_INT0_IRQHandler_Install(); + + if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE); + } + + else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE); + } + + else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL); + } + + else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL); + } + + else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_PULSE); + } + + else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_PULSE); + } + + else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_LEVEL); + } + + else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL); + } + + else { + return; + } + + CPU_Interrupt_Enable(GPIO_INT0_IRQn); + break; + } + + GLB_GPIO_Init(&gpio_cfg); +} +/** + * @brief + * + * @param pin + * @param value + */ +void gpio_write(uint32_t pin, uint32_t value) +{ + GLB_GPIO_Write(pin, value); +} +/** + * @brief + * + * @param pin + */ +void gpio_toggle(uint32_t pin) +{ +} +/** + * @brief + * + * @param pin + * @return int + */ +int gpio_read(uint32_t pin) +{ + return GLB_GPIO_Read(pin); +} +/** + * @brief + * + * @param pin + * @param cbFun + */ +void gpio_attach_irq(uint32_t pin, void (*cbFun)(void)) +{ + GLB_GPIO_INT0_Callback_Install(pin, cbFun); +} +/** + * @brief + * + * @param pin + * @param enabled + */ +void gpio_irq_enable(uint32_t pin, uint8_t enabled) +{ + if (enabled) { + GLB_GPIO_IntMask(pin, UNMASK); + } else { + GLB_GPIO_IntMask(pin, MASK); + } +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_mtimer.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_mtimer.c new file mode 100644 index 0000000000000000000000000000000000000000..c8c2c2b6be6b9b15060ab92c9fff210c6ea8ce5c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_mtimer.c @@ -0,0 +1,142 @@ +/** + * @file hal_mtimer.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_mtimer.h" +#include "bl602_glb.h" + +static void (*systick_callback)(void); +static uint64_t next_compare_tick = 0; +static uint64_t current_set_ticks = 0; + +static void Systick_Handler(void) +{ + *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick; + systick_callback(); + next_compare_tick += current_set_ticks; +} + +/** + * @brief + * + * @param time + * @param interruptFun + */ +void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)) +{ + CPU_Interrupt_Disable(MTIME_IRQn); + + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t *const pulTimeHigh = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); + volatile uint32_t *const pulTimeLow = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME); + volatile uint32_t ulHartId = 0; + + current_set_ticks = ticks; + systick_callback = interruptfun; + + __asm volatile("csrr %0, mhartid" + : "=r"(ulHartId)); + + do { + ulCurrentTimeHigh = *pulTimeHigh; + ulCurrentTimeLow = *pulTimeLow; + } while (ulCurrentTimeHigh != *pulTimeHigh); + + next_compare_tick = (uint64_t)ulCurrentTimeHigh; + next_compare_tick <<= 32ULL; + next_compare_tick |= (uint64_t)ulCurrentTimeLow; + next_compare_tick += (uint64_t)current_set_ticks; + + *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick; + + /* Prepare the time to use after the next tick interrupt. */ + next_compare_tick += (uint64_t)current_set_ticks; + + Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler); + CPU_Interrupt_Enable(MTIME_IRQn); +} + +/** + * @brief + * + * @return uint64_t + */ +uint64_t mtimer_get_time_ms() +{ + return mtimer_get_time_us() / 1000; +} +/** + * @brief + * + * @return uint64_t + */ +uint64_t mtimer_get_time_us() +{ + uint32_t tmpValLow, tmpValHigh, tmpValHigh1; + + do { + tmpValLow = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME); + tmpValHigh = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); + tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); + } while (tmpValHigh != tmpValHigh1); + + return (((uint64_t)tmpValHigh << 32) + tmpValLow); +} +/** + * @brief + * + * @param time + */ +void mtimer_delay_ms(uint32_t time) +{ + uint64_t cnt = 0; + uint32_t clock = SystemCoreClockGet(); + uint64_t startTime = mtimer_get_time_ms(); + + while (mtimer_get_time_ms() - startTime < time) { + cnt++; + + /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/ + if (cnt > (time * (clock >> (10 + 5))) * 2) { + break; + } + } +} +/** + * @brief + * + * @param time + */ +void mtimer_delay_us(uint32_t time) +{ + uint64_t cnt = 0; + uint32_t clock = SystemCoreClockGet(); + uint64_t startTime = mtimer_get_time_us(); + + while (mtimer_get_time_us() - startTime < time) { + cnt++; + + /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/ + if (cnt > (time * (clock >> (10 + 5))) * 2) { + break; + } + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_sec_ecdsa.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_sec_ecdsa.c new file mode 100644 index 0000000000000000000000000000000000000000..5708004808e8a87baec13307b99606f3b824b8a6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_sec_ecdsa.c @@ -0,0 +1,1248 @@ +#include "hal_sec_ecdsa.h" +#include "bl602_sec_eng.h" + +#define ECP_SECP256R1_REG_TYPE SEC_ENG_PKA_REG_SIZE_32 +#define ECP_SECP256R1_N_REG_INDEX 0 +#define ECP_SECP256R1_NPRIME_N_REG_INDEX 1 +#define ECP_SECP256R1_INVR_N_REG_INDEX 2 +#define ECP_SECP256R1_NPRIME_P_REG_INDEX 3 +#define ECP_SECP256R1_INVR_P_REG_INDEX 4 +#define ECP_SECP256R1_SIZE 32 +/* Used in verify */ +#define ECP_SECP256R1_S_REG_INDEX 5 +#define ECP_SECP256R1_BAR_S_REG_INDEX 6 +#define ECP_SECP256R1_HASH_REG_INDEX 6 //use ECP_SECP256R1_BAR_S_REG_INDEX since it's temp +#define ECP_SECP256R1_U1_REG_INDEX 7 +#define ECP_SECP256R1_LT_REG_TYPE SEC_ENG_PKA_REG_SIZE_64 +#define ECP_SECP256R1_LT_REG_INDEX 7 +#define ECP_SECP256R1_SLT_REG_TYPE SEC_ENG_PKA_REG_SIZE_128 +#define ECP_SECP256R1_SLT_REG_INDEX 3 + +//#define ECDSA_DBG 1 +//#define ECDSA_DBG_DETAIL 1 +void bflb_platform_dump(uint8_t *data, uint32_t len); + +#if (defined(ECDSA_DBG) || defined(ECDSA_DBG_DETAIL)) +uint32_t pka_tmp[32] = { 0 }; +#endif + +const uint8_t secp256r1P[32] ALIGN4 = { + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +}; +const uint8_t secp256r1B[32] ALIGN4 = { + 0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86, 0xbc, + 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2, 0x60, 0x4b +}; +const uint8_t secp256r1Gx[32] ALIGN4 = { + 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2, + 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96 +}; +const uint8_t secp256r1Gy[32] ALIGN4 = { + 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, + 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5 +}; +const uint8_t secp256r1N[32] ALIGN4 = { + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51 +}; +const uint8_t secp256r1PrimeN_N[32] ALIGN4 = { + 0x60, 0xd0, 0x66, 0x33, 0xa9, 0xd6, 0x28, 0x1c, 0x50, 0xfe, 0x77, 0xec, 0xc5, 0x88, 0xc6, 0xf6, + 0x48, 0xc9, 0x44, 0x08, 0x7d, 0x74, 0xd2, 0xe4, 0xcc, 0xd1, 0xc8, 0xaa, 0xee, 0x00, 0xbc, 0x4f +}; +const uint8_t secp256r1InvR_N[32] ALIGN4 = { + 0x60, 0xd0, 0x66, 0x33, 0x49, 0x05, 0xc1, 0xe9, 0x07, 0xf8, 0xb6, 0x04, 0x1e, 0x60, 0x77, 0x25, + 0xba, 0xde, 0xf3, 0xe2, 0x43, 0x56, 0x6f, 0xaf, 0xce, 0x1b, 0xc8, 0xf7, 0x9c, 0x19, 0x7c, 0x79 +}; +const uint8_t secp256r1PrimeN_P[32] ALIGN4 = { + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; +const uint8_t secp256r1InvR_P[32] ALIGN4 = { + 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x02, + 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 +}; +const uint8_t secp256r1_1[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; +const uint8_t secp256r1_BAR2[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 +}; +const uint8_t secp256r1_BAR3[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x02, 0xff, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 +}; +const uint8_t secp256r1_BAR4[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04 +}; +const uint8_t secp256r1_BAR8[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08 +}; +const uint8_t secp256r1_1P1[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 +}; +const uint8_t secp256r1_1M1[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +const uint8_t secp256r1_Zerox[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +const uint8_t secp256r1_Zeroy[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; +const uint8_t secp256r1_Gx[32] ALIGN4 = { + 0x18, 0x90, 0x5f, 0x76, 0xa5, 0x37, 0x55, 0xc6, 0x79, 0xfb, 0x73, 0x2b, 0x77, 0x62, 0x25, 0x10, + 0x75, 0xba, 0x95, 0xfc, 0x5f, 0xed, 0xb6, 0x01, 0x79, 0xe7, 0x30, 0xd4, 0x18, 0xa9, 0x14, 0x3c +}; +const uint8_t secp256r1_Gy[32] ALIGN4 = { + 0x85, 0x71, 0xff, 0x18, 0x25, 0x88, 0x5d, 0x85, 0xd2, 0xe8, 0x86, 0x88, 0xdd, 0x21, 0xf3, 0x25, + 0x8b, 0x4a, 0xb8, 0xe4, 0xba, 0x19, 0xe4, 0x5c, 0xdd, 0xf2, 0x53, 0x57, 0xce, 0x95, 0x56, 0x0a +}; + +static int sec_ecc_basic_parameter_init(uint8_t id) +{ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_NPRIME_N_REG_INDEX, (uint32_t *)secp256r1PrimeN_N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, (uint32_t *)secp256r1InvR_N, ECP_SECP256R1_SIZE / 4, 0); + + return 0; +} + +static int sec_ecc_point_mul_init(uint8_t id) +{ + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 1, (uint32_t *)secp256r1PrimeN_P, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 9, (uint32_t *)secp256r1_BAR2, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 10, (uint32_t *)secp256r1_BAR3, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 11, (uint32_t *)secp256r1_BAR4, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 12, (uint32_t *)secp256r1_BAR8, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 19, (uint32_t *)secp256r1_1P1, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 20, (uint32_t *)secp256r1_1M1, ECP_SECP256R1_SIZE / 4, 0); + + return 0; +} + +static void sec_ecdsa_point_add_inf_check(uint8_t *pka_p1_eq_inf, uint8_t *pka_p2_eq_inf) +{ + uint8_t res[4]; + + /* index 2:BAR_Zero_x + * index 3:BAR_Zero_y + * index 4:BAR_Zero_z + * index 5:BAR_G_x + * index 6:BAR_G_y + * index 7:BAR_G_z + * index 8:1 + * index 9:2 + * index 10:3 + * index 11:4 + * index 12:8 + * index 19:1P1 + * index 20:1m1*/ + + //cout = 1 if X1 = 0 + Sec_Eng_PKA_LCMP(res, 3, 2, 3, 8); //s0 < s1 => cout = 1 + //cout = 1 if Y1 < Bar_1p1 + Sec_Eng_PKA_LCMP(res + 1, 3, 3, 3, 19); + //cout=1 if Y1 > Bar_1m1 + Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 3); + //cout =1 if Z1 = 0 + Sec_Eng_PKA_LCMP(res + 3, 3, 4, 3, 8); + *pka_p1_eq_inf = res[0] & res[1] & res[2] & res[3]; + + //cout = 1 if X2 = 0 + Sec_Eng_PKA_LCMP(res, 3, 5, 3, 8); + // cout = 1 if Y2 < Bar_1p1 + Sec_Eng_PKA_LCMP(res + 1, 3, 6, 3, 19); + //cout = 1 if Y2 > Bar_1m1 + Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 6); + //cout = 1 if Z2 = 0 + Sec_Eng_PKA_LCMP(res + 3, 3, 7, 3, 8); + *pka_p2_eq_inf = res[0] & res[1] & res[2] & res[3]; +} + +static void sec_ecdsa_copy_x2_to_x1(uint8_t id) +{ + //X2->X1 + Sec_Eng_PKA_Move_Data(3, 2, 3, 5, 0); + //Y2->Y1 + Sec_Eng_PKA_Move_Data(3, 3, 3, 6, 0); + //Z2->Z1 + Sec_Eng_PKA_Move_Data(3, 4, 3, 7, 1); //Caution!!! wait movdat ready to execute next command +} + +static void sec_ecdsa_point_add(uint8_t id) +{ + /* index 2:BAR_Zero_x + * index 3:BAR_Zero_y + * index 4:BAR_Zero_z + * index 5:BAR_G_x + * index 6:BAR_G_y + * index 7:BAR_G_z + * index 8:1 + * index 9:2 + * index 10:3 + * index 11:4 + * index 12:8 + * index 19:1P1 + * index 20:1m1*/ + + //U1 = Y2*Z1 + //PKA_MMUL(0,3,13,3, 6,3, 4,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx + Sec_Eng_PKA_MMUL(3, 13, 3, 6, 3, 4, 3, 0, 0); + + //U2 = Y1*Z2 + //PKA_MMUL(0,3,14,3, 3,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 14, 3, 3, 3, 7, 3, 0, 0); + + //V1 = X2*Z1 + //PKA_MMUL(0,3,15,3, 5,3, 4,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 4, 3, 0, 0); + + //V2 = X1*Z2 + //PKA_MMUL(0,3,16,3, 2,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 16, 3, 2, 3, 7, 3, 0, 0); + + //U = U1-U2 + //PKA_MSUB(0,3,13,3,13,3,14,3,0); + Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0); + + //V = V1-V2 + //PKA_MSUB(0,3,15,3,15,3,16,3,0); + Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 16, 3, 0, 0); + + //W = Z1*Z2 + //PKA_MMUL(0,3, 2,3, 4,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 2, 3, 4, 3, 7, 3, 0, 0); + + //V^2 + //PKA_MMUL(0,3, 3,3,15,3,15,3,0); + Sec_Eng_PKA_MMUL(3, 3, 3, 15, 3, 15, 3, 0, 0); + + //V^3 + //PKA_MMUL(0,3, 4,3, 3,3,15,3,0); + Sec_Eng_PKA_MMUL(3, 4, 3, 3, 3, 15, 3, 0, 0); + + //U^2 + //PKA_MMUL(0,3,17,3,13,3,13,3,0); + Sec_Eng_PKA_MMUL(3, 17, 3, 13, 3, 13, 3, 0, 0); + + //U^2*W + //PKA_MMUL(0,3,17,3,17,3, 2,3,0); + Sec_Eng_PKA_MMUL(3, 17, 3, 17, 3, 2, 3, 0, 0); + + //U^2*W-V^3 + //PKA_MSUB(0,3,17,3,17,3, 4,3,0); + Sec_Eng_PKA_MSUB(3, 17, 3, 17, 3, 4, 3, 0, 0); + + //2*V^2 + //PKA_MMUL(0,3,18,3, 9,3, 3,3,0); + Sec_Eng_PKA_MMUL(3, 18, 3, 9, 3, 3, 3, 0, 0); + + //2*V^2*V2 + //PKA_MMUL(0,3,18,3,18,3,16,3,0); + Sec_Eng_PKA_MMUL(3, 18, 3, 18, 3, 16, 3, 0, 0); + + //A = U^2*W-V^3-2*V^2*V2 + //PKA_MSUB(0,3,18,3,17,3,18,3,0); + Sec_Eng_PKA_MSUB(3, 18, 3, 17, 3, 18, 3, 0, 0); + + //V^2*V2 + //PKA_MMUL(0,3, 3,3, 3,3,16,3,0); + Sec_Eng_PKA_MMUL(3, 3, 3, 3, 3, 16, 3, 0, 0); + + //V^3*U2 + //PKA_MMUL(0,3,14,3, 4,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 14, 3, 4, 3, 14, 3, 0, 0); + + //Z3 = V^3*W + //PKA_MMUL(0,3, 4,3, 4,3, 2,3,0); + Sec_Eng_PKA_MMUL(3, 4, 3, 4, 3, 2, 3, 0, 0); + + //X3 = V*A + //PKA_MMUL(0,3, 2,3,15,3,18,3,0); + Sec_Eng_PKA_MMUL(3, 2, 3, 15, 3, 18, 3, 0, 0); + + //V^2*V2-A + //PKA_MSUB(0,3, 3,3, 3,3,18,3,0); + Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 18, 3, 0, 0); + + //U*(V^2*V2-A) + //PKA_MMUL(0,3, 3,3,13,3, 3,3,0); + Sec_Eng_PKA_MMUL(3, 3, 3, 13, 3, 3, 3, 0, 0); + + //Y3 = U*(V^2*V2-A)-V^3*U2 + //PKA_MSUB(1,3, 3,3, 3,3,14,3,0); + Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 14, 3, 0, 1); +} + +static void sec_ecdsa_point_double(uint8_t id) +{ + /* index 2:BAR_Zero_x + * index 3:BAR_Zero_y + * index 4:BAR_Zero_z + * index 5:BAR_G_x + * index 6:BAR_G_y + * index 7:BAR_G_z + * index 8:1 + * index 9:2 + * index 10:3 + * index 11:4 + * index 12:8 + * index 19:1P1 + * index 20:1m1*/ + + //X1^2 + //PKA_MMUL(0,3,13,3, 5,3, 5,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx + Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0); + + //Z1^2 + //PKA_MMUL(0,3,14,3, 7,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 14, 3, 7, 3, 7, 3, 0, 0); + + //X1^2-Z1^2 + //PKA_MSUB(0,3,13,3,13,3,14,3,0); + Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0); + + //W = 3*(X1^2-Z1^2) + //PKA_MMUL(0,3,13,3,10,3,13,3,0); + Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0); + + //S = Y1*Z1 + //PKA_MMUL(0,3,14,3, 6,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 14, 3, 6, 3, 7, 3, 0, 0); + + //X1*Y1 + //PKA_MMUL(0,3,15,3, 5,3, 6,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 6, 3, 0, 0); + + //W^2 + //PKA_MMUL(0,3, 7,3,13,3,13,3,0); + Sec_Eng_PKA_MMUL(3, 7, 3, 13, 3, 13, 3, 0, 0); + + //B = X1*Y1*S + //PKA_MMUL(0,3,15,3,15,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 14, 3, 0, 0); + + //8*B + //PKA_MMUL(0,3, 5,3,12,3,15,3,0); + Sec_Eng_PKA_MMUL(3, 5, 3, 12, 3, 15, 3, 0, 0); + + //H = W^2-8*B + //PKA_MSUB(0,3, 7,3, 7,3, 5,3,0); + Sec_Eng_PKA_MSUB(3, 7, 3, 7, 3, 5, 3, 0, 0); + + //2*H + //PKA_MMUL(0,3, 5,3, 9,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 5, 3, 9, 3, 7, 3, 0, 0); + + //X2 = 2*H*S + //PKA_MMUL(0,3, 5,3, 5,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 5, 3, 5, 3, 14, 3, 0, 0); + + //4*B + //PKA_MMUL(0,3,15,3,11,3,15,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 11, 3, 15, 3, 0, 0); + + //S^2 + //PKA_MMUL(0,3,16,3,14,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 16, 3, 14, 3, 14, 3, 0, 0); + + //4*B-H + //PKA_MSUB(0,3,15,3,15,3, 7,3,0); + Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 7, 3, 0, 0); + + //Y1^2 + //PKA_MMUL(0,3, 6,3, 6,3, 6,3,0); + Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 6, 3, 0, 0); + + //W*(4*B-H) + //PKA_MMUL(0,3,15,3,15,3,13,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 13, 3, 0, 0); + + //8*Y1^2 + //PKA_MMUL(0,3, 6,3,12,3, 6,3,0); + Sec_Eng_PKA_MMUL(3, 6, 3, 12, 3, 6, 3, 0, 0); + + //8*Y1^2*S^2 + //PKA_MMUL(0,3, 6,3, 6,3,16,3,0); + Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 16, 3, 0, 0); + + //Y2 = W*(4*B-H)-8*Y1^2*S^2 + //PKA_MSUB(0,3, 6,3,15,3, 6,3,0); + Sec_Eng_PKA_MSUB(3, 6, 3, 15, 3, 6, 3, 0, 0); + + //S^3 + //PKA_MMUL(0,3, 7,3,14,3,16,3,0); + Sec_Eng_PKA_MMUL(3, 7, 3, 14, 3, 16, 3, 0, 0); + + //Z2 = 8*S^3 + //PKA_MMUL(1,3, 7,3,12,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 7, 3, 12, 3, 7, 3, 0, 1); +} +#ifdef ECDSA_DBG_DETAIL +static void sec_ecdsa_dump_temp_result() +{ + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("2=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("3=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("4=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("5=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("6=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 7, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("7=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +} +#endif +static int sec_ecdsa_verify_point_mul(uint8_t id, const uint32_t *m) +{ + uint32_t i, j, k; + uint32_t tmp; + uint32_t isOne = 0; + uint8_t *p = (uint8_t *)m; + uint8_t pka_p1_eq_inf, pka_p2_eq_inf; + + /* Remove zeros bytes*/ + k = 0; + + while (p[k] == 0 && k < 31) { + k++; + } + + i = 31; + + for (; i >= k; i--) { + tmp = p[i]; + j = 0; + + for (j = 0; j < 8; j++) { + isOne = tmp & (1 << j); + + if (isOne) { + sec_ecdsa_point_add_inf_check(&pka_p1_eq_inf, &pka_p2_eq_inf); + + if (pka_p1_eq_inf == 1 && pka_p2_eq_inf == 0) { + //sum = X2 + sec_ecdsa_copy_x2_to_x1(id); +#ifdef ECDSA_DBG_DETAIL + MSG("sum = X2\r\n"); + sec_ecdsa_dump_temp_result(); +#endif + } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 1) { + //sum = X1 + MSG("sum = X1\r\n"); + } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 0) { + //sum = X1 + X2 + sec_ecdsa_point_add(id); +#ifdef ECDSA_DBG_DETAIL + MSG("sum = X1+X2\r\n"); + sec_ecdsa_dump_temp_result(); +#endif + } else { + MSG("Error! infinite point + infinite point\r\n"); + return -1; + } + } + + sec_ecdsa_point_double(id); +#ifdef ECDSA_DBG_DETAIL + sec_ecdsa_dump_temp_result(); +#endif + } + + if (i == 0) { + break; + } + } + + return 0; +} + +/*cal d*G if pkX(pky)==NULL + * cal d(bG) if pkX(pky)!=NULL */ +static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) +{ +#ifdef ECDSA_DBG + uint32_t pk_z[8]; +#endif + + /* Pointer check */ + if (private_key == NULL) { + return -1; + } + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + sec_ecc_basic_parameter_init(id); + + //Clear D[7] + //PKA_CREG(1,4, 7,0); + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); + + sec_ecc_point_mul_init(id); + + //X1 + //PKA_CTREG(3, 2,8,bar_Zero_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); + //Y1 + //PKA_CTREG(3, 3,8,bar_Zero_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); + //Z1 + //PKA_CTREG(3, 4,8,bar_Zero_z); + //PKA_MOVDAT(1,3, 4,3, 2); + Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); + + if (pkX == NULL) { + //X2 + //PKA_CTREG(3, 5,8,bar_G_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0); + //Y2 + //PKA_CTREG(3, 6,8,bar_G_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0); + } else { + /* chaneg peer's public key to mont domain*/ + //PUB_x + //PKA_CTREG(3, 5,8,PUB_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pkX, ECP_SECP256R1_SIZE / 4, 0); + //bar_pub_x + //PKA_GF2MONT(3, 5,3, 5); + /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("PK.x in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + //PUB_y + //PKA_CTREG(3, 6,8,PUB_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pkY, ECP_SECP256R1_SIZE / 4, 0); + //bar_pub_y + //PKA_GF2MONT(3, 6,3, 6); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("PK.y in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + } + + //Z2 + //PKA_CTREG(3, 7,8,bar_G_z); + //PKA_MOVDAT(1,3, 7,3, 3); + Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); + /* Clear temp register since it's used in point-mul*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); + + sec_ecdsa_verify_point_mul(id, private_key); + //get bar_u1_x + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_x\r\n"); + bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_y\r\n"); + bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); +#endif +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pk_z, ECP_SECP256R1_SIZE / 4); + MSG("bar_u1_z\r\n"); + bflb_platform_dump(pk_z, ECP_SECP256R1_SIZE); +#endif + + //get R.x + //R.z ^ -1 + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); + //inv_r + //PKA_CTREG(3, 6,8,inv_r); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); + //R.z ^ -1 + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + //PKA_MONT2GF(3, 5,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (Montgomery to GF) + //PKA_MONT2GF(3, 6,3, 2,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (GF to Affine domain) + //PKA_MONT2GF(3, 2,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.x=\r\n"); + bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 2, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.x%n=\r\n"); + bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); +#endif + + /*after %n,re write p*/ + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0); + //get R.y + //R.z ^ -1 + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); + //inv_r + //PKA_CTREG(3, 6,8,inv_r); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); + //R.z ^ -1 + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + //PKA_MONT2GF(3, 5,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + //R.x (Montgomery to GF) + //PKA_MONT2GF(3, 6,3, 2,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (GF to Affine domain) + //PKA_MONT2GF(3, 2,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.y=\r\n"); + bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 3, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.y%n=\r\n"); + bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); +#endif + return 0; +} + +static int32_t sec_ecc_is_zero(uint8_t *a, uint32_t len) +{ + uint32_t i = 0; + + for (i = 0; i < len; i++) { + if (a[i] != 0) { + return 0; + } + } + + return 1; +} + +static int32_t sec_ecc_cmp(uint8_t *a, uint8_t *b, uint32_t len) +{ + uint32_t i = 0, j = 0; + + for (i = 0; i < len; i++) { + if (a[i] != 0) { + break; + } + } + + for (j = 0; j < len; j++) { + if (b[j] != 0) { + break; + } + } + + if (i == len && j == len) { + return (0); + } + + if (i > j) { + return (-1); + } + + if (j > i) { + return (1); + } + + for (; i < len; i++) { + if (a[i] > b[i]) { + return (1); + } + + if (a[i] < b[i]) { + return (-1); + } + } + + return 0; +} + +int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id) +{ + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + handle->ecpId = id; + + return 0; +} + +int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle) +{ + Sec_Eng_PKA_Reset(); + + return 0; +} + +int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *r, const uint32_t *s) +{ + uint32_t bar_u1_x[8]; + uint32_t bar_u1_y[8]; + uint32_t bar_u1_z[8]; + uint32_t bar_u2_x[8]; + uint32_t bar_u2_y[8]; + uint32_t bar_u2_z[8]; + uint32_t pka_u1[8] = { 0 }; + uint32_t pka_u2[8] = { 0 }; + uint32_t i = 0; + + /* Pointer check */ + if (hash == NULL || handle->publicKeyx == NULL || handle->publicKeyy == NULL || r == NULL || s == NULL) { + return -1; + } + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + /*Step 0: make sure r and s are in range 1..n-1*/ + + /* r and s should not be 0*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0); + //cout = 1 if r = 0 + Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1 + + if (i == 1) { + return -1; + } + + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); + //cout = 1 if r = 0 + Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1 + + if (i == 1) { + return -1; + } + + sec_ecc_basic_parameter_init(handle->ecpId); + + /* r and s should not be 0*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); + //cout = 1 if r < N + Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); + + if (i != 1) { + return -1; + } + + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); + //cout = 1 if r < N + Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); + + if (i != 1) { + return -1; + } + + /* u1 = e / s mod n, u2 = r / s mod n + * R = u1 G + u2 Q*/ + + /* Step1: Get S^-1*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); + /* Change s to Mont domain */ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("GF2Mont Result of s:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + /* Get S^-1 in Mont domain */ + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("s^-1 in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + /* Change S^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store s^-1*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("S^-1:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + /* Step2: Get u1*/ + //u1=hash(e)*s^-1; + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u1, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("u1:\r\n"); + bflb_platform_dump(pka_u1, ECP_SECP256R1_SIZE); +#endif + + /* Step3: Get u2*/ + //u2=r*s^-1; + // use hash and u1 temp register + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u2, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("u2:\r\n"); + bflb_platform_dump(pka_u2, ECP_SECP256R1_SIZE); +#endif + + /* Step4: Get u1*G*/ + + //Clear D[7] + //PKA_CREG(1,4, 7,0); + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); + + sec_ecc_point_mul_init(handle->ecpId); + + //X1 + //PKA_CTREG(3, 2,8,bar_Zero_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); + //Y1 + //PKA_CTREG(3, 3,8,bar_Zero_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); + //Z1 + //PKA_CTREG(3, 4,8,bar_Zero_z); + //PKA_MOVDAT(1,3, 4,3, 2); + Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); + + //X2 + //PKA_CTREG(3, 5,8,bar_G_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0); + //Y2 + //PKA_CTREG(3, 6,8,bar_G_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0); + //Z2 + //PKA_CTREG(3, 7,8,bar_G_z); + //PKA_MOVDAT(1,3, 7,3, 3); + Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); + + sec_ecdsa_verify_point_mul(handle->ecpId, pka_u1); + //get bar_u1_x + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_x\r\n"); + bflb_platform_dump(bar_u1_x, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_y\r\n"); + bflb_platform_dump(bar_u1_y, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_z\r\n"); + bflb_platform_dump(bar_u1_z, ECP_SECP256R1_SIZE); +#endif + + /* Step4: Get u2*Q*/ + //X1 + //PKA_CTREG(3, 2,8,bar_Zero_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); + //Y1 + //PKA_CTREG(3, 3,8,bar_Zero_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); + //Z1 + //PKA_CTREG(3, 4,8,bar_Zero_z); + //PKA_MOVDAT(1,3, 4,3, 2); + Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); + + //PUB_x + //PKA_CTREG(3, 5,8,PUB_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)handle->publicKeyx, ECP_SECP256R1_SIZE / 4, 0); + //bar_pub_x + //PKA_GF2MONT(3, 5,3, 5); + /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("PK.x in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + //PUB_y + //PKA_CTREG(3, 6,8,PUB_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)handle->publicKeyy, ECP_SECP256R1_SIZE / 4, 0); + //bar_pub_y + //PKA_GF2MONT(3, 6,3, 6); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("PK.y in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + //bar_pub_z + //PKA_CTREG(3, 7,8,PUB_z); + //PKA_MOVDAT(1,3, 7,3, 3); + Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); + + /* Clear temp register since it's used in point-mul*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); + + sec_ecdsa_verify_point_mul(handle->ecpId, pka_u2); + //get bar_u1_x + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u2_x\r\n"); + bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u2_y, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u2_y\r\n"); + bflb_platform_dump(bar_u2_y, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u2_z, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u2_z\r\n"); + bflb_platform_dump(bar_u2_z, ECP_SECP256R1_SIZE); +#endif + + /* Step5: Get u1*G+u2*Q*/ + //move bar_u2_x + //PKA_MOVDAT(0,3, 5,3, 2); + Sec_Eng_PKA_Move_Data(3, 5, 3, 2, 0); + //move bar_u2_y + //PKA_MOVDAT(0,3, 6,3, 3); + Sec_Eng_PKA_Move_Data(3, 6, 3, 3, 0); + //move bar_u2_z + //PKA_MOVDAT(1,3, 7,3, 4); + Sec_Eng_PKA_Move_Data(3, 7, 3, 4, 1); + + //bar_u1_x + //PKA_CTREG(3, 2,8,bar_u1_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4, 0); + //bar_u1_y + //PKA_CTREG(3, 3,8,bar_u1_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4, 0); + //bar_u1_z + //PKA_CTREG(3, 4,8,bar_u1_z); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4, 0); + + //R = u1 * G + u2 * PUB + //PKA_POINT_ADDITION(); + sec_ecdsa_point_add(handle->ecpId); + + /* Step6 Get R.x(R=u1G+u2P)*/ + //R.z ^ -1 + //PKA_MINV(0,3, 5,3, 4,3, 0); + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); + //inv_r + //PKA_CTREG(3, 6,8,inv_r); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); + //R.z ^ -1 + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + //PKA_MONT2GF(3, 5,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (Montgomery to GF) + //PKA_MONT2GF(3, 6,3, 2,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (GF to Affine domain) + //PKA_MONT2GF(3, 2,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.x=\r\n"); + bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE); +#endif + + /* Step7 check R.x=r*/ + /* Check Result */ + for (i = 0; i < 8; i++) { + if (bar_u2_x[i] != r[i]) { + return -1; + } + } + +#ifdef ECDSA_DBG + MSG("Verify success\r\n"); +#endif + return 0; +} + +int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s) +{ + uint32_t k[8]; + uint32_t Rx[8]; + uint32_t Ry[8]; + uint32_t KInvert[8]; + uint32_t maxTry1 = 100; + + /* Pointer check */ + if (handle->privateKey == NULL || hash == NULL || r == NULL || s == NULL) { + return -1; + } + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + while (maxTry1--) { + /* step 1 ,get random k*/ + if (random_k == NULL) { + if (sec_ecc_get_random_value(k, (uint32_t *)secp256r1N, 32) < 0) { + return -1; + } + } else { + memcpy(k, random_k, 32); + } + +#ifdef ECDSA_DBG + MSG("Random k:\r\n"); + bflb_platform_dump(k, ECP_SECP256R1_SIZE); +#endif + + /*step 2, calc R=kG*/ + if (sec_ecdsa_get_public_key(handle, k, Rx, Ry) < 0) { + return -1; + } + + if (sec_ecc_is_zero((uint8_t *)Rx, 32)) { + continue; + } + + memcpy(r, Rx, 32); +#ifdef ECDSA_DBG + MSG("r:\r\n"); + bflb_platform_dump(r, ECP_SECP256R1_SIZE); +#endif + sec_ecc_basic_parameter_init(handle->ecpId); + /* step 3,get k^-1*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)k, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + /* Change k to Mont domain */ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("GF2Mont Result of k:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + /* Get k^-1 in Mont domain */ + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 5, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4); + MSG("k^-1 in Mont:\r\n"); + bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE); +#endif + + /* Change k^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store k^-1*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("k^-1:\r\n"); + bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE); +#endif + + /* Step 4,r*d ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)handle->privateKey, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 4, + ECP_SECP256R1_REG_TYPE, 5, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); + MSG("r*d:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); +#endif + + /* Step 5,e+r*d ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LADD(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, 5, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); + MSG("e+r*d:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); +#endif + + /* Step 6,(e+r*d)*k^-1 ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, 5, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); + MSG("(e+r*d)*k^-1:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); +#endif + /*N write only this time,add following operation will not change this register*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)s, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("s:\r\n"); + bflb_platform_dump(s, ECP_SECP256R1_SIZE); +#endif + + /* Check s zero*/ + if (sec_ecc_is_zero((uint8_t *)s, 32)) { + continue; + } + + return 0; + } + + return -1; +} + +int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key) +{ + if (sec_ecc_get_random_value(private_key, (uint32_t *)secp256r1N, 32) < 0) { + return -1; + } + + return 0; +} + +int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy); +} + +int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size) +{ + uint32_t maxTry = 100; + int32_t ret = 0; + + while (maxTry--) { + ret = Sec_Eng_Trng_Get_Random((uint8_t *)randomData, size); + + if (ret < 0) { + return -1; + } + + if (maxRef != NULL) { + if (sec_ecc_cmp((uint8_t *)maxRef, (uint8_t *)randomData, size) > 0) { + return 0; + } + } else { + return 0; + } + } + + return -1; +} + +int sec_eng_trng_enable(void) +{ + return Sec_Eng_Trng_Enable(); +} + +void sec_eng_trng_disable(void) +{ + Sec_Eng_Trng_Disable(); +} + +int sec_eng_trng_read(uint8_t data[32]) +{ + return Sec_Eng_Trng_Read(data); +} + +int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id) +{ + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + handle->ecpId = id; + + return 0; +} + +int sec_ecdh_deinit(sec_ecdh_handle_t *handle) +{ + Sec_Eng_PKA_Reset(); + + return 0; +} + +int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId, pkX, pkY, private_key, pRx, pRy); +} + +int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_sec_hash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_sec_hash.c new file mode 100644 index 0000000000000000000000000000000000000000..231d05efe3d167c53d6ecb898aec236497af0660 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_sec_hash.c @@ -0,0 +1,252 @@ +/** + * @file hal_sec_hash.c + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_sec_hash.h" +#include "bl602_sec_eng.h" + +void SEC_SHA_IRQHandler(void); + +static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] = { + 0 +}; +static SEC_Eng_SHA256_Ctx shaCtx; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int sec_hash_open(struct device *dev, uint16_t oflag) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret = 0; + + switch (sec_hash_device->type) { + case SEC_HASH_SHA1: + ret = -1; + break; + + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, sec_hash_device->shaBuf, sec_hash_device->shaPadding); + Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); + break; + + case SEC_HASH_SHA256: + Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, sec_hash_device->shaBuf, sec_hash_device->shaPadding); + Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); + break; + + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret = -1; + break; + + default: + ret = -1; + break; + } + + return ret; +} +/** + * @brief + * + * @param dev + * @return int + */ +int sec_hash_close(struct device *dev) +{ + //sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + //memset(sec_hash_device, 0, sizeof(sec_hash_device_t)); //will cause crash + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int sec_hash_control(struct device *dev, int cmd, void *args) +{ + return 0; +} + +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret = 0; + + switch (sec_hash_device->type) { + case SEC_HASH_SHA1: + ret = -1; + break; + + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); + break; + + case SEC_HASH_SHA256: + Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); + break; + + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret = -1; + break; + + default: + ret = -1; + break; + } + + return ret; +} + +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret = 0; + + switch (sec_hash_device->type) { + case SEC_HASH_SHA1: + ret = -1; + break; + + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); + ret = 28; + break; + + case SEC_HASH_SHA256: + Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); + ret = 32; + break; + + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret = -1; + break; + + default: + ret = -1; + break; + } + + return ret; +} + +/** + * @brief + * + * @param index + * @param type + * @param name + * @param flag + * @return int + */ +static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type, const char *name) +{ + struct device *dev; + + if (SEC_HASH_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(sec_hashx_device[index].parent); + sec_hashx_device[index].type = type; + + dev->open = sec_hash_open; + dev->close = sec_hash_close; + dev->control = sec_hash_control; + dev->write = sec_hash_write; + dev->read = sec_hash_read; + + dev->type = DEVICE_CLASS_SEC_HASH; + dev->handle = NULL; + + return device_register(dev, name); +} + +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name) +{ + return sec_hash_sha_register(index, SEC_HASH_SHA256, name); +} + +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name) +{ + return sec_hash_sha_register(index, SEC_HASH_SHA224, name); +} + +/** + * @brief + * + * @param handle + */ +void sec_hash_isr(sec_hash_device_t *handle) +{ +} + +/** + * @brief + * + */ +void SEC_SHA_IRQ(void) +{ + sec_hash_isr(&sec_hashx_device[0]); +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_uart.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..912ca6d2a20d7e8bdaf3dea856763fece649e976 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/hal_drv/src/hal_uart.c @@ -0,0 +1,442 @@ +/** + * ***************************************************************************** + * @file hal_uart.c + * @version 0.1 + * @date 2021-03-01 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#include "hal_uart.h" +#include "hal_dma.h" +#include "hal_gpio.h" +#include "hal_clock.h" +#include "bl602_uart.h" +#include "bl602_glb.h" +#include "uart_config.h" + +#define UART_CLOCK (40000000) + +#ifdef BSP_USING_UART0 +void UART0_IRQ(void); +#endif +#ifdef BSP_USING_UART1 +void UART1_IRQ(void); +#endif + +uart_device_t uartx_device[UART_MAX_INDEX] = { +#ifdef BSP_USING_UART0 + UART0_CONFIG, +#endif +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +}; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int uart_open(struct device *dev, uint16_t oflag) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + UART_FifoCfg_Type fifoCfg = { 0 }; + UART_CFG_Type uart_cfg = { 0 }; + + /* disable all interrupt */ + UART_IntMask(uart_device->id, UART_INT_ALL, MASK); + /* disable uart before config */ + UART_Disable(uart_device->id, UART_TXRX); + + //uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART); + + uart_cfg.baudRate = uart_device->baudrate; + uart_cfg.dataBits = uart_device->databits; + uart_cfg.stopBits = uart_device->stopbits; + uart_cfg.parity = uart_device->parity; + uart_cfg.uartClk = UART_CLOCK; + uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; + uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; + uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; + + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, 160000000 / UART_CLOCK - 1); + /* uart init with default configuration */ + UART_Init(uart_device->id, &uart_cfg); + + /* Enable tx free run mode */ + UART_TxFreeRun(uart_device->id, ENABLE); + + /* Set rx time-out value */ + UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT); + + fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold; + fifoCfg.txFifoDmaEnable = DISABLE; + fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold; + fifoCfg.rxFifoDmaEnable = DISABLE; + + if (oflag & DEVICE_OFLAG_STREAM_TX) { + } + + if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) { +#ifdef BSP_USING_UART0 + + if (uart_device->id == UART0_ID) { + Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ); + } + +#endif +#ifdef BSP_USING_UART1 + + if (uart_device->id == UART1_ID) { + Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ); + } + +#endif + } + + if (oflag & DEVICE_OFLAG_DMA_TX) { + fifoCfg.txFifoDmaEnable = ENABLE; + } + + if (oflag & DEVICE_OFLAG_DMA_RX) { + fifoCfg.rxFifoDmaEnable = ENABLE; + } + + UART_FifoConfig(uart_device->id, &fifoCfg); + /* enable uart */ + UART_Enable(uart_device->id, UART_TXRX); + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int uart_close(struct device *dev) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + + UART_Disable(uart_device->id, UART_TXRX); + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int uart_control(struct device *dev, int cmd, void *args) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: { + uint32_t offset = __builtin_ctz((uint32_t)args); + + while ((0 <= offset) && (offset < 9)) { + if ((uint32_t)args & (1 << offset)) { + UART_IntMask(uart_device->id, offset, UNMASK); + } + + offset++; + } + + if (uart_device->id == UART0_ID) { + Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ); + CPU_Interrupt_Enable(UART0_IRQn); + } else if (uart_device->id == UART1_ID) { + Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ); + CPU_Interrupt_Enable(UART1_IRQn); + } + + break; + } + + case DEVICE_CTRL_CLR_INT /* constant-expression */: { + uint32_t offset = __builtin_ctz((uint32_t)args); + + while ((0 <= offset) && (offset < 9)) { + if ((uint32_t)args & (1 << offset)) { + UART_IntMask(uart_device->id, offset, MASK); + } + + offset++; + } + + if (uart_device->id == UART0_ID) { + CPU_Interrupt_Disable(UART0_IRQn); + } else if (uart_device->id == UART1_ID) { + CPU_Interrupt_Disable(UART1_IRQn); + } + + break; + } + + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_CONFIG /* constant-expression */: { + uart_param_cfg_t *cfg = (uart_param_cfg_t *)args; + UART_CFG_Type uart_cfg = { 0 }; + + /* Disable uart before config */ + UART_Disable(uart_device->id, UART_TXRX); + + uart_cfg.uartClk = 160 * 1000 * 1000; + uart_cfg.baudRate = cfg->baudrate; + uart_cfg.stopBits = cfg->stopbits; + uart_cfg.parity = cfg->parity; + uart_cfg.dataBits = cfg->databits; + uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; + uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; + uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; + UART_Init(uart_device->id, &uart_cfg); +#ifdef BSP_USING_UART0 + + if (uart_device->id == UART0_ID) { + Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ); + } +#endif +#ifdef BSP_USING_UART1 + + if (uart_device->id == UART1_ID) { + Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ); + } +#endif + /* Enable uart */ + UART_Enable(uart_device->id, UART_TXRX); + break; + } + + case DEVICE_CTRL_GET_CONFIG /* constant-expression */: + break; + + case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */: + uart_device->tx_dma = (struct device *)args; + break; + + case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */: + uart_device->rx_dma = (struct device *)args; + break; + + case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */: + return UART_GetTxFifoCount(uart_device->id); + + case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */: + return UART_GetRxFifoCount(uart_device->id); + + default: + break; + } + + return 0; +} +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + + if (dev->oflag & DEVICE_OFLAG_DMA_TX) { + struct device *dma_ch = (struct device *)uart_device->tx_dma; + + if (!dma_ch) { + return -1; + } + + if (uart_device->id == 0) { + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size); + dma_channel_start(dma_ch); + } else if (uart_device->id == 1) { + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size); + dma_channel_start(dma_ch); + } + + return 0; + } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { + return -2; + } else + return UART_SendData(uart_device->id, (uint8_t *)buffer, size); +} +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + + if (dev->oflag & DEVICE_OFLAG_DMA_RX) { + struct device *dma_ch = (struct device *)uart_device->rx_dma; + + if (!dma_ch) { + return -1; + } + return 0; + } else if (dev->oflag & DEVICE_OFLAG_INT_RX) { + return -2; + } else { + return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size); + } +} +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int uart_register(enum uart_index_type index, const char *name) +{ + struct device *dev; + + if (UART_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(uartx_device[index].parent); + + dev->open = uart_open; + dev->close = uart_close; + dev->control = uart_control; + dev->write = uart_write; + dev->read = uart_read; + + dev->type = DEVICE_CLASS_UART; + dev->handle = NULL; + + return device_register(dev, name); +} +/** + * @brief + * + * @param handle + */ +void uart_isr(uart_device_t *handle) +{ + uint32_t tmpVal = 0; + uint32_t maskVal = 0; + uint32_t UARTx = (UART0_BASE + handle->id * 0x100); + uint16_t len; + + tmpVal = BL_RD_REG(UARTx, UART_INT_STS); + maskVal = BL_RD_REG(UARTx, UART_INT_MASK); + + if (!handle->parent.callback) { + return; + } + + /* Length of uart tx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1); + handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END); + } + + /* Length of uart rx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2); + handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_END); + } + + /* Tx fifo ready interrupt,auto-cleared when data is pushed */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO); + } + + /* Rx fifo ready interrupt,auto-cleared when data is popped */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) { + uint8_t buffer[UART_FIFO_MAX_LEN]; + len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold); + handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO); + } + + /* Rx time-out interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { + uint8_t buffer[UART_FIFO_MAX_LEN]; + len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold); + handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO); + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10); + } + + /* Rx parity check error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20); + handle->parent.callback(&handle->parent, NULL, 0, UART_PCE_IT); + } + + /* Tx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, UART_TX_FER_IT); + } + + /* Rx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, UART_RX_FER_IT); + } +} + +#ifdef BSP_USING_UART0 +/** + * @brief + * + */ +void UART0_IRQ(void) +{ + uart_isr(&uartx_device[UART0_INDEX]); +} +#endif +#ifdef BSP_USING_UART1 +/** + * @brief + * + */ +void UART1_IRQ(void) +{ + uart_isr(&uartx_device[UART1_INDEX]); +} +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/aon_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/aon_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..993e06043c5e29df9175151bb474c2c89341683a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/aon_reg.h @@ -0,0 +1,1560 @@ +/** + ****************************************************************************** + * @file aon_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __AON_REG_H__ +#define __AON_REG_H__ + +#include "bl602.h" + +/* 0x800 : aon */ +#define AON_OFFSET (0x800) +#define AON_RESV AON_RESV +#define AON_RESV_POS (0U) +#define AON_RESV_LEN (8U) +#define AON_RESV_MSK (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS) +#define AON_RESV_UMSK (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)) +#define AON_PU_AON_DC_TBUF AON_PU_AON_DC_TBUF +#define AON_PU_AON_DC_TBUF_POS (12U) +#define AON_PU_AON_DC_TBUF_LEN (1U) +#define AON_PU_AON_DC_TBUF_MSK (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS) +#define AON_PU_AON_DC_TBUF_UMSK (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)) +#define AON_LDO11_RT_PULLDOWN AON_LDO11_RT_PULLDOWN +#define AON_LDO11_RT_PULLDOWN_POS (20U) +#define AON_LDO11_RT_PULLDOWN_LEN (1U) +#define AON_LDO11_RT_PULLDOWN_MSK (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS) +#define AON_LDO11_RT_PULLDOWN_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)) +#define AON_LDO11_RT_PULLDOWN_SEL AON_LDO11_RT_PULLDOWN_SEL +#define AON_LDO11_RT_PULLDOWN_SEL_POS (21U) +#define AON_LDO11_RT_PULLDOWN_SEL_LEN (1U) +#define AON_LDO11_RT_PULLDOWN_SEL_MSK (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS) +#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)) +#define AON_SW_PU_LDO11_RT AON_SW_PU_LDO11_RT +#define AON_SW_PU_LDO11_RT_POS (22U) +#define AON_SW_PU_LDO11_RT_LEN (1U) +#define AON_SW_PU_LDO11_RT_MSK (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS) +#define AON_SW_PU_LDO11_RT_UMSK (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)) + +/* 0x804 : aon_common */ +#define AON_COMMON_OFFSET (0x804) +#define AON_TMUX_AON AON_TMUX_AON +#define AON_TMUX_AON_POS (0U) +#define AON_TMUX_AON_LEN (3U) +#define AON_TMUX_AON_MSK (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS) +#define AON_TMUX_AON_UMSK (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)) +#define AON_TEN_AON AON_TEN_AON +#define AON_TEN_AON_POS (4U) +#define AON_TEN_AON_LEN (1U) +#define AON_TEN_AON_MSK (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS) +#define AON_TEN_AON_UMSK (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)) +#define AON_DTEN_XTAL32K AON_DTEN_XTAL32K +#define AON_DTEN_XTAL32K_POS (5U) +#define AON_DTEN_XTAL32K_LEN (1U) +#define AON_DTEN_XTAL32K_MSK (((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS) +#define AON_DTEN_XTAL32K_UMSK (~(((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS)) +#define AON_TEN_XTAL32K AON_TEN_XTAL32K +#define AON_TEN_XTAL32K_POS (6U) +#define AON_TEN_XTAL32K_LEN (1U) +#define AON_TEN_XTAL32K_MSK (((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS) +#define AON_TEN_XTAL32K_UMSK (~(((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS)) +#define AON_TEN_VDDCORE_AON AON_TEN_VDDCORE_AON +#define AON_TEN_VDDCORE_AON_POS (8U) +#define AON_TEN_VDDCORE_AON_LEN (1U) +#define AON_TEN_VDDCORE_AON_MSK (((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS) +#define AON_TEN_VDDCORE_AON_UMSK (~(((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS)) +#define AON_TEN_LDO11SOC_AON AON_TEN_LDO11SOC_AON +#define AON_TEN_LDO11SOC_AON_POS (9U) +#define AON_TEN_LDO11SOC_AON_LEN (1U) +#define AON_TEN_LDO11SOC_AON_MSK (((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS) +#define AON_TEN_LDO11SOC_AON_UMSK (~(((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS)) +#define AON_TEN_DCDC18_0_AON AON_TEN_DCDC18_0_AON +#define AON_TEN_DCDC18_0_AON_POS (10U) +#define AON_TEN_DCDC18_0_AON_LEN (1U) +#define AON_TEN_DCDC18_0_AON_MSK (((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS) +#define AON_TEN_DCDC18_0_AON_UMSK (~(((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS)) +#define AON_TEN_DCDC18_1_AON AON_TEN_DCDC18_1_AON +#define AON_TEN_DCDC18_1_AON_POS (11U) +#define AON_TEN_DCDC18_1_AON_LEN (1U) +#define AON_TEN_DCDC18_1_AON_MSK (((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS) +#define AON_TEN_DCDC18_1_AON_UMSK (~(((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS)) +#define AON_TEN_BG_SYS_AON AON_TEN_BG_SYS_AON +#define AON_TEN_BG_SYS_AON_POS (12U) +#define AON_TEN_BG_SYS_AON_LEN (1U) +#define AON_TEN_BG_SYS_AON_MSK (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS) +#define AON_TEN_BG_SYS_AON_UMSK (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)) +#define AON_TEN_LDO15RF_AON AON_TEN_LDO15RF_AON +#define AON_TEN_LDO15RF_AON_POS (16U) +#define AON_TEN_LDO15RF_AON_LEN (1U) +#define AON_TEN_LDO15RF_AON_MSK (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS) +#define AON_TEN_LDO15RF_AON_UMSK (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)) +#define AON_TEN_XTAL_AON AON_TEN_XTAL_AON +#define AON_TEN_XTAL_AON_POS (17U) +#define AON_TEN_XTAL_AON_LEN (1U) +#define AON_TEN_XTAL_AON_MSK (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS) +#define AON_TEN_XTAL_AON_UMSK (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)) +#define AON_DTEN_XTAL_AON AON_DTEN_XTAL_AON +#define AON_DTEN_XTAL_AON_POS (18U) +#define AON_DTEN_XTAL_AON_LEN (1U) +#define AON_DTEN_XTAL_AON_MSK (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS) +#define AON_DTEN_XTAL_AON_UMSK (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)) +#define AON_TEN_MBG_AON AON_TEN_MBG_AON +#define AON_TEN_MBG_AON_POS (19U) +#define AON_TEN_MBG_AON_LEN (1U) +#define AON_TEN_MBG_AON_MSK (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS) +#define AON_TEN_MBG_AON_UMSK (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)) +#define AON_TEN_CIP_MISC_AON AON_TEN_CIP_MISC_AON +#define AON_TEN_CIP_MISC_AON_POS (20U) +#define AON_TEN_CIP_MISC_AON_LEN (1U) +#define AON_TEN_CIP_MISC_AON_MSK (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS) +#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)) + +/* 0x808 : aon_misc */ +#define AON_MISC_OFFSET (0x808) +#define AON_SW_SOC_EN_AON AON_SW_SOC_EN_AON +#define AON_SW_SOC_EN_AON_POS (0U) +#define AON_SW_SOC_EN_AON_LEN (1U) +#define AON_SW_SOC_EN_AON_MSK (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS) +#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)) +#define AON_SW_WB_EN_AON AON_SW_WB_EN_AON +#define AON_SW_WB_EN_AON_POS (1U) +#define AON_SW_WB_EN_AON_LEN (1U) +#define AON_SW_WB_EN_AON_MSK (((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS) +#define AON_SW_WB_EN_AON_UMSK (~(((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS)) + +/* 0x810 : bg_sys_top */ +#define AON_BG_SYS_TOP_OFFSET (0x810) +#define AON_PMIP_RESV AON_PMIP_RESV +#define AON_PMIP_RESV_POS (0U) +#define AON_PMIP_RESV_LEN (8U) +#define AON_PMIP_RESV_MSK (((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS) +#define AON_PMIP_RESV_UMSK (~(((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS)) +#define AON_PU_BG_SYS_AON AON_PU_BG_SYS_AON +#define AON_PU_BG_SYS_AON_POS (8U) +#define AON_PU_BG_SYS_AON_LEN (1U) +#define AON_PU_BG_SYS_AON_MSK (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS) +#define AON_PU_BG_SYS_AON_UMSK (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)) +#define AON_BG_SYS_START_CTRL_AON AON_BG_SYS_START_CTRL_AON +#define AON_BG_SYS_START_CTRL_AON_POS (12U) +#define AON_BG_SYS_START_CTRL_AON_LEN (1U) +#define AON_BG_SYS_START_CTRL_AON_MSK (((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS) +#define AON_BG_SYS_START_CTRL_AON_UMSK (~(((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS)) + +/* 0x814 : dcdc18_top_0 */ +#define AON_DCDC18_TOP_0_OFFSET (0x814) +#define AON_DCDC18_VOUT_SEL_AON AON_DCDC18_VOUT_SEL_AON +#define AON_DCDC18_VOUT_SEL_AON_POS (1U) +#define AON_DCDC18_VOUT_SEL_AON_LEN (5U) +#define AON_DCDC18_VOUT_SEL_AON_MSK (((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS) +#define AON_DCDC18_VOUT_SEL_AON_UMSK (~(((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS)) +#define AON_DCDC18_VPFM_AON AON_DCDC18_VPFM_AON +#define AON_DCDC18_VPFM_AON_POS (8U) +#define AON_DCDC18_VPFM_AON_LEN (4U) +#define AON_DCDC18_VPFM_AON_MSK (((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS) +#define AON_DCDC18_VPFM_AON_UMSK (~(((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS)) +#define AON_DCDC18_OSC_2M_MODE_AON AON_DCDC18_OSC_2M_MODE_AON +#define AON_DCDC18_OSC_2M_MODE_AON_POS (12U) +#define AON_DCDC18_OSC_2M_MODE_AON_LEN (1U) +#define AON_DCDC18_OSC_2M_MODE_AON_MSK (((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS) +#define AON_DCDC18_OSC_2M_MODE_AON_UMSK (~(((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS)) +#define AON_DCDC18_OSC_FREQ_TRIM_AON AON_DCDC18_OSC_FREQ_TRIM_AON +#define AON_DCDC18_OSC_FREQ_TRIM_AON_POS (16U) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_LEN (4U) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_MSK (((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_UMSK (~(((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS)) +#define AON_DCDC18_SLOPE_CURR_SEL_AON AON_DCDC18_SLOPE_CURR_SEL_AON +#define AON_DCDC18_SLOPE_CURR_SEL_AON_POS (20U) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_LEN (5U) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_MSK (((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS)) +#define AON_DCDC18_STOP_OSC_AON AON_DCDC18_STOP_OSC_AON +#define AON_DCDC18_STOP_OSC_AON_POS (25U) +#define AON_DCDC18_STOP_OSC_AON_LEN (1U) +#define AON_DCDC18_STOP_OSC_AON_MSK (((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS) +#define AON_DCDC18_STOP_OSC_AON_UMSK (~(((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS)) +#define AON_DCDC18_SLOW_OSC_AON AON_DCDC18_SLOW_OSC_AON +#define AON_DCDC18_SLOW_OSC_AON_POS (26U) +#define AON_DCDC18_SLOW_OSC_AON_LEN (1U) +#define AON_DCDC18_SLOW_OSC_AON_MSK (((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS) +#define AON_DCDC18_SLOW_OSC_AON_UMSK (~(((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS)) +#define AON_DCDC18_OSC_INHIBIT_T2_AON AON_DCDC18_OSC_INHIBIT_T2_AON +#define AON_DCDC18_OSC_INHIBIT_T2_AON_POS (27U) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_LEN (1U) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_MSK (((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS)) +#define AON_DCDC18_SSTART_TIME_AON AON_DCDC18_SSTART_TIME_AON +#define AON_DCDC18_SSTART_TIME_AON_POS (28U) +#define AON_DCDC18_SSTART_TIME_AON_LEN (2U) +#define AON_DCDC18_SSTART_TIME_AON_MSK (((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS) +#define AON_DCDC18_SSTART_TIME_AON_UMSK (~(((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS)) +#define AON_DCDC18_RDY_AON AON_DCDC18_RDY_AON +#define AON_DCDC18_RDY_AON_POS (31U) +#define AON_DCDC18_RDY_AON_LEN (1U) +#define AON_DCDC18_RDY_AON_MSK (((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS) +#define AON_DCDC18_RDY_AON_UMSK (~(((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS)) + +/* 0x818 : dcdc18_top_1 */ +#define AON_DCDC18_TOP_1_OFFSET (0x818) +#define AON_DCDC18_FORCE_CS_ZVS_AON AON_DCDC18_FORCE_CS_ZVS_AON +#define AON_DCDC18_FORCE_CS_ZVS_AON_POS (0U) +#define AON_DCDC18_FORCE_CS_ZVS_AON_LEN (1U) +#define AON_DCDC18_FORCE_CS_ZVS_AON_MSK (((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS) +#define AON_DCDC18_FORCE_CS_ZVS_AON_UMSK (~(((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS)) +#define AON_DCDC18_CS_DELAY_AON AON_DCDC18_CS_DELAY_AON +#define AON_DCDC18_CS_DELAY_AON_POS (1U) +#define AON_DCDC18_CS_DELAY_AON_LEN (3U) +#define AON_DCDC18_CS_DELAY_AON_MSK (((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS) +#define AON_DCDC18_CS_DELAY_AON_UMSK (~(((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS)) +#define AON_DCDC18_ZVS_TD_OPT_AON AON_DCDC18_ZVS_TD_OPT_AON +#define AON_DCDC18_ZVS_TD_OPT_AON_POS (4U) +#define AON_DCDC18_ZVS_TD_OPT_AON_LEN (3U) +#define AON_DCDC18_ZVS_TD_OPT_AON_MSK (((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS) +#define AON_DCDC18_ZVS_TD_OPT_AON_UMSK (~(((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS)) +#define AON_DCDC18_NONOVERLAP_TD_AON AON_DCDC18_NONOVERLAP_TD_AON +#define AON_DCDC18_NONOVERLAP_TD_AON_POS (8U) +#define AON_DCDC18_NONOVERLAP_TD_AON_LEN (5U) +#define AON_DCDC18_NONOVERLAP_TD_AON_MSK (((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS) +#define AON_DCDC18_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS)) +#define AON_DCDC18_RC_SEL_AON AON_DCDC18_RC_SEL_AON +#define AON_DCDC18_RC_SEL_AON_POS (16U) +#define AON_DCDC18_RC_SEL_AON_LEN (4U) +#define AON_DCDC18_RC_SEL_AON_MSK (((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS) +#define AON_DCDC18_RC_SEL_AON_UMSK (~(((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS)) +#define AON_DCDC18_CHF_SEL_AON AON_DCDC18_CHF_SEL_AON +#define AON_DCDC18_CHF_SEL_AON_POS (20U) +#define AON_DCDC18_CHF_SEL_AON_LEN (4U) +#define AON_DCDC18_CHF_SEL_AON_MSK (((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS) +#define AON_DCDC18_CHF_SEL_AON_UMSK (~(((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS)) +#define AON_DCDC18_CFB_SEL_AON AON_DCDC18_CFB_SEL_AON +#define AON_DCDC18_CFB_SEL_AON_POS (24U) +#define AON_DCDC18_CFB_SEL_AON_LEN (4U) +#define AON_DCDC18_CFB_SEL_AON_MSK (((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS) +#define AON_DCDC18_CFB_SEL_AON_UMSK (~(((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS)) +#define AON_DCDC18_EN_ANTIRING_AON AON_DCDC18_EN_ANTIRING_AON +#define AON_DCDC18_EN_ANTIRING_AON_POS (28U) +#define AON_DCDC18_EN_ANTIRING_AON_LEN (1U) +#define AON_DCDC18_EN_ANTIRING_AON_MSK (((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS) +#define AON_DCDC18_EN_ANTIRING_AON_UMSK (~(((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS)) +#define AON_DCDC18_PULLDOWN_AON AON_DCDC18_PULLDOWN_AON +#define AON_DCDC18_PULLDOWN_AON_POS (29U) +#define AON_DCDC18_PULLDOWN_AON_LEN (1U) +#define AON_DCDC18_PULLDOWN_AON_MSK (((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS) +#define AON_DCDC18_PULLDOWN_AON_UMSK (~(((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS)) + +/* 0x81C : ldo11soc_and_dctest */ +#define AON_LDO11SOC_AND_DCTEST_OFFSET (0x81C) +#define AON_PU_LDO11SOC_AON AON_PU_LDO11SOC_AON +#define AON_PU_LDO11SOC_AON_POS (0U) +#define AON_PU_LDO11SOC_AON_LEN (1U) +#define AON_PU_LDO11SOC_AON_MSK (((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS) +#define AON_PU_LDO11SOC_AON_UMSK (~(((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS)) +#define AON_LDO11SOC_SSTART_SEL_AON AON_LDO11SOC_SSTART_SEL_AON +#define AON_LDO11SOC_SSTART_SEL_AON_POS (4U) +#define AON_LDO11SOC_SSTART_SEL_AON_LEN (1U) +#define AON_LDO11SOC_SSTART_SEL_AON_MSK (((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS) +#define AON_LDO11SOC_SSTART_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS)) +#define AON_LDO11SOC_SSTART_DELAY_AON AON_LDO11SOC_SSTART_DELAY_AON +#define AON_LDO11SOC_SSTART_DELAY_AON_POS (8U) +#define AON_LDO11SOC_SSTART_DELAY_AON_LEN (2U) +#define AON_LDO11SOC_SSTART_DELAY_AON_MSK (((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS) +#define AON_LDO11SOC_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS)) +#define AON_LDO11SOC_PULLDOWN_AON AON_LDO11SOC_PULLDOWN_AON +#define AON_LDO11SOC_PULLDOWN_AON_POS (10U) +#define AON_LDO11SOC_PULLDOWN_AON_LEN (1U) +#define AON_LDO11SOC_PULLDOWN_AON_MSK (((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS) +#define AON_LDO11SOC_PULLDOWN_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS)) +#define AON_LDO11SOC_PULLDOWN_SEL_AON AON_LDO11SOC_PULLDOWN_SEL_AON +#define AON_LDO11SOC_PULLDOWN_SEL_AON_POS (11U) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_LEN (1U) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_MSK (((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS)) +#define AON_LDO11SOC_VTH_SEL_AON AON_LDO11SOC_VTH_SEL_AON +#define AON_LDO11SOC_VTH_SEL_AON_POS (12U) +#define AON_LDO11SOC_VTH_SEL_AON_LEN (2U) +#define AON_LDO11SOC_VTH_SEL_AON_MSK (((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS) +#define AON_LDO11SOC_VTH_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS)) +#define AON_LDO11SOC_CC_AON AON_LDO11SOC_CC_AON +#define AON_LDO11SOC_CC_AON_POS (24U) +#define AON_LDO11SOC_CC_AON_LEN (2U) +#define AON_LDO11SOC_CC_AON_MSK (((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS) +#define AON_LDO11SOC_CC_AON_UMSK (~(((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS)) +#define AON_LDO11SOC_RDY_AON AON_LDO11SOC_RDY_AON +#define AON_LDO11SOC_RDY_AON_POS (28U) +#define AON_LDO11SOC_RDY_AON_LEN (1U) +#define AON_LDO11SOC_RDY_AON_MSK (((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS) +#define AON_LDO11SOC_RDY_AON_UMSK (~(((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS)) +#define AON_LDO11SOC_POWER_GOOD_AON AON_LDO11SOC_POWER_GOOD_AON +#define AON_LDO11SOC_POWER_GOOD_AON_POS (29U) +#define AON_LDO11SOC_POWER_GOOD_AON_LEN (1U) +#define AON_LDO11SOC_POWER_GOOD_AON_MSK (((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS) +#define AON_LDO11SOC_POWER_GOOD_AON_UMSK (~(((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS)) +#define AON_PU_VDDCORE_MISC_AON AON_PU_VDDCORE_MISC_AON +#define AON_PU_VDDCORE_MISC_AON_POS (30U) +#define AON_PU_VDDCORE_MISC_AON_LEN (1U) +#define AON_PU_VDDCORE_MISC_AON_MSK (((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS) +#define AON_PU_VDDCORE_MISC_AON_UMSK (~(((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS)) +#define AON_PMIP_DC_TP_OUT_EN_AON AON_PMIP_DC_TP_OUT_EN_AON +#define AON_PMIP_DC_TP_OUT_EN_AON_POS (31U) +#define AON_PMIP_DC_TP_OUT_EN_AON_LEN (1U) +#define AON_PMIP_DC_TP_OUT_EN_AON_MSK (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS) +#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)) + +/* 0x820 : psw_irrcv */ +#define AON_PSW_IRRCV_OFFSET (0x820) +#define AON_PU_IR_PSW_AON AON_PU_IR_PSW_AON +#define AON_PU_IR_PSW_AON_POS (0U) +#define AON_PU_IR_PSW_AON_LEN (1U) +#define AON_PU_IR_PSW_AON_MSK (((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS) +#define AON_PU_IR_PSW_AON_UMSK (~(((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS)) + +/* 0x880 : rf_top_aon */ +#define AON_RF_TOP_AON_OFFSET (0x880) +#define AON_PU_MBG_AON AON_PU_MBG_AON +#define AON_PU_MBG_AON_POS (0U) +#define AON_PU_MBG_AON_LEN (1U) +#define AON_PU_MBG_AON_MSK (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS) +#define AON_PU_MBG_AON_UMSK (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)) +#define AON_PU_LDO15RF_AON AON_PU_LDO15RF_AON +#define AON_PU_LDO15RF_AON_POS (1U) +#define AON_PU_LDO15RF_AON_LEN (1U) +#define AON_PU_LDO15RF_AON_MSK (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS) +#define AON_PU_LDO15RF_AON_UMSK (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)) +#define AON_PU_SFREG_AON AON_PU_SFREG_AON +#define AON_PU_SFREG_AON_POS (2U) +#define AON_PU_SFREG_AON_LEN (1U) +#define AON_PU_SFREG_AON_MSK (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS) +#define AON_PU_SFREG_AON_UMSK (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)) +#define AON_PU_XTAL_BUF_AON AON_PU_XTAL_BUF_AON +#define AON_PU_XTAL_BUF_AON_POS (4U) +#define AON_PU_XTAL_BUF_AON_LEN (1U) +#define AON_PU_XTAL_BUF_AON_MSK (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS) +#define AON_PU_XTAL_BUF_AON_UMSK (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)) +#define AON_PU_XTAL_AON AON_PU_XTAL_AON +#define AON_PU_XTAL_AON_POS (5U) +#define AON_PU_XTAL_AON_LEN (1U) +#define AON_PU_XTAL_AON_MSK (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS) +#define AON_PU_XTAL_AON_UMSK (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)) +#define AON_LDO15RF_SSTART_SEL_AON AON_LDO15RF_SSTART_SEL_AON +#define AON_LDO15RF_SSTART_SEL_AON_POS (8U) +#define AON_LDO15RF_SSTART_SEL_AON_LEN (1U) +#define AON_LDO15RF_SSTART_SEL_AON_MSK (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS) +#define AON_LDO15RF_SSTART_SEL_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)) +#define AON_LDO15RF_SSTART_DELAY_AON AON_LDO15RF_SSTART_DELAY_AON +#define AON_LDO15RF_SSTART_DELAY_AON_POS (9U) +#define AON_LDO15RF_SSTART_DELAY_AON_LEN (2U) +#define AON_LDO15RF_SSTART_DELAY_AON_MSK (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS) +#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)) +#define AON_LDO15RF_PULLDOWN_AON AON_LDO15RF_PULLDOWN_AON +#define AON_LDO15RF_PULLDOWN_AON_POS (12U) +#define AON_LDO15RF_PULLDOWN_AON_LEN (1U) +#define AON_LDO15RF_PULLDOWN_AON_MSK (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS) +#define AON_LDO15RF_PULLDOWN_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)) +#define AON_LDO15RF_PULLDOWN_SEL_AON AON_LDO15RF_PULLDOWN_SEL_AON +#define AON_LDO15RF_PULLDOWN_SEL_AON_POS (13U) +#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN (1U) +#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS) +#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)) +#define AON_LDO15RF_VOUT_SEL_AON AON_LDO15RF_VOUT_SEL_AON +#define AON_LDO15RF_VOUT_SEL_AON_POS (16U) +#define AON_LDO15RF_VOUT_SEL_AON_LEN (3U) +#define AON_LDO15RF_VOUT_SEL_AON_MSK (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS) +#define AON_LDO15RF_VOUT_SEL_AON_UMSK (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)) +#define AON_LDO15RF_CC_AON AON_LDO15RF_CC_AON +#define AON_LDO15RF_CC_AON_POS (24U) +#define AON_LDO15RF_CC_AON_LEN (2U) +#define AON_LDO15RF_CC_AON_MSK (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS) +#define AON_LDO15RF_CC_AON_UMSK (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)) +#define AON_LDO15RF_BYPASS_AON AON_LDO15RF_BYPASS_AON +#define AON_LDO15RF_BYPASS_AON_POS (28U) +#define AON_LDO15RF_BYPASS_AON_LEN (1U) +#define AON_LDO15RF_BYPASS_AON_MSK (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS) +#define AON_LDO15RF_BYPASS_AON_UMSK (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)) + +/* 0x884 : xtal_cfg */ +#define AON_XTAL_CFG_OFFSET (0x884) +#define AON_XTAL_BK_AON AON_XTAL_BK_AON +#define AON_XTAL_BK_AON_POS (0U) +#define AON_XTAL_BK_AON_LEN (2U) +#define AON_XTAL_BK_AON_MSK (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS) +#define AON_XTAL_BK_AON_UMSK (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)) +#define AON_XTAL_CAPCODE_EXTRA_AON AON_XTAL_CAPCODE_EXTRA_AON +#define AON_XTAL_CAPCODE_EXTRA_AON_POS (2U) +#define AON_XTAL_CAPCODE_EXTRA_AON_LEN (1U) +#define AON_XTAL_CAPCODE_EXTRA_AON_MSK (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS) +#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)) +#define AON_XTAL_EXT_SEL_AON AON_XTAL_EXT_SEL_AON +#define AON_XTAL_EXT_SEL_AON_POS (3U) +#define AON_XTAL_EXT_SEL_AON_LEN (1U) +#define AON_XTAL_EXT_SEL_AON_MSK (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS) +#define AON_XTAL_EXT_SEL_AON_UMSK (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)) +#define AON_XTAL_BUF_EN_AON AON_XTAL_BUF_EN_AON +#define AON_XTAL_BUF_EN_AON_POS (4U) +#define AON_XTAL_BUF_EN_AON_LEN (4U) +#define AON_XTAL_BUF_EN_AON_MSK (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS) +#define AON_XTAL_BUF_EN_AON_UMSK (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)) +#define AON_XTAL_BUF_HP_AON AON_XTAL_BUF_HP_AON +#define AON_XTAL_BUF_HP_AON_POS (8U) +#define AON_XTAL_BUF_HP_AON_LEN (4U) +#define AON_XTAL_BUF_HP_AON_MSK (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS) +#define AON_XTAL_BUF_HP_AON_UMSK (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)) +#define AON_XTAL_FAST_STARTUP_AON AON_XTAL_FAST_STARTUP_AON +#define AON_XTAL_FAST_STARTUP_AON_POS (12U) +#define AON_XTAL_FAST_STARTUP_AON_LEN (1U) +#define AON_XTAL_FAST_STARTUP_AON_MSK (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS) +#define AON_XTAL_FAST_STARTUP_AON_UMSK (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)) +#define AON_XTAL_SLEEP_AON AON_XTAL_SLEEP_AON +#define AON_XTAL_SLEEP_AON_POS (13U) +#define AON_XTAL_SLEEP_AON_LEN (1U) +#define AON_XTAL_SLEEP_AON_MSK (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS) +#define AON_XTAL_SLEEP_AON_UMSK (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)) +#define AON_XTAL_AMP_CTRL_AON AON_XTAL_AMP_CTRL_AON +#define AON_XTAL_AMP_CTRL_AON_POS (14U) +#define AON_XTAL_AMP_CTRL_AON_LEN (2U) +#define AON_XTAL_AMP_CTRL_AON_MSK (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS) +#define AON_XTAL_AMP_CTRL_AON_UMSK (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)) +#define AON_XTAL_CAPCODE_OUT_AON AON_XTAL_CAPCODE_OUT_AON +#define AON_XTAL_CAPCODE_OUT_AON_POS (16U) +#define AON_XTAL_CAPCODE_OUT_AON_LEN (6U) +#define AON_XTAL_CAPCODE_OUT_AON_MSK (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS) +#define AON_XTAL_CAPCODE_OUT_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)) +#define AON_XTAL_CAPCODE_IN_AON AON_XTAL_CAPCODE_IN_AON +#define AON_XTAL_CAPCODE_IN_AON_POS (22U) +#define AON_XTAL_CAPCODE_IN_AON_LEN (6U) +#define AON_XTAL_CAPCODE_IN_AON_MSK (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS) +#define AON_XTAL_CAPCODE_IN_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)) +#define AON_XTAL_GM_BOOST_AON AON_XTAL_GM_BOOST_AON +#define AON_XTAL_GM_BOOST_AON_POS (28U) +#define AON_XTAL_GM_BOOST_AON_LEN (2U) +#define AON_XTAL_GM_BOOST_AON_MSK (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS) +#define AON_XTAL_GM_BOOST_AON_UMSK (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)) +#define AON_XTAL_RDY_SEL_AON AON_XTAL_RDY_SEL_AON +#define AON_XTAL_RDY_SEL_AON_POS (30U) +#define AON_XTAL_RDY_SEL_AON_LEN (2U) +#define AON_XTAL_RDY_SEL_AON_MSK (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS) +#define AON_XTAL_RDY_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)) + +/* 0x888 : tsen */ +#define AON_TSEN_OFFSET (0x888) +#define AON_TSEN_REFCODE_CORNER AON_TSEN_REFCODE_CORNER +#define AON_TSEN_REFCODE_CORNER_POS (0U) +#define AON_TSEN_REFCODE_CORNER_LEN (12U) +#define AON_TSEN_REFCODE_CORNER_MSK (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS) +#define AON_TSEN_REFCODE_CORNER_UMSK (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)) +#define AON_TSEN_REFCODE_RFCAL AON_TSEN_REFCODE_RFCAL +#define AON_TSEN_REFCODE_RFCAL_POS (16U) +#define AON_TSEN_REFCODE_RFCAL_LEN (12U) +#define AON_TSEN_REFCODE_RFCAL_MSK (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS) +#define AON_TSEN_REFCODE_RFCAL_UMSK (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)) +#define AON_XTAL_RDY AON_XTAL_RDY +#define AON_XTAL_RDY_POS (28U) +#define AON_XTAL_RDY_LEN (1U) +#define AON_XTAL_RDY_MSK (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS) +#define AON_XTAL_RDY_UMSK (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)) +#define AON_XTAL_INN_CFG_EN_AON AON_XTAL_INN_CFG_EN_AON +#define AON_XTAL_INN_CFG_EN_AON_POS (29U) +#define AON_XTAL_INN_CFG_EN_AON_LEN (1U) +#define AON_XTAL_INN_CFG_EN_AON_MSK (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS) +#define AON_XTAL_INN_CFG_EN_AON_UMSK (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)) +#define AON_XTAL_RDY_INT_SEL_AON AON_XTAL_RDY_INT_SEL_AON +#define AON_XTAL_RDY_INT_SEL_AON_POS (30U) +#define AON_XTAL_RDY_INT_SEL_AON_LEN (2U) +#define AON_XTAL_RDY_INT_SEL_AON_MSK (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS) +#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)) + +/* 0x900 : acomp0_ctrl */ +#define AON_ACOMP0_CTRL_OFFSET (0x900) +#define AON_ACOMP0_EN AON_ACOMP0_EN +#define AON_ACOMP0_EN_POS (0U) +#define AON_ACOMP0_EN_LEN (1U) +#define AON_ACOMP0_EN_MSK (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS) +#define AON_ACOMP0_EN_UMSK (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)) +#define AON_ACOMP0_HYST_SELN AON_ACOMP0_HYST_SELN +#define AON_ACOMP0_HYST_SELN_POS (4U) +#define AON_ACOMP0_HYST_SELN_LEN (3U) +#define AON_ACOMP0_HYST_SELN_MSK (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS) +#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)) +#define AON_ACOMP0_HYST_SELP AON_ACOMP0_HYST_SELP +#define AON_ACOMP0_HYST_SELP_POS (7U) +#define AON_ACOMP0_HYST_SELP_LEN (3U) +#define AON_ACOMP0_HYST_SELP_MSK (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS) +#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)) +#define AON_ACOMP0_BIAS_PROG AON_ACOMP0_BIAS_PROG +#define AON_ACOMP0_BIAS_PROG_POS (10U) +#define AON_ACOMP0_BIAS_PROG_LEN (2U) +#define AON_ACOMP0_BIAS_PROG_MSK (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS) +#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)) +#define AON_ACOMP0_LEVEL_SEL AON_ACOMP0_LEVEL_SEL +#define AON_ACOMP0_LEVEL_SEL_POS (12U) +#define AON_ACOMP0_LEVEL_SEL_LEN (6U) +#define AON_ACOMP0_LEVEL_SEL_MSK (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS) +#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)) +#define AON_ACOMP0_NEG_SEL AON_ACOMP0_NEG_SEL +#define AON_ACOMP0_NEG_SEL_POS (18U) +#define AON_ACOMP0_NEG_SEL_LEN (4U) +#define AON_ACOMP0_NEG_SEL_MSK (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS) +#define AON_ACOMP0_NEG_SEL_UMSK (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)) +#define AON_ACOMP0_POS_SEL AON_ACOMP0_POS_SEL +#define AON_ACOMP0_POS_SEL_POS (22U) +#define AON_ACOMP0_POS_SEL_LEN (4U) +#define AON_ACOMP0_POS_SEL_MSK (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS) +#define AON_ACOMP0_POS_SEL_UMSK (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)) +#define AON_ACOMP0_MUXEN AON_ACOMP0_MUXEN +#define AON_ACOMP0_MUXEN_POS (26U) +#define AON_ACOMP0_MUXEN_LEN (1U) +#define AON_ACOMP0_MUXEN_MSK (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS) +#define AON_ACOMP0_MUXEN_UMSK (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)) + +/* 0x904 : acomp1_ctrl */ +#define AON_ACOMP1_CTRL_OFFSET (0x904) +#define AON_ACOMP1_EN AON_ACOMP1_EN +#define AON_ACOMP1_EN_POS (0U) +#define AON_ACOMP1_EN_LEN (1U) +#define AON_ACOMP1_EN_MSK (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS) +#define AON_ACOMP1_EN_UMSK (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)) +#define AON_ACOMP1_HYST_SELN AON_ACOMP1_HYST_SELN +#define AON_ACOMP1_HYST_SELN_POS (4U) +#define AON_ACOMP1_HYST_SELN_LEN (3U) +#define AON_ACOMP1_HYST_SELN_MSK (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS) +#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)) +#define AON_ACOMP1_HYST_SELP AON_ACOMP1_HYST_SELP +#define AON_ACOMP1_HYST_SELP_POS (7U) +#define AON_ACOMP1_HYST_SELP_LEN (3U) +#define AON_ACOMP1_HYST_SELP_MSK (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS) +#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)) +#define AON_ACOMP1_BIAS_PROG AON_ACOMP1_BIAS_PROG +#define AON_ACOMP1_BIAS_PROG_POS (10U) +#define AON_ACOMP1_BIAS_PROG_LEN (2U) +#define AON_ACOMP1_BIAS_PROG_MSK (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS) +#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)) +#define AON_ACOMP1_LEVEL_SEL AON_ACOMP1_LEVEL_SEL +#define AON_ACOMP1_LEVEL_SEL_POS (12U) +#define AON_ACOMP1_LEVEL_SEL_LEN (6U) +#define AON_ACOMP1_LEVEL_SEL_MSK (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS) +#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)) +#define AON_ACOMP1_NEG_SEL AON_ACOMP1_NEG_SEL +#define AON_ACOMP1_NEG_SEL_POS (18U) +#define AON_ACOMP1_NEG_SEL_LEN (4U) +#define AON_ACOMP1_NEG_SEL_MSK (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS) +#define AON_ACOMP1_NEG_SEL_UMSK (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)) +#define AON_ACOMP1_POS_SEL AON_ACOMP1_POS_SEL +#define AON_ACOMP1_POS_SEL_POS (22U) +#define AON_ACOMP1_POS_SEL_LEN (4U) +#define AON_ACOMP1_POS_SEL_MSK (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS) +#define AON_ACOMP1_POS_SEL_UMSK (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)) +#define AON_ACOMP1_MUXEN AON_ACOMP1_MUXEN +#define AON_ACOMP1_MUXEN_POS (26U) +#define AON_ACOMP1_MUXEN_LEN (1U) +#define AON_ACOMP1_MUXEN_MSK (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS) +#define AON_ACOMP1_MUXEN_UMSK (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)) + +/* 0x908 : acomp_ctrl */ +#define AON_ACOMP_CTRL_OFFSET (0x908) +#define AON_ACOMP1_RSTN_ANA AON_ACOMP1_RSTN_ANA +#define AON_ACOMP1_RSTN_ANA_POS (0U) +#define AON_ACOMP1_RSTN_ANA_LEN (1U) +#define AON_ACOMP1_RSTN_ANA_MSK (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS) +#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)) +#define AON_ACOMP0_RSTN_ANA AON_ACOMP0_RSTN_ANA +#define AON_ACOMP0_RSTN_ANA_POS (1U) +#define AON_ACOMP0_RSTN_ANA_LEN (1U) +#define AON_ACOMP0_RSTN_ANA_MSK (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS) +#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)) +#define AON_ACOMP1_TEST_EN AON_ACOMP1_TEST_EN +#define AON_ACOMP1_TEST_EN_POS (8U) +#define AON_ACOMP1_TEST_EN_LEN (1U) +#define AON_ACOMP1_TEST_EN_MSK (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS) +#define AON_ACOMP1_TEST_EN_UMSK (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)) +#define AON_ACOMP0_TEST_EN AON_ACOMP0_TEST_EN +#define AON_ACOMP0_TEST_EN_POS (9U) +#define AON_ACOMP0_TEST_EN_LEN (1U) +#define AON_ACOMP0_TEST_EN_MSK (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS) +#define AON_ACOMP0_TEST_EN_UMSK (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)) +#define AON_ACOMP1_TEST_SEL AON_ACOMP1_TEST_SEL +#define AON_ACOMP1_TEST_SEL_POS (10U) +#define AON_ACOMP1_TEST_SEL_LEN (2U) +#define AON_ACOMP1_TEST_SEL_MSK (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS) +#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)) +#define AON_ACOMP0_TEST_SEL AON_ACOMP0_TEST_SEL +#define AON_ACOMP0_TEST_SEL_POS (12U) +#define AON_ACOMP0_TEST_SEL_LEN (2U) +#define AON_ACOMP0_TEST_SEL_MSK (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS) +#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)) +#define AON_ACOMP1_OUT_RAW AON_ACOMP1_OUT_RAW +#define AON_ACOMP1_OUT_RAW_POS (17U) +#define AON_ACOMP1_OUT_RAW_LEN (1U) +#define AON_ACOMP1_OUT_RAW_MSK (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS) +#define AON_ACOMP1_OUT_RAW_UMSK (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)) +#define AON_ACOMP0_OUT_RAW AON_ACOMP0_OUT_RAW +#define AON_ACOMP0_OUT_RAW_POS (19U) +#define AON_ACOMP0_OUT_RAW_LEN (1U) +#define AON_ACOMP0_OUT_RAW_MSK (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS) +#define AON_ACOMP0_OUT_RAW_UMSK (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)) +#define AON_ACOMP_RESERVED AON_ACOMP_RESERVED +#define AON_ACOMP_RESERVED_POS (24U) +#define AON_ACOMP_RESERVED_LEN (8U) +#define AON_ACOMP_RESERVED_MSK (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS) +#define AON_ACOMP_RESERVED_UMSK (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)) + +/* 0x90C : gpadc_reg_cmd */ +#define AON_GPADC_REG_CMD_OFFSET (0x90C) +#define AON_GPADC_GLOBAL_EN AON_GPADC_GLOBAL_EN +#define AON_GPADC_GLOBAL_EN_POS (0U) +#define AON_GPADC_GLOBAL_EN_LEN (1U) +#define AON_GPADC_GLOBAL_EN_MSK (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS) +#define AON_GPADC_GLOBAL_EN_UMSK (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)) +#define AON_GPADC_CONV_START AON_GPADC_CONV_START +#define AON_GPADC_CONV_START_POS (1U) +#define AON_GPADC_CONV_START_LEN (1U) +#define AON_GPADC_CONV_START_MSK (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS) +#define AON_GPADC_CONV_START_UMSK (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)) +#define AON_GPADC_SOFT_RST AON_GPADC_SOFT_RST +#define AON_GPADC_SOFT_RST_POS (2U) +#define AON_GPADC_SOFT_RST_LEN (1U) +#define AON_GPADC_SOFT_RST_MSK (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS) +#define AON_GPADC_SOFT_RST_UMSK (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)) +#define AON_GPADC_NEG_SEL AON_GPADC_NEG_SEL +#define AON_GPADC_NEG_SEL_POS (3U) +#define AON_GPADC_NEG_SEL_LEN (5U) +#define AON_GPADC_NEG_SEL_MSK (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS) +#define AON_GPADC_NEG_SEL_UMSK (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)) +#define AON_GPADC_POS_SEL AON_GPADC_POS_SEL +#define AON_GPADC_POS_SEL_POS (8U) +#define AON_GPADC_POS_SEL_LEN (5U) +#define AON_GPADC_POS_SEL_MSK (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS) +#define AON_GPADC_POS_SEL_UMSK (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)) +#define AON_GPADC_NEG_GND AON_GPADC_NEG_GND +#define AON_GPADC_NEG_GND_POS (13U) +#define AON_GPADC_NEG_GND_LEN (1U) +#define AON_GPADC_NEG_GND_MSK (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS) +#define AON_GPADC_NEG_GND_UMSK (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)) +#define AON_GPADC_MICBIAS_EN AON_GPADC_MICBIAS_EN +#define AON_GPADC_MICBIAS_EN_POS (14U) +#define AON_GPADC_MICBIAS_EN_LEN (1U) +#define AON_GPADC_MICBIAS_EN_MSK (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS) +#define AON_GPADC_MICBIAS_EN_UMSK (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)) +#define AON_GPADC_MICPGA_EN AON_GPADC_MICPGA_EN +#define AON_GPADC_MICPGA_EN_POS (15U) +#define AON_GPADC_MICPGA_EN_LEN (1U) +#define AON_GPADC_MICPGA_EN_MSK (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS) +#define AON_GPADC_MICPGA_EN_UMSK (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)) +#define AON_GPADC_BYP_MICBOOST AON_GPADC_BYP_MICBOOST +#define AON_GPADC_BYP_MICBOOST_POS (16U) +#define AON_GPADC_BYP_MICBOOST_LEN (1U) +#define AON_GPADC_BYP_MICBOOST_MSK (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS) +#define AON_GPADC_BYP_MICBOOST_UMSK (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)) +#define AON_GPADC_DWA_EN AON_GPADC_DWA_EN +#define AON_GPADC_DWA_EN_POS (18U) +#define AON_GPADC_DWA_EN_LEN (1U) +#define AON_GPADC_DWA_EN_MSK (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS) +#define AON_GPADC_DWA_EN_UMSK (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)) +#define AON_GPADC_MIC2_DIFF AON_GPADC_MIC2_DIFF +#define AON_GPADC_MIC2_DIFF_POS (19U) +#define AON_GPADC_MIC2_DIFF_LEN (1U) +#define AON_GPADC_MIC2_DIFF_MSK (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS) +#define AON_GPADC_MIC2_DIFF_UMSK (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)) +#define AON_GPADC_MIC1_DIFF AON_GPADC_MIC1_DIFF +#define AON_GPADC_MIC1_DIFF_POS (20U) +#define AON_GPADC_MIC1_DIFF_LEN (1U) +#define AON_GPADC_MIC1_DIFF_MSK (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS) +#define AON_GPADC_MIC1_DIFF_UMSK (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)) +#define AON_GPADC_MIC_PGA2_GAIN AON_GPADC_MIC_PGA2_GAIN +#define AON_GPADC_MIC_PGA2_GAIN_POS (21U) +#define AON_GPADC_MIC_PGA2_GAIN_LEN (2U) +#define AON_GPADC_MIC_PGA2_GAIN_MSK (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS) +#define AON_GPADC_MIC_PGA2_GAIN_UMSK (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)) +#define AON_GPADC_MICBOOST_32DB_EN AON_GPADC_MICBOOST_32DB_EN +#define AON_GPADC_MICBOOST_32DB_EN_POS (23U) +#define AON_GPADC_MICBOOST_32DB_EN_LEN (1U) +#define AON_GPADC_MICBOOST_32DB_EN_MSK (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS) +#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)) +#define AON_GPADC_CHIP_SEN_PU AON_GPADC_CHIP_SEN_PU +#define AON_GPADC_CHIP_SEN_PU_POS (27U) +#define AON_GPADC_CHIP_SEN_PU_LEN (1U) +#define AON_GPADC_CHIP_SEN_PU_MSK (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS) +#define AON_GPADC_CHIP_SEN_PU_UMSK (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)) +#define AON_GPADC_SEN_SEL AON_GPADC_SEN_SEL +#define AON_GPADC_SEN_SEL_POS (28U) +#define AON_GPADC_SEN_SEL_LEN (2U) +#define AON_GPADC_SEN_SEL_MSK (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS) +#define AON_GPADC_SEN_SEL_UMSK (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)) +#define AON_GPADC_SEN_TEST_EN AON_GPADC_SEN_TEST_EN +#define AON_GPADC_SEN_TEST_EN_POS (30U) +#define AON_GPADC_SEN_TEST_EN_LEN (1U) +#define AON_GPADC_SEN_TEST_EN_MSK (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS) +#define AON_GPADC_SEN_TEST_EN_UMSK (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)) + +/* 0x910 : gpadc_reg_config1 */ +#define AON_GPADC_REG_CONFIG1_OFFSET (0x910) +#define AON_GPADC_CAL_OS_EN AON_GPADC_CAL_OS_EN +#define AON_GPADC_CAL_OS_EN_POS (0U) +#define AON_GPADC_CAL_OS_EN_LEN (1U) +#define AON_GPADC_CAL_OS_EN_MSK (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS) +#define AON_GPADC_CAL_OS_EN_UMSK (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)) +#define AON_GPADC_CONT_CONV_EN AON_GPADC_CONT_CONV_EN +#define AON_GPADC_CONT_CONV_EN_POS (1U) +#define AON_GPADC_CONT_CONV_EN_LEN (1U) +#define AON_GPADC_CONT_CONV_EN_MSK (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS) +#define AON_GPADC_CONT_CONV_EN_UMSK (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)) +#define AON_GPADC_RES_SEL AON_GPADC_RES_SEL +#define AON_GPADC_RES_SEL_POS (2U) +#define AON_GPADC_RES_SEL_LEN (3U) +#define AON_GPADC_RES_SEL_MSK (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS) +#define AON_GPADC_RES_SEL_UMSK (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)) +#define AON_GPADC_CLK_ANA_INV AON_GPADC_CLK_ANA_INV +#define AON_GPADC_CLK_ANA_INV_POS (17U) +#define AON_GPADC_CLK_ANA_INV_LEN (1U) +#define AON_GPADC_CLK_ANA_INV_MSK (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS) +#define AON_GPADC_CLK_ANA_INV_UMSK (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)) +#define AON_GPADC_CLK_DIV_RATIO AON_GPADC_CLK_DIV_RATIO +#define AON_GPADC_CLK_DIV_RATIO_POS (18U) +#define AON_GPADC_CLK_DIV_RATIO_LEN (3U) +#define AON_GPADC_CLK_DIV_RATIO_MSK (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS) +#define AON_GPADC_CLK_DIV_RATIO_UMSK (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)) +#define AON_GPADC_SCAN_LENGTH AON_GPADC_SCAN_LENGTH +#define AON_GPADC_SCAN_LENGTH_POS (21U) +#define AON_GPADC_SCAN_LENGTH_LEN (4U) +#define AON_GPADC_SCAN_LENGTH_MSK (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS) +#define AON_GPADC_SCAN_LENGTH_UMSK (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)) +#define AON_GPADC_SCAN_EN AON_GPADC_SCAN_EN +#define AON_GPADC_SCAN_EN_POS (25U) +#define AON_GPADC_SCAN_EN_LEN (1U) +#define AON_GPADC_SCAN_EN_MSK (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS) +#define AON_GPADC_SCAN_EN_UMSK (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)) +#define AON_GPADC_DITHER_EN AON_GPADC_DITHER_EN +#define AON_GPADC_DITHER_EN_POS (26U) +#define AON_GPADC_DITHER_EN_LEN (1U) +#define AON_GPADC_DITHER_EN_MSK (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS) +#define AON_GPADC_DITHER_EN_UMSK (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)) +#define AON_GPADC_V11_SEL AON_GPADC_V11_SEL +#define AON_GPADC_V11_SEL_POS (27U) +#define AON_GPADC_V11_SEL_LEN (2U) +#define AON_GPADC_V11_SEL_MSK (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS) +#define AON_GPADC_V11_SEL_UMSK (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)) +#define AON_GPADC_V18_SEL AON_GPADC_V18_SEL +#define AON_GPADC_V18_SEL_POS (29U) +#define AON_GPADC_V18_SEL_LEN (2U) +#define AON_GPADC_V18_SEL_MSK (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS) +#define AON_GPADC_V18_SEL_UMSK (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)) + +/* 0x914 : gpadc_reg_config2 */ +#define AON_GPADC_REG_CONFIG2_OFFSET (0x914) +#define AON_GPADC_DIFF_MODE AON_GPADC_DIFF_MODE +#define AON_GPADC_DIFF_MODE_POS (2U) +#define AON_GPADC_DIFF_MODE_LEN (1U) +#define AON_GPADC_DIFF_MODE_MSK (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS) +#define AON_GPADC_DIFF_MODE_UMSK (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)) +#define AON_GPADC_VREF_SEL AON_GPADC_VREF_SEL +#define AON_GPADC_VREF_SEL_POS (3U) +#define AON_GPADC_VREF_SEL_LEN (1U) +#define AON_GPADC_VREF_SEL_MSK (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS) +#define AON_GPADC_VREF_SEL_UMSK (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)) +#define AON_GPADC_VBAT_EN AON_GPADC_VBAT_EN +#define AON_GPADC_VBAT_EN_POS (4U) +#define AON_GPADC_VBAT_EN_LEN (1U) +#define AON_GPADC_VBAT_EN_MSK (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS) +#define AON_GPADC_VBAT_EN_UMSK (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)) +#define AON_GPADC_TSEXT_SEL AON_GPADC_TSEXT_SEL +#define AON_GPADC_TSEXT_SEL_POS (5U) +#define AON_GPADC_TSEXT_SEL_LEN (1U) +#define AON_GPADC_TSEXT_SEL_MSK (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS) +#define AON_GPADC_TSEXT_SEL_UMSK (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)) +#define AON_GPADC_TS_EN AON_GPADC_TS_EN +#define AON_GPADC_TS_EN_POS (6U) +#define AON_GPADC_TS_EN_LEN (1U) +#define AON_GPADC_TS_EN_MSK (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS) +#define AON_GPADC_TS_EN_UMSK (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)) +#define AON_GPADC_PGA_VCM AON_GPADC_PGA_VCM +#define AON_GPADC_PGA_VCM_POS (7U) +#define AON_GPADC_PGA_VCM_LEN (2U) +#define AON_GPADC_PGA_VCM_MSK (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS) +#define AON_GPADC_PGA_VCM_UMSK (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)) +#define AON_GPADC_PGA_OS_CAL AON_GPADC_PGA_OS_CAL +#define AON_GPADC_PGA_OS_CAL_POS (9U) +#define AON_GPADC_PGA_OS_CAL_LEN (4U) +#define AON_GPADC_PGA_OS_CAL_MSK (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS) +#define AON_GPADC_PGA_OS_CAL_UMSK (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)) +#define AON_GPADC_PGA_EN AON_GPADC_PGA_EN +#define AON_GPADC_PGA_EN_POS (13U) +#define AON_GPADC_PGA_EN_LEN (1U) +#define AON_GPADC_PGA_EN_MSK (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS) +#define AON_GPADC_PGA_EN_UMSK (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)) +#define AON_GPADC_PGA_VCMI_EN AON_GPADC_PGA_VCMI_EN +#define AON_GPADC_PGA_VCMI_EN_POS (14U) +#define AON_GPADC_PGA_VCMI_EN_LEN (1U) +#define AON_GPADC_PGA_VCMI_EN_MSK (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS) +#define AON_GPADC_PGA_VCMI_EN_UMSK (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)) +#define AON_GPADC_CHOP_MODE AON_GPADC_CHOP_MODE +#define AON_GPADC_CHOP_MODE_POS (15U) +#define AON_GPADC_CHOP_MODE_LEN (2U) +#define AON_GPADC_CHOP_MODE_MSK (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS) +#define AON_GPADC_CHOP_MODE_UMSK (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)) +#define AON_GPADC_BIAS_SEL AON_GPADC_BIAS_SEL +#define AON_GPADC_BIAS_SEL_POS (17U) +#define AON_GPADC_BIAS_SEL_LEN (1U) +#define AON_GPADC_BIAS_SEL_MSK (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS) +#define AON_GPADC_BIAS_SEL_UMSK (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)) +#define AON_GPADC_TEST_EN AON_GPADC_TEST_EN +#define AON_GPADC_TEST_EN_POS (18U) +#define AON_GPADC_TEST_EN_LEN (1U) +#define AON_GPADC_TEST_EN_MSK (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS) +#define AON_GPADC_TEST_EN_UMSK (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)) +#define AON_GPADC_TEST_SEL AON_GPADC_TEST_SEL +#define AON_GPADC_TEST_SEL_POS (19U) +#define AON_GPADC_TEST_SEL_LEN (3U) +#define AON_GPADC_TEST_SEL_MSK (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS) +#define AON_GPADC_TEST_SEL_UMSK (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)) +#define AON_GPADC_PGA2_GAIN AON_GPADC_PGA2_GAIN +#define AON_GPADC_PGA2_GAIN_POS (22U) +#define AON_GPADC_PGA2_GAIN_LEN (3U) +#define AON_GPADC_PGA2_GAIN_MSK (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS) +#define AON_GPADC_PGA2_GAIN_UMSK (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)) +#define AON_GPADC_PGA1_GAIN AON_GPADC_PGA1_GAIN +#define AON_GPADC_PGA1_GAIN_POS (25U) +#define AON_GPADC_PGA1_GAIN_LEN (3U) +#define AON_GPADC_PGA1_GAIN_MSK (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS) +#define AON_GPADC_PGA1_GAIN_UMSK (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)) +#define AON_GPADC_DLY_SEL AON_GPADC_DLY_SEL +#define AON_GPADC_DLY_SEL_POS (28U) +#define AON_GPADC_DLY_SEL_LEN (3U) +#define AON_GPADC_DLY_SEL_MSK (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS) +#define AON_GPADC_DLY_SEL_UMSK (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)) +#define AON_GPADC_TSVBE_LOW AON_GPADC_TSVBE_LOW +#define AON_GPADC_TSVBE_LOW_POS (31U) +#define AON_GPADC_TSVBE_LOW_LEN (1U) +#define AON_GPADC_TSVBE_LOW_MSK (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS) +#define AON_GPADC_TSVBE_LOW_UMSK (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)) + +/* 0x918 : adc converation sequence 1 */ +#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918) +#define AON_GPADC_SCAN_POS_0 AON_GPADC_SCAN_POS_0 +#define AON_GPADC_SCAN_POS_0_POS (0U) +#define AON_GPADC_SCAN_POS_0_LEN (5U) +#define AON_GPADC_SCAN_POS_0_MSK (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS) +#define AON_GPADC_SCAN_POS_0_UMSK (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)) +#define AON_GPADC_SCAN_POS_1 AON_GPADC_SCAN_POS_1 +#define AON_GPADC_SCAN_POS_1_POS (5U) +#define AON_GPADC_SCAN_POS_1_LEN (5U) +#define AON_GPADC_SCAN_POS_1_MSK (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS) +#define AON_GPADC_SCAN_POS_1_UMSK (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)) +#define AON_GPADC_SCAN_POS_2 AON_GPADC_SCAN_POS_2 +#define AON_GPADC_SCAN_POS_2_POS (10U) +#define AON_GPADC_SCAN_POS_2_LEN (5U) +#define AON_GPADC_SCAN_POS_2_MSK (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS) +#define AON_GPADC_SCAN_POS_2_UMSK (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)) +#define AON_GPADC_SCAN_POS_3 AON_GPADC_SCAN_POS_3 +#define AON_GPADC_SCAN_POS_3_POS (15U) +#define AON_GPADC_SCAN_POS_3_LEN (5U) +#define AON_GPADC_SCAN_POS_3_MSK (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS) +#define AON_GPADC_SCAN_POS_3_UMSK (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)) +#define AON_GPADC_SCAN_POS_4 AON_GPADC_SCAN_POS_4 +#define AON_GPADC_SCAN_POS_4_POS (20U) +#define AON_GPADC_SCAN_POS_4_LEN (5U) +#define AON_GPADC_SCAN_POS_4_MSK (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS) +#define AON_GPADC_SCAN_POS_4_UMSK (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)) +#define AON_GPADC_SCAN_POS_5 AON_GPADC_SCAN_POS_5 +#define AON_GPADC_SCAN_POS_5_POS (25U) +#define AON_GPADC_SCAN_POS_5_LEN (5U) +#define AON_GPADC_SCAN_POS_5_MSK (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS) +#define AON_GPADC_SCAN_POS_5_UMSK (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)) + +/* 0x91C : adc converation sequence 2 */ +#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C) +#define AON_GPADC_SCAN_POS_6 AON_GPADC_SCAN_POS_6 +#define AON_GPADC_SCAN_POS_6_POS (0U) +#define AON_GPADC_SCAN_POS_6_LEN (5U) +#define AON_GPADC_SCAN_POS_6_MSK (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS) +#define AON_GPADC_SCAN_POS_6_UMSK (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)) +#define AON_GPADC_SCAN_POS_7 AON_GPADC_SCAN_POS_7 +#define AON_GPADC_SCAN_POS_7_POS (5U) +#define AON_GPADC_SCAN_POS_7_LEN (5U) +#define AON_GPADC_SCAN_POS_7_MSK (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS) +#define AON_GPADC_SCAN_POS_7_UMSK (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)) +#define AON_GPADC_SCAN_POS_8 AON_GPADC_SCAN_POS_8 +#define AON_GPADC_SCAN_POS_8_POS (10U) +#define AON_GPADC_SCAN_POS_8_LEN (5U) +#define AON_GPADC_SCAN_POS_8_MSK (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS) +#define AON_GPADC_SCAN_POS_8_UMSK (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)) +#define AON_GPADC_SCAN_POS_9 AON_GPADC_SCAN_POS_9 +#define AON_GPADC_SCAN_POS_9_POS (15U) +#define AON_GPADC_SCAN_POS_9_LEN (5U) +#define AON_GPADC_SCAN_POS_9_MSK (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS) +#define AON_GPADC_SCAN_POS_9_UMSK (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)) +#define AON_GPADC_SCAN_POS_10 AON_GPADC_SCAN_POS_10 +#define AON_GPADC_SCAN_POS_10_POS (20U) +#define AON_GPADC_SCAN_POS_10_LEN (5U) +#define AON_GPADC_SCAN_POS_10_MSK (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS) +#define AON_GPADC_SCAN_POS_10_UMSK (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)) +#define AON_GPADC_SCAN_POS_11 AON_GPADC_SCAN_POS_11 +#define AON_GPADC_SCAN_POS_11_POS (25U) +#define AON_GPADC_SCAN_POS_11_LEN (5U) +#define AON_GPADC_SCAN_POS_11_MSK (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS) +#define AON_GPADC_SCAN_POS_11_UMSK (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)) + +/* 0x920 : adc converation sequence 3 */ +#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920) +#define AON_GPADC_SCAN_NEG_0 AON_GPADC_SCAN_NEG_0 +#define AON_GPADC_SCAN_NEG_0_POS (0U) +#define AON_GPADC_SCAN_NEG_0_LEN (5U) +#define AON_GPADC_SCAN_NEG_0_MSK (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS) +#define AON_GPADC_SCAN_NEG_0_UMSK (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)) +#define AON_GPADC_SCAN_NEG_1 AON_GPADC_SCAN_NEG_1 +#define AON_GPADC_SCAN_NEG_1_POS (5U) +#define AON_GPADC_SCAN_NEG_1_LEN (5U) +#define AON_GPADC_SCAN_NEG_1_MSK (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS) +#define AON_GPADC_SCAN_NEG_1_UMSK (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)) +#define AON_GPADC_SCAN_NEG_2 AON_GPADC_SCAN_NEG_2 +#define AON_GPADC_SCAN_NEG_2_POS (10U) +#define AON_GPADC_SCAN_NEG_2_LEN (5U) +#define AON_GPADC_SCAN_NEG_2_MSK (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS) +#define AON_GPADC_SCAN_NEG_2_UMSK (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)) +#define AON_GPADC_SCAN_NEG_3 AON_GPADC_SCAN_NEG_3 +#define AON_GPADC_SCAN_NEG_3_POS (15U) +#define AON_GPADC_SCAN_NEG_3_LEN (5U) +#define AON_GPADC_SCAN_NEG_3_MSK (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS) +#define AON_GPADC_SCAN_NEG_3_UMSK (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)) +#define AON_GPADC_SCAN_NEG_4 AON_GPADC_SCAN_NEG_4 +#define AON_GPADC_SCAN_NEG_4_POS (20U) +#define AON_GPADC_SCAN_NEG_4_LEN (5U) +#define AON_GPADC_SCAN_NEG_4_MSK (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS) +#define AON_GPADC_SCAN_NEG_4_UMSK (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)) +#define AON_GPADC_SCAN_NEG_5 AON_GPADC_SCAN_NEG_5 +#define AON_GPADC_SCAN_NEG_5_POS (25U) +#define AON_GPADC_SCAN_NEG_5_LEN (5U) +#define AON_GPADC_SCAN_NEG_5_MSK (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS) +#define AON_GPADC_SCAN_NEG_5_UMSK (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)) + +/* 0x924 : adc converation sequence 4 */ +#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924) +#define AON_GPADC_SCAN_NEG_6 AON_GPADC_SCAN_NEG_6 +#define AON_GPADC_SCAN_NEG_6_POS (0U) +#define AON_GPADC_SCAN_NEG_6_LEN (5U) +#define AON_GPADC_SCAN_NEG_6_MSK (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS) +#define AON_GPADC_SCAN_NEG_6_UMSK (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)) +#define AON_GPADC_SCAN_NEG_7 AON_GPADC_SCAN_NEG_7 +#define AON_GPADC_SCAN_NEG_7_POS (5U) +#define AON_GPADC_SCAN_NEG_7_LEN (5U) +#define AON_GPADC_SCAN_NEG_7_MSK (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS) +#define AON_GPADC_SCAN_NEG_7_UMSK (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)) +#define AON_GPADC_SCAN_NEG_8 AON_GPADC_SCAN_NEG_8 +#define AON_GPADC_SCAN_NEG_8_POS (10U) +#define AON_GPADC_SCAN_NEG_8_LEN (5U) +#define AON_GPADC_SCAN_NEG_8_MSK (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS) +#define AON_GPADC_SCAN_NEG_8_UMSK (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)) +#define AON_GPADC_SCAN_NEG_9 AON_GPADC_SCAN_NEG_9 +#define AON_GPADC_SCAN_NEG_9_POS (15U) +#define AON_GPADC_SCAN_NEG_9_LEN (5U) +#define AON_GPADC_SCAN_NEG_9_MSK (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS) +#define AON_GPADC_SCAN_NEG_9_UMSK (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)) +#define AON_GPADC_SCAN_NEG_10 AON_GPADC_SCAN_NEG_10 +#define AON_GPADC_SCAN_NEG_10_POS (20U) +#define AON_GPADC_SCAN_NEG_10_LEN (5U) +#define AON_GPADC_SCAN_NEG_10_MSK (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS) +#define AON_GPADC_SCAN_NEG_10_UMSK (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)) +#define AON_GPADC_SCAN_NEG_11 AON_GPADC_SCAN_NEG_11 +#define AON_GPADC_SCAN_NEG_11_POS (25U) +#define AON_GPADC_SCAN_NEG_11_LEN (5U) +#define AON_GPADC_SCAN_NEG_11_MSK (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS) +#define AON_GPADC_SCAN_NEG_11_UMSK (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)) + +/* 0x928 : gpadc_reg_status */ +#define AON_GPADC_REG_STATUS_OFFSET (0x928) +#define AON_GPADC_DATA_RDY AON_GPADC_DATA_RDY +#define AON_GPADC_DATA_RDY_POS (0U) +#define AON_GPADC_DATA_RDY_LEN (1U) +#define AON_GPADC_DATA_RDY_MSK (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS) +#define AON_GPADC_DATA_RDY_UMSK (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)) +#define AON_GPADC_RESERVED AON_GPADC_RESERVED +#define AON_GPADC_RESERVED_POS (16U) +#define AON_GPADC_RESERVED_LEN (16U) +#define AON_GPADC_RESERVED_MSK (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS) +#define AON_GPADC_RESERVED_UMSK (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)) + +/* 0x92C : gpadc_reg_isr */ +#define AON_GPADC_REG_ISR_OFFSET (0x92C) +#define AON_GPADC_NEG_SATUR AON_GPADC_NEG_SATUR +#define AON_GPADC_NEG_SATUR_POS (0U) +#define AON_GPADC_NEG_SATUR_LEN (1U) +#define AON_GPADC_NEG_SATUR_MSK (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS) +#define AON_GPADC_NEG_SATUR_UMSK (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)) +#define AON_GPADC_POS_SATUR AON_GPADC_POS_SATUR +#define AON_GPADC_POS_SATUR_POS (1U) +#define AON_GPADC_POS_SATUR_LEN (1U) +#define AON_GPADC_POS_SATUR_MSK (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS) +#define AON_GPADC_POS_SATUR_UMSK (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)) +#define AON_GPADC_NEG_SATUR_CLR AON_GPADC_NEG_SATUR_CLR +#define AON_GPADC_NEG_SATUR_CLR_POS (4U) +#define AON_GPADC_NEG_SATUR_CLR_LEN (1U) +#define AON_GPADC_NEG_SATUR_CLR_MSK (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS) +#define AON_GPADC_NEG_SATUR_CLR_UMSK (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)) +#define AON_GPADC_POS_SATUR_CLR AON_GPADC_POS_SATUR_CLR +#define AON_GPADC_POS_SATUR_CLR_POS (5U) +#define AON_GPADC_POS_SATUR_CLR_LEN (1U) +#define AON_GPADC_POS_SATUR_CLR_MSK (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS) +#define AON_GPADC_POS_SATUR_CLR_UMSK (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)) +#define AON_GPADC_NEG_SATUR_MASK AON_GPADC_NEG_SATUR_MASK +#define AON_GPADC_NEG_SATUR_MASK_POS (8U) +#define AON_GPADC_NEG_SATUR_MASK_LEN (1U) +#define AON_GPADC_NEG_SATUR_MASK_MSK (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS) +#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)) +#define AON_GPADC_POS_SATUR_MASK AON_GPADC_POS_SATUR_MASK +#define AON_GPADC_POS_SATUR_MASK_POS (9U) +#define AON_GPADC_POS_SATUR_MASK_LEN (1U) +#define AON_GPADC_POS_SATUR_MASK_MSK (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS) +#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)) + +/* 0x930 : gpadc_reg_result */ +#define AON_GPADC_REG_RESULT_OFFSET (0x930) +#define AON_GPADC_DATA_OUT AON_GPADC_DATA_OUT +#define AON_GPADC_DATA_OUT_POS (0U) +#define AON_GPADC_DATA_OUT_LEN (26U) +#define AON_GPADC_DATA_OUT_MSK (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS) +#define AON_GPADC_DATA_OUT_UMSK (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)) + +/* 0x934 : gpadc_reg_raw_result */ +#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934) +#define AON_GPADC_RAW_DATA AON_GPADC_RAW_DATA +#define AON_GPADC_RAW_DATA_POS (0U) +#define AON_GPADC_RAW_DATA_LEN (12U) +#define AON_GPADC_RAW_DATA_MSK (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS) +#define AON_GPADC_RAW_DATA_UMSK (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)) + +/* 0x938 : gpadc_reg_define */ +#define AON_GPADC_REG_DEFINE_OFFSET (0x938) +#define AON_GPADC_OS_CAL_DATA AON_GPADC_OS_CAL_DATA +#define AON_GPADC_OS_CAL_DATA_POS (0U) +#define AON_GPADC_OS_CAL_DATA_LEN (16U) +#define AON_GPADC_OS_CAL_DATA_MSK (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS) +#define AON_GPADC_OS_CAL_DATA_UMSK (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)) + +/* 0x93C : hbncore_resv0 */ +#define AON_HBNCORE_RESV0_OFFSET (0x93C) +#define AON_HBNCORE_RESV0_DATA AON_HBNCORE_RESV0_DATA +#define AON_HBNCORE_RESV0_DATA_POS (0U) +#define AON_HBNCORE_RESV0_DATA_LEN (32U) +#define AON_HBNCORE_RESV0_DATA_MSK (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS) +#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)) + +/* 0x940 : hbncore_resv1 */ +#define AON_HBNCORE_RESV1_OFFSET (0x940) +#define AON_HBNCORE_RESV1_DATA AON_HBNCORE_RESV1_DATA +#define AON_HBNCORE_RESV1_DATA_POS (0U) +#define AON_HBNCORE_RESV1_DATA_LEN (32U) +#define AON_HBNCORE_RESV1_DATA_MSK (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS) +#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)) + +struct aon_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[2048]; + + /* 0x800 : aon */ + union { + struct + { + uint32_t aon_resv : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t pu_aon_dc_tbuf : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_19 : 7; /* [19:13], rsvd, 0x0 */ + uint32_t ldo11_rt_pulldown : 1; /* [ 20], r/w, 0x0 */ + uint32_t ldo11_rt_pulldown_sel : 1; /* [ 21], r/w, 0x0 */ + uint32_t sw_pu_ldo11_rt : 1; /* [ 22], r/w, 0x1 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon; + + /* 0x804 : aon_common */ + union { + struct + { + uint32_t tmux_aon : 3; /* [ 2: 0], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t ten_aon : 1; /* [ 4], r/w, 0x0 */ + uint32_t dten_xtal32k : 1; /* [ 5], r/w, 0x0 */ + uint32_t ten_xtal32k : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t ten_vddcore_aon : 1; /* [ 8], r/w, 0x0 */ + uint32_t ten_ldo11soc_aon : 1; /* [ 9], r/w, 0x0 */ + uint32_t ten_dcdc18_0_aon : 1; /* [ 10], r/w, 0x0 */ + uint32_t ten_dcdc18_1_aon : 1; /* [ 11], r/w, 0x0 */ + uint32_t ten_bg_sys_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t ten_ldo15rf_aon : 1; /* [ 16], r/w, 0x0 */ + uint32_t ten_xtal_aon : 1; /* [ 17], r/w, 0x0 */ + uint32_t dten_xtal_aon : 1; /* [ 18], r/w, 0x0 */ + uint32_t ten_mbg_aon : 1; /* [ 19], r/w, 0x0 */ + uint32_t ten_cip_misc_aon : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon_common; + + /* 0x808 : aon_misc */ + union { + struct + { + uint32_t sw_soc_en_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t sw_wb_en_aon : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon_misc; + + /* 0x80c reserved */ + uint8_t RESERVED0x80c[4]; + + /* 0x810 : bg_sys_top */ + union { + struct + { + uint32_t pmip_resv : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t pu_bg_sys_aon : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t bg_sys_start_ctrl_aon : 1; /* [ 12], r/w, 0x1 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } bg_sys_top; + + /* 0x814 : dcdc18_top_0 */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t dcdc18_vout_sel_aon : 5; /* [ 5: 1], r/w, 0x1b */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t dcdc18_vpfm_aon : 4; /* [11: 8], r/w, 0x7 */ + uint32_t dcdc18_osc_2m_mode_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t dcdc18_osc_freq_trim_aon : 4; /* [19:16], r/w, 0x8 */ + uint32_t dcdc18_slope_curr_sel_aon : 5; /* [24:20], r/w, 0x5 */ + uint32_t dcdc18_stop_osc_aon : 1; /* [ 25], r/w, 0x1 */ + uint32_t dcdc18_slow_osc_aon : 1; /* [ 26], r/w, 0x0 */ + uint32_t dcdc18_osc_inhibit_t2_aon : 1; /* [ 27], r/w, 0x1 */ + uint32_t dcdc18_sstart_time_aon : 2; /* [29:28], r/w, 0x0 */ + uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ + uint32_t dcdc18_rdy_aon : 1; /* [ 31], r, 0x1 */ + } BF; + uint32_t WORD; + } dcdc18_top_0; + + /* 0x818 : dcdc18_top_1 */ + union { + struct + { + uint32_t dcdc18_force_cs_zvs_aon : 1; /* [ 0], r/w, 0x0 */ + uint32_t dcdc18_cs_delay_aon : 3; /* [ 3: 1], r/w, 0x4 */ + uint32_t dcdc18_zvs_td_opt_aon : 3; /* [ 6: 4], r/w, 0x4 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t dcdc18_nonoverlap_td_aon : 5; /* [12: 8], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t dcdc18_rc_sel_aon : 4; /* [19:16], r/w, 0x8 */ + uint32_t dcdc18_chf_sel_aon : 4; /* [23:20], r/w, 0x1 */ + uint32_t dcdc18_cfb_sel_aon : 4; /* [27:24], r/w, 0x8 */ + uint32_t dcdc18_en_antiring_aon : 1; /* [ 28], r/w, 0x1 */ + uint32_t dcdc18_pulldown_aon : 1; /* [ 29], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } dcdc18_top_1; + + /* 0x81C : ldo11soc_and_dctest */ + union { + struct + { + uint32_t pu_ldo11soc_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t ldo11soc_sstart_sel_aon : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t ldo11soc_sstart_delay_aon : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t ldo11soc_pulldown_aon : 1; /* [ 10], r/w, 0x0 */ + uint32_t ldo11soc_pulldown_sel_aon : 1; /* [ 11], r/w, 0x1 */ + uint32_t ldo11soc_vth_sel_aon : 2; /* [13:12], r/w, 0x1 */ + uint32_t reserved_14_23 : 10; /* [23:14], rsvd, 0x0 */ + uint32_t ldo11soc_cc_aon : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t ldo11soc_rdy_aon : 1; /* [ 28], r, 0x1 */ + uint32_t ldo11soc_power_good_aon : 1; /* [ 29], r, 0x1 */ + uint32_t pu_vddcore_misc_aon : 1; /* [ 30], r/w, 0x1 */ + uint32_t pmip_dc_tp_out_en_aon : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ldo11soc_and_dctest; + + /* 0x820 : psw_irrcv */ + union { + struct + { + uint32_t pu_ir_psw_aon : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } psw_irrcv; + + /* 0x824 reserved */ + uint8_t RESERVED0x824[92]; + + /* 0x880 : rf_top_aon */ + union { + struct + { + uint32_t pu_mbg_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t pu_ldo15rf_aon : 1; /* [ 1], r/w, 0x1 */ + uint32_t pu_sfreg_aon : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t pu_xtal_buf_aon : 1; /* [ 4], r/w, 0x1 */ + uint32_t pu_xtal_aon : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t ldo15rf_sstart_sel_aon : 1; /* [ 8], r/w, 0x1 */ + uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t ldo15rf_pulldown_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t ldo15rf_pulldown_sel_aon : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t ldo15rf_vout_sel_aon : 3; /* [18:16], r/w, 0x2 */ + uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ + uint32_t ldo15rf_cc_aon : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t ldo15rf_bypass_aon : 1; /* [ 28], r/w, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rf_top_aon; + + /* 0x884 : xtal_cfg */ + union { + struct + { + uint32_t xtal_bk_aon : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t xtal_capcode_extra_aon : 1; /* [ 2], r/w, 0x0 */ + uint32_t xtal_ext_sel_aon : 1; /* [ 3], r/w, 0x0 */ + uint32_t xtal_buf_en_aon : 4; /* [ 7: 4], r/w, 0xf */ + uint32_t xtal_buf_hp_aon : 4; /* [11: 8], r/w, 0x0 */ + uint32_t xtal_fast_startup_aon : 1; /* [ 12], r/w, 0x1 */ + uint32_t xtal_sleep_aon : 1; /* [ 13], r/w, 0x1 */ + uint32_t xtal_amp_ctrl_aon : 2; /* [15:14], r/w, 0x3 */ + uint32_t xtal_capcode_out_aon : 6; /* [21:16], r/w, 0x10 */ + uint32_t xtal_capcode_in_aon : 6; /* [27:22], r/w, 0x10 */ + uint32_t xtal_gm_boost_aon : 2; /* [29:28], r/w, 0x3 */ + uint32_t xtal_rdy_sel_aon : 2; /* [31:30], r/w, 0x2 */ + } BF; + uint32_t WORD; + } xtal_cfg; + + /* 0x888 : tsen */ + union { + struct + { + uint32_t tsen_refcode_corner : 12; /* [11: 0], r/w, 0x8ff */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t tsen_refcode_rfcal : 12; /* [27:16], r/w, 0x8ff */ + uint32_t xtal_rdy : 1; /* [ 28], r, 0x1 */ + uint32_t xtal_inn_cfg_en_aon : 1; /* [ 29], r/w, 0x1 */ + uint32_t xtal_rdy_int_sel_aon : 2; /* [31:30], r/w, 0x1 */ + } BF; + uint32_t WORD; + } tsen; + + /* 0x88c reserved */ + uint8_t RESERVED0x88c[116]; + + /* 0x900 : acomp0_ctrl */ + union { + struct + { + uint32_t acomp0_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t acomp0_hyst_seln : 3; /* [ 6: 4], r/w, 0x0 */ + uint32_t acomp0_hyst_selp : 3; /* [ 9: 7], r/w, 0x0 */ + uint32_t acomp0_bias_prog : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp0_level_sel : 6; /* [17:12], r/w, 0x0 */ + uint32_t acomp0_neg_sel : 4; /* [21:18], r/w, 0x0 */ + uint32_t acomp0_pos_sel : 4; /* [25:22], r/w, 0x0 */ + uint32_t acomp0_muxen : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } acomp0_ctrl; + + /* 0x904 : acomp1_ctrl */ + union { + struct + { + uint32_t acomp1_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t acomp1_hyst_seln : 3; /* [ 6: 4], r/w, 0x0 */ + uint32_t acomp1_hyst_selp : 3; /* [ 9: 7], r/w, 0x0 */ + uint32_t acomp1_bias_prog : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp1_level_sel : 6; /* [17:12], r/w, 0x0 */ + uint32_t acomp1_neg_sel : 4; /* [21:18], r/w, 0x0 */ + uint32_t acomp1_pos_sel : 4; /* [25:22], r/w, 0x0 */ + uint32_t acomp1_muxen : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } acomp1_ctrl; + + /* 0x908 : acomp_ctrl */ + union { + struct + { + uint32_t acomp1_rstn_ana : 1; /* [ 0], r/w, 0x1 */ + uint32_t acomp0_rstn_ana : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t acomp1_test_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t acomp0_test_en : 1; /* [ 9], r/w, 0x0 */ + uint32_t acomp1_test_sel : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp0_test_sel : 2; /* [13:12], r/w, 0x0 */ + uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */ + uint32_t acomp1_out_raw : 1; /* [ 17], r, 0x0 */ + uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t acomp0_out_raw : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t acomp_reserved : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } acomp_ctrl; + + /* 0x90C : gpadc_reg_cmd */ + union { + struct + { + uint32_t gpadc_global_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpadc_conv_start : 1; /* [ 1], r/w, 0x0 */ + uint32_t gpadc_soft_rst : 1; /* [ 2], r/w, 0x0 */ + uint32_t gpadc_neg_sel : 5; /* [ 7: 3], r/w, 0xf */ + uint32_t gpadc_pos_sel : 5; /* [12: 8], r/w, 0xf */ + uint32_t gpadc_neg_gnd : 1; /* [ 13], r/w, 0x0 */ + uint32_t gpadc_micbias_en : 1; /* [ 14], r/w, 0x0 */ + uint32_t gpadc_micpga_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t gpadc_byp_micboost : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t gpadc_dwa_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t gpadc_mic2_diff : 1; /* [ 19], r/w, 0x0 */ + uint32_t gpadc_mic1_diff : 1; /* [ 20], r/w, 0x0 */ + uint32_t gpadc_mic_pga2_gain : 2; /* [22:21], r/w, 0x0 */ + uint32_t gpadc_micboost_32db_en : 1; /* [ 23], r/w, 0x0 */ + uint32_t reserved_24_26 : 3; /* [26:24], rsvd, 0x0 */ + uint32_t gpadc_chip_sen_pu : 1; /* [ 27], r/w, 0x0 */ + uint32_t gpadc_sen_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t gpadc_sen_test_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_cmd; + + /* 0x910 : gpadc_reg_config1 */ + union { + struct + { + uint32_t gpadc_cal_os_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpadc_cont_conv_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t gpadc_res_sel : 3; /* [ 4: 2], r/w, 0x0 */ + uint32_t reserved_5_16 : 12; /* [16: 5], rsvd, 0x0 */ + uint32_t gpadc_clk_ana_inv : 1; /* [ 17], r/w, 0x0 */ + uint32_t gpadc_clk_div_ratio : 3; /* [20:18], r/w, 0x3 */ + uint32_t gpadc_scan_length : 4; /* [24:21], r/w, 0x0 */ + uint32_t gpadc_scan_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t gpadc_dither_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t gpadc_v11_sel : 2; /* [28:27], r/w, 0x0 */ + uint32_t gpadc_v18_sel : 2; /* [30:29], r/w, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_config1; + + /* 0x914 : gpadc_reg_config2 */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t gpadc_diff_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t gpadc_vref_sel : 1; /* [ 3], r/w, 0x0 */ + uint32_t gpadc_vbat_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t gpadc_tsext_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t gpadc_ts_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t gpadc_pga_vcm : 2; /* [ 8: 7], r/w, 0x2 */ + uint32_t gpadc_pga_os_cal : 4; /* [12: 9], r/w, 0x8 */ + uint32_t gpadc_pga_en : 1; /* [ 13], r/w, 0x0 */ + uint32_t gpadc_pga_vcmi_en : 1; /* [ 14], r/w, 0x0 */ + uint32_t gpadc_chop_mode : 2; /* [16:15], r/w, 0x3 */ + uint32_t gpadc_bias_sel : 1; /* [ 17], r/w, 0x0 */ + uint32_t gpadc_test_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t gpadc_test_sel : 3; /* [21:19], r/w, 0x0 */ + uint32_t gpadc_pga2_gain : 3; /* [24:22], r/w, 0x0 */ + uint32_t gpadc_pga1_gain : 3; /* [27:25], r/w, 0x0 */ + uint32_t gpadc_dly_sel : 3; /* [30:28], r/w, 0x0 */ + uint32_t gpadc_tsvbe_low : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_config2; + + /* 0x918 : adc converation sequence 1 */ + union { + struct + { + uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_pos_2 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_pos_3 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_pos_4 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_pos_5 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_pos1; + + /* 0x91C : adc converation sequence 2 */ + union { + struct + { + uint32_t gpadc_scan_pos_6 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_pos_7 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_pos_8 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_pos_9 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_pos_10 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_pos_11 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_pos2; + + /* 0x920 : adc converation sequence 3 */ + union { + struct + { + uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_neg_2 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_neg_3 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_neg_4 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_neg_5 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_neg1; + + /* 0x924 : adc converation sequence 4 */ + union { + struct + { + uint32_t gpadc_scan_neg_6 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_neg_7 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_neg_8 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_neg_9 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_neg_10 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_neg_11 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_neg2; + + /* 0x928 : gpadc_reg_status */ + union { + struct + { + uint32_t gpadc_data_rdy : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ + uint32_t gpadc_reserved : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_status; + + /* 0x92C : gpadc_reg_isr */ + union { + struct + { + uint32_t gpadc_neg_satur : 1; /* [ 0], r, 0x0 */ + uint32_t gpadc_pos_satur : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t gpadc_neg_satur_clr : 1; /* [ 4], r/w, 0x0 */ + uint32_t gpadc_pos_satur_clr : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t gpadc_neg_satur_mask : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpadc_pos_satur_mask : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_isr; + + /* 0x930 : gpadc_reg_result */ + union { + struct + { + uint32_t gpadc_data_out : 26; /* [25: 0], r, 0x1ef0000 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_result; + + /* 0x934 : gpadc_reg_raw_result */ + union { + struct + { + uint32_t gpadc_raw_data : 12; /* [11: 0], r, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_raw_result; + + /* 0x938 : gpadc_reg_define */ + union { + struct + { + uint32_t gpadc_os_cal_data : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_define; + + /* 0x93C : hbncore_resv0 */ + union { + struct + { + uint32_t hbncore_resv0_data : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } hbncore_resv0; + + /* 0x940 : hbncore_resv1 */ + union { + struct + { + uint32_t hbncore_resv1_data : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } hbncore_resv1; +}; + +typedef volatile struct aon_reg aon_reg_t; + +#endif /* __AON_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/bl602.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/bl602.h new file mode 100644 index 0000000000000000000000000000000000000000..5bb3efcb8d6ba9b93076cc4a00f18307651deedc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/bl602.h @@ -0,0 +1,272 @@ +#ifndef __BL602_H__ +#define __BL602_H__ + +/** @addtogroup Configuration_section_for_RISCV + * @{ + */ + +/** + * @brief Configuration of the Processor and Core Peripherals + */ +#define SystemCoreClockSet(val) BL_WR_WORD(0x4000F108, val) +#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +#ifdef ARCH_ARM +#define IRQ_NUM_BASE 0 +#endif + +#ifdef ARCH_RISCV +#define IRQ_NUM_BASE 16 +#endif +/** + * @brief BL602 Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum { +#ifdef ARCH_ARM + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +#endif +#ifdef ARCH_RISCV + MSOFT_IRQn = 3, /*!< 3 RISCV machine software Interrupt */ + MTIME_IRQn = 7, /*!< 7 RISCV machine time Interrupt */ + MEXT_IRQn = 11, /*!< 11 RISCV external Interrupt */ + CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending Interrupt */ +#endif + /****** BL602 specific Interrupt Numbers **********************************************************************/ + BMX_ERR_IRQn = IRQ_NUM_BASE + 0, /*!< BMX Error Interrupt */ + BMX_TO_IRQn = IRQ_NUM_BASE + 1, /*!< BMX Timeout Interrupt */ + L1C_BMX_ERR_IRQn = IRQ_NUM_BASE + 2, /*!< L1C BMX Error Interrupt */ + L1C_BMX_TO_IRQn = IRQ_NUM_BASE + 3, /*!< L1C BMX Timeout Interrupt */ + SEC_BMX_ERR_IRQn = IRQ_NUM_BASE + 4, /*!< SEC BMX Error Interrupt */ + RF_TOP_INT0_IRQn = IRQ_NUM_BASE + 5, /*!< RF_TOP_INT0 Interrupt */ + RF_TOP_INT1_IRQn = IRQ_NUM_BASE + 6, /*!< RF_TOP_INT1 Interrupt */ + SDIO_IRQn = IRQ_NUM_BASE + 7, /*!< SDIO Interrupt */ + DMA_BMX_ERR_IRQn = IRQ_NUM_BASE + 8, /*!< DMA BMX Error Interrupt */ + SEC_GMAC_IRQn = IRQ_NUM_BASE + 9, /*!< SEC_ENG_GMAC_INT Interrupt */ + SEC_CDET_IRQn = IRQ_NUM_BASE + 10, /*!< SEC_ENG_CDET_INT Interrupt */ + SEC_PKA_IRQn = IRQ_NUM_BASE + 11, /*!< SEC_ENG_PKA_INT Interrupt */ + SEC_TRNG_IRQn = IRQ_NUM_BASE + 12, /*!< SEC_ENG_TRNG_INT Interrupt */ + SEC_AES_IRQn = IRQ_NUM_BASE + 13, /*!< SEC_ENG_AES_INT Interrupt */ + SEC_SHA_IRQn = IRQ_NUM_BASE + 14, /*!< SEC_ENG_SHA_INT Interrupt */ + DMA_ALL_IRQn = IRQ_NUM_BASE + 15, /*!< DMA ALL Interrupt */ + RESERVED0 = IRQ_NUM_BASE + 16, /*!< RESERVED Interrupt */ + RESERVED1 = IRQ_NUM_BASE + 17, /*!< RESERVED Interrupt */ + RESERVED2 = IRQ_NUM_BASE + 18, /*!< RESERVED Interrupt */ + IRTX_IRQn = IRQ_NUM_BASE + 19, /*!< IR TX Interrupt */ + IRRX_IRQn = IRQ_NUM_BASE + 20, /*!< IR RX Interrupt */ + RESERVED3 = IRQ_NUM_BASE + 21, /*!< RESERVED Interrupt */ + RESERVED4 = IRQ_NUM_BASE + 22, /*!< RESERVED Interrupt */ + SF_CTRL_IRQn = IRQ_NUM_BASE + 23, /*!< SF_CTRL Interrupt */ + RESERVED5 = IRQ_NUM_BASE + 24, /*!< RESERVED Interrupt */ + GPADC_DMA_IRQn = IRQ_NUM_BASE + 25, /*!< GPADC_DMA Interrupt */ + EFUSE_IRQn = IRQ_NUM_BASE + 26, /*!< Efuse Interrupt */ + SPI_IRQn = IRQ_NUM_BASE + 27, /*!< SPI Interrupt */ + RESERVED6 = IRQ_NUM_BASE + 28, /*!< RESERVED Interrupt */ + UART0_IRQn = IRQ_NUM_BASE + 29, /*!< UART Interrupt */ + UART1_IRQn = IRQ_NUM_BASE + 30, /*!< UART1 Interrupt */ + RESERVED7 = IRQ_NUM_BASE + 31, /*!< RESERVED Interrupt */ + I2C_IRQn = IRQ_NUM_BASE + 32, /*!< I2C Interrupt */ + RESERVED8 = IRQ_NUM_BASE + 33, /*!< RESERVED Interrupt */ + PWM_IRQn = IRQ_NUM_BASE + 34, /*!< PWM Interrupt */ + RESERVED9 = IRQ_NUM_BASE + 35, /*!< RESERVED Interrupt */ + TIMER_CH0_IRQn = IRQ_NUM_BASE + 36, /*!< Timer Channel 0 Interrupt */ + TIMER_CH1_IRQn = IRQ_NUM_BASE + 37, /*!< Timer Channel 1 Interrupt */ + TIMER_WDT_IRQn = IRQ_NUM_BASE + 38, /*!< Timer Watch Dog Interrupt */ + RESERVED10 = IRQ_NUM_BASE + 39, /*!< RESERVED Interrupt */ + RESERVED11 = IRQ_NUM_BASE + 40, /*!< RESERVED Interrupt */ + RESERVED12 = IRQ_NUM_BASE + 41, /*!< RESERVED Interrupt */ + RESERVED13 = IRQ_NUM_BASE + 42, /*!< RESERVED Interrupt */ + RESERVED14 = IRQ_NUM_BASE + 43, /*!< RESERVED Interrupt */ + GPIO_INT0_IRQn = IRQ_NUM_BASE + 44, /*!< RESERVED Interrupt */ + RESERVED16 = IRQ_NUM_BASE + 45, /*!< RESERVED Interrupt */ + RESERVED17 = IRQ_NUM_BASE + 46, /*!< RESERVED Interrupt */ + RESERVED18 = IRQ_NUM_BASE + 47, /*!< RESERVED Interrupt */ + RESERVED19 = IRQ_NUM_BASE + 48, /*!< RESERVED Interrupt */ + RESERVED20 = IRQ_NUM_BASE + 49, /*!< RESERVED Interrupt */ + PDS_WAKEUP_IRQn = IRQ_NUM_BASE + 50, /*!< PDS Wakeup Interrupt */ + HBN_OUT0_IRQn = IRQ_NUM_BASE + 51, /*!< Hibernate out 0 Interrupt */ + HBN_OUT1_IRQn = IRQ_NUM_BASE + 52, /*!< Hibernate out 1 Interrupt */ + BOR_IRQn = IRQ_NUM_BASE + 53, /*!< BOR Interrupt */ + WIFI_IRQn = IRQ_NUM_BASE + 54, /*!< WIFI To CPU Interrupt */ + BZ_PHY_IRQn = IRQ_NUM_BASE + 55, /*!< RESERVED Interrupt */ + BLE_IRQn = IRQ_NUM_BASE + 56, /*!< RESERVED Interrupt */ + MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE + 57, /*!< mac_int_tx_rx_timer Interrupt */ + MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE + 58, /*!< mac_int_tx_rx_misc Interrupt */ + MAC_RX_TRG_IRQn = IRQ_NUM_BASE + 59, /*!< mac_int_rx_trigger Interrupt */ + MAC_TX_TRG_IRQn = IRQ_NUM_BASE + 60, /*!< mac_int_tx_trigger Interrupt */ + MAC_GEN_IRQn = IRQ_NUM_BASE + 61, /*!< mac_int_gen Interrupt */ + MAC_PORT_TRG_IRQn = IRQ_NUM_BASE + 62, /*!< mac_int_port_trigger Interrupt */ + WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE + 63, /*!< wifi IPC public Interrupt */ + IRQn_LAST, +} IRQn_Type; + +/** + * @brief BL602 Memory Map Definitions + */ +#define BL602_FLASH_XIP_BASE 0x23000000 +#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000 +#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000 +#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000 +#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024) + +#define BL602_WRAM_BASE 0x42020000 +#define BL602_WRAM_END (0x42020000 + 176 * 1024) +#define BL602_WRAM_REMAP0_BASE 0x22020000 +#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024) +#define BL602_WRAM_REMAP1_BASE 0x32020000 +#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024) +#define BL602_WRAM_REMAP2_BASE 0x52020000 +#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024) + +#define BL602_TCM_BASE 0x22008000 +#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP0_BASE 0x32008000 +#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP1_BASE 0x42008000 +#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP2_BASE 0x52008000 +#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024) +/*@} end of group Memory_Map_Section */ + +/* BL602 peripherals base address */ +#define GLB_BASE ((uint32_t)0x40000000) +#define RF_BASE ((uint32_t)0x40001000) +#define GPIP_BASE ((uint32_t)0x40002000) /*!< AUX module base address */ +#define SEC_DBG_BASE ((uint32_t)0x40003000) /*!< Security Debug module base address */ +#define SEC_ENG_BASE ((uint32_t)0x40004000) /*!< Security Engine module base address */ +#define TZC_SEC_BASE ((uint32_t)0x40005000) /*!< Trustzone control security base address */ +#define TZC_NSEC_BASE ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */ +#define EF_DATA_BASE ((uint32_t)0x40007000) +#define EF_CTRL_BASE ((uint32_t)0x40007000) +#define CCI_BASE ((uint32_t)0x40008000) +#define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ +#define UART0_BASE ((uint32_t)0x4000A000) +#define UART1_BASE ((uint32_t)0x4000A100) +#define SPI_BASE ((uint32_t)0x4000A200) +#define I2C_BASE ((uint32_t)0x4000A300) +#define PWM_BASE ((uint32_t)0x4000A400) +#define TIMER_BASE ((uint32_t)0x4000A500) +#define IR_BASE ((uint32_t)0x4000A600) +#define SF_CTRL_BASE ((uint32_t)0x4000B000) +#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700) +#define DMA_BASE ((uint32_t)0x4000C000) +#define SDU_BASE ((uint32_t)0x4000D000) +#define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ +#define HBN_BASE ((uint32_t)0x4000F000) /*!< Hibernate module base address */ +#define AON_BASE ((uint32_t)0x4000F000) /*!< Always on module base address */ +#define HBN_RAM_BASE ((uint32_t)0x40010000) + +typedef enum { + BL_AHB_SLAVE1_GLB = 0x00, + BL_AHB_SLAVE1_RF = 0x01, + BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02, + BL_AHB_SLAVE1_SEC_DBG = 0x03, + BL_AHB_SLAVE1_SEC = 0x04, + BL_AHB_SLAVE1_TZ1 = 0x05, + BL_AHB_SLAVE1_TZ2 = 0x06, + BL_AHB_SLAVE1_EFUSE = 0x07, + BL_AHB_SLAVE1_CCI = 0x08, + BL_AHB_SLAVE1_L1C = 0x09, + BL_AHB_SLAVE1_RSVD0A = 0x0A, + BL_AHB_SLAVE1_SFC = 0x0B, + BL_AHB_SLAVE1_DMA = 0x0C, + BL_AHB_SLAVE1_SDU = 0x0D, + BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E, + BL_AHB_SLAVE1_RSVD0F = 0x0F, + BL_AHB_SLAVE1_UART0 = 0x10, + BL_AHB_SLAVE1_UART1 = 0x11, + BL_AHB_SLAVE1_SPI = 0x12, + BL_AHB_SLAVE1_I2C = 0x13, + BL_AHB_SLAVE1_PWM = 0x14, + BL_AHB_SLAVE1_TMR = 0x15, + BL_AHB_SLAVE1_IRR = 0x16, + BL_AHB_SLAVE1_CKS = 0x17, + BL_AHB_SLAVE1_MAX = 0x18, +} BL_AHB_Slave1_Type; + +typedef enum { + BL_AHB_SEC_ENG_AES0 = 0, + BL_AHB_SEC_ENG_AES1, + BL_AHB_SEC_ENG_SHA0, + BL_AHB_SEC_ENG_SHA1, +} BL_AHB_Sec_Eng_Type; + +typedef enum { + BL_AHB_DMA0_CH0 = 0, + BL_AHB_DMA0_CH1, + BL_AHB_DMA0_CH2, + BL_AHB_DMA0_CH3, + BL_AHB_DMA0_CH4, +} BL_AHB_DMA0_CHNL_Type; + +typedef enum { + BL_CORE_MASTER_IBUS_CPU = 0, + BL_CORE_MASTER_DBUS_CPU, + BL_CORE_MASTER_BUS_S2F, + BL_CORE_MASTER_MAX, +} BL_Core_Master_Type; + +typedef enum { + BL_CORE_SLAVE0_DTCM_CPU = 0, + BL_CORE_SLAVE0_MAX, +} BL_Core_Slave0_Type; + +typedef enum { + BL_CORE_SLAVE1_XIP_CPU = 0, + BL_CORE_SLAVE1_ITCM_CPU, + BL_CORE_SLAVE1_ROM, + BL_CORE_SLAVE1_MAX, +} BL_Core_Slave1_Type; + +typedef enum { + BL_CORE_SLAVE2_F2S = 0, + BL_CORE_SLAVE2_MAX, +} BL_Core_Slave2_Type; + +/** + * @} + */ +#include +#include +/* ARM CPU include files */ +#ifdef ARCH_ARM +#ifdef CPU_AP_CM4 +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#endif +#ifdef CPU_NP_CM0 +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#endif +#endif +/* RISCV CPU include files */ +#ifdef ARCH_RISCV +#ifdef __GNUC__ +#include "cmsis_compatible_gcc.h" +#include "clic.h" +#include "riscv_encoding.h" +#endif +#endif + +/** + * @} + */ + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/cci_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/cci_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..aa1188d90c0e3728b8b583d41f74c42406f25a07 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/cci_reg.h @@ -0,0 +1,192 @@ +/** + ****************************************************************************** + * @file cci_reg.h + * @version V1.2 + * @date 2019-11-12 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __CCI_REG_H__ +#define __CCI_REG_H__ + +#include "bl602.h" + +/* 0x0 : cci_cfg */ +#define CCI_CFG_OFFSET (0x0) +#define CCI_EN CCI_EN +#define CCI_EN_POS (0U) +#define CCI_EN_LEN (1U) +#define CCI_EN_MSK (((1U << CCI_EN_LEN) - 1) << CCI_EN_POS) +#define CCI_EN_UMSK (~(((1U << CCI_EN_LEN) - 1) << CCI_EN_POS)) +#define CCI_SLV_SEL_CCI2 CCI_SLV_SEL_CCI2 +#define CCI_SLV_SEL_CCI2_POS (1U) +#define CCI_SLV_SEL_CCI2_LEN (1U) +#define CCI_SLV_SEL_CCI2_MSK (((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS) +#define CCI_SLV_SEL_CCI2_UMSK (~(((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS)) +#define CCI_MAS_SEL_CCI2 CCI_MAS_SEL_CCI2 +#define CCI_MAS_SEL_CCI2_POS (2U) +#define CCI_MAS_SEL_CCI2_LEN (1U) +#define CCI_MAS_SEL_CCI2_MSK (((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS) +#define CCI_MAS_SEL_CCI2_UMSK (~(((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS)) +#define CCI_MAS_HW_MODE CCI_MAS_HW_MODE +#define CCI_MAS_HW_MODE_POS (3U) +#define CCI_MAS_HW_MODE_LEN (1U) +#define CCI_MAS_HW_MODE_MSK (((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS) +#define CCI_MAS_HW_MODE_UMSK (~(((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS)) +#define CCI_REG_M_CCI_SCLK_EN CCI_REG_M_CCI_SCLK_EN +#define CCI_REG_M_CCI_SCLK_EN_POS (4U) +#define CCI_REG_M_CCI_SCLK_EN_LEN (1U) +#define CCI_REG_M_CCI_SCLK_EN_MSK (((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS) +#define CCI_REG_M_CCI_SCLK_EN_UMSK (~(((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS)) +#define CCI_REG_DIV_M_CCI_SCLK CCI_REG_DIV_M_CCI_SCLK +#define CCI_REG_DIV_M_CCI_SCLK_POS (5U) +#define CCI_REG_DIV_M_CCI_SCLK_LEN (2U) +#define CCI_REG_DIV_M_CCI_SCLK_MSK (((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS) +#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS)) +#define CCI_CFG_CCI1_PRE_READ CCI_CFG_CCI1_PRE_READ +#define CCI_CFG_CCI1_PRE_READ_POS (7U) +#define CCI_CFG_CCI1_PRE_READ_LEN (1U) +#define CCI_CFG_CCI1_PRE_READ_MSK (((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS) +#define CCI_CFG_CCI1_PRE_READ_UMSK (~(((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS)) +#define CCI_REG_SCCI_CLK_INV CCI_REG_SCCI_CLK_INV +#define CCI_REG_SCCI_CLK_INV_POS (8U) +#define CCI_REG_SCCI_CLK_INV_LEN (1U) +#define CCI_REG_SCCI_CLK_INV_MSK (((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS) +#define CCI_REG_SCCI_CLK_INV_UMSK (~(((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS)) +#define CCI_REG_MCCI_CLK_INV CCI_REG_MCCI_CLK_INV +#define CCI_REG_MCCI_CLK_INV_POS (9U) +#define CCI_REG_MCCI_CLK_INV_LEN (1U) +#define CCI_REG_MCCI_CLK_INV_MSK (((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS) +#define CCI_REG_MCCI_CLK_INV_UMSK (~(((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS)) + +/* 0x4 : cci_addr */ +#define CCI_ADDR_OFFSET (0x4) +#define CCI_APB_CCI_ADDR CCI_APB_CCI_ADDR +#define CCI_APB_CCI_ADDR_POS (0U) +#define CCI_APB_CCI_ADDR_LEN (32U) +#define CCI_APB_CCI_ADDR_MSK (((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS) +#define CCI_APB_CCI_ADDR_UMSK (~(((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS)) + +/* 0x8 : cci_wdata */ +#define CCI_WDATA_OFFSET (0x8) +#define CCI_APB_CCI_WDATA CCI_APB_CCI_WDATA +#define CCI_APB_CCI_WDATA_POS (0U) +#define CCI_APB_CCI_WDATA_LEN (32U) +#define CCI_APB_CCI_WDATA_MSK (((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS) +#define CCI_APB_CCI_WDATA_UMSK (~(((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS)) + +/* 0xC : cci_rdata */ +#define CCI_RDATA_OFFSET (0xC) +#define CCI_APB_CCI_RDATA CCI_APB_CCI_RDATA +#define CCI_APB_CCI_RDATA_POS (0U) +#define CCI_APB_CCI_RDATA_LEN (32U) +#define CCI_APB_CCI_RDATA_MSK (((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS) +#define CCI_APB_CCI_RDATA_UMSK (~(((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS)) + +/* 0x10 : cci_ctl */ +#define CCI_CTL_OFFSET (0x10) +#define CCI_WRITE_FLAG CCI_WRITE_FLAG +#define CCI_WRITE_FLAG_POS (0U) +#define CCI_WRITE_FLAG_LEN (1U) +#define CCI_WRITE_FLAG_MSK (((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS) +#define CCI_WRITE_FLAG_UMSK (~(((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS)) +#define CCI_READ_FLAG CCI_READ_FLAG +#define CCI_READ_FLAG_POS (1U) +#define CCI_READ_FLAG_LEN (1U) +#define CCI_READ_FLAG_MSK (((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS) +#define CCI_READ_FLAG_UMSK (~(((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS)) +#define CCI_AHB_STATE CCI_AHB_STATE +#define CCI_AHB_STATE_POS (2U) +#define CCI_AHB_STATE_LEN (2U) +#define CCI_AHB_STATE_MSK (((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS) +#define CCI_AHB_STATE_UMSK (~(((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS)) + +struct cci_reg { + /* 0x0 : cci_cfg */ + union { + struct + { + uint32_t cci_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t cci_slv_sel_cci2 : 1; /* [ 1], r/w, 0x0 */ + uint32_t cci_mas_sel_cci2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t cci_mas_hw_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_m_cci_sclk_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_div_m_cci_sclk : 2; /* [ 6: 5], r/w, 0x1 */ + uint32_t cfg_cci1_pre_read : 1; /* [ 7], r/w, 0x0 */ + uint32_t reg_scci_clk_inv : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_mcci_clk_inv : 1; /* [ 9], r/w, 0x1 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cci_cfg; + + /* 0x4 : cci_addr */ + union { + struct + { + uint32_t apb_cci_addr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } cci_addr; + + /* 0x8 : cci_wdata */ + union { + struct + { + uint32_t apb_cci_wdata : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } cci_wdata; + + /* 0xC : cci_rdata */ + union { + struct + { + uint32_t apb_cci_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } cci_rdata; + + /* 0x10 : cci_ctl */ + union { + struct + { + uint32_t cci_write_flag : 1; /* [ 0], r, 0x0 */ + uint32_t cci_read_flag : 1; /* [ 1], r, 0x0 */ + uint32_t ahb_state : 2; /* [ 3: 2], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cci_ctl; +}; + +typedef volatile struct cci_reg cci_reg_t; + +#endif /* __CCI_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/cks_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/cks_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..cc7d31482ad4639da4a90883f1a8637c1d4da70c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/cks_reg.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file cks_reg.h + * @version V1.2 + * @date 2019-11-08 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __CKS_REG_H__ +#define __CKS_REG_H__ + +#include "bl602.h" + +/* 0x0 : cks_config */ +#define CKS_CONFIG_OFFSET (0x0) +#define CKS_CR_CKS_CLR CKS_CR_CKS_CLR +#define CKS_CR_CKS_CLR_POS (0U) +#define CKS_CR_CKS_CLR_LEN (1U) +#define CKS_CR_CKS_CLR_MSK (((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS) +#define CKS_CR_CKS_CLR_UMSK (~(((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS)) +#define CKS_CR_CKS_BYTE_SWAP CKS_CR_CKS_BYTE_SWAP +#define CKS_CR_CKS_BYTE_SWAP_POS (1U) +#define CKS_CR_CKS_BYTE_SWAP_LEN (1U) +#define CKS_CR_CKS_BYTE_SWAP_MSK (((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS) +#define CKS_CR_CKS_BYTE_SWAP_UMSK (~(((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS)) + +/* 0x4 : data_in */ +#define CKS_DATA_IN_OFFSET (0x4) +#define CKS_DATA_IN CKS_DATA_IN +#define CKS_DATA_IN_POS (0U) +#define CKS_DATA_IN_LEN (8U) +#define CKS_DATA_IN_MSK (((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS) +#define CKS_DATA_IN_UMSK (~(((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS)) + +/* 0x8 : cks_out */ +#define CKS_OUT_OFFSET (0x8) +#define CKS_OUT CKS_OUT +#define CKS_OUT_POS (0U) +#define CKS_OUT_LEN (16U) +#define CKS_OUT_MSK (((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS) +#define CKS_OUT_UMSK (~(((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS)) + +struct cks_reg { + /* 0x0 : cks_config */ + union { + struct + { + uint32_t cr_cks_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t cr_cks_byte_swap : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cks_config; + + /* 0x4 : data_in */ + union { + struct + { + uint32_t data_in : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } data_in; + + /* 0x8 : cks_out */ + union { + struct + { + uint32_t cks_out : 16; /* [15: 0], r, 0xffff */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cks_out; +}; + +typedef volatile struct cks_reg cks_reg_t; + +#endif /* __CKS_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/dma_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/dma_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..ba1ca6a96cf660adc35ae95d91d10a2201718c58 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/dma_reg.h @@ -0,0 +1,1258 @@ +/** + ****************************************************************************** + * @file dma_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __DMA_REG_H__ +#define __DMA_REG_H__ + +#include "bl602.h" + +/* 0x0 : DMA_IntStatus */ +#define DMA_INTSTATUS_OFFSET (0x0) +#define DMA_INTSTATUS DMA_INTSTATUS +#define DMA_INTSTATUS_POS (0U) +#define DMA_INTSTATUS_LEN (8U) +#define DMA_INTSTATUS_MSK (((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS) +#define DMA_INTSTATUS_UMSK (~(((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS)) + +/* 0x4 : DMA_IntTCStatus */ +#define DMA_INTTCSTATUS_OFFSET (0x4) +#define DMA_INTTCSTATUS DMA_INTTCSTATUS +#define DMA_INTTCSTATUS_POS (0U) +#define DMA_INTTCSTATUS_LEN (8U) +#define DMA_INTTCSTATUS_MSK (((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS) +#define DMA_INTTCSTATUS_UMSK (~(((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS)) + +/* 0x8 : DMA_IntTCClear */ +#define DMA_INTTCCLEAR_OFFSET (0x8) +#define DMA_INTTCCLEAR DMA_INTTCCLEAR +#define DMA_INTTCCLEAR_POS (0U) +#define DMA_INTTCCLEAR_LEN (8U) +#define DMA_INTTCCLEAR_MSK (((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS) +#define DMA_INTTCCLEAR_UMSK (~(((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS)) + +/* 0xC : DMA_IntErrorStatus */ +#define DMA_INTERRORSTATUS_OFFSET (0xC) +#define DMA_INTERRORSTATUS DMA_INTERRORSTATUS +#define DMA_INTERRORSTATUS_POS (0U) +#define DMA_INTERRORSTATUS_LEN (8U) +#define DMA_INTERRORSTATUS_MSK (((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS) +#define DMA_INTERRORSTATUS_UMSK (~(((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS)) + +/* 0x10 : DMA_IntErrClr */ +#define DMA_INTERRCLR_OFFSET (0x10) +#define DMA_INTERRCLR DMA_INTERRCLR +#define DMA_INTERRCLR_POS (0U) +#define DMA_INTERRCLR_LEN (8U) +#define DMA_INTERRCLR_MSK (((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS) +#define DMA_INTERRCLR_UMSK (~(((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS)) + +/* 0x14 : DMA_RawIntTCStatus */ +#define DMA_RAWINTTCSTATUS_OFFSET (0x14) +#define DMA_RAWINTTCSTATUS DMA_RAWINTTCSTATUS +#define DMA_RAWINTTCSTATUS_POS (0U) +#define DMA_RAWINTTCSTATUS_LEN (8U) +#define DMA_RAWINTTCSTATUS_MSK (((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS) +#define DMA_RAWINTTCSTATUS_UMSK (~(((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS)) + +/* 0x18 : DMA_RawIntErrorStatus */ +#define DMA_RAWINTERRORSTATUS_OFFSET (0x18) +#define DMA_RAWINTERRORSTATUS DMA_RAWINTERRORSTATUS +#define DMA_RAWINTERRORSTATUS_POS (0U) +#define DMA_RAWINTERRORSTATUS_LEN (8U) +#define DMA_RAWINTERRORSTATUS_MSK (((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS) +#define DMA_RAWINTERRORSTATUS_UMSK (~(((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS)) + +/* 0x1C : DMA_EnbldChns */ +#define DMA_ENBLDCHNS_OFFSET (0x1C) +#define DMA_ENABLEDCHANNELS DMA_ENABLEDCHANNELS +#define DMA_ENABLEDCHANNELS_POS (0U) +#define DMA_ENABLEDCHANNELS_LEN (8U) +#define DMA_ENABLEDCHANNELS_MSK (((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS) +#define DMA_ENABLEDCHANNELS_UMSK (~(((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS)) + +/* 0x20 : DMA_SoftBReq */ +#define DMA_SOFTBREQ_OFFSET (0x20) +#define DMA_SOFTBREQ DMA_SOFTBREQ +#define DMA_SOFTBREQ_POS (0U) +#define DMA_SOFTBREQ_LEN (32U) +#define DMA_SOFTBREQ_MSK (((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS) +#define DMA_SOFTBREQ_UMSK (~(((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS)) + +/* 0x24 : DMA_SoftSReq */ +#define DMA_SOFTSREQ_OFFSET (0x24) +#define DMA_SOFTSREQ DMA_SOFTSREQ +#define DMA_SOFTSREQ_POS (0U) +#define DMA_SOFTSREQ_LEN (32U) +#define DMA_SOFTSREQ_MSK (((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS) +#define DMA_SOFTSREQ_UMSK (~(((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS)) + +/* 0x28 : DMA_SoftLBReq */ +#define DMA_SOFTLBREQ_OFFSET (0x28) +#define DMA_SOFTLBREQ DMA_SOFTLBREQ +#define DMA_SOFTLBREQ_POS (0U) +#define DMA_SOFTLBREQ_LEN (32U) +#define DMA_SOFTLBREQ_MSK (((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS) +#define DMA_SOFTLBREQ_UMSK (~(((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS)) + +/* 0x2C : DMA_SoftLSReq */ +#define DMA_SOFTLSREQ_OFFSET (0x2C) +#define DMA_SOFTLSREQ DMA_SOFTLSREQ +#define DMA_SOFTLSREQ_POS (0U) +#define DMA_SOFTLSREQ_LEN (32U) +#define DMA_SOFTLSREQ_MSK (((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS) +#define DMA_SOFTLSREQ_UMSK (~(((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS)) + +/* 0x30 : DMA_Top_Config */ +#define DMA_TOP_CONFIG_OFFSET (0x30) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_M DMA_M +#define DMA_M_POS (1U) +#define DMA_M_LEN (1U) +#define DMA_M_MSK (((1U << DMA_M_LEN) - 1) << DMA_M_POS) +#define DMA_M_UMSK (~(((1U << DMA_M_LEN) - 1) << DMA_M_POS)) + +/* 0x34 : DMA_Sync */ +#define DMA_SYNC_OFFSET (0x34) +#define DMA_SYNC DMA_SYNC +#define DMA_SYNC_POS (0U) +#define DMA_SYNC_LEN (32U) +#define DMA_SYNC_MSK (((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS) +#define DMA_SYNC_UMSK (~(((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS)) + +/* 0x100 : DMA_C0SrcAddr */ +#define DMA_C0SRCADDR_OFFSET (0x100) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x104 : DMA_C0DstAddr */ +#define DMA_C0DSTADDR_OFFSET (0x104) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x108 : DMA_C0LLI */ +#define DMA_C0LLI_OFFSET (0x108) +#define DMA_LLI DMA_LLI +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x10C : DMA_C0Control */ +#define DMA_C0CONTROL_OFFSET (0x10C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (3U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (3U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_SLARGERD DMA_SLARGERD +#define DMA_SLARGERD_POS (24U) +#define DMA_SLARGERD_LEN (1U) +#define DMA_SLARGERD_MSK (((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS) +#define DMA_SLARGERD_UMSK (~(((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x110 : DMA_C0Config */ +#define DMA_C0CONFIG_OFFSET (0x110) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) +#define DMA_LLICOUNTER DMA_LLICOUNTER +#define DMA_LLICOUNTER_POS (20U) +#define DMA_LLICOUNTER_LEN (10U) +#define DMA_LLICOUNTER_MSK (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS) +#define DMA_LLICOUNTER_UMSK (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)) + +/* 0x200 : DMA_C1SrcAddr */ +#define DMA_C1SRCADDR_OFFSET (0x200) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x204 : DMA_C1DstAddr */ +#define DMA_C1DSTADDR_OFFSET (0x204) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x208 : DMA_C1LLI */ +#define DMA_C1LLI_OFFSET (0x208) +#define DMA_LLI DMA_LLI +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x20C : DMA_C1Control */ +#define DMA_C1CONTROL_OFFSET (0x20C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (3U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (3U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x210 : DMA_C1Config */ +#define DMA_C1CONFIG_OFFSET (0x210) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +/* 0x300 : DMA_C2SrcAddr */ +#define DMA_C2SRCADDR_OFFSET (0x300) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x304 : DMA_C2DstAddr */ +#define DMA_C2DSTADDR_OFFSET (0x304) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x308 : DMA_C2LLI */ +#define DMA_C2LLI_OFFSET (0x308) +#define DMA_LLI DMA_LLI +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x30C : DMA_C2Control */ +#define DMA_C2CONTROL_OFFSET (0x30C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (3U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (3U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x310 : DMA_C2Config */ +#define DMA_C2CONFIG_OFFSET (0x310) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +/* 0x400 : DMA_C3SrcAddr */ +#define DMA_C3SRCADDR_OFFSET (0x400) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x404 : DMA_C3DstAddr */ +#define DMA_C3DSTADDR_OFFSET (0x404) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x408 : DMA_C3LLI */ +#define DMA_C3LLI_OFFSET (0x408) +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x40C : DMA_C3Control */ +#define DMA_C3CONTROL_OFFSET (0x40C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (3U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (3U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x410 : DMA_C3Config */ +#define DMA_C3CONFIG_OFFSET (0x410) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +struct dma_reg { + /* 0x0 : DMA_IntStatus */ + union { + struct + { + uint32_t IntStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntStatus; + + /* 0x4 : DMA_IntTCStatus */ + union { + struct + { + uint32_t IntTCStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntTCStatus; + + /* 0x8 : DMA_IntTCClear */ + union { + struct + { + uint32_t IntTCClear : 8; /* [ 7: 0], w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntTCClear; + + /* 0xC : DMA_IntErrorStatus */ + union { + struct + { + uint32_t IntErrorStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntErrorStatus; + + /* 0x10 : DMA_IntErrClr */ + union { + struct + { + uint32_t IntErrClr : 8; /* [ 7: 0], w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntErrClr; + + /* 0x14 : DMA_RawIntTCStatus */ + union { + struct + { + uint32_t RawIntTCStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_RawIntTCStatus; + + /* 0x18 : DMA_RawIntErrorStatus */ + union { + struct + { + uint32_t RawIntErrorStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_RawIntErrorStatus; + + /* 0x1C : DMA_EnbldChns */ + union { + struct + { + uint32_t EnabledChannels : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_EnbldChns; + + /* 0x20 : DMA_SoftBReq */ + union { + struct + { + uint32_t SoftBReq : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SoftBReq; + + /* 0x24 : DMA_SoftSReq */ + union { + struct + { + uint32_t SoftSReq : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SoftSReq; + + /* 0x28 : DMA_SoftLBReq */ + union { + struct + { + uint32_t SoftLBReq : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SoftLBReq; + + /* 0x2C : DMA_SoftLSReq */ + union { + struct + { + uint32_t SoftLSReq : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SoftLSReq; + + /* 0x30 : DMA_Top_Config */ + union { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t M : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_Top_Config; + + /* 0x34 : DMA_Sync */ + union { + struct + { + uint32_t DMA_Sync : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_Sync; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[200]; + + /* 0x100 : DMA_C0SrcAddr */ + union { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0SrcAddr; + + /* 0x104 : DMA_C0DstAddr */ + union { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0DstAddr; + + /* 0x108 : DMA_C0LLI */ + union { + struct + { + uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0LLI; + + /* 0x10C : DMA_C0Control */ + union { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 3; /* [14:12], r/w, 0x1 */ + uint32_t DBSize : 3; /* [17:15], r/w, 0x1 */ + uint32_t SWidth : 3; /* [20:18], r/w, 0x2 */ + uint32_t DWidth : 3; /* [23:21], r/w, 0x2 */ + uint32_t SLargerD : 1; /* [ 24], r/w, 0x0 */ + uint32_t reserved_25 : 1; /* [ 25], rsvd, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0Control; + + /* 0x110 : DMA_C0Config */ + union { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0Config; + + /* 0x114 reserved */ + uint8_t RESERVED0x114[236]; + + /* 0x200 : DMA_C1SrcAddr */ + union { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1SrcAddr; + + /* 0x204 : DMA_C1DstAddr */ + union { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1DstAddr; + + /* 0x208 : DMA_C1LLI */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1LLI; + + /* 0x20C : DMA_C1Control */ + union { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 3; /* [14:12], r/w, 0x1 */ + uint32_t DBSize : 3; /* [17:15], r/w, 0x1 */ + uint32_t SWidth : 3; /* [20:18], r/w, 0x2 */ + uint32_t DWidth : 3; /* [23:21], r/w, 0x2 */ + uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1Control; + + /* 0x210 : DMA_C1Config */ + union { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1Config; + + /* 0x214 reserved */ + uint8_t RESERVED0x214[236]; + + /* 0x300 : DMA_C2SrcAddr */ + union { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2SrcAddr; + + /* 0x304 : DMA_C2DstAddr */ + union { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2DstAddr; + + /* 0x308 : DMA_C2LLI */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2LLI; + + /* 0x30C : DMA_C2Control */ + union { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 3; /* [14:12], r/w, 0x1 */ + uint32_t DBSize : 3; /* [17:15], r/w, 0x1 */ + uint32_t SWidth : 3; /* [20:18], r/w, 0x2 */ + uint32_t DWidth : 3; /* [23:21], r/w, 0x2 */ + uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2Control; + + /* 0x310 : DMA_C2Config */ + union { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2Config; + + /* 0x314 reserved */ + uint8_t RESERVED0x314[236]; + + /* 0x400 : DMA_C3SrcAddr */ + union { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3SrcAddr; + + /* 0x404 : DMA_C3DstAddr */ + union { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3DstAddr; + + /* 0x408 : DMA_C3LLI */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3LLI; + + /* 0x40C : DMA_C3Control */ + union { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 3; /* [14:12], r/w, 0x1 */ + uint32_t DBSize : 3; /* [17:15], r/w, 0x1 */ + uint32_t SWidth : 3; /* [20:18], r/w, 0x2 */ + uint32_t DWidth : 3; /* [23:21], r/w, 0x2 */ + uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3Control; + + /* 0x410 : DMA_C3Config */ + union { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3Config; +}; + +typedef volatile struct dma_reg dma_reg_t; + +/* 0x0 : DMA_SrcAddr */ +#define DMA_SRCADDR_OFFSET (0x0) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x4 : DMA_DstAddr */ +#define DMA_DSTADDR_OFFSET (0x4) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x8 : DMA_LLI */ +#define DMA_LLI_OFFSET (0x8) +#define DMA_LLI DMA_LLI +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0xc : DMA_Control */ +#define DMA_CONTROL_OFFSET (0xc) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (3U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (3U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_SLARGERD DMA_SLARGERD +#define DMA_SLARGERD_POS (24U) +#define DMA_SLARGERD_LEN (1U) +#define DMA_SLARGERD_MSK (((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS) +#define DMA_SLARGERD_UMSK (~(((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x10 : DMA_Config */ +#define DMA_CONFIG_OFFSET (0x10) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) +#define DMA_LLICOUNTER DMA_LLICOUNTER +#define DMA_LLICOUNTER_POS (20U) +#define DMA_LLICOUNTER_LEN (10U) +#define DMA_LLICOUNTER_MSK (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS) +#define DMA_LLICOUNTER_UMSK (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)) + +struct dma_channel_reg { + /* 0x0 : DMA_SrcAddr */ + union { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SrcAddr; + + /* 0x4 : DMA_DstAddr */ + union { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_DstAddr; + + /* 0x8 : DMA_LLI */ + union { + struct + { + uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_LLI; + + /* 0xc : DMA_Control */ + union { + struct DMA_Control_Reg { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 3; /* [14:12], r/w, 0x1 */ + uint32_t DBSize : 3; /* [17:15], r/w, 0x1 */ + uint32_t SWidth : 3; /* [20:18], r/w, 0x2 */ + uint32_t DWidth : 3; /* [23:21], r/w, 0x2 */ + uint32_t SLargerD : 1; /* [ 24], r/w, 0x0 */ + uint32_t reserved_25 : 1; /* [ 25], rsvd, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_Control; + + /* 0x10 : DMA_Config */ + union { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_Config; +}; + +typedef volatile struct dma_channel_reg dma_channel_reg_t; + +#define DMA_CHANNEL_OFFSET 0x100 + +#endif /* __DMA_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ef_ctrl_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ef_ctrl_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..772c9030c17c3d2c3e68dd3298a5f06857eb7850 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ef_ctrl_reg.h @@ -0,0 +1,812 @@ +/** + ****************************************************************************** + * @file ef_ctrl_reg.h + * @version V1.2 + * @date 2019-11-22 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_CTRL_REG_H__ +#define __EF_CTRL_REG_H__ + +#include "bl602.h" + +/* 0x800 : ef_if_ctrl_0 */ +#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)) +#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY +#define EF_CTRL_EF_IF_0_BUSY_POS (2U) +#define EF_CTRL_EF_IF_0_BUSY_LEN (1U) +#define EF_CTRL_EF_IF_0_BUSY_MSK (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS) +#define EF_CTRL_EF_IF_0_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)) +#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW +#define EF_CTRL_EF_IF_0_RW_POS (3U) +#define EF_CTRL_EF_IF_0_RW_LEN (1U) +#define EF_CTRL_EF_IF_0_RW_MSK (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS) +#define EF_CTRL_EF_IF_0_RW_UMSK (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)) +#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG +#define EF_CTRL_EF_IF_0_TRIG_POS (4U) +#define EF_CTRL_EF_IF_0_TRIG_LEN (1U) +#define EF_CTRL_EF_IF_0_TRIG_MSK (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS) +#define EF_CTRL_EF_IF_0_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)) +#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN +#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U) +#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U) +#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS) +#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)) +#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY +#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL EF_CTRL_EF_CLK_SAHB_DATA_SEL +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS (7U) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN (1U) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)) +#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG +#define EF_CTRL_EF_IF_POR_DIG_POS (16U) +#define EF_CTRL_EF_IF_POR_DIG_LEN (1U) +#define EF_CTRL_EF_IF_POR_DIG_MSK (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS) +#define EF_CTRL_EF_IF_POR_DIG_UMSK (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE EF_CTRL_EF_CLK_SAHB_DATA_GATE +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS (17U) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN (1U) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)) +#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN +#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U) +#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U) +#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS) +#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)) +#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT +#define EF_CTRL_EF_IF_0_INT_POS (20U) +#define EF_CTRL_EF_IF_0_INT_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_MSK (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS) +#define EF_CTRL_EF_IF_0_INT_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)) +#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR +#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U) +#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS) +#define EF_CTRL_EF_IF_0_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)) +#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET +#define EF_CTRL_EF_IF_0_INT_SET_POS (22U) +#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_SET_MSK (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS) +#define EF_CTRL_EF_IF_0_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC +#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)) + +/* 0x804 : ef_if_cyc_0 */ +#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804) +#define EF_CTRL_EF_IF_CYC_RD_DMY EF_CTRL_EF_IF_CYC_RD_DMY +#define EF_CTRL_EF_IF_CYC_RD_DMY_POS (0U) +#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS) +#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)) +#define EF_CTRL_EF_IF_CYC_RD_DAT EF_CTRL_EF_IF_CYC_RD_DAT +#define EF_CTRL_EF_IF_CYC_RD_DAT_POS (6U) +#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS) +#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)) +#define EF_CTRL_EF_IF_CYC_RD_ADR EF_CTRL_EF_IF_CYC_RD_ADR +#define EF_CTRL_EF_IF_CYC_RD_ADR_POS (12U) +#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS) +#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)) +#define EF_CTRL_EF_IF_CYC_CS EF_CTRL_EF_IF_CYC_CS +#define EF_CTRL_EF_IF_CYC_CS_POS (18U) +#define EF_CTRL_EF_IF_CYC_CS_LEN (6U) +#define EF_CTRL_EF_IF_CYC_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS) +#define EF_CTRL_EF_IF_CYC_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)) +#define EF_CTRL_EF_IF_CYC_PD_CS_S EF_CTRL_EF_IF_CYC_PD_CS_S +#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS (24U) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN (8U) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)) + +/* 0x808 : ef_if_cyc_1 */ +#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808) +#define EF_CTRL_EF_IF_CYC_PI EF_CTRL_EF_IF_CYC_PI +#define EF_CTRL_EF_IF_CYC_PI_POS (0U) +#define EF_CTRL_EF_IF_CYC_PI_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PI_MSK (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS) +#define EF_CTRL_EF_IF_CYC_PI_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)) +#define EF_CTRL_EF_IF_CYC_PP EF_CTRL_EF_IF_CYC_PP +#define EF_CTRL_EF_IF_CYC_PP_POS (6U) +#define EF_CTRL_EF_IF_CYC_PP_LEN (8U) +#define EF_CTRL_EF_IF_CYC_PP_MSK (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS) +#define EF_CTRL_EF_IF_CYC_PP_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)) +#define EF_CTRL_EF_IF_CYC_WR_ADR EF_CTRL_EF_IF_CYC_WR_ADR +#define EF_CTRL_EF_IF_CYC_WR_ADR_POS (14U) +#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN (6U) +#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS) +#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)) +#define EF_CTRL_EF_IF_CYC_PS_CS EF_CTRL_EF_IF_CYC_PS_CS +#define EF_CTRL_EF_IF_CYC_PS_CS_POS (20U) +#define EF_CTRL_EF_IF_CYC_PS_CS_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PS_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS) +#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)) +#define EF_CTRL_EF_IF_CYC_PD_CS_H EF_CTRL_EF_IF_CYC_PD_CS_H +#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS (26U) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)) + +/* 0x80C : ef_if_0_manual */ +#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C) +#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A +#define EF_CTRL_EF_IF_A_POS (0U) +#define EF_CTRL_EF_IF_A_LEN (10U) +#define EF_CTRL_EF_IF_A_MSK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS) +#define EF_CTRL_EF_IF_A_UMSK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)) +#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD +#define EF_CTRL_EF_IF_PD_POS (10U) +#define EF_CTRL_EF_IF_PD_LEN (1U) +#define EF_CTRL_EF_IF_PD_MSK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS) +#define EF_CTRL_EF_IF_PD_UMSK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)) +#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS +#define EF_CTRL_EF_IF_PS_POS (11U) +#define EF_CTRL_EF_IF_PS_LEN (1U) +#define EF_CTRL_EF_IF_PS_MSK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS) +#define EF_CTRL_EF_IF_PS_UMSK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)) +#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE +#define EF_CTRL_EF_IF_STROBE_POS (12U) +#define EF_CTRL_EF_IF_STROBE_LEN (1U) +#define EF_CTRL_EF_IF_STROBE_MSK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS) +#define EF_CTRL_EF_IF_STROBE_UMSK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)) +#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB +#define EF_CTRL_EF_IF_PGENB_POS (13U) +#define EF_CTRL_EF_IF_PGENB_LEN (1U) +#define EF_CTRL_EF_IF_PGENB_MSK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS) +#define EF_CTRL_EF_IF_PGENB_UMSK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)) +#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD +#define EF_CTRL_EF_IF_LOAD_POS (14U) +#define EF_CTRL_EF_IF_LOAD_LEN (1U) +#define EF_CTRL_EF_IF_LOAD_MSK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS) +#define EF_CTRL_EF_IF_LOAD_UMSK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)) +#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB +#define EF_CTRL_EF_IF_CSB_POS (15U) +#define EF_CTRL_EF_IF_CSB_LEN (1U) +#define EF_CTRL_EF_IF_CSB_MSK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS) +#define EF_CTRL_EF_IF_CSB_UMSK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)) +#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q +#define EF_CTRL_EF_IF_0_Q_POS (16U) +#define EF_CTRL_EF_IF_0_Q_LEN (8U) +#define EF_CTRL_EF_IF_0_Q_MSK (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS) +#define EF_CTRL_EF_IF_0_Q_UMSK (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)) + +/* 0x810 : ef_if_0_status */ +#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810) +#define EF_CTRL_EF_IF_0_STATUS EF_CTRL_EF_IF_0_STATUS +#define EF_CTRL_EF_IF_0_STATUS_POS (0U) +#define EF_CTRL_EF_IF_0_STATUS_LEN (32U) +#define EF_CTRL_EF_IF_0_STATUS_MSK (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS) +#define EF_CTRL_EF_IF_0_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)) + +/* 0x814 : ef_if_cfg_0 */ +#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814) +#define EF_CTRL_EF_IF_SF_AES_MODE EF_CTRL_EF_IF_SF_AES_MODE +#define EF_CTRL_EF_IF_SF_AES_MODE_POS (0U) +#define EF_CTRL_EF_IF_SF_AES_MODE_LEN (2U) +#define EF_CTRL_EF_IF_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS) +#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE EF_CTRL_EF_IF_SBOOT_SIGN_MODE +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS (2U) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN (2U) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)) +#define EF_CTRL_EF_IF_SBOOT_EN EF_CTRL_EF_IF_SBOOT_EN +#define EF_CTRL_EF_IF_SBOOT_EN_POS (4U) +#define EF_CTRL_EF_IF_SBOOT_EN_LEN (2U) +#define EF_CTRL_EF_IF_SBOOT_EN_MSK (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS) +#define EF_CTRL_EF_IF_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)) +#define EF_CTRL_EF_IF_CPU1_ENC_EN EF_CTRL_EF_IF_CPU1_ENC_EN +#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS (6U) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)) +#define EF_CTRL_EF_IF_CPU0_ENC_EN EF_CTRL_EF_IF_CPU0_ENC_EN +#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS (7U) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)) +#define EF_CTRL_EF_IF_BOOT_SEL EF_CTRL_EF_IF_BOOT_SEL +#define EF_CTRL_EF_IF_BOOT_SEL_POS (8U) +#define EF_CTRL_EF_IF_BOOT_SEL_LEN (4U) +#define EF_CTRL_EF_IF_BOOT_SEL_MSK (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS) +#define EF_CTRL_EF_IF_BOOT_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)) +#define EF_CTRL_EF_IF_SW_USAGE_1 EF_CTRL_EF_IF_SW_USAGE_1 +#define EF_CTRL_EF_IF_SW_USAGE_1_POS (12U) +#define EF_CTRL_EF_IF_SW_USAGE_1_LEN (2U) +#define EF_CTRL_EF_IF_SW_USAGE_1_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS) +#define EF_CTRL_EF_IF_SW_USAGE_1_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS)) +#define EF_CTRL_EF_IF_SDU_DIS EF_CTRL_EF_IF_SDU_DIS +#define EF_CTRL_EF_IF_SDU_DIS_POS (14U) +#define EF_CTRL_EF_IF_SDU_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SDU_DIS_MSK (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS) +#define EF_CTRL_EF_IF_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)) +#define EF_CTRL_EF_IF_BLE_DIS EF_CTRL_EF_IF_BLE_DIS +#define EF_CTRL_EF_IF_BLE_DIS_POS (15U) +#define EF_CTRL_EF_IF_BLE_DIS_LEN (1U) +#define EF_CTRL_EF_IF_BLE_DIS_MSK (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS) +#define EF_CTRL_EF_IF_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)) +#define EF_CTRL_EF_IF_WIFI_DIS EF_CTRL_EF_IF_WIFI_DIS +#define EF_CTRL_EF_IF_WIFI_DIS_POS (16U) +#define EF_CTRL_EF_IF_WIFI_DIS_LEN (1U) +#define EF_CTRL_EF_IF_WIFI_DIS_MSK (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS) +#define EF_CTRL_EF_IF_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN EF_CTRL_EF_IF_0_KEY_ENC_EN +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS (17U) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)) +#define EF_CTRL_EF_IF_CAM_DIS EF_CTRL_EF_IF_CAM_DIS +#define EF_CTRL_EF_IF_CAM_DIS_POS (18U) +#define EF_CTRL_EF_IF_CAM_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CAM_DIS_MSK (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS) +#define EF_CTRL_EF_IF_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)) +#define EF_CTRL_EF_IF_SF_DIS EF_CTRL_EF_IF_SF_DIS +#define EF_CTRL_EF_IF_SF_DIS_POS (19U) +#define EF_CTRL_EF_IF_SF_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SF_DIS_MSK (((1U << EF_CTRL_EF_IF_SF_DIS_LEN) - 1) << EF_CTRL_EF_IF_SF_DIS_POS) +#define EF_CTRL_EF_IF_SF_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SF_DIS_LEN) - 1) << EF_CTRL_EF_IF_SF_DIS_POS)) +#define EF_CTRL_EF_IF_CPU1_DIS EF_CTRL_EF_IF_CPU1_DIS +#define EF_CTRL_EF_IF_CPU1_DIS_POS (20U) +#define EF_CTRL_EF_IF_CPU1_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CPU1_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS) +#define EF_CTRL_EF_IF_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS EF_CTRL_EF_IF_CPU_RST_DBG_DIS +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS (21U) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_SE_DBG_DIS EF_CTRL_EF_IF_SE_DBG_DIS +#define EF_CTRL_EF_IF_SE_DBG_DIS_POS (22U) +#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS) +#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS EF_CTRL_EF_IF_EFUSE_DBG_DIS +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS (23U) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS EF_CTRL_EF_IF_DBG_JTAG_1_DIS +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS (24U) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN (2U) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS EF_CTRL_EF_IF_DBG_JTAG_0_DIS +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS (26U) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN (2U) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_MODE EF_CTRL_EF_IF_DBG_MODE +#define EF_CTRL_EF_IF_DBG_MODE_POS (28U) +#define EF_CTRL_EF_IF_DBG_MODE_LEN (4U) +#define EF_CTRL_EF_IF_DBG_MODE_MSK (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS) +#define EF_CTRL_EF_IF_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)) + +/* 0x818 : ef_sw_cfg_0 */ +#define EF_CTRL_EF_SW_CFG_0_OFFSET (0x818) +#define EF_CTRL_EF_SW_SF_AES_MODE EF_CTRL_EF_SW_SF_AES_MODE +#define EF_CTRL_EF_SW_SF_AES_MODE_POS (0U) +#define EF_CTRL_EF_SW_SF_AES_MODE_LEN (2U) +#define EF_CTRL_EF_SW_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS) +#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE EF_CTRL_EF_SW_SBOOT_SIGN_MODE +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS (2U) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN (2U) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)) +#define EF_CTRL_EF_SW_SBOOT_EN EF_CTRL_EF_SW_SBOOT_EN +#define EF_CTRL_EF_SW_SBOOT_EN_POS (4U) +#define EF_CTRL_EF_SW_SBOOT_EN_LEN (2U) +#define EF_CTRL_EF_SW_SBOOT_EN_MSK (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS) +#define EF_CTRL_EF_SW_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)) +#define EF_CTRL_EF_SW_CPU1_ENC_EN EF_CTRL_EF_SW_CPU1_ENC_EN +#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS (6U) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)) +#define EF_CTRL_EF_SW_CPU0_ENC_EN EF_CTRL_EF_SW_CPU0_ENC_EN +#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS (7U) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)) +#define EF_CTRL_EF_SW_SW_USAGE_1 EF_CTRL_EF_SW_SW_USAGE_1 +#define EF_CTRL_EF_SW_SW_USAGE_1_POS (12U) +#define EF_CTRL_EF_SW_SW_USAGE_1_LEN (2U) +#define EF_CTRL_EF_SW_SW_USAGE_1_MSK (((1U << EF_CTRL_EF_SW_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_SW_SW_USAGE_1_POS) +#define EF_CTRL_EF_SW_SW_USAGE_1_UMSK (~(((1U << EF_CTRL_EF_SW_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_SW_SW_USAGE_1_POS)) +#define EF_CTRL_EF_SW_SDU_DIS EF_CTRL_EF_SW_SDU_DIS +#define EF_CTRL_EF_SW_SDU_DIS_POS (14U) +#define EF_CTRL_EF_SW_SDU_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SDU_DIS_MSK (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS) +#define EF_CTRL_EF_SW_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)) +#define EF_CTRL_EF_SW_BLE_DIS EF_CTRL_EF_SW_BLE_DIS +#define EF_CTRL_EF_SW_BLE_DIS_POS (15U) +#define EF_CTRL_EF_SW_BLE_DIS_LEN (1U) +#define EF_CTRL_EF_SW_BLE_DIS_MSK (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS) +#define EF_CTRL_EF_SW_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)) +#define EF_CTRL_EF_SW_WIFI_DIS EF_CTRL_EF_SW_WIFI_DIS +#define EF_CTRL_EF_SW_WIFI_DIS_POS (16U) +#define EF_CTRL_EF_SW_WIFI_DIS_LEN (1U) +#define EF_CTRL_EF_SW_WIFI_DIS_MSK (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS) +#define EF_CTRL_EF_SW_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN EF_CTRL_EF_SW_0_KEY_ENC_EN +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS (17U) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)) +#define EF_CTRL_EF_SW_CAM_DIS EF_CTRL_EF_SW_CAM_DIS +#define EF_CTRL_EF_SW_CAM_DIS_POS (18U) +#define EF_CTRL_EF_SW_CAM_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CAM_DIS_MSK (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS) +#define EF_CTRL_EF_SW_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)) +#define EF_CTRL_EF_SW_SF_DIS EF_CTRL_EF_SW_SF_DIS +#define EF_CTRL_EF_SW_SF_DIS_POS (19U) +#define EF_CTRL_EF_SW_SF_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SF_DIS_MSK (((1U << EF_CTRL_EF_SW_SF_DIS_LEN) - 1) << EF_CTRL_EF_SW_SF_DIS_POS) +#define EF_CTRL_EF_SW_SF_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SF_DIS_LEN) - 1) << EF_CTRL_EF_SW_SF_DIS_POS)) +#define EF_CTRL_EF_SW_CPU1_DIS EF_CTRL_EF_SW_CPU1_DIS +#define EF_CTRL_EF_SW_CPU1_DIS_POS (20U) +#define EF_CTRL_EF_SW_CPU1_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CPU1_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS) +#define EF_CTRL_EF_SW_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS EF_CTRL_EF_SW_CPU_RST_DBG_DIS +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS (21U) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_SE_DBG_DIS EF_CTRL_EF_SW_SE_DBG_DIS +#define EF_CTRL_EF_SW_SE_DBG_DIS_POS (22U) +#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS) +#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS EF_CTRL_EF_SW_EFUSE_DBG_DIS +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS (23U) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS EF_CTRL_EF_SW_DBG_JTAG_1_DIS +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS (24U) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN (2U) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS EF_CTRL_EF_SW_DBG_JTAG_0_DIS +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS (26U) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN (2U) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_MODE EF_CTRL_EF_SW_DBG_MODE +#define EF_CTRL_EF_SW_DBG_MODE_POS (28U) +#define EF_CTRL_EF_SW_DBG_MODE_LEN (4U) +#define EF_CTRL_EF_SW_DBG_MODE_MSK (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS) +#define EF_CTRL_EF_SW_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)) + +/* 0x81C : ef_reserved */ +#define EF_CTRL_EF_RESERVED_OFFSET (0x81C) +#define EF_CTRL_EF_RESERVED EF_CTRL_EF_RESERVED +#define EF_CTRL_EF_RESERVED_POS (0U) +#define EF_CTRL_EF_RESERVED_LEN (32U) +#define EF_CTRL_EF_RESERVED_MSK (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS) +#define EF_CTRL_EF_RESERVED_UMSK (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)) + +/* 0x820 : ef_if_ana_trim_0 */ +#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820) +#define EF_CTRL_EF_IF_ANA_TRIM_0 EF_CTRL_EF_IF_ANA_TRIM_0 +#define EF_CTRL_EF_IF_ANA_TRIM_0_POS (0U) +#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN (32U) +#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS) +#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)) + +/* 0x824 : ef_if_sw_usage_0 */ +#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824) +#define EF_CTRL_EF_IF_SW_USAGE_0 EF_CTRL_EF_IF_SW_USAGE_0 +#define EF_CTRL_EF_IF_SW_USAGE_0_POS (0U) +#define EF_CTRL_EF_IF_SW_USAGE_0_LEN (32U) +#define EF_CTRL_EF_IF_SW_USAGE_0_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS) +#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)) + +/* 0xA00 : ef_crc_ctrl_0 */ +#define EF_CTRL_EF_CRC_CTRL_0_OFFSET (0xA00) +#define EF_CTRL_EF_CRC_BUSY EF_CTRL_EF_CRC_BUSY +#define EF_CTRL_EF_CRC_BUSY_POS (0U) +#define EF_CTRL_EF_CRC_BUSY_LEN (1U) +#define EF_CTRL_EF_CRC_BUSY_MSK (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS) +#define EF_CTRL_EF_CRC_BUSY_UMSK (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)) +#define EF_CTRL_EF_CRC_TRIG EF_CTRL_EF_CRC_TRIG +#define EF_CTRL_EF_CRC_TRIG_POS (1U) +#define EF_CTRL_EF_CRC_TRIG_LEN (1U) +#define EF_CTRL_EF_CRC_TRIG_MSK (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS) +#define EF_CTRL_EF_CRC_TRIG_UMSK (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)) +#define EF_CTRL_EF_CRC_EN EF_CTRL_EF_CRC_EN +#define EF_CTRL_EF_CRC_EN_POS (2U) +#define EF_CTRL_EF_CRC_EN_LEN (1U) +#define EF_CTRL_EF_CRC_EN_MSK (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS) +#define EF_CTRL_EF_CRC_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)) +#define EF_CTRL_EF_CRC_MODE EF_CTRL_EF_CRC_MODE +#define EF_CTRL_EF_CRC_MODE_POS (3U) +#define EF_CTRL_EF_CRC_MODE_LEN (1U) +#define EF_CTRL_EF_CRC_MODE_MSK (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS) +#define EF_CTRL_EF_CRC_MODE_UMSK (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)) +#define EF_CTRL_EF_CRC_ERROR EF_CTRL_EF_CRC_ERROR +#define EF_CTRL_EF_CRC_ERROR_POS (4U) +#define EF_CTRL_EF_CRC_ERROR_LEN (1U) +#define EF_CTRL_EF_CRC_ERROR_MSK (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS) +#define EF_CTRL_EF_CRC_ERROR_UMSK (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)) +#define EF_CTRL_EF_CRC_DOUT_INV_EN EF_CTRL_EF_CRC_DOUT_INV_EN +#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS (5U) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN (1U) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN EF_CTRL_EF_CRC_DOUT_ENDIAN +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS (6U) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN (1U) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)) +#define EF_CTRL_EF_CRC_DIN_ENDIAN EF_CTRL_EF_CRC_DIN_ENDIAN +#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS (7U) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN (1U) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)) +#define EF_CTRL_EF_CRC_INT EF_CTRL_EF_CRC_INT +#define EF_CTRL_EF_CRC_INT_POS (8U) +#define EF_CTRL_EF_CRC_INT_LEN (1U) +#define EF_CTRL_EF_CRC_INT_MSK (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS) +#define EF_CTRL_EF_CRC_INT_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)) +#define EF_CTRL_EF_CRC_INT_CLR EF_CTRL_EF_CRC_INT_CLR +#define EF_CTRL_EF_CRC_INT_CLR_POS (9U) +#define EF_CTRL_EF_CRC_INT_CLR_LEN (1U) +#define EF_CTRL_EF_CRC_INT_CLR_MSK (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS) +#define EF_CTRL_EF_CRC_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)) +#define EF_CTRL_EF_CRC_INT_SET EF_CTRL_EF_CRC_INT_SET +#define EF_CTRL_EF_CRC_INT_SET_POS (10U) +#define EF_CTRL_EF_CRC_INT_SET_LEN (1U) +#define EF_CTRL_EF_CRC_INT_SET_MSK (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS) +#define EF_CTRL_EF_CRC_INT_SET_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)) +#define EF_CTRL_EF_CRC_LOCK EF_CTRL_EF_CRC_LOCK +#define EF_CTRL_EF_CRC_LOCK_POS (11U) +#define EF_CTRL_EF_CRC_LOCK_LEN (1U) +#define EF_CTRL_EF_CRC_LOCK_MSK (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS) +#define EF_CTRL_EF_CRC_LOCK_UMSK (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)) +#define EF_CTRL_EF_CRC_SLP_N EF_CTRL_EF_CRC_SLP_N +#define EF_CTRL_EF_CRC_SLP_N_POS (16U) +#define EF_CTRL_EF_CRC_SLP_N_LEN (16U) +#define EF_CTRL_EF_CRC_SLP_N_MSK (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS) +#define EF_CTRL_EF_CRC_SLP_N_UMSK (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)) + +/* 0xA04 : ef_crc_ctrl_1 */ +#define EF_CTRL_EF_CRC_CTRL_1_OFFSET (0xA04) +#define EF_CTRL_EF_CRC_DATA_0_EN EF_CTRL_EF_CRC_DATA_0_EN +#define EF_CTRL_EF_CRC_DATA_0_EN_POS (0U) +#define EF_CTRL_EF_CRC_DATA_0_EN_LEN (32U) +#define EF_CTRL_EF_CRC_DATA_0_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS) +#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)) + +/* 0xA08 : ef_crc_ctrl_2 */ +#define EF_CTRL_EF_CRC_CTRL_2_OFFSET (0xA08) +#define EF_CTRL_EF_CRC_DATA_1_EN EF_CTRL_EF_CRC_DATA_1_EN +#define EF_CTRL_EF_CRC_DATA_1_EN_POS (0U) +#define EF_CTRL_EF_CRC_DATA_1_EN_LEN (32U) +#define EF_CTRL_EF_CRC_DATA_1_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS) +#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)) + +/* 0xA0C : ef_crc_ctrl_3 */ +#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C) +#define EF_CTRL_EF_CRC_IV EF_CTRL_EF_CRC_IV +#define EF_CTRL_EF_CRC_IV_POS (0U) +#define EF_CTRL_EF_CRC_IV_LEN (32U) +#define EF_CTRL_EF_CRC_IV_MSK (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS) +#define EF_CTRL_EF_CRC_IV_UMSK (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)) + +/* 0xA10 : ef_crc_ctrl_4 */ +#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10) +#define EF_CTRL_EF_CRC_GOLDEN EF_CTRL_EF_CRC_GOLDEN +#define EF_CTRL_EF_CRC_GOLDEN_POS (0U) +#define EF_CTRL_EF_CRC_GOLDEN_LEN (32U) +#define EF_CTRL_EF_CRC_GOLDEN_MSK (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS) +#define EF_CTRL_EF_CRC_GOLDEN_UMSK (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)) + +/* 0xA14 : ef_crc_ctrl_5 */ +#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14) +#define EF_CTRL_EF_CRC_DOUT EF_CTRL_EF_CRC_DOUT +#define EF_CTRL_EF_CRC_DOUT_POS (0U) +#define EF_CTRL_EF_CRC_DOUT_LEN (32U) +#define EF_CTRL_EF_CRC_DOUT_MSK (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS) +#define EF_CTRL_EF_CRC_DOUT_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)) + +struct ef_ctrl_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[2048]; + + /* 0x800 : ef_if_ctrl_0 */ + union { + struct + { + uint32_t ef_if_0_autoload_p1_done : 1; /* [ 0], r, 0x1 */ + uint32_t ef_if_0_autoload_done : 1; /* [ 1], r, 0x1 */ + uint32_t ef_if_0_busy : 1; /* [ 2], r, 0x0 */ + uint32_t ef_if_0_rw : 1; /* [ 3], r/w, 0x0 */ + uint32_t ef_if_0_trig : 1; /* [ 4], r/w, 0x0 */ + uint32_t ef_if_0_manual_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t ef_if_0_cyc_modify : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_clk_sahb_data_sel : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_if_prot_code_ctrl : 8; /* [15: 8], r/w, 0x0 */ + uint32_t ef_if_por_dig : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_clk_sahb_data_gate : 1; /* [ 17], r/w, 0x0 */ + uint32_t ef_if_auto_rd_en : 1; /* [ 18], r/w, 0x1 */ + uint32_t ef_if_cyc_modify_lock : 1; /* [ 19], r/w, 0x0 */ + uint32_t ef_if_0_int : 1; /* [ 20], r, 0x0 */ + uint32_t ef_if_0_int_clr : 1; /* [ 21], r/w, 0x1 */ + uint32_t ef_if_0_int_set : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t ef_if_prot_code_cyc : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_ctrl_0; + + /* 0x804 : ef_if_cyc_0 */ + union { + struct + { + uint32_t ef_if_cyc_rd_dmy : 6; /* [ 5: 0], r/w, 0x0 */ + uint32_t ef_if_cyc_rd_dat : 6; /* [11: 6], r/w, 0x1 */ + uint32_t ef_if_cyc_rd_adr : 6; /* [17:12], r/w, 0x0 */ + uint32_t ef_if_cyc_cs : 6; /* [23:18], r/w, 0x0 */ + uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24], r/w, 0x16 */ + } BF; + uint32_t WORD; + } ef_if_cyc_0; + + /* 0x808 : ef_if_cyc_1 */ + union { + struct + { + uint32_t ef_if_cyc_pi : 6; /* [ 5: 0], r/w, 0x9 */ + uint32_t ef_if_cyc_pp : 8; /* [13: 6], r/w, 0x98 */ + uint32_t ef_if_cyc_wr_adr : 6; /* [19:14], r/w, 0x1 */ + uint32_t ef_if_cyc_ps_cs : 6; /* [25:20], r/w, 0x2 */ + uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_cyc_1; + + /* 0x80C : ef_if_0_manual */ + union { + struct + { + uint32_t ef_if_a : 10; /* [ 9: 0], r/w, 0x0 */ + uint32_t ef_if_pd : 1; /* [ 10], r/w, 0x1 */ + uint32_t ef_if_ps : 1; /* [ 11], r/w, 0x0 */ + uint32_t ef_if_strobe : 1; /* [ 12], r/w, 0x0 */ + uint32_t ef_if_pgenb : 1; /* [ 13], r/w, 0x1 */ + uint32_t ef_if_load : 1; /* [ 14], r/w, 0x1 */ + uint32_t ef_if_csb : 1; /* [ 15], r/w, 0x1 */ + uint32_t ef_if_0_q : 8; /* [23:16], r, 0x0 */ + uint32_t ef_if_prot_code_manual : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_0_manual; + + /* 0x810 : ef_if_0_status */ + union { + struct + { + uint32_t ef_if_0_status : 32; /* [31: 0], r, 0xe400 */ + } BF; + uint32_t WORD; + } ef_if_0_status; + + /* 0x814 : ef_if_cfg_0 */ + union { + struct + { + uint32_t ef_if_sf_aes_mode : 2; /* [ 1: 0], r, 0x0 */ + uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2], r, 0x0 */ + uint32_t ef_if_sboot_en : 2; /* [ 5: 4], r, 0x0 */ + uint32_t ef_if_cpu1_enc_en : 1; /* [ 6], r, 0x0 */ + uint32_t ef_if_cpu0_enc_en : 1; /* [ 7], r, 0x0 */ + uint32_t ef_if_boot_sel : 4; /* [11: 8], r, 0x0 */ + uint32_t ef_if_sw_usage_1 : 2; /* [13:12], r, 0x0 */ + uint32_t ef_if_sdu_dis : 1; /* [ 14], r, 0x0 */ + uint32_t ef_if_ble_dis : 1; /* [ 15], r, 0x0 */ + uint32_t ef_if_wifi_dis : 1; /* [ 16], r, 0x0 */ + uint32_t ef_if_0_key_enc_en : 1; /* [ 17], r, 0x0 */ + uint32_t ef_if_cam_dis : 1; /* [ 18], r, 0x0 */ + uint32_t ef_if_sf_dis : 1; /* [ 19], r, 0x0 */ + uint32_t ef_if_cpu1_dis : 1; /* [ 20], r, 0x0 */ + uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [ 21], r, 0x0 */ + uint32_t ef_if_se_dbg_dis : 1; /* [ 22], r, 0x0 */ + uint32_t ef_if_efuse_dbg_dis : 1; /* [ 23], r, 0x0 */ + uint32_t ef_if_dbg_jtag_1_dis : 2; /* [25:24], r, 0x0 */ + uint32_t ef_if_dbg_jtag_0_dis : 2; /* [27:26], r, 0x0 */ + uint32_t ef_if_dbg_mode : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_cfg_0; + + /* 0x818 : ef_sw_cfg_0 */ + union { + struct + { + uint32_t ef_sw_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t ef_sw_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t ef_sw_cpu1_enc_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_sw_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t ef_sw_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */ + uint32_t ef_sw_sdu_dis : 1; /* [ 14], r/w, 0x0 */ + uint32_t ef_sw_ble_dis : 1; /* [ 15], r/w, 0x0 */ + uint32_t ef_sw_wifi_dis : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_sw_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t ef_sw_cam_dis : 1; /* [ 18], r/w, 0x0 */ + uint32_t ef_sw_sf_dis : 1; /* [ 19], r/w, 0x0 */ + uint32_t ef_sw_cpu1_dis : 1; /* [ 20], r/w, 0x0 */ + uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */ + uint32_t ef_sw_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */ + uint32_t ef_sw_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */ + uint32_t ef_sw_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */ + uint32_t ef_sw_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ + uint32_t ef_sw_dbg_mode : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_sw_cfg_0; + + /* 0x81C : ef_reserved */ + union { + struct + { + uint32_t ef_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } ef_reserved; + + /* 0x820 : ef_if_ana_trim_0 */ + union { + struct + { + uint32_t ef_if_ana_trim_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_ana_trim_0; + + /* 0x824 : ef_if_sw_usage_0 */ + union { + struct + { + uint32_t ef_if_sw_usage_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_sw_usage_0; + + /* 0x828 reserved */ + uint8_t RESERVED0x828[472]; + + /* 0xA00 : ef_crc_ctrl_0 */ + union { + struct + { + uint32_t ef_crc_busy : 1; /* [ 0], r, 0x0 */ + uint32_t ef_crc_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t ef_crc_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t ef_crc_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t ef_crc_error : 1; /* [ 4], r, 0x0 */ + uint32_t ef_crc_dout_inv_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t ef_crc_dout_endian : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_crc_din_endian : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_crc_int : 1; /* [ 8], r, 0x0 */ + uint32_t ef_crc_int_clr : 1; /* [ 9], r/w, 0x1 */ + uint32_t ef_crc_int_set : 1; /* [ 10], r/w, 0x0 */ + uint32_t ef_crc_lock : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t ef_crc_slp_n : 16; /* [31:16], r/w, 0xff */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_0; + + /* 0xA04 : ef_crc_ctrl_1 */ + union { + struct + { + uint32_t ef_crc_data_0_en : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_1; + + /* 0xA08 : ef_crc_ctrl_2 */ + union { + struct + { + uint32_t ef_crc_data_1_en : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_2; + + /* 0xA0C : ef_crc_ctrl_3 */ + union { + struct + { + uint32_t ef_crc_iv : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_3; + + /* 0xA10 : ef_crc_ctrl_4 */ + union { + struct + { + uint32_t ef_crc_golden : 32; /* [31: 0], r/w, 0xc2a8fa9dL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_4; + + /* 0xA14 : ef_crc_ctrl_5 */ + union { + struct + { + uint32_t ef_crc_dout : 32; /* [31: 0], r, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_5; +}; + +typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t; + +#endif /* __EF_CTRL_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ef_data_0_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ef_data_0_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..2322c74081015a5a3ea7948010d55d6b2f27824d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ef_data_0_reg.h @@ -0,0 +1,762 @@ +/** + ****************************************************************************** + * @file ef_data_0_reg.h + * @version V1.2 + * @date 2019-11-22 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_DATA_0_REG_H__ +#define __EF_DATA_0_REG_H__ + +#include "bl602.h" + +/* 0x0 : ef_cfg_0 */ +#define EF_DATA_0_EF_CFG_0_OFFSET (0x0) +#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE +#define EF_DATA_0_EF_SF_AES_MODE_POS (0U) +#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U) +#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS) +#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (2U) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)) +#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN +#define EF_DATA_0_EF_SBOOT_EN_POS (4U) +#define EF_DATA_0_EF_SBOOT_EN_LEN (2U) +#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS) +#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)) +#define EF_DATA_0_EF_CPU0_ENC_EN EF_DATA_0_EF_CPU0_ENC_EN +#define EF_DATA_0_EF_CPU0_ENC_EN_POS (7U) +#define EF_DATA_0_EF_CPU0_ENC_EN_LEN (1U) +#define EF_DATA_0_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS) +#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)) +#define EF_DATA_0_EF_TRIM_EN EF_DATA_0_EF_TRIM_EN +#define EF_DATA_0_EF_TRIM_EN_POS (12U) +#define EF_DATA_0_EF_TRIM_EN_LEN (1U) +#define EF_DATA_0_EF_TRIM_EN_MSK (((1U << EF_DATA_0_EF_TRIM_EN_LEN) - 1) << EF_DATA_0_EF_TRIM_EN_POS) +#define EF_DATA_0_EF_TRIM_EN_UMSK (~(((1U << EF_DATA_0_EF_TRIM_EN_LEN) - 1) << EF_DATA_0_EF_TRIM_EN_POS)) +#define EF_DATA_0_EF_NO_HD_BOOT_EN EF_DATA_0_EF_NO_HD_BOOT_EN +#define EF_DATA_0_EF_NO_HD_BOOT_EN_POS (13U) +#define EF_DATA_0_EF_NO_HD_BOOT_EN_LEN (1U) +#define EF_DATA_0_EF_NO_HD_BOOT_EN_MSK (((1U << EF_DATA_0_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_0_EF_NO_HD_BOOT_EN_POS) +#define EF_DATA_0_EF_NO_HD_BOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_0_EF_NO_HD_BOOT_EN_POS)) +#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN +#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U) +#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U) +#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS) +#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)) +#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE +#define EF_DATA_0_EF_DBG_MODE_POS (28U) +#define EF_DATA_0_EF_DBG_MODE_LEN (4U) +#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS) +#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)) + +/* 0x4 : ef_dbg_pwd_low */ +#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4) +#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW +#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U) +#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U) +#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS) +#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)) + +/* 0x8 : ef_dbg_pwd_high */ +#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8) +#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH +#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U) +#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U) +#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS) +#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)) + +/* 0xC : ef_ana_trim_0 */ +#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC) +#define EF_DATA_0_EF_ANA_TRIM_0 EF_DATA_0_EF_ANA_TRIM_0 +#define EF_DATA_0_EF_ANA_TRIM_0_POS (0U) +#define EF_DATA_0_EF_ANA_TRIM_0_LEN (32U) +#define EF_DATA_0_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS) +#define EF_DATA_0_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)) + +/* 0x10 : ef_sw_usage_0 */ +#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10) +#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0 +#define EF_DATA_0_EF_SW_USAGE_0_POS (0U) +#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U) +#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS) +#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)) + +/* 0x14 : ef_wifi_mac_low */ +#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14) +#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW +#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U) +#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U) +#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS) +#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)) + +/* 0x18 : ef_wifi_mac_high */ +#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18) +#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH +#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)) + +/* 0x1C : ef_key_slot_0_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C) +#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0 +#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)) + +/* 0x20 : ef_key_slot_0_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20) +#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1 +#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)) + +/* 0x24 : ef_key_slot_0_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24) +#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2 +#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)) + +/* 0x28 : ef_key_slot_0_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28) +#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3 +#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)) + +/* 0x2C : ef_key_slot_1_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C) +#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0 +#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)) + +/* 0x30 : ef_key_slot_1_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30) +#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1 +#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)) + +/* 0x34 : ef_key_slot_1_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34) +#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2 +#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)) + +/* 0x38 : ef_key_slot_1_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38) +#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3 +#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)) + +/* 0x3C : ef_key_slot_2_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C) +#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0 +#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)) + +/* 0x40 : ef_key_slot_2_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40) +#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1 +#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)) + +/* 0x44 : ef_key_slot_2_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44) +#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2 +#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)) + +/* 0x48 : ef_key_slot_2_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48) +#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3 +#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)) + +/* 0x4C : ef_key_slot_3_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C) +#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0 +#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)) + +/* 0x50 : ef_key_slot_3_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50) +#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1 +#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)) + +/* 0x54 : ef_key_slot_3_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54) +#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2 +#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)) + +/* 0x58 : ef_key_slot_3_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58) +#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3 +#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)) + +/* 0x5C : ef_key_slot_4_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C) +#define EF_DATA_0_EF_KEY_SLOT_4_W0 EF_DATA_0_EF_KEY_SLOT_4_W0 +#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)) + +/* 0x60 : ef_key_slot_4_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60) +#define EF_DATA_0_EF_KEY_SLOT_4_W1 EF_DATA_0_EF_KEY_SLOT_4_W1 +#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)) + +/* 0x64 : ef_key_slot_4_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64) +#define EF_DATA_0_EF_KEY_SLOT_4_W2 EF_DATA_0_EF_KEY_SLOT_4_W2 +#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)) + +/* 0x68 : ef_key_slot_4_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68) +#define EF_DATA_0_EF_KEY_SLOT_4_W3 EF_DATA_0_EF_KEY_SLOT_4_W3 +#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)) + +/* 0x6C : ef_key_slot_5_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C) +#define EF_DATA_0_EF_KEY_SLOT_5_W0 EF_DATA_0_EF_KEY_SLOT_5_W0 +#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)) + +/* 0x70 : ef_key_slot_5_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70) +#define EF_DATA_0_EF_KEY_SLOT_5_W1 EF_DATA_0_EF_KEY_SLOT_5_W1 +#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)) + +/* 0x74 : ef_key_slot_5_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74) +#define EF_DATA_0_EF_KEY_SLOT_5_W2 EF_DATA_0_EF_KEY_SLOT_5_W2 +#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)) + +/* 0x78 : ef_key_slot_5_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78) +#define EF_DATA_0_EF_KEY_SLOT_5_W3 EF_DATA_0_EF_KEY_SLOT_5_W3 +#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)) + +/* 0x7C : ef_data_0_lock */ +#define EF_DATA_0_LOCK_OFFSET (0x7C) +#define EF_DATA_0_EF_ANA_TRIM_1 EF_DATA_0_EF_ANA_TRIM_1 +#define EF_DATA_0_EF_ANA_TRIM_1_POS (0U) +#define EF_DATA_0_EF_ANA_TRIM_1_LEN (13U) +#define EF_DATA_0_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS) +#define EF_DATA_0_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L EF_DATA_0_WR_LOCK_KEY_SLOT_4_L +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS (13U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L EF_DATA_0_WR_LOCK_KEY_SLOT_5_L +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS (14U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)) +#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE +#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (15U) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)) +#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD +#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (16U) +#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U) +#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS) +#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0 +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (17U) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)) +#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC +#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (18U) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (19U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (20U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (21U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (22U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H EF_DATA_0_WR_LOCK_KEY_SLOT_4_H +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS (23U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H EF_DATA_0_WR_LOCK_KEY_SLOT_5_H +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS (24U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)) +#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD +#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (25U) +#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U) +#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS) +#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (26U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (27U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (28U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (29U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4 EF_DATA_0_RD_LOCK_KEY_SLOT_4 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS (30U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5 EF_DATA_0_RD_LOCK_KEY_SLOT_5 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS (31U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)) + +struct ef_data_0_reg { + /* 0x0 : ef_cfg_0 */ + union { + struct + { + uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t ef_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t ef_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */ + uint32_t rsvd0 : 1; /* [ 14], r/w, 0x0 */ + uint32_t rsvd1 : 1; /* [ 15], r/w, 0x0 */ + uint32_t rsvd2 : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t rsvd3 : 1; /* [ 19], r/w, 0x0 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t rsvd4 : 1; /* [ 21], r/w, 0x0 */ + uint32_t rsvd5 : 1; /* [ 22], r/w, 0x0 */ + uint32_t rsvd6 : 1; /* [ 23], r/w, 0x0 */ + uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */ + uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ + uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_cfg_0; + + /* 0x4 : ef_dbg_pwd_low */ + union { + struct + { + uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_dbg_pwd_low; + + /* 0x8 : ef_dbg_pwd_high */ + union { + struct + { + uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_dbg_pwd_high; + + /* 0xC : ef_ana_trim_0 */ + union { + struct + { + uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_ana_trim_0; + + /* 0x10 : ef_sw_usage_0 */ + union { + struct + { + uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_sw_usage_0; + + /* 0x14 : ef_wifi_mac_low */ + union { + struct + { + uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_wifi_mac_low; + + /* 0x18 : ef_wifi_mac_high */ + union { + struct + { + uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_wifi_mac_high; + + /* 0x1C : ef_key_slot_0_w0 */ + union { + struct + { + uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w0; + + /* 0x20 : ef_key_slot_0_w1 */ + union { + struct + { + uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w1; + + /* 0x24 : ef_key_slot_0_w2 */ + union { + struct + { + uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w2; + + /* 0x28 : ef_key_slot_0_w3 */ + union { + struct + { + uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w3; + + /* 0x2C : ef_key_slot_1_w0 */ + union { + struct + { + uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w0; + + /* 0x30 : ef_key_slot_1_w1 */ + union { + struct + { + uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w1; + + /* 0x34 : ef_key_slot_1_w2 */ + union { + struct + { + uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w2; + + /* 0x38 : ef_key_slot_1_w3 */ + union { + struct + { + uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w3; + + /* 0x3C : ef_key_slot_2_w0 */ + union { + struct + { + uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w0; + + /* 0x40 : ef_key_slot_2_w1 */ + union { + struct + { + uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w1; + + /* 0x44 : ef_key_slot_2_w2 */ + union { + struct + { + uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w2; + + /* 0x48 : ef_key_slot_2_w3 */ + union { + struct + { + uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w3; + + /* 0x4C : ef_key_slot_3_w0 */ + union { + struct + { + uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w0; + + /* 0x50 : ef_key_slot_3_w1 */ + union { + struct + { + uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w1; + + /* 0x54 : ef_key_slot_3_w2 */ + union { + struct + { + uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w2; + + /* 0x58 : ef_key_slot_3_w3 */ + union { + struct + { + uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w3; + + /* 0x5C : ef_key_slot_4_w0 */ + union { + struct + { + uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w0; + + /* 0x60 : ef_key_slot_4_w1 */ + union { + struct + { + uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w1; + + /* 0x64 : ef_key_slot_4_w2 */ + union { + struct + { + uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w2; + + /* 0x68 : ef_key_slot_4_w3 */ + union { + struct + { + uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w3; + + /* 0x6C : ef_key_slot_5_w0 */ + union { + struct + { + uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w0; + + /* 0x70 : ef_key_slot_5_w1 */ + union { + struct + { + uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w1; + + /* 0x74 : ef_key_slot_5_w2 */ + union { + struct + { + uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w2; + + /* 0x78 : ef_key_slot_5_w3 */ + union { + struct + { + uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w3; + + /* 0x7C : ef_data_0_lock */ + union { + struct + { + uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */ + uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */ + uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */ + uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */ + uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */ + uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */ + uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */ + uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */ + uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */ + uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */ + uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */ + uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */ + uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */ + uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */ + uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */ + uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */ + uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */ + uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */ + uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_data_0_lock; +}; + +typedef volatile struct ef_data_0_reg ef_data_0_reg_t; + +#endif /* __EF_DATA_0_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/glb_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/glb_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..f60cab640170d2c61c11acbee18a34a867cb5f75 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/glb_reg.h @@ -0,0 +1,4094 @@ +/** + ****************************************************************************** + * @file glb_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __GLB_REG_H__ +#define __GLB_REG_H__ + +#include "bl602.h" + +/* 0x0 : clk_cfg0 */ +#define GLB_CLK_CFG0_OFFSET (0x0) +#define GLB_REG_PLL_EN GLB_REG_PLL_EN +#define GLB_REG_PLL_EN_POS (0U) +#define GLB_REG_PLL_EN_LEN (1U) +#define GLB_REG_PLL_EN_MSK (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS) +#define GLB_REG_PLL_EN_UMSK (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)) +#define GLB_REG_FCLK_EN GLB_REG_FCLK_EN +#define GLB_REG_FCLK_EN_POS (1U) +#define GLB_REG_FCLK_EN_LEN (1U) +#define GLB_REG_FCLK_EN_MSK (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS) +#define GLB_REG_FCLK_EN_UMSK (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)) +#define GLB_REG_HCLK_EN GLB_REG_HCLK_EN +#define GLB_REG_HCLK_EN_POS (2U) +#define GLB_REG_HCLK_EN_LEN (1U) +#define GLB_REG_HCLK_EN_MSK (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS) +#define GLB_REG_HCLK_EN_UMSK (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)) +#define GLB_REG_BCLK_EN GLB_REG_BCLK_EN +#define GLB_REG_BCLK_EN_POS (3U) +#define GLB_REG_BCLK_EN_LEN (1U) +#define GLB_REG_BCLK_EN_MSK (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS) +#define GLB_REG_BCLK_EN_UMSK (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)) +#define GLB_REG_PLL_SEL GLB_REG_PLL_SEL +#define GLB_REG_PLL_SEL_POS (4U) +#define GLB_REG_PLL_SEL_LEN (2U) +#define GLB_REG_PLL_SEL_MSK (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS) +#define GLB_REG_PLL_SEL_UMSK (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)) +#define GLB_HBN_ROOT_CLK_SEL GLB_HBN_ROOT_CLK_SEL +#define GLB_HBN_ROOT_CLK_SEL_POS (6U) +#define GLB_HBN_ROOT_CLK_SEL_LEN (2U) +#define GLB_HBN_ROOT_CLK_SEL_MSK (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS) +#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)) +#define GLB_REG_HCLK_DIV GLB_REG_HCLK_DIV +#define GLB_REG_HCLK_DIV_POS (8U) +#define GLB_REG_HCLK_DIV_LEN (8U) +#define GLB_REG_HCLK_DIV_MSK (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS) +#define GLB_REG_HCLK_DIV_UMSK (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)) +#define GLB_REG_BCLK_DIV GLB_REG_BCLK_DIV +#define GLB_REG_BCLK_DIV_POS (16U) +#define GLB_REG_BCLK_DIV_LEN (8U) +#define GLB_REG_BCLK_DIV_MSK (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS) +#define GLB_REG_BCLK_DIV_UMSK (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)) +#define GLB_FCLK_SW_STATE GLB_FCLK_SW_STATE +#define GLB_FCLK_SW_STATE_POS (24U) +#define GLB_FCLK_SW_STATE_LEN (3U) +#define GLB_FCLK_SW_STATE_MSK (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS) +#define GLB_FCLK_SW_STATE_UMSK (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)) +#define GLB_CHIP_RDY GLB_CHIP_RDY +#define GLB_CHIP_RDY_POS (27U) +#define GLB_CHIP_RDY_LEN (1U) +#define GLB_CHIP_RDY_MSK (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS) +#define GLB_CHIP_RDY_UMSK (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)) +#define GLB_ID GLB_ID +#define GLB_ID_POS (28U) +#define GLB_ID_LEN (4U) +#define GLB_ID_MSK (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS) +#define GLB_ID_UMSK (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)) + +/* 0x4 : clk_cfg1 */ +#define GLB_CLK_CFG1_OFFSET (0x4) +#define GLB_WIFI_MAC_CORE_DIV GLB_WIFI_MAC_CORE_DIV +#define GLB_WIFI_MAC_CORE_DIV_POS (0U) +#define GLB_WIFI_MAC_CORE_DIV_LEN (4U) +#define GLB_WIFI_MAC_CORE_DIV_MSK (((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS) +#define GLB_WIFI_MAC_CORE_DIV_UMSK (~(((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)) +#define GLB_WIFI_MAC_WT_DIV GLB_WIFI_MAC_WT_DIV +#define GLB_WIFI_MAC_WT_DIV_POS (4U) +#define GLB_WIFI_MAC_WT_DIV_LEN (4U) +#define GLB_WIFI_MAC_WT_DIV_MSK (((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS) +#define GLB_WIFI_MAC_WT_DIV_UMSK (~(((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)) +#define GLB_BLE_CLK_SEL GLB_BLE_CLK_SEL +#define GLB_BLE_CLK_SEL_POS (16U) +#define GLB_BLE_CLK_SEL_LEN (6U) +#define GLB_BLE_CLK_SEL_MSK (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS) +#define GLB_BLE_CLK_SEL_UMSK (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)) +#define GLB_BLE_EN GLB_BLE_EN +#define GLB_BLE_EN_POS (24U) +#define GLB_BLE_EN_LEN (1U) +#define GLB_BLE_EN_MSK (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS) +#define GLB_BLE_EN_UMSK (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)) + +/* 0x8 : clk_cfg2 */ +#define GLB_CLK_CFG2_OFFSET (0x8) +#define GLB_UART_CLK_DIV GLB_UART_CLK_DIV +#define GLB_UART_CLK_DIV_POS (0U) +#define GLB_UART_CLK_DIV_LEN (3U) +#define GLB_UART_CLK_DIV_MSK (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS) +#define GLB_UART_CLK_DIV_UMSK (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)) +#define GLB_UART_CLK_EN GLB_UART_CLK_EN +#define GLB_UART_CLK_EN_POS (4U) +#define GLB_UART_CLK_EN_LEN (1U) +#define GLB_UART_CLK_EN_MSK (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS) +#define GLB_UART_CLK_EN_UMSK (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)) +#define GLB_HBN_UART_CLK_SEL GLB_HBN_UART_CLK_SEL +#define GLB_HBN_UART_CLK_SEL_POS (7U) +#define GLB_HBN_UART_CLK_SEL_LEN (1U) +#define GLB_HBN_UART_CLK_SEL_MSK (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS) +#define GLB_HBN_UART_CLK_SEL_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)) +#define GLB_SF_CLK_DIV GLB_SF_CLK_DIV +#define GLB_SF_CLK_DIV_POS (8U) +#define GLB_SF_CLK_DIV_LEN (3U) +#define GLB_SF_CLK_DIV_MSK (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS) +#define GLB_SF_CLK_DIV_UMSK (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)) +#define GLB_SF_CLK_EN GLB_SF_CLK_EN +#define GLB_SF_CLK_EN_POS (11U) +#define GLB_SF_CLK_EN_LEN (1U) +#define GLB_SF_CLK_EN_MSK (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS) +#define GLB_SF_CLK_EN_UMSK (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)) +#define GLB_SF_CLK_SEL GLB_SF_CLK_SEL +#define GLB_SF_CLK_SEL_POS (12U) +#define GLB_SF_CLK_SEL_LEN (2U) +#define GLB_SF_CLK_SEL_MSK (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS) +#define GLB_SF_CLK_SEL_UMSK (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)) +#define GLB_SF_CLK_SEL2 GLB_SF_CLK_SEL2 +#define GLB_SF_CLK_SEL2_POS (14U) +#define GLB_SF_CLK_SEL2_LEN (2U) +#define GLB_SF_CLK_SEL2_MSK (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS) +#define GLB_SF_CLK_SEL2_UMSK (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)) +#define GLB_IR_CLK_DIV GLB_IR_CLK_DIV +#define GLB_IR_CLK_DIV_POS (16U) +#define GLB_IR_CLK_DIV_LEN (6U) +#define GLB_IR_CLK_DIV_MSK (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS) +#define GLB_IR_CLK_DIV_UMSK (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)) +#define GLB_IR_CLK_EN GLB_IR_CLK_EN +#define GLB_IR_CLK_EN_POS (23U) +#define GLB_IR_CLK_EN_LEN (1U) +#define GLB_IR_CLK_EN_MSK (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS) +#define GLB_IR_CLK_EN_UMSK (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)) +#define GLB_DMA_CLK_EN GLB_DMA_CLK_EN +#define GLB_DMA_CLK_EN_POS (24U) +#define GLB_DMA_CLK_EN_LEN (8U) +#define GLB_DMA_CLK_EN_MSK (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS) +#define GLB_DMA_CLK_EN_UMSK (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)) + +/* 0xC : clk_cfg3 */ +#define GLB_CLK_CFG3_OFFSET (0xC) +#define GLB_SPI_CLK_DIV GLB_SPI_CLK_DIV +#define GLB_SPI_CLK_DIV_POS (0U) +#define GLB_SPI_CLK_DIV_LEN (5U) +#define GLB_SPI_CLK_DIV_MSK (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS) +#define GLB_SPI_CLK_DIV_UMSK (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)) +#define GLB_SPI_CLK_EN GLB_SPI_CLK_EN +#define GLB_SPI_CLK_EN_POS (8U) +#define GLB_SPI_CLK_EN_LEN (1U) +#define GLB_SPI_CLK_EN_MSK (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS) +#define GLB_SPI_CLK_EN_UMSK (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)) +#define GLB_I2C_CLK_DIV GLB_I2C_CLK_DIV +#define GLB_I2C_CLK_DIV_POS (16U) +#define GLB_I2C_CLK_DIV_LEN (8U) +#define GLB_I2C_CLK_DIV_MSK (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS) +#define GLB_I2C_CLK_DIV_UMSK (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)) +#define GLB_I2C_CLK_EN GLB_I2C_CLK_EN +#define GLB_I2C_CLK_EN_POS (24U) +#define GLB_I2C_CLK_EN_LEN (1U) +#define GLB_I2C_CLK_EN_MSK (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS) +#define GLB_I2C_CLK_EN_UMSK (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)) + +/* 0x10 : swrst_cfg0 */ +#define GLB_SWRST_CFG0_OFFSET (0x10) +#define GLB_SWRST_S00 GLB_SWRST_S00 +#define GLB_SWRST_S00_POS (0U) +#define GLB_SWRST_S00_LEN (1U) +#define GLB_SWRST_S00_MSK (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS) +#define GLB_SWRST_S00_UMSK (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)) +#define GLB_SWRST_S01 GLB_SWRST_S01 +#define GLB_SWRST_S01_POS (1U) +#define GLB_SWRST_S01_LEN (1U) +#define GLB_SWRST_S01_MSK (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS) +#define GLB_SWRST_S01_UMSK (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)) +#define GLB_SWRST_S20 GLB_SWRST_S20 +#define GLB_SWRST_S20_POS (4U) +#define GLB_SWRST_S20_LEN (1U) +#define GLB_SWRST_S20_MSK (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS) +#define GLB_SWRST_S20_UMSK (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)) +#define GLB_SWRST_S30 GLB_SWRST_S30 +#define GLB_SWRST_S30_POS (8U) +#define GLB_SWRST_S30_LEN (1U) +#define GLB_SWRST_S30_MSK (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS) +#define GLB_SWRST_S30_UMSK (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)) + +/* 0x14 : swrst_cfg1 */ +#define GLB_SWRST_CFG1_OFFSET (0x14) +#define GLB_SWRST_S10 GLB_SWRST_S10 +#define GLB_SWRST_S10_POS (0U) +#define GLB_SWRST_S10_LEN (1U) +#define GLB_SWRST_S10_MSK (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS) +#define GLB_SWRST_S10_UMSK (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)) +#define GLB_SWRST_S11 GLB_SWRST_S11 +#define GLB_SWRST_S11_POS (1U) +#define GLB_SWRST_S11_LEN (1U) +#define GLB_SWRST_S11_MSK (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS) +#define GLB_SWRST_S11_UMSK (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)) +#define GLB_SWRST_S12 GLB_SWRST_S12 +#define GLB_SWRST_S12_POS (2U) +#define GLB_SWRST_S12_LEN (1U) +#define GLB_SWRST_S12_MSK (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS) +#define GLB_SWRST_S12_UMSK (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)) +#define GLB_SWRST_S13 GLB_SWRST_S13 +#define GLB_SWRST_S13_POS (3U) +#define GLB_SWRST_S13_LEN (1U) +#define GLB_SWRST_S13_MSK (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS) +#define GLB_SWRST_S13_UMSK (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)) +#define GLB_SWRST_S14 GLB_SWRST_S14 +#define GLB_SWRST_S14_POS (4U) +#define GLB_SWRST_S14_LEN (1U) +#define GLB_SWRST_S14_MSK (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS) +#define GLB_SWRST_S14_UMSK (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)) +#define GLB_SWRST_S15 GLB_SWRST_S15 +#define GLB_SWRST_S15_POS (5U) +#define GLB_SWRST_S15_LEN (1U) +#define GLB_SWRST_S15_MSK (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS) +#define GLB_SWRST_S15_UMSK (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)) +#define GLB_SWRST_S16 GLB_SWRST_S16 +#define GLB_SWRST_S16_POS (6U) +#define GLB_SWRST_S16_LEN (1U) +#define GLB_SWRST_S16_MSK (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS) +#define GLB_SWRST_S16_UMSK (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)) +#define GLB_SWRST_S17 GLB_SWRST_S17 +#define GLB_SWRST_S17_POS (7U) +#define GLB_SWRST_S17_LEN (1U) +#define GLB_SWRST_S17_MSK (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS) +#define GLB_SWRST_S17_UMSK (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)) +#define GLB_SWRST_S18 GLB_SWRST_S18 +#define GLB_SWRST_S18_POS (8U) +#define GLB_SWRST_S18_LEN (1U) +#define GLB_SWRST_S18_MSK (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS) +#define GLB_SWRST_S18_UMSK (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)) +#define GLB_SWRST_S19 GLB_SWRST_S19 +#define GLB_SWRST_S19_POS (9U) +#define GLB_SWRST_S19_LEN (1U) +#define GLB_SWRST_S19_MSK (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS) +#define GLB_SWRST_S19_UMSK (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)) +#define GLB_SWRST_S1A GLB_SWRST_S1A +#define GLB_SWRST_S1A_POS (10U) +#define GLB_SWRST_S1A_LEN (1U) +#define GLB_SWRST_S1A_MSK (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS) +#define GLB_SWRST_S1A_UMSK (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)) +#define GLB_SWRST_S1B GLB_SWRST_S1B +#define GLB_SWRST_S1B_POS (11U) +#define GLB_SWRST_S1B_LEN (1U) +#define GLB_SWRST_S1B_MSK (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS) +#define GLB_SWRST_S1B_UMSK (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)) +#define GLB_SWRST_S1C GLB_SWRST_S1C +#define GLB_SWRST_S1C_POS (12U) +#define GLB_SWRST_S1C_LEN (1U) +#define GLB_SWRST_S1C_MSK (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS) +#define GLB_SWRST_S1C_UMSK (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)) +#define GLB_SWRST_S1D GLB_SWRST_S1D +#define GLB_SWRST_S1D_POS (13U) +#define GLB_SWRST_S1D_LEN (1U) +#define GLB_SWRST_S1D_MSK (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS) +#define GLB_SWRST_S1D_UMSK (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)) +#define GLB_SWRST_S1E GLB_SWRST_S1E +#define GLB_SWRST_S1E_POS (14U) +#define GLB_SWRST_S1E_LEN (1U) +#define GLB_SWRST_S1E_MSK (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS) +#define GLB_SWRST_S1E_UMSK (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)) +#define GLB_SWRST_S1F GLB_SWRST_S1F +#define GLB_SWRST_S1F_POS (15U) +#define GLB_SWRST_S1F_LEN (1U) +#define GLB_SWRST_S1F_MSK (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS) +#define GLB_SWRST_S1F_UMSK (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)) +#define GLB_SWRST_S1A0 GLB_SWRST_S1A0 +#define GLB_SWRST_S1A0_POS (16U) +#define GLB_SWRST_S1A0_LEN (1U) +#define GLB_SWRST_S1A0_MSK (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS) +#define GLB_SWRST_S1A0_UMSK (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)) +#define GLB_SWRST_S1A1 GLB_SWRST_S1A1 +#define GLB_SWRST_S1A1_POS (17U) +#define GLB_SWRST_S1A1_LEN (1U) +#define GLB_SWRST_S1A1_MSK (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS) +#define GLB_SWRST_S1A1_UMSK (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)) +#define GLB_SWRST_S1A2 GLB_SWRST_S1A2 +#define GLB_SWRST_S1A2_POS (18U) +#define GLB_SWRST_S1A2_LEN (1U) +#define GLB_SWRST_S1A2_MSK (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS) +#define GLB_SWRST_S1A2_UMSK (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)) +#define GLB_SWRST_S1A3 GLB_SWRST_S1A3 +#define GLB_SWRST_S1A3_POS (19U) +#define GLB_SWRST_S1A3_LEN (1U) +#define GLB_SWRST_S1A3_MSK (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS) +#define GLB_SWRST_S1A3_UMSK (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)) +#define GLB_SWRST_S1A4 GLB_SWRST_S1A4 +#define GLB_SWRST_S1A4_POS (20U) +#define GLB_SWRST_S1A4_LEN (1U) +#define GLB_SWRST_S1A4_MSK (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS) +#define GLB_SWRST_S1A4_UMSK (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)) +#define GLB_SWRST_S1A5 GLB_SWRST_S1A5 +#define GLB_SWRST_S1A5_POS (21U) +#define GLB_SWRST_S1A5_LEN (1U) +#define GLB_SWRST_S1A5_MSK (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS) +#define GLB_SWRST_S1A5_UMSK (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)) +#define GLB_SWRST_S1A6 GLB_SWRST_S1A6 +#define GLB_SWRST_S1A6_POS (22U) +#define GLB_SWRST_S1A6_LEN (1U) +#define GLB_SWRST_S1A6_MSK (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS) +#define GLB_SWRST_S1A6_UMSK (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)) +#define GLB_SWRST_S1A7 GLB_SWRST_S1A7 +#define GLB_SWRST_S1A7_POS (23U) +#define GLB_SWRST_S1A7_LEN (1U) +#define GLB_SWRST_S1A7_MSK (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS) +#define GLB_SWRST_S1A7_UMSK (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)) + +/* 0x18 : swrst_cfg2 */ +#define GLB_SWRST_CFG2_OFFSET (0x18) +#define GLB_REG_CTRL_PWRON_RST GLB_REG_CTRL_PWRON_RST +#define GLB_REG_CTRL_PWRON_RST_POS (0U) +#define GLB_REG_CTRL_PWRON_RST_LEN (1U) +#define GLB_REG_CTRL_PWRON_RST_MSK (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS) +#define GLB_REG_CTRL_PWRON_RST_UMSK (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)) +#define GLB_REG_CTRL_CPU_RESET GLB_REG_CTRL_CPU_RESET +#define GLB_REG_CTRL_CPU_RESET_POS (1U) +#define GLB_REG_CTRL_CPU_RESET_LEN (1U) +#define GLB_REG_CTRL_CPU_RESET_MSK (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS) +#define GLB_REG_CTRL_CPU_RESET_UMSK (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)) +#define GLB_REG_CTRL_SYS_RESET GLB_REG_CTRL_SYS_RESET +#define GLB_REG_CTRL_SYS_RESET_POS (2U) +#define GLB_REG_CTRL_SYS_RESET_LEN (1U) +#define GLB_REG_CTRL_SYS_RESET_MSK (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS) +#define GLB_REG_CTRL_SYS_RESET_UMSK (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)) +#define GLB_REG_CTRL_RESET_DUMMY GLB_REG_CTRL_RESET_DUMMY +#define GLB_REG_CTRL_RESET_DUMMY_POS (4U) +#define GLB_REG_CTRL_RESET_DUMMY_LEN (4U) +#define GLB_REG_CTRL_RESET_DUMMY_MSK (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS) +#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)) +#define GLB_PKA_CLK_SEL GLB_PKA_CLK_SEL +#define GLB_PKA_CLK_SEL_POS (24U) +#define GLB_PKA_CLK_SEL_LEN (1U) +#define GLB_PKA_CLK_SEL_MSK (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS) +#define GLB_PKA_CLK_SEL_UMSK (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)) + +/* 0x1C : swrst_cfg3 */ +#define GLB_SWRST_CFG3_OFFSET (0x1C) + +/* 0x20 : cgen_cfg0 */ +#define GLB_CGEN_CFG0_OFFSET (0x20) +#define GLB_CGEN_M GLB_CGEN_M +#define GLB_CGEN_M_POS (0U) +#define GLB_CGEN_M_LEN (8U) +#define GLB_CGEN_M_MSK (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS) +#define GLB_CGEN_M_UMSK (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)) + +/* 0x24 : cgen_cfg1 */ +#define GLB_CGEN_CFG1_OFFSET (0x24) +#define GLB_CGEN_S1 GLB_CGEN_S1 +#define GLB_CGEN_S1_POS (0U) +#define GLB_CGEN_S1_LEN (16U) +#define GLB_CGEN_S1_MSK (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS) +#define GLB_CGEN_S1_UMSK (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)) +#define GLB_CGEN_S1A GLB_CGEN_S1A +#define GLB_CGEN_S1A_POS (16U) +#define GLB_CGEN_S1A_LEN (8U) +#define GLB_CGEN_S1A_MSK (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS) +#define GLB_CGEN_S1A_UMSK (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)) + +/* 0x28 : cgen_cfg2 */ +#define GLB_CGEN_CFG2_OFFSET (0x28) +#define GLB_CGEN_S2 GLB_CGEN_S2 +#define GLB_CGEN_S2_POS (0U) +#define GLB_CGEN_S2_LEN (1U) +#define GLB_CGEN_S2_MSK (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS) +#define GLB_CGEN_S2_UMSK (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)) +#define GLB_CGEN_S3 GLB_CGEN_S3 +#define GLB_CGEN_S3_POS (4U) +#define GLB_CGEN_S3_LEN (1U) +#define GLB_CGEN_S3_MSK (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS) +#define GLB_CGEN_S3_UMSK (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)) + +/* 0x2C : cgen_cfg3 */ +#define GLB_CGEN_CFG3_OFFSET (0x2C) + +/* 0x30 : MBIST_CTL */ +#define GLB_MBIST_CTL_OFFSET (0x30) +#define GLB_IROM_MBIST_MODE GLB_IROM_MBIST_MODE +#define GLB_IROM_MBIST_MODE_POS (0U) +#define GLB_IROM_MBIST_MODE_LEN (1U) +#define GLB_IROM_MBIST_MODE_MSK (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS) +#define GLB_IROM_MBIST_MODE_UMSK (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)) +#define GLB_HSRAM_MBIST_MODE GLB_HSRAM_MBIST_MODE +#define GLB_HSRAM_MBIST_MODE_POS (1U) +#define GLB_HSRAM_MBIST_MODE_LEN (1U) +#define GLB_HSRAM_MBIST_MODE_MSK (((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS) +#define GLB_HSRAM_MBIST_MODE_UMSK (~(((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)) +#define GLB_TAG_MBIST_MODE GLB_TAG_MBIST_MODE +#define GLB_TAG_MBIST_MODE_POS (2U) +#define GLB_TAG_MBIST_MODE_LEN (1U) +#define GLB_TAG_MBIST_MODE_MSK (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS) +#define GLB_TAG_MBIST_MODE_UMSK (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)) +#define GLB_OCRAM_MBIST_MODE GLB_OCRAM_MBIST_MODE +#define GLB_OCRAM_MBIST_MODE_POS (3U) +#define GLB_OCRAM_MBIST_MODE_LEN (1U) +#define GLB_OCRAM_MBIST_MODE_MSK (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS) +#define GLB_OCRAM_MBIST_MODE_UMSK (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)) +#define GLB_WIFI_MBIST_MODE GLB_WIFI_MBIST_MODE +#define GLB_WIFI_MBIST_MODE_POS (4U) +#define GLB_WIFI_MBIST_MODE_LEN (1U) +#define GLB_WIFI_MBIST_MODE_MSK (((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS) +#define GLB_WIFI_MBIST_MODE_UMSK (~(((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)) +#define GLB_REG_MBIST_RST_N GLB_REG_MBIST_RST_N +#define GLB_REG_MBIST_RST_N_POS (31U) +#define GLB_REG_MBIST_RST_N_LEN (1U) +#define GLB_REG_MBIST_RST_N_MSK (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS) +#define GLB_REG_MBIST_RST_N_UMSK (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)) + +/* 0x34 : MBIST_STAT */ +#define GLB_MBIST_STAT_OFFSET (0x34) +#define GLB_IROM_MBIST_DONE GLB_IROM_MBIST_DONE +#define GLB_IROM_MBIST_DONE_POS (0U) +#define GLB_IROM_MBIST_DONE_LEN (1U) +#define GLB_IROM_MBIST_DONE_MSK (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS) +#define GLB_IROM_MBIST_DONE_UMSK (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)) +#define GLB_HSRAM_MBIST_DONE GLB_HSRAM_MBIST_DONE +#define GLB_HSRAM_MBIST_DONE_POS (1U) +#define GLB_HSRAM_MBIST_DONE_LEN (1U) +#define GLB_HSRAM_MBIST_DONE_MSK (((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS) +#define GLB_HSRAM_MBIST_DONE_UMSK (~(((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)) +#define GLB_TAG_MBIST_DONE GLB_TAG_MBIST_DONE +#define GLB_TAG_MBIST_DONE_POS (2U) +#define GLB_TAG_MBIST_DONE_LEN (1U) +#define GLB_TAG_MBIST_DONE_MSK (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS) +#define GLB_TAG_MBIST_DONE_UMSK (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)) +#define GLB_OCRAM_MBIST_DONE GLB_OCRAM_MBIST_DONE +#define GLB_OCRAM_MBIST_DONE_POS (3U) +#define GLB_OCRAM_MBIST_DONE_LEN (1U) +#define GLB_OCRAM_MBIST_DONE_MSK (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS) +#define GLB_OCRAM_MBIST_DONE_UMSK (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)) +#define GLB_WIFI_MBIST_DONE GLB_WIFI_MBIST_DONE +#define GLB_WIFI_MBIST_DONE_POS (4U) +#define GLB_WIFI_MBIST_DONE_LEN (1U) +#define GLB_WIFI_MBIST_DONE_MSK (((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS) +#define GLB_WIFI_MBIST_DONE_UMSK (~(((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)) +#define GLB_IROM_MBIST_FAIL GLB_IROM_MBIST_FAIL +#define GLB_IROM_MBIST_FAIL_POS (16U) +#define GLB_IROM_MBIST_FAIL_LEN (1U) +#define GLB_IROM_MBIST_FAIL_MSK (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS) +#define GLB_IROM_MBIST_FAIL_UMSK (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)) +#define GLB_HSRAM_MBIST_FAIL GLB_HSRAM_MBIST_FAIL +#define GLB_HSRAM_MBIST_FAIL_POS (17U) +#define GLB_HSRAM_MBIST_FAIL_LEN (1U) +#define GLB_HSRAM_MBIST_FAIL_MSK (((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS) +#define GLB_HSRAM_MBIST_FAIL_UMSK (~(((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)) +#define GLB_TAG_MBIST_FAIL GLB_TAG_MBIST_FAIL +#define GLB_TAG_MBIST_FAIL_POS (18U) +#define GLB_TAG_MBIST_FAIL_LEN (1U) +#define GLB_TAG_MBIST_FAIL_MSK (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS) +#define GLB_TAG_MBIST_FAIL_UMSK (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)) +#define GLB_OCRAM_MBIST_FAIL GLB_OCRAM_MBIST_FAIL +#define GLB_OCRAM_MBIST_FAIL_POS (19U) +#define GLB_OCRAM_MBIST_FAIL_LEN (1U) +#define GLB_OCRAM_MBIST_FAIL_MSK (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS) +#define GLB_OCRAM_MBIST_FAIL_UMSK (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)) +#define GLB_WIFI_MBIST_FAIL GLB_WIFI_MBIST_FAIL +#define GLB_WIFI_MBIST_FAIL_POS (20U) +#define GLB_WIFI_MBIST_FAIL_LEN (1U) +#define GLB_WIFI_MBIST_FAIL_MSK (((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS) +#define GLB_WIFI_MBIST_FAIL_UMSK (~(((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)) + +/* 0x50 : bmx_cfg1 */ +#define GLB_BMX_CFG1_OFFSET (0x50) +#define GLB_BMX_TIMEOUT_EN GLB_BMX_TIMEOUT_EN +#define GLB_BMX_TIMEOUT_EN_POS (0U) +#define GLB_BMX_TIMEOUT_EN_LEN (4U) +#define GLB_BMX_TIMEOUT_EN_MSK (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS) +#define GLB_BMX_TIMEOUT_EN_UMSK (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)) +#define GLB_BMX_ARB_MODE GLB_BMX_ARB_MODE +#define GLB_BMX_ARB_MODE_POS (4U) +#define GLB_BMX_ARB_MODE_LEN (2U) +#define GLB_BMX_ARB_MODE_MSK (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS) +#define GLB_BMX_ARB_MODE_UMSK (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)) +#define GLB_BMX_ERR_EN GLB_BMX_ERR_EN +#define GLB_BMX_ERR_EN_POS (8U) +#define GLB_BMX_ERR_EN_LEN (1U) +#define GLB_BMX_ERR_EN_MSK (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS) +#define GLB_BMX_ERR_EN_UMSK (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)) +#define GLB_BMX_BUSY_OPTION_DIS GLB_BMX_BUSY_OPTION_DIS +#define GLB_BMX_BUSY_OPTION_DIS_POS (9U) +#define GLB_BMX_BUSY_OPTION_DIS_LEN (1U) +#define GLB_BMX_BUSY_OPTION_DIS_MSK (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS) +#define GLB_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)) +#define GLB_BMX_GATING_DIS GLB_BMX_GATING_DIS +#define GLB_BMX_GATING_DIS_POS (10U) +#define GLB_BMX_GATING_DIS_LEN (1U) +#define GLB_BMX_GATING_DIS_MSK (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS) +#define GLB_BMX_GATING_DIS_UMSK (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)) +#define GLB_HSEL_OPTION GLB_HSEL_OPTION +#define GLB_HSEL_OPTION_POS (12U) +#define GLB_HSEL_OPTION_LEN (4U) +#define GLB_HSEL_OPTION_MSK (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS) +#define GLB_HSEL_OPTION_UMSK (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)) +#define GLB_PDS_APB_CFG GLB_PDS_APB_CFG +#define GLB_PDS_APB_CFG_POS (16U) +#define GLB_PDS_APB_CFG_LEN (8U) +#define GLB_PDS_APB_CFG_MSK (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS) +#define GLB_PDS_APB_CFG_UMSK (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)) +#define GLB_HBN_APB_CFG GLB_HBN_APB_CFG +#define GLB_HBN_APB_CFG_POS (24U) +#define GLB_HBN_APB_CFG_LEN (8U) +#define GLB_HBN_APB_CFG_MSK (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS) +#define GLB_HBN_APB_CFG_UMSK (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)) + +/* 0x54 : bmx_cfg2 */ +#define GLB_BMX_CFG2_OFFSET (0x54) +#define GLB_BMX_ERR_ADDR_DIS GLB_BMX_ERR_ADDR_DIS +#define GLB_BMX_ERR_ADDR_DIS_POS (0U) +#define GLB_BMX_ERR_ADDR_DIS_LEN (1U) +#define GLB_BMX_ERR_ADDR_DIS_MSK (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS) +#define GLB_BMX_ERR_ADDR_DIS_UMSK (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)) +#define GLB_BMX_ERR_DEC GLB_BMX_ERR_DEC +#define GLB_BMX_ERR_DEC_POS (4U) +#define GLB_BMX_ERR_DEC_LEN (1U) +#define GLB_BMX_ERR_DEC_MSK (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS) +#define GLB_BMX_ERR_DEC_UMSK (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)) +#define GLB_BMX_ERR_TZ GLB_BMX_ERR_TZ +#define GLB_BMX_ERR_TZ_POS (5U) +#define GLB_BMX_ERR_TZ_LEN (1U) +#define GLB_BMX_ERR_TZ_MSK (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS) +#define GLB_BMX_ERR_TZ_UMSK (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)) +#define GLB_BMX_DBG_SEL GLB_BMX_DBG_SEL +#define GLB_BMX_DBG_SEL_POS (28U) +#define GLB_BMX_DBG_SEL_LEN (4U) +#define GLB_BMX_DBG_SEL_MSK (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS) +#define GLB_BMX_DBG_SEL_UMSK (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)) + +/* 0x58 : bmx_err_addr */ +#define GLB_BMX_ERR_ADDR_OFFSET (0x58) +#define GLB_BMX_ERR_ADDR GLB_BMX_ERR_ADDR +#define GLB_BMX_ERR_ADDR_POS (0U) +#define GLB_BMX_ERR_ADDR_LEN (32U) +#define GLB_BMX_ERR_ADDR_MSK (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS) +#define GLB_BMX_ERR_ADDR_UMSK (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)) + +/* 0x5C : bmx_dbg_out */ +#define GLB_BMX_DBG_OUT_OFFSET (0x5C) +#define GLB_BMX_DBG_OUT GLB_BMX_DBG_OUT +#define GLB_BMX_DBG_OUT_POS (0U) +#define GLB_BMX_DBG_OUT_LEN (32U) +#define GLB_BMX_DBG_OUT_MSK (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS) +#define GLB_BMX_DBG_OUT_UMSK (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)) + +/* 0x60 : rsv0 */ +#define GLB_RSV0_OFFSET (0x60) + +/* 0x64 : rsv1 */ +#define GLB_RSV1_OFFSET (0x64) + +/* 0x68 : rsv2 */ +#define GLB_RSV2_OFFSET (0x68) + +/* 0x6C : rsv3 */ +#define GLB_RSV3_OFFSET (0x6C) + +/* 0x70 : sram_ret */ +#define GLB_SRAM_RET_OFFSET (0x70) +#define GLB_REG_SRAM_RET GLB_REG_SRAM_RET +#define GLB_REG_SRAM_RET_POS (0U) +#define GLB_REG_SRAM_RET_LEN (32U) +#define GLB_REG_SRAM_RET_MSK (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS) +#define GLB_REG_SRAM_RET_UMSK (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)) + +/* 0x74 : sram_slp */ +#define GLB_SRAM_SLP_OFFSET (0x74) +#define GLB_REG_SRAM_SLP GLB_REG_SRAM_SLP +#define GLB_REG_SRAM_SLP_POS (0U) +#define GLB_REG_SRAM_SLP_LEN (32U) +#define GLB_REG_SRAM_SLP_MSK (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS) +#define GLB_REG_SRAM_SLP_UMSK (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)) + +/* 0x78 : sram_parm */ +#define GLB_SRAM_PARM_OFFSET (0x78) +#define GLB_REG_SRAM_PARM GLB_REG_SRAM_PARM +#define GLB_REG_SRAM_PARM_POS (0U) +#define GLB_REG_SRAM_PARM_LEN (32U) +#define GLB_REG_SRAM_PARM_MSK (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS) +#define GLB_REG_SRAM_PARM_UMSK (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)) + +/* 0x7C : seam_misc */ +#define GLB_SEAM_MISC_OFFSET (0x7C) +#define GLB_EM_SEL GLB_EM_SEL +#define GLB_EM_SEL_POS (0U) +#define GLB_EM_SEL_LEN (4U) +#define GLB_EM_SEL_MSK (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS) +#define GLB_EM_SEL_UMSK (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)) + +/* 0x80 : glb_parm */ +#define GLB_PARM_OFFSET (0x80) +#define GLB_REG_BD_EN GLB_REG_BD_EN +#define GLB_REG_BD_EN_POS (0U) +#define GLB_REG_BD_EN_LEN (1U) +#define GLB_REG_BD_EN_MSK (((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS) +#define GLB_REG_BD_EN_UMSK (~(((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)) +#define GLB_REG_EXT_RST_SMT GLB_REG_EXT_RST_SMT +#define GLB_REG_EXT_RST_SMT_POS (1U) +#define GLB_REG_EXT_RST_SMT_LEN (1U) +#define GLB_REG_EXT_RST_SMT_MSK (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS) +#define GLB_REG_EXT_RST_SMT_UMSK (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)) +#define GLB_JTAG_SWAP_SET GLB_JTAG_SWAP_SET +#define GLB_JTAG_SWAP_SET_POS (2U) +#define GLB_JTAG_SWAP_SET_LEN (6U) +#define GLB_JTAG_SWAP_SET_MSK (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS) +#define GLB_JTAG_SWAP_SET_UMSK (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)) +#define GLB_SWAP_SFLASH_IO_3_IO_0 GLB_SWAP_SFLASH_IO_3_IO_0 +#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8U) +#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1U) +#define GLB_SWAP_SFLASH_IO_3_IO_0_MSK (((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS) +#define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK (~(((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS)) +#define GLB_SEL_EMBEDDED_SFLASH GLB_SEL_EMBEDDED_SFLASH +#define GLB_SEL_EMBEDDED_SFLASH_POS (9U) +#define GLB_SEL_EMBEDDED_SFLASH_LEN (1U) +#define GLB_SEL_EMBEDDED_SFLASH_MSK (((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS) +#define GLB_SEL_EMBEDDED_SFLASH_UMSK (~(((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)) +#define GLB_REG_SPI_0_MASTER_MODE GLB_REG_SPI_0_MASTER_MODE +#define GLB_REG_SPI_0_MASTER_MODE_POS (12U) +#define GLB_REG_SPI_0_MASTER_MODE_LEN (1U) +#define GLB_REG_SPI_0_MASTER_MODE_MSK (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS) +#define GLB_REG_SPI_0_MASTER_MODE_UMSK (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)) +#define GLB_REG_SPI_0_SWAP GLB_REG_SPI_0_SWAP +#define GLB_REG_SPI_0_SWAP_POS (13U) +#define GLB_REG_SPI_0_SWAP_LEN (1U) +#define GLB_REG_SPI_0_SWAP_MSK (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS) +#define GLB_REG_SPI_0_SWAP_UMSK (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)) +#define GLB_REG_CCI_USE_JTAG_PIN GLB_REG_CCI_USE_JTAG_PIN +#define GLB_REG_CCI_USE_JTAG_PIN_POS (15U) +#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1U) +#define GLB_REG_CCI_USE_JTAG_PIN_MSK (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS) +#define GLB_REG_CCI_USE_JTAG_PIN_UMSK (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)) +#define GLB_REG_CCI_USE_SDIO_PIN GLB_REG_CCI_USE_SDIO_PIN +#define GLB_REG_CCI_USE_SDIO_PIN_POS (16U) +#define GLB_REG_CCI_USE_SDIO_PIN_LEN (1U) +#define GLB_REG_CCI_USE_SDIO_PIN_MSK (((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS) +#define GLB_REG_CCI_USE_SDIO_PIN_UMSK (~(((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS)) +#define GLB_P1_ADC_TEST_WITH_CCI GLB_P1_ADC_TEST_WITH_CCI +#define GLB_P1_ADC_TEST_WITH_CCI_POS (17U) +#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1U) +#define GLB_P1_ADC_TEST_WITH_CCI_MSK (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS) +#define GLB_P1_ADC_TEST_WITH_CCI_UMSK (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)) +#define GLB_P2_DAC_TEST_WITH_CCI GLB_P2_DAC_TEST_WITH_CCI +#define GLB_P2_DAC_TEST_WITH_CCI_POS (18U) +#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1U) +#define GLB_P2_DAC_TEST_WITH_CCI_MSK (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS) +#define GLB_P2_DAC_TEST_WITH_CCI_UMSK (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)) +#define GLB_P3_CCI_USE_IO_2_5 GLB_P3_CCI_USE_IO_2_5 +#define GLB_P3_CCI_USE_IO_2_5_POS (19U) +#define GLB_P3_CCI_USE_IO_2_5_LEN (1U) +#define GLB_P3_CCI_USE_IO_2_5_MSK (((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS) +#define GLB_P3_CCI_USE_IO_2_5_UMSK (~(((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)) +#define GLB_P4_ADC_TEST_WITH_JTAG GLB_P4_ADC_TEST_WITH_JTAG +#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20U) +#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1U) +#define GLB_P4_ADC_TEST_WITH_JTAG_MSK (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS) +#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS)) +#define GLB_P5_DAC_TEST_WITH_JTAG GLB_P5_DAC_TEST_WITH_JTAG +#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21U) +#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1U) +#define GLB_P5_DAC_TEST_WITH_JTAG_MSK (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS) +#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS)) +#define GLB_P6_SDIO_USE_IO_0_5 GLB_P6_SDIO_USE_IO_0_5 +#define GLB_P6_SDIO_USE_IO_0_5_POS (22U) +#define GLB_P6_SDIO_USE_IO_0_5_LEN (1U) +#define GLB_P6_SDIO_USE_IO_0_5_MSK (((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS) +#define GLB_P6_SDIO_USE_IO_0_5_UMSK (~(((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)) +#define GLB_P7_JTAG_USE_IO_2_5 GLB_P7_JTAG_USE_IO_2_5 +#define GLB_P7_JTAG_USE_IO_2_5_POS (23U) +#define GLB_P7_JTAG_USE_IO_2_5_LEN (1U) +#define GLB_P7_JTAG_USE_IO_2_5_MSK (((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS) +#define GLB_P7_JTAG_USE_IO_2_5_UMSK (~(((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)) +#define GLB_UART_SWAP_SET GLB_UART_SWAP_SET +#define GLB_UART_SWAP_SET_POS (24U) +#define GLB_UART_SWAP_SET_LEN (3U) +#define GLB_UART_SWAP_SET_MSK (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS) +#define GLB_UART_SWAP_SET_UMSK (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)) + +/* 0x90 : CPU_CLK_CFG */ +#define GLB_CPU_CLK_CFG_OFFSET (0x90) +#define GLB_CPU_RTC_DIV GLB_CPU_RTC_DIV +#define GLB_CPU_RTC_DIV_POS (0U) +#define GLB_CPU_RTC_DIV_LEN (17U) +#define GLB_CPU_RTC_DIV_MSK (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS) +#define GLB_CPU_RTC_DIV_UMSK (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)) +#define GLB_CPU_RTC_EN GLB_CPU_RTC_EN +#define GLB_CPU_RTC_EN_POS (18U) +#define GLB_CPU_RTC_EN_LEN (1U) +#define GLB_CPU_RTC_EN_MSK (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS) +#define GLB_CPU_RTC_EN_UMSK (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)) +#define GLB_CPU_RTC_SEL GLB_CPU_RTC_SEL +#define GLB_CPU_RTC_SEL_POS (19U) +#define GLB_CPU_RTC_SEL_LEN (1U) +#define GLB_CPU_RTC_SEL_MSK (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS) +#define GLB_CPU_RTC_SEL_UMSK (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)) +#define GLB_DEBUG_NDRESET_GATE GLB_DEBUG_NDRESET_GATE +#define GLB_DEBUG_NDRESET_GATE_POS (20U) +#define GLB_DEBUG_NDRESET_GATE_LEN (1U) +#define GLB_DEBUG_NDRESET_GATE_MSK (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS) +#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)) + +/* 0xA4 : GPADC_32M_SRC_CTRL */ +#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4) +#define GLB_GPADC_32M_CLK_DIV GLB_GPADC_32M_CLK_DIV +#define GLB_GPADC_32M_CLK_DIV_POS (0U) +#define GLB_GPADC_32M_CLK_DIV_LEN (6U) +#define GLB_GPADC_32M_CLK_DIV_MSK (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS) +#define GLB_GPADC_32M_CLK_DIV_UMSK (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)) +#define GLB_GPADC_32M_CLK_SEL GLB_GPADC_32M_CLK_SEL +#define GLB_GPADC_32M_CLK_SEL_POS (7U) +#define GLB_GPADC_32M_CLK_SEL_LEN (1U) +#define GLB_GPADC_32M_CLK_SEL_MSK (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS) +#define GLB_GPADC_32M_CLK_SEL_UMSK (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)) +#define GLB_GPADC_32M_DIV_EN GLB_GPADC_32M_DIV_EN +#define GLB_GPADC_32M_DIV_EN_POS (8U) +#define GLB_GPADC_32M_DIV_EN_LEN (1U) +#define GLB_GPADC_32M_DIV_EN_MSK (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS) +#define GLB_GPADC_32M_DIV_EN_UMSK (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)) + +/* 0xA8 : DIG32K_WAKEUP_CTRL */ +#define GLB_DIG32K_WAKEUP_CTRL_OFFSET (0xA8) +#define GLB_DIG_32K_DIV GLB_DIG_32K_DIV +#define GLB_DIG_32K_DIV_POS (0U) +#define GLB_DIG_32K_DIV_LEN (11U) +#define GLB_DIG_32K_DIV_MSK (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS) +#define GLB_DIG_32K_DIV_UMSK (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)) +#define GLB_DIG_32K_EN GLB_DIG_32K_EN +#define GLB_DIG_32K_EN_POS (12U) +#define GLB_DIG_32K_EN_LEN (1U) +#define GLB_DIG_32K_EN_MSK (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS) +#define GLB_DIG_32K_EN_UMSK (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)) +#define GLB_DIG_32K_COMP GLB_DIG_32K_COMP +#define GLB_DIG_32K_COMP_POS (13U) +#define GLB_DIG_32K_COMP_LEN (1U) +#define GLB_DIG_32K_COMP_MSK (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS) +#define GLB_DIG_32K_COMP_UMSK (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)) +#define GLB_DIG_512K_DIV GLB_DIG_512K_DIV +#define GLB_DIG_512K_DIV_POS (16U) +#define GLB_DIG_512K_DIV_LEN (7U) +#define GLB_DIG_512K_DIV_MSK (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS) +#define GLB_DIG_512K_DIV_UMSK (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)) +#define GLB_DIG_512K_EN GLB_DIG_512K_EN +#define GLB_DIG_512K_EN_POS (24U) +#define GLB_DIG_512K_EN_LEN (1U) +#define GLB_DIG_512K_EN_MSK (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS) +#define GLB_DIG_512K_EN_UMSK (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)) +#define GLB_DIG_512K_COMP GLB_DIG_512K_COMP +#define GLB_DIG_512K_COMP_POS (25U) +#define GLB_DIG_512K_COMP_LEN (1U) +#define GLB_DIG_512K_COMP_MSK (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS) +#define GLB_DIG_512K_COMP_UMSK (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)) +#define GLB_DIG_CLK_SRC_SEL GLB_DIG_CLK_SRC_SEL +#define GLB_DIG_CLK_SRC_SEL_POS (28U) +#define GLB_DIG_CLK_SRC_SEL_LEN (1U) +#define GLB_DIG_CLK_SRC_SEL_MSK (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS) +#define GLB_DIG_CLK_SRC_SEL_UMSK (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)) +#define GLB_REG_EN_PLATFORM_WAKEUP GLB_REG_EN_PLATFORM_WAKEUP +#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31U) +#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1U) +#define GLB_REG_EN_PLATFORM_WAKEUP_MSK (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS) +#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)) + +/* 0xAC : WIFI_BT_COEX_CTRL */ +#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC) +#define GLB_COEX_BT_CHANNEL GLB_COEX_BT_CHANNEL +#define GLB_COEX_BT_CHANNEL_POS (0U) +#define GLB_COEX_BT_CHANNEL_LEN (7U) +#define GLB_COEX_BT_CHANNEL_MSK (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS) +#define GLB_COEX_BT_CHANNEL_UMSK (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)) +#define GLB_COEX_BT_PTI GLB_COEX_BT_PTI +#define GLB_COEX_BT_PTI_POS (7U) +#define GLB_COEX_BT_PTI_LEN (4U) +#define GLB_COEX_BT_PTI_MSK (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS) +#define GLB_COEX_BT_PTI_UMSK (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)) +#define GLB_COEX_BT_BW GLB_COEX_BT_BW +#define GLB_COEX_BT_BW_POS (11U) +#define GLB_COEX_BT_BW_LEN (1U) +#define GLB_COEX_BT_BW_MSK (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS) +#define GLB_COEX_BT_BW_UMSK (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)) +#define GLB_EN_GPIO_BT_COEX GLB_EN_GPIO_BT_COEX +#define GLB_EN_GPIO_BT_COEX_POS (12U) +#define GLB_EN_GPIO_BT_COEX_LEN (1U) +#define GLB_EN_GPIO_BT_COEX_MSK (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS) +#define GLB_EN_GPIO_BT_COEX_UMSK (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)) + +/* 0xC0 : UART_SIG_SEL_0 */ +#define GLB_UART_SIG_SEL_0_OFFSET (0xC0) +#define GLB_UART_SIG_0_SEL GLB_UART_SIG_0_SEL +#define GLB_UART_SIG_0_SEL_POS (0U) +#define GLB_UART_SIG_0_SEL_LEN (4U) +#define GLB_UART_SIG_0_SEL_MSK (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS) +#define GLB_UART_SIG_0_SEL_UMSK (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)) +#define GLB_UART_SIG_1_SEL GLB_UART_SIG_1_SEL +#define GLB_UART_SIG_1_SEL_POS (4U) +#define GLB_UART_SIG_1_SEL_LEN (4U) +#define GLB_UART_SIG_1_SEL_MSK (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS) +#define GLB_UART_SIG_1_SEL_UMSK (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)) +#define GLB_UART_SIG_2_SEL GLB_UART_SIG_2_SEL +#define GLB_UART_SIG_2_SEL_POS (8U) +#define GLB_UART_SIG_2_SEL_LEN (4U) +#define GLB_UART_SIG_2_SEL_MSK (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS) +#define GLB_UART_SIG_2_SEL_UMSK (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)) +#define GLB_UART_SIG_3_SEL GLB_UART_SIG_3_SEL +#define GLB_UART_SIG_3_SEL_POS (12U) +#define GLB_UART_SIG_3_SEL_LEN (4U) +#define GLB_UART_SIG_3_SEL_MSK (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS) +#define GLB_UART_SIG_3_SEL_UMSK (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)) +#define GLB_UART_SIG_4_SEL GLB_UART_SIG_4_SEL +#define GLB_UART_SIG_4_SEL_POS (16U) +#define GLB_UART_SIG_4_SEL_LEN (4U) +#define GLB_UART_SIG_4_SEL_MSK (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS) +#define GLB_UART_SIG_4_SEL_UMSK (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)) +#define GLB_UART_SIG_5_SEL GLB_UART_SIG_5_SEL +#define GLB_UART_SIG_5_SEL_POS (20U) +#define GLB_UART_SIG_5_SEL_LEN (4U) +#define GLB_UART_SIG_5_SEL_MSK (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS) +#define GLB_UART_SIG_5_SEL_UMSK (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)) +#define GLB_UART_SIG_6_SEL GLB_UART_SIG_6_SEL +#define GLB_UART_SIG_6_SEL_POS (24U) +#define GLB_UART_SIG_6_SEL_LEN (4U) +#define GLB_UART_SIG_6_SEL_MSK (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS) +#define GLB_UART_SIG_6_SEL_UMSK (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)) +#define GLB_UART_SIG_7_SEL GLB_UART_SIG_7_SEL +#define GLB_UART_SIG_7_SEL_POS (28U) +#define GLB_UART_SIG_7_SEL_LEN (4U) +#define GLB_UART_SIG_7_SEL_MSK (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS) +#define GLB_UART_SIG_7_SEL_UMSK (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)) + +/* 0xD0 : DBG_SEL_LL */ +#define GLB_DBG_SEL_LL_OFFSET (0xD0) +#define GLB_REG_DBG_LL_CTRL GLB_REG_DBG_LL_CTRL +#define GLB_REG_DBG_LL_CTRL_POS (0U) +#define GLB_REG_DBG_LL_CTRL_LEN (32U) +#define GLB_REG_DBG_LL_CTRL_MSK (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS) +#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)) + +/* 0xD4 : DBG_SEL_LH */ +#define GLB_DBG_SEL_LH_OFFSET (0xD4) +#define GLB_REG_DBG_LH_CTRL GLB_REG_DBG_LH_CTRL +#define GLB_REG_DBG_LH_CTRL_POS (0U) +#define GLB_REG_DBG_LH_CTRL_LEN (32U) +#define GLB_REG_DBG_LH_CTRL_MSK (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS) +#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)) + +/* 0xD8 : DBG_SEL_HL */ +#define GLB_DBG_SEL_HL_OFFSET (0xD8) +#define GLB_REG_DBG_HL_CTRL GLB_REG_DBG_HL_CTRL +#define GLB_REG_DBG_HL_CTRL_POS (0U) +#define GLB_REG_DBG_HL_CTRL_LEN (32U) +#define GLB_REG_DBG_HL_CTRL_MSK (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS) +#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)) + +/* 0xDC : DBG_SEL_HH */ +#define GLB_DBG_SEL_HH_OFFSET (0xDC) +#define GLB_REG_DBG_HH_CTRL GLB_REG_DBG_HH_CTRL +#define GLB_REG_DBG_HH_CTRL_POS (0U) +#define GLB_REG_DBG_HH_CTRL_LEN (32U) +#define GLB_REG_DBG_HH_CTRL_MSK (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS) +#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)) + +/* 0xE0 : debug */ +#define GLB_DEBUG_OFFSET (0xE0) +#define GLB_DEBUG_OE GLB_DEBUG_OE +#define GLB_DEBUG_OE_POS (0U) +#define GLB_DEBUG_OE_LEN (1U) +#define GLB_DEBUG_OE_MSK (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS) +#define GLB_DEBUG_OE_UMSK (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)) +#define GLB_DEBUG_I GLB_DEBUG_I +#define GLB_DEBUG_I_POS (1U) +#define GLB_DEBUG_I_LEN (31U) +#define GLB_DEBUG_I_MSK (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS) +#define GLB_DEBUG_I_UMSK (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)) + +/* 0x100 : GPIO_CFGCTL0 */ +#define GLB_GPIO_CFGCTL0_OFFSET (0x100) +#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE +#define GLB_REG_GPIO_0_IE_POS (0U) +#define GLB_REG_GPIO_0_IE_LEN (1U) +#define GLB_REG_GPIO_0_IE_MSK (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) +#define GLB_REG_GPIO_0_IE_UMSK (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) +#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT +#define GLB_REG_GPIO_0_SMT_POS (1U) +#define GLB_REG_GPIO_0_SMT_LEN (1U) +#define GLB_REG_GPIO_0_SMT_MSK (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) +#define GLB_REG_GPIO_0_SMT_UMSK (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) +#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV +#define GLB_REG_GPIO_0_DRV_POS (2U) +#define GLB_REG_GPIO_0_DRV_LEN (2U) +#define GLB_REG_GPIO_0_DRV_MSK (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) +#define GLB_REG_GPIO_0_DRV_UMSK (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) +#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU +#define GLB_REG_GPIO_0_PU_POS (4U) +#define GLB_REG_GPIO_0_PU_LEN (1U) +#define GLB_REG_GPIO_0_PU_MSK (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) +#define GLB_REG_GPIO_0_PU_UMSK (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) +#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD +#define GLB_REG_GPIO_0_PD_POS (5U) +#define GLB_REG_GPIO_0_PD_LEN (1U) +#define GLB_REG_GPIO_0_PD_MSK (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) +#define GLB_REG_GPIO_0_PD_UMSK (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) +#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL +#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) +#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL +#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U) +#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS) +#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)) +#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE +#define GLB_REG_GPIO_1_IE_POS (16U) +#define GLB_REG_GPIO_1_IE_LEN (1U) +#define GLB_REG_GPIO_1_IE_MSK (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) +#define GLB_REG_GPIO_1_IE_UMSK (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) +#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT +#define GLB_REG_GPIO_1_SMT_POS (17U) +#define GLB_REG_GPIO_1_SMT_LEN (1U) +#define GLB_REG_GPIO_1_SMT_MSK (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) +#define GLB_REG_GPIO_1_SMT_UMSK (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) +#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV +#define GLB_REG_GPIO_1_DRV_POS (18U) +#define GLB_REG_GPIO_1_DRV_LEN (2U) +#define GLB_REG_GPIO_1_DRV_MSK (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) +#define GLB_REG_GPIO_1_DRV_UMSK (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) +#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU +#define GLB_REG_GPIO_1_PU_POS (20U) +#define GLB_REG_GPIO_1_PU_LEN (1U) +#define GLB_REG_GPIO_1_PU_MSK (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) +#define GLB_REG_GPIO_1_PU_UMSK (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) +#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD +#define GLB_REG_GPIO_1_PD_POS (21U) +#define GLB_REG_GPIO_1_PD_LEN (1U) +#define GLB_REG_GPIO_1_PD_MSK (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) +#define GLB_REG_GPIO_1_PD_UMSK (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) +#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL +#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) +#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL +#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U) +#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS) +#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)) + +/* 0x104 : GPIO_CFGCTL1 */ +#define GLB_GPIO_CFGCTL1_OFFSET (0x104) +#define GLB_REG_GPIO_2_IE GLB_REG_GPIO_2_IE +#define GLB_REG_GPIO_2_IE_POS (0U) +#define GLB_REG_GPIO_2_IE_LEN (1U) +#define GLB_REG_GPIO_2_IE_MSK (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS) +#define GLB_REG_GPIO_2_IE_UMSK (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)) +#define GLB_REG_GPIO_2_SMT GLB_REG_GPIO_2_SMT +#define GLB_REG_GPIO_2_SMT_POS (1U) +#define GLB_REG_GPIO_2_SMT_LEN (1U) +#define GLB_REG_GPIO_2_SMT_MSK (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS) +#define GLB_REG_GPIO_2_SMT_UMSK (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)) +#define GLB_REG_GPIO_2_DRV GLB_REG_GPIO_2_DRV +#define GLB_REG_GPIO_2_DRV_POS (2U) +#define GLB_REG_GPIO_2_DRV_LEN (2U) +#define GLB_REG_GPIO_2_DRV_MSK (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS) +#define GLB_REG_GPIO_2_DRV_UMSK (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)) +#define GLB_REG_GPIO_2_PU GLB_REG_GPIO_2_PU +#define GLB_REG_GPIO_2_PU_POS (4U) +#define GLB_REG_GPIO_2_PU_LEN (1U) +#define GLB_REG_GPIO_2_PU_MSK (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS) +#define GLB_REG_GPIO_2_PU_UMSK (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)) +#define GLB_REG_GPIO_2_PD GLB_REG_GPIO_2_PD +#define GLB_REG_GPIO_2_PD_POS (5U) +#define GLB_REG_GPIO_2_PD_LEN (1U) +#define GLB_REG_GPIO_2_PD_MSK (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS) +#define GLB_REG_GPIO_2_PD_UMSK (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)) +#define GLB_REG_GPIO_2_FUNC_SEL GLB_REG_GPIO_2_FUNC_SEL +#define GLB_REG_GPIO_2_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_2_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_2_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS) +#define GLB_REG_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_2_FUNC_SEL GLB_REAL_GPIO_2_FUNC_SEL +#define GLB_REAL_GPIO_2_FUNC_SEL_POS (12U) +#define GLB_REAL_GPIO_2_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_2_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS) +#define GLB_REAL_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS)) +#define GLB_REG_GPIO_3_IE GLB_REG_GPIO_3_IE +#define GLB_REG_GPIO_3_IE_POS (16U) +#define GLB_REG_GPIO_3_IE_LEN (1U) +#define GLB_REG_GPIO_3_IE_MSK (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS) +#define GLB_REG_GPIO_3_IE_UMSK (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)) +#define GLB_REG_GPIO_3_SMT GLB_REG_GPIO_3_SMT +#define GLB_REG_GPIO_3_SMT_POS (17U) +#define GLB_REG_GPIO_3_SMT_LEN (1U) +#define GLB_REG_GPIO_3_SMT_MSK (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS) +#define GLB_REG_GPIO_3_SMT_UMSK (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)) +#define GLB_REG_GPIO_3_DRV GLB_REG_GPIO_3_DRV +#define GLB_REG_GPIO_3_DRV_POS (18U) +#define GLB_REG_GPIO_3_DRV_LEN (2U) +#define GLB_REG_GPIO_3_DRV_MSK (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS) +#define GLB_REG_GPIO_3_DRV_UMSK (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)) +#define GLB_REG_GPIO_3_PU GLB_REG_GPIO_3_PU +#define GLB_REG_GPIO_3_PU_POS (20U) +#define GLB_REG_GPIO_3_PU_LEN (1U) +#define GLB_REG_GPIO_3_PU_MSK (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS) +#define GLB_REG_GPIO_3_PU_UMSK (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)) +#define GLB_REG_GPIO_3_PD GLB_REG_GPIO_3_PD +#define GLB_REG_GPIO_3_PD_POS (21U) +#define GLB_REG_GPIO_3_PD_LEN (1U) +#define GLB_REG_GPIO_3_PD_MSK (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS) +#define GLB_REG_GPIO_3_PD_UMSK (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)) +#define GLB_REG_GPIO_3_FUNC_SEL GLB_REG_GPIO_3_FUNC_SEL +#define GLB_REG_GPIO_3_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_3_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_3_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS) +#define GLB_REG_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_3_FUNC_SEL GLB_REAL_GPIO_3_FUNC_SEL +#define GLB_REAL_GPIO_3_FUNC_SEL_POS (28U) +#define GLB_REAL_GPIO_3_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_3_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS) +#define GLB_REAL_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS)) + +/* 0x108 : GPIO_CFGCTL2 */ +#define GLB_GPIO_CFGCTL2_OFFSET (0x108) +#define GLB_REG_GPIO_4_IE GLB_REG_GPIO_4_IE +#define GLB_REG_GPIO_4_IE_POS (0U) +#define GLB_REG_GPIO_4_IE_LEN (1U) +#define GLB_REG_GPIO_4_IE_MSK (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS) +#define GLB_REG_GPIO_4_IE_UMSK (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)) +#define GLB_REG_GPIO_4_SMT GLB_REG_GPIO_4_SMT +#define GLB_REG_GPIO_4_SMT_POS (1U) +#define GLB_REG_GPIO_4_SMT_LEN (1U) +#define GLB_REG_GPIO_4_SMT_MSK (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS) +#define GLB_REG_GPIO_4_SMT_UMSK (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)) +#define GLB_REG_GPIO_4_DRV GLB_REG_GPIO_4_DRV +#define GLB_REG_GPIO_4_DRV_POS (2U) +#define GLB_REG_GPIO_4_DRV_LEN (2U) +#define GLB_REG_GPIO_4_DRV_MSK (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS) +#define GLB_REG_GPIO_4_DRV_UMSK (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)) +#define GLB_REG_GPIO_4_PU GLB_REG_GPIO_4_PU +#define GLB_REG_GPIO_4_PU_POS (4U) +#define GLB_REG_GPIO_4_PU_LEN (1U) +#define GLB_REG_GPIO_4_PU_MSK (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS) +#define GLB_REG_GPIO_4_PU_UMSK (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)) +#define GLB_REG_GPIO_4_PD GLB_REG_GPIO_4_PD +#define GLB_REG_GPIO_4_PD_POS (5U) +#define GLB_REG_GPIO_4_PD_LEN (1U) +#define GLB_REG_GPIO_4_PD_MSK (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS) +#define GLB_REG_GPIO_4_PD_UMSK (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)) +#define GLB_REG_GPIO_4_FUNC_SEL GLB_REG_GPIO_4_FUNC_SEL +#define GLB_REG_GPIO_4_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_4_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_4_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS) +#define GLB_REG_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_4_FUNC_SEL GLB_REAL_GPIO_4_FUNC_SEL +#define GLB_REAL_GPIO_4_FUNC_SEL_POS (12U) +#define GLB_REAL_GPIO_4_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_4_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS) +#define GLB_REAL_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS)) +#define GLB_REG_GPIO_5_IE GLB_REG_GPIO_5_IE +#define GLB_REG_GPIO_5_IE_POS (16U) +#define GLB_REG_GPIO_5_IE_LEN (1U) +#define GLB_REG_GPIO_5_IE_MSK (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS) +#define GLB_REG_GPIO_5_IE_UMSK (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)) +#define GLB_REG_GPIO_5_SMT GLB_REG_GPIO_5_SMT +#define GLB_REG_GPIO_5_SMT_POS (17U) +#define GLB_REG_GPIO_5_SMT_LEN (1U) +#define GLB_REG_GPIO_5_SMT_MSK (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS) +#define GLB_REG_GPIO_5_SMT_UMSK (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)) +#define GLB_REG_GPIO_5_DRV GLB_REG_GPIO_5_DRV +#define GLB_REG_GPIO_5_DRV_POS (18U) +#define GLB_REG_GPIO_5_DRV_LEN (2U) +#define GLB_REG_GPIO_5_DRV_MSK (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS) +#define GLB_REG_GPIO_5_DRV_UMSK (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)) +#define GLB_REG_GPIO_5_PU GLB_REG_GPIO_5_PU +#define GLB_REG_GPIO_5_PU_POS (20U) +#define GLB_REG_GPIO_5_PU_LEN (1U) +#define GLB_REG_GPIO_5_PU_MSK (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS) +#define GLB_REG_GPIO_5_PU_UMSK (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)) +#define GLB_REG_GPIO_5_PD GLB_REG_GPIO_5_PD +#define GLB_REG_GPIO_5_PD_POS (21U) +#define GLB_REG_GPIO_5_PD_LEN (1U) +#define GLB_REG_GPIO_5_PD_MSK (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS) +#define GLB_REG_GPIO_5_PD_UMSK (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)) +#define GLB_REG_GPIO_5_FUNC_SEL GLB_REG_GPIO_5_FUNC_SEL +#define GLB_REG_GPIO_5_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_5_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_5_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS) +#define GLB_REG_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_5_FUNC_SEL GLB_REAL_GPIO_5_FUNC_SEL +#define GLB_REAL_GPIO_5_FUNC_SEL_POS (28U) +#define GLB_REAL_GPIO_5_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_5_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS) +#define GLB_REAL_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS)) + +/* 0x10C : GPIO_CFGCTL3 */ +#define GLB_GPIO_CFGCTL3_OFFSET (0x10C) +#define GLB_REG_GPIO_6_IE GLB_REG_GPIO_6_IE +#define GLB_REG_GPIO_6_IE_POS (0U) +#define GLB_REG_GPIO_6_IE_LEN (1U) +#define GLB_REG_GPIO_6_IE_MSK (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS) +#define GLB_REG_GPIO_6_IE_UMSK (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)) +#define GLB_REG_GPIO_6_SMT GLB_REG_GPIO_6_SMT +#define GLB_REG_GPIO_6_SMT_POS (1U) +#define GLB_REG_GPIO_6_SMT_LEN (1U) +#define GLB_REG_GPIO_6_SMT_MSK (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS) +#define GLB_REG_GPIO_6_SMT_UMSK (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)) +#define GLB_REG_GPIO_6_DRV GLB_REG_GPIO_6_DRV +#define GLB_REG_GPIO_6_DRV_POS (2U) +#define GLB_REG_GPIO_6_DRV_LEN (2U) +#define GLB_REG_GPIO_6_DRV_MSK (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS) +#define GLB_REG_GPIO_6_DRV_UMSK (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)) +#define GLB_REG_GPIO_6_PU GLB_REG_GPIO_6_PU +#define GLB_REG_GPIO_6_PU_POS (4U) +#define GLB_REG_GPIO_6_PU_LEN (1U) +#define GLB_REG_GPIO_6_PU_MSK (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS) +#define GLB_REG_GPIO_6_PU_UMSK (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)) +#define GLB_REG_GPIO_6_PD GLB_REG_GPIO_6_PD +#define GLB_REG_GPIO_6_PD_POS (5U) +#define GLB_REG_GPIO_6_PD_LEN (1U) +#define GLB_REG_GPIO_6_PD_MSK (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS) +#define GLB_REG_GPIO_6_PD_UMSK (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)) +#define GLB_REG_GPIO_6_FUNC_SEL GLB_REG_GPIO_6_FUNC_SEL +#define GLB_REG_GPIO_6_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_6_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_6_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS) +#define GLB_REG_GPIO_6_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)) +#define GLB_REG_GPIO_7_IE GLB_REG_GPIO_7_IE +#define GLB_REG_GPIO_7_IE_POS (16U) +#define GLB_REG_GPIO_7_IE_LEN (1U) +#define GLB_REG_GPIO_7_IE_MSK (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS) +#define GLB_REG_GPIO_7_IE_UMSK (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)) +#define GLB_REG_GPIO_7_SMT GLB_REG_GPIO_7_SMT +#define GLB_REG_GPIO_7_SMT_POS (17U) +#define GLB_REG_GPIO_7_SMT_LEN (1U) +#define GLB_REG_GPIO_7_SMT_MSK (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS) +#define GLB_REG_GPIO_7_SMT_UMSK (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)) +#define GLB_REG_GPIO_7_DRV GLB_REG_GPIO_7_DRV +#define GLB_REG_GPIO_7_DRV_POS (18U) +#define GLB_REG_GPIO_7_DRV_LEN (2U) +#define GLB_REG_GPIO_7_DRV_MSK (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS) +#define GLB_REG_GPIO_7_DRV_UMSK (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)) +#define GLB_REG_GPIO_7_PU GLB_REG_GPIO_7_PU +#define GLB_REG_GPIO_7_PU_POS (20U) +#define GLB_REG_GPIO_7_PU_LEN (1U) +#define GLB_REG_GPIO_7_PU_MSK (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS) +#define GLB_REG_GPIO_7_PU_UMSK (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)) +#define GLB_REG_GPIO_7_PD GLB_REG_GPIO_7_PD +#define GLB_REG_GPIO_7_PD_POS (21U) +#define GLB_REG_GPIO_7_PD_LEN (1U) +#define GLB_REG_GPIO_7_PD_MSK (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS) +#define GLB_REG_GPIO_7_PD_UMSK (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)) +#define GLB_REG_GPIO_7_FUNC_SEL GLB_REG_GPIO_7_FUNC_SEL +#define GLB_REG_GPIO_7_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_7_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_7_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS) +#define GLB_REG_GPIO_7_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)) + +/* 0x110 : GPIO_CFGCTL4 */ +#define GLB_GPIO_CFGCTL4_OFFSET (0x110) +#define GLB_REG_GPIO_8_IE GLB_REG_GPIO_8_IE +#define GLB_REG_GPIO_8_IE_POS (0U) +#define GLB_REG_GPIO_8_IE_LEN (1U) +#define GLB_REG_GPIO_8_IE_MSK (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS) +#define GLB_REG_GPIO_8_IE_UMSK (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)) +#define GLB_REG_GPIO_8_SMT GLB_REG_GPIO_8_SMT +#define GLB_REG_GPIO_8_SMT_POS (1U) +#define GLB_REG_GPIO_8_SMT_LEN (1U) +#define GLB_REG_GPIO_8_SMT_MSK (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS) +#define GLB_REG_GPIO_8_SMT_UMSK (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)) +#define GLB_REG_GPIO_8_DRV GLB_REG_GPIO_8_DRV +#define GLB_REG_GPIO_8_DRV_POS (2U) +#define GLB_REG_GPIO_8_DRV_LEN (2U) +#define GLB_REG_GPIO_8_DRV_MSK (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS) +#define GLB_REG_GPIO_8_DRV_UMSK (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)) +#define GLB_REG_GPIO_8_PU GLB_REG_GPIO_8_PU +#define GLB_REG_GPIO_8_PU_POS (4U) +#define GLB_REG_GPIO_8_PU_LEN (1U) +#define GLB_REG_GPIO_8_PU_MSK (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS) +#define GLB_REG_GPIO_8_PU_UMSK (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)) +#define GLB_REG_GPIO_8_PD GLB_REG_GPIO_8_PD +#define GLB_REG_GPIO_8_PD_POS (5U) +#define GLB_REG_GPIO_8_PD_LEN (1U) +#define GLB_REG_GPIO_8_PD_MSK (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS) +#define GLB_REG_GPIO_8_PD_UMSK (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)) +#define GLB_REG_GPIO_8_FUNC_SEL GLB_REG_GPIO_8_FUNC_SEL +#define GLB_REG_GPIO_8_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_8_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_8_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS) +#define GLB_REG_GPIO_8_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)) +#define GLB_REG_GPIO_9_IE GLB_REG_GPIO_9_IE +#define GLB_REG_GPIO_9_IE_POS (16U) +#define GLB_REG_GPIO_9_IE_LEN (1U) +#define GLB_REG_GPIO_9_IE_MSK (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS) +#define GLB_REG_GPIO_9_IE_UMSK (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)) +#define GLB_REG_GPIO_9_SMT GLB_REG_GPIO_9_SMT +#define GLB_REG_GPIO_9_SMT_POS (17U) +#define GLB_REG_GPIO_9_SMT_LEN (1U) +#define GLB_REG_GPIO_9_SMT_MSK (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS) +#define GLB_REG_GPIO_9_SMT_UMSK (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)) +#define GLB_REG_GPIO_9_DRV GLB_REG_GPIO_9_DRV +#define GLB_REG_GPIO_9_DRV_POS (18U) +#define GLB_REG_GPIO_9_DRV_LEN (2U) +#define GLB_REG_GPIO_9_DRV_MSK (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS) +#define GLB_REG_GPIO_9_DRV_UMSK (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)) +#define GLB_REG_GPIO_9_PU GLB_REG_GPIO_9_PU +#define GLB_REG_GPIO_9_PU_POS (20U) +#define GLB_REG_GPIO_9_PU_LEN (1U) +#define GLB_REG_GPIO_9_PU_MSK (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS) +#define GLB_REG_GPIO_9_PU_UMSK (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)) +#define GLB_REG_GPIO_9_PD GLB_REG_GPIO_9_PD +#define GLB_REG_GPIO_9_PD_POS (21U) +#define GLB_REG_GPIO_9_PD_LEN (1U) +#define GLB_REG_GPIO_9_PD_MSK (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS) +#define GLB_REG_GPIO_9_PD_UMSK (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)) +#define GLB_REG_GPIO_9_FUNC_SEL GLB_REG_GPIO_9_FUNC_SEL +#define GLB_REG_GPIO_9_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_9_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_9_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS) +#define GLB_REG_GPIO_9_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)) + +/* 0x114 : GPIO_CFGCTL5 */ +#define GLB_GPIO_CFGCTL5_OFFSET (0x114) +#define GLB_REG_GPIO_10_IE GLB_REG_GPIO_10_IE +#define GLB_REG_GPIO_10_IE_POS (0U) +#define GLB_REG_GPIO_10_IE_LEN (1U) +#define GLB_REG_GPIO_10_IE_MSK (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS) +#define GLB_REG_GPIO_10_IE_UMSK (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)) +#define GLB_REG_GPIO_10_SMT GLB_REG_GPIO_10_SMT +#define GLB_REG_GPIO_10_SMT_POS (1U) +#define GLB_REG_GPIO_10_SMT_LEN (1U) +#define GLB_REG_GPIO_10_SMT_MSK (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS) +#define GLB_REG_GPIO_10_SMT_UMSK (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)) +#define GLB_REG_GPIO_10_DRV GLB_REG_GPIO_10_DRV +#define GLB_REG_GPIO_10_DRV_POS (2U) +#define GLB_REG_GPIO_10_DRV_LEN (2U) +#define GLB_REG_GPIO_10_DRV_MSK (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS) +#define GLB_REG_GPIO_10_DRV_UMSK (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)) +#define GLB_REG_GPIO_10_PU GLB_REG_GPIO_10_PU +#define GLB_REG_GPIO_10_PU_POS (4U) +#define GLB_REG_GPIO_10_PU_LEN (1U) +#define GLB_REG_GPIO_10_PU_MSK (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS) +#define GLB_REG_GPIO_10_PU_UMSK (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)) +#define GLB_REG_GPIO_10_PD GLB_REG_GPIO_10_PD +#define GLB_REG_GPIO_10_PD_POS (5U) +#define GLB_REG_GPIO_10_PD_LEN (1U) +#define GLB_REG_GPIO_10_PD_MSK (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS) +#define GLB_REG_GPIO_10_PD_UMSK (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)) +#define GLB_REG_GPIO_10_FUNC_SEL GLB_REG_GPIO_10_FUNC_SEL +#define GLB_REG_GPIO_10_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_10_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_10_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS) +#define GLB_REG_GPIO_10_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)) +#define GLB_REG_GPIO_11_IE GLB_REG_GPIO_11_IE +#define GLB_REG_GPIO_11_IE_POS (16U) +#define GLB_REG_GPIO_11_IE_LEN (1U) +#define GLB_REG_GPIO_11_IE_MSK (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS) +#define GLB_REG_GPIO_11_IE_UMSK (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)) +#define GLB_REG_GPIO_11_SMT GLB_REG_GPIO_11_SMT +#define GLB_REG_GPIO_11_SMT_POS (17U) +#define GLB_REG_GPIO_11_SMT_LEN (1U) +#define GLB_REG_GPIO_11_SMT_MSK (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS) +#define GLB_REG_GPIO_11_SMT_UMSK (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)) +#define GLB_REG_GPIO_11_DRV GLB_REG_GPIO_11_DRV +#define GLB_REG_GPIO_11_DRV_POS (18U) +#define GLB_REG_GPIO_11_DRV_LEN (2U) +#define GLB_REG_GPIO_11_DRV_MSK (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS) +#define GLB_REG_GPIO_11_DRV_UMSK (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)) +#define GLB_REG_GPIO_11_PU GLB_REG_GPIO_11_PU +#define GLB_REG_GPIO_11_PU_POS (20U) +#define GLB_REG_GPIO_11_PU_LEN (1U) +#define GLB_REG_GPIO_11_PU_MSK (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS) +#define GLB_REG_GPIO_11_PU_UMSK (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)) +#define GLB_REG_GPIO_11_PD GLB_REG_GPIO_11_PD +#define GLB_REG_GPIO_11_PD_POS (21U) +#define GLB_REG_GPIO_11_PD_LEN (1U) +#define GLB_REG_GPIO_11_PD_MSK (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS) +#define GLB_REG_GPIO_11_PD_UMSK (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)) +#define GLB_REG_GPIO_11_FUNC_SEL GLB_REG_GPIO_11_FUNC_SEL +#define GLB_REG_GPIO_11_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_11_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_11_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS) +#define GLB_REG_GPIO_11_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)) + +/* 0x118 : GPIO_CFGCTL6 */ +#define GLB_GPIO_CFGCTL6_OFFSET (0x118) +#define GLB_REG_GPIO_12_IE GLB_REG_GPIO_12_IE +#define GLB_REG_GPIO_12_IE_POS (0U) +#define GLB_REG_GPIO_12_IE_LEN (1U) +#define GLB_REG_GPIO_12_IE_MSK (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS) +#define GLB_REG_GPIO_12_IE_UMSK (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)) +#define GLB_REG_GPIO_12_SMT GLB_REG_GPIO_12_SMT +#define GLB_REG_GPIO_12_SMT_POS (1U) +#define GLB_REG_GPIO_12_SMT_LEN (1U) +#define GLB_REG_GPIO_12_SMT_MSK (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS) +#define GLB_REG_GPIO_12_SMT_UMSK (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)) +#define GLB_REG_GPIO_12_DRV GLB_REG_GPIO_12_DRV +#define GLB_REG_GPIO_12_DRV_POS (2U) +#define GLB_REG_GPIO_12_DRV_LEN (2U) +#define GLB_REG_GPIO_12_DRV_MSK (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS) +#define GLB_REG_GPIO_12_DRV_UMSK (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)) +#define GLB_REG_GPIO_12_PU GLB_REG_GPIO_12_PU +#define GLB_REG_GPIO_12_PU_POS (4U) +#define GLB_REG_GPIO_12_PU_LEN (1U) +#define GLB_REG_GPIO_12_PU_MSK (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS) +#define GLB_REG_GPIO_12_PU_UMSK (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)) +#define GLB_REG_GPIO_12_PD GLB_REG_GPIO_12_PD +#define GLB_REG_GPIO_12_PD_POS (5U) +#define GLB_REG_GPIO_12_PD_LEN (1U) +#define GLB_REG_GPIO_12_PD_MSK (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS) +#define GLB_REG_GPIO_12_PD_UMSK (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)) +#define GLB_REG_GPIO_12_FUNC_SEL GLB_REG_GPIO_12_FUNC_SEL +#define GLB_REG_GPIO_12_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_12_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_12_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS) +#define GLB_REG_GPIO_12_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)) +#define GLB_REG_GPIO_13_IE GLB_REG_GPIO_13_IE +#define GLB_REG_GPIO_13_IE_POS (16U) +#define GLB_REG_GPIO_13_IE_LEN (1U) +#define GLB_REG_GPIO_13_IE_MSK (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS) +#define GLB_REG_GPIO_13_IE_UMSK (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)) +#define GLB_REG_GPIO_13_SMT GLB_REG_GPIO_13_SMT +#define GLB_REG_GPIO_13_SMT_POS (17U) +#define GLB_REG_GPIO_13_SMT_LEN (1U) +#define GLB_REG_GPIO_13_SMT_MSK (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS) +#define GLB_REG_GPIO_13_SMT_UMSK (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)) +#define GLB_REG_GPIO_13_DRV GLB_REG_GPIO_13_DRV +#define GLB_REG_GPIO_13_DRV_POS (18U) +#define GLB_REG_GPIO_13_DRV_LEN (2U) +#define GLB_REG_GPIO_13_DRV_MSK (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS) +#define GLB_REG_GPIO_13_DRV_UMSK (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)) +#define GLB_REG_GPIO_13_PU GLB_REG_GPIO_13_PU +#define GLB_REG_GPIO_13_PU_POS (20U) +#define GLB_REG_GPIO_13_PU_LEN (1U) +#define GLB_REG_GPIO_13_PU_MSK (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS) +#define GLB_REG_GPIO_13_PU_UMSK (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)) +#define GLB_REG_GPIO_13_PD GLB_REG_GPIO_13_PD +#define GLB_REG_GPIO_13_PD_POS (21U) +#define GLB_REG_GPIO_13_PD_LEN (1U) +#define GLB_REG_GPIO_13_PD_MSK (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS) +#define GLB_REG_GPIO_13_PD_UMSK (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)) +#define GLB_REG_GPIO_13_FUNC_SEL GLB_REG_GPIO_13_FUNC_SEL +#define GLB_REG_GPIO_13_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_13_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_13_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS) +#define GLB_REG_GPIO_13_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)) + +/* 0x11C : GPIO_CFGCTL7 */ +#define GLB_GPIO_CFGCTL7_OFFSET (0x11C) +#define GLB_REG_GPIO_14_IE GLB_REG_GPIO_14_IE +#define GLB_REG_GPIO_14_IE_POS (0U) +#define GLB_REG_GPIO_14_IE_LEN (1U) +#define GLB_REG_GPIO_14_IE_MSK (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS) +#define GLB_REG_GPIO_14_IE_UMSK (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)) +#define GLB_REG_GPIO_14_SMT GLB_REG_GPIO_14_SMT +#define GLB_REG_GPIO_14_SMT_POS (1U) +#define GLB_REG_GPIO_14_SMT_LEN (1U) +#define GLB_REG_GPIO_14_SMT_MSK (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS) +#define GLB_REG_GPIO_14_SMT_UMSK (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)) +#define GLB_REG_GPIO_14_DRV GLB_REG_GPIO_14_DRV +#define GLB_REG_GPIO_14_DRV_POS (2U) +#define GLB_REG_GPIO_14_DRV_LEN (2U) +#define GLB_REG_GPIO_14_DRV_MSK (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS) +#define GLB_REG_GPIO_14_DRV_UMSK (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)) +#define GLB_REG_GPIO_14_PU GLB_REG_GPIO_14_PU +#define GLB_REG_GPIO_14_PU_POS (4U) +#define GLB_REG_GPIO_14_PU_LEN (1U) +#define GLB_REG_GPIO_14_PU_MSK (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS) +#define GLB_REG_GPIO_14_PU_UMSK (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)) +#define GLB_REG_GPIO_14_PD GLB_REG_GPIO_14_PD +#define GLB_REG_GPIO_14_PD_POS (5U) +#define GLB_REG_GPIO_14_PD_LEN (1U) +#define GLB_REG_GPIO_14_PD_MSK (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS) +#define GLB_REG_GPIO_14_PD_UMSK (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)) +#define GLB_REG_GPIO_14_FUNC_SEL GLB_REG_GPIO_14_FUNC_SEL +#define GLB_REG_GPIO_14_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_14_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_14_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS) +#define GLB_REG_GPIO_14_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)) +#define GLB_REG_GPIO_15_IE GLB_REG_GPIO_15_IE +#define GLB_REG_GPIO_15_IE_POS (16U) +#define GLB_REG_GPIO_15_IE_LEN (1U) +#define GLB_REG_GPIO_15_IE_MSK (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS) +#define GLB_REG_GPIO_15_IE_UMSK (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)) +#define GLB_REG_GPIO_15_SMT GLB_REG_GPIO_15_SMT +#define GLB_REG_GPIO_15_SMT_POS (17U) +#define GLB_REG_GPIO_15_SMT_LEN (1U) +#define GLB_REG_GPIO_15_SMT_MSK (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS) +#define GLB_REG_GPIO_15_SMT_UMSK (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)) +#define GLB_REG_GPIO_15_DRV GLB_REG_GPIO_15_DRV +#define GLB_REG_GPIO_15_DRV_POS (18U) +#define GLB_REG_GPIO_15_DRV_LEN (2U) +#define GLB_REG_GPIO_15_DRV_MSK (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS) +#define GLB_REG_GPIO_15_DRV_UMSK (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)) +#define GLB_REG_GPIO_15_PU GLB_REG_GPIO_15_PU +#define GLB_REG_GPIO_15_PU_POS (20U) +#define GLB_REG_GPIO_15_PU_LEN (1U) +#define GLB_REG_GPIO_15_PU_MSK (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS) +#define GLB_REG_GPIO_15_PU_UMSK (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)) +#define GLB_REG_GPIO_15_PD GLB_REG_GPIO_15_PD +#define GLB_REG_GPIO_15_PD_POS (21U) +#define GLB_REG_GPIO_15_PD_LEN (1U) +#define GLB_REG_GPIO_15_PD_MSK (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS) +#define GLB_REG_GPIO_15_PD_UMSK (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)) +#define GLB_REG_GPIO_15_FUNC_SEL GLB_REG_GPIO_15_FUNC_SEL +#define GLB_REG_GPIO_15_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_15_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_15_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS) +#define GLB_REG_GPIO_15_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)) + +/* 0x120 : GPIO_CFGCTL8 */ +#define GLB_GPIO_CFGCTL8_OFFSET (0x120) +#define GLB_REG_GPIO_16_IE GLB_REG_GPIO_16_IE +#define GLB_REG_GPIO_16_IE_POS (0U) +#define GLB_REG_GPIO_16_IE_LEN (1U) +#define GLB_REG_GPIO_16_IE_MSK (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS) +#define GLB_REG_GPIO_16_IE_UMSK (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)) +#define GLB_REG_GPIO_16_SMT GLB_REG_GPIO_16_SMT +#define GLB_REG_GPIO_16_SMT_POS (1U) +#define GLB_REG_GPIO_16_SMT_LEN (1U) +#define GLB_REG_GPIO_16_SMT_MSK (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS) +#define GLB_REG_GPIO_16_SMT_UMSK (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)) +#define GLB_REG_GPIO_16_DRV GLB_REG_GPIO_16_DRV +#define GLB_REG_GPIO_16_DRV_POS (2U) +#define GLB_REG_GPIO_16_DRV_LEN (2U) +#define GLB_REG_GPIO_16_DRV_MSK (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS) +#define GLB_REG_GPIO_16_DRV_UMSK (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)) +#define GLB_REG_GPIO_16_PU GLB_REG_GPIO_16_PU +#define GLB_REG_GPIO_16_PU_POS (4U) +#define GLB_REG_GPIO_16_PU_LEN (1U) +#define GLB_REG_GPIO_16_PU_MSK (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS) +#define GLB_REG_GPIO_16_PU_UMSK (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)) +#define GLB_REG_GPIO_16_PD GLB_REG_GPIO_16_PD +#define GLB_REG_GPIO_16_PD_POS (5U) +#define GLB_REG_GPIO_16_PD_LEN (1U) +#define GLB_REG_GPIO_16_PD_MSK (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS) +#define GLB_REG_GPIO_16_PD_UMSK (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)) +#define GLB_REG_GPIO_16_FUNC_SEL GLB_REG_GPIO_16_FUNC_SEL +#define GLB_REG_GPIO_16_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_16_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_16_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS) +#define GLB_REG_GPIO_16_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)) +#define GLB_REG_GPIO_17_IE GLB_REG_GPIO_17_IE +#define GLB_REG_GPIO_17_IE_POS (16U) +#define GLB_REG_GPIO_17_IE_LEN (1U) +#define GLB_REG_GPIO_17_IE_MSK (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS) +#define GLB_REG_GPIO_17_IE_UMSK (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)) +#define GLB_REG_GPIO_17_SMT GLB_REG_GPIO_17_SMT +#define GLB_REG_GPIO_17_SMT_POS (17U) +#define GLB_REG_GPIO_17_SMT_LEN (1U) +#define GLB_REG_GPIO_17_SMT_MSK (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS) +#define GLB_REG_GPIO_17_SMT_UMSK (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)) +#define GLB_REG_GPIO_17_DRV GLB_REG_GPIO_17_DRV +#define GLB_REG_GPIO_17_DRV_POS (18U) +#define GLB_REG_GPIO_17_DRV_LEN (2U) +#define GLB_REG_GPIO_17_DRV_MSK (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS) +#define GLB_REG_GPIO_17_DRV_UMSK (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)) +#define GLB_REG_GPIO_17_PU GLB_REG_GPIO_17_PU +#define GLB_REG_GPIO_17_PU_POS (20U) +#define GLB_REG_GPIO_17_PU_LEN (1U) +#define GLB_REG_GPIO_17_PU_MSK (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS) +#define GLB_REG_GPIO_17_PU_UMSK (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)) +#define GLB_REG_GPIO_17_PD GLB_REG_GPIO_17_PD +#define GLB_REG_GPIO_17_PD_POS (21U) +#define GLB_REG_GPIO_17_PD_LEN (1U) +#define GLB_REG_GPIO_17_PD_MSK (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS) +#define GLB_REG_GPIO_17_PD_UMSK (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)) +#define GLB_REG_GPIO_17_FUNC_SEL GLB_REG_GPIO_17_FUNC_SEL +#define GLB_REG_GPIO_17_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_17_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_17_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS) +#define GLB_REG_GPIO_17_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)) + +/* 0x124 : GPIO_CFGCTL9 */ +#define GLB_GPIO_CFGCTL9_OFFSET (0x124) +#define GLB_REG_GPIO_18_IE GLB_REG_GPIO_18_IE +#define GLB_REG_GPIO_18_IE_POS (0U) +#define GLB_REG_GPIO_18_IE_LEN (1U) +#define GLB_REG_GPIO_18_IE_MSK (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS) +#define GLB_REG_GPIO_18_IE_UMSK (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)) +#define GLB_REG_GPIO_18_SMT GLB_REG_GPIO_18_SMT +#define GLB_REG_GPIO_18_SMT_POS (1U) +#define GLB_REG_GPIO_18_SMT_LEN (1U) +#define GLB_REG_GPIO_18_SMT_MSK (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS) +#define GLB_REG_GPIO_18_SMT_UMSK (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)) +#define GLB_REG_GPIO_18_DRV GLB_REG_GPIO_18_DRV +#define GLB_REG_GPIO_18_DRV_POS (2U) +#define GLB_REG_GPIO_18_DRV_LEN (2U) +#define GLB_REG_GPIO_18_DRV_MSK (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS) +#define GLB_REG_GPIO_18_DRV_UMSK (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)) +#define GLB_REG_GPIO_18_PU GLB_REG_GPIO_18_PU +#define GLB_REG_GPIO_18_PU_POS (4U) +#define GLB_REG_GPIO_18_PU_LEN (1U) +#define GLB_REG_GPIO_18_PU_MSK (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS) +#define GLB_REG_GPIO_18_PU_UMSK (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)) +#define GLB_REG_GPIO_18_PD GLB_REG_GPIO_18_PD +#define GLB_REG_GPIO_18_PD_POS (5U) +#define GLB_REG_GPIO_18_PD_LEN (1U) +#define GLB_REG_GPIO_18_PD_MSK (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS) +#define GLB_REG_GPIO_18_PD_UMSK (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)) +#define GLB_REG_GPIO_18_FUNC_SEL GLB_REG_GPIO_18_FUNC_SEL +#define GLB_REG_GPIO_18_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_18_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_18_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS) +#define GLB_REG_GPIO_18_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)) +#define GLB_REG_GPIO_19_IE GLB_REG_GPIO_19_IE +#define GLB_REG_GPIO_19_IE_POS (16U) +#define GLB_REG_GPIO_19_IE_LEN (1U) +#define GLB_REG_GPIO_19_IE_MSK (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS) +#define GLB_REG_GPIO_19_IE_UMSK (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)) +#define GLB_REG_GPIO_19_SMT GLB_REG_GPIO_19_SMT +#define GLB_REG_GPIO_19_SMT_POS (17U) +#define GLB_REG_GPIO_19_SMT_LEN (1U) +#define GLB_REG_GPIO_19_SMT_MSK (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS) +#define GLB_REG_GPIO_19_SMT_UMSK (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)) +#define GLB_REG_GPIO_19_DRV GLB_REG_GPIO_19_DRV +#define GLB_REG_GPIO_19_DRV_POS (18U) +#define GLB_REG_GPIO_19_DRV_LEN (2U) +#define GLB_REG_GPIO_19_DRV_MSK (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS) +#define GLB_REG_GPIO_19_DRV_UMSK (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)) +#define GLB_REG_GPIO_19_PU GLB_REG_GPIO_19_PU +#define GLB_REG_GPIO_19_PU_POS (20U) +#define GLB_REG_GPIO_19_PU_LEN (1U) +#define GLB_REG_GPIO_19_PU_MSK (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS) +#define GLB_REG_GPIO_19_PU_UMSK (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)) +#define GLB_REG_GPIO_19_PD GLB_REG_GPIO_19_PD +#define GLB_REG_GPIO_19_PD_POS (21U) +#define GLB_REG_GPIO_19_PD_LEN (1U) +#define GLB_REG_GPIO_19_PD_MSK (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS) +#define GLB_REG_GPIO_19_PD_UMSK (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)) +#define GLB_REG_GPIO_19_FUNC_SEL GLB_REG_GPIO_19_FUNC_SEL +#define GLB_REG_GPIO_19_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_19_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_19_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS) +#define GLB_REG_GPIO_19_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)) + +/* 0x128 : GPIO_CFGCTL10 */ +#define GLB_GPIO_CFGCTL10_OFFSET (0x128) +#define GLB_REG_GPIO_20_IE GLB_REG_GPIO_20_IE +#define GLB_REG_GPIO_20_IE_POS (0U) +#define GLB_REG_GPIO_20_IE_LEN (1U) +#define GLB_REG_GPIO_20_IE_MSK (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS) +#define GLB_REG_GPIO_20_IE_UMSK (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)) +#define GLB_REG_GPIO_20_SMT GLB_REG_GPIO_20_SMT +#define GLB_REG_GPIO_20_SMT_POS (1U) +#define GLB_REG_GPIO_20_SMT_LEN (1U) +#define GLB_REG_GPIO_20_SMT_MSK (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS) +#define GLB_REG_GPIO_20_SMT_UMSK (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)) +#define GLB_REG_GPIO_20_DRV GLB_REG_GPIO_20_DRV +#define GLB_REG_GPIO_20_DRV_POS (2U) +#define GLB_REG_GPIO_20_DRV_LEN (2U) +#define GLB_REG_GPIO_20_DRV_MSK (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS) +#define GLB_REG_GPIO_20_DRV_UMSK (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)) +#define GLB_REG_GPIO_20_PU GLB_REG_GPIO_20_PU +#define GLB_REG_GPIO_20_PU_POS (4U) +#define GLB_REG_GPIO_20_PU_LEN (1U) +#define GLB_REG_GPIO_20_PU_MSK (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS) +#define GLB_REG_GPIO_20_PU_UMSK (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)) +#define GLB_REG_GPIO_20_PD GLB_REG_GPIO_20_PD +#define GLB_REG_GPIO_20_PD_POS (5U) +#define GLB_REG_GPIO_20_PD_LEN (1U) +#define GLB_REG_GPIO_20_PD_MSK (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS) +#define GLB_REG_GPIO_20_PD_UMSK (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)) +#define GLB_REG_GPIO_20_FUNC_SEL GLB_REG_GPIO_20_FUNC_SEL +#define GLB_REG_GPIO_20_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_20_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_20_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS) +#define GLB_REG_GPIO_20_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)) +#define GLB_REG_GPIO_21_IE GLB_REG_GPIO_21_IE +#define GLB_REG_GPIO_21_IE_POS (16U) +#define GLB_REG_GPIO_21_IE_LEN (1U) +#define GLB_REG_GPIO_21_IE_MSK (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS) +#define GLB_REG_GPIO_21_IE_UMSK (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)) +#define GLB_REG_GPIO_21_SMT GLB_REG_GPIO_21_SMT +#define GLB_REG_GPIO_21_SMT_POS (17U) +#define GLB_REG_GPIO_21_SMT_LEN (1U) +#define GLB_REG_GPIO_21_SMT_MSK (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS) +#define GLB_REG_GPIO_21_SMT_UMSK (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)) +#define GLB_REG_GPIO_21_DRV GLB_REG_GPIO_21_DRV +#define GLB_REG_GPIO_21_DRV_POS (18U) +#define GLB_REG_GPIO_21_DRV_LEN (2U) +#define GLB_REG_GPIO_21_DRV_MSK (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS) +#define GLB_REG_GPIO_21_DRV_UMSK (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)) +#define GLB_REG_GPIO_21_PU GLB_REG_GPIO_21_PU +#define GLB_REG_GPIO_21_PU_POS (20U) +#define GLB_REG_GPIO_21_PU_LEN (1U) +#define GLB_REG_GPIO_21_PU_MSK (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS) +#define GLB_REG_GPIO_21_PU_UMSK (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)) +#define GLB_REG_GPIO_21_PD GLB_REG_GPIO_21_PD +#define GLB_REG_GPIO_21_PD_POS (21U) +#define GLB_REG_GPIO_21_PD_LEN (1U) +#define GLB_REG_GPIO_21_PD_MSK (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS) +#define GLB_REG_GPIO_21_PD_UMSK (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)) +#define GLB_REG_GPIO_21_FUNC_SEL GLB_REG_GPIO_21_FUNC_SEL +#define GLB_REG_GPIO_21_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_21_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_21_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS) +#define GLB_REG_GPIO_21_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)) + +/* 0x12C : GPIO_CFGCTL11 */ +#define GLB_GPIO_CFGCTL11_OFFSET (0x12C) +#define GLB_REG_GPIO_22_IE GLB_REG_GPIO_22_IE +#define GLB_REG_GPIO_22_IE_POS (0U) +#define GLB_REG_GPIO_22_IE_LEN (1U) +#define GLB_REG_GPIO_22_IE_MSK (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS) +#define GLB_REG_GPIO_22_IE_UMSK (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)) +#define GLB_REG_GPIO_22_SMT GLB_REG_GPIO_22_SMT +#define GLB_REG_GPIO_22_SMT_POS (1U) +#define GLB_REG_GPIO_22_SMT_LEN (1U) +#define GLB_REG_GPIO_22_SMT_MSK (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS) +#define GLB_REG_GPIO_22_SMT_UMSK (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)) +#define GLB_REG_GPIO_22_DRV GLB_REG_GPIO_22_DRV +#define GLB_REG_GPIO_22_DRV_POS (2U) +#define GLB_REG_GPIO_22_DRV_LEN (2U) +#define GLB_REG_GPIO_22_DRV_MSK (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS) +#define GLB_REG_GPIO_22_DRV_UMSK (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)) +#define GLB_REG_GPIO_22_PU GLB_REG_GPIO_22_PU +#define GLB_REG_GPIO_22_PU_POS (4U) +#define GLB_REG_GPIO_22_PU_LEN (1U) +#define GLB_REG_GPIO_22_PU_MSK (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS) +#define GLB_REG_GPIO_22_PU_UMSK (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)) +#define GLB_REG_GPIO_22_PD GLB_REG_GPIO_22_PD +#define GLB_REG_GPIO_22_PD_POS (5U) +#define GLB_REG_GPIO_22_PD_LEN (1U) +#define GLB_REG_GPIO_22_PD_MSK (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS) +#define GLB_REG_GPIO_22_PD_UMSK (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)) +#define GLB_REG_GPIO_22_FUNC_SEL GLB_REG_GPIO_22_FUNC_SEL +#define GLB_REG_GPIO_22_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_22_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_22_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS) +#define GLB_REG_GPIO_22_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)) +#define GLB_REG_GPIO_23_IE GLB_REG_GPIO_23_IE +#define GLB_REG_GPIO_23_IE_POS (16U) +#define GLB_REG_GPIO_23_IE_LEN (1U) +#define GLB_REG_GPIO_23_IE_MSK (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS) +#define GLB_REG_GPIO_23_IE_UMSK (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)) +#define GLB_REG_GPIO_23_SMT GLB_REG_GPIO_23_SMT +#define GLB_REG_GPIO_23_SMT_POS (17U) +#define GLB_REG_GPIO_23_SMT_LEN (1U) +#define GLB_REG_GPIO_23_SMT_MSK (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS) +#define GLB_REG_GPIO_23_SMT_UMSK (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)) +#define GLB_REG_GPIO_23_DRV GLB_REG_GPIO_23_DRV +#define GLB_REG_GPIO_23_DRV_POS (18U) +#define GLB_REG_GPIO_23_DRV_LEN (2U) +#define GLB_REG_GPIO_23_DRV_MSK (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS) +#define GLB_REG_GPIO_23_DRV_UMSK (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)) +#define GLB_REG_GPIO_23_PU GLB_REG_GPIO_23_PU +#define GLB_REG_GPIO_23_PU_POS (20U) +#define GLB_REG_GPIO_23_PU_LEN (1U) +#define GLB_REG_GPIO_23_PU_MSK (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS) +#define GLB_REG_GPIO_23_PU_UMSK (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)) +#define GLB_REG_GPIO_23_PD GLB_REG_GPIO_23_PD +#define GLB_REG_GPIO_23_PD_POS (21U) +#define GLB_REG_GPIO_23_PD_LEN (1U) +#define GLB_REG_GPIO_23_PD_MSK (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS) +#define GLB_REG_GPIO_23_PD_UMSK (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)) + +/* 0x130 : GPIO_CFGCTL12 */ +#define GLB_GPIO_CFGCTL12_OFFSET (0x130) +#define GLB_REG_GPIO_24_IE GLB_REG_GPIO_24_IE +#define GLB_REG_GPIO_24_IE_POS (0U) +#define GLB_REG_GPIO_24_IE_LEN (1U) +#define GLB_REG_GPIO_24_IE_MSK (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS) +#define GLB_REG_GPIO_24_IE_UMSK (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)) +#define GLB_REG_GPIO_24_SMT GLB_REG_GPIO_24_SMT +#define GLB_REG_GPIO_24_SMT_POS (1U) +#define GLB_REG_GPIO_24_SMT_LEN (1U) +#define GLB_REG_GPIO_24_SMT_MSK (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS) +#define GLB_REG_GPIO_24_SMT_UMSK (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)) +#define GLB_REG_GPIO_24_DRV GLB_REG_GPIO_24_DRV +#define GLB_REG_GPIO_24_DRV_POS (2U) +#define GLB_REG_GPIO_24_DRV_LEN (2U) +#define GLB_REG_GPIO_24_DRV_MSK (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS) +#define GLB_REG_GPIO_24_DRV_UMSK (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)) +#define GLB_REG_GPIO_24_PU GLB_REG_GPIO_24_PU +#define GLB_REG_GPIO_24_PU_POS (4U) +#define GLB_REG_GPIO_24_PU_LEN (1U) +#define GLB_REG_GPIO_24_PU_MSK (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS) +#define GLB_REG_GPIO_24_PU_UMSK (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)) +#define GLB_REG_GPIO_24_PD GLB_REG_GPIO_24_PD +#define GLB_REG_GPIO_24_PD_POS (5U) +#define GLB_REG_GPIO_24_PD_LEN (1U) +#define GLB_REG_GPIO_24_PD_MSK (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS) +#define GLB_REG_GPIO_24_PD_UMSK (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)) +#define GLB_REG_GPIO_25_IE GLB_REG_GPIO_25_IE +#define GLB_REG_GPIO_25_IE_POS (16U) +#define GLB_REG_GPIO_25_IE_LEN (1U) +#define GLB_REG_GPIO_25_IE_MSK (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS) +#define GLB_REG_GPIO_25_IE_UMSK (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)) +#define GLB_REG_GPIO_25_SMT GLB_REG_GPIO_25_SMT +#define GLB_REG_GPIO_25_SMT_POS (17U) +#define GLB_REG_GPIO_25_SMT_LEN (1U) +#define GLB_REG_GPIO_25_SMT_MSK (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS) +#define GLB_REG_GPIO_25_SMT_UMSK (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)) +#define GLB_REG_GPIO_25_DRV GLB_REG_GPIO_25_DRV +#define GLB_REG_GPIO_25_DRV_POS (18U) +#define GLB_REG_GPIO_25_DRV_LEN (2U) +#define GLB_REG_GPIO_25_DRV_MSK (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS) +#define GLB_REG_GPIO_25_DRV_UMSK (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)) +#define GLB_REG_GPIO_25_PU GLB_REG_GPIO_25_PU +#define GLB_REG_GPIO_25_PU_POS (20U) +#define GLB_REG_GPIO_25_PU_LEN (1U) +#define GLB_REG_GPIO_25_PU_MSK (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS) +#define GLB_REG_GPIO_25_PU_UMSK (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)) +#define GLB_REG_GPIO_25_PD GLB_REG_GPIO_25_PD +#define GLB_REG_GPIO_25_PD_POS (21U) +#define GLB_REG_GPIO_25_PD_LEN (1U) +#define GLB_REG_GPIO_25_PD_MSK (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS) +#define GLB_REG_GPIO_25_PD_UMSK (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)) + +/* 0x134 : GPIO_CFGCTL13 */ +#define GLB_GPIO_CFGCTL13_OFFSET (0x134) +#define GLB_REG_GPIO_26_IE GLB_REG_GPIO_26_IE +#define GLB_REG_GPIO_26_IE_POS (0U) +#define GLB_REG_GPIO_26_IE_LEN (1U) +#define GLB_REG_GPIO_26_IE_MSK (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS) +#define GLB_REG_GPIO_26_IE_UMSK (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)) +#define GLB_REG_GPIO_26_SMT GLB_REG_GPIO_26_SMT +#define GLB_REG_GPIO_26_SMT_POS (1U) +#define GLB_REG_GPIO_26_SMT_LEN (1U) +#define GLB_REG_GPIO_26_SMT_MSK (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS) +#define GLB_REG_GPIO_26_SMT_UMSK (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)) +#define GLB_REG_GPIO_26_DRV GLB_REG_GPIO_26_DRV +#define GLB_REG_GPIO_26_DRV_POS (2U) +#define GLB_REG_GPIO_26_DRV_LEN (2U) +#define GLB_REG_GPIO_26_DRV_MSK (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS) +#define GLB_REG_GPIO_26_DRV_UMSK (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)) +#define GLB_REG_GPIO_26_PU GLB_REG_GPIO_26_PU +#define GLB_REG_GPIO_26_PU_POS (4U) +#define GLB_REG_GPIO_26_PU_LEN (1U) +#define GLB_REG_GPIO_26_PU_MSK (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS) +#define GLB_REG_GPIO_26_PU_UMSK (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)) +#define GLB_REG_GPIO_26_PD GLB_REG_GPIO_26_PD +#define GLB_REG_GPIO_26_PD_POS (5U) +#define GLB_REG_GPIO_26_PD_LEN (1U) +#define GLB_REG_GPIO_26_PD_MSK (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS) +#define GLB_REG_GPIO_26_PD_UMSK (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)) +#define GLB_REG_GPIO_27_IE GLB_REG_GPIO_27_IE +#define GLB_REG_GPIO_27_IE_POS (16U) +#define GLB_REG_GPIO_27_IE_LEN (1U) +#define GLB_REG_GPIO_27_IE_MSK (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS) +#define GLB_REG_GPIO_27_IE_UMSK (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)) +#define GLB_REG_GPIO_27_SMT GLB_REG_GPIO_27_SMT +#define GLB_REG_GPIO_27_SMT_POS (17U) +#define GLB_REG_GPIO_27_SMT_LEN (1U) +#define GLB_REG_GPIO_27_SMT_MSK (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS) +#define GLB_REG_GPIO_27_SMT_UMSK (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)) +#define GLB_REG_GPIO_27_DRV GLB_REG_GPIO_27_DRV +#define GLB_REG_GPIO_27_DRV_POS (18U) +#define GLB_REG_GPIO_27_DRV_LEN (2U) +#define GLB_REG_GPIO_27_DRV_MSK (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS) +#define GLB_REG_GPIO_27_DRV_UMSK (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)) +#define GLB_REG_GPIO_27_PU GLB_REG_GPIO_27_PU +#define GLB_REG_GPIO_27_PU_POS (20U) +#define GLB_REG_GPIO_27_PU_LEN (1U) +#define GLB_REG_GPIO_27_PU_MSK (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS) +#define GLB_REG_GPIO_27_PU_UMSK (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)) +#define GLB_REG_GPIO_27_PD GLB_REG_GPIO_27_PD +#define GLB_REG_GPIO_27_PD_POS (21U) +#define GLB_REG_GPIO_27_PD_LEN (1U) +#define GLB_REG_GPIO_27_PD_MSK (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS) +#define GLB_REG_GPIO_27_PD_UMSK (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)) + +/* 0x138 : GPIO_CFGCTL14 */ +#define GLB_GPIO_CFGCTL14_OFFSET (0x138) +#define GLB_REG_GPIO_28_IE GLB_REG_GPIO_28_IE +#define GLB_REG_GPIO_28_IE_POS (0U) +#define GLB_REG_GPIO_28_IE_LEN (1U) +#define GLB_REG_GPIO_28_IE_MSK (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS) +#define GLB_REG_GPIO_28_IE_UMSK (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)) +#define GLB_REG_GPIO_28_SMT GLB_REG_GPIO_28_SMT +#define GLB_REG_GPIO_28_SMT_POS (1U) +#define GLB_REG_GPIO_28_SMT_LEN (1U) +#define GLB_REG_GPIO_28_SMT_MSK (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS) +#define GLB_REG_GPIO_28_SMT_UMSK (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)) +#define GLB_REG_GPIO_28_DRV GLB_REG_GPIO_28_DRV +#define GLB_REG_GPIO_28_DRV_POS (2U) +#define GLB_REG_GPIO_28_DRV_LEN (2U) +#define GLB_REG_GPIO_28_DRV_MSK (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS) +#define GLB_REG_GPIO_28_DRV_UMSK (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)) +#define GLB_REG_GPIO_28_PU GLB_REG_GPIO_28_PU +#define GLB_REG_GPIO_28_PU_POS (4U) +#define GLB_REG_GPIO_28_PU_LEN (1U) +#define GLB_REG_GPIO_28_PU_MSK (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS) +#define GLB_REG_GPIO_28_PU_UMSK (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)) +#define GLB_REG_GPIO_28_PD GLB_REG_GPIO_28_PD +#define GLB_REG_GPIO_28_PD_POS (5U) +#define GLB_REG_GPIO_28_PD_LEN (1U) +#define GLB_REG_GPIO_28_PD_MSK (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS) +#define GLB_REG_GPIO_28_PD_UMSK (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)) + +/* 0x180 : GPIO_CFGCTL30 */ +#define GLB_GPIO_CFGCTL30_OFFSET (0x180) +#define GLB_REG_GPIO_0_I GLB_REG_GPIO_0_I +#define GLB_REG_GPIO_0_I_POS (0U) +#define GLB_REG_GPIO_0_I_LEN (1U) +#define GLB_REG_GPIO_0_I_MSK (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS) +#define GLB_REG_GPIO_0_I_UMSK (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)) +#define GLB_REG_GPIO_1_I GLB_REG_GPIO_1_I +#define GLB_REG_GPIO_1_I_POS (1U) +#define GLB_REG_GPIO_1_I_LEN (1U) +#define GLB_REG_GPIO_1_I_MSK (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS) +#define GLB_REG_GPIO_1_I_UMSK (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)) +#define GLB_REG_GPIO_2_I GLB_REG_GPIO_2_I +#define GLB_REG_GPIO_2_I_POS (2U) +#define GLB_REG_GPIO_2_I_LEN (1U) +#define GLB_REG_GPIO_2_I_MSK (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS) +#define GLB_REG_GPIO_2_I_UMSK (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)) +#define GLB_REG_GPIO_3_I GLB_REG_GPIO_3_I +#define GLB_REG_GPIO_3_I_POS (3U) +#define GLB_REG_GPIO_3_I_LEN (1U) +#define GLB_REG_GPIO_3_I_MSK (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS) +#define GLB_REG_GPIO_3_I_UMSK (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)) +#define GLB_REG_GPIO_4_I GLB_REG_GPIO_4_I +#define GLB_REG_GPIO_4_I_POS (4U) +#define GLB_REG_GPIO_4_I_LEN (1U) +#define GLB_REG_GPIO_4_I_MSK (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS) +#define GLB_REG_GPIO_4_I_UMSK (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)) +#define GLB_REG_GPIO_5_I GLB_REG_GPIO_5_I +#define GLB_REG_GPIO_5_I_POS (5U) +#define GLB_REG_GPIO_5_I_LEN (1U) +#define GLB_REG_GPIO_5_I_MSK (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS) +#define GLB_REG_GPIO_5_I_UMSK (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)) +#define GLB_REG_GPIO_6_I GLB_REG_GPIO_6_I +#define GLB_REG_GPIO_6_I_POS (6U) +#define GLB_REG_GPIO_6_I_LEN (1U) +#define GLB_REG_GPIO_6_I_MSK (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS) +#define GLB_REG_GPIO_6_I_UMSK (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)) +#define GLB_REG_GPIO_7_I GLB_REG_GPIO_7_I +#define GLB_REG_GPIO_7_I_POS (7U) +#define GLB_REG_GPIO_7_I_LEN (1U) +#define GLB_REG_GPIO_7_I_MSK (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS) +#define GLB_REG_GPIO_7_I_UMSK (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)) +#define GLB_REG_GPIO_8_I GLB_REG_GPIO_8_I +#define GLB_REG_GPIO_8_I_POS (8U) +#define GLB_REG_GPIO_8_I_LEN (1U) +#define GLB_REG_GPIO_8_I_MSK (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS) +#define GLB_REG_GPIO_8_I_UMSK (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)) +#define GLB_REG_GPIO_9_I GLB_REG_GPIO_9_I +#define GLB_REG_GPIO_9_I_POS (9U) +#define GLB_REG_GPIO_9_I_LEN (1U) +#define GLB_REG_GPIO_9_I_MSK (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS) +#define GLB_REG_GPIO_9_I_UMSK (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)) +#define GLB_REG_GPIO_10_I GLB_REG_GPIO_10_I +#define GLB_REG_GPIO_10_I_POS (10U) +#define GLB_REG_GPIO_10_I_LEN (1U) +#define GLB_REG_GPIO_10_I_MSK (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS) +#define GLB_REG_GPIO_10_I_UMSK (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)) +#define GLB_REG_GPIO_11_I GLB_REG_GPIO_11_I +#define GLB_REG_GPIO_11_I_POS (11U) +#define GLB_REG_GPIO_11_I_LEN (1U) +#define GLB_REG_GPIO_11_I_MSK (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS) +#define GLB_REG_GPIO_11_I_UMSK (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)) +#define GLB_REG_GPIO_12_I GLB_REG_GPIO_12_I +#define GLB_REG_GPIO_12_I_POS (12U) +#define GLB_REG_GPIO_12_I_LEN (1U) +#define GLB_REG_GPIO_12_I_MSK (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS) +#define GLB_REG_GPIO_12_I_UMSK (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)) +#define GLB_REG_GPIO_13_I GLB_REG_GPIO_13_I +#define GLB_REG_GPIO_13_I_POS (13U) +#define GLB_REG_GPIO_13_I_LEN (1U) +#define GLB_REG_GPIO_13_I_MSK (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS) +#define GLB_REG_GPIO_13_I_UMSK (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)) +#define GLB_REG_GPIO_14_I GLB_REG_GPIO_14_I +#define GLB_REG_GPIO_14_I_POS (14U) +#define GLB_REG_GPIO_14_I_LEN (1U) +#define GLB_REG_GPIO_14_I_MSK (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS) +#define GLB_REG_GPIO_14_I_UMSK (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)) +#define GLB_REG_GPIO_15_I GLB_REG_GPIO_15_I +#define GLB_REG_GPIO_15_I_POS (15U) +#define GLB_REG_GPIO_15_I_LEN (1U) +#define GLB_REG_GPIO_15_I_MSK (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS) +#define GLB_REG_GPIO_15_I_UMSK (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)) +#define GLB_REG_GPIO_16_I GLB_REG_GPIO_16_I +#define GLB_REG_GPIO_16_I_POS (16U) +#define GLB_REG_GPIO_16_I_LEN (1U) +#define GLB_REG_GPIO_16_I_MSK (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS) +#define GLB_REG_GPIO_16_I_UMSK (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)) +#define GLB_REG_GPIO_17_I GLB_REG_GPIO_17_I +#define GLB_REG_GPIO_17_I_POS (17U) +#define GLB_REG_GPIO_17_I_LEN (1U) +#define GLB_REG_GPIO_17_I_MSK (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS) +#define GLB_REG_GPIO_17_I_UMSK (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)) +#define GLB_REG_GPIO_18_I GLB_REG_GPIO_18_I +#define GLB_REG_GPIO_18_I_POS (18U) +#define GLB_REG_GPIO_18_I_LEN (1U) +#define GLB_REG_GPIO_18_I_MSK (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS) +#define GLB_REG_GPIO_18_I_UMSK (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)) +#define GLB_REG_GPIO_19_I GLB_REG_GPIO_19_I +#define GLB_REG_GPIO_19_I_POS (19U) +#define GLB_REG_GPIO_19_I_LEN (1U) +#define GLB_REG_GPIO_19_I_MSK (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS) +#define GLB_REG_GPIO_19_I_UMSK (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)) +#define GLB_REG_GPIO_20_I GLB_REG_GPIO_20_I +#define GLB_REG_GPIO_20_I_POS (20U) +#define GLB_REG_GPIO_20_I_LEN (1U) +#define GLB_REG_GPIO_20_I_MSK (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS) +#define GLB_REG_GPIO_20_I_UMSK (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)) +#define GLB_REG_GPIO_21_I GLB_REG_GPIO_21_I +#define GLB_REG_GPIO_21_I_POS (21U) +#define GLB_REG_GPIO_21_I_LEN (1U) +#define GLB_REG_GPIO_21_I_MSK (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS) +#define GLB_REG_GPIO_21_I_UMSK (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)) +#define GLB_REG_GPIO_22_I GLB_REG_GPIO_22_I +#define GLB_REG_GPIO_22_I_POS (22U) +#define GLB_REG_GPIO_22_I_LEN (1U) +#define GLB_REG_GPIO_22_I_MSK (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS) +#define GLB_REG_GPIO_22_I_UMSK (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)) + +/* 0x184 : GPIO_CFGCTL31 */ +#define GLB_GPIO_CFGCTL31_OFFSET (0x184) + +/* 0x188 : GPIO_CFGCTL32 */ +#define GLB_GPIO_CFGCTL32_OFFSET (0x188) +#define GLB_REG_GPIO_0_O GLB_REG_GPIO_0_O +#define GLB_REG_GPIO_0_O_POS (0U) +#define GLB_REG_GPIO_0_O_LEN (1U) +#define GLB_REG_GPIO_0_O_MSK (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS) +#define GLB_REG_GPIO_0_O_UMSK (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)) +#define GLB_REG_GPIO_1_O GLB_REG_GPIO_1_O +#define GLB_REG_GPIO_1_O_POS (1U) +#define GLB_REG_GPIO_1_O_LEN (1U) +#define GLB_REG_GPIO_1_O_MSK (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS) +#define GLB_REG_GPIO_1_O_UMSK (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)) +#define GLB_REG_GPIO_2_O GLB_REG_GPIO_2_O +#define GLB_REG_GPIO_2_O_POS (2U) +#define GLB_REG_GPIO_2_O_LEN (1U) +#define GLB_REG_GPIO_2_O_MSK (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS) +#define GLB_REG_GPIO_2_O_UMSK (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)) +#define GLB_REG_GPIO_3_O GLB_REG_GPIO_3_O +#define GLB_REG_GPIO_3_O_POS (3U) +#define GLB_REG_GPIO_3_O_LEN (1U) +#define GLB_REG_GPIO_3_O_MSK (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS) +#define GLB_REG_GPIO_3_O_UMSK (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)) +#define GLB_REG_GPIO_4_O GLB_REG_GPIO_4_O +#define GLB_REG_GPIO_4_O_POS (4U) +#define GLB_REG_GPIO_4_O_LEN (1U) +#define GLB_REG_GPIO_4_O_MSK (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS) +#define GLB_REG_GPIO_4_O_UMSK (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)) +#define GLB_REG_GPIO_5_O GLB_REG_GPIO_5_O +#define GLB_REG_GPIO_5_O_POS (5U) +#define GLB_REG_GPIO_5_O_LEN (1U) +#define GLB_REG_GPIO_5_O_MSK (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS) +#define GLB_REG_GPIO_5_O_UMSK (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)) +#define GLB_REG_GPIO_6_O GLB_REG_GPIO_6_O +#define GLB_REG_GPIO_6_O_POS (6U) +#define GLB_REG_GPIO_6_O_LEN (1U) +#define GLB_REG_GPIO_6_O_MSK (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS) +#define GLB_REG_GPIO_6_O_UMSK (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)) +#define GLB_REG_GPIO_7_O GLB_REG_GPIO_7_O +#define GLB_REG_GPIO_7_O_POS (7U) +#define GLB_REG_GPIO_7_O_LEN (1U) +#define GLB_REG_GPIO_7_O_MSK (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS) +#define GLB_REG_GPIO_7_O_UMSK (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)) +#define GLB_REG_GPIO_8_O GLB_REG_GPIO_8_O +#define GLB_REG_GPIO_8_O_POS (8U) +#define GLB_REG_GPIO_8_O_LEN (1U) +#define GLB_REG_GPIO_8_O_MSK (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS) +#define GLB_REG_GPIO_8_O_UMSK (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)) +#define GLB_REG_GPIO_9_O GLB_REG_GPIO_9_O +#define GLB_REG_GPIO_9_O_POS (9U) +#define GLB_REG_GPIO_9_O_LEN (1U) +#define GLB_REG_GPIO_9_O_MSK (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS) +#define GLB_REG_GPIO_9_O_UMSK (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)) +#define GLB_REG_GPIO_10_O GLB_REG_GPIO_10_O +#define GLB_REG_GPIO_10_O_POS (10U) +#define GLB_REG_GPIO_10_O_LEN (1U) +#define GLB_REG_GPIO_10_O_MSK (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS) +#define GLB_REG_GPIO_10_O_UMSK (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)) +#define GLB_REG_GPIO_11_O GLB_REG_GPIO_11_O +#define GLB_REG_GPIO_11_O_POS (11U) +#define GLB_REG_GPIO_11_O_LEN (1U) +#define GLB_REG_GPIO_11_O_MSK (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS) +#define GLB_REG_GPIO_11_O_UMSK (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)) +#define GLB_REG_GPIO_12_O GLB_REG_GPIO_12_O +#define GLB_REG_GPIO_12_O_POS (12U) +#define GLB_REG_GPIO_12_O_LEN (1U) +#define GLB_REG_GPIO_12_O_MSK (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS) +#define GLB_REG_GPIO_12_O_UMSK (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)) +#define GLB_REG_GPIO_13_O GLB_REG_GPIO_13_O +#define GLB_REG_GPIO_13_O_POS (13U) +#define GLB_REG_GPIO_13_O_LEN (1U) +#define GLB_REG_GPIO_13_O_MSK (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS) +#define GLB_REG_GPIO_13_O_UMSK (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)) +#define GLB_REG_GPIO_14_O GLB_REG_GPIO_14_O +#define GLB_REG_GPIO_14_O_POS (14U) +#define GLB_REG_GPIO_14_O_LEN (1U) +#define GLB_REG_GPIO_14_O_MSK (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS) +#define GLB_REG_GPIO_14_O_UMSK (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)) +#define GLB_REG_GPIO_15_O GLB_REG_GPIO_15_O +#define GLB_REG_GPIO_15_O_POS (15U) +#define GLB_REG_GPIO_15_O_LEN (1U) +#define GLB_REG_GPIO_15_O_MSK (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS) +#define GLB_REG_GPIO_15_O_UMSK (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)) +#define GLB_REG_GPIO_16_O GLB_REG_GPIO_16_O +#define GLB_REG_GPIO_16_O_POS (16U) +#define GLB_REG_GPIO_16_O_LEN (1U) +#define GLB_REG_GPIO_16_O_MSK (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS) +#define GLB_REG_GPIO_16_O_UMSK (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)) +#define GLB_REG_GPIO_17_O GLB_REG_GPIO_17_O +#define GLB_REG_GPIO_17_O_POS (17U) +#define GLB_REG_GPIO_17_O_LEN (1U) +#define GLB_REG_GPIO_17_O_MSK (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS) +#define GLB_REG_GPIO_17_O_UMSK (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)) +#define GLB_REG_GPIO_18_O GLB_REG_GPIO_18_O +#define GLB_REG_GPIO_18_O_POS (18U) +#define GLB_REG_GPIO_18_O_LEN (1U) +#define GLB_REG_GPIO_18_O_MSK (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS) +#define GLB_REG_GPIO_18_O_UMSK (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)) +#define GLB_REG_GPIO_19_O GLB_REG_GPIO_19_O +#define GLB_REG_GPIO_19_O_POS (19U) +#define GLB_REG_GPIO_19_O_LEN (1U) +#define GLB_REG_GPIO_19_O_MSK (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS) +#define GLB_REG_GPIO_19_O_UMSK (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)) +#define GLB_REG_GPIO_20_O GLB_REG_GPIO_20_O +#define GLB_REG_GPIO_20_O_POS (20U) +#define GLB_REG_GPIO_20_O_LEN (1U) +#define GLB_REG_GPIO_20_O_MSK (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS) +#define GLB_REG_GPIO_20_O_UMSK (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)) +#define GLB_REG_GPIO_21_O GLB_REG_GPIO_21_O +#define GLB_REG_GPIO_21_O_POS (21U) +#define GLB_REG_GPIO_21_O_LEN (1U) +#define GLB_REG_GPIO_21_O_MSK (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS) +#define GLB_REG_GPIO_21_O_UMSK (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)) +#define GLB_REG_GPIO_22_O GLB_REG_GPIO_22_O +#define GLB_REG_GPIO_22_O_POS (22U) +#define GLB_REG_GPIO_22_O_LEN (1U) +#define GLB_REG_GPIO_22_O_MSK (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS) +#define GLB_REG_GPIO_22_O_UMSK (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)) + +/* 0x18C : GPIO_CFGCTL33 */ +#define GLB_GPIO_CFGCTL33_OFFSET (0x18C) + +/* 0x190 : GPIO_CFGCTL34 */ +#define GLB_GPIO_CFGCTL34_OFFSET (0x190) +#define GLB_REG_GPIO_0_OE GLB_REG_GPIO_0_OE +#define GLB_REG_GPIO_0_OE_POS (0U) +#define GLB_REG_GPIO_0_OE_LEN (1U) +#define GLB_REG_GPIO_0_OE_MSK (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS) +#define GLB_REG_GPIO_0_OE_UMSK (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)) +#define GLB_REG_GPIO_1_OE GLB_REG_GPIO_1_OE +#define GLB_REG_GPIO_1_OE_POS (1U) +#define GLB_REG_GPIO_1_OE_LEN (1U) +#define GLB_REG_GPIO_1_OE_MSK (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS) +#define GLB_REG_GPIO_1_OE_UMSK (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)) +#define GLB_REG_GPIO_2_OE GLB_REG_GPIO_2_OE +#define GLB_REG_GPIO_2_OE_POS (2U) +#define GLB_REG_GPIO_2_OE_LEN (1U) +#define GLB_REG_GPIO_2_OE_MSK (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS) +#define GLB_REG_GPIO_2_OE_UMSK (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)) +#define GLB_REG_GPIO_3_OE GLB_REG_GPIO_3_OE +#define GLB_REG_GPIO_3_OE_POS (3U) +#define GLB_REG_GPIO_3_OE_LEN (1U) +#define GLB_REG_GPIO_3_OE_MSK (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS) +#define GLB_REG_GPIO_3_OE_UMSK (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)) +#define GLB_REG_GPIO_4_OE GLB_REG_GPIO_4_OE +#define GLB_REG_GPIO_4_OE_POS (4U) +#define GLB_REG_GPIO_4_OE_LEN (1U) +#define GLB_REG_GPIO_4_OE_MSK (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS) +#define GLB_REG_GPIO_4_OE_UMSK (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)) +#define GLB_REG_GPIO_5_OE GLB_REG_GPIO_5_OE +#define GLB_REG_GPIO_5_OE_POS (5U) +#define GLB_REG_GPIO_5_OE_LEN (1U) +#define GLB_REG_GPIO_5_OE_MSK (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS) +#define GLB_REG_GPIO_5_OE_UMSK (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)) +#define GLB_REG_GPIO_6_OE GLB_REG_GPIO_6_OE +#define GLB_REG_GPIO_6_OE_POS (6U) +#define GLB_REG_GPIO_6_OE_LEN (1U) +#define GLB_REG_GPIO_6_OE_MSK (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS) +#define GLB_REG_GPIO_6_OE_UMSK (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)) +#define GLB_REG_GPIO_7_OE GLB_REG_GPIO_7_OE +#define GLB_REG_GPIO_7_OE_POS (7U) +#define GLB_REG_GPIO_7_OE_LEN (1U) +#define GLB_REG_GPIO_7_OE_MSK (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS) +#define GLB_REG_GPIO_7_OE_UMSK (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)) +#define GLB_REG_GPIO_8_OE GLB_REG_GPIO_8_OE +#define GLB_REG_GPIO_8_OE_POS (8U) +#define GLB_REG_GPIO_8_OE_LEN (1U) +#define GLB_REG_GPIO_8_OE_MSK (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS) +#define GLB_REG_GPIO_8_OE_UMSK (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)) +#define GLB_REG_GPIO_9_OE GLB_REG_GPIO_9_OE +#define GLB_REG_GPIO_9_OE_POS (9U) +#define GLB_REG_GPIO_9_OE_LEN (1U) +#define GLB_REG_GPIO_9_OE_MSK (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS) +#define GLB_REG_GPIO_9_OE_UMSK (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)) +#define GLB_REG_GPIO_10_OE GLB_REG_GPIO_10_OE +#define GLB_REG_GPIO_10_OE_POS (10U) +#define GLB_REG_GPIO_10_OE_LEN (1U) +#define GLB_REG_GPIO_10_OE_MSK (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS) +#define GLB_REG_GPIO_10_OE_UMSK (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)) +#define GLB_REG_GPIO_11_OE GLB_REG_GPIO_11_OE +#define GLB_REG_GPIO_11_OE_POS (11U) +#define GLB_REG_GPIO_11_OE_LEN (1U) +#define GLB_REG_GPIO_11_OE_MSK (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS) +#define GLB_REG_GPIO_11_OE_UMSK (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)) +#define GLB_REG_GPIO_12_OE GLB_REG_GPIO_12_OE +#define GLB_REG_GPIO_12_OE_POS (12U) +#define GLB_REG_GPIO_12_OE_LEN (1U) +#define GLB_REG_GPIO_12_OE_MSK (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS) +#define GLB_REG_GPIO_12_OE_UMSK (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)) +#define GLB_REG_GPIO_13_OE GLB_REG_GPIO_13_OE +#define GLB_REG_GPIO_13_OE_POS (13U) +#define GLB_REG_GPIO_13_OE_LEN (1U) +#define GLB_REG_GPIO_13_OE_MSK (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS) +#define GLB_REG_GPIO_13_OE_UMSK (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)) +#define GLB_REG_GPIO_14_OE GLB_REG_GPIO_14_OE +#define GLB_REG_GPIO_14_OE_POS (14U) +#define GLB_REG_GPIO_14_OE_LEN (1U) +#define GLB_REG_GPIO_14_OE_MSK (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS) +#define GLB_REG_GPIO_14_OE_UMSK (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)) +#define GLB_REG_GPIO_15_OE GLB_REG_GPIO_15_OE +#define GLB_REG_GPIO_15_OE_POS (15U) +#define GLB_REG_GPIO_15_OE_LEN (1U) +#define GLB_REG_GPIO_15_OE_MSK (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS) +#define GLB_REG_GPIO_15_OE_UMSK (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)) +#define GLB_REG_GPIO_16_OE GLB_REG_GPIO_16_OE +#define GLB_REG_GPIO_16_OE_POS (16U) +#define GLB_REG_GPIO_16_OE_LEN (1U) +#define GLB_REG_GPIO_16_OE_MSK (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS) +#define GLB_REG_GPIO_16_OE_UMSK (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)) +#define GLB_REG_GPIO_17_OE GLB_REG_GPIO_17_OE +#define GLB_REG_GPIO_17_OE_POS (17U) +#define GLB_REG_GPIO_17_OE_LEN (1U) +#define GLB_REG_GPIO_17_OE_MSK (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS) +#define GLB_REG_GPIO_17_OE_UMSK (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)) +#define GLB_REG_GPIO_18_OE GLB_REG_GPIO_18_OE +#define GLB_REG_GPIO_18_OE_POS (18U) +#define GLB_REG_GPIO_18_OE_LEN (1U) +#define GLB_REG_GPIO_18_OE_MSK (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS) +#define GLB_REG_GPIO_18_OE_UMSK (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)) +#define GLB_REG_GPIO_19_OE GLB_REG_GPIO_19_OE +#define GLB_REG_GPIO_19_OE_POS (19U) +#define GLB_REG_GPIO_19_OE_LEN (1U) +#define GLB_REG_GPIO_19_OE_MSK (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS) +#define GLB_REG_GPIO_19_OE_UMSK (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)) +#define GLB_REG_GPIO_20_OE GLB_REG_GPIO_20_OE +#define GLB_REG_GPIO_20_OE_POS (20U) +#define GLB_REG_GPIO_20_OE_LEN (1U) +#define GLB_REG_GPIO_20_OE_MSK (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS) +#define GLB_REG_GPIO_20_OE_UMSK (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)) +#define GLB_REG_GPIO_21_OE GLB_REG_GPIO_21_OE +#define GLB_REG_GPIO_21_OE_POS (21U) +#define GLB_REG_GPIO_21_OE_LEN (1U) +#define GLB_REG_GPIO_21_OE_MSK (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS) +#define GLB_REG_GPIO_21_OE_UMSK (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)) +#define GLB_REG_GPIO_22_OE GLB_REG_GPIO_22_OE +#define GLB_REG_GPIO_22_OE_POS (22U) +#define GLB_REG_GPIO_22_OE_LEN (1U) +#define GLB_REG_GPIO_22_OE_MSK (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS) +#define GLB_REG_GPIO_22_OE_UMSK (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)) + +/* 0x194 : GPIO_CFGCTL35 */ +#define GLB_GPIO_CFGCTL35_OFFSET (0x194) + +/* 0x1A0 : GPIO_INT_MASK1 */ +#define GLB_GPIO_INT_MASK1_OFFSET (0x1A0) +#define GLB_REG_GPIO_INT_MASK1 GLB_REG_GPIO_INT_MASK1 +#define GLB_REG_GPIO_INT_MASK1_POS (0U) +#define GLB_REG_GPIO_INT_MASK1_LEN (32U) +#define GLB_REG_GPIO_INT_MASK1_MSK (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS) +#define GLB_REG_GPIO_INT_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)) + +/* 0x1A8 : GPIO_INT_STAT1 */ +#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8) +#define GLB_GPIO_INT_STAT1 GLB_GPIO_INT_STAT1 +#define GLB_GPIO_INT_STAT1_POS (0U) +#define GLB_GPIO_INT_STAT1_LEN (32U) +#define GLB_GPIO_INT_STAT1_MSK (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS) +#define GLB_GPIO_INT_STAT1_UMSK (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)) + +/* 0x1B0 : GPIO_INT_CLR1 */ +#define GLB_GPIO_INT_CLR1_OFFSET (0x1B0) +#define GLB_REG_GPIO_INT_CLR1 GLB_REG_GPIO_INT_CLR1 +#define GLB_REG_GPIO_INT_CLR1_POS (0U) +#define GLB_REG_GPIO_INT_CLR1_LEN (32U) +#define GLB_REG_GPIO_INT_CLR1_MSK (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS) +#define GLB_REG_GPIO_INT_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)) + +/* 0x1C0 : GPIO_INT_MODE_SET1 */ +#define GLB_GPIO_INT_MODE_SET1_OFFSET (0x1C0) +#define GLB_REG_GPIO_INT_MODE_SET1 GLB_REG_GPIO_INT_MODE_SET1 +#define GLB_REG_GPIO_INT_MODE_SET1_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET1_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET1_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS) +#define GLB_REG_GPIO_INT_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS)) + +/* 0x1C4 : GPIO_INT_MODE_SET2 */ +#define GLB_GPIO_INT_MODE_SET2_OFFSET (0x1C4) +#define GLB_REG_GPIO_INT_MODE_SET2 GLB_REG_GPIO_INT_MODE_SET2 +#define GLB_REG_GPIO_INT_MODE_SET2_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET2_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET2_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS) +#define GLB_REG_GPIO_INT_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS)) + +/* 0x1C8 : GPIO_INT_MODE_SET3 */ +#define GLB_GPIO_INT_MODE_SET3_OFFSET (0x1C8) +#define GLB_REG_GPIO_INT_MODE_SET3 GLB_REG_GPIO_INT_MODE_SET3 +#define GLB_REG_GPIO_INT_MODE_SET3_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET3_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET3_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS) +#define GLB_REG_GPIO_INT_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS)) + +/* 0x224 : led_driver */ +#define GLB_LED_DRIVER_OFFSET (0x224) +#define GLB_LED_DIN_REG GLB_LED_DIN_REG +#define GLB_LED_DIN_REG_POS (0U) +#define GLB_LED_DIN_REG_LEN (1U) +#define GLB_LED_DIN_REG_MSK (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS) +#define GLB_LED_DIN_REG_UMSK (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)) +#define GLB_LED_DIN_SEL GLB_LED_DIN_SEL +#define GLB_LED_DIN_SEL_POS (1U) +#define GLB_LED_DIN_SEL_LEN (1U) +#define GLB_LED_DIN_SEL_MSK (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS) +#define GLB_LED_DIN_SEL_UMSK (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)) +#define GLB_LED_DIN_POLARITY_SEL GLB_LED_DIN_POLARITY_SEL +#define GLB_LED_DIN_POLARITY_SEL_POS (2U) +#define GLB_LED_DIN_POLARITY_SEL_LEN (1U) +#define GLB_LED_DIN_POLARITY_SEL_MSK (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS) +#define GLB_LED_DIN_POLARITY_SEL_UMSK (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)) +#define GLB_LEDDRV_IBIAS GLB_LEDDRV_IBIAS +#define GLB_LEDDRV_IBIAS_POS (4U) +#define GLB_LEDDRV_IBIAS_LEN (4U) +#define GLB_LEDDRV_IBIAS_MSK (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS) +#define GLB_LEDDRV_IBIAS_UMSK (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)) +#define GLB_IR_RX_GPIO_SEL GLB_IR_RX_GPIO_SEL +#define GLB_IR_RX_GPIO_SEL_POS (8U) +#define GLB_IR_RX_GPIO_SEL_LEN (2U) +#define GLB_IR_RX_GPIO_SEL_MSK (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS) +#define GLB_IR_RX_GPIO_SEL_UMSK (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)) +#define GLB_PU_LEDDRV GLB_PU_LEDDRV +#define GLB_PU_LEDDRV_POS (31U) +#define GLB_PU_LEDDRV_LEN (1U) +#define GLB_PU_LEDDRV_MSK (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS) +#define GLB_PU_LEDDRV_UMSK (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)) + +/* 0x308 : gpdac_ctrl */ +#define GLB_GPDAC_CTRL_OFFSET (0x308) +#define GLB_GPDACA_RSTN_ANA GLB_GPDACA_RSTN_ANA +#define GLB_GPDACA_RSTN_ANA_POS (0U) +#define GLB_GPDACA_RSTN_ANA_LEN (1U) +#define GLB_GPDACA_RSTN_ANA_MSK (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS) +#define GLB_GPDACA_RSTN_ANA_UMSK (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)) +#define GLB_GPDACB_RSTN_ANA GLB_GPDACB_RSTN_ANA +#define GLB_GPDACB_RSTN_ANA_POS (1U) +#define GLB_GPDACB_RSTN_ANA_LEN (1U) +#define GLB_GPDACB_RSTN_ANA_MSK (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS) +#define GLB_GPDACB_RSTN_ANA_UMSK (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)) +#define GLB_GPDAC_TEST_EN GLB_GPDAC_TEST_EN +#define GLB_GPDAC_TEST_EN_POS (7U) +#define GLB_GPDAC_TEST_EN_LEN (1U) +#define GLB_GPDAC_TEST_EN_MSK (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS) +#define GLB_GPDAC_TEST_EN_UMSK (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)) +#define GLB_GPDAC_REF_SEL GLB_GPDAC_REF_SEL +#define GLB_GPDAC_REF_SEL_POS (8U) +#define GLB_GPDAC_REF_SEL_LEN (1U) +#define GLB_GPDAC_REF_SEL_MSK (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS) +#define GLB_GPDAC_REF_SEL_UMSK (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)) +#define GLB_GPDAC_TEST_SEL GLB_GPDAC_TEST_SEL +#define GLB_GPDAC_TEST_SEL_POS (9U) +#define GLB_GPDAC_TEST_SEL_LEN (3U) +#define GLB_GPDAC_TEST_SEL_MSK (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS) +#define GLB_GPDAC_TEST_SEL_UMSK (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)) +#define GLB_GPDAC_RESERVED GLB_GPDAC_RESERVED +#define GLB_GPDAC_RESERVED_POS (24U) +#define GLB_GPDAC_RESERVED_LEN (8U) +#define GLB_GPDAC_RESERVED_MSK (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS) +#define GLB_GPDAC_RESERVED_UMSK (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)) + +/* 0x30C : gpdac_actrl */ +#define GLB_GPDAC_ACTRL_OFFSET (0x30C) +#define GLB_GPDAC_A_EN GLB_GPDAC_A_EN +#define GLB_GPDAC_A_EN_POS (0U) +#define GLB_GPDAC_A_EN_LEN (1U) +#define GLB_GPDAC_A_EN_MSK (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS) +#define GLB_GPDAC_A_EN_UMSK (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)) +#define GLB_GPDAC_IOA_EN GLB_GPDAC_IOA_EN +#define GLB_GPDAC_IOA_EN_POS (1U) +#define GLB_GPDAC_IOA_EN_LEN (1U) +#define GLB_GPDAC_IOA_EN_MSK (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS) +#define GLB_GPDAC_IOA_EN_UMSK (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)) +#define GLB_GPDAC_A_RNG GLB_GPDAC_A_RNG +#define GLB_GPDAC_A_RNG_POS (18U) +#define GLB_GPDAC_A_RNG_LEN (2U) +#define GLB_GPDAC_A_RNG_MSK (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS) +#define GLB_GPDAC_A_RNG_UMSK (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)) +#define GLB_GPDAC_A_OUTMUX GLB_GPDAC_A_OUTMUX +#define GLB_GPDAC_A_OUTMUX_POS (20U) +#define GLB_GPDAC_A_OUTMUX_LEN (3U) +#define GLB_GPDAC_A_OUTMUX_MSK (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS) +#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)) + +/* 0x310 : gpdac_bctrl */ +#define GLB_GPDAC_BCTRL_OFFSET (0x310) +#define GLB_GPDAC_B_EN GLB_GPDAC_B_EN +#define GLB_GPDAC_B_EN_POS (0U) +#define GLB_GPDAC_B_EN_LEN (1U) +#define GLB_GPDAC_B_EN_MSK (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS) +#define GLB_GPDAC_B_EN_UMSK (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)) +#define GLB_GPDAC_IOB_EN GLB_GPDAC_IOB_EN +#define GLB_GPDAC_IOB_EN_POS (1U) +#define GLB_GPDAC_IOB_EN_LEN (1U) +#define GLB_GPDAC_IOB_EN_MSK (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS) +#define GLB_GPDAC_IOB_EN_UMSK (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)) +#define GLB_GPDAC_B_RNG GLB_GPDAC_B_RNG +#define GLB_GPDAC_B_RNG_POS (18U) +#define GLB_GPDAC_B_RNG_LEN (2U) +#define GLB_GPDAC_B_RNG_MSK (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS) +#define GLB_GPDAC_B_RNG_UMSK (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)) +#define GLB_GPDAC_B_OUTMUX GLB_GPDAC_B_OUTMUX +#define GLB_GPDAC_B_OUTMUX_POS (20U) +#define GLB_GPDAC_B_OUTMUX_LEN (3U) +#define GLB_GPDAC_B_OUTMUX_MSK (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS) +#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)) + +/* 0x314 : gpdac_data */ +#define GLB_GPDAC_DATA_OFFSET (0x314) +#define GLB_GPDAC_B_DATA GLB_GPDAC_B_DATA +#define GLB_GPDAC_B_DATA_POS (0U) +#define GLB_GPDAC_B_DATA_LEN (10U) +#define GLB_GPDAC_B_DATA_MSK (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS) +#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)) +#define GLB_GPDAC_A_DATA GLB_GPDAC_A_DATA +#define GLB_GPDAC_A_DATA_POS (16U) +#define GLB_GPDAC_A_DATA_LEN (10U) +#define GLB_GPDAC_A_DATA_MSK (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS) +#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)) + +/* 0xF00 : tzc_glb_ctrl_0 */ +#define GLB_TZC_GLB_CTRL_0_OFFSET (0xF00) +#define GLB_TZC_GLB_SWRST_S00_LOCK GLB_TZC_GLB_SWRST_S00_LOCK +#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0U) +#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S01_LOCK GLB_TZC_GLB_SWRST_S01_LOCK +#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1U) +#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S30_LOCK GLB_TZC_GLB_SWRST_S30_LOCK +#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8U) +#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK GLB_TZC_GLB_CTRL_PWRON_RST_LOCK +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12U) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK GLB_TZC_GLB_CTRL_CPU_RESET_LOCK +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13U) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK GLB_TZC_GLB_CTRL_SYS_RESET_LOCK +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14U) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15U) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)) +#define GLB_TZC_GLB_MISC_LOCK GLB_TZC_GLB_MISC_LOCK +#define GLB_TZC_GLB_MISC_LOCK_POS (25U) +#define GLB_TZC_GLB_MISC_LOCK_LEN (1U) +#define GLB_TZC_GLB_MISC_LOCK_MSK (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS) +#define GLB_TZC_GLB_MISC_LOCK_UMSK (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)) +#define GLB_TZC_GLB_SRAM_LOCK GLB_TZC_GLB_SRAM_LOCK +#define GLB_TZC_GLB_SRAM_LOCK_POS (26U) +#define GLB_TZC_GLB_SRAM_LOCK_LEN (1U) +#define GLB_TZC_GLB_SRAM_LOCK_MSK (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS) +#define GLB_TZC_GLB_SRAM_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)) +#define GLB_TZC_GLB_L2C_LOCK GLB_TZC_GLB_L2C_LOCK +#define GLB_TZC_GLB_L2C_LOCK_POS (27U) +#define GLB_TZC_GLB_L2C_LOCK_LEN (1U) +#define GLB_TZC_GLB_L2C_LOCK_MSK (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS) +#define GLB_TZC_GLB_L2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)) +#define GLB_TZC_GLB_BMX_LOCK GLB_TZC_GLB_BMX_LOCK +#define GLB_TZC_GLB_BMX_LOCK_POS (28U) +#define GLB_TZC_GLB_BMX_LOCK_LEN (1U) +#define GLB_TZC_GLB_BMX_LOCK_MSK (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS) +#define GLB_TZC_GLB_BMX_LOCK_UMSK (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)) +#define GLB_TZC_GLB_DBG_LOCK GLB_TZC_GLB_DBG_LOCK +#define GLB_TZC_GLB_DBG_LOCK_POS (29U) +#define GLB_TZC_GLB_DBG_LOCK_LEN (1U) +#define GLB_TZC_GLB_DBG_LOCK_MSK (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS) +#define GLB_TZC_GLB_DBG_LOCK_UMSK (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)) +#define GLB_TZC_GLB_MBIST_LOCK GLB_TZC_GLB_MBIST_LOCK +#define GLB_TZC_GLB_MBIST_LOCK_POS (30U) +#define GLB_TZC_GLB_MBIST_LOCK_LEN (1U) +#define GLB_TZC_GLB_MBIST_LOCK_MSK (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS) +#define GLB_TZC_GLB_MBIST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)) +#define GLB_TZC_GLB_CLK_LOCK GLB_TZC_GLB_CLK_LOCK +#define GLB_TZC_GLB_CLK_LOCK_POS (31U) +#define GLB_TZC_GLB_CLK_LOCK_LEN (1U) +#define GLB_TZC_GLB_CLK_LOCK_MSK (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS) +#define GLB_TZC_GLB_CLK_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)) + +/* 0xF04 : tzc_glb_ctrl_1 */ +#define GLB_TZC_GLB_CTRL_1_OFFSET (0xF04) +#define GLB_TZC_GLB_SWRST_S20_LOCK GLB_TZC_GLB_SWRST_S20_LOCK +#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0U) +#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S21_LOCK GLB_TZC_GLB_SWRST_S21_LOCK +#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1U) +#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S22_LOCK GLB_TZC_GLB_SWRST_S22_LOCK +#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2U) +#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S23_LOCK GLB_TZC_GLB_SWRST_S23_LOCK +#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3U) +#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S24_LOCK GLB_TZC_GLB_SWRST_S24_LOCK +#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4U) +#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S25_LOCK GLB_TZC_GLB_SWRST_S25_LOCK +#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5U) +#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S26_LOCK GLB_TZC_GLB_SWRST_S26_LOCK +#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6U) +#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S27_LOCK GLB_TZC_GLB_SWRST_S27_LOCK +#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7U) +#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S28_LOCK GLB_TZC_GLB_SWRST_S28_LOCK +#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8U) +#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S29_LOCK GLB_TZC_GLB_SWRST_S29_LOCK +#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9U) +#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2A_LOCK GLB_TZC_GLB_SWRST_S2A_LOCK +#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10U) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2B_LOCK GLB_TZC_GLB_SWRST_S2B_LOCK +#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11U) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2C_LOCK GLB_TZC_GLB_SWRST_S2C_LOCK +#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12U) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2D_LOCK GLB_TZC_GLB_SWRST_S2D_LOCK +#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13U) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2E_LOCK GLB_TZC_GLB_SWRST_S2E_LOCK +#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14U) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2F_LOCK GLB_TZC_GLB_SWRST_S2F_LOCK +#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15U) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S10_LOCK GLB_TZC_GLB_SWRST_S10_LOCK +#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16U) +#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S11_LOCK GLB_TZC_GLB_SWRST_S11_LOCK +#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17U) +#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S12_LOCK GLB_TZC_GLB_SWRST_S12_LOCK +#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18U) +#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S13_LOCK GLB_TZC_GLB_SWRST_S13_LOCK +#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19U) +#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S14_LOCK GLB_TZC_GLB_SWRST_S14_LOCK +#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20U) +#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S15_LOCK GLB_TZC_GLB_SWRST_S15_LOCK +#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21U) +#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S16_LOCK GLB_TZC_GLB_SWRST_S16_LOCK +#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22U) +#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S17_LOCK GLB_TZC_GLB_SWRST_S17_LOCK +#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23U) +#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S18_LOCK GLB_TZC_GLB_SWRST_S18_LOCK +#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24U) +#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S19_LOCK GLB_TZC_GLB_SWRST_S19_LOCK +#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25U) +#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1A_LOCK GLB_TZC_GLB_SWRST_S1A_LOCK +#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26U) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1B_LOCK GLB_TZC_GLB_SWRST_S1B_LOCK +#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27U) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1C_LOCK GLB_TZC_GLB_SWRST_S1C_LOCK +#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28U) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1D_LOCK GLB_TZC_GLB_SWRST_S1D_LOCK +#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29U) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1E_LOCK GLB_TZC_GLB_SWRST_S1E_LOCK +#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30U) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1F_LOCK GLB_TZC_GLB_SWRST_S1F_LOCK +#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31U) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)) + +/* 0xF08 : tzc_glb_ctrl_2 */ +#define GLB_TZC_GLB_CTRL_2_OFFSET (0xF08) +#define GLB_TZC_GLB_GPIO_0_LOCK GLB_TZC_GLB_GPIO_0_LOCK +#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0U) +#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_0_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS) +#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_1_LOCK GLB_TZC_GLB_GPIO_1_LOCK +#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1U) +#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_1_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS) +#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_2_LOCK GLB_TZC_GLB_GPIO_2_LOCK +#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2U) +#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_2_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS) +#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_3_LOCK GLB_TZC_GLB_GPIO_3_LOCK +#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3U) +#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_3_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS) +#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_4_LOCK GLB_TZC_GLB_GPIO_4_LOCK +#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4U) +#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_4_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS) +#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_5_LOCK GLB_TZC_GLB_GPIO_5_LOCK +#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5U) +#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_5_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS) +#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_6_LOCK GLB_TZC_GLB_GPIO_6_LOCK +#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6U) +#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_6_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS) +#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_7_LOCK GLB_TZC_GLB_GPIO_7_LOCK +#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7U) +#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_7_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS) +#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_8_LOCK GLB_TZC_GLB_GPIO_8_LOCK +#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8U) +#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_8_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS) +#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_9_LOCK GLB_TZC_GLB_GPIO_9_LOCK +#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9U) +#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_9_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS) +#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_10_LOCK GLB_TZC_GLB_GPIO_10_LOCK +#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10U) +#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_10_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS) +#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_11_LOCK GLB_TZC_GLB_GPIO_11_LOCK +#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11U) +#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_11_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS) +#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_12_LOCK GLB_TZC_GLB_GPIO_12_LOCK +#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12U) +#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_12_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS) +#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_13_LOCK GLB_TZC_GLB_GPIO_13_LOCK +#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13U) +#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_13_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS) +#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_14_LOCK GLB_TZC_GLB_GPIO_14_LOCK +#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14U) +#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_14_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS) +#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_15_LOCK GLB_TZC_GLB_GPIO_15_LOCK +#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15U) +#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_15_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS) +#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_16_LOCK GLB_TZC_GLB_GPIO_16_LOCK +#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16U) +#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_16_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS) +#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_17_LOCK GLB_TZC_GLB_GPIO_17_LOCK +#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17U) +#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_17_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS) +#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_18_LOCK GLB_TZC_GLB_GPIO_18_LOCK +#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18U) +#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_18_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS) +#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_19_LOCK GLB_TZC_GLB_GPIO_19_LOCK +#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19U) +#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_19_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS) +#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_20_LOCK GLB_TZC_GLB_GPIO_20_LOCK +#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20U) +#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_20_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS) +#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_21_LOCK GLB_TZC_GLB_GPIO_21_LOCK +#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21U) +#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_21_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS) +#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_22_LOCK GLB_TZC_GLB_GPIO_22_LOCK +#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22U) +#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_22_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS) +#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_23_LOCK GLB_TZC_GLB_GPIO_23_LOCK +#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23U) +#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_23_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS) +#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_24_LOCK GLB_TZC_GLB_GPIO_24_LOCK +#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24U) +#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_24_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS) +#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_25_LOCK GLB_TZC_GLB_GPIO_25_LOCK +#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25U) +#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_25_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS) +#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_26_LOCK GLB_TZC_GLB_GPIO_26_LOCK +#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26U) +#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_26_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS) +#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_27_LOCK GLB_TZC_GLB_GPIO_27_LOCK +#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27U) +#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_27_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS) +#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_28_LOCK GLB_TZC_GLB_GPIO_28_LOCK +#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28U) +#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_28_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS) +#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)) + +/* 0xF0C : tzc_glb_ctrl_3 */ +#define GLB_TZC_GLB_CTRL_3_OFFSET (0xF0C) + +struct glb_reg { + /* 0x0 : clk_cfg0 */ + union { + struct + { + uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_fclk_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_hclk_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reg_bclk_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t reg_pll_sel : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t hbn_root_clk_sel : 2; /* [ 7: 6], r, 0x0 */ + uint32_t reg_hclk_div : 8; /* [15: 8], r/w, 0x0 */ + uint32_t reg_bclk_div : 8; /* [23:16], r/w, 0x0 */ + uint32_t fclk_sw_state : 3; /* [26:24], r, 0x0 */ + uint32_t chip_rdy : 1; /* [ 27], r, 0x0 */ + uint32_t glb_id : 4; /* [31:28], r, 0x6 */ + } BF; + uint32_t WORD; + } clk_cfg0; + + /* 0x4 : clk_cfg1 */ + union { + struct + { + uint32_t wifi_mac_core_div : 4; /* [ 3: 0], r/w, 0x1 */ + uint32_t wifi_mac_wt_div : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ + uint32_t ble_clk_sel : 6; /* [21:16], r/w, 0x10 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t ble_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clk_cfg1; + + /* 0x8 : clk_cfg2 */ + union { + struct + { + uint32_t uart_clk_div : 3; /* [ 2: 0], r/w, 0x7 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t uart_clk_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ + uint32_t hbn_uart_clk_sel : 1; /* [ 7], r, 0x0 */ + uint32_t sf_clk_div : 3; /* [10: 8], r/w, 0x3 */ + uint32_t sf_clk_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t sf_clk_sel : 2; /* [13:12], r/w, 0x2 */ + uint32_t sf_clk_sel2 : 2; /* [15:14], r/w, 0x0 */ + uint32_t ir_clk_div : 6; /* [21:16], r/w, 0xf */ + uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ + uint32_t ir_clk_en : 1; /* [ 23], r/w, 0x1 */ + uint32_t dma_clk_en : 8; /* [31:24], r/w, 0xff */ + } BF; + uint32_t WORD; + } clk_cfg2; + + /* 0xC : clk_cfg3 */ + union { + struct + { + uint32_t spi_clk_div : 5; /* [ 4: 0], r/w, 0x3 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t spi_clk_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ + uint32_t i2c_clk_div : 8; /* [23:16], r/w, 0xff */ + uint32_t i2c_clk_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clk_cfg3; + + /* 0x10 : swrst_cfg0 */ + union { + struct + { + uint32_t swrst_s00 : 1; /* [ 0], r/w, 0x0 */ + uint32_t swrst_s01 : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t swrst_s20 : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t swrst_s30 : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg0; + + /* 0x14 : swrst_cfg1 */ + union { + struct + { + uint32_t swrst_s10 : 1; /* [ 0], r/w, 0x0 */ + uint32_t swrst_s11 : 1; /* [ 1], r/w, 0x0 */ + uint32_t swrst_s12 : 1; /* [ 2], r/w, 0x0 */ + uint32_t swrst_s13 : 1; /* [ 3], r/w, 0x0 */ + uint32_t swrst_s14 : 1; /* [ 4], r/w, 0x0 */ + uint32_t swrst_s15 : 1; /* [ 5], r/w, 0x0 */ + uint32_t swrst_s16 : 1; /* [ 6], r/w, 0x0 */ + uint32_t swrst_s17 : 1; /* [ 7], r/w, 0x0 */ + uint32_t swrst_s18 : 1; /* [ 8], r/w, 0x0 */ + uint32_t swrst_s19 : 1; /* [ 9], r/w, 0x0 */ + uint32_t swrst_s1a : 1; /* [ 10], r/w, 0x0 */ + uint32_t swrst_s1b : 1; /* [ 11], r/w, 0x0 */ + uint32_t swrst_s1c : 1; /* [ 12], r/w, 0x0 */ + uint32_t swrst_s1d : 1; /* [ 13], r/w, 0x0 */ + uint32_t swrst_s1e : 1; /* [ 14], r/w, 0x0 */ + uint32_t swrst_s1f : 1; /* [ 15], r/w, 0x0 */ + uint32_t swrst_s1a0 : 1; /* [ 16], r/w, 0x0 */ + uint32_t swrst_s1a1 : 1; /* [ 17], r/w, 0x0 */ + uint32_t swrst_s1a2 : 1; /* [ 18], r/w, 0x0 */ + uint32_t swrst_s1a3 : 1; /* [ 19], r/w, 0x0 */ + uint32_t swrst_s1a4 : 1; /* [ 20], r/w, 0x0 */ + uint32_t swrst_s1a5 : 1; /* [ 21], r/w, 0x0 */ + uint32_t swrst_s1a6 : 1; /* [ 22], r/w, 0x0 */ + uint32_t swrst_s1a7 : 1; /* [ 23], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg1; + + /* 0x18 : swrst_cfg2 */ + union { + struct + { + uint32_t reg_ctrl_pwron_rst : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_ctrl_cpu_reset : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_ctrl_sys_reset : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t reg_ctrl_reset_dummy : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t reserved_8_23 : 16; /* [23: 8], rsvd, 0x0 */ + uint32_t pka_clk_sel : 1; /* [ 24], r/w, 0x0 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg2; + + /* 0x1C : swrst_cfg3 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg3; + + /* 0x20 : cgen_cfg0 */ + union { + struct + { + uint32_t cgen_m : 8; /* [ 7: 0], r/w, 0xff */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg0; + + /* 0x24 : cgen_cfg1 */ + union { + struct + { + uint32_t cgen_s1 : 16; /* [15: 0], r/w, 0xffff */ + uint32_t cgen_s1a : 8; /* [23:16], r/w, 0xff */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg1; + + /* 0x28 : cgen_cfg2 */ + union { + struct + { + uint32_t cgen_s2 : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t cgen_s3 : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg2; + + /* 0x2C : cgen_cfg3 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg3; + + /* 0x30 : MBIST_CTL */ + union { + struct + { + uint32_t irom_mbist_mode : 1; /* [ 0], r/w, 0x0 */ + uint32_t hsram_mbist_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t tag_mbist_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t ocram_mbist_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t wifi_mbist_mode : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_30 : 26; /* [30: 5], rsvd, 0x0 */ + uint32_t reg_mbist_rst_n : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } MBIST_CTL; + + /* 0x34 : MBIST_STAT */ + union { + struct + { + uint32_t irom_mbist_done : 1; /* [ 0], r, 0x0 */ + uint32_t hsram_mbist_done : 1; /* [ 1], r, 0x0 */ + uint32_t tag_mbist_done : 1; /* [ 2], r, 0x0 */ + uint32_t ocram_mbist_done : 1; /* [ 3], r, 0x0 */ + uint32_t wifi_mbist_done : 1; /* [ 4], r, 0x0 */ + uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ + uint32_t irom_mbist_fail : 1; /* [ 16], r, 0x0 */ + uint32_t hsram_mbist_fail : 1; /* [ 17], r, 0x0 */ + uint32_t tag_mbist_fail : 1; /* [ 18], r, 0x0 */ + uint32_t ocram_mbist_fail : 1; /* [ 19], r, 0x0 */ + uint32_t wifi_mbist_fail : 1; /* [ 20], r, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MBIST_STAT; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[24]; + + /* 0x50 : bmx_cfg1 */ + union { + struct + { + uint32_t bmx_timeout_en : 4; /* [ 3: 0], r/w, 0x0 */ + uint32_t bmx_arb_mode : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t bmx_err_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t bmx_busy_option_dis : 1; /* [ 9], r/w, 0x0 */ + uint32_t bmx_gating_dis : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t hsel_option : 4; /* [15:12], r/w, 0x0 */ + uint32_t pds_apb_cfg : 8; /* [23:16], r/w, 0x0 */ + uint32_t hbn_apb_cfg : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } bmx_cfg1; + + /* 0x54 : bmx_cfg2 */ + union { + struct + { + uint32_t bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t bmx_err_dec : 1; /* [ 4], r, 0x0 */ + uint32_t bmx_err_tz : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_27 : 22; /* [27: 6], rsvd, 0x0 */ + uint32_t bmx_dbg_sel : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } bmx_cfg2; + + /* 0x58 : bmx_err_addr */ + union { + struct + { + uint32_t bmx_err_addr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } bmx_err_addr; + + /* 0x5C : bmx_dbg_out */ + union { + struct + { + uint32_t bmx_dbg_out : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } bmx_dbg_out; + + /* 0x60 : rsv0 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv0; + + /* 0x64 : rsv1 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv1; + + /* 0x68 : rsv2 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv2; + + /* 0x6C : rsv3 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0xffffffffL */ + } BF; + uint32_t WORD; + } rsv3; + + /* 0x70 : sram_ret */ + union { + struct + { + uint32_t reg_sram_ret : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sram_ret; + + /* 0x74 : sram_slp */ + union { + struct + { + uint32_t reg_sram_slp : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sram_slp; + + /* 0x78 : sram_parm */ + union { + struct + { + uint32_t reg_sram_parm : 32; /* [31: 0], r/w, 0xc0c0c0c */ + } BF; + uint32_t WORD; + } sram_parm; + + /* 0x7C : seam_misc */ + union { + struct + { + uint32_t em_sel : 4; /* [ 3: 0], r/w, 0x3 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } seam_misc; + + /* 0x80 : glb_parm */ + union { + struct + { + uint32_t reg_bd_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_ext_rst_smt : 1; /* [ 1], r/w, 0x0 */ + uint32_t jtag_swap_set : 6; /* [ 7: 2], r/w, 0x0 */ + uint32_t swap_sflash_io_3_io_0 : 1; /* [ 8], r/w, 0x1 */ + uint32_t sel_embedded_sflash : 1; /* [ 9], r/w, 0x1 */ + uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ + uint32_t reg_spi_0_master_mode : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_spi_0_swap : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ + uint32_t reg_cci_use_jtag_pin : 1; /* [ 15], r/w, 0x1 */ + uint32_t reg_cci_use_sdio_pin : 1; /* [ 16], r/w, 0x1 */ + uint32_t p1_adc_test_with_cci : 1; /* [ 17], r/w, 0x0 */ + uint32_t p2_dac_test_with_cci : 1; /* [ 18], r/w, 0x0 */ + uint32_t p3_cci_use_io_2_5 : 1; /* [ 19], r/w, 0x0 */ + uint32_t p4_adc_test_with_jtag : 1; /* [ 20], r/w, 0x0 */ + uint32_t p5_dac_test_with_jtag : 1; /* [ 21], r/w, 0x0 */ + uint32_t p6_sdio_use_io_0_5 : 1; /* [ 22], r/w, 0x0 */ + uint32_t p7_jtag_use_io_2_5 : 1; /* [ 23], r/w, 0x0 */ + uint32_t uart_swap_set : 3; /* [26:24], r/w, 0x0 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } glb_parm; + + /* 0x84 reserved */ + uint8_t RESERVED0x84[12]; + + /* 0x90 : CPU_CLK_CFG */ + union { + struct + { + uint32_t cpu_rtc_div : 17; /* [16: 0], r/w, 0x10 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t cpu_rtc_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t cpu_rtc_sel : 1; /* [ 19], r/w, 0x1 */ + uint32_t debug_ndreset_gate : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } CPU_CLK_CFG; + + /* 0x94 reserved */ + uint8_t RESERVED0x94[16]; + + /* 0xA4 : GPADC_32M_SRC_CTRL */ + union { + struct + { + uint32_t gpadc_32m_clk_div : 6; /* [ 5: 0], r/w, 0x2 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t gpadc_32m_clk_sel : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpadc_32m_div_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPADC_32M_SRC_CTRL; + + /* 0xA8 : DIG32K_WAKEUP_CTRL */ + union { + struct + { + uint32_t dig_32k_div : 11; /* [10: 0], r/w, 0x3e8 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t dig_32k_en : 1; /* [ 12], r/w, 0x1 */ + uint32_t dig_32k_comp : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t dig_512k_div : 7; /* [22:16], r/w, 0x3e */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t dig_512k_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t dig_512k_comp : 1; /* [ 25], r/w, 0x1 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t dig_clk_src_sel : 1; /* [ 28], r/w, 0x0 */ + uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ + uint32_t reg_en_platform_wakeup : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DIG32K_WAKEUP_CTRL; + + /* 0xAC : WIFI_BT_COEX_CTRL */ + union { + struct + { + uint32_t coex_bt_channel : 7; /* [ 6: 0], r/w, 0x0 */ + uint32_t coex_bt_pti : 4; /* [10: 7], r/w, 0x0 */ + uint32_t coex_bt_bw : 1; /* [ 11], r/w, 0x0 */ + uint32_t en_gpio_bt_coex : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WIFI_BT_COEX_CTRL; + + /* 0xb0 reserved */ + uint8_t RESERVED0xb0[16]; + + /* 0xC0 : UART_SIG_SEL_0 */ + union { + struct + { + uint32_t uart_sig_0_sel : 4; /* [ 3: 0], r/w, 0x0 */ + uint32_t uart_sig_1_sel : 4; /* [ 7: 4], r/w, 0x1 */ + uint32_t uart_sig_2_sel : 4; /* [11: 8], r/w, 0x2 */ + uint32_t uart_sig_3_sel : 4; /* [15:12], r/w, 0x3 */ + uint32_t uart_sig_4_sel : 4; /* [19:16], r/w, 0x4 */ + uint32_t uart_sig_5_sel : 4; /* [23:20], r/w, 0x5 */ + uint32_t uart_sig_6_sel : 4; /* [27:24], r/w, 0x6 */ + uint32_t uart_sig_7_sel : 4; /* [31:28], r/w, 0x7 */ + } BF; + uint32_t WORD; + } UART_SIG_SEL_0; + + /* 0xc4 reserved */ + uint8_t RESERVED0xc4[12]; + + /* 0xD0 : DBG_SEL_LL */ + union { + struct + { + uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_LL; + + /* 0xD4 : DBG_SEL_LH */ + union { + struct + { + uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_LH; + + /* 0xD8 : DBG_SEL_HL */ + union { + struct + { + uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_HL; + + /* 0xDC : DBG_SEL_HH */ + union { + struct + { + uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_HH; + + /* 0xE0 : debug */ + union { + struct + { + uint32_t debug_oe : 1; /* [ 0], r/w, 0x0 */ + uint32_t debug_i : 31; /* [31: 1], r, 0x0 */ + } BF; + uint32_t WORD; + } debug; + + /* 0xe4 reserved */ + uint8_t RESERVED0xe4[28]; + + /* 0x100 : GPIO_CFGCTL0 */ + union { + struct + { + uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_0_func_sel : 4; /* [11: 8], r/w, 0x1 */ + uint32_t real_gpio_0_func_sel : 4; /* [15:12], r, 0x1 */ + uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_1_func_sel : 4; /* [27:24], r/w, 0x1 */ + uint32_t real_gpio_1_func_sel : 4; /* [31:28], r, 0x1 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL0; + + /* 0x104 : GPIO_CFGCTL1 */ + union { + struct + { + uint32_t reg_gpio_2_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_2_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_2_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_2_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_2_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_2_func_sel : 4; /* [11: 8], r/w, 0x1 */ + uint32_t real_gpio_2_func_sel : 4; /* [15:12], r, 0x1 */ + uint32_t reg_gpio_3_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_3_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_3_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_3_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_3_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_3_func_sel : 4; /* [27:24], r/w, 0x1 */ + uint32_t real_gpio_3_func_sel : 4; /* [31:28], r, 0x1 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL1; + + /* 0x108 : GPIO_CFGCTL2 */ + union { + struct + { + uint32_t reg_gpio_4_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_4_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_4_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_4_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_4_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_4_func_sel : 4; /* [11: 8], r/w, 0x1 */ + uint32_t real_gpio_4_func_sel : 4; /* [15:12], r, 0x1 */ + uint32_t reg_gpio_5_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_5_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_5_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_5_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_5_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_5_func_sel : 4; /* [27:24], r/w, 0x1 */ + uint32_t real_gpio_5_func_sel : 4; /* [31:28], r, 0x1 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL2; + + /* 0x10C : GPIO_CFGCTL3 */ + union { + struct + { + uint32_t reg_gpio_6_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_6_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_6_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_6_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_6_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_6_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_7_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_7_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_7_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_7_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_7_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_7_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL3; + + /* 0x110 : GPIO_CFGCTL4 */ + union { + struct + { + uint32_t reg_gpio_8_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_8_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_8_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_8_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_8_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_8_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_9_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_9_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_9_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_9_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_9_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_9_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL4; + + /* 0x114 : GPIO_CFGCTL5 */ + union { + struct + { + uint32_t reg_gpio_10_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_10_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_10_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_10_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_10_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_10_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_11_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_11_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_11_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_11_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_11_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_11_func_sel : 4; /* [27:24], r/w, 0xe */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL5; + + /* 0x118 : GPIO_CFGCTL6 */ + union { + struct + { + uint32_t reg_gpio_12_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_12_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_12_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_12_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_12_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_12_func_sel : 4; /* [11: 8], r/w, 0xe */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_13_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_13_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_13_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_13_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_13_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_13_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL6; + + /* 0x11C : GPIO_CFGCTL7 */ + union { + struct + { + uint32_t reg_gpio_14_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_14_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_14_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_14_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_14_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_14_func_sel : 4; /* [11: 8], r/w, 0xe */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_15_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_15_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_15_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_15_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_15_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_15_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL7; + + /* 0x120 : GPIO_CFGCTL8 */ + union { + struct + { + uint32_t reg_gpio_16_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_16_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_16_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_16_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_16_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_16_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_17_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_17_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_17_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_17_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_17_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_17_func_sel : 4; /* [27:24], r/w, 0xe */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL8; + + /* 0x124 : GPIO_CFGCTL9 */ + union { + struct + { + uint32_t reg_gpio_18_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_18_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_18_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_18_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_18_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_18_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_19_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_19_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_19_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_19_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_19_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_19_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL9; + + /* 0x128 : GPIO_CFGCTL10 */ + union { + struct + { + uint32_t reg_gpio_20_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_20_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_20_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_20_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_20_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_20_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_21_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_21_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_21_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_21_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_21_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL10; + + /* 0x12C : GPIO_CFGCTL11 */ + union { + struct + { + uint32_t reg_gpio_22_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_22_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_22_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_22_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_22_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_22_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_23_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_23_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_23_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_23_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_23_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL11; + + /* 0x130 : GPIO_CFGCTL12 */ + union { + struct + { + uint32_t reg_gpio_24_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_24_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_24_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_24_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_24_pd : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t reg_gpio_25_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_25_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_25_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_25_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_25_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL12; + + /* 0x134 : GPIO_CFGCTL13 */ + union { + struct + { + uint32_t reg_gpio_26_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_26_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_26_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_26_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_26_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t reg_gpio_27_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_27_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_27_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_27_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_27_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL13; + + /* 0x138 : GPIO_CFGCTL14 */ + union { + struct + { + uint32_t reg_gpio_28_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_28_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_28_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_28_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_28_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL14; + + /* 0x13c reserved */ + uint8_t RESERVED0x13c[68]; + + /* 0x180 : GPIO_CFGCTL30 */ + union { + struct + { + uint32_t reg_gpio_0_i : 1; /* [ 0], r, 0x0 */ + uint32_t reg_gpio_1_i : 1; /* [ 1], r, 0x0 */ + uint32_t reg_gpio_2_i : 1; /* [ 2], r, 0x0 */ + uint32_t reg_gpio_3_i : 1; /* [ 3], r, 0x0 */ + uint32_t reg_gpio_4_i : 1; /* [ 4], r, 0x0 */ + uint32_t reg_gpio_5_i : 1; /* [ 5], r, 0x0 */ + uint32_t reg_gpio_6_i : 1; /* [ 6], r, 0x0 */ + uint32_t reg_gpio_7_i : 1; /* [ 7], r, 0x0 */ + uint32_t reg_gpio_8_i : 1; /* [ 8], r, 0x0 */ + uint32_t reg_gpio_9_i : 1; /* [ 9], r, 0x0 */ + uint32_t reg_gpio_10_i : 1; /* [ 10], r, 0x0 */ + uint32_t reg_gpio_11_i : 1; /* [ 11], r, 0x0 */ + uint32_t reg_gpio_12_i : 1; /* [ 12], r, 0x0 */ + uint32_t reg_gpio_13_i : 1; /* [ 13], r, 0x0 */ + uint32_t reg_gpio_14_i : 1; /* [ 14], r, 0x0 */ + uint32_t reg_gpio_15_i : 1; /* [ 15], r, 0x0 */ + uint32_t reg_gpio_16_i : 1; /* [ 16], r, 0x0 */ + uint32_t reg_gpio_17_i : 1; /* [ 17], r, 0x0 */ + uint32_t reg_gpio_18_i : 1; /* [ 18], r, 0x0 */ + uint32_t reg_gpio_19_i : 1; /* [ 19], r, 0x0 */ + uint32_t reg_gpio_20_i : 1; /* [ 20], r, 0x0 */ + uint32_t reg_gpio_21_i : 1; /* [ 21], r, 0x0 */ + uint32_t reg_gpio_22_i : 1; /* [ 22], r, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL30; + + /* 0x184 : GPIO_CFGCTL31 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL31; + + /* 0x188 : GPIO_CFGCTL32 */ + union { + struct + { + uint32_t reg_gpio_0_o : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_gpio_1_o : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_gpio_2_o : 1; /* [ 2], r/w, 0x0 */ + uint32_t reg_gpio_3_o : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_gpio_4_o : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_5_o : 1; /* [ 5], r/w, 0x0 */ + uint32_t reg_gpio_6_o : 1; /* [ 6], r/w, 0x0 */ + uint32_t reg_gpio_7_o : 1; /* [ 7], r/w, 0x0 */ + uint32_t reg_gpio_8_o : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_gpio_9_o : 1; /* [ 9], r/w, 0x0 */ + uint32_t reg_gpio_10_o : 1; /* [ 10], r/w, 0x0 */ + uint32_t reg_gpio_11_o : 1; /* [ 11], r/w, 0x0 */ + uint32_t reg_gpio_12_o : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_gpio_13_o : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_gpio_14_o : 1; /* [ 14], r/w, 0x0 */ + uint32_t reg_gpio_15_o : 1; /* [ 15], r/w, 0x0 */ + uint32_t reg_gpio_16_o : 1; /* [ 16], r/w, 0x0 */ + uint32_t reg_gpio_17_o : 1; /* [ 17], r/w, 0x0 */ + uint32_t reg_gpio_18_o : 1; /* [ 18], r/w, 0x0 */ + uint32_t reg_gpio_19_o : 1; /* [ 19], r/w, 0x0 */ + uint32_t reg_gpio_20_o : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_o : 1; /* [ 21], r/w, 0x0 */ + uint32_t reg_gpio_22_o : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL32; + + /* 0x18C : GPIO_CFGCTL33 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL33; + + /* 0x190 : GPIO_CFGCTL34 */ + union { + struct + { + uint32_t reg_gpio_0_oe : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_gpio_1_oe : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_gpio_2_oe : 1; /* [ 2], r/w, 0x0 */ + uint32_t reg_gpio_3_oe : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_gpio_4_oe : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_5_oe : 1; /* [ 5], r/w, 0x0 */ + uint32_t reg_gpio_6_oe : 1; /* [ 6], r/w, 0x0 */ + uint32_t reg_gpio_7_oe : 1; /* [ 7], r/w, 0x0 */ + uint32_t reg_gpio_8_oe : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_gpio_9_oe : 1; /* [ 9], r/w, 0x0 */ + uint32_t reg_gpio_10_oe : 1; /* [ 10], r/w, 0x0 */ + uint32_t reg_gpio_11_oe : 1; /* [ 11], r/w, 0x0 */ + uint32_t reg_gpio_12_oe : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_gpio_13_oe : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_gpio_14_oe : 1; /* [ 14], r/w, 0x0 */ + uint32_t reg_gpio_15_oe : 1; /* [ 15], r/w, 0x0 */ + uint32_t reg_gpio_16_oe : 1; /* [ 16], r/w, 0x0 */ + uint32_t reg_gpio_17_oe : 1; /* [ 17], r/w, 0x0 */ + uint32_t reg_gpio_18_oe : 1; /* [ 18], r/w, 0x0 */ + uint32_t reg_gpio_19_oe : 1; /* [ 19], r/w, 0x0 */ + uint32_t reg_gpio_20_oe : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_oe : 1; /* [ 21], r/w, 0x0 */ + uint32_t reg_gpio_22_oe : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL34; + + /* 0x194 : GPIO_CFGCTL35 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL35; + + /* 0x198 reserved */ + uint8_t RESERVED0x198[8]; + + /* 0x1A0 : GPIO_INT_MASK1 */ + union { + struct + { + uint32_t reg_gpio_int_mask1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } GPIO_INT_MASK1; + + /* 0x1a4 reserved */ + uint8_t RESERVED0x1a4[4]; + + /* 0x1A8 : GPIO_INT_STAT1 */ + union { + struct + { + uint32_t gpio_int_stat1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_STAT1; + + /* 0x1ac reserved */ + uint8_t RESERVED0x1ac[4]; + + /* 0x1B0 : GPIO_INT_CLR1 */ + union { + struct + { + uint32_t reg_gpio_int_clr1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_CLR1; + + /* 0x1b4 reserved */ + uint8_t RESERVED0x1b4[12]; + + /* 0x1C0 : GPIO_INT_MODE_SET1 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET1; + + /* 0x1C4 : GPIO_INT_MODE_SET2 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET2; + + /* 0x1C8 : GPIO_INT_MODE_SET3 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET3; + + /* 0x1cc reserved */ + uint8_t RESERVED0x1cc[88]; + + /* 0x224 : led_driver */ + union { + struct + { + uint32_t led_din_reg : 1; /* [ 0], r/w, 0x0 */ + uint32_t led_din_sel : 1; /* [ 1], r/w, 0x0 */ + uint32_t led_din_polarity_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t leddrv_ibias : 4; /* [ 7: 4], r/w, 0x8 */ + uint32_t ir_rx_gpio_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_30 : 21; /* [30:10], rsvd, 0x0 */ + uint32_t pu_leddrv : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } led_driver; + + /* 0x228 reserved */ + uint8_t RESERVED0x228[224]; + + /* 0x308 : gpdac_ctrl */ + union { + struct + { + uint32_t gpdaca_rstn_ana : 1; /* [ 0], r/w, 0x1 */ + uint32_t gpdacb_rstn_ana : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_6 : 5; /* [ 6: 2], rsvd, 0x0 */ + uint32_t gpdac_test_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpdac_ref_sel : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpdac_test_sel : 3; /* [11: 9], r/w, 0x0 */ + uint32_t reserved_12_23 : 12; /* [23:12], rsvd, 0x0 */ + uint32_t gpdac_reserved : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } gpdac_ctrl; + + /* 0x30C : gpdac_actrl */ + union { + struct + { + uint32_t gpdac_a_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpdac_ioa_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */ + uint32_t gpdac_a_rng : 2; /* [19:18], r/w, 0x3 */ + uint32_t gpdac_a_outmux : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_actrl; + + /* 0x310 : gpdac_bctrl */ + union { + struct + { + uint32_t gpdac_b_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpdac_iob_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */ + uint32_t gpdac_b_rng : 2; /* [19:18], r/w, 0x3 */ + uint32_t gpdac_b_outmux : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_bctrl; + + /* 0x314 : gpdac_data */ + union { + struct + { + uint32_t gpdac_b_data : 10; /* [ 9: 0], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t gpdac_a_data : 10; /* [25:16], r/w, 0x0 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_data; + + /* 0x318 reserved */ + uint8_t RESERVED0x318[3048]; + + /* 0xF00 : tzc_glb_ctrl_0 */ + union { + struct + { + uint32_t tzc_glb_swrst_s00_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_swrst_s01_lock : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t tzc_glb_swrst_s30_lock : 1; /* [ 8], r, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t tzc_glb_ctrl_pwron_rst_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_ctrl_cpu_reset_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_ctrl_sys_reset_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [ 15], r, 0x0 */ + uint32_t reserved_16_24 : 9; /* [24:16], rsvd, 0x0 */ + uint32_t tzc_glb_misc_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_sram_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_l2c_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_bmx_lock : 1; /* [ 28], r, 0x0 */ + uint32_t tzc_glb_dbg_lock : 1; /* [ 29], r, 0x0 */ + uint32_t tzc_glb_mbist_lock : 1; /* [ 30], r, 0x0 */ + uint32_t tzc_glb_clk_lock : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_0; + + /* 0xF04 : tzc_glb_ctrl_1 */ + union { + struct + { + uint32_t tzc_glb_swrst_s20_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_swrst_s21_lock : 1; /* [ 1], r, 0x0 */ + uint32_t tzc_glb_swrst_s22_lock : 1; /* [ 2], r, 0x0 */ + uint32_t tzc_glb_swrst_s23_lock : 1; /* [ 3], r, 0x0 */ + uint32_t tzc_glb_swrst_s24_lock : 1; /* [ 4], r, 0x0 */ + uint32_t tzc_glb_swrst_s25_lock : 1; /* [ 5], r, 0x0 */ + uint32_t tzc_glb_swrst_s26_lock : 1; /* [ 6], r, 0x0 */ + uint32_t tzc_glb_swrst_s27_lock : 1; /* [ 7], r, 0x0 */ + uint32_t tzc_glb_swrst_s28_lock : 1; /* [ 8], r, 0x0 */ + uint32_t tzc_glb_swrst_s29_lock : 1; /* [ 9], r, 0x0 */ + uint32_t tzc_glb_swrst_s2a_lock : 1; /* [ 10], r, 0x0 */ + uint32_t tzc_glb_swrst_s2b_lock : 1; /* [ 11], r, 0x0 */ + uint32_t tzc_glb_swrst_s2c_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_swrst_s2d_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_swrst_s2e_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_swrst_s2f_lock : 1; /* [ 15], r, 0x0 */ + uint32_t tzc_glb_swrst_s10_lock : 1; /* [ 16], r, 0x0 */ + uint32_t tzc_glb_swrst_s11_lock : 1; /* [ 17], r, 0x0 */ + uint32_t tzc_glb_swrst_s12_lock : 1; /* [ 18], r, 0x0 */ + uint32_t tzc_glb_swrst_s13_lock : 1; /* [ 19], r, 0x0 */ + uint32_t tzc_glb_swrst_s14_lock : 1; /* [ 20], r, 0x0 */ + uint32_t tzc_glb_swrst_s15_lock : 1; /* [ 21], r, 0x0 */ + uint32_t tzc_glb_swrst_s16_lock : 1; /* [ 22], r, 0x0 */ + uint32_t tzc_glb_swrst_s17_lock : 1; /* [ 23], r, 0x0 */ + uint32_t tzc_glb_swrst_s18_lock : 1; /* [ 24], r, 0x0 */ + uint32_t tzc_glb_swrst_s19_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_swrst_s1a_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_swrst_s1b_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_swrst_s1c_lock : 1; /* [ 28], r, 0x0 */ + uint32_t tzc_glb_swrst_s1d_lock : 1; /* [ 29], r, 0x0 */ + uint32_t tzc_glb_swrst_s1e_lock : 1; /* [ 30], r, 0x0 */ + uint32_t tzc_glb_swrst_s1f_lock : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_1; + + /* 0xF08 : tzc_glb_ctrl_2 */ + union { + struct + { + uint32_t tzc_glb_gpio_0_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_gpio_1_lock : 1; /* [ 1], r, 0x0 */ + uint32_t tzc_glb_gpio_2_lock : 1; /* [ 2], r, 0x0 */ + uint32_t tzc_glb_gpio_3_lock : 1; /* [ 3], r, 0x0 */ + uint32_t tzc_glb_gpio_4_lock : 1; /* [ 4], r, 0x0 */ + uint32_t tzc_glb_gpio_5_lock : 1; /* [ 5], r, 0x0 */ + uint32_t tzc_glb_gpio_6_lock : 1; /* [ 6], r, 0x0 */ + uint32_t tzc_glb_gpio_7_lock : 1; /* [ 7], r, 0x0 */ + uint32_t tzc_glb_gpio_8_lock : 1; /* [ 8], r, 0x0 */ + uint32_t tzc_glb_gpio_9_lock : 1; /* [ 9], r, 0x0 */ + uint32_t tzc_glb_gpio_10_lock : 1; /* [ 10], r, 0x0 */ + uint32_t tzc_glb_gpio_11_lock : 1; /* [ 11], r, 0x0 */ + uint32_t tzc_glb_gpio_12_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_gpio_13_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_gpio_14_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_gpio_15_lock : 1; /* [ 15], r, 0x0 */ + uint32_t tzc_glb_gpio_16_lock : 1; /* [ 16], r, 0x0 */ + uint32_t tzc_glb_gpio_17_lock : 1; /* [ 17], r, 0x0 */ + uint32_t tzc_glb_gpio_18_lock : 1; /* [ 18], r, 0x0 */ + uint32_t tzc_glb_gpio_19_lock : 1; /* [ 19], r, 0x0 */ + uint32_t tzc_glb_gpio_20_lock : 1; /* [ 20], r, 0x0 */ + uint32_t tzc_glb_gpio_21_lock : 1; /* [ 21], r, 0x0 */ + uint32_t tzc_glb_gpio_22_lock : 1; /* [ 22], r, 0x0 */ + uint32_t tzc_glb_gpio_23_lock : 1; /* [ 23], r, 0x0 */ + uint32_t tzc_glb_gpio_24_lock : 1; /* [ 24], r, 0x0 */ + uint32_t tzc_glb_gpio_25_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_gpio_26_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_gpio_27_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_gpio_28_lock : 1; /* [ 28], r, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_2; + + /* 0xF0C : tzc_glb_ctrl_3 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_3; +}; + +typedef volatile struct glb_reg glb_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : GPIO_CFGCTL */ +#define GLB_GPIO_CFGCTL_OFFSET (0x0) +#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE +#define GLB_REG_GPIO_0_IE_POS (0U) +#define GLB_REG_GPIO_0_IE_LEN (1U) +#define GLB_REG_GPIO_0_IE_MSK (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) +#define GLB_REG_GPIO_0_IE_UMSK (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) +#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT +#define GLB_REG_GPIO_0_SMT_POS (1U) +#define GLB_REG_GPIO_0_SMT_LEN (1U) +#define GLB_REG_GPIO_0_SMT_MSK (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) +#define GLB_REG_GPIO_0_SMT_UMSK (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) +#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV +#define GLB_REG_GPIO_0_DRV_POS (2U) +#define GLB_REG_GPIO_0_DRV_LEN (2U) +#define GLB_REG_GPIO_0_DRV_MSK (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) +#define GLB_REG_GPIO_0_DRV_UMSK (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) +#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU +#define GLB_REG_GPIO_0_PU_POS (4U) +#define GLB_REG_GPIO_0_PU_LEN (1U) +#define GLB_REG_GPIO_0_PU_MSK (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) +#define GLB_REG_GPIO_0_PU_UMSK (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) +#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD +#define GLB_REG_GPIO_0_PD_POS (5U) +#define GLB_REG_GPIO_0_PD_LEN (1U) +#define GLB_REG_GPIO_0_PD_MSK (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) +#define GLB_REG_GPIO_0_PD_UMSK (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) +#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL +#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) +#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL +#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U) +#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS) +#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)) +#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE +#define GLB_REG_GPIO_1_IE_POS (16U) +#define GLB_REG_GPIO_1_IE_LEN (1U) +#define GLB_REG_GPIO_1_IE_MSK (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) +#define GLB_REG_GPIO_1_IE_UMSK (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) +#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT +#define GLB_REG_GPIO_1_SMT_POS (17U) +#define GLB_REG_GPIO_1_SMT_LEN (1U) +#define GLB_REG_GPIO_1_SMT_MSK (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) +#define GLB_REG_GPIO_1_SMT_UMSK (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) +#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV +#define GLB_REG_GPIO_1_DRV_POS (18U) +#define GLB_REG_GPIO_1_DRV_LEN (2U) +#define GLB_REG_GPIO_1_DRV_MSK (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) +#define GLB_REG_GPIO_1_DRV_UMSK (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) +#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU +#define GLB_REG_GPIO_1_PU_POS (20U) +#define GLB_REG_GPIO_1_PU_LEN (1U) +#define GLB_REG_GPIO_1_PU_MSK (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) +#define GLB_REG_GPIO_1_PU_UMSK (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) +#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD +#define GLB_REG_GPIO_1_PD_POS (21U) +#define GLB_REG_GPIO_1_PD_LEN (1U) +#define GLB_REG_GPIO_1_PD_MSK (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) +#define GLB_REG_GPIO_1_PD_UMSK (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) +#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL +#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) +#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL +#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U) +#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS) +#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)) + +struct glb_gpio_reg { + /* 0x0 : GPIO_CFGCTL */ + union { + struct + { + uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_0_func_sel : 4; /* [11: 8], r/w, 0x1 */ + uint32_t real_gpio_0_func_sel : 4; /* [15:12], r, 0x1 */ + uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_1_func_sel : 4; /* [27:24], r/w, 0x1 */ + uint32_t real_gpio_1_func_sel : 4; /* [31:28], r, 0x1 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL; +}; + +typedef volatile struct glb_gpio_reg glb_gpio_reg_t; + +#define GLB_GPIO_OFFSET 0x100 +#define GLB_GPIO_INPUT_OFFSET 0x180 +#define GLB_GPIO_OUTPUT_OFFSET 0x188 +#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190 + +#endif /* __GLB_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/gpip_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/gpip_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..7b5984554ff4cfb2a86551726084479215057c6a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/gpip_reg.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file gpip_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __GPIP_REG_H__ +#define __GPIP_REG_H__ + +#include "bl602.h" + +/* 0x0 : gpadc_config */ +#define GPIP_GPADC_CONFIG_OFFSET (0x0) +#define GPIP_GPADC_DMA_EN GPIP_GPADC_DMA_EN +#define GPIP_GPADC_DMA_EN_POS (0U) +#define GPIP_GPADC_DMA_EN_LEN (1U) +#define GPIP_GPADC_DMA_EN_MSK (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS) +#define GPIP_GPADC_DMA_EN_UMSK (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)) +#define GPIP_GPADC_FIFO_CLR GPIP_GPADC_FIFO_CLR +#define GPIP_GPADC_FIFO_CLR_POS (1U) +#define GPIP_GPADC_FIFO_CLR_LEN (1U) +#define GPIP_GPADC_FIFO_CLR_MSK (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS) +#define GPIP_GPADC_FIFO_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)) +#define GPIP_GPADC_FIFO_NE GPIP_GPADC_FIFO_NE +#define GPIP_GPADC_FIFO_NE_POS (2U) +#define GPIP_GPADC_FIFO_NE_LEN (1U) +#define GPIP_GPADC_FIFO_NE_MSK (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS) +#define GPIP_GPADC_FIFO_NE_UMSK (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)) +#define GPIP_GPADC_FIFO_FULL GPIP_GPADC_FIFO_FULL +#define GPIP_GPADC_FIFO_FULL_POS (3U) +#define GPIP_GPADC_FIFO_FULL_LEN (1U) +#define GPIP_GPADC_FIFO_FULL_MSK (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS) +#define GPIP_GPADC_FIFO_FULL_UMSK (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)) +#define GPIP_GPADC_RDY GPIP_GPADC_RDY +#define GPIP_GPADC_RDY_POS (4U) +#define GPIP_GPADC_RDY_LEN (1U) +#define GPIP_GPADC_RDY_MSK (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS) +#define GPIP_GPADC_RDY_UMSK (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)) +#define GPIP_GPADC_FIFO_OVERRUN GPIP_GPADC_FIFO_OVERRUN +#define GPIP_GPADC_FIFO_OVERRUN_POS (5U) +#define GPIP_GPADC_FIFO_OVERRUN_LEN (1U) +#define GPIP_GPADC_FIFO_OVERRUN_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS) +#define GPIP_GPADC_FIFO_OVERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)) +#define GPIP_GPADC_FIFO_UNDERRUN GPIP_GPADC_FIFO_UNDERRUN +#define GPIP_GPADC_FIFO_UNDERRUN_POS (6U) +#define GPIP_GPADC_FIFO_UNDERRUN_LEN (1U) +#define GPIP_GPADC_FIFO_UNDERRUN_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS) +#define GPIP_GPADC_FIFO_UNDERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)) +#define GPIP_GPADC_RDY_CLR GPIP_GPADC_RDY_CLR +#define GPIP_GPADC_RDY_CLR_POS (8U) +#define GPIP_GPADC_RDY_CLR_LEN (1U) +#define GPIP_GPADC_RDY_CLR_MSK (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS) +#define GPIP_GPADC_RDY_CLR_UMSK (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)) +#define GPIP_GPADC_FIFO_OVERRUN_CLR GPIP_GPADC_FIFO_OVERRUN_CLR +#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS (9U) +#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN (1U) +#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS) +#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)) +#define GPIP_GPADC_FIFO_UNDERRUN_CLR GPIP_GPADC_FIFO_UNDERRUN_CLR +#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS (10U) +#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN (1U) +#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS) +#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)) +#define GPIP_GPADC_RDY_MASK GPIP_GPADC_RDY_MASK +#define GPIP_GPADC_RDY_MASK_POS (12U) +#define GPIP_GPADC_RDY_MASK_LEN (1U) +#define GPIP_GPADC_RDY_MASK_MSK (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS) +#define GPIP_GPADC_RDY_MASK_UMSK (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)) +#define GPIP_GPADC_FIFO_OVERRUN_MASK GPIP_GPADC_FIFO_OVERRUN_MASK +#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS (13U) +#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN (1U) +#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS) +#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)) +#define GPIP_GPADC_FIFO_UNDERRUN_MASK GPIP_GPADC_FIFO_UNDERRUN_MASK +#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS (14U) +#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN (1U) +#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS) +#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)) +#define GPIP_GPADC_FIFO_DATA_COUNT GPIP_GPADC_FIFO_DATA_COUNT +#define GPIP_GPADC_FIFO_DATA_COUNT_POS (16U) +#define GPIP_GPADC_FIFO_DATA_COUNT_LEN (6U) +#define GPIP_GPADC_FIFO_DATA_COUNT_MSK (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS) +#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)) +#define GPIP_GPADC_FIFO_THL GPIP_GPADC_FIFO_THL +#define GPIP_GPADC_FIFO_THL_POS (22U) +#define GPIP_GPADC_FIFO_THL_LEN (2U) +#define GPIP_GPADC_FIFO_THL_MSK (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS) +#define GPIP_GPADC_FIFO_THL_UMSK (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)) + +/* 0x4 : gpadc_dma_rdata */ +#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4) +#define GPIP_GPADC_DMA_RDATA GPIP_GPADC_DMA_RDATA +#define GPIP_GPADC_DMA_RDATA_POS (0U) +#define GPIP_GPADC_DMA_RDATA_LEN (26U) +#define GPIP_GPADC_DMA_RDATA_MSK (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS) +#define GPIP_GPADC_DMA_RDATA_UMSK (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)) + +/* 0x40 : gpdac_config */ +#define GPIP_GPDAC_CONFIG_OFFSET (0x40) +#define GPIP_GPDAC_EN GPIP_GPDAC_EN +#define GPIP_GPDAC_EN_POS (0U) +#define GPIP_GPDAC_EN_LEN (1U) +#define GPIP_GPDAC_EN_MSK (((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS) +#define GPIP_GPDAC_EN_UMSK (~(((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS)) +#define GPIP_GPDAC_EN2 GPIP_GPDAC_EN2 +#define GPIP_GPDAC_EN2_POS (1U) +#define GPIP_GPDAC_EN2_LEN (1U) +#define GPIP_GPDAC_EN2_MSK (((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS) +#define GPIP_GPDAC_EN2_UMSK (~(((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS)) +#define GPIP_DSM_MODE GPIP_DSM_MODE +#define GPIP_DSM_MODE_POS (4U) +#define GPIP_DSM_MODE_LEN (2U) +#define GPIP_DSM_MODE_MSK (((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS) +#define GPIP_DSM_MODE_UMSK (~(((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS)) +#define GPIP_GPDAC_MODE GPIP_GPDAC_MODE +#define GPIP_GPDAC_MODE_POS (8U) +#define GPIP_GPDAC_MODE_LEN (3U) +#define GPIP_GPDAC_MODE_MSK (((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS) +#define GPIP_GPDAC_MODE_UMSK (~(((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS)) +#define GPIP_GPDAC_CH_A_SEL GPIP_GPDAC_CH_A_SEL +#define GPIP_GPDAC_CH_A_SEL_POS (16U) +#define GPIP_GPDAC_CH_A_SEL_LEN (4U) +#define GPIP_GPDAC_CH_A_SEL_MSK (((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS) +#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS)) +#define GPIP_GPDAC_CH_B_SEL GPIP_GPDAC_CH_B_SEL +#define GPIP_GPDAC_CH_B_SEL_POS (20U) +#define GPIP_GPDAC_CH_B_SEL_LEN (4U) +#define GPIP_GPDAC_CH_B_SEL_MSK (((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS) +#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS)) + +/* 0x44 : gpdac_dma_config */ +#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44) +#define GPIP_GPDAC_DMA_TX_EN GPIP_GPDAC_DMA_TX_EN +#define GPIP_GPDAC_DMA_TX_EN_POS (0U) +#define GPIP_GPDAC_DMA_TX_EN_LEN (1U) +#define GPIP_GPDAC_DMA_TX_EN_MSK (((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS) +#define GPIP_GPDAC_DMA_TX_EN_UMSK (~(((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS)) +#define GPIP_GPDAC_DMA_FORMAT GPIP_GPDAC_DMA_FORMAT +#define GPIP_GPDAC_DMA_FORMAT_POS (4U) +#define GPIP_GPDAC_DMA_FORMAT_LEN (2U) +#define GPIP_GPDAC_DMA_FORMAT_MSK (((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS) +#define GPIP_GPDAC_DMA_FORMAT_UMSK (~(((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS)) + +/* 0x48 : gpdac_dma_wdata */ +#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48) +#define GPIP_GPDAC_DMA_WDATA GPIP_GPDAC_DMA_WDATA +#define GPIP_GPDAC_DMA_WDATA_POS (0U) +#define GPIP_GPDAC_DMA_WDATA_LEN (32U) +#define GPIP_GPDAC_DMA_WDATA_MSK (((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS) +#define GPIP_GPDAC_DMA_WDATA_UMSK (~(((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS)) + +/* 0x4C : gpdac_tx_fifo_status */ +#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C) +#define GPIP_TX_FIFO_EMPTY GPIP_TX_FIFO_EMPTY +#define GPIP_TX_FIFO_EMPTY_POS (0U) +#define GPIP_TX_FIFO_EMPTY_LEN (1U) +#define GPIP_TX_FIFO_EMPTY_MSK (((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS) +#define GPIP_TX_FIFO_EMPTY_UMSK (~(((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS)) +#define GPIP_TX_FIFO_FULL GPIP_TX_FIFO_FULL +#define GPIP_TX_FIFO_FULL_POS (1U) +#define GPIP_TX_FIFO_FULL_LEN (1U) +#define GPIP_TX_FIFO_FULL_MSK (((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS) +#define GPIP_TX_FIFO_FULL_UMSK (~(((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS)) +#define GPIP_TX_CS GPIP_TX_CS +#define GPIP_TX_CS_POS (2U) +#define GPIP_TX_CS_LEN (2U) +#define GPIP_TX_CS_MSK (((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS) +#define GPIP_TX_CS_UMSK (~(((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS)) +#define GPIP_TXFIFORDPTR GPIP_TXFIFORDPTR +#define GPIP_TXFIFORDPTR_POS (4U) +#define GPIP_TXFIFORDPTR_LEN (3U) +#define GPIP_TXFIFORDPTR_MSK (((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS) +#define GPIP_TXFIFORDPTR_UMSK (~(((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS)) +#define GPIP_TXFIFOWRPTR GPIP_TXFIFOWRPTR +#define GPIP_TXFIFOWRPTR_POS (8U) +#define GPIP_TXFIFOWRPTR_LEN (2U) +#define GPIP_TXFIFOWRPTR_MSK (((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS) +#define GPIP_TXFIFOWRPTR_UMSK (~(((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS)) + +struct gpip_reg { + /* 0x0 : gpadc_config */ + union { + struct + { + uint32_t gpadc_dma_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpadc_fifo_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t gpadc_fifo_ne : 1; /* [ 2], r, 0x0 */ + uint32_t gpadc_fifo_full : 1; /* [ 3], r, 0x0 */ + uint32_t gpadc_rdy : 1; /* [ 4], r, 0x0 */ + uint32_t gpadc_fifo_overrun : 1; /* [ 5], r, 0x0 */ + uint32_t gpadc_fifo_underrun : 1; /* [ 6], r, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t gpadc_rdy_clr : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpadc_fifo_overrun_clr : 1; /* [ 9], r/w, 0x0 */ + uint32_t gpadc_fifo_underrun_clr : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t gpadc_rdy_mask : 1; /* [ 12], r/w, 0x0 */ + uint32_t gpadc_fifo_overrun_mask : 1; /* [ 13], r/w, 0x0 */ + uint32_t gpadc_fifo_underrun_mask : 1; /* [ 14], r/w, 0x0 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t gpadc_fifo_data_count : 6; /* [21:16], r, 0x0 */ + uint32_t gpadc_fifo_thl : 2; /* [23:22], r/w, 0x0 */ + uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_config; + + /* 0x4 : gpadc_dma_rdata */ + union { + struct + { + uint32_t gpadc_dma_rdata : 26; /* [25: 0], r, 0x0 */ + uint32_t rsvd_31_26 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_dma_rdata; + + /* 0x8 reserved */ + uint8_t RESERVED0x8[56]; + + /* 0x40 : gpdac_config */ + union { + struct + { + uint32_t gpdac_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpdac_en2 : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t dsm_mode : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t gpdac_mode : 3; /* [10: 8], r/w, 0x0 */ + uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ + uint32_t gpdac_ch_a_sel : 4; /* [19:16], r/w, 0x0 */ + uint32_t gpdac_ch_b_sel : 4; /* [23:20], r/w, 0x0 */ + uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0xd */ + } BF; + uint32_t WORD; + } gpdac_config; + + /* 0x44 : gpdac_dma_config */ + union { + struct + { + uint32_t gpdac_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t gpdac_dma_format : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_dma_config; + + /* 0x48 : gpdac_dma_wdata */ + union { + struct + { + uint32_t gpdac_dma_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } gpdac_dma_wdata; + + /* 0x4C : gpdac_tx_fifo_status */ + union { + struct + { + uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */ + uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */ + uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */ + uint32_t TxFifoRdPtr : 3; /* [ 6: 4], r, 0x4 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_tx_fifo_status; +}; + +typedef volatile struct gpip_reg gpip_reg_t; + +#endif /* __GPIP_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/hbn_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/hbn_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..1aef0ab76661fc3062fc64a16c805d90b6e1e08b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/hbn_reg.h @@ -0,0 +1,760 @@ +/** + ****************************************************************************** + * @file hbn_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HBN_REG_H__ +#define __HBN_REG_H__ + +#include "bl602.h" + +/* 0x0 : HBN_CTL */ +#define HBN_CTL_OFFSET (0x0) +#define HBN_RTC_CTL HBN_RTC_CTL +#define HBN_RTC_CTL_POS (0U) +#define HBN_RTC_CTL_LEN (7U) +#define HBN_RTC_CTL_MSK (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS) +#define HBN_RTC_CTL_UMSK (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)) +#define HBN_MODE HBN_MODE +#define HBN_MODE_POS (7U) +#define HBN_MODE_LEN (1U) +#define HBN_MODE_MSK (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS) +#define HBN_MODE_UMSK (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)) +#define HBN_TRAP_MODE HBN_TRAP_MODE +#define HBN_TRAP_MODE_POS (8U) +#define HBN_TRAP_MODE_LEN (1U) +#define HBN_TRAP_MODE_MSK (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS) +#define HBN_TRAP_MODE_UMSK (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)) +#define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE +#define HBN_PWRDN_HBN_CORE_POS (9U) +#define HBN_PWRDN_HBN_CORE_LEN (1U) +#define HBN_PWRDN_HBN_CORE_MSK (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS) +#define HBN_PWRDN_HBN_CORE_UMSK (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)) +#define HBN_PWRDN_HBN_RTC HBN_PWRDN_HBN_RTC +#define HBN_PWRDN_HBN_RTC_POS (11U) +#define HBN_PWRDN_HBN_RTC_LEN (1U) +#define HBN_PWRDN_HBN_RTC_MSK (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS) +#define HBN_PWRDN_HBN_RTC_UMSK (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)) +#define HBN_SW_RST HBN_SW_RST +#define HBN_SW_RST_POS (12U) +#define HBN_SW_RST_LEN (1U) +#define HBN_SW_RST_MSK (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS) +#define HBN_SW_RST_UMSK (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)) +#define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11 +#define HBN_DIS_PWR_OFF_LDO11_POS (13U) +#define HBN_DIS_PWR_OFF_LDO11_LEN (1U) +#define HBN_DIS_PWR_OFF_LDO11_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS) +#define HBN_DIS_PWR_OFF_LDO11_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)) +#define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT +#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U) +#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U) +#define HBN_DIS_PWR_OFF_LDO11_RT_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS) +#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)) +#define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL +#define HBN_LDO11_RT_VOUT_SEL_POS (15U) +#define HBN_LDO11_RT_VOUT_SEL_LEN (4U) +#define HBN_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS) +#define HBN_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)) +#define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL +#define HBN_LDO11_AON_VOUT_SEL_POS (19U) +#define HBN_LDO11_AON_VOUT_SEL_LEN (4U) +#define HBN_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS) +#define HBN_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)) +#define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON +#define HBN_PU_DCDC18_AON_POS (23U) +#define HBN_PU_DCDC18_AON_LEN (1U) +#define HBN_PU_DCDC18_AON_MSK (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS) +#define HBN_PU_DCDC18_AON_UMSK (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)) +#define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION +#define HBN_RTC_DLY_OPTION_POS (24U) +#define HBN_RTC_DLY_OPTION_LEN (1U) +#define HBN_RTC_DLY_OPTION_MSK (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS) +#define HBN_RTC_DLY_OPTION_UMSK (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)) +#define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION +#define HBN_PWR_ON_OPTION_POS (25U) +#define HBN_PWR_ON_OPTION_LEN (1U) +#define HBN_PWR_ON_OPTION_MSK (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS) +#define HBN_PWR_ON_OPTION_UMSK (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)) +#define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION +#define HBN_SRAM_SLP_OPTION_POS (26U) +#define HBN_SRAM_SLP_OPTION_LEN (1U) +#define HBN_SRAM_SLP_OPTION_MSK (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS) +#define HBN_SRAM_SLP_OPTION_UMSK (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)) +#define HBN_SRAM_SLP HBN_SRAM_SLP +#define HBN_SRAM_SLP_POS (27U) +#define HBN_SRAM_SLP_LEN (1U) +#define HBN_SRAM_SLP_MSK (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS) +#define HBN_SRAM_SLP_UMSK (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)) +#define HBN_STATE HBN_STATE +#define HBN_STATE_POS (28U) +#define HBN_STATE_LEN (4U) +#define HBN_STATE_MSK (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS) +#define HBN_STATE_UMSK (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)) + +/* 0x4 : HBN_TIME_L */ +#define HBN_TIME_L_OFFSET (0x4) +#define HBN_TIME_L HBN_TIME_L +#define HBN_TIME_L_POS (0U) +#define HBN_TIME_L_LEN (32U) +#define HBN_TIME_L_MSK (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS) +#define HBN_TIME_L_UMSK (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)) + +/* 0x8 : HBN_TIME_H */ +#define HBN_TIME_H_OFFSET (0x8) +#define HBN_TIME_H HBN_TIME_H +#define HBN_TIME_H_POS (0U) +#define HBN_TIME_H_LEN (8U) +#define HBN_TIME_H_MSK (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS) +#define HBN_TIME_H_UMSK (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)) + +/* 0xC : RTC_TIME_L */ +#define HBN_RTC_TIME_L_OFFSET (0xC) +#define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L +#define HBN_RTC_TIME_LATCH_L_POS (0U) +#define HBN_RTC_TIME_LATCH_L_LEN (32U) +#define HBN_RTC_TIME_LATCH_L_MSK (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS) +#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)) + +/* 0x10 : RTC_TIME_H */ +#define HBN_RTC_TIME_H_OFFSET (0x10) +#define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H +#define HBN_RTC_TIME_LATCH_H_POS (0U) +#define HBN_RTC_TIME_LATCH_H_LEN (8U) +#define HBN_RTC_TIME_LATCH_H_MSK (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS) +#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)) +#define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH +#define HBN_RTC_TIME_LATCH_POS (31U) +#define HBN_RTC_TIME_LATCH_LEN (1U) +#define HBN_RTC_TIME_LATCH_MSK (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS) +#define HBN_RTC_TIME_LATCH_UMSK (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)) + +/* 0x14 : HBN_IRQ_MODE */ +#define HBN_IRQ_MODE_OFFSET (0x14) +#define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE +#define HBN_PIN_WAKEUP_MODE_POS (0U) +#define HBN_PIN_WAKEUP_MODE_LEN (3U) +#define HBN_PIN_WAKEUP_MODE_MSK (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS) +#define HBN_PIN_WAKEUP_MODE_UMSK (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)) +#define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK +#define HBN_PIN_WAKEUP_MASK_POS (3U) +#define HBN_PIN_WAKEUP_MASK_LEN (2U) +#define HBN_PIN_WAKEUP_MASK_MSK (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS) +#define HBN_PIN_WAKEUP_MASK_UMSK (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)) +#define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT +#define HBN_REG_AON_PAD_IE_SMT_POS (8U) +#define HBN_REG_AON_PAD_IE_SMT_LEN (1U) +#define HBN_REG_AON_PAD_IE_SMT_MSK (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS) +#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)) +#define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD +#define HBN_REG_EN_HW_PU_PD_POS (16U) +#define HBN_REG_EN_HW_PU_PD_LEN (1U) +#define HBN_REG_EN_HW_PU_PD_MSK (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS) +#define HBN_REG_EN_HW_PU_PD_UMSK (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)) +#define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN +#define HBN_IRQ_BOR_EN_POS (18U) +#define HBN_IRQ_BOR_EN_LEN (1U) +#define HBN_IRQ_BOR_EN_MSK (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS) +#define HBN_IRQ_BOR_EN_UMSK (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)) +#define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN +#define HBN_IRQ_ACOMP0_EN_POS (20U) +#define HBN_IRQ_ACOMP0_EN_LEN (2U) +#define HBN_IRQ_ACOMP0_EN_MSK (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS) +#define HBN_IRQ_ACOMP0_EN_UMSK (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)) +#define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN +#define HBN_IRQ_ACOMP1_EN_POS (22U) +#define HBN_IRQ_ACOMP1_EN_LEN (2U) +#define HBN_IRQ_ACOMP1_EN_MSK (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS) +#define HBN_IRQ_ACOMP1_EN_UMSK (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)) +#define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL +#define HBN_PIN_WAKEUP_SEL_POS (24U) +#define HBN_PIN_WAKEUP_SEL_LEN (3U) +#define HBN_PIN_WAKEUP_SEL_MSK (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS) +#define HBN_PIN_WAKEUP_SEL_UMSK (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)) +#define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN +#define HBN_PIN_WAKEUP_EN_POS (27U) +#define HBN_PIN_WAKEUP_EN_LEN (1U) +#define HBN_PIN_WAKEUP_EN_MSK (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS) +#define HBN_PIN_WAKEUP_EN_UMSK (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)) + +/* 0x18 : HBN_IRQ_STAT */ +#define HBN_IRQ_STAT_OFFSET (0x18) +#define HBN_IRQ_STAT HBN_IRQ_STAT +#define HBN_IRQ_STAT_POS (0U) +#define HBN_IRQ_STAT_LEN (32U) +#define HBN_IRQ_STAT_MSK (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS) +#define HBN_IRQ_STAT_UMSK (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)) + +/* 0x1C : HBN_IRQ_CLR */ +#define HBN_IRQ_CLR_OFFSET (0x1C) +#define HBN_IRQ_CLR HBN_IRQ_CLR +#define HBN_IRQ_CLR_POS (0U) +#define HBN_IRQ_CLR_LEN (32U) +#define HBN_IRQ_CLR_MSK (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS) +#define HBN_IRQ_CLR_UMSK (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)) + +/* 0x20 : HBN_PIR_CFG */ +#define HBN_PIR_CFG_OFFSET (0x20) +#define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL +#define HBN_PIR_HPF_SEL_POS (0U) +#define HBN_PIR_HPF_SEL_LEN (2U) +#define HBN_PIR_HPF_SEL_MSK (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS) +#define HBN_PIR_HPF_SEL_UMSK (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)) +#define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL +#define HBN_PIR_LPF_SEL_POS (2U) +#define HBN_PIR_LPF_SEL_LEN (1U) +#define HBN_PIR_LPF_SEL_MSK (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS) +#define HBN_PIR_LPF_SEL_UMSK (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)) +#define HBN_PIR_DIS HBN_PIR_DIS +#define HBN_PIR_DIS_POS (4U) +#define HBN_PIR_DIS_LEN (2U) +#define HBN_PIR_DIS_MSK (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS) +#define HBN_PIR_DIS_UMSK (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)) +#define HBN_PIR_EN HBN_PIR_EN +#define HBN_PIR_EN_POS (7U) +#define HBN_PIR_EN_LEN (1U) +#define HBN_PIR_EN_MSK (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS) +#define HBN_PIR_EN_UMSK (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)) +#define HBN_GPADC_CGEN HBN_GPADC_CGEN +#define HBN_GPADC_CGEN_POS (8U) +#define HBN_GPADC_CGEN_LEN (1U) +#define HBN_GPADC_CGEN_MSK (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS) +#define HBN_GPADC_CGEN_UMSK (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)) +#define HBN_GPADC_NOSYNC HBN_GPADC_NOSYNC +#define HBN_GPADC_NOSYNC_POS (9U) +#define HBN_GPADC_NOSYNC_LEN (1U) +#define HBN_GPADC_NOSYNC_MSK (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS) +#define HBN_GPADC_NOSYNC_UMSK (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)) + +/* 0x24 : HBN_PIR_VTH */ +#define HBN_PIR_VTH_OFFSET (0x24) +#define HBN_PIR_VTH HBN_PIR_VTH +#define HBN_PIR_VTH_POS (0U) +#define HBN_PIR_VTH_LEN (14U) +#define HBN_PIR_VTH_MSK (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS) +#define HBN_PIR_VTH_UMSK (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)) + +/* 0x28 : HBN_PIR_INTERVAL */ +#define HBN_PIR_INTERVAL_OFFSET (0x28) +#define HBN_PIR_INTERVAL HBN_PIR_INTERVAL +#define HBN_PIR_INTERVAL_POS (0U) +#define HBN_PIR_INTERVAL_LEN (12U) +#define HBN_PIR_INTERVAL_MSK (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS) +#define HBN_PIR_INTERVAL_UMSK (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)) + +/* 0x2C : HBN_BOR_CFG */ +#define HBN_BOR_CFG_OFFSET (0x2C) +#define HBN_BOR_SEL HBN_BOR_SEL +#define HBN_BOR_SEL_POS (0U) +#define HBN_BOR_SEL_LEN (1U) +#define HBN_BOR_SEL_MSK (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS) +#define HBN_BOR_SEL_UMSK (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)) +#define HBN_BOR_VTH HBN_BOR_VTH +#define HBN_BOR_VTH_POS (1U) +#define HBN_BOR_VTH_LEN (1U) +#define HBN_BOR_VTH_MSK (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS) +#define HBN_BOR_VTH_UMSK (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)) +#define HBN_PU_BOR HBN_PU_BOR +#define HBN_PU_BOR_POS (2U) +#define HBN_PU_BOR_LEN (1U) +#define HBN_PU_BOR_MSK (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS) +#define HBN_PU_BOR_UMSK (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)) +#define HBN_R_BOR_OUT HBN_R_BOR_OUT +#define HBN_R_BOR_OUT_POS (3U) +#define HBN_R_BOR_OUT_LEN (1U) +#define HBN_R_BOR_OUT_MSK (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS) +#define HBN_R_BOR_OUT_UMSK (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)) + +/* 0x30 : HBN_GLB */ +#define HBN_GLB_OFFSET (0x30) +#define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL +#define HBN_ROOT_CLK_SEL_POS (0U) +#define HBN_ROOT_CLK_SEL_LEN (2U) +#define HBN_ROOT_CLK_SEL_MSK (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS) +#define HBN_ROOT_CLK_SEL_UMSK (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)) +#define HBN_UART_CLK_SEL HBN_UART_CLK_SEL +#define HBN_UART_CLK_SEL_POS (2U) +#define HBN_UART_CLK_SEL_LEN (1U) +#define HBN_UART_CLK_SEL_MSK (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS) +#define HBN_UART_CLK_SEL_UMSK (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)) +#define HBN_F32K_SEL HBN_F32K_SEL +#define HBN_F32K_SEL_POS (3U) +#define HBN_F32K_SEL_LEN (2U) +#define HBN_F32K_SEL_MSK (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS) +#define HBN_F32K_SEL_UMSK (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)) +#define HBN_PU_RC32K HBN_PU_RC32K +#define HBN_PU_RC32K_POS (5U) +#define HBN_PU_RC32K_LEN (1U) +#define HBN_PU_RC32K_MSK (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS) +#define HBN_PU_RC32K_UMSK (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)) +#define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL +#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U) +#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U) +#define HBN_SW_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS) +#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)) +#define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL +#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U) +#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U) +#define HBN_SW_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS) +#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)) + +/* 0x34 : HBN_SRAM */ +#define HBN_SRAM_OFFSET (0x34) +#define HBN_RETRAM_RET HBN_RETRAM_RET +#define HBN_RETRAM_RET_POS (6U) +#define HBN_RETRAM_RET_LEN (1U) +#define HBN_RETRAM_RET_MSK (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS) +#define HBN_RETRAM_RET_UMSK (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)) +#define HBN_RETRAM_SLP HBN_RETRAM_SLP +#define HBN_RETRAM_SLP_POS (7U) +#define HBN_RETRAM_SLP_LEN (1U) +#define HBN_RETRAM_SLP_MSK (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS) +#define HBN_RETRAM_SLP_UMSK (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)) + +/* 0x100 : HBN_RSV0 */ +#define HBN_RSV0_OFFSET (0x100) +#define HBN_RSV0 HBN_RSV0 +#define HBN_RSV0_POS (0U) +#define HBN_RSV0_LEN (32U) +#define HBN_RSV0_MSK (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS) +#define HBN_RSV0_UMSK (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)) + +/* 0x104 : HBN_RSV1 */ +#define HBN_RSV1_OFFSET (0x104) +#define HBN_RSV1 HBN_RSV1 +#define HBN_RSV1_POS (0U) +#define HBN_RSV1_LEN (32U) +#define HBN_RSV1_MSK (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS) +#define HBN_RSV1_UMSK (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)) + +/* 0x108 : HBN_RSV2 */ +#define HBN_RSV2_OFFSET (0x108) +#define HBN_RSV2 HBN_RSV2 +#define HBN_RSV2_POS (0U) +#define HBN_RSV2_LEN (32U) +#define HBN_RSV2_MSK (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS) +#define HBN_RSV2_UMSK (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)) + +/* 0x10C : HBN_RSV3 */ +#define HBN_RSV3_OFFSET (0x10C) +#define HBN_RSV3 HBN_RSV3 +#define HBN_RSV3_POS (0U) +#define HBN_RSV3_LEN (32U) +#define HBN_RSV3_MSK (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS) +#define HBN_RSV3_UMSK (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)) + +/* 0x200 : rc32k_ctrl0 */ +#define HBN_RC32K_CTRL0_OFFSET (0x200) +#define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE +#define HBN_RC32K_CAL_DONE_POS (0U) +#define HBN_RC32K_CAL_DONE_LEN (1U) +#define HBN_RC32K_CAL_DONE_MSK (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS) +#define HBN_RC32K_CAL_DONE_UMSK (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)) +#define HBN_RC32K_RDY HBN_RC32K_RDY +#define HBN_RC32K_RDY_POS (1U) +#define HBN_RC32K_RDY_LEN (1U) +#define HBN_RC32K_RDY_MSK (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS) +#define HBN_RC32K_RDY_UMSK (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)) +#define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS +#define HBN_RC32K_CAL_INPROGRESS_POS (2U) +#define HBN_RC32K_CAL_INPROGRESS_LEN (1U) +#define HBN_RC32K_CAL_INPROGRESS_MSK (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS) +#define HBN_RC32K_CAL_INPROGRESS_UMSK (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)) +#define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV +#define HBN_RC32K_CAL_DIV_POS (3U) +#define HBN_RC32K_CAL_DIV_LEN (2U) +#define HBN_RC32K_CAL_DIV_MSK (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS) +#define HBN_RC32K_CAL_DIV_UMSK (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)) +#define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE +#define HBN_RC32K_CAL_PRECHARGE_POS (5U) +#define HBN_RC32K_CAL_PRECHARGE_LEN (1U) +#define HBN_RC32K_CAL_PRECHARGE_MSK (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS) +#define HBN_RC32K_CAL_PRECHARGE_UMSK (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)) +#define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL +#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U) +#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U) +#define HBN_RC32K_DIG_CODE_FR_CAL_MSK (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS) +#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)) +#define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY +#define HBN_RC32K_VREF_DLY_POS (16U) +#define HBN_RC32K_VREF_DLY_LEN (2U) +#define HBN_RC32K_VREF_DLY_MSK (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS) +#define HBN_RC32K_VREF_DLY_UMSK (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)) +#define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL +#define HBN_RC32K_ALLOW_CAL_POS (18U) +#define HBN_RC32K_ALLOW_CAL_LEN (1U) +#define HBN_RC32K_ALLOW_CAL_MSK (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS) +#define HBN_RC32K_ALLOW_CAL_UMSK (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)) +#define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN +#define HBN_RC32K_EXT_CODE_EN_POS (19U) +#define HBN_RC32K_EXT_CODE_EN_LEN (1U) +#define HBN_RC32K_EXT_CODE_EN_MSK (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS) +#define HBN_RC32K_EXT_CODE_EN_UMSK (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)) +#define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN +#define HBN_RC32K_CAL_EN_POS (20U) +#define HBN_RC32K_CAL_EN_LEN (1U) +#define HBN_RC32K_CAL_EN_MSK (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS) +#define HBN_RC32K_CAL_EN_UMSK (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)) +#define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT +#define HBN_RC32K_CODE_FR_EXT_POS (22U) +#define HBN_RC32K_CODE_FR_EXT_LEN (10U) +#define HBN_RC32K_CODE_FR_EXT_MSK (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS) +#define HBN_RC32K_CODE_FR_EXT_UMSK (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)) + +/* 0x204 : xtal32k */ +#define HBN_XTAL32K_OFFSET (0x204) +#define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL +#define HBN_XTAL32K_EXT_SEL_POS (2U) +#define HBN_XTAL32K_EXT_SEL_LEN (1U) +#define HBN_XTAL32K_EXT_SEL_MSK (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS) +#define HBN_XTAL32K_EXT_SEL_UMSK (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)) +#define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL +#define HBN_XTAL32K_AMP_CTRL_POS (3U) +#define HBN_XTAL32K_AMP_CTRL_LEN (2U) +#define HBN_XTAL32K_AMP_CTRL_MSK (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS) +#define HBN_XTAL32K_AMP_CTRL_UMSK (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)) +#define HBN_XTAL32K_REG HBN_XTAL32K_REG +#define HBN_XTAL32K_REG_POS (5U) +#define HBN_XTAL32K_REG_LEN (2U) +#define HBN_XTAL32K_REG_MSK (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS) +#define HBN_XTAL32K_REG_UMSK (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)) +#define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE +#define HBN_XTAL32K_OUTBUF_STRE_POS (7U) +#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U) +#define HBN_XTAL32K_OUTBUF_STRE_MSK (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS) +#define HBN_XTAL32K_OUTBUF_STRE_UMSK (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)) +#define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT +#define HBN_XTAL32K_OTF_SHORT_POS (8U) +#define HBN_XTAL32K_OTF_SHORT_LEN (1U) +#define HBN_XTAL32K_OTF_SHORT_MSK (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS) +#define HBN_XTAL32K_OTF_SHORT_UMSK (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)) +#define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE +#define HBN_XTAL32K_INV_STRE_POS (9U) +#define HBN_XTAL32K_INV_STRE_LEN (2U) +#define HBN_XTAL32K_INV_STRE_MSK (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS) +#define HBN_XTAL32K_INV_STRE_UMSK (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)) +#define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK +#define HBN_XTAL32K_CAPBANK_POS (11U) +#define HBN_XTAL32K_CAPBANK_LEN (6U) +#define HBN_XTAL32K_CAPBANK_MSK (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS) +#define HBN_XTAL32K_CAPBANK_UMSK (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)) +#define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT +#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U) +#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U) +#define HBN_XTAL32K_AC_CAP_SHORT_MSK (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS) +#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)) +#define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF +#define HBN_PU_XTAL32K_BUF_POS (18U) +#define HBN_PU_XTAL32K_BUF_LEN (1U) +#define HBN_PU_XTAL32K_BUF_MSK (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS) +#define HBN_PU_XTAL32K_BUF_UMSK (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)) +#define HBN_PU_XTAL32K HBN_PU_XTAL32K +#define HBN_PU_XTAL32K_POS (19U) +#define HBN_PU_XTAL32K_LEN (1U) +#define HBN_PU_XTAL32K_MSK (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS) +#define HBN_PU_XTAL32K_UMSK (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)) + +struct hbn_reg { + /* 0x0 : HBN_CTL */ + union { + struct + { + uint32_t rtc_ctl : 7; /* [ 6: 0], r/w, 0x0 */ + uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */ + uint32_t trap_mode : 1; /* [ 8], r, 0x0 */ + uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ + uint32_t pwrdn_hbn_rtc : 1; /* [ 11], r/w, 0x0 */ + uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */ + uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */ + uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */ + uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */ + uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */ + uint32_t pu_dcdc18_aon : 1; /* [ 23], r/w, 0x1 */ + uint32_t rtc_dly_option : 1; /* [ 24], r/w, 0x0 */ + uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */ + uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */ + uint32_t sram_slp : 1; /* [ 27], r, 0x0 */ + uint32_t hbn_state : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } HBN_CTL; + + /* 0x4 : HBN_TIME_L */ + union { + struct + { + uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_TIME_L; + + /* 0x8 : HBN_TIME_H */ + union { + struct + { + uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_TIME_H; + + /* 0xC : RTC_TIME_L */ + union { + struct + { + uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } RTC_TIME_L; + + /* 0x10 : RTC_TIME_H */ + union { + struct + { + uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */ + uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */ + } BF; + uint32_t WORD; + } RTC_TIME_H; + + /* 0x14 : HBN_IRQ_MODE */ + union { + struct + { + uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0], r/w, 0x5 */ + uint32_t hbn_pin_wakeup_mask : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t reg_aon_pad_ie_smt : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ + uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */ + uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */ + uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */ + uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_MODE; + + /* 0x18 : HBN_IRQ_STAT */ + union { + struct + { + uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_STAT; + + /* 0x1C : HBN_IRQ_CLR */ + union { + struct + { + uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_CLR; + + /* 0x20 : HBN_PIR_CFG */ + union { + struct + { + uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpadc_cgen : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpadc_nosync : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_CFG; + + /* 0x24 : HBN_PIR_VTH */ + union { + struct + { + uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */ + uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_VTH; + + /* 0x28 : HBN_PIR_INTERVAL */ + union { + struct + { + uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_INTERVAL; + + /* 0x2C : HBN_BOR_CFG */ + union { + struct + { + uint32_t bor_sel : 1; /* [ 0], r/w, 0x0 */ + uint32_t bor_vth : 1; /* [ 1], r/w, 0x1 */ + uint32_t pu_bor : 1; /* [ 2], r/w, 0x0 */ + uint32_t r_bor_out : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_BOR_CFG; + + /* 0x30 : HBN_GLB */ + union { + struct + { + uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t hbn_pu_rc32k : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */ + uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */ + } BF; + uint32_t WORD; + } HBN_GLB; + + /* 0x34 : HBN_SRAM */ + union { + struct + { + uint32_t reserved_0_5 : 6; /* [ 5: 0], rsvd, 0x0 */ + uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */ + uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_SRAM; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[200]; + + /* 0x100 : HBN_RSV0 */ + union { + struct + { + uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_RSV0; + + /* 0x104 : HBN_RSV1 */ + union { + struct + { + uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } HBN_RSV1; + + /* 0x108 : HBN_RSV2 */ + union { + struct + { + uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_RSV2; + + /* 0x10C : HBN_RSV3 */ + union { + struct + { + uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } HBN_RSV3; + + /* 0x110 reserved */ + uint8_t RESERVED0x110[240]; + + /* 0x200 : rc32k_ctrl0 */ + union { + struct + { + uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */ + uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */ + uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */ + uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */ + uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */ + uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */ + uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */ + uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */ + uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */ + uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */ + uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x140 */ + } BF; + uint32_t WORD; + } rc32k_ctrl0; + + /* 0x204 : xtal32k */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */ + uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */ + uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */ + uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */ + uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */ + uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */ + uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x1 */ + uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */ + uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x1 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } xtal32k; +}; + +typedef volatile struct hbn_reg hbn_reg_t; + +#endif /* __HBN_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/i2c_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/i2c_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..31bd014fb2019016482878217e192bb1e0d9fbd1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/i2c_reg.h @@ -0,0 +1,557 @@ +/** + ****************************************************************************** + * @file i2c_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +#include "bl602.h" + +/* 0x0 : i2c_config */ +#define I2C_CONFIG_OFFSET (0x0) +#define I2C_CR_I2C_M_EN I2C_CR_I2C_M_EN +#define I2C_CR_I2C_M_EN_POS (0U) +#define I2C_CR_I2C_M_EN_LEN (1U) +#define I2C_CR_I2C_M_EN_MSK (((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS) +#define I2C_CR_I2C_M_EN_UMSK (~(((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS)) +#define I2C_CR_I2C_PKT_DIR I2C_CR_I2C_PKT_DIR +#define I2C_CR_I2C_PKT_DIR_POS (1U) +#define I2C_CR_I2C_PKT_DIR_LEN (1U) +#define I2C_CR_I2C_PKT_DIR_MSK (((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS) +#define I2C_CR_I2C_PKT_DIR_UMSK (~(((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS)) +#define I2C_CR_I2C_DEG_EN I2C_CR_I2C_DEG_EN +#define I2C_CR_I2C_DEG_EN_POS (2U) +#define I2C_CR_I2C_DEG_EN_LEN (1U) +#define I2C_CR_I2C_DEG_EN_MSK (((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS) +#define I2C_CR_I2C_DEG_EN_UMSK (~(((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS)) +#define I2C_CR_I2C_SCL_SYNC_EN I2C_CR_I2C_SCL_SYNC_EN +#define I2C_CR_I2C_SCL_SYNC_EN_POS (3U) +#define I2C_CR_I2C_SCL_SYNC_EN_LEN (1U) +#define I2C_CR_I2C_SCL_SYNC_EN_MSK (((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS) +#define I2C_CR_I2C_SCL_SYNC_EN_UMSK (~(((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS)) +#define I2C_CR_I2C_SUB_ADDR_EN I2C_CR_I2C_SUB_ADDR_EN +#define I2C_CR_I2C_SUB_ADDR_EN_POS (4U) +#define I2C_CR_I2C_SUB_ADDR_EN_LEN (1U) +#define I2C_CR_I2C_SUB_ADDR_EN_MSK (((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS) +#define I2C_CR_I2C_SUB_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS)) +#define I2C_CR_I2C_SUB_ADDR_BC I2C_CR_I2C_SUB_ADDR_BC +#define I2C_CR_I2C_SUB_ADDR_BC_POS (5U) +#define I2C_CR_I2C_SUB_ADDR_BC_LEN (2U) +#define I2C_CR_I2C_SUB_ADDR_BC_MSK (((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS) +#define I2C_CR_I2C_SUB_ADDR_BC_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS)) +#define I2C_CR_I2C_SLV_ADDR I2C_CR_I2C_SLV_ADDR +#define I2C_CR_I2C_SLV_ADDR_POS (8U) +#define I2C_CR_I2C_SLV_ADDR_LEN (7U) +#define I2C_CR_I2C_SLV_ADDR_MSK (((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS) +#define I2C_CR_I2C_SLV_ADDR_UMSK (~(((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS)) +#define I2C_CR_I2C_PKT_LEN I2C_CR_I2C_PKT_LEN +#define I2C_CR_I2C_PKT_LEN_POS (16U) +#define I2C_CR_I2C_PKT_LEN_LEN (8U) +#define I2C_CR_I2C_PKT_LEN_MSK (((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS) +#define I2C_CR_I2C_PKT_LEN_UMSK (~(((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS)) +#define I2C_CR_I2C_DEG_CNT I2C_CR_I2C_DEG_CNT +#define I2C_CR_I2C_DEG_CNT_POS (28U) +#define I2C_CR_I2C_DEG_CNT_LEN (4U) +#define I2C_CR_I2C_DEG_CNT_MSK (((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS) +#define I2C_CR_I2C_DEG_CNT_UMSK (~(((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS)) + +/* 0x4 : i2c_int_sts */ +#define I2C_INT_STS_OFFSET (0x4) +#define I2C_END_INT I2C_END_INT +#define I2C_END_INT_POS (0U) +#define I2C_END_INT_LEN (1U) +#define I2C_END_INT_MSK (((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS) +#define I2C_END_INT_UMSK (~(((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS)) +#define I2C_TXF_INT I2C_TXF_INT +#define I2C_TXF_INT_POS (1U) +#define I2C_TXF_INT_LEN (1U) +#define I2C_TXF_INT_MSK (((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS) +#define I2C_TXF_INT_UMSK (~(((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS)) +#define I2C_RXF_INT I2C_RXF_INT +#define I2C_RXF_INT_POS (2U) +#define I2C_RXF_INT_LEN (1U) +#define I2C_RXF_INT_MSK (((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS) +#define I2C_RXF_INT_UMSK (~(((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS)) +#define I2C_NAK_INT I2C_NAK_INT +#define I2C_NAK_INT_POS (3U) +#define I2C_NAK_INT_LEN (1U) +#define I2C_NAK_INT_MSK (((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS) +#define I2C_NAK_INT_UMSK (~(((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS)) +#define I2C_ARB_INT I2C_ARB_INT +#define I2C_ARB_INT_POS (4U) +#define I2C_ARB_INT_LEN (1U) +#define I2C_ARB_INT_MSK (((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS) +#define I2C_ARB_INT_UMSK (~(((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS)) +#define I2C_FER_INT I2C_FER_INT +#define I2C_FER_INT_POS (5U) +#define I2C_FER_INT_LEN (1U) +#define I2C_FER_INT_MSK (((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS) +#define I2C_FER_INT_UMSK (~(((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS)) +#define I2C_CR_I2C_END_MASK I2C_CR_I2C_END_MASK +#define I2C_CR_I2C_END_MASK_POS (8U) +#define I2C_CR_I2C_END_MASK_LEN (1U) +#define I2C_CR_I2C_END_MASK_MSK (((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS) +#define I2C_CR_I2C_END_MASK_UMSK (~(((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS)) +#define I2C_CR_I2C_TXF_MASK I2C_CR_I2C_TXF_MASK +#define I2C_CR_I2C_TXF_MASK_POS (9U) +#define I2C_CR_I2C_TXF_MASK_LEN (1U) +#define I2C_CR_I2C_TXF_MASK_MSK (((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS) +#define I2C_CR_I2C_TXF_MASK_UMSK (~(((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS)) +#define I2C_CR_I2C_RXF_MASK I2C_CR_I2C_RXF_MASK +#define I2C_CR_I2C_RXF_MASK_POS (10U) +#define I2C_CR_I2C_RXF_MASK_LEN (1U) +#define I2C_CR_I2C_RXF_MASK_MSK (((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS) +#define I2C_CR_I2C_RXF_MASK_UMSK (~(((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS)) +#define I2C_CR_I2C_NAK_MASK I2C_CR_I2C_NAK_MASK +#define I2C_CR_I2C_NAK_MASK_POS (11U) +#define I2C_CR_I2C_NAK_MASK_LEN (1U) +#define I2C_CR_I2C_NAK_MASK_MSK (((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS) +#define I2C_CR_I2C_NAK_MASK_UMSK (~(((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS)) +#define I2C_CR_I2C_ARB_MASK I2C_CR_I2C_ARB_MASK +#define I2C_CR_I2C_ARB_MASK_POS (12U) +#define I2C_CR_I2C_ARB_MASK_LEN (1U) +#define I2C_CR_I2C_ARB_MASK_MSK (((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS) +#define I2C_CR_I2C_ARB_MASK_UMSK (~(((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS)) +#define I2C_CR_I2C_FER_MASK I2C_CR_I2C_FER_MASK +#define I2C_CR_I2C_FER_MASK_POS (13U) +#define I2C_CR_I2C_FER_MASK_LEN (1U) +#define I2C_CR_I2C_FER_MASK_MSK (((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS) +#define I2C_CR_I2C_FER_MASK_UMSK (~(((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS)) +#define I2C_CR_I2C_END_CLR I2C_CR_I2C_END_CLR +#define I2C_CR_I2C_END_CLR_POS (16U) +#define I2C_CR_I2C_END_CLR_LEN (1U) +#define I2C_CR_I2C_END_CLR_MSK (((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS) +#define I2C_CR_I2C_END_CLR_UMSK (~(((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS)) +#define I2C_CR_I2C_NAK_CLR I2C_CR_I2C_NAK_CLR +#define I2C_CR_I2C_NAK_CLR_POS (19U) +#define I2C_CR_I2C_NAK_CLR_LEN (1U) +#define I2C_CR_I2C_NAK_CLR_MSK (((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS) +#define I2C_CR_I2C_NAK_CLR_UMSK (~(((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS)) +#define I2C_CR_I2C_ARB_CLR I2C_CR_I2C_ARB_CLR +#define I2C_CR_I2C_ARB_CLR_POS (20U) +#define I2C_CR_I2C_ARB_CLR_LEN (1U) +#define I2C_CR_I2C_ARB_CLR_MSK (((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS) +#define I2C_CR_I2C_ARB_CLR_UMSK (~(((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS)) +#define I2C_CR_I2C_END_EN I2C_CR_I2C_END_EN +#define I2C_CR_I2C_END_EN_POS (24U) +#define I2C_CR_I2C_END_EN_LEN (1U) +#define I2C_CR_I2C_END_EN_MSK (((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS) +#define I2C_CR_I2C_END_EN_UMSK (~(((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS)) +#define I2C_CR_I2C_TXF_EN I2C_CR_I2C_TXF_EN +#define I2C_CR_I2C_TXF_EN_POS (25U) +#define I2C_CR_I2C_TXF_EN_LEN (1U) +#define I2C_CR_I2C_TXF_EN_MSK (((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS) +#define I2C_CR_I2C_TXF_EN_UMSK (~(((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS)) +#define I2C_CR_I2C_RXF_EN I2C_CR_I2C_RXF_EN +#define I2C_CR_I2C_RXF_EN_POS (26U) +#define I2C_CR_I2C_RXF_EN_LEN (1U) +#define I2C_CR_I2C_RXF_EN_MSK (((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS) +#define I2C_CR_I2C_RXF_EN_UMSK (~(((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS)) +#define I2C_CR_I2C_NAK_EN I2C_CR_I2C_NAK_EN +#define I2C_CR_I2C_NAK_EN_POS (27U) +#define I2C_CR_I2C_NAK_EN_LEN (1U) +#define I2C_CR_I2C_NAK_EN_MSK (((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS) +#define I2C_CR_I2C_NAK_EN_UMSK (~(((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS)) +#define I2C_CR_I2C_ARB_EN I2C_CR_I2C_ARB_EN +#define I2C_CR_I2C_ARB_EN_POS (28U) +#define I2C_CR_I2C_ARB_EN_LEN (1U) +#define I2C_CR_I2C_ARB_EN_MSK (((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS) +#define I2C_CR_I2C_ARB_EN_UMSK (~(((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS)) +#define I2C_CR_I2C_FER_EN I2C_CR_I2C_FER_EN +#define I2C_CR_I2C_FER_EN_POS (29U) +#define I2C_CR_I2C_FER_EN_LEN (1U) +#define I2C_CR_I2C_FER_EN_MSK (((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS) +#define I2C_CR_I2C_FER_EN_UMSK (~(((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS)) + +/* 0x8 : i2c_sub_addr */ +#define I2C_SUB_ADDR_OFFSET (0x8) +#define I2C_CR_I2C_SUB_ADDR_B0 I2C_CR_I2C_SUB_ADDR_B0 +#define I2C_CR_I2C_SUB_ADDR_B0_POS (0U) +#define I2C_CR_I2C_SUB_ADDR_B0_LEN (8U) +#define I2C_CR_I2C_SUB_ADDR_B0_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS) +#define I2C_CR_I2C_SUB_ADDR_B0_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS)) +#define I2C_CR_I2C_SUB_ADDR_B1 I2C_CR_I2C_SUB_ADDR_B1 +#define I2C_CR_I2C_SUB_ADDR_B1_POS (8U) +#define I2C_CR_I2C_SUB_ADDR_B1_LEN (8U) +#define I2C_CR_I2C_SUB_ADDR_B1_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS) +#define I2C_CR_I2C_SUB_ADDR_B1_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS)) +#define I2C_CR_I2C_SUB_ADDR_B2 I2C_CR_I2C_SUB_ADDR_B2 +#define I2C_CR_I2C_SUB_ADDR_B2_POS (16U) +#define I2C_CR_I2C_SUB_ADDR_B2_LEN (8U) +#define I2C_CR_I2C_SUB_ADDR_B2_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS) +#define I2C_CR_I2C_SUB_ADDR_B2_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS)) +#define I2C_CR_I2C_SUB_ADDR_B3 I2C_CR_I2C_SUB_ADDR_B3 +#define I2C_CR_I2C_SUB_ADDR_B3_POS (24U) +#define I2C_CR_I2C_SUB_ADDR_B3_LEN (8U) +#define I2C_CR_I2C_SUB_ADDR_B3_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS) +#define I2C_CR_I2C_SUB_ADDR_B3_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS)) + +/* 0xC : i2c_bus_busy */ +#define I2C_BUS_BUSY_OFFSET (0xC) +#define I2C_STS_I2C_BUS_BUSY I2C_STS_I2C_BUS_BUSY +#define I2C_STS_I2C_BUS_BUSY_POS (0U) +#define I2C_STS_I2C_BUS_BUSY_LEN (1U) +#define I2C_STS_I2C_BUS_BUSY_MSK (((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS) +#define I2C_STS_I2C_BUS_BUSY_UMSK (~(((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS)) +#define I2C_CR_I2C_BUS_BUSY_CLR I2C_CR_I2C_BUS_BUSY_CLR +#define I2C_CR_I2C_BUS_BUSY_CLR_POS (1U) +#define I2C_CR_I2C_BUS_BUSY_CLR_LEN (1U) +#define I2C_CR_I2C_BUS_BUSY_CLR_MSK (((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS) +#define I2C_CR_I2C_BUS_BUSY_CLR_UMSK (~(((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS)) + +/* 0x10 : i2c_prd_start */ +#define I2C_PRD_START_OFFSET (0x10) +#define I2C_CR_I2C_PRD_S_PH_0 I2C_CR_I2C_PRD_S_PH_0 +#define I2C_CR_I2C_PRD_S_PH_0_POS (0U) +#define I2C_CR_I2C_PRD_S_PH_0_LEN (8U) +#define I2C_CR_I2C_PRD_S_PH_0_MSK (((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS) +#define I2C_CR_I2C_PRD_S_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS)) +#define I2C_CR_I2C_PRD_S_PH_1 I2C_CR_I2C_PRD_S_PH_1 +#define I2C_CR_I2C_PRD_S_PH_1_POS (8U) +#define I2C_CR_I2C_PRD_S_PH_1_LEN (8U) +#define I2C_CR_I2C_PRD_S_PH_1_MSK (((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS) +#define I2C_CR_I2C_PRD_S_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS)) +#define I2C_CR_I2C_PRD_S_PH_2 I2C_CR_I2C_PRD_S_PH_2 +#define I2C_CR_I2C_PRD_S_PH_2_POS (16U) +#define I2C_CR_I2C_PRD_S_PH_2_LEN (8U) +#define I2C_CR_I2C_PRD_S_PH_2_MSK (((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS) +#define I2C_CR_I2C_PRD_S_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS)) +#define I2C_CR_I2C_PRD_S_PH_3 I2C_CR_I2C_PRD_S_PH_3 +#define I2C_CR_I2C_PRD_S_PH_3_POS (24U) +#define I2C_CR_I2C_PRD_S_PH_3_LEN (8U) +#define I2C_CR_I2C_PRD_S_PH_3_MSK (((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS) +#define I2C_CR_I2C_PRD_S_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS)) + +/* 0x14 : i2c_prd_stop */ +#define I2C_PRD_STOP_OFFSET (0x14) +#define I2C_CR_I2C_PRD_P_PH_0 I2C_CR_I2C_PRD_P_PH_0 +#define I2C_CR_I2C_PRD_P_PH_0_POS (0U) +#define I2C_CR_I2C_PRD_P_PH_0_LEN (8U) +#define I2C_CR_I2C_PRD_P_PH_0_MSK (((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS) +#define I2C_CR_I2C_PRD_P_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS)) +#define I2C_CR_I2C_PRD_P_PH_1 I2C_CR_I2C_PRD_P_PH_1 +#define I2C_CR_I2C_PRD_P_PH_1_POS (8U) +#define I2C_CR_I2C_PRD_P_PH_1_LEN (8U) +#define I2C_CR_I2C_PRD_P_PH_1_MSK (((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS) +#define I2C_CR_I2C_PRD_P_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS)) +#define I2C_CR_I2C_PRD_P_PH_2 I2C_CR_I2C_PRD_P_PH_2 +#define I2C_CR_I2C_PRD_P_PH_2_POS (16U) +#define I2C_CR_I2C_PRD_P_PH_2_LEN (8U) +#define I2C_CR_I2C_PRD_P_PH_2_MSK (((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS) +#define I2C_CR_I2C_PRD_P_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS)) +#define I2C_CR_I2C_PRD_P_PH_3 I2C_CR_I2C_PRD_P_PH_3 +#define I2C_CR_I2C_PRD_P_PH_3_POS (24U) +#define I2C_CR_I2C_PRD_P_PH_3_LEN (8U) +#define I2C_CR_I2C_PRD_P_PH_3_MSK (((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS) +#define I2C_CR_I2C_PRD_P_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS)) + +/* 0x18 : i2c_prd_data */ +#define I2C_PRD_DATA_OFFSET (0x18) +#define I2C_CR_I2C_PRD_D_PH_0 I2C_CR_I2C_PRD_D_PH_0 +#define I2C_CR_I2C_PRD_D_PH_0_POS (0U) +#define I2C_CR_I2C_PRD_D_PH_0_LEN (8U) +#define I2C_CR_I2C_PRD_D_PH_0_MSK (((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS) +#define I2C_CR_I2C_PRD_D_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS)) +#define I2C_CR_I2C_PRD_D_PH_1 I2C_CR_I2C_PRD_D_PH_1 +#define I2C_CR_I2C_PRD_D_PH_1_POS (8U) +#define I2C_CR_I2C_PRD_D_PH_1_LEN (8U) +#define I2C_CR_I2C_PRD_D_PH_1_MSK (((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS) +#define I2C_CR_I2C_PRD_D_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS)) +#define I2C_CR_I2C_PRD_D_PH_2 I2C_CR_I2C_PRD_D_PH_2 +#define I2C_CR_I2C_PRD_D_PH_2_POS (16U) +#define I2C_CR_I2C_PRD_D_PH_2_LEN (8U) +#define I2C_CR_I2C_PRD_D_PH_2_MSK (((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS) +#define I2C_CR_I2C_PRD_D_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS)) +#define I2C_CR_I2C_PRD_D_PH_3 I2C_CR_I2C_PRD_D_PH_3 +#define I2C_CR_I2C_PRD_D_PH_3_POS (24U) +#define I2C_CR_I2C_PRD_D_PH_3_LEN (8U) +#define I2C_CR_I2C_PRD_D_PH_3_MSK (((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS) +#define I2C_CR_I2C_PRD_D_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS)) + +/* 0x80 : i2c_fifo_config_0 */ +#define I2C_FIFO_CONFIG_0_OFFSET (0x80) +#define I2C_DMA_TX_EN I2C_DMA_TX_EN +#define I2C_DMA_TX_EN_POS (0U) +#define I2C_DMA_TX_EN_LEN (1U) +#define I2C_DMA_TX_EN_MSK (((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS) +#define I2C_DMA_TX_EN_UMSK (~(((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS)) +#define I2C_DMA_RX_EN I2C_DMA_RX_EN +#define I2C_DMA_RX_EN_POS (1U) +#define I2C_DMA_RX_EN_LEN (1U) +#define I2C_DMA_RX_EN_MSK (((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS) +#define I2C_DMA_RX_EN_UMSK (~(((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS)) +#define I2C_TX_FIFO_CLR I2C_TX_FIFO_CLR +#define I2C_TX_FIFO_CLR_POS (2U) +#define I2C_TX_FIFO_CLR_LEN (1U) +#define I2C_TX_FIFO_CLR_MSK (((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS) +#define I2C_TX_FIFO_CLR_UMSK (~(((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS)) +#define I2C_RX_FIFO_CLR I2C_RX_FIFO_CLR +#define I2C_RX_FIFO_CLR_POS (3U) +#define I2C_RX_FIFO_CLR_LEN (1U) +#define I2C_RX_FIFO_CLR_MSK (((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS) +#define I2C_RX_FIFO_CLR_UMSK (~(((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS)) +#define I2C_TX_FIFO_OVERFLOW I2C_TX_FIFO_OVERFLOW +#define I2C_TX_FIFO_OVERFLOW_POS (4U) +#define I2C_TX_FIFO_OVERFLOW_LEN (1U) +#define I2C_TX_FIFO_OVERFLOW_MSK (((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS) +#define I2C_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS)) +#define I2C_TX_FIFO_UNDERFLOW I2C_TX_FIFO_UNDERFLOW +#define I2C_TX_FIFO_UNDERFLOW_POS (5U) +#define I2C_TX_FIFO_UNDERFLOW_LEN (1U) +#define I2C_TX_FIFO_UNDERFLOW_MSK (((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS) +#define I2C_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS)) +#define I2C_RX_FIFO_OVERFLOW I2C_RX_FIFO_OVERFLOW +#define I2C_RX_FIFO_OVERFLOW_POS (6U) +#define I2C_RX_FIFO_OVERFLOW_LEN (1U) +#define I2C_RX_FIFO_OVERFLOW_MSK (((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS) +#define I2C_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS)) +#define I2C_RX_FIFO_UNDERFLOW I2C_RX_FIFO_UNDERFLOW +#define I2C_RX_FIFO_UNDERFLOW_POS (7U) +#define I2C_RX_FIFO_UNDERFLOW_LEN (1U) +#define I2C_RX_FIFO_UNDERFLOW_MSK (((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS) +#define I2C_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS)) + +/* 0x84 : i2c_fifo_config_1 */ +#define I2C_FIFO_CONFIG_1_OFFSET (0x84) +#define I2C_TX_FIFO_CNT I2C_TX_FIFO_CNT +#define I2C_TX_FIFO_CNT_POS (0U) +#define I2C_TX_FIFO_CNT_LEN (2U) +#define I2C_TX_FIFO_CNT_MSK (((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS) +#define I2C_TX_FIFO_CNT_UMSK (~(((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS)) +#define I2C_RX_FIFO_CNT I2C_RX_FIFO_CNT +#define I2C_RX_FIFO_CNT_POS (8U) +#define I2C_RX_FIFO_CNT_LEN (2U) +#define I2C_RX_FIFO_CNT_MSK (((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS) +#define I2C_RX_FIFO_CNT_UMSK (~(((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS)) +#define I2C_TX_FIFO_TH I2C_TX_FIFO_TH +#define I2C_TX_FIFO_TH_POS (16U) +#define I2C_TX_FIFO_TH_LEN (1U) +#define I2C_TX_FIFO_TH_MSK (((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS) +#define I2C_TX_FIFO_TH_UMSK (~(((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS)) +#define I2C_RX_FIFO_TH I2C_RX_FIFO_TH +#define I2C_RX_FIFO_TH_POS (24U) +#define I2C_RX_FIFO_TH_LEN (1U) +#define I2C_RX_FIFO_TH_MSK (((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS) +#define I2C_RX_FIFO_TH_UMSK (~(((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS)) + +/* 0x88 : i2c_fifo_wdata */ +#define I2C_FIFO_WDATA_OFFSET (0x88) +#define I2C_FIFO_WDATA I2C_FIFO_WDATA +#define I2C_FIFO_WDATA_POS (0U) +#define I2C_FIFO_WDATA_LEN (32U) +#define I2C_FIFO_WDATA_MSK (((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS) +#define I2C_FIFO_WDATA_UMSK (~(((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS)) + +/* 0x8C : i2c_fifo_rdata */ +#define I2C_FIFO_RDATA_OFFSET (0x8C) +#define I2C_FIFO_RDATA I2C_FIFO_RDATA +#define I2C_FIFO_RDATA_POS (0U) +#define I2C_FIFO_RDATA_LEN (32U) +#define I2C_FIFO_RDATA_MSK (((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS) +#define I2C_FIFO_RDATA_UMSK (~(((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS)) + +struct i2c_reg { + /* 0x0 : i2c_config */ + union { + struct + { + uint32_t cr_i2c_m_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_i2c_pkt_dir : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_i2c_deg_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_i2c_scl_sync_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t cr_i2c_sub_addr_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_i2c_sub_addr_bc : 2; /* [ 6: 5], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cr_i2c_slv_addr : 7; /* [14: 8], r/w, 0x0 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t cr_i2c_pkt_len : 8; /* [23:16], r/w, 0x0 */ + uint32_t reserved_24_27 : 4; /* [27:24], rsvd, 0x0 */ + uint32_t cr_i2c_deg_cnt : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } i2c_config; + + /* 0x4 : i2c_int_sts */ + union { + struct + { + uint32_t i2c_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t i2c_txf_int : 1; /* [ 1], r, 0x0 */ + uint32_t i2c_rxf_int : 1; /* [ 2], r, 0x0 */ + uint32_t i2c_nak_int : 1; /* [ 3], r, 0x0 */ + uint32_t i2c_arb_int : 1; /* [ 4], r, 0x0 */ + uint32_t i2c_fer_int : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t cr_i2c_end_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_i2c_txf_mask : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_i2c_rxf_mask : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_i2c_nak_mask : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_i2c_arb_mask : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_i2c_fer_mask : 1; /* [ 13], r/w, 0x1 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t cr_i2c_end_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t cr_i2c_nak_clr : 1; /* [ 19], w1c, 0x0 */ + uint32_t cr_i2c_arb_clr : 1; /* [ 20], w1c, 0x0 */ + uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t cr_i2c_end_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t cr_i2c_txf_en : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_i2c_rxf_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t cr_i2c_nak_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t cr_i2c_arb_en : 1; /* [ 28], r/w, 0x1 */ + uint32_t cr_i2c_fer_en : 1; /* [ 29], r/w, 0x1 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2c_int_sts; + + /* 0x8 : i2c_sub_addr */ + union { + struct + { + uint32_t cr_i2c_sub_addr_b0 : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t cr_i2c_sub_addr_b1 : 8; /* [15: 8], r/w, 0x0 */ + uint32_t cr_i2c_sub_addr_b2 : 8; /* [23:16], r/w, 0x0 */ + uint32_t cr_i2c_sub_addr_b3 : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } i2c_sub_addr; + + /* 0xC : i2c_bus_busy */ + union { + struct + { + uint32_t sts_i2c_bus_busy : 1; /* [ 0], r, 0x0 */ + uint32_t cr_i2c_bus_busy_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2c_bus_busy; + + /* 0x10 : i2c_prd_start */ + union { + struct + { + uint32_t cr_i2c_prd_s_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t cr_i2c_prd_s_ph_1 : 8; /* [15: 8], r/w, 0xf */ + uint32_t cr_i2c_prd_s_ph_2 : 8; /* [23:16], r/w, 0xf */ + uint32_t cr_i2c_prd_s_ph_3 : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } i2c_prd_start; + + /* 0x14 : i2c_prd_stop */ + union { + struct + { + uint32_t cr_i2c_prd_p_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t cr_i2c_prd_p_ph_1 : 8; /* [15: 8], r/w, 0xf */ + uint32_t cr_i2c_prd_p_ph_2 : 8; /* [23:16], r/w, 0xf */ + uint32_t cr_i2c_prd_p_ph_3 : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } i2c_prd_stop; + + /* 0x18 : i2c_prd_data */ + union { + struct + { + uint32_t cr_i2c_prd_d_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t cr_i2c_prd_d_ph_1 : 8; /* [15: 8], r/w, 0xf */ + uint32_t cr_i2c_prd_d_ph_2 : 8; /* [23:16], r/w, 0xf */ + uint32_t cr_i2c_prd_d_ph_3 : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } i2c_prd_data; + + /* 0x1c reserved */ + uint8_t RESERVED0x1c[100]; + + /* 0x80 : i2c_fifo_config_0 */ + union { + struct + { + uint32_t i2c_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t i2c_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2c_fifo_config_0; + + /* 0x84 : i2c_fifo_config_1 */ + union { + struct + { + uint32_t tx_fifo_cnt : 2; /* [ 1: 0], r, 0x2 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t rx_fifo_cnt : 2; /* [ 9: 8], r, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t tx_fifo_th : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ + uint32_t rx_fifo_th : 1; /* [ 24], r/w, 0x0 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2c_fifo_config_1; + + /* 0x88 : i2c_fifo_wdata */ + union { + struct + { + uint32_t i2c_fifo_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } i2c_fifo_wdata; + + /* 0x8C : i2c_fifo_rdata */ + union { + struct + { + uint32_t i2c_fifo_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } i2c_fifo_rdata; +}; + +typedef volatile struct i2c_reg i2c_reg_t; + +#endif /* __I2C_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ir_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ir_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..1e471543b72f04c80e514f744ee7972002cd77ee --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/ir_reg.h @@ -0,0 +1,652 @@ +/** + ****************************************************************************** + * @file ir_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __IR_REG_H__ +#define __IR_REG_H__ + +#include "bl602.h" + +/* 0x0 : irtx_config */ +#define IRTX_CONFIG_OFFSET (0x0) +#define IR_CR_IRTX_EN IR_CR_IRTX_EN +#define IR_CR_IRTX_EN_POS (0U) +#define IR_CR_IRTX_EN_LEN (1U) +#define IR_CR_IRTX_EN_MSK (((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS) +#define IR_CR_IRTX_EN_UMSK (~(((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS)) +#define IR_CR_IRTX_OUT_INV IR_CR_IRTX_OUT_INV +#define IR_CR_IRTX_OUT_INV_POS (1U) +#define IR_CR_IRTX_OUT_INV_LEN (1U) +#define IR_CR_IRTX_OUT_INV_MSK (((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS) +#define IR_CR_IRTX_OUT_INV_UMSK (~(((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS)) +#define IR_CR_IRTX_MOD_EN IR_CR_IRTX_MOD_EN +#define IR_CR_IRTX_MOD_EN_POS (2U) +#define IR_CR_IRTX_MOD_EN_LEN (1U) +#define IR_CR_IRTX_MOD_EN_MSK (((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS) +#define IR_CR_IRTX_MOD_EN_UMSK (~(((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS)) +#define IR_CR_IRTX_SWM_EN IR_CR_IRTX_SWM_EN +#define IR_CR_IRTX_SWM_EN_POS (3U) +#define IR_CR_IRTX_SWM_EN_LEN (1U) +#define IR_CR_IRTX_SWM_EN_MSK (((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS) +#define IR_CR_IRTX_SWM_EN_UMSK (~(((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS)) +#define IR_CR_IRTX_DATA_EN IR_CR_IRTX_DATA_EN +#define IR_CR_IRTX_DATA_EN_POS (4U) +#define IR_CR_IRTX_DATA_EN_LEN (1U) +#define IR_CR_IRTX_DATA_EN_MSK (((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS) +#define IR_CR_IRTX_DATA_EN_UMSK (~(((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS)) +#define IR_CR_IRTX_LOGIC0_HL_INV IR_CR_IRTX_LOGIC0_HL_INV +#define IR_CR_IRTX_LOGIC0_HL_INV_POS (5U) +#define IR_CR_IRTX_LOGIC0_HL_INV_LEN (1U) +#define IR_CR_IRTX_LOGIC0_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS) +#define IR_CR_IRTX_LOGIC0_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS)) +#define IR_CR_IRTX_LOGIC1_HL_INV IR_CR_IRTX_LOGIC1_HL_INV +#define IR_CR_IRTX_LOGIC1_HL_INV_POS (6U) +#define IR_CR_IRTX_LOGIC1_HL_INV_LEN (1U) +#define IR_CR_IRTX_LOGIC1_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS) +#define IR_CR_IRTX_LOGIC1_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS)) +#define IR_CR_IRTX_HEAD_EN IR_CR_IRTX_HEAD_EN +#define IR_CR_IRTX_HEAD_EN_POS (8U) +#define IR_CR_IRTX_HEAD_EN_LEN (1U) +#define IR_CR_IRTX_HEAD_EN_MSK (((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS) +#define IR_CR_IRTX_HEAD_EN_UMSK (~(((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS)) +#define IR_CR_IRTX_HEAD_HL_INV IR_CR_IRTX_HEAD_HL_INV +#define IR_CR_IRTX_HEAD_HL_INV_POS (9U) +#define IR_CR_IRTX_HEAD_HL_INV_LEN (1U) +#define IR_CR_IRTX_HEAD_HL_INV_MSK (((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS) +#define IR_CR_IRTX_HEAD_HL_INV_UMSK (~(((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS)) +#define IR_CR_IRTX_TAIL_EN IR_CR_IRTX_TAIL_EN +#define IR_CR_IRTX_TAIL_EN_POS (10U) +#define IR_CR_IRTX_TAIL_EN_LEN (1U) +#define IR_CR_IRTX_TAIL_EN_MSK (((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS) +#define IR_CR_IRTX_TAIL_EN_UMSK (~(((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS)) +#define IR_CR_IRTX_TAIL_HL_INV IR_CR_IRTX_TAIL_HL_INV +#define IR_CR_IRTX_TAIL_HL_INV_POS (11U) +#define IR_CR_IRTX_TAIL_HL_INV_LEN (1U) +#define IR_CR_IRTX_TAIL_HL_INV_MSK (((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS) +#define IR_CR_IRTX_TAIL_HL_INV_UMSK (~(((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS)) +#define IR_CR_IRTX_DATA_NUM IR_CR_IRTX_DATA_NUM +#define IR_CR_IRTX_DATA_NUM_POS (12U) +#define IR_CR_IRTX_DATA_NUM_LEN (6U) +#define IR_CR_IRTX_DATA_NUM_MSK (((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS) +#define IR_CR_IRTX_DATA_NUM_UMSK (~(((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS)) + +/* 0x4 : irtx_int_sts */ +#define IRTX_INT_STS_OFFSET (0x4) +#define IRTX_END_INT IRTX_END_INT +#define IRTX_END_INT_POS (0U) +#define IRTX_END_INT_LEN (1U) +#define IRTX_END_INT_MSK (((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS) +#define IRTX_END_INT_UMSK (~(((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS)) +#define IR_CR_IRTX_END_MASK IR_CR_IRTX_END_MASK +#define IR_CR_IRTX_END_MASK_POS (8U) +#define IR_CR_IRTX_END_MASK_LEN (1U) +#define IR_CR_IRTX_END_MASK_MSK (((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS) +#define IR_CR_IRTX_END_MASK_UMSK (~(((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS)) +#define IR_CR_IRTX_END_CLR IR_CR_IRTX_END_CLR +#define IR_CR_IRTX_END_CLR_POS (16U) +#define IR_CR_IRTX_END_CLR_LEN (1U) +#define IR_CR_IRTX_END_CLR_MSK (((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS) +#define IR_CR_IRTX_END_CLR_UMSK (~(((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS)) +#define IR_CR_IRTX_END_EN IR_CR_IRTX_END_EN +#define IR_CR_IRTX_END_EN_POS (24U) +#define IR_CR_IRTX_END_EN_LEN (1U) +#define IR_CR_IRTX_END_EN_MSK (((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS) +#define IR_CR_IRTX_END_EN_UMSK (~(((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS)) + +/* 0x8 : irtx_data_word0 */ +#define IRTX_DATA_WORD0_OFFSET (0x8) +#define IR_CR_IRTX_DATA_WORD0 IR_CR_IRTX_DATA_WORD0 +#define IR_CR_IRTX_DATA_WORD0_POS (0U) +#define IR_CR_IRTX_DATA_WORD0_LEN (32U) +#define IR_CR_IRTX_DATA_WORD0_MSK (((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS) +#define IR_CR_IRTX_DATA_WORD0_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS)) + +/* 0xC : irtx_data_word1 */ +#define IRTX_DATA_WORD1_OFFSET (0xC) +#define IR_CR_IRTX_DATA_WORD1 IR_CR_IRTX_DATA_WORD1 +#define IR_CR_IRTX_DATA_WORD1_POS (0U) +#define IR_CR_IRTX_DATA_WORD1_LEN (32U) +#define IR_CR_IRTX_DATA_WORD1_MSK (((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS) +#define IR_CR_IRTX_DATA_WORD1_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS)) + +/* 0x10 : irtx_pulse_width */ +#define IRTX_PULSE_WIDTH_OFFSET (0x10) +#define IR_CR_IRTX_PW_UNIT IR_CR_IRTX_PW_UNIT +#define IR_CR_IRTX_PW_UNIT_POS (0U) +#define IR_CR_IRTX_PW_UNIT_LEN (12U) +#define IR_CR_IRTX_PW_UNIT_MSK (((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS) +#define IR_CR_IRTX_PW_UNIT_UMSK (~(((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS)) +#define IR_CR_IRTX_MOD_PH0_W IR_CR_IRTX_MOD_PH0_W +#define IR_CR_IRTX_MOD_PH0_W_POS (16U) +#define IR_CR_IRTX_MOD_PH0_W_LEN (8U) +#define IR_CR_IRTX_MOD_PH0_W_MSK (((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS) +#define IR_CR_IRTX_MOD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS)) +#define IR_CR_IRTX_MOD_PH1_W IR_CR_IRTX_MOD_PH1_W +#define IR_CR_IRTX_MOD_PH1_W_POS (24U) +#define IR_CR_IRTX_MOD_PH1_W_LEN (8U) +#define IR_CR_IRTX_MOD_PH1_W_MSK (((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS) +#define IR_CR_IRTX_MOD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS)) + +/* 0x14 : irtx_pw */ +#define IRTX_PW_OFFSET (0x14) +#define IR_CR_IRTX_LOGIC0_PH0_W IR_CR_IRTX_LOGIC0_PH0_W +#define IR_CR_IRTX_LOGIC0_PH0_W_POS (0U) +#define IR_CR_IRTX_LOGIC0_PH0_W_LEN (4U) +#define IR_CR_IRTX_LOGIC0_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS) +#define IR_CR_IRTX_LOGIC0_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS)) +#define IR_CR_IRTX_LOGIC0_PH1_W IR_CR_IRTX_LOGIC0_PH1_W +#define IR_CR_IRTX_LOGIC0_PH1_W_POS (4U) +#define IR_CR_IRTX_LOGIC0_PH1_W_LEN (4U) +#define IR_CR_IRTX_LOGIC0_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS) +#define IR_CR_IRTX_LOGIC0_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS)) +#define IR_CR_IRTX_LOGIC1_PH0_W IR_CR_IRTX_LOGIC1_PH0_W +#define IR_CR_IRTX_LOGIC1_PH0_W_POS (8U) +#define IR_CR_IRTX_LOGIC1_PH0_W_LEN (4U) +#define IR_CR_IRTX_LOGIC1_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS) +#define IR_CR_IRTX_LOGIC1_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS)) +#define IR_CR_IRTX_LOGIC1_PH1_W IR_CR_IRTX_LOGIC1_PH1_W +#define IR_CR_IRTX_LOGIC1_PH1_W_POS (12U) +#define IR_CR_IRTX_LOGIC1_PH1_W_LEN (4U) +#define IR_CR_IRTX_LOGIC1_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS) +#define IR_CR_IRTX_LOGIC1_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS)) +#define IR_CR_IRTX_HEAD_PH0_W IR_CR_IRTX_HEAD_PH0_W +#define IR_CR_IRTX_HEAD_PH0_W_POS (16U) +#define IR_CR_IRTX_HEAD_PH0_W_LEN (4U) +#define IR_CR_IRTX_HEAD_PH0_W_MSK (((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS) +#define IR_CR_IRTX_HEAD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS)) +#define IR_CR_IRTX_HEAD_PH1_W IR_CR_IRTX_HEAD_PH1_W +#define IR_CR_IRTX_HEAD_PH1_W_POS (20U) +#define IR_CR_IRTX_HEAD_PH1_W_LEN (4U) +#define IR_CR_IRTX_HEAD_PH1_W_MSK (((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS) +#define IR_CR_IRTX_HEAD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS)) +#define IR_CR_IRTX_TAIL_PH0_W IR_CR_IRTX_TAIL_PH0_W +#define IR_CR_IRTX_TAIL_PH0_W_POS (24U) +#define IR_CR_IRTX_TAIL_PH0_W_LEN (4U) +#define IR_CR_IRTX_TAIL_PH0_W_MSK (((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS) +#define IR_CR_IRTX_TAIL_PH0_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS)) +#define IR_CR_IRTX_TAIL_PH1_W IR_CR_IRTX_TAIL_PH1_W +#define IR_CR_IRTX_TAIL_PH1_W_POS (28U) +#define IR_CR_IRTX_TAIL_PH1_W_LEN (4U) +#define IR_CR_IRTX_TAIL_PH1_W_MSK (((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS) +#define IR_CR_IRTX_TAIL_PH1_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS)) + +/* 0x40 : irtx_swm_pw_0 */ +#define IRTX_SWM_PW_0_OFFSET (0x40) +#define IR_CR_IRTX_SWM_PW_0 IR_CR_IRTX_SWM_PW_0 +#define IR_CR_IRTX_SWM_PW_0_POS (0U) +#define IR_CR_IRTX_SWM_PW_0_LEN (32U) +#define IR_CR_IRTX_SWM_PW_0_MSK (((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS) +#define IR_CR_IRTX_SWM_PW_0_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS)) + +/* 0x44 : irtx_swm_pw_1 */ +#define IRTX_SWM_PW_1_OFFSET (0x44) +#define IR_CR_IRTX_SWM_PW_1 IR_CR_IRTX_SWM_PW_1 +#define IR_CR_IRTX_SWM_PW_1_POS (0U) +#define IR_CR_IRTX_SWM_PW_1_LEN (32U) +#define IR_CR_IRTX_SWM_PW_1_MSK (((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS) +#define IR_CR_IRTX_SWM_PW_1_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS)) + +/* 0x48 : irtx_swm_pw_2 */ +#define IRTX_SWM_PW_2_OFFSET (0x48) +#define IR_CR_IRTX_SWM_PW_2 IR_CR_IRTX_SWM_PW_2 +#define IR_CR_IRTX_SWM_PW_2_POS (0U) +#define IR_CR_IRTX_SWM_PW_2_LEN (32U) +#define IR_CR_IRTX_SWM_PW_2_MSK (((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS) +#define IR_CR_IRTX_SWM_PW_2_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS)) + +/* 0x4C : irtx_swm_pw_3 */ +#define IRTX_SWM_PW_3_OFFSET (0x4C) +#define IR_CR_IRTX_SWM_PW_3 IR_CR_IRTX_SWM_PW_3 +#define IR_CR_IRTX_SWM_PW_3_POS (0U) +#define IR_CR_IRTX_SWM_PW_3_LEN (32U) +#define IR_CR_IRTX_SWM_PW_3_MSK (((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS) +#define IR_CR_IRTX_SWM_PW_3_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS)) + +/* 0x50 : irtx_swm_pw_4 */ +#define IRTX_SWM_PW_4_OFFSET (0x50) +#define IR_CR_IRTX_SWM_PW_4 IR_CR_IRTX_SWM_PW_4 +#define IR_CR_IRTX_SWM_PW_4_POS (0U) +#define IR_CR_IRTX_SWM_PW_4_LEN (32U) +#define IR_CR_IRTX_SWM_PW_4_MSK (((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS) +#define IR_CR_IRTX_SWM_PW_4_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS)) + +/* 0x54 : irtx_swm_pw_5 */ +#define IRTX_SWM_PW_5_OFFSET (0x54) +#define IR_CR_IRTX_SWM_PW_5 IR_CR_IRTX_SWM_PW_5 +#define IR_CR_IRTX_SWM_PW_5_POS (0U) +#define IR_CR_IRTX_SWM_PW_5_LEN (32U) +#define IR_CR_IRTX_SWM_PW_5_MSK (((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS) +#define IR_CR_IRTX_SWM_PW_5_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS)) + +/* 0x58 : irtx_swm_pw_6 */ +#define IRTX_SWM_PW_6_OFFSET (0x58) +#define IR_CR_IRTX_SWM_PW_6 IR_CR_IRTX_SWM_PW_6 +#define IR_CR_IRTX_SWM_PW_6_POS (0U) +#define IR_CR_IRTX_SWM_PW_6_LEN (32U) +#define IR_CR_IRTX_SWM_PW_6_MSK (((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS) +#define IR_CR_IRTX_SWM_PW_6_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS)) + +/* 0x5C : irtx_swm_pw_7 */ +#define IRTX_SWM_PW_7_OFFSET (0x5C) +#define IR_CR_IRTX_SWM_PW_7 IR_CR_IRTX_SWM_PW_7 +#define IR_CR_IRTX_SWM_PW_7_POS (0U) +#define IR_CR_IRTX_SWM_PW_7_LEN (32U) +#define IR_CR_IRTX_SWM_PW_7_MSK (((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS) +#define IR_CR_IRTX_SWM_PW_7_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS)) + +/* 0x80 : irrx_config */ +#define IRRX_CONFIG_OFFSET (0x80) +#define IR_CR_IRRX_EN IR_CR_IRRX_EN +#define IR_CR_IRRX_EN_POS (0U) +#define IR_CR_IRRX_EN_LEN (1U) +#define IR_CR_IRRX_EN_MSK (((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS) +#define IR_CR_IRRX_EN_UMSK (~(((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS)) +#define IR_CR_IRRX_IN_INV IR_CR_IRRX_IN_INV +#define IR_CR_IRRX_IN_INV_POS (1U) +#define IR_CR_IRRX_IN_INV_LEN (1U) +#define IR_CR_IRRX_IN_INV_MSK (((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS) +#define IR_CR_IRRX_IN_INV_UMSK (~(((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS)) +#define IR_CR_IRRX_MODE IR_CR_IRRX_MODE +#define IR_CR_IRRX_MODE_POS (2U) +#define IR_CR_IRRX_MODE_LEN (2U) +#define IR_CR_IRRX_MODE_MSK (((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS) +#define IR_CR_IRRX_MODE_UMSK (~(((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS)) +#define IR_CR_IRRX_DEG_EN IR_CR_IRRX_DEG_EN +#define IR_CR_IRRX_DEG_EN_POS (4U) +#define IR_CR_IRRX_DEG_EN_LEN (1U) +#define IR_CR_IRRX_DEG_EN_MSK (((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS) +#define IR_CR_IRRX_DEG_EN_UMSK (~(((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS)) +#define IR_CR_IRRX_DEG_CNT IR_CR_IRRX_DEG_CNT +#define IR_CR_IRRX_DEG_CNT_POS (8U) +#define IR_CR_IRRX_DEG_CNT_LEN (4U) +#define IR_CR_IRRX_DEG_CNT_MSK (((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS) +#define IR_CR_IRRX_DEG_CNT_UMSK (~(((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS)) + +/* 0x84 : irrx_int_sts */ +#define IRRX_INT_STS_OFFSET (0x84) +#define IRRX_END_INT IRRX_END_INT +#define IRRX_END_INT_POS (0U) +#define IRRX_END_INT_LEN (1U) +#define IRRX_END_INT_MSK (((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS) +#define IRRX_END_INT_UMSK (~(((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS)) +#define IR_CR_IRRX_END_MASK IR_CR_IRRX_END_MASK +#define IR_CR_IRRX_END_MASK_POS (8U) +#define IR_CR_IRRX_END_MASK_LEN (1U) +#define IR_CR_IRRX_END_MASK_MSK (((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS) +#define IR_CR_IRRX_END_MASK_UMSK (~(((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS)) +#define IR_CR_IRRX_END_CLR IR_CR_IRRX_END_CLR +#define IR_CR_IRRX_END_CLR_POS (16U) +#define IR_CR_IRRX_END_CLR_LEN (1U) +#define IR_CR_IRRX_END_CLR_MSK (((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS) +#define IR_CR_IRRX_END_CLR_UMSK (~(((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS)) +#define IR_CR_IRRX_END_EN IR_CR_IRRX_END_EN +#define IR_CR_IRRX_END_EN_POS (24U) +#define IR_CR_IRRX_END_EN_LEN (1U) +#define IR_CR_IRRX_END_EN_MSK (((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS) +#define IR_CR_IRRX_END_EN_UMSK (~(((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS)) + +/* 0x88 : irrx_pw_config */ +#define IRRX_PW_CONFIG_OFFSET (0x88) +#define IR_CR_IRRX_DATA_TH IR_CR_IRRX_DATA_TH +#define IR_CR_IRRX_DATA_TH_POS (0U) +#define IR_CR_IRRX_DATA_TH_LEN (16U) +#define IR_CR_IRRX_DATA_TH_MSK (((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS) +#define IR_CR_IRRX_DATA_TH_UMSK (~(((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS)) +#define IR_CR_IRRX_END_TH IR_CR_IRRX_END_TH +#define IR_CR_IRRX_END_TH_POS (16U) +#define IR_CR_IRRX_END_TH_LEN (16U) +#define IR_CR_IRRX_END_TH_MSK (((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS) +#define IR_CR_IRRX_END_TH_UMSK (~(((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS)) + +/* 0x90 : irrx_data_count */ +#define IRRX_DATA_COUNT_OFFSET (0x90) +#define IR_STS_IRRX_DATA_CNT IR_STS_IRRX_DATA_CNT +#define IR_STS_IRRX_DATA_CNT_POS (0U) +#define IR_STS_IRRX_DATA_CNT_LEN (7U) +#define IR_STS_IRRX_DATA_CNT_MSK (((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS) +#define IR_STS_IRRX_DATA_CNT_UMSK (~(((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS)) + +/* 0x94 : irrx_data_word0 */ +#define IRRX_DATA_WORD0_OFFSET (0x94) +#define IR_STS_IRRX_DATA_WORD0 IR_STS_IRRX_DATA_WORD0 +#define IR_STS_IRRX_DATA_WORD0_POS (0U) +#define IR_STS_IRRX_DATA_WORD0_LEN (32U) +#define IR_STS_IRRX_DATA_WORD0_MSK (((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS) +#define IR_STS_IRRX_DATA_WORD0_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS)) + +/* 0x98 : irrx_data_word1 */ +#define IRRX_DATA_WORD1_OFFSET (0x98) +#define IR_STS_IRRX_DATA_WORD1 IR_STS_IRRX_DATA_WORD1 +#define IR_STS_IRRX_DATA_WORD1_POS (0U) +#define IR_STS_IRRX_DATA_WORD1_LEN (32U) +#define IR_STS_IRRX_DATA_WORD1_MSK (((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS) +#define IR_STS_IRRX_DATA_WORD1_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS)) + +/* 0xC0 : irrx_swm_fifo_config_0 */ +#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0) +#define IR_RX_FIFO_CLR IR_RX_FIFO_CLR +#define IR_RX_FIFO_CLR_POS (0U) +#define IR_RX_FIFO_CLR_LEN (1U) +#define IR_RX_FIFO_CLR_MSK (((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS) +#define IR_RX_FIFO_CLR_UMSK (~(((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS)) +#define IR_RX_FIFO_OVERFLOW IR_RX_FIFO_OVERFLOW +#define IR_RX_FIFO_OVERFLOW_POS (2U) +#define IR_RX_FIFO_OVERFLOW_LEN (1U) +#define IR_RX_FIFO_OVERFLOW_MSK (((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS) +#define IR_RX_FIFO_OVERFLOW_UMSK (~(((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS)) +#define IR_RX_FIFO_UNDERFLOW IR_RX_FIFO_UNDERFLOW +#define IR_RX_FIFO_UNDERFLOW_POS (3U) +#define IR_RX_FIFO_UNDERFLOW_LEN (1U) +#define IR_RX_FIFO_UNDERFLOW_MSK (((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS) +#define IR_RX_FIFO_UNDERFLOW_UMSK (~(((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS)) +#define IR_RX_FIFO_CNT IR_RX_FIFO_CNT +#define IR_RX_FIFO_CNT_POS (4U) +#define IR_RX_FIFO_CNT_LEN (7U) +#define IR_RX_FIFO_CNT_MSK (((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS) +#define IR_RX_FIFO_CNT_UMSK (~(((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS)) + +/* 0xC4 : irrx_swm_fifo_rdata */ +#define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4) +#define IR_RX_FIFO_RDATA IR_RX_FIFO_RDATA +#define IR_RX_FIFO_RDATA_POS (0U) +#define IR_RX_FIFO_RDATA_LEN (16U) +#define IR_RX_FIFO_RDATA_MSK (((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS) +#define IR_RX_FIFO_RDATA_UMSK (~(((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS)) + +struct ir_reg { + /* 0x0 : irtx_config */ + union { + struct + { + uint32_t cr_irtx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_irtx_out_inv : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_irtx_mod_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_irtx_swm_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_irtx_data_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t cr_irtx_logic0_hl_inv : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_irtx_logic1_hl_inv : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cr_irtx_head_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_irtx_head_hl_inv : 1; /* [ 9], r/w, 0x0 */ + uint32_t cr_irtx_tail_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_irtx_tail_hl_inv : 1; /* [ 11], r/w, 0x0 */ + uint32_t cr_irtx_data_num : 6; /* [17:12], r/w, 0x1f */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irtx_config; + + /* 0x4 : irtx_int_sts */ + union { + struct + { + uint32_t irtx_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ + uint32_t cr_irtx_end_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ + uint32_t cr_irtx_end_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ + uint32_t cr_irtx_end_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irtx_int_sts; + + /* 0x8 : irtx_data_word0 */ + union { + struct + { + uint32_t cr_irtx_data_word0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_data_word0; + + /* 0xC : irtx_data_word1 */ + union { + struct + { + uint32_t cr_irtx_data_word1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_data_word1; + + /* 0x10 : irtx_pulse_width */ + union { + struct + { + uint32_t cr_irtx_pw_unit : 12; /* [11: 0], r/w, 0x464 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t cr_irtx_mod_ph0_w : 8; /* [23:16], r/w, 0x11 */ + uint32_t cr_irtx_mod_ph1_w : 8; /* [31:24], r/w, 0x22 */ + } BF; + uint32_t WORD; + } irtx_pulse_width; + + /* 0x14 : irtx_pw */ + union { + struct + { + uint32_t cr_irtx_logic0_ph0_w : 4; /* [ 3: 0], r/w, 0x0 */ + uint32_t cr_irtx_logic0_ph1_w : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t cr_irtx_logic1_ph0_w : 4; /* [11: 8], r/w, 0x0 */ + uint32_t cr_irtx_logic1_ph1_w : 4; /* [15:12], r/w, 0x2 */ + uint32_t cr_irtx_head_ph0_w : 4; /* [19:16], r/w, 0xf */ + uint32_t cr_irtx_head_ph1_w : 4; /* [23:20], r/w, 0x7 */ + uint32_t cr_irtx_tail_ph0_w : 4; /* [27:24], r/w, 0x0 */ + uint32_t cr_irtx_tail_ph1_w : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_pw; + + /* 0x18 reserved */ + uint8_t RESERVED0x18[40]; + + /* 0x40 : irtx_swm_pw_0 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_0; + + /* 0x44 : irtx_swm_pw_1 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_1; + + /* 0x48 : irtx_swm_pw_2 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_2; + + /* 0x4C : irtx_swm_pw_3 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_3; + + /* 0x50 : irtx_swm_pw_4 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_4; + + /* 0x54 : irtx_swm_pw_5 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_5; + + /* 0x58 : irtx_swm_pw_6 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_6; + + /* 0x5C : irtx_swm_pw_7 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_7; + + /* 0x60 reserved */ + uint8_t RESERVED0x60[32]; + + /* 0x80 : irrx_config */ + union { + struct + { + uint32_t cr_irrx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_irrx_in_inv : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_irrx_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t cr_irrx_deg_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t cr_irrx_deg_cnt : 4; /* [11: 8], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_config; + + /* 0x84 : irrx_int_sts */ + union { + struct + { + uint32_t irrx_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ + uint32_t cr_irrx_end_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ + uint32_t cr_irrx_end_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ + uint32_t cr_irrx_end_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_int_sts; + + /* 0x88 : irrx_pw_config */ + union { + struct + { + uint32_t cr_irrx_data_th : 16; /* [15: 0], r/w, 0xd47 */ + uint32_t cr_irrx_end_th : 16; /* [31:16], r/w, 0x2327 */ + } BF; + uint32_t WORD; + } irrx_pw_config; + + /* 0x8c reserved */ + uint8_t RESERVED0x8c[4]; + + /* 0x90 : irrx_data_count */ + union { + struct + { + uint32_t sts_irrx_data_cnt : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_data_count; + + /* 0x94 : irrx_data_word0 */ + union { + struct + { + uint32_t sts_irrx_data_word0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } irrx_data_word0; + + /* 0x98 : irrx_data_word1 */ + union { + struct + { + uint32_t sts_irrx_data_word1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } irrx_data_word1; + + /* 0x9c reserved */ + uint8_t RESERVED0x9c[36]; + + /* 0xC0 : irrx_swm_fifo_config_0 */ + union { + struct + { + uint32_t rx_fifo_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 2], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 3], r, 0x0 */ + uint32_t rx_fifo_cnt : 7; /* [10: 4], r, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_swm_fifo_config_0; + + /* 0xC4 : irrx_swm_fifo_rdata */ + union { + struct + { + uint32_t rx_fifo_rdata : 16; /* [15: 0], r, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_swm_fifo_rdata; +}; + +typedef volatile struct ir_reg ir_reg_t; + +#endif /* __IR_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/l1c_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/l1c_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..2c618383c87c7122f388e88378fb047e95199376 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/l1c_reg.h @@ -0,0 +1,318 @@ +/** + ****************************************************************************** + * @file l1c_reg.h + * @version V1.2 + * @date 2019-11-22 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __L1C_REG_H__ +#define __L1C_REG_H__ + +#include "bl602.h" + +/* 0x0 : l1c_config */ +#define L1C_CONFIG_OFFSET (0x0) +#define L1C_CACHEABLE L1C_CACHEABLE +#define L1C_CACHEABLE_POS (0U) +#define L1C_CACHEABLE_LEN (1U) +#define L1C_CACHEABLE_MSK (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS) +#define L1C_CACHEABLE_UMSK (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)) +#define L1C_CNT_EN L1C_CNT_EN +#define L1C_CNT_EN_POS (1U) +#define L1C_CNT_EN_LEN (1U) +#define L1C_CNT_EN_MSK (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS) +#define L1C_CNT_EN_UMSK (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)) +#define L1C_INVALID_EN L1C_INVALID_EN +#define L1C_INVALID_EN_POS (2U) +#define L1C_INVALID_EN_LEN (1U) +#define L1C_INVALID_EN_MSK (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS) +#define L1C_INVALID_EN_UMSK (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)) +#define L1C_INVALID_DONE L1C_INVALID_DONE +#define L1C_INVALID_DONE_POS (3U) +#define L1C_INVALID_DONE_LEN (1U) +#define L1C_INVALID_DONE_MSK (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS) +#define L1C_INVALID_DONE_UMSK (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)) +#define L1C_WAY_DIS L1C_WAY_DIS +#define L1C_WAY_DIS_POS (8U) +#define L1C_WAY_DIS_LEN (4U) +#define L1C_WAY_DIS_MSK (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS) +#define L1C_WAY_DIS_UMSK (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)) +#define L1C_IROM_2T_ACCESS L1C_IROM_2T_ACCESS +#define L1C_IROM_2T_ACCESS_POS (12U) +#define L1C_IROM_2T_ACCESS_LEN (1U) +#define L1C_IROM_2T_ACCESS_MSK (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS) +#define L1C_IROM_2T_ACCESS_UMSK (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)) +#define L1C_BYPASS L1C_BYPASS +#define L1C_BYPASS_POS (14U) +#define L1C_BYPASS_LEN (1U) +#define L1C_BYPASS_MSK (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS) +#define L1C_BYPASS_UMSK (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)) +#define L1C_BMX_ERR_EN L1C_BMX_ERR_EN +#define L1C_BMX_ERR_EN_POS (15U) +#define L1C_BMX_ERR_EN_LEN (1U) +#define L1C_BMX_ERR_EN_MSK (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS) +#define L1C_BMX_ERR_EN_UMSK (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)) +#define L1C_BMX_ARB_MODE L1C_BMX_ARB_MODE +#define L1C_BMX_ARB_MODE_POS (16U) +#define L1C_BMX_ARB_MODE_LEN (2U) +#define L1C_BMX_ARB_MODE_MSK (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS) +#define L1C_BMX_ARB_MODE_UMSK (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)) +#define L1C_BMX_TIMEOUT_EN L1C_BMX_TIMEOUT_EN +#define L1C_BMX_TIMEOUT_EN_POS (20U) +#define L1C_BMX_TIMEOUT_EN_LEN (4U) +#define L1C_BMX_TIMEOUT_EN_MSK (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS) +#define L1C_BMX_TIMEOUT_EN_UMSK (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)) +#define L1C_BMX_BUSY_OPTION_DIS L1C_BMX_BUSY_OPTION_DIS +#define L1C_BMX_BUSY_OPTION_DIS_POS (24U) +#define L1C_BMX_BUSY_OPTION_DIS_LEN (1U) +#define L1C_BMX_BUSY_OPTION_DIS_MSK (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS) +#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)) +#define L1C_EARLY_RESP_DIS L1C_EARLY_RESP_DIS +#define L1C_EARLY_RESP_DIS_POS (25U) +#define L1C_EARLY_RESP_DIS_LEN (1U) +#define L1C_EARLY_RESP_DIS_MSK (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS) +#define L1C_EARLY_RESP_DIS_UMSK (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)) +#define L1C_WRAP_DIS L1C_WRAP_DIS +#define L1C_WRAP_DIS_POS (26U) +#define L1C_WRAP_DIS_LEN (1U) +#define L1C_WRAP_DIS_MSK (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS) +#define L1C_WRAP_DIS_UMSK (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)) + +/* 0x4 : hit_cnt_lsb */ +#define L1C_HIT_CNT_LSB_OFFSET (0x4) +#define L1C_HIT_CNT_LSB L1C_HIT_CNT_LSB +#define L1C_HIT_CNT_LSB_POS (0U) +#define L1C_HIT_CNT_LSB_LEN (32U) +#define L1C_HIT_CNT_LSB_MSK (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS) +#define L1C_HIT_CNT_LSB_UMSK (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)) + +/* 0x8 : hit_cnt_msb */ +#define L1C_HIT_CNT_MSB_OFFSET (0x8) +#define L1C_HIT_CNT_MSB L1C_HIT_CNT_MSB +#define L1C_HIT_CNT_MSB_POS (0U) +#define L1C_HIT_CNT_MSB_LEN (32U) +#define L1C_HIT_CNT_MSB_MSK (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS) +#define L1C_HIT_CNT_MSB_UMSK (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)) + +/* 0xC : miss_cnt */ +#define L1C_MISS_CNT_OFFSET (0xC) +#define L1C_MISS_CNT L1C_MISS_CNT +#define L1C_MISS_CNT_POS (0U) +#define L1C_MISS_CNT_LEN (32U) +#define L1C_MISS_CNT_MSK (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS) +#define L1C_MISS_CNT_UMSK (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)) + +/* 0x10 : l1c_range */ +#define L1C_RANGE_OFFSET (0x10) + +/* 0x200 : l1c_bmx_err_addr_en */ +#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200) +#define L1C_BMX_ERR_ADDR_DIS L1C_BMX_ERR_ADDR_DIS +#define L1C_BMX_ERR_ADDR_DIS_POS (0U) +#define L1C_BMX_ERR_ADDR_DIS_LEN (1U) +#define L1C_BMX_ERR_ADDR_DIS_MSK (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS) +#define L1C_BMX_ERR_ADDR_DIS_UMSK (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)) +#define L1C_BMX_ERR_DEC L1C_BMX_ERR_DEC +#define L1C_BMX_ERR_DEC_POS (4U) +#define L1C_BMX_ERR_DEC_LEN (1U) +#define L1C_BMX_ERR_DEC_MSK (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS) +#define L1C_BMX_ERR_DEC_UMSK (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)) +#define L1C_BMX_ERR_TZ L1C_BMX_ERR_TZ +#define L1C_BMX_ERR_TZ_POS (5U) +#define L1C_BMX_ERR_TZ_LEN (1U) +#define L1C_BMX_ERR_TZ_MSK (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS) +#define L1C_BMX_ERR_TZ_UMSK (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)) +#define L1C_HSEL_OPTION L1C_HSEL_OPTION +#define L1C_HSEL_OPTION_POS (16U) +#define L1C_HSEL_OPTION_LEN (4U) +#define L1C_HSEL_OPTION_MSK (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS) +#define L1C_HSEL_OPTION_UMSK (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)) + +/* 0x204 : l1c_bmx_err_addr */ +#define L1C_BMX_ERR_ADDR_OFFSET (0x204) +#define L1C_BMX_ERR_ADDR L1C_BMX_ERR_ADDR +#define L1C_BMX_ERR_ADDR_POS (0U) +#define L1C_BMX_ERR_ADDR_LEN (32U) +#define L1C_BMX_ERR_ADDR_MSK (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS) +#define L1C_BMX_ERR_ADDR_UMSK (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)) + +/* 0x208 : irom1_misr_dataout_0 */ +#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208) +#define L1C_IROM1_MISR_DATAOUT_0 L1C_IROM1_MISR_DATAOUT_0 +#define L1C_IROM1_MISR_DATAOUT_0_POS (0U) +#define L1C_IROM1_MISR_DATAOUT_0_LEN (32U) +#define L1C_IROM1_MISR_DATAOUT_0_MSK (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS) +#define L1C_IROM1_MISR_DATAOUT_0_UMSK (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)) + +/* 0x20C : irom1_misr_dataout_1 */ +#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C) + +/* 0x210 : cpu_clk_gate */ +#define L1C_CPU_CLK_GATE_OFFSET (0x210) +#define L1C_FORCE_E21_CLOCK_ON_0 L1C_FORCE_E21_CLOCK_ON_0 +#define L1C_FORCE_E21_CLOCK_ON_0_POS (0U) +#define L1C_FORCE_E21_CLOCK_ON_0_LEN (1U) +#define L1C_FORCE_E21_CLOCK_ON_0_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS) +#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)) +#define L1C_FORCE_E21_CLOCK_ON_1 L1C_FORCE_E21_CLOCK_ON_1 +#define L1C_FORCE_E21_CLOCK_ON_1_POS (1U) +#define L1C_FORCE_E21_CLOCK_ON_1_LEN (1U) +#define L1C_FORCE_E21_CLOCK_ON_1_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS) +#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)) +#define L1C_FORCE_E21_CLOCK_ON_2 L1C_FORCE_E21_CLOCK_ON_2 +#define L1C_FORCE_E21_CLOCK_ON_2_POS (2U) +#define L1C_FORCE_E21_CLOCK_ON_2_LEN (1U) +#define L1C_FORCE_E21_CLOCK_ON_2_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS) +#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)) + +struct l1c_reg { + /* 0x0 : l1c_config */ + union { + struct + { + uint32_t l1c_cacheable : 1; /* [ 0], r/w, 0x0 */ + uint32_t l1c_cnt_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t l1c_invalid_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t l1c_invalid_done : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t l1c_way_dis : 4; /* [11: 8], r/w, 0xf */ + uint32_t irom_2t_access : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */ + uint32_t l1c_bypass : 1; /* [ 14], r/w, 0x0 */ + uint32_t l1c_bmx_err_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t l1c_bmx_arb_mode : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */ + uint32_t l1c_bmx_timeout_en : 4; /* [23:20], r/w, 0x0 */ + uint32_t l1c_bmx_busy_option_dis : 1; /* [ 24], r/w, 0x0 */ + uint32_t early_resp_dis : 1; /* [ 25], r/w, 0x1 */ + uint32_t wrap_dis : 1; /* [ 26], r/w, 0x1 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } l1c_config; + + /* 0x4 : hit_cnt_lsb */ + union { + struct + { + uint32_t hit_cnt_lsb : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } hit_cnt_lsb; + + /* 0x8 : hit_cnt_msb */ + union { + struct + { + uint32_t hit_cnt_msb : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } hit_cnt_msb; + + /* 0xC : miss_cnt */ + union { + struct + { + uint32_t miss_cnt : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } miss_cnt; + + /* 0x10 : l1c_range */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } l1c_range; + + /* 0x14 reserved */ + uint8_t RESERVED0x14[492]; + + /* 0x200 : l1c_bmx_err_addr_en */ + union { + struct + { + uint32_t l1c_bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t l1c_bmx_err_dec : 1; /* [ 4], r, 0x0 */ + uint32_t l1c_bmx_err_tz : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t l1c_hsel_option : 4; /* [19:16], r/w, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } l1c_bmx_err_addr_en; + + /* 0x204 : l1c_bmx_err_addr */ + union { + struct + { + uint32_t l1c_bmx_err_addr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } l1c_bmx_err_addr; + + /* 0x208 : irom1_misr_dataout_0 */ + union { + struct + { + uint32_t irom1_misr_dataout_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } irom1_misr_dataout_0; + + /* 0x20C : irom1_misr_dataout_1 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irom1_misr_dataout_1; + + /* 0x210 : cpu_clk_gate */ + union { + struct + { + uint32_t force_e21_clock_on_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t force_e21_clock_on_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t force_e21_clock_on_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cpu_clk_gate; +}; + +typedef volatile struct l1c_reg l1c_reg_t; + +#endif /* __L1C_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/pds_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/pds_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..5b5ebe6654be2df4c65ce5f13eee73e448ea0427 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/pds_reg.h @@ -0,0 +1,1085 @@ +/** + ****************************************************************************** + * @file pds_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PDS_REG_H__ +#define __PDS_REG_H__ + +#include "bl602.h" + +/* 0x0 : PDS_CTL */ +#define PDS_CTL_OFFSET (0x0) +#define PDS_START_PS PDS_START_PS +#define PDS_START_PS_POS (0U) +#define PDS_START_PS_LEN (1U) +#define PDS_START_PS_MSK (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS) +#define PDS_START_PS_UMSK (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)) +#define PDS_CR_SLEEP_FOREVER PDS_CR_SLEEP_FOREVER +#define PDS_CR_SLEEP_FOREVER_POS (1U) +#define PDS_CR_SLEEP_FOREVER_LEN (1U) +#define PDS_CR_SLEEP_FOREVER_MSK (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS) +#define PDS_CR_SLEEP_FOREVER_UMSK (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)) +#define PDS_CR_XTAL_FORCE_OFF PDS_CR_XTAL_FORCE_OFF +#define PDS_CR_XTAL_FORCE_OFF_POS (2U) +#define PDS_CR_XTAL_FORCE_OFF_LEN (1U) +#define PDS_CR_XTAL_FORCE_OFF_MSK (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS) +#define PDS_CR_XTAL_FORCE_OFF_UMSK (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)) +#define PDS_CR_WIFI_PDS_SAVE_STATE PDS_CR_WIFI_PDS_SAVE_STATE +#define PDS_CR_WIFI_PDS_SAVE_STATE_POS (3U) +#define PDS_CR_WIFI_PDS_SAVE_STATE_LEN (1U) +#define PDS_CR_WIFI_PDS_SAVE_STATE_MSK (((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS) +#define PDS_CR_WIFI_PDS_SAVE_STATE_UMSK (~(((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS)) +#define PDS_CR_PDS_PD_DCDC18 PDS_CR_PDS_PD_DCDC18 +#define PDS_CR_PDS_PD_DCDC18_POS (4U) +#define PDS_CR_PDS_PD_DCDC18_LEN (1U) +#define PDS_CR_PDS_PD_DCDC18_MSK (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS) +#define PDS_CR_PDS_PD_DCDC18_UMSK (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)) +#define PDS_CR_PDS_PD_BG_SYS PDS_CR_PDS_PD_BG_SYS +#define PDS_CR_PDS_PD_BG_SYS_POS (5U) +#define PDS_CR_PDS_PD_BG_SYS_LEN (1U) +#define PDS_CR_PDS_PD_BG_SYS_MSK (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS) +#define PDS_CR_PDS_PD_BG_SYS_UMSK (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)) +#define PDS_CR_PDS_GATE_CLK PDS_CR_PDS_GATE_CLK +#define PDS_CR_PDS_GATE_CLK_POS (8U) +#define PDS_CR_PDS_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_GATE_CLK_MSK (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS) +#define PDS_CR_PDS_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)) +#define PDS_CR_PDS_MEM_STBY PDS_CR_PDS_MEM_STBY +#define PDS_CR_PDS_MEM_STBY_POS (9U) +#define PDS_CR_PDS_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_MEM_STBY_MSK (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS) +#define PDS_CR_PDS_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)) +#define PDS_CR_PDS_ISO_EN PDS_CR_PDS_ISO_EN +#define PDS_CR_PDS_ISO_EN_POS (11U) +#define PDS_CR_PDS_ISO_EN_LEN (1U) +#define PDS_CR_PDS_ISO_EN_MSK (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS) +#define PDS_CR_PDS_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)) +#define PDS_CR_PDS_WAIT_XTAL_RDY PDS_CR_PDS_WAIT_XTAL_RDY +#define PDS_CR_PDS_WAIT_XTAL_RDY_POS (12U) +#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN (1U) +#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS) +#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)) +#define PDS_CR_PDS_PWR_OFF PDS_CR_PDS_PWR_OFF +#define PDS_CR_PDS_PWR_OFF_POS (13U) +#define PDS_CR_PDS_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_PWR_OFF_MSK (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS) +#define PDS_CR_PDS_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)) +#define PDS_CR_PDS_PD_XTAL PDS_CR_PDS_PD_XTAL +#define PDS_CR_PDS_PD_XTAL_POS (14U) +#define PDS_CR_PDS_PD_XTAL_LEN (1U) +#define PDS_CR_PDS_PD_XTAL_MSK (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS) +#define PDS_CR_PDS_PD_XTAL_UMSK (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON PDS_CR_PDS_SOC_ENB_FORCE_ON +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_POS (15U) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN (1U) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_MSK (((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_UMSK (~(((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS)) +#define PDS_CR_PDS_RST_SOC_EN PDS_CR_PDS_RST_SOC_EN +#define PDS_CR_PDS_RST_SOC_EN_POS (16U) +#define PDS_CR_PDS_RST_SOC_EN_LEN (1U) +#define PDS_CR_PDS_RST_SOC_EN_MSK (((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS) +#define PDS_CR_PDS_RST_SOC_EN_UMSK (~(((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS)) +#define PDS_CR_PDS_RC32M_OFF_DIS PDS_CR_PDS_RC32M_OFF_DIS +#define PDS_CR_PDS_RC32M_OFF_DIS_POS (17U) +#define PDS_CR_PDS_RC32M_OFF_DIS_LEN (1U) +#define PDS_CR_PDS_RC32M_OFF_DIS_MSK (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS) +#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)) +#define PDS_CR_PDS_LDO_VSEL_EN PDS_CR_PDS_LDO_VSEL_EN +#define PDS_CR_PDS_LDO_VSEL_EN_POS (18U) +#define PDS_CR_PDS_LDO_VSEL_EN_LEN (1U) +#define PDS_CR_PDS_LDO_VSEL_EN_MSK (((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS) +#define PDS_CR_PDS_LDO_VSEL_EN_UMSK (~(((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS)) +#define PDS_CR_NP_WFI_MASK PDS_CR_NP_WFI_MASK +#define PDS_CR_NP_WFI_MASK_POS (21U) +#define PDS_CR_NP_WFI_MASK_LEN (1U) +#define PDS_CR_NP_WFI_MASK_MSK (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS) +#define PDS_CR_NP_WFI_MASK_UMSK (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)) +#define PDS_CR_PDS_PD_LDO11 PDS_CR_PDS_PD_LDO11 +#define PDS_CR_PDS_PD_LDO11_POS (22U) +#define PDS_CR_PDS_PD_LDO11_LEN (1U) +#define PDS_CR_PDS_PD_LDO11_MSK (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS) +#define PDS_CR_PDS_PD_LDO11_UMSK (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)) +#define PDS_CR_PDS_LDO_VOL PDS_CR_PDS_LDO_VOL +#define PDS_CR_PDS_LDO_VOL_POS (24U) +#define PDS_CR_PDS_LDO_VOL_LEN (4U) +#define PDS_CR_PDS_LDO_VOL_MSK (((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS) +#define PDS_CR_PDS_LDO_VOL_UMSK (~(((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS)) +#define PDS_CR_PDS_CTRL_RF PDS_CR_PDS_CTRL_RF +#define PDS_CR_PDS_CTRL_RF_POS (28U) +#define PDS_CR_PDS_CTRL_RF_LEN (2U) +#define PDS_CR_PDS_CTRL_RF_MSK (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS) +#define PDS_CR_PDS_CTRL_RF_UMSK (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)) +#define PDS_CR_PDS_CTRL_PLL PDS_CR_PDS_CTRL_PLL +#define PDS_CR_PDS_CTRL_PLL_POS (30U) +#define PDS_CR_PDS_CTRL_PLL_LEN (2U) +#define PDS_CR_PDS_CTRL_PLL_MSK (((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS) +#define PDS_CR_PDS_CTRL_PLL_UMSK (~(((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS)) + +/* 0x4 : PDS_TIME1 */ +#define PDS_TIME1_OFFSET (0x4) +#define PDS_CR_SLEEP_DURATION PDS_CR_SLEEP_DURATION +#define PDS_CR_SLEEP_DURATION_POS (0U) +#define PDS_CR_SLEEP_DURATION_LEN (32U) +#define PDS_CR_SLEEP_DURATION_MSK (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS) +#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)) + +/* 0xC : PDS_INT */ +#define PDS_INT_OFFSET (0xC) +#define PDS_RO_PDS_WAKE_INT PDS_RO_PDS_WAKE_INT +#define PDS_RO_PDS_WAKE_INT_POS (0U) +#define PDS_RO_PDS_WAKE_INT_LEN (1U) +#define PDS_RO_PDS_WAKE_INT_MSK (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS) +#define PDS_RO_PDS_WAKE_INT_UMSK (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)) +#define PDS_RO_PDS_IRQ_IN PDS_RO_PDS_IRQ_IN +#define PDS_RO_PDS_IRQ_IN_POS (1U) +#define PDS_RO_PDS_IRQ_IN_LEN (1U) +#define PDS_RO_PDS_IRQ_IN_MSK (((1U << PDS_RO_PDS_IRQ_IN_LEN) - 1) << PDS_RO_PDS_IRQ_IN_POS) +#define PDS_RO_PDS_IRQ_IN_UMSK (~(((1U << PDS_RO_PDS_IRQ_IN_LEN) - 1) << PDS_RO_PDS_IRQ_IN_POS)) +#define PDS_RO_PDS_RF_DONE_INT PDS_RO_PDS_RF_DONE_INT +#define PDS_RO_PDS_RF_DONE_INT_POS (2U) +#define PDS_RO_PDS_RF_DONE_INT_LEN (1U) +#define PDS_RO_PDS_RF_DONE_INT_MSK (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS) +#define PDS_RO_PDS_RF_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)) +#define PDS_RO_PDS_PLL_DONE_INT PDS_RO_PDS_PLL_DONE_INT +#define PDS_RO_PDS_PLL_DONE_INT_POS (3U) +#define PDS_RO_PDS_PLL_DONE_INT_LEN (1U) +#define PDS_RO_PDS_PLL_DONE_INT_MSK (((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS) +#define PDS_RO_PDS_PLL_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS)) +#define PDS_CR_PDS_WAKE_INT_MASK PDS_CR_PDS_WAKE_INT_MASK +#define PDS_CR_PDS_WAKE_INT_MASK_POS (8U) +#define PDS_CR_PDS_WAKE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_WAKE_INT_MASK_MSK (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS) +#define PDS_CR_PDS_WAKE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)) +#define PDS_CR_PDS_IRQ_IN_DIS PDS_CR_PDS_IRQ_IN_DIS +#define PDS_CR_PDS_IRQ_IN_DIS_POS (9U) +#define PDS_CR_PDS_IRQ_IN_DIS_LEN (1U) +#define PDS_CR_PDS_IRQ_IN_DIS_MSK (((1U << PDS_CR_PDS_IRQ_IN_DIS_LEN) - 1) << PDS_CR_PDS_IRQ_IN_DIS_POS) +#define PDS_CR_PDS_IRQ_IN_DIS_UMSK (~(((1U << PDS_CR_PDS_IRQ_IN_DIS_LEN) - 1) << PDS_CR_PDS_IRQ_IN_DIS_POS)) +#define PDS_CR_PDS_RF_DONE_INT_MASK PDS_CR_PDS_RF_DONE_INT_MASK +#define PDS_CR_PDS_RF_DONE_INT_MASK_POS (10U) +#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS) +#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)) +#define PDS_CR_PDS_PLL_DONE_INT_MASK PDS_CR_PDS_PLL_DONE_INT_MASK +#define PDS_CR_PDS_PLL_DONE_INT_MASK_POS (11U) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS)) +#define PDS_CR_PDS_INT_CLR PDS_CR_PDS_INT_CLR +#define PDS_CR_PDS_INT_CLR_POS (16U) +#define PDS_CR_PDS_INT_CLR_LEN (1U) +#define PDS_CR_PDS_INT_CLR_MSK (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS) +#define PDS_CR_PDS_INT_CLR_UMSK (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)) + +/* 0x10 : PDS_CTL2 */ +#define PDS_CTL2_OFFSET (0x10) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF PDS_CR_PDS_FORCE_NP_PWR_OFF +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS (0U) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_WB_PWR_OFF PDS_CR_PDS_FORCE_WB_PWR_OFF +#define PDS_CR_PDS_FORCE_WB_PWR_OFF_POS (2U) +#define PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_WB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_NP_ISO_EN PDS_CR_PDS_FORCE_NP_ISO_EN +#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS (4U) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_WB_ISO_EN PDS_CR_PDS_FORCE_WB_ISO_EN +#define PDS_CR_PDS_FORCE_WB_ISO_EN_POS (6U) +#define PDS_CR_PDS_FORCE_WB_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_WB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_NP_PDS_RST PDS_CR_PDS_FORCE_NP_PDS_RST +#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS (8U) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_WB_PDS_RST PDS_CR_PDS_FORCE_WB_PDS_RST +#define PDS_CR_PDS_FORCE_WB_PDS_RST_POS (10U) +#define PDS_CR_PDS_FORCE_WB_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_WB_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY PDS_CR_PDS_FORCE_NP_MEM_STBY +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS (12U) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_WB_MEM_STBY PDS_CR_PDS_FORCE_WB_MEM_STBY +#define PDS_CR_PDS_FORCE_WB_MEM_STBY_POS (14U) +#define PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_WB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK PDS_CR_PDS_FORCE_NP_GATE_CLK +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS (16U) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)) +#define PDS_CR_PDS_FORCE_WB_GATE_CLK PDS_CR_PDS_FORCE_WB_GATE_CLK +#define PDS_CR_PDS_FORCE_WB_GATE_CLK_POS (18U) +#define PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_WB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS)) + +/* 0x14 : PDS_CTL3 */ +#define PDS_CTL3_OFFSET (0x14) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF PDS_CR_PDS_FORCE_MISC_PWR_OFF +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS (1U) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_MISC_ISO_EN PDS_CR_PDS_FORCE_MISC_ISO_EN +#define PDS_CR_PDS_FORCE_MISC_ISO_EN_POS (4U) +#define PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_MISC_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST PDS_CR_PDS_FORCE_MISC_PDS_RST +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS (7U) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY PDS_CR_PDS_FORCE_MISC_MEM_STBY +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS (10U) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK PDS_CR_PDS_FORCE_MISC_GATE_CLK +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS (13U) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)) +#define PDS_CR_PDS_NP_ISO_EN PDS_CR_PDS_NP_ISO_EN +#define PDS_CR_PDS_NP_ISO_EN_POS (24U) +#define PDS_CR_PDS_NP_ISO_EN_LEN (1U) +#define PDS_CR_PDS_NP_ISO_EN_MSK (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS) +#define PDS_CR_PDS_NP_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)) +#define PDS_CR_PDS_WB_ISO_EN PDS_CR_PDS_WB_ISO_EN +#define PDS_CR_PDS_WB_ISO_EN_POS (27U) +#define PDS_CR_PDS_WB_ISO_EN_LEN (1U) +#define PDS_CR_PDS_WB_ISO_EN_MSK (((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS) +#define PDS_CR_PDS_WB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS)) +#define PDS_CR_PDS_MISC_ISO_EN PDS_CR_PDS_MISC_ISO_EN +#define PDS_CR_PDS_MISC_ISO_EN_POS (30U) +#define PDS_CR_PDS_MISC_ISO_EN_LEN (1U) +#define PDS_CR_PDS_MISC_ISO_EN_MSK (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS) +#define PDS_CR_PDS_MISC_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)) + +/* 0x18 : PDS_CTL4 */ +#define PDS_CTL4_OFFSET (0x18) +#define PDS_CR_PDS_NP_PWR_OFF PDS_CR_PDS_NP_PWR_OFF +#define PDS_CR_PDS_NP_PWR_OFF_POS (0U) +#define PDS_CR_PDS_NP_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_NP_PWR_OFF_MSK (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS) +#define PDS_CR_PDS_NP_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)) +#define PDS_CR_PDS_NP_RESET PDS_CR_PDS_NP_RESET +#define PDS_CR_PDS_NP_RESET_POS (1U) +#define PDS_CR_PDS_NP_RESET_LEN (1U) +#define PDS_CR_PDS_NP_RESET_MSK (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS) +#define PDS_CR_PDS_NP_RESET_UMSK (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)) +#define PDS_CR_PDS_NP_MEM_STBY PDS_CR_PDS_NP_MEM_STBY +#define PDS_CR_PDS_NP_MEM_STBY_POS (2U) +#define PDS_CR_PDS_NP_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS) +#define PDS_CR_PDS_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)) +#define PDS_CR_PDS_NP_GATE_CLK PDS_CR_PDS_NP_GATE_CLK +#define PDS_CR_PDS_NP_GATE_CLK_POS (3U) +#define PDS_CR_PDS_NP_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS) +#define PDS_CR_PDS_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)) +#define PDS_CR_PDS_WB_PWR_OFF PDS_CR_PDS_WB_PWR_OFF +#define PDS_CR_PDS_WB_PWR_OFF_POS (12U) +#define PDS_CR_PDS_WB_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_WB_PWR_OFF_MSK (((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS) +#define PDS_CR_PDS_WB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS)) +#define PDS_CR_PDS_WB_RESET PDS_CR_PDS_WB_RESET +#define PDS_CR_PDS_WB_RESET_POS (13U) +#define PDS_CR_PDS_WB_RESET_LEN (1U) +#define PDS_CR_PDS_WB_RESET_MSK (((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS) +#define PDS_CR_PDS_WB_RESET_UMSK (~(((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS)) +#define PDS_CR_PDS_WB_MEM_STBY PDS_CR_PDS_WB_MEM_STBY +#define PDS_CR_PDS_WB_MEM_STBY_POS (14U) +#define PDS_CR_PDS_WB_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_WB_MEM_STBY_MSK (((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS) +#define PDS_CR_PDS_WB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS)) +#define PDS_CR_PDS_WB_GATE_CLK PDS_CR_PDS_WB_GATE_CLK +#define PDS_CR_PDS_WB_GATE_CLK_POS (15U) +#define PDS_CR_PDS_WB_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_WB_GATE_CLK_MSK (((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS) +#define PDS_CR_PDS_WB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS)) +#define PDS_CR_PDS_MISC_PWR_OFF PDS_CR_PDS_MISC_PWR_OFF +#define PDS_CR_PDS_MISC_PWR_OFF_POS (24U) +#define PDS_CR_PDS_MISC_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS) +#define PDS_CR_PDS_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)) +#define PDS_CR_PDS_MISC_RESET PDS_CR_PDS_MISC_RESET +#define PDS_CR_PDS_MISC_RESET_POS (25U) +#define PDS_CR_PDS_MISC_RESET_LEN (1U) +#define PDS_CR_PDS_MISC_RESET_MSK (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS) +#define PDS_CR_PDS_MISC_RESET_UMSK (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)) +#define PDS_CR_PDS_MISC_MEM_STBY PDS_CR_PDS_MISC_MEM_STBY +#define PDS_CR_PDS_MISC_MEM_STBY_POS (26U) +#define PDS_CR_PDS_MISC_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS) +#define PDS_CR_PDS_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)) +#define PDS_CR_PDS_MISC_GATE_CLK PDS_CR_PDS_MISC_GATE_CLK +#define PDS_CR_PDS_MISC_GATE_CLK_POS (27U) +#define PDS_CR_PDS_MISC_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS) +#define PDS_CR_PDS_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)) + +/* 0x1C : pds_stat */ +#define PDS_STAT_OFFSET (0x1C) +#define PDS_RO_PDS_STATE PDS_RO_PDS_STATE +#define PDS_RO_PDS_STATE_POS (0U) +#define PDS_RO_PDS_STATE_LEN (4U) +#define PDS_RO_PDS_STATE_MSK (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS) +#define PDS_RO_PDS_STATE_UMSK (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)) +#define PDS_RO_PDS_RF_STATE PDS_RO_PDS_RF_STATE +#define PDS_RO_PDS_RF_STATE_POS (8U) +#define PDS_RO_PDS_RF_STATE_LEN (4U) +#define PDS_RO_PDS_RF_STATE_MSK (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS) +#define PDS_RO_PDS_RF_STATE_UMSK (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)) +#define PDS_RO_PDS_PLL_STATE PDS_RO_PDS_PLL_STATE +#define PDS_RO_PDS_PLL_STATE_POS (16U) +#define PDS_RO_PDS_PLL_STATE_LEN (2U) +#define PDS_RO_PDS_PLL_STATE_MSK (((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS) +#define PDS_RO_PDS_PLL_STATE_UMSK (~(((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS)) + +/* 0x20 : pds_ram1 */ +#define PDS_RAM1_OFFSET (0x20) +#define PDS_CR_NP_SRAM_PWR PDS_CR_NP_SRAM_PWR +#define PDS_CR_NP_SRAM_PWR_POS (0U) +#define PDS_CR_NP_SRAM_PWR_LEN (8U) +#define PDS_CR_NP_SRAM_PWR_MSK (((1U << PDS_CR_NP_SRAM_PWR_LEN) - 1) << PDS_CR_NP_SRAM_PWR_POS) +#define PDS_CR_NP_SRAM_PWR_UMSK (~(((1U << PDS_CR_NP_SRAM_PWR_LEN) - 1) << PDS_CR_NP_SRAM_PWR_POS)) + +/* 0x300 : rc32m_ctrl0 */ +#define PDS_RC32M_CTRL0_OFFSET (0x300) +#define PDS_RC32M_CAL_DONE PDS_RC32M_CAL_DONE +#define PDS_RC32M_CAL_DONE_POS (0U) +#define PDS_RC32M_CAL_DONE_LEN (1U) +#define PDS_RC32M_CAL_DONE_MSK (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS) +#define PDS_RC32M_CAL_DONE_UMSK (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)) +#define PDS_RC32M_RDY PDS_RC32M_RDY +#define PDS_RC32M_RDY_POS (1U) +#define PDS_RC32M_RDY_LEN (1U) +#define PDS_RC32M_RDY_MSK (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS) +#define PDS_RC32M_RDY_UMSK (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)) +#define PDS_RC32M_CAL_INPROGRESS PDS_RC32M_CAL_INPROGRESS +#define PDS_RC32M_CAL_INPROGRESS_POS (2U) +#define PDS_RC32M_CAL_INPROGRESS_LEN (1U) +#define PDS_RC32M_CAL_INPROGRESS_MSK (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS) +#define PDS_RC32M_CAL_INPROGRESS_UMSK (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)) +#define PDS_RC32M_CAL_DIV PDS_RC32M_CAL_DIV +#define PDS_RC32M_CAL_DIV_POS (3U) +#define PDS_RC32M_CAL_DIV_LEN (2U) +#define PDS_RC32M_CAL_DIV_MSK (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS) +#define PDS_RC32M_CAL_DIV_UMSK (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)) +#define PDS_RC32M_CAL_PRECHARGE PDS_RC32M_CAL_PRECHARGE +#define PDS_RC32M_CAL_PRECHARGE_POS (5U) +#define PDS_RC32M_CAL_PRECHARGE_LEN (1U) +#define PDS_RC32M_CAL_PRECHARGE_MSK (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS) +#define PDS_RC32M_CAL_PRECHARGE_UMSK (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)) +#define PDS_RC32M_DIG_CODE_FR_CAL PDS_RC32M_DIG_CODE_FR_CAL +#define PDS_RC32M_DIG_CODE_FR_CAL_POS (6U) +#define PDS_RC32M_DIG_CODE_FR_CAL_LEN (8U) +#define PDS_RC32M_DIG_CODE_FR_CAL_MSK (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS) +#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)) +#define PDS_RC32M_ALLOW_CAL PDS_RC32M_ALLOW_CAL +#define PDS_RC32M_ALLOW_CAL_POS (17U) +#define PDS_RC32M_ALLOW_CAL_LEN (1U) +#define PDS_RC32M_ALLOW_CAL_MSK (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS) +#define PDS_RC32M_ALLOW_CAL_UMSK (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)) +#define PDS_RC32M_REFCLK_HALF PDS_RC32M_REFCLK_HALF +#define PDS_RC32M_REFCLK_HALF_POS (18U) +#define PDS_RC32M_REFCLK_HALF_LEN (1U) +#define PDS_RC32M_REFCLK_HALF_MSK (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS) +#define PDS_RC32M_REFCLK_HALF_UMSK (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)) +#define PDS_RC32M_EXT_CODE_EN PDS_RC32M_EXT_CODE_EN +#define PDS_RC32M_EXT_CODE_EN_POS (19U) +#define PDS_RC32M_EXT_CODE_EN_LEN (1U) +#define PDS_RC32M_EXT_CODE_EN_MSK (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS) +#define PDS_RC32M_EXT_CODE_EN_UMSK (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)) +#define PDS_RC32M_CAL_EN PDS_RC32M_CAL_EN +#define PDS_RC32M_CAL_EN_POS (20U) +#define PDS_RC32M_CAL_EN_LEN (1U) +#define PDS_RC32M_CAL_EN_MSK (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS) +#define PDS_RC32M_CAL_EN_UMSK (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)) +#define PDS_RC32M_PD PDS_RC32M_PD +#define PDS_RC32M_PD_POS (21U) +#define PDS_RC32M_PD_LEN (1U) +#define PDS_RC32M_PD_MSK (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS) +#define PDS_RC32M_PD_UMSK (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)) +#define PDS_RC32M_CODE_FR_EXT PDS_RC32M_CODE_FR_EXT +#define PDS_RC32M_CODE_FR_EXT_POS (22U) +#define PDS_RC32M_CODE_FR_EXT_LEN (8U) +#define PDS_RC32M_CODE_FR_EXT_MSK (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS) +#define PDS_RC32M_CODE_FR_EXT_UMSK (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)) + +/* 0x304 : rc32m_ctrl1 */ +#define PDS_RC32M_CTRL1_OFFSET (0x304) +#define PDS_RC32M_TEST_EN PDS_RC32M_TEST_EN +#define PDS_RC32M_TEST_EN_POS (0U) +#define PDS_RC32M_TEST_EN_LEN (1U) +#define PDS_RC32M_TEST_EN_MSK (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS) +#define PDS_RC32M_TEST_EN_UMSK (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)) +#define PDS_RC32M_SOFT_RST PDS_RC32M_SOFT_RST +#define PDS_RC32M_SOFT_RST_POS (1U) +#define PDS_RC32M_SOFT_RST_LEN (1U) +#define PDS_RC32M_SOFT_RST_MSK (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS) +#define PDS_RC32M_SOFT_RST_UMSK (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)) +#define PDS_RC32M_CLK_SOFT_RST PDS_RC32M_CLK_SOFT_RST +#define PDS_RC32M_CLK_SOFT_RST_POS (2U) +#define PDS_RC32M_CLK_SOFT_RST_LEN (1U) +#define PDS_RC32M_CLK_SOFT_RST_MSK (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS) +#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)) +#define PDS_RC32M_CLK_INV PDS_RC32M_CLK_INV +#define PDS_RC32M_CLK_INV_POS (3U) +#define PDS_RC32M_CLK_INV_LEN (1U) +#define PDS_RC32M_CLK_INV_MSK (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS) +#define PDS_RC32M_CLK_INV_UMSK (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)) +#define PDS_RC32M_CLK_FORCE_ON PDS_RC32M_CLK_FORCE_ON +#define PDS_RC32M_CLK_FORCE_ON_POS (4U) +#define PDS_RC32M_CLK_FORCE_ON_LEN (1U) +#define PDS_RC32M_CLK_FORCE_ON_MSK (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS) +#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)) +#define PDS_RC32M_RESERVED PDS_RC32M_RESERVED +#define PDS_RC32M_RESERVED_POS (24U) +#define PDS_RC32M_RESERVED_LEN (8U) +#define PDS_RC32M_RESERVED_MSK (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS) +#define PDS_RC32M_RESERVED_UMSK (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)) + +/* 0x400 : pu_rst_clkpll */ +#define PDS_PU_RST_CLKPLL_OFFSET (0x400) +#define PDS_CLKPLL_SDM_RESET PDS_CLKPLL_SDM_RESET +#define PDS_CLKPLL_SDM_RESET_POS (0U) +#define PDS_CLKPLL_SDM_RESET_LEN (1U) +#define PDS_CLKPLL_SDM_RESET_MSK (((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS) +#define PDS_CLKPLL_SDM_RESET_UMSK (~(((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS)) +#define PDS_CLKPLL_RESET_POSTDIV PDS_CLKPLL_RESET_POSTDIV +#define PDS_CLKPLL_RESET_POSTDIV_POS (1U) +#define PDS_CLKPLL_RESET_POSTDIV_LEN (1U) +#define PDS_CLKPLL_RESET_POSTDIV_MSK (((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS) +#define PDS_CLKPLL_RESET_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS)) +#define PDS_CLKPLL_RESET_FBDV PDS_CLKPLL_RESET_FBDV +#define PDS_CLKPLL_RESET_FBDV_POS (2U) +#define PDS_CLKPLL_RESET_FBDV_LEN (1U) +#define PDS_CLKPLL_RESET_FBDV_MSK (((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS) +#define PDS_CLKPLL_RESET_FBDV_UMSK (~(((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS)) +#define PDS_CLKPLL_RESET_REFDIV PDS_CLKPLL_RESET_REFDIV +#define PDS_CLKPLL_RESET_REFDIV_POS (3U) +#define PDS_CLKPLL_RESET_REFDIV_LEN (1U) +#define PDS_CLKPLL_RESET_REFDIV_MSK (((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS) +#define PDS_CLKPLL_RESET_REFDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS)) +#define PDS_CLKPLL_PU_POSTDIV PDS_CLKPLL_PU_POSTDIV +#define PDS_CLKPLL_PU_POSTDIV_POS (4U) +#define PDS_CLKPLL_PU_POSTDIV_LEN (1U) +#define PDS_CLKPLL_PU_POSTDIV_MSK (((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS) +#define PDS_CLKPLL_PU_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS)) +#define PDS_CLKPLL_PU_FBDV PDS_CLKPLL_PU_FBDV +#define PDS_CLKPLL_PU_FBDV_POS (5U) +#define PDS_CLKPLL_PU_FBDV_LEN (1U) +#define PDS_CLKPLL_PU_FBDV_MSK (((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS) +#define PDS_CLKPLL_PU_FBDV_UMSK (~(((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS)) +#define PDS_CLKPLL_PU_CLAMP_OP PDS_CLKPLL_PU_CLAMP_OP +#define PDS_CLKPLL_PU_CLAMP_OP_POS (6U) +#define PDS_CLKPLL_PU_CLAMP_OP_LEN (1U) +#define PDS_CLKPLL_PU_CLAMP_OP_MSK (((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS) +#define PDS_CLKPLL_PU_CLAMP_OP_UMSK (~(((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS)) +#define PDS_CLKPLL_PU_PFD PDS_CLKPLL_PU_PFD +#define PDS_CLKPLL_PU_PFD_POS (7U) +#define PDS_CLKPLL_PU_PFD_LEN (1U) +#define PDS_CLKPLL_PU_PFD_MSK (((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS) +#define PDS_CLKPLL_PU_PFD_UMSK (~(((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS)) +#define PDS_CLKPLL_PU_CP PDS_CLKPLL_PU_CP +#define PDS_CLKPLL_PU_CP_POS (8U) +#define PDS_CLKPLL_PU_CP_LEN (1U) +#define PDS_CLKPLL_PU_CP_MSK (((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS) +#define PDS_CLKPLL_PU_CP_UMSK (~(((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS)) +#define PDS_PU_CLKPLL_SFREG PDS_PU_CLKPLL_SFREG +#define PDS_PU_CLKPLL_SFREG_POS (9U) +#define PDS_PU_CLKPLL_SFREG_LEN (1U) +#define PDS_PU_CLKPLL_SFREG_MSK (((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS) +#define PDS_PU_CLKPLL_SFREG_UMSK (~(((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS)) +#define PDS_PU_CLKPLL PDS_PU_CLKPLL +#define PDS_PU_CLKPLL_POS (10U) +#define PDS_PU_CLKPLL_LEN (1U) +#define PDS_PU_CLKPLL_MSK (((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS) +#define PDS_PU_CLKPLL_UMSK (~(((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS)) + +/* 0x404 : clkpll_top_ctrl */ +#define PDS_CLKPLL_TOP_CTRL_OFFSET (0x404) +#define PDS_CLKPLL_POSTDIV PDS_CLKPLL_POSTDIV +#define PDS_CLKPLL_POSTDIV_POS (0U) +#define PDS_CLKPLL_POSTDIV_LEN (7U) +#define PDS_CLKPLL_POSTDIV_MSK (((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS) +#define PDS_CLKPLL_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS)) +#define PDS_CLKPLL_REFDIV_RATIO PDS_CLKPLL_REFDIV_RATIO +#define PDS_CLKPLL_REFDIV_RATIO_POS (8U) +#define PDS_CLKPLL_REFDIV_RATIO_LEN (4U) +#define PDS_CLKPLL_REFDIV_RATIO_MSK (((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS) +#define PDS_CLKPLL_REFDIV_RATIO_UMSK (~(((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS)) +#define PDS_CLKPLL_XTAL_RC32M_SEL PDS_CLKPLL_XTAL_RC32M_SEL +#define PDS_CLKPLL_XTAL_RC32M_SEL_POS (12U) +#define PDS_CLKPLL_XTAL_RC32M_SEL_LEN (1U) +#define PDS_CLKPLL_XTAL_RC32M_SEL_MSK (((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS) +#define PDS_CLKPLL_XTAL_RC32M_SEL_UMSK (~(((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS)) +#define PDS_CLKPLL_REFCLK_SEL PDS_CLKPLL_REFCLK_SEL +#define PDS_CLKPLL_REFCLK_SEL_POS (16U) +#define PDS_CLKPLL_REFCLK_SEL_LEN (1U) +#define PDS_CLKPLL_REFCLK_SEL_MSK (((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS) +#define PDS_CLKPLL_REFCLK_SEL_UMSK (~(((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS)) +#define PDS_CLKPLL_VG11_SEL PDS_CLKPLL_VG11_SEL +#define PDS_CLKPLL_VG11_SEL_POS (20U) +#define PDS_CLKPLL_VG11_SEL_LEN (2U) +#define PDS_CLKPLL_VG11_SEL_MSK (((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS) +#define PDS_CLKPLL_VG11_SEL_UMSK (~(((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS)) +#define PDS_CLKPLL_VG13_SEL PDS_CLKPLL_VG13_SEL +#define PDS_CLKPLL_VG13_SEL_POS (24U) +#define PDS_CLKPLL_VG13_SEL_LEN (2U) +#define PDS_CLKPLL_VG13_SEL_MSK (((1U << PDS_CLKPLL_VG13_SEL_LEN) - 1) << PDS_CLKPLL_VG13_SEL_POS) +#define PDS_CLKPLL_VG13_SEL_UMSK (~(((1U << PDS_CLKPLL_VG13_SEL_LEN) - 1) << PDS_CLKPLL_VG13_SEL_POS)) + +/* 0x408 : clkpll_cp */ +#define PDS_CLKPLL_CP_OFFSET (0x408) +#define PDS_CLKPLL_SEL_CP_BIAS PDS_CLKPLL_SEL_CP_BIAS +#define PDS_CLKPLL_SEL_CP_BIAS_POS (0U) +#define PDS_CLKPLL_SEL_CP_BIAS_LEN (1U) +#define PDS_CLKPLL_SEL_CP_BIAS_MSK (((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS) +#define PDS_CLKPLL_SEL_CP_BIAS_UMSK (~(((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS)) +#define PDS_CLKPLL_ICP_5U PDS_CLKPLL_ICP_5U +#define PDS_CLKPLL_ICP_5U_POS (4U) +#define PDS_CLKPLL_ICP_5U_LEN (2U) +#define PDS_CLKPLL_ICP_5U_MSK (((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS) +#define PDS_CLKPLL_ICP_5U_UMSK (~(((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS)) +#define PDS_CLKPLL_ICP_1U PDS_CLKPLL_ICP_1U +#define PDS_CLKPLL_ICP_1U_POS (6U) +#define PDS_CLKPLL_ICP_1U_LEN (2U) +#define PDS_CLKPLL_ICP_1U_MSK (((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS) +#define PDS_CLKPLL_ICP_1U_UMSK (~(((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS)) +#define PDS_CLKPLL_INT_FRAC_SW PDS_CLKPLL_INT_FRAC_SW +#define PDS_CLKPLL_INT_FRAC_SW_POS (8U) +#define PDS_CLKPLL_INT_FRAC_SW_LEN (1U) +#define PDS_CLKPLL_INT_FRAC_SW_MSK (((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS) +#define PDS_CLKPLL_INT_FRAC_SW_UMSK (~(((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS)) +#define PDS_CLKPLL_CP_STARTUP_EN PDS_CLKPLL_CP_STARTUP_EN +#define PDS_CLKPLL_CP_STARTUP_EN_POS (9U) +#define PDS_CLKPLL_CP_STARTUP_EN_LEN (1U) +#define PDS_CLKPLL_CP_STARTUP_EN_MSK (((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS) +#define PDS_CLKPLL_CP_STARTUP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS)) +#define PDS_CLKPLL_CP_OPAMP_EN PDS_CLKPLL_CP_OPAMP_EN +#define PDS_CLKPLL_CP_OPAMP_EN_POS (10U) +#define PDS_CLKPLL_CP_OPAMP_EN_LEN (1U) +#define PDS_CLKPLL_CP_OPAMP_EN_MSK (((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS) +#define PDS_CLKPLL_CP_OPAMP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS)) + +/* 0x40C : clkpll_rz */ +#define PDS_CLKPLL_RZ_OFFSET (0x40C) +#define PDS_CLKPLL_C4_EN PDS_CLKPLL_C4_EN +#define PDS_CLKPLL_C4_EN_POS (0U) +#define PDS_CLKPLL_C4_EN_LEN (1U) +#define PDS_CLKPLL_C4_EN_MSK (((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS) +#define PDS_CLKPLL_C4_EN_UMSK (~(((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS)) +#define PDS_CLKPLL_R4 PDS_CLKPLL_R4 +#define PDS_CLKPLL_R4_POS (4U) +#define PDS_CLKPLL_R4_LEN (2U) +#define PDS_CLKPLL_R4_MSK (((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS) +#define PDS_CLKPLL_R4_UMSK (~(((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS)) +#define PDS_CLKPLL_R4_SHORT PDS_CLKPLL_R4_SHORT +#define PDS_CLKPLL_R4_SHORT_POS (8U) +#define PDS_CLKPLL_R4_SHORT_LEN (1U) +#define PDS_CLKPLL_R4_SHORT_MSK (((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS) +#define PDS_CLKPLL_R4_SHORT_UMSK (~(((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS)) +#define PDS_CLKPLL_C3 PDS_CLKPLL_C3 +#define PDS_CLKPLL_C3_POS (12U) +#define PDS_CLKPLL_C3_LEN (2U) +#define PDS_CLKPLL_C3_MSK (((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS) +#define PDS_CLKPLL_C3_UMSK (~(((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS)) +#define PDS_CLKPLL_CZ PDS_CLKPLL_CZ +#define PDS_CLKPLL_CZ_POS (14U) +#define PDS_CLKPLL_CZ_LEN (2U) +#define PDS_CLKPLL_CZ_MSK (((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS) +#define PDS_CLKPLL_CZ_UMSK (~(((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS)) +#define PDS_CLKPLL_RZ PDS_CLKPLL_RZ +#define PDS_CLKPLL_RZ_POS (16U) +#define PDS_CLKPLL_RZ_LEN (3U) +#define PDS_CLKPLL_RZ_MSK (((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS) +#define PDS_CLKPLL_RZ_UMSK (~(((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS)) + +/* 0x410 : clkpll_fbdv */ +#define PDS_CLKPLL_FBDV_OFFSET (0x410) +#define PDS_CLKPLL_SEL_SAMPLE_CLK PDS_CLKPLL_SEL_SAMPLE_CLK +#define PDS_CLKPLL_SEL_SAMPLE_CLK_POS (0U) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_LEN (2U) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_MSK (((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS)) +#define PDS_CLKPLL_SEL_FB_CLK PDS_CLKPLL_SEL_FB_CLK +#define PDS_CLKPLL_SEL_FB_CLK_POS (2U) +#define PDS_CLKPLL_SEL_FB_CLK_LEN (2U) +#define PDS_CLKPLL_SEL_FB_CLK_MSK (((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS) +#define PDS_CLKPLL_SEL_FB_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS)) + +/* 0x414 : clkpll_vco */ +#define PDS_CLKPLL_VCO_OFFSET (0x414) +#define PDS_CLKPLL_VCO_SPEED PDS_CLKPLL_VCO_SPEED +#define PDS_CLKPLL_VCO_SPEED_POS (0U) +#define PDS_CLKPLL_VCO_SPEED_LEN (3U) +#define PDS_CLKPLL_VCO_SPEED_MSK (((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS) +#define PDS_CLKPLL_VCO_SPEED_UMSK (~(((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS)) +#define PDS_CLKPLL_SHRTR PDS_CLKPLL_SHRTR +#define PDS_CLKPLL_SHRTR_POS (3U) +#define PDS_CLKPLL_SHRTR_LEN (1U) +#define PDS_CLKPLL_SHRTR_MSK (((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS) +#define PDS_CLKPLL_SHRTR_UMSK (~(((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS)) + +/* 0x418 : clkpll_sdm */ +#define PDS_CLKPLL_SDM_OFFSET (0x418) +#define PDS_CLKPLL_SDMIN PDS_CLKPLL_SDMIN +#define PDS_CLKPLL_SDMIN_POS (0U) +#define PDS_CLKPLL_SDMIN_LEN (24U) +#define PDS_CLKPLL_SDMIN_MSK (((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS) +#define PDS_CLKPLL_SDMIN_UMSK (~(((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS)) +#define PDS_CLKPLL_DITHER_SEL PDS_CLKPLL_DITHER_SEL +#define PDS_CLKPLL_DITHER_SEL_POS (24U) +#define PDS_CLKPLL_DITHER_SEL_LEN (2U) +#define PDS_CLKPLL_DITHER_SEL_MSK (((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS) +#define PDS_CLKPLL_DITHER_SEL_UMSK (~(((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS)) +#define PDS_CLKPLL_SDM_FLAG PDS_CLKPLL_SDM_FLAG +#define PDS_CLKPLL_SDM_FLAG_POS (28U) +#define PDS_CLKPLL_SDM_FLAG_LEN (1U) +#define PDS_CLKPLL_SDM_FLAG_MSK (((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS) +#define PDS_CLKPLL_SDM_FLAG_UMSK (~(((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS)) +#define PDS_CLKPLL_SDM_BYPASS PDS_CLKPLL_SDM_BYPASS +#define PDS_CLKPLL_SDM_BYPASS_POS (29U) +#define PDS_CLKPLL_SDM_BYPASS_LEN (1U) +#define PDS_CLKPLL_SDM_BYPASS_MSK (((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS) +#define PDS_CLKPLL_SDM_BYPASS_UMSK (~(((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS)) + +/* 0x41C : clkpll_output_en */ +#define PDS_CLKPLL_OUTPUT_EN_OFFSET (0x41C) +#define PDS_CLKPLL_EN_480M PDS_CLKPLL_EN_480M +#define PDS_CLKPLL_EN_480M_POS (0U) +#define PDS_CLKPLL_EN_480M_LEN (1U) +#define PDS_CLKPLL_EN_480M_MSK (((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS) +#define PDS_CLKPLL_EN_480M_UMSK (~(((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS)) +#define PDS_CLKPLL_EN_240M PDS_CLKPLL_EN_240M +#define PDS_CLKPLL_EN_240M_POS (1U) +#define PDS_CLKPLL_EN_240M_LEN (1U) +#define PDS_CLKPLL_EN_240M_MSK (((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS) +#define PDS_CLKPLL_EN_240M_UMSK (~(((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS)) +#define PDS_CLKPLL_EN_192M PDS_CLKPLL_EN_192M +#define PDS_CLKPLL_EN_192M_POS (2U) +#define PDS_CLKPLL_EN_192M_LEN (1U) +#define PDS_CLKPLL_EN_192M_MSK (((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS) +#define PDS_CLKPLL_EN_192M_UMSK (~(((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS)) +#define PDS_CLKPLL_EN_160M PDS_CLKPLL_EN_160M +#define PDS_CLKPLL_EN_160M_POS (3U) +#define PDS_CLKPLL_EN_160M_LEN (1U) +#define PDS_CLKPLL_EN_160M_MSK (((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS) +#define PDS_CLKPLL_EN_160M_UMSK (~(((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS)) +#define PDS_CLKPLL_EN_120M PDS_CLKPLL_EN_120M +#define PDS_CLKPLL_EN_120M_POS (4U) +#define PDS_CLKPLL_EN_120M_LEN (1U) +#define PDS_CLKPLL_EN_120M_MSK (((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS) +#define PDS_CLKPLL_EN_120M_UMSK (~(((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS)) +#define PDS_CLKPLL_EN_96M PDS_CLKPLL_EN_96M +#define PDS_CLKPLL_EN_96M_POS (5U) +#define PDS_CLKPLL_EN_96M_LEN (1U) +#define PDS_CLKPLL_EN_96M_MSK (((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS) +#define PDS_CLKPLL_EN_96M_UMSK (~(((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS)) +#define PDS_CLKPLL_EN_80M PDS_CLKPLL_EN_80M +#define PDS_CLKPLL_EN_80M_POS (6U) +#define PDS_CLKPLL_EN_80M_LEN (1U) +#define PDS_CLKPLL_EN_80M_MSK (((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS) +#define PDS_CLKPLL_EN_80M_UMSK (~(((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS)) +#define PDS_CLKPLL_EN_48M PDS_CLKPLL_EN_48M +#define PDS_CLKPLL_EN_48M_POS (7U) +#define PDS_CLKPLL_EN_48M_LEN (1U) +#define PDS_CLKPLL_EN_48M_MSK (((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS) +#define PDS_CLKPLL_EN_48M_UMSK (~(((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS)) +#define PDS_CLKPLL_EN_32M PDS_CLKPLL_EN_32M +#define PDS_CLKPLL_EN_32M_POS (8U) +#define PDS_CLKPLL_EN_32M_LEN (1U) +#define PDS_CLKPLL_EN_32M_MSK (((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS) +#define PDS_CLKPLL_EN_32M_UMSK (~(((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS)) +#define PDS_CLKPLL_EN_DIV2_480M PDS_CLKPLL_EN_DIV2_480M +#define PDS_CLKPLL_EN_DIV2_480M_POS (9U) +#define PDS_CLKPLL_EN_DIV2_480M_LEN (1U) +#define PDS_CLKPLL_EN_DIV2_480M_MSK (((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS) +#define PDS_CLKPLL_EN_DIV2_480M_UMSK (~(((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS)) + +struct pds_reg { + /* 0x0 : PDS_CTL */ + union { + struct + { + uint32_t pds_start_ps : 1; /* [ 0], w1p, 0x0 */ + uint32_t cr_sleep_forever : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_xtal_force_off : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_wifi_pds_save_state : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_pds_pd_dcdc18 : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_pds_pd_bg_sys : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t cr_pds_gate_clk : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_pds_mem_stby : 1; /* [ 9], r/w, 0x1 */ + uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ + uint32_t cr_pds_iso_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_pds_wait_xtal_rdy : 1; /* [ 12], r/w, 0x0 */ + uint32_t cr_pds_pwr_off : 1; /* [ 13], r/w, 0x1 */ + uint32_t cr_pds_pd_xtal : 1; /* [ 14], r/w, 0x1 */ + uint32_t cr_pds_soc_enb_force_on : 1; /* [ 15], r/w, 0x0 */ + uint32_t cr_pds_rst_soc_en : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_pds_rc32m_off_dis : 1; /* [ 17], r/w, 0x0 */ + uint32_t cr_pds_ldo_vsel_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_20 : 2; /* [20:19], rsvd, 0x0 */ + uint32_t cr_np_wfi_mask : 1; /* [ 21], r/w, 0x0 */ + uint32_t cr_pds_pd_ldo11 : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t cr_pds_ldo_vol : 4; /* [27:24], r/w, 0xa */ + uint32_t cr_pds_ctrl_rf : 2; /* [29:28], r/w, 0x1 */ + uint32_t cr_pds_ctrl_pll : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL; + + /* 0x4 : PDS_TIME1 */ + union { + struct + { + uint32_t cr_sleep_duration : 32; /* [31: 0], r/w, 0xca8 */ + } BF; + uint32_t WORD; + } PDS_TIME1; + + /* 0x8 reserved */ + uint8_t RESERVED0x8[4]; + + /* 0xC : PDS_INT */ + union { + struct + { + uint32_t ro_pds_wake_int : 1; /* [ 0], r, 0x0 */ + uint32_t ro_pds_irq_in : 1; /* [ 1], r, 0x0 */ + uint32_t ro_pds_rf_done_int : 1; /* [ 2], r, 0x0 */ + uint32_t ro_pds_pll_done_int : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t cr_pds_wake_int_mask : 1; /* [ 8], r/w, 0x0 */ + uint32_t cr_pds_irq_in_dis : 1; /* [ 9], r/w, 0x0 */ + uint32_t cr_pds_rf_done_int_mask : 1; /* [ 10], r/w, 0x0 */ + uint32_t cr_pds_pll_done_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t cr_pds_int_clr : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_INT; + + /* 0x10 : PDS_CTL2 */ + union { + struct + { + uint32_t cr_pds_force_np_pwr_off : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_pwr_off : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t cr_pds_force_np_iso_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_iso_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cr_pds_force_np_pds_rst : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_pds_rst : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t cr_pds_force_np_mem_stby : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_mem_stby : 1; /* [ 14], r/w, 0x0 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t cr_pds_force_np_gate_clk : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_gate_clk : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL2; + + /* 0x14 : PDS_CTL3 */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_pwr_off : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_iso_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_pds_rst : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_9 : 2; /* [ 9: 8], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_mem_stby : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_12 : 2; /* [12:11], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_gate_clk : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_23 : 10; /* [23:14], rsvd, 0x0 */ + uint32_t cr_pds_np_iso_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_26 : 2; /* [26:25], rsvd, 0x0 */ + uint32_t cr_pds_wb_iso_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t reserved_28_29 : 2; /* [29:28], rsvd, 0x0 */ + uint32_t cr_pds_misc_iso_en : 1; /* [ 30], r/w, 0x1 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL3; + + /* 0x18 : PDS_CTL4 */ + union { + struct + { + uint32_t cr_pds_np_pwr_off : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_pds_np_reset : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_pds_np_mem_stby : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_pds_np_gate_clk : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_11 : 8; /* [11: 4], rsvd, 0x0 */ + uint32_t cr_pds_wb_pwr_off : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_pds_wb_reset : 1; /* [ 13], r/w, 0x1 */ + uint32_t cr_pds_wb_mem_stby : 1; /* [ 14], r/w, 0x1 */ + uint32_t cr_pds_wb_gate_clk : 1; /* [ 15], r/w, 0x1 */ + uint32_t reserved_16_23 : 8; /* [23:16], rsvd, 0x0 */ + uint32_t cr_pds_misc_pwr_off : 1; /* [ 24], r/w, 0x1 */ + uint32_t cr_pds_misc_reset : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_pds_misc_mem_stby : 1; /* [ 26], r/w, 0x1 */ + uint32_t cr_pds_misc_gate_clk : 1; /* [ 27], r/w, 0x1 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL4; + + /* 0x1C : pds_stat */ + union { + struct + { + uint32_t ro_pds_state : 4; /* [ 3: 0], r, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t ro_pds_rf_state : 4; /* [11: 8], r, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t ro_pds_pll_state : 2; /* [17:16], r, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pds_stat; + + /* 0x20 : pds_ram1 */ + union { + struct + { + uint32_t cr_np_sram_pwr : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pds_ram1; + + /* 0x24 reserved */ + uint8_t RESERVED0x24[732]; + + /* 0x300 : rc32m_ctrl0 */ + union { + struct + { + uint32_t rc32m_cal_done : 1; /* [ 0], r, 0x0 */ + uint32_t rc32m_rdy : 1; /* [ 1], r, 0x0 */ + uint32_t rc32m_cal_inprogress : 1; /* [ 2], r, 0x0 */ + uint32_t rc32m_cal_div : 2; /* [ 4: 3], r/w, 0x3 */ + uint32_t rc32m_cal_precharge : 1; /* [ 5], r, 0x0 */ + uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6], r, 0x0 */ + uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */ + uint32_t rc32m_allow_cal : 1; /* [ 17], r/w, 0x0 */ + uint32_t rc32m_refclk_half : 1; /* [ 18], r/w, 0x0 */ + uint32_t rc32m_ext_code_en : 1; /* [ 19], r/w, 0x1 */ + uint32_t rc32m_cal_en : 1; /* [ 20], r/w, 0x0 */ + uint32_t rc32m_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t rc32m_code_fr_ext : 8; /* [29:22], r/w, 0x60 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rc32m_ctrl0; + + /* 0x304 : rc32m_ctrl1 */ + union { + struct + { + uint32_t rc32m_test_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t rc32m_soft_rst : 1; /* [ 1], r/w, 0x0 */ + uint32_t rc32m_clk_soft_rst : 1; /* [ 2], r/w, 0x0 */ + uint32_t rc32m_clk_inv : 1; /* [ 3], r/w, 0x0 */ + uint32_t rc32m_clk_force_on : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_23 : 19; /* [23: 5], rsvd, 0x0 */ + uint32_t rc32m_reserved : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } rc32m_ctrl1; + + /* 0x308 reserved */ + uint8_t RESERVED0x308[248]; + + /* 0x400 : pu_rst_clkpll */ + union { + struct + { + uint32_t clkpll_sdm_reset : 1; /* [ 0], r/w, 0x0 */ + uint32_t clkpll_reset_postdiv : 1; /* [ 1], r/w, 0x0 */ + uint32_t clkpll_reset_fbdv : 1; /* [ 2], r/w, 0x0 */ + uint32_t clkpll_reset_refdiv : 1; /* [ 3], r/w, 0x0 */ + uint32_t clkpll_pu_postdiv : 1; /* [ 4], r/w, 0x1 */ + uint32_t clkpll_pu_fbdv : 1; /* [ 5], r/w, 0x1 */ + uint32_t clkpll_pu_clamp_op : 1; /* [ 6], r/w, 0x1 */ + uint32_t clkpll_pu_pfd : 1; /* [ 7], r/w, 0x1 */ + uint32_t clkpll_pu_cp : 1; /* [ 8], r/w, 0x1 */ + uint32_t pu_clkpll_sfreg : 1; /* [ 9], r/w, 0x0 */ + uint32_t pu_clkpll : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pu_rst_clkpll; + + /* 0x404 : clkpll_top_ctrl */ + union { + struct + { + uint32_t clkpll_postdiv : 7; /* [ 6: 0], r/w, 0x14 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t clkpll_refdiv_ratio : 4; /* [11: 8], r/w, 0x4 */ + uint32_t clkpll_xtal_rc32m_sel : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t clkpll_refclk_sel : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ + uint32_t clkpll_vg11_sel : 2; /* [21:20], r/w, 0x1 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t clkpll_vg13_sel : 2; /* [25:24], r/w, 0x1 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_top_ctrl; + + /* 0x408 : clkpll_cp */ + union { + struct + { + uint32_t clkpll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t clkpll_icp_5u : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t clkpll_icp_1u : 2; /* [ 7: 6], r/w, 0x1 */ + uint32_t clkpll_int_frac_sw : 1; /* [ 8], r/w, 0x1 */ + uint32_t clkpll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */ + uint32_t clkpll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_cp; + + /* 0x40C : clkpll_rz */ + union { + struct + { + uint32_t clkpll_c4_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t clkpll_r4 : 2; /* [ 5: 4], r/w, 0x2 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t clkpll_r4_short : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t clkpll_c3 : 2; /* [13:12], r/w, 0x2 */ + uint32_t clkpll_cz : 2; /* [15:14], r/w, 0x2 */ + uint32_t clkpll_rz : 3; /* [18:16], r/w, 0x5 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_rz; + + /* 0x410 : clkpll_fbdv */ + union { + struct + { + uint32_t clkpll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */ + uint32_t clkpll_sel_fb_clk : 2; /* [ 3: 2], r/w, 0x1 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_fbdv; + + /* 0x414 : clkpll_vco */ + union { + struct + { + uint32_t clkpll_vco_speed : 3; /* [ 2: 0], r/w, 0x7 */ + uint32_t clkpll_shrtr : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_vco; + + /* 0x418 : clkpll_sdm */ + union { + struct + { + uint32_t clkpll_sdmin : 24; /* [23: 0], r/w, 0x600000 */ + uint32_t clkpll_dither_sel : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t clkpll_sdm_flag : 1; /* [ 28], r/w, 0x1 */ + uint32_t clkpll_sdm_bypass : 1; /* [ 29], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_sdm; + + /* 0x41C : clkpll_output_en */ + union { + struct + { + uint32_t clkpll_en_480m : 1; /* [ 0], r/w, 0x0 */ + uint32_t clkpll_en_240m : 1; /* [ 1], r/w, 0x0 */ + uint32_t clkpll_en_192m : 1; /* [ 2], r/w, 0x0 */ + uint32_t clkpll_en_160m : 1; /* [ 3], r/w, 0x0 */ + uint32_t clkpll_en_120m : 1; /* [ 4], r/w, 0x0 */ + uint32_t clkpll_en_96m : 1; /* [ 5], r/w, 0x0 */ + uint32_t clkpll_en_80m : 1; /* [ 6], r/w, 0x0 */ + uint32_t clkpll_en_48m : 1; /* [ 7], r/w, 0x0 */ + uint32_t clkpll_en_32m : 1; /* [ 8], r/w, 0x1 */ + uint32_t clkpll_en_div2_480m : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_output_en; +}; + +typedef volatile struct pds_reg pds_reg_t; + +#endif /* __PDS_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/pwm_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/pwm_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..273f7485400152667bc52b19cc24c5009775c189 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/pwm_reg.h @@ -0,0 +1,993 @@ +/** + ****************************************************************************** + * @file pwm_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PWM_REG_H__ +#define __PWM_REG_H__ + +#include "bl602.h" + +/* 0x0 : pwm_int_config */ +#define PWM_INT_CONFIG_OFFSET (0x0) +#define PWM_INTERRUPT_STS PWM_INTERRUPT_STS +#define PWM_INTERRUPT_STS_POS (0U) +#define PWM_INTERRUPT_STS_LEN (6U) +#define PWM_INTERRUPT_STS_MSK (((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS) +#define PWM_INTERRUPT_STS_UMSK (~(((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS)) +#define PWM_INT_CLEAR PWM_INT_CLEAR +#define PWM_INT_CLEAR_POS (8U) +#define PWM_INT_CLEAR_LEN (6U) +#define PWM_INT_CLEAR_MSK (((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS) +#define PWM_INT_CLEAR_UMSK (~(((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS)) + +/* 0x20 : pwm0_clkdiv */ +#define PWM0_CLKDIV_OFFSET (0x20) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x24 : pwm0_thre1 */ +#define PWM0_THRE1_OFFSET (0x24) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x28 : pwm0_thre2 */ +#define PWM0_THRE2_OFFSET (0x28) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0x2C : pwm0_period */ +#define PWM0_PERIOD_OFFSET (0x2C) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x30 : pwm0_config */ +#define PWM0_CONFIG_OFFSET (0x30) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x34 : pwm0_interrupt */ +#define PWM0_INTERRUPT_OFFSET (0x34) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +/* 0x40 : pwm1_clkdiv */ +#define PWM1_CLKDIV_OFFSET (0x40) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x44 : pwm1_thre1 */ +#define PWM1_THRE1_OFFSET (0x44) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x48 : pwm1_thre2 */ +#define PWM1_THRE2_OFFSET (0x48) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0x4C : pwm1_period */ +#define PWM1_PERIOD_OFFSET (0x4C) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x50 : pwm1_config */ +#define PWM1_CONFIG_OFFSET (0x50) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x54 : pwm1_interrupt */ +#define PWM1_INTERRUPT_OFFSET (0x54) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +/* 0x60 : pwm2_clkdiv */ +#define PWM2_CLKDIV_OFFSET (0x60) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x64 : pwm2_thre1 */ +#define PWM2_THRE1_OFFSET (0x64) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x68 : pwm2_thre2 */ +#define PWM2_THRE2_OFFSET (0x68) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0x6C : pwm2_period */ +#define PWM2_PERIOD_OFFSET (0x6C) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x70 : pwm2_config */ +#define PWM2_CONFIG_OFFSET (0x70) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x74 : pwm2_interrupt */ +#define PWM2_INTERRUPT_OFFSET (0x74) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +/* 0x80 : pwm3_clkdiv */ +#define PWM3_CLKDIV_OFFSET (0x80) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x84 : pwm3_thre1 */ +#define PWM3_THRE1_OFFSET (0x84) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x88 : pwm3_thre2 */ +#define PWM3_THRE2_OFFSET (0x88) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0x8C : pwm3_period */ +#define PWM3_PERIOD_OFFSET (0x8C) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x90 : pwm3_config */ +#define PWM3_CONFIG_OFFSET (0x90) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x94 : pwm3_interrupt */ +#define PWM3_INTERRUPT_OFFSET (0x94) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +/* 0xA0 : pwm4_clkdiv */ +#define PWM4_CLKDIV_OFFSET (0xA0) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0xA4 : pwm4_thre1 */ +#define PWM4_THRE1_OFFSET (0xA4) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0xA8 : pwm4_thre2 */ +#define PWM4_THRE2_OFFSET (0xA8) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0xAC : pwm4_period */ +#define PWM4_PERIOD_OFFSET (0xAC) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0xB0 : pwm4_config */ +#define PWM4_CONFIG_OFFSET (0xB0) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0xB4 : pwm4_interrupt */ +#define PWM4_INTERRUPT_OFFSET (0xB4) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +struct pwm_reg { + /* 0x0 : pwm_int_config */ + union { + struct + { + uint32_t pwm_interrupt_sts : 6; /* [ 5: 0], r, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t pwm_int_clear : 6; /* [13: 8], w, 0x0 */ + uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_int_config; + + /* 0x4 reserved */ + uint8_t RESERVED0x4[28]; + + /* 0x20 : pwm0_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_clkdiv; + + /* 0x24 : pwm0_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_thre1; + + /* 0x28 : pwm0_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_thre2; + + /* 0x2C : pwm0_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_period; + + /* 0x30 : pwm0_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_config; + + /* 0x34 : pwm0_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_interrupt; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[8]; + + /* 0x40 : pwm1_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_clkdiv; + + /* 0x44 : pwm1_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_thre1; + + /* 0x48 : pwm1_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_thre2; + + /* 0x4C : pwm1_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_period; + + /* 0x50 : pwm1_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_config; + + /* 0x54 : pwm1_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_interrupt; + + /* 0x58 reserved */ + uint8_t RESERVED0x58[8]; + + /* 0x60 : pwm2_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_clkdiv; + + /* 0x64 : pwm2_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_thre1; + + /* 0x68 : pwm2_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_thre2; + + /* 0x6C : pwm2_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_period; + + /* 0x70 : pwm2_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_config; + + /* 0x74 : pwm2_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_interrupt; + + /* 0x78 reserved */ + uint8_t RESERVED0x78[8]; + + /* 0x80 : pwm3_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_clkdiv; + + /* 0x84 : pwm3_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_thre1; + + /* 0x88 : pwm3_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_thre2; + + /* 0x8C : pwm3_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_period; + + /* 0x90 : pwm3_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_config; + + /* 0x94 : pwm3_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_interrupt; + + /* 0x98 reserved */ + uint8_t RESERVED0x98[8]; + + /* 0xA0 : pwm4_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_clkdiv; + + /* 0xA4 : pwm4_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_thre1; + + /* 0xA8 : pwm4_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_thre2; + + /* 0xAC : pwm4_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_period; + + /* 0xB0 : pwm4_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_config; + + /* 0xB4 : pwm4_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_interrupt; +}; + +typedef volatile struct pwm_reg pwm_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : pwm_clkdiv */ +#define PWM_CLKDIV_OFFSET (0x0) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x4 : pwm_thre1 */ +#define PWM_THRE1_OFFSET (0x4) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x8 : pwm_thre2 */ +#define PWM_THRE2_OFFSET (0x8) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0xc : pwm_period */ +#define PWM_PERIOD_OFFSET (0xc) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x10 : pwm_config */ +#define PWM_CONFIG_OFFSET (0x10) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x14 : pwm_interrupt */ +#define PWM_INTERRUPT_OFFSET (0x14) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +struct pwm_channel_reg { + /* 0x0 : pwm_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_clkdiv; + + /* 0x4 : pwm_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_thre1; + + /* 0x8 : pwm_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_thre2; + + /* 0xc : pwm_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_period; + + /* 0x10 : pwm_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_config; + + /* 0x14 : pwm_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_interrupt; +}; + +typedef volatile struct pwm_channel_reg pwm_channel_reg_t; + +#define PWM_CHANNEL_OFFSET 0x20 + +#endif /* __PWM_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sec_dbg_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sec_dbg_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..10d75ce7ace78e4b97a4d06ad93fba4d6b79a41e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sec_dbg_reg.h @@ -0,0 +1,217 @@ +/** + ****************************************************************************** + * @file sec_dbg_reg.h + * @version V1.2 + * @date 2019-11-04 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SEC_DBG_REG_H__ +#define __SEC_DBG_REG_H__ + +#include "bl602.h" + +/* 0x0 : sd_chip_id_low */ +#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0) +#define SEC_DBG_SD_CHIP_ID_LOW SEC_DBG_SD_CHIP_ID_LOW +#define SEC_DBG_SD_CHIP_ID_LOW_POS (0U) +#define SEC_DBG_SD_CHIP_ID_LOW_LEN (32U) +#define SEC_DBG_SD_CHIP_ID_LOW_MSK (((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS) +#define SEC_DBG_SD_CHIP_ID_LOW_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS)) + +/* 0x4 : sd_chip_id_high */ +#define SEC_DBG_SD_CHIP_ID_HIGH_OFFSET (0x4) +#define SEC_DBG_SD_CHIP_ID_HIGH SEC_DBG_SD_CHIP_ID_HIGH +#define SEC_DBG_SD_CHIP_ID_HIGH_POS (0U) +#define SEC_DBG_SD_CHIP_ID_HIGH_LEN (32U) +#define SEC_DBG_SD_CHIP_ID_HIGH_MSK (((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS) +#define SEC_DBG_SD_CHIP_ID_HIGH_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS)) + +/* 0x8 : sd_wifi_mac_low */ +#define SEC_DBG_SD_WIFI_MAC_LOW_OFFSET (0x8) +#define SEC_DBG_SD_WIFI_MAC_LOW SEC_DBG_SD_WIFI_MAC_LOW +#define SEC_DBG_SD_WIFI_MAC_LOW_POS (0U) +#define SEC_DBG_SD_WIFI_MAC_LOW_LEN (32U) +#define SEC_DBG_SD_WIFI_MAC_LOW_MSK (((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS) +#define SEC_DBG_SD_WIFI_MAC_LOW_UMSK (~(((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS)) + +/* 0xC : sd_wifi_mac_high */ +#define SEC_DBG_SD_WIFI_MAC_HIGH_OFFSET (0xC) +#define SEC_DBG_SD_WIFI_MAC_HIGH SEC_DBG_SD_WIFI_MAC_HIGH +#define SEC_DBG_SD_WIFI_MAC_HIGH_POS (0U) +#define SEC_DBG_SD_WIFI_MAC_HIGH_LEN (32U) +#define SEC_DBG_SD_WIFI_MAC_HIGH_MSK (((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS) +#define SEC_DBG_SD_WIFI_MAC_HIGH_UMSK (~(((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS)) + +/* 0x10 : sd_dbg_pwd_low */ +#define SEC_DBG_SD_DBG_PWD_LOW_OFFSET (0x10) +#define SEC_DBG_SD_DBG_PWD_LOW SEC_DBG_SD_DBG_PWD_LOW +#define SEC_DBG_SD_DBG_PWD_LOW_POS (0U) +#define SEC_DBG_SD_DBG_PWD_LOW_LEN (32U) +#define SEC_DBG_SD_DBG_PWD_LOW_MSK (((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS) +#define SEC_DBG_SD_DBG_PWD_LOW_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS)) + +/* 0x14 : sd_dbg_pwd_high */ +#define SEC_DBG_SD_DBG_PWD_HIGH_OFFSET (0x14) +#define SEC_DBG_SD_DBG_PWD_HIGH SEC_DBG_SD_DBG_PWD_HIGH +#define SEC_DBG_SD_DBG_PWD_HIGH_POS (0U) +#define SEC_DBG_SD_DBG_PWD_HIGH_LEN (32U) +#define SEC_DBG_SD_DBG_PWD_HIGH_MSK (((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS) +#define SEC_DBG_SD_DBG_PWD_HIGH_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS)) + +/* 0x18 : sd_status */ +#define SEC_DBG_SD_STATUS_OFFSET (0x18) +#define SEC_DBG_SD_DBG_PWD_BUSY SEC_DBG_SD_DBG_PWD_BUSY +#define SEC_DBG_SD_DBG_PWD_BUSY_POS (0U) +#define SEC_DBG_SD_DBG_PWD_BUSY_LEN (1U) +#define SEC_DBG_SD_DBG_PWD_BUSY_MSK (((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS) +#define SEC_DBG_SD_DBG_PWD_BUSY_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS)) +#define SEC_DBG_SD_DBG_PWD_TRIG SEC_DBG_SD_DBG_PWD_TRIG +#define SEC_DBG_SD_DBG_PWD_TRIG_POS (1U) +#define SEC_DBG_SD_DBG_PWD_TRIG_LEN (1U) +#define SEC_DBG_SD_DBG_PWD_TRIG_MSK (((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS) +#define SEC_DBG_SD_DBG_PWD_TRIG_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS)) +#define SEC_DBG_SD_DBG_CCI_READ_EN SEC_DBG_SD_DBG_CCI_READ_EN +#define SEC_DBG_SD_DBG_CCI_READ_EN_POS (2U) +#define SEC_DBG_SD_DBG_CCI_READ_EN_LEN (1U) +#define SEC_DBG_SD_DBG_CCI_READ_EN_MSK (((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS) +#define SEC_DBG_SD_DBG_CCI_READ_EN_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS)) +#define SEC_DBG_SD_DBG_CCI_CLK_SEL SEC_DBG_SD_DBG_CCI_CLK_SEL +#define SEC_DBG_SD_DBG_CCI_CLK_SEL_POS (3U) +#define SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN (1U) +#define SEC_DBG_SD_DBG_CCI_CLK_SEL_MSK (((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS) +#define SEC_DBG_SD_DBG_CCI_CLK_SEL_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS)) +#define SEC_DBG_SD_DBG_PWD_CNT SEC_DBG_SD_DBG_PWD_CNT +#define SEC_DBG_SD_DBG_PWD_CNT_POS (4U) +#define SEC_DBG_SD_DBG_PWD_CNT_LEN (20U) +#define SEC_DBG_SD_DBG_PWD_CNT_MSK (((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS) +#define SEC_DBG_SD_DBG_PWD_CNT_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS)) +#define SEC_DBG_SD_DBG_MODE SEC_DBG_SD_DBG_MODE +#define SEC_DBG_SD_DBG_MODE_POS (24U) +#define SEC_DBG_SD_DBG_MODE_LEN (4U) +#define SEC_DBG_SD_DBG_MODE_MSK (((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS) +#define SEC_DBG_SD_DBG_MODE_UMSK (~(((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS)) +#define SEC_DBG_SD_DBG_ENA SEC_DBG_SD_DBG_ENA +#define SEC_DBG_SD_DBG_ENA_POS (28U) +#define SEC_DBG_SD_DBG_ENA_LEN (4U) +#define SEC_DBG_SD_DBG_ENA_MSK (((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS) +#define SEC_DBG_SD_DBG_ENA_UMSK (~(((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS)) + +/* 0x1C : sd_dbg_reserved */ +#define SEC_DBG_SD_DBG_RESERVED_OFFSET (0x1C) +#define SEC_DBG_SD_DBG_RESERVED SEC_DBG_SD_DBG_RESERVED +#define SEC_DBG_SD_DBG_RESERVED_POS (0U) +#define SEC_DBG_SD_DBG_RESERVED_LEN (32U) +#define SEC_DBG_SD_DBG_RESERVED_MSK (((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS) +#define SEC_DBG_SD_DBG_RESERVED_UMSK (~(((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS)) + +struct sec_dbg_reg { + /* 0x0 : sd_chip_id_low */ + union { + struct + { + uint32_t sd_chip_id_low : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_chip_id_low; + + /* 0x4 : sd_chip_id_high */ + union { + struct + { + uint32_t sd_chip_id_high : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_chip_id_high; + + /* 0x8 : sd_wifi_mac_low */ + union { + struct + { + uint32_t sd_wifi_mac_low : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_wifi_mac_low; + + /* 0xC : sd_wifi_mac_high */ + union { + struct + { + uint32_t sd_wifi_mac_high : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_wifi_mac_high; + + /* 0x10 : sd_dbg_pwd_low */ + union { + struct + { + uint32_t sd_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sd_dbg_pwd_low; + + /* 0x14 : sd_dbg_pwd_high */ + union { + struct + { + uint32_t sd_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sd_dbg_pwd_high; + + /* 0x18 : sd_status */ + union { + struct + { + uint32_t sd_dbg_pwd_busy : 1; /* [ 0], r, 0x0 */ + uint32_t sd_dbg_pwd_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t sd_dbg_cci_read_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t sd_dbg_cci_clk_sel : 1; /* [ 3], r/w, 0x0 */ + uint32_t sd_dbg_pwd_cnt : 20; /* [23: 4], r, 0x0 */ + uint32_t sd_dbg_mode : 4; /* [27:24], r, 0x0 */ + uint32_t sd_dbg_ena : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_status; + + /* 0x1C : sd_dbg_reserved */ + union { + struct + { + uint32_t sd_dbg_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } sd_dbg_reserved; +}; + +typedef volatile struct sec_dbg_reg sec_dbg_reg_t; + +#endif /* __SEC_DBG_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sec_eng_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sec_eng_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..e563d86ff98498d0f982ce07aa407c30cf4d1b75 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sec_eng_reg.h @@ -0,0 +1,3529 @@ +/** + ****************************************************************************** + * @file sec_eng_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SEC_ENG_REG_H__ +#define __SEC_ENG_REG_H__ + +#include "bl602.h" + +/* 0x0 : se_sha_0_ctrl */ +#define SEC_ENG_SE_SHA_0_CTRL_OFFSET (0x0) +#define SEC_ENG_SE_SHA_0_BUSY SEC_ENG_SE_SHA_0_BUSY +#define SEC_ENG_SE_SHA_0_BUSY_POS (0U) +#define SEC_ENG_SE_SHA_0_BUSY_LEN (1U) +#define SEC_ENG_SE_SHA_0_BUSY_MSK (((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS) +#define SEC_ENG_SE_SHA_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS)) +#define SEC_ENG_SE_SHA_0_TRIG_1T SEC_ENG_SE_SHA_0_TRIG_1T +#define SEC_ENG_SE_SHA_0_TRIG_1T_POS (1U) +#define SEC_ENG_SE_SHA_0_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_SHA_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS) +#define SEC_ENG_SE_SHA_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS)) +#define SEC_ENG_SE_SHA_0_MODE SEC_ENG_SE_SHA_0_MODE +#define SEC_ENG_SE_SHA_0_MODE_POS (2U) +#define SEC_ENG_SE_SHA_0_MODE_LEN (3U) +#define SEC_ENG_SE_SHA_0_MODE_MSK (((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS) +#define SEC_ENG_SE_SHA_0_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS)) +#define SEC_ENG_SE_SHA_0_EN SEC_ENG_SE_SHA_0_EN +#define SEC_ENG_SE_SHA_0_EN_POS (5U) +#define SEC_ENG_SE_SHA_0_EN_LEN (1U) +#define SEC_ENG_SE_SHA_0_EN_MSK (((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS) +#define SEC_ENG_SE_SHA_0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS)) +#define SEC_ENG_SE_SHA_0_HASH_SEL SEC_ENG_SE_SHA_0_HASH_SEL +#define SEC_ENG_SE_SHA_0_HASH_SEL_POS (6U) +#define SEC_ENG_SE_SHA_0_HASH_SEL_LEN (1U) +#define SEC_ENG_SE_SHA_0_HASH_SEL_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS) +#define SEC_ENG_SE_SHA_0_HASH_SEL_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS)) +#define SEC_ENG_SE_SHA_0_INT SEC_ENG_SE_SHA_0_INT +#define SEC_ENG_SE_SHA_0_INT_POS (8U) +#define SEC_ENG_SE_SHA_0_INT_LEN (1U) +#define SEC_ENG_SE_SHA_0_INT_MSK (((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS) +#define SEC_ENG_SE_SHA_0_INT_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS)) +#define SEC_ENG_SE_SHA_0_INT_CLR_1T SEC_ENG_SE_SHA_0_INT_CLR_1T +#define SEC_ENG_SE_SHA_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_SHA_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_SHA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_SHA_0_INT_SET_1T SEC_ENG_SE_SHA_0_INT_SET_1T +#define SEC_ENG_SE_SHA_0_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_SHA_0_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_SHA_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS) +#define SEC_ENG_SE_SHA_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS)) +#define SEC_ENG_SE_SHA_0_INT_MASK SEC_ENG_SE_SHA_0_INT_MASK +#define SEC_ENG_SE_SHA_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_SHA_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_SHA_0_INT_MASK_MSK (((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS) +#define SEC_ENG_SE_SHA_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS)) +#define SEC_ENG_SE_SHA_0_LINK_MODE SEC_ENG_SE_SHA_0_LINK_MODE +#define SEC_ENG_SE_SHA_0_LINK_MODE_POS (15U) +#define SEC_ENG_SE_SHA_0_LINK_MODE_LEN (1U) +#define SEC_ENG_SE_SHA_0_LINK_MODE_MSK (((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS) +#define SEC_ENG_SE_SHA_0_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS)) +#define SEC_ENG_SE_SHA_0_MSG_LEN SEC_ENG_SE_SHA_0_MSG_LEN +#define SEC_ENG_SE_SHA_0_MSG_LEN_POS (16U) +#define SEC_ENG_SE_SHA_0_MSG_LEN_LEN (16U) +#define SEC_ENG_SE_SHA_0_MSG_LEN_MSK (((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS) +#define SEC_ENG_SE_SHA_0_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS)) + +/* 0x4 : se_sha_0_msa */ +#define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4) +#define SEC_ENG_SE_SHA_0_MSA SEC_ENG_SE_SHA_0_MSA +#define SEC_ENG_SE_SHA_0_MSA_POS (0U) +#define SEC_ENG_SE_SHA_0_MSA_LEN (32U) +#define SEC_ENG_SE_SHA_0_MSA_MSK (((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS) +#define SEC_ENG_SE_SHA_0_MSA_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS)) + +/* 0x8 : se_sha_0_status */ +#define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8) +#define SEC_ENG_SE_SHA_0_STATUS SEC_ENG_SE_SHA_0_STATUS +#define SEC_ENG_SE_SHA_0_STATUS_POS (0U) +#define SEC_ENG_SE_SHA_0_STATUS_LEN (32U) +#define SEC_ENG_SE_SHA_0_STATUS_MSK (((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS) +#define SEC_ENG_SE_SHA_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS)) + +/* 0xC : se_sha_0_endian */ +#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET (0xC) +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN SEC_ENG_SE_SHA_0_DOUT_ENDIAN +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS (0U) +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN (1U) +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS) +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS)) + +/* 0x10 : se_sha_0_hash_l_0 */ +#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10) +#define SEC_ENG_SE_SHA_0_HASH_L_0 SEC_ENG_SE_SHA_0_HASH_L_0 +#define SEC_ENG_SE_SHA_0_HASH_L_0_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_0_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_0_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_0_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS)) + +/* 0x14 : se_sha_0_hash_l_1 */ +#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14) +#define SEC_ENG_SE_SHA_0_HASH_L_1 SEC_ENG_SE_SHA_0_HASH_L_1 +#define SEC_ENG_SE_SHA_0_HASH_L_1_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_1_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_1_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_1_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS)) + +/* 0x18 : se_sha_0_hash_l_2 */ +#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18) +#define SEC_ENG_SE_SHA_0_HASH_L_2 SEC_ENG_SE_SHA_0_HASH_L_2 +#define SEC_ENG_SE_SHA_0_HASH_L_2_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_2_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_2_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_2_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS)) + +/* 0x1C : se_sha_0_hash_l_3 */ +#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C) +#define SEC_ENG_SE_SHA_0_HASH_L_3 SEC_ENG_SE_SHA_0_HASH_L_3 +#define SEC_ENG_SE_SHA_0_HASH_L_3_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_3_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_3_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_3_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS)) + +/* 0x20 : se_sha_0_hash_l_4 */ +#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20) +#define SEC_ENG_SE_SHA_0_HASH_L_4 SEC_ENG_SE_SHA_0_HASH_L_4 +#define SEC_ENG_SE_SHA_0_HASH_L_4_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_4_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_4_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_4_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS)) + +/* 0x24 : se_sha_0_hash_l_5 */ +#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24) +#define SEC_ENG_SE_SHA_0_HASH_L_5 SEC_ENG_SE_SHA_0_HASH_L_5 +#define SEC_ENG_SE_SHA_0_HASH_L_5_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_5_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_5_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_5_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS)) + +/* 0x28 : se_sha_0_hash_l_6 */ +#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28) +#define SEC_ENG_SE_SHA_0_HASH_L_6 SEC_ENG_SE_SHA_0_HASH_L_6 +#define SEC_ENG_SE_SHA_0_HASH_L_6_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_6_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_6_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_6_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS)) + +/* 0x2C : se_sha_0_hash_l_7 */ +#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C) +#define SEC_ENG_SE_SHA_0_HASH_L_7 SEC_ENG_SE_SHA_0_HASH_L_7 +#define SEC_ENG_SE_SHA_0_HASH_L_7_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_7_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_7_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_7_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS)) + +/* 0x30 : se_sha_0_hash_h_0 */ +#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30) +#define SEC_ENG_SE_SHA_0_HASH_H_0 SEC_ENG_SE_SHA_0_HASH_H_0 +#define SEC_ENG_SE_SHA_0_HASH_H_0_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_0_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_0_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_0_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS)) + +/* 0x34 : se_sha_0_hash_h_1 */ +#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34) +#define SEC_ENG_SE_SHA_0_HASH_H_1 SEC_ENG_SE_SHA_0_HASH_H_1 +#define SEC_ENG_SE_SHA_0_HASH_H_1_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_1_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_1_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_1_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS)) + +/* 0x38 : se_sha_0_hash_h_2 */ +#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38) +#define SEC_ENG_SE_SHA_0_HASH_H_2 SEC_ENG_SE_SHA_0_HASH_H_2 +#define SEC_ENG_SE_SHA_0_HASH_H_2_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_2_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_2_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_2_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS)) + +/* 0x3C : se_sha_0_hash_h_3 */ +#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C) +#define SEC_ENG_SE_SHA_0_HASH_H_3 SEC_ENG_SE_SHA_0_HASH_H_3 +#define SEC_ENG_SE_SHA_0_HASH_H_3_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_3_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_3_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_3_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS)) + +/* 0x40 : se_sha_0_hash_h_4 */ +#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40) +#define SEC_ENG_SE_SHA_0_HASH_H_4 SEC_ENG_SE_SHA_0_HASH_H_4 +#define SEC_ENG_SE_SHA_0_HASH_H_4_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_4_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_4_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_4_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS)) + +/* 0x44 : se_sha_0_hash_h_5 */ +#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44) +#define SEC_ENG_SE_SHA_0_HASH_H_5 SEC_ENG_SE_SHA_0_HASH_H_5 +#define SEC_ENG_SE_SHA_0_HASH_H_5_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_5_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_5_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_5_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS)) + +/* 0x48 : se_sha_0_hash_h_6 */ +#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48) +#define SEC_ENG_SE_SHA_0_HASH_H_6 SEC_ENG_SE_SHA_0_HASH_H_6 +#define SEC_ENG_SE_SHA_0_HASH_H_6_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_6_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_6_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_6_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS)) + +/* 0x4C : se_sha_0_hash_h_7 */ +#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C) +#define SEC_ENG_SE_SHA_0_HASH_H_7 SEC_ENG_SE_SHA_0_HASH_H_7 +#define SEC_ENG_SE_SHA_0_HASH_H_7_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_7_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_7_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_7_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS)) + +/* 0x50 : se_sha_0_link */ +#define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50) +#define SEC_ENG_SE_SHA_0_LCA SEC_ENG_SE_SHA_0_LCA +#define SEC_ENG_SE_SHA_0_LCA_POS (0U) +#define SEC_ENG_SE_SHA_0_LCA_LEN (32U) +#define SEC_ENG_SE_SHA_0_LCA_MSK (((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS) +#define SEC_ENG_SE_SHA_0_LCA_UMSK (~(((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS)) + +/* 0xFC : se_sha_0_ctrl_prot */ +#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC) +#define SEC_ENG_SE_SHA_PROT_EN SEC_ENG_SE_SHA_PROT_EN +#define SEC_ENG_SE_SHA_PROT_EN_POS (0U) +#define SEC_ENG_SE_SHA_PROT_EN_LEN (1U) +#define SEC_ENG_SE_SHA_PROT_EN_MSK (((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS) +#define SEC_ENG_SE_SHA_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS)) +#define SEC_ENG_SE_SHA_ID0_EN SEC_ENG_SE_SHA_ID0_EN +#define SEC_ENG_SE_SHA_ID0_EN_POS (1U) +#define SEC_ENG_SE_SHA_ID0_EN_LEN (1U) +#define SEC_ENG_SE_SHA_ID0_EN_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS) +#define SEC_ENG_SE_SHA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)) +#define SEC_ENG_SE_SHA_ID1_EN SEC_ENG_SE_SHA_ID1_EN +#define SEC_ENG_SE_SHA_ID1_EN_POS (2U) +#define SEC_ENG_SE_SHA_ID1_EN_LEN (1U) +#define SEC_ENG_SE_SHA_ID1_EN_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS) +#define SEC_ENG_SE_SHA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)) + +/* 0x100 : se_aes_0_ctrl */ +#define SEC_ENG_SE_AES_0_CTRL_OFFSET (0x100) +#define SEC_ENG_SE_AES_0_BUSY SEC_ENG_SE_AES_0_BUSY +#define SEC_ENG_SE_AES_0_BUSY_POS (0U) +#define SEC_ENG_SE_AES_0_BUSY_LEN (1U) +#define SEC_ENG_SE_AES_0_BUSY_MSK (((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS) +#define SEC_ENG_SE_AES_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS)) +#define SEC_ENG_SE_AES_0_TRIG_1T SEC_ENG_SE_AES_0_TRIG_1T +#define SEC_ENG_SE_AES_0_TRIG_1T_POS (1U) +#define SEC_ENG_SE_AES_0_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_AES_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS) +#define SEC_ENG_SE_AES_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS)) +#define SEC_ENG_SE_AES_0_EN SEC_ENG_SE_AES_0_EN +#define SEC_ENG_SE_AES_0_EN_POS (2U) +#define SEC_ENG_SE_AES_0_EN_LEN (1U) +#define SEC_ENG_SE_AES_0_EN_MSK (((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS) +#define SEC_ENG_SE_AES_0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS)) +#define SEC_ENG_SE_AES_0_MODE SEC_ENG_SE_AES_0_MODE +#define SEC_ENG_SE_AES_0_MODE_POS (3U) +#define SEC_ENG_SE_AES_0_MODE_LEN (2U) +#define SEC_ENG_SE_AES_0_MODE_MSK (((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS) +#define SEC_ENG_SE_AES_0_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS)) +#define SEC_ENG_SE_AES_0_DEC_EN SEC_ENG_SE_AES_0_DEC_EN +#define SEC_ENG_SE_AES_0_DEC_EN_POS (5U) +#define SEC_ENG_SE_AES_0_DEC_EN_LEN (1U) +#define SEC_ENG_SE_AES_0_DEC_EN_MSK (((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS) +#define SEC_ENG_SE_AES_0_DEC_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS)) +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL SEC_ENG_SE_AES_0_DEC_KEY_SEL +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS (6U) +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN (1U) +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS) +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS)) +#define SEC_ENG_SE_AES_0_HW_KEY_EN SEC_ENG_SE_AES_0_HW_KEY_EN +#define SEC_ENG_SE_AES_0_HW_KEY_EN_POS (7U) +#define SEC_ENG_SE_AES_0_HW_KEY_EN_LEN (1U) +#define SEC_ENG_SE_AES_0_HW_KEY_EN_MSK (((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS) +#define SEC_ENG_SE_AES_0_HW_KEY_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS)) +#define SEC_ENG_SE_AES_0_INT SEC_ENG_SE_AES_0_INT +#define SEC_ENG_SE_AES_0_INT_POS (8U) +#define SEC_ENG_SE_AES_0_INT_LEN (1U) +#define SEC_ENG_SE_AES_0_INT_MSK (((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS) +#define SEC_ENG_SE_AES_0_INT_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS)) +#define SEC_ENG_SE_AES_0_INT_CLR_1T SEC_ENG_SE_AES_0_INT_CLR_1T +#define SEC_ENG_SE_AES_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_AES_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_AES_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_AES_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_AES_0_INT_SET_1T SEC_ENG_SE_AES_0_INT_SET_1T +#define SEC_ENG_SE_AES_0_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_AES_0_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_AES_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS) +#define SEC_ENG_SE_AES_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS)) +#define SEC_ENG_SE_AES_0_INT_MASK SEC_ENG_SE_AES_0_INT_MASK +#define SEC_ENG_SE_AES_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_AES_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_AES_0_INT_MASK_MSK (((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS) +#define SEC_ENG_SE_AES_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS)) +#define SEC_ENG_SE_AES_0_BLOCK_MODE SEC_ENG_SE_AES_0_BLOCK_MODE +#define SEC_ENG_SE_AES_0_BLOCK_MODE_POS (12U) +#define SEC_ENG_SE_AES_0_BLOCK_MODE_LEN (2U) +#define SEC_ENG_SE_AES_0_BLOCK_MODE_MSK (((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS) +#define SEC_ENG_SE_AES_0_BLOCK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS)) +#define SEC_ENG_SE_AES_0_IV_SEL SEC_ENG_SE_AES_0_IV_SEL +#define SEC_ENG_SE_AES_0_IV_SEL_POS (14U) +#define SEC_ENG_SE_AES_0_IV_SEL_LEN (1U) +#define SEC_ENG_SE_AES_0_IV_SEL_MSK (((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS) +#define SEC_ENG_SE_AES_0_IV_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS)) +#define SEC_ENG_SE_AES_0_LINK_MODE SEC_ENG_SE_AES_0_LINK_MODE +#define SEC_ENG_SE_AES_0_LINK_MODE_POS (15U) +#define SEC_ENG_SE_AES_0_LINK_MODE_LEN (1U) +#define SEC_ENG_SE_AES_0_LINK_MODE_MSK (((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS) +#define SEC_ENG_SE_AES_0_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS)) +#define SEC_ENG_SE_AES_0_MSG_LEN SEC_ENG_SE_AES_0_MSG_LEN +#define SEC_ENG_SE_AES_0_MSG_LEN_POS (16U) +#define SEC_ENG_SE_AES_0_MSG_LEN_LEN (16U) +#define SEC_ENG_SE_AES_0_MSG_LEN_MSK (((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS) +#define SEC_ENG_SE_AES_0_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS)) + +/* 0x104 : se_aes_0_msa */ +#define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104) +#define SEC_ENG_SE_AES_0_MSA SEC_ENG_SE_AES_0_MSA +#define SEC_ENG_SE_AES_0_MSA_POS (0U) +#define SEC_ENG_SE_AES_0_MSA_LEN (32U) +#define SEC_ENG_SE_AES_0_MSA_MSK (((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS) +#define SEC_ENG_SE_AES_0_MSA_UMSK (~(((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS)) + +/* 0x108 : se_aes_0_mda */ +#define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108) +#define SEC_ENG_SE_AES_0_MDA SEC_ENG_SE_AES_0_MDA +#define SEC_ENG_SE_AES_0_MDA_POS (0U) +#define SEC_ENG_SE_AES_0_MDA_LEN (32U) +#define SEC_ENG_SE_AES_0_MDA_MSK (((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS) +#define SEC_ENG_SE_AES_0_MDA_UMSK (~(((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS)) + +/* 0x10C : se_aes_0_status */ +#define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C) +#define SEC_ENG_SE_AES_0_STATUS SEC_ENG_SE_AES_0_STATUS +#define SEC_ENG_SE_AES_0_STATUS_POS (0U) +#define SEC_ENG_SE_AES_0_STATUS_LEN (32U) +#define SEC_ENG_SE_AES_0_STATUS_MSK (((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS) +#define SEC_ENG_SE_AES_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS)) + +/* 0x110 : se_aes_0_iv_0 */ +#define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110) +#define SEC_ENG_SE_AES_0_IV_0 SEC_ENG_SE_AES_0_IV_0 +#define SEC_ENG_SE_AES_0_IV_0_POS (0U) +#define SEC_ENG_SE_AES_0_IV_0_LEN (32U) +#define SEC_ENG_SE_AES_0_IV_0_MSK (((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS) +#define SEC_ENG_SE_AES_0_IV_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS)) + +/* 0x114 : se_aes_0_iv_1 */ +#define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114) +#define SEC_ENG_SE_AES_0_IV_1 SEC_ENG_SE_AES_0_IV_1 +#define SEC_ENG_SE_AES_0_IV_1_POS (0U) +#define SEC_ENG_SE_AES_0_IV_1_LEN (32U) +#define SEC_ENG_SE_AES_0_IV_1_MSK (((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS) +#define SEC_ENG_SE_AES_0_IV_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS)) + +/* 0x118 : se_aes_0_iv_2 */ +#define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118) +#define SEC_ENG_SE_AES_0_IV_2 SEC_ENG_SE_AES_0_IV_2 +#define SEC_ENG_SE_AES_0_IV_2_POS (0U) +#define SEC_ENG_SE_AES_0_IV_2_LEN (32U) +#define SEC_ENG_SE_AES_0_IV_2_MSK (((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS) +#define SEC_ENG_SE_AES_0_IV_2_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS)) + +/* 0x11C : se_aes_0_iv_3 */ +#define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C) +#define SEC_ENG_SE_AES_0_IV_3 SEC_ENG_SE_AES_0_IV_3 +#define SEC_ENG_SE_AES_0_IV_3_POS (0U) +#define SEC_ENG_SE_AES_0_IV_3_LEN (32U) +#define SEC_ENG_SE_AES_0_IV_3_MSK (((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS) +#define SEC_ENG_SE_AES_0_IV_3_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS)) + +/* 0x120 : se_aes_0_key_0 */ +#define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120) +#define SEC_ENG_SE_AES_0_KEY_0 SEC_ENG_SE_AES_0_KEY_0 +#define SEC_ENG_SE_AES_0_KEY_0_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_0_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_0_MSK (((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS) +#define SEC_ENG_SE_AES_0_KEY_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS)) + +/* 0x124 : se_aes_0_key_1 */ +#define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124) +#define SEC_ENG_SE_AES_0_KEY_1 SEC_ENG_SE_AES_0_KEY_1 +#define SEC_ENG_SE_AES_0_KEY_1_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_1_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_1_MSK (((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS) +#define SEC_ENG_SE_AES_0_KEY_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS)) + +/* 0x128 : se_aes_0_key_2 */ +#define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128) +#define SEC_ENG_SE_AES_0_KEY_2 SEC_ENG_SE_AES_0_KEY_2 +#define SEC_ENG_SE_AES_0_KEY_2_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_2_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_2_MSK (((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS) +#define SEC_ENG_SE_AES_0_KEY_2_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS)) + +/* 0x12C : se_aes_0_key_3 */ +#define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C) +#define SEC_ENG_SE_AES_0_KEY_3 SEC_ENG_SE_AES_0_KEY_3 +#define SEC_ENG_SE_AES_0_KEY_3_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_3_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_3_MSK (((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS) +#define SEC_ENG_SE_AES_0_KEY_3_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS)) + +/* 0x130 : se_aes_0_key_4 */ +#define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130) +#define SEC_ENG_SE_AES_0_KEY_4 SEC_ENG_SE_AES_0_KEY_4 +#define SEC_ENG_SE_AES_0_KEY_4_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_4_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_4_MSK (((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS) +#define SEC_ENG_SE_AES_0_KEY_4_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS)) + +/* 0x134 : se_aes_0_key_5 */ +#define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134) +#define SEC_ENG_SE_AES_0_KEY_5 SEC_ENG_SE_AES_0_KEY_5 +#define SEC_ENG_SE_AES_0_KEY_5_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_5_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_5_MSK (((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS) +#define SEC_ENG_SE_AES_0_KEY_5_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS)) + +/* 0x138 : se_aes_0_key_6 */ +#define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138) +#define SEC_ENG_SE_AES_0_KEY_6 SEC_ENG_SE_AES_0_KEY_6 +#define SEC_ENG_SE_AES_0_KEY_6_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_6_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_6_MSK (((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS) +#define SEC_ENG_SE_AES_0_KEY_6_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS)) + +/* 0x13C : se_aes_0_key_7 */ +#define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C) +#define SEC_ENG_SE_AES_0_KEY_7 SEC_ENG_SE_AES_0_KEY_7 +#define SEC_ENG_SE_AES_0_KEY_7_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_7_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_7_MSK (((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS) +#define SEC_ENG_SE_AES_0_KEY_7_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS)) + +/* 0x140 : se_aes_0_key_sel_0 */ +#define SEC_ENG_SE_AES_0_KEY_SEL_0_OFFSET (0x140) +#define SEC_ENG_SE_AES_0_KEY_SEL_0 SEC_ENG_SE_AES_0_KEY_SEL_0 +#define SEC_ENG_SE_AES_0_KEY_SEL_0_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_SEL_0_LEN (2U) +#define SEC_ENG_SE_AES_0_KEY_SEL_0_MSK (((1U << SEC_ENG_SE_AES_0_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_0_POS) +#define SEC_ENG_SE_AES_0_KEY_SEL_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_0_POS)) + +/* 0x144 : se_aes_0_key_sel_1 */ +#define SEC_ENG_SE_AES_0_KEY_SEL_1_OFFSET (0x144) +#define SEC_ENG_SE_AES_0_KEY_SEL_1 SEC_ENG_SE_AES_0_KEY_SEL_1 +#define SEC_ENG_SE_AES_0_KEY_SEL_1_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_SEL_1_LEN (2U) +#define SEC_ENG_SE_AES_0_KEY_SEL_1_MSK (((1U << SEC_ENG_SE_AES_0_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_1_POS) +#define SEC_ENG_SE_AES_0_KEY_SEL_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_1_POS)) + +/* 0x148 : se_aes_0_endian */ +#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET (0x148) +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN SEC_ENG_SE_AES_0_DOUT_ENDIAN +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS (0U) +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS) +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS)) +#define SEC_ENG_SE_AES_0_DIN_ENDIAN SEC_ENG_SE_AES_0_DIN_ENDIAN +#define SEC_ENG_SE_AES_0_DIN_ENDIAN_POS (1U) +#define SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_0_DIN_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS) +#define SEC_ENG_SE_AES_0_DIN_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS)) +#define SEC_ENG_SE_AES_0_KEY_ENDIAN SEC_ENG_SE_AES_0_KEY_ENDIAN +#define SEC_ENG_SE_AES_0_KEY_ENDIAN_POS (2U) +#define SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_0_KEY_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS) +#define SEC_ENG_SE_AES_0_KEY_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS)) +#define SEC_ENG_SE_AES_0_IV_ENDIAN SEC_ENG_SE_AES_0_IV_ENDIAN +#define SEC_ENG_SE_AES_0_IV_ENDIAN_POS (3U) +#define SEC_ENG_SE_AES_0_IV_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_0_IV_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS) +#define SEC_ENG_SE_AES_0_IV_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS)) +#define SEC_ENG_SE_AES_0_CTR_LEN SEC_ENG_SE_AES_0_CTR_LEN +#define SEC_ENG_SE_AES_0_CTR_LEN_POS (30U) +#define SEC_ENG_SE_AES_0_CTR_LEN_LEN (2U) +#define SEC_ENG_SE_AES_0_CTR_LEN_MSK (((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS) +#define SEC_ENG_SE_AES_0_CTR_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS)) + +/* 0x14C : se_aes_0_sboot */ +#define SEC_ENG_SE_AES_0_SBOOT_OFFSET (0x14C) +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL SEC_ENG_SE_AES_0_SBOOT_KEY_SEL +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS (0U) +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN (1U) +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS) +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS)) + +/* 0x150 : se_aes_0_link */ +#define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150) +#define SEC_ENG_SE_AES_0_LCA SEC_ENG_SE_AES_0_LCA +#define SEC_ENG_SE_AES_0_LCA_POS (0U) +#define SEC_ENG_SE_AES_0_LCA_LEN (32U) +#define SEC_ENG_SE_AES_0_LCA_MSK (((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS) +#define SEC_ENG_SE_AES_0_LCA_UMSK (~(((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS)) + +/* 0x1FC : se_aes_0_ctrl_prot */ +#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC) +#define SEC_ENG_SE_AES_PROT_EN SEC_ENG_SE_AES_PROT_EN +#define SEC_ENG_SE_AES_PROT_EN_POS (0U) +#define SEC_ENG_SE_AES_PROT_EN_LEN (1U) +#define SEC_ENG_SE_AES_PROT_EN_MSK (((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS) +#define SEC_ENG_SE_AES_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS)) +#define SEC_ENG_SE_AES_ID0_EN SEC_ENG_SE_AES_ID0_EN +#define SEC_ENG_SE_AES_ID0_EN_POS (1U) +#define SEC_ENG_SE_AES_ID0_EN_LEN (1U) +#define SEC_ENG_SE_AES_ID0_EN_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS) +#define SEC_ENG_SE_AES_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)) +#define SEC_ENG_SE_AES_ID1_EN SEC_ENG_SE_AES_ID1_EN +#define SEC_ENG_SE_AES_ID1_EN_POS (2U) +#define SEC_ENG_SE_AES_ID1_EN_LEN (1U) +#define SEC_ENG_SE_AES_ID1_EN_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS) +#define SEC_ENG_SE_AES_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)) + +/* 0x200 : se_trng_0_ctrl_0 */ +#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET (0x200) +#define SEC_ENG_SE_TRNG_0_BUSY SEC_ENG_SE_TRNG_0_BUSY +#define SEC_ENG_SE_TRNG_0_BUSY_POS (0U) +#define SEC_ENG_SE_TRNG_0_BUSY_LEN (1U) +#define SEC_ENG_SE_TRNG_0_BUSY_MSK (((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS) +#define SEC_ENG_SE_TRNG_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS)) +#define SEC_ENG_SE_TRNG_0_TRIG_1T SEC_ENG_SE_TRNG_0_TRIG_1T +#define SEC_ENG_SE_TRNG_0_TRIG_1T_POS (1U) +#define SEC_ENG_SE_TRNG_0_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS) +#define SEC_ENG_SE_TRNG_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS)) +#define SEC_ENG_SE_TRNG_0_EN SEC_ENG_SE_TRNG_0_EN +#define SEC_ENG_SE_TRNG_0_EN_POS (2U) +#define SEC_ENG_SE_TRNG_0_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS) +#define SEC_ENG_SE_TRNG_0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS)) +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T SEC_ENG_SE_TRNG_0_DOUT_CLR_1T +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS (3U) +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS)) +#define SEC_ENG_SE_TRNG_0_HT_ERROR SEC_ENG_SE_TRNG_0_HT_ERROR +#define SEC_ENG_SE_TRNG_0_HT_ERROR_POS (4U) +#define SEC_ENG_SE_TRNG_0_HT_ERROR_LEN (1U) +#define SEC_ENG_SE_TRNG_0_HT_ERROR_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS) +#define SEC_ENG_SE_TRNG_0_HT_ERROR_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS)) +#define SEC_ENG_SE_TRNG_0_INT SEC_ENG_SE_TRNG_0_INT +#define SEC_ENG_SE_TRNG_0_INT_POS (8U) +#define SEC_ENG_SE_TRNG_0_INT_LEN (1U) +#define SEC_ENG_SE_TRNG_0_INT_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS) +#define SEC_ENG_SE_TRNG_0_INT_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS)) +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T SEC_ENG_SE_TRNG_0_INT_CLR_1T +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_TRNG_0_INT_SET_1T SEC_ENG_SE_TRNG_0_INT_SET_1T +#define SEC_ENG_SE_TRNG_0_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS) +#define SEC_ENG_SE_TRNG_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS)) +#define SEC_ENG_SE_TRNG_0_INT_MASK SEC_ENG_SE_TRNG_0_INT_MASK +#define SEC_ENG_SE_TRNG_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_TRNG_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_TRNG_0_INT_MASK_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS) +#define SEC_ENG_SE_TRNG_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS)) +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS (13U) +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN (1U) +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS) +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS)) +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED SEC_ENG_SE_TRNG_0_MANUAL_RESEED +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS (14U) +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN (1U) +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS) +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS)) +#define SEC_ENG_SE_TRNG_0_MANUAL_EN SEC_ENG_SE_TRNG_0_MANUAL_EN +#define SEC_ENG_SE_TRNG_0_MANUAL_EN_POS (15U) +#define SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_MANUAL_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS) +#define SEC_ENG_SE_TRNG_0_MANUAL_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS)) + +/* 0x204 : se_trng_0_status */ +#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204) +#define SEC_ENG_SE_TRNG_0_STATUS SEC_ENG_SE_TRNG_0_STATUS +#define SEC_ENG_SE_TRNG_0_STATUS_POS (0U) +#define SEC_ENG_SE_TRNG_0_STATUS_LEN (32U) +#define SEC_ENG_SE_TRNG_0_STATUS_MSK (((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS) +#define SEC_ENG_SE_TRNG_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS)) + +/* 0x208 : se_trng_0_dout_0 */ +#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208) +#define SEC_ENG_SE_TRNG_0_DOUT_0 SEC_ENG_SE_TRNG_0_DOUT_0 +#define SEC_ENG_SE_TRNG_0_DOUT_0_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_0_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_0_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS)) + +/* 0x20C : se_trng_0_dout_1 */ +#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C) +#define SEC_ENG_SE_TRNG_0_DOUT_1 SEC_ENG_SE_TRNG_0_DOUT_1 +#define SEC_ENG_SE_TRNG_0_DOUT_1_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_1_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_1_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS)) + +/* 0x210 : se_trng_0_dout_2 */ +#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210) +#define SEC_ENG_SE_TRNG_0_DOUT_2 SEC_ENG_SE_TRNG_0_DOUT_2 +#define SEC_ENG_SE_TRNG_0_DOUT_2_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_2_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_2_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS)) + +/* 0x214 : se_trng_0_dout_3 */ +#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214) +#define SEC_ENG_SE_TRNG_0_DOUT_3 SEC_ENG_SE_TRNG_0_DOUT_3 +#define SEC_ENG_SE_TRNG_0_DOUT_3_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_3_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_3_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS)) + +/* 0x218 : se_trng_0_dout_4 */ +#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218) +#define SEC_ENG_SE_TRNG_0_DOUT_4 SEC_ENG_SE_TRNG_0_DOUT_4 +#define SEC_ENG_SE_TRNG_0_DOUT_4_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_4_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_4_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_4_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS)) + +/* 0x21C : se_trng_0_dout_5 */ +#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C) +#define SEC_ENG_SE_TRNG_0_DOUT_5 SEC_ENG_SE_TRNG_0_DOUT_5 +#define SEC_ENG_SE_TRNG_0_DOUT_5_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_5_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_5_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_5_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS)) + +/* 0x220 : se_trng_0_dout_6 */ +#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220) +#define SEC_ENG_SE_TRNG_0_DOUT_6 SEC_ENG_SE_TRNG_0_DOUT_6 +#define SEC_ENG_SE_TRNG_0_DOUT_6_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_6_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_6_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_6_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS)) + +/* 0x224 : se_trng_0_dout_7 */ +#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224) +#define SEC_ENG_SE_TRNG_0_DOUT_7 SEC_ENG_SE_TRNG_0_DOUT_7 +#define SEC_ENG_SE_TRNG_0_DOUT_7_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_7_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_7_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_7_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS)) + +/* 0x228 : se_trng_0_test */ +#define SEC_ENG_SE_TRNG_0_TEST_OFFSET (0x228) +#define SEC_ENG_SE_TRNG_0_TEST_EN SEC_ENG_SE_TRNG_0_TEST_EN +#define SEC_ENG_SE_TRNG_0_TEST_EN_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS) +#define SEC_ENG_SE_TRNG_0_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS)) +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN SEC_ENG_SE_TRNG_0_CP_TEST_EN +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS (1U) +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS) +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS)) +#define SEC_ENG_SE_TRNG_0_CP_BYPASS SEC_ENG_SE_TRNG_0_CP_BYPASS +#define SEC_ENG_SE_TRNG_0_CP_BYPASS_POS (2U) +#define SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN (1U) +#define SEC_ENG_SE_TRNG_0_CP_BYPASS_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS) +#define SEC_ENG_SE_TRNG_0_CP_BYPASS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS)) +#define SEC_ENG_SE_TRNG_0_HT_DIS SEC_ENG_SE_TRNG_0_HT_DIS +#define SEC_ENG_SE_TRNG_0_HT_DIS_POS (3U) +#define SEC_ENG_SE_TRNG_0_HT_DIS_LEN (1U) +#define SEC_ENG_SE_TRNG_0_HT_DIS_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS) +#define SEC_ENG_SE_TRNG_0_HT_DIS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS)) +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N SEC_ENG_SE_TRNG_0_HT_ALARM_N +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS (4U) +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN (8U) +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS) +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS)) + +/* 0x22C : se_trng_0_ctrl_1 */ +#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET (0x22C) +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB SEC_ENG_SE_TRNG_0_RESEED_N_LSB +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS (0U) +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN (32U) +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MSK (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS) +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS)) + +/* 0x230 : se_trng_0_ctrl_2 */ +#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET (0x230) +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB SEC_ENG_SE_TRNG_0_RESEED_N_MSB +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS (0U) +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN (16U) +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MSK (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS) +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS)) + +/* 0x234 : se_trng_0_ctrl_3 */ +#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234) +#define SEC_ENG_SE_TRNG_0_CP_RATIO SEC_ENG_SE_TRNG_0_CP_RATIO +#define SEC_ENG_SE_TRNG_0_CP_RATIO_POS (0U) +#define SEC_ENG_SE_TRNG_0_CP_RATIO_LEN (8U) +#define SEC_ENG_SE_TRNG_0_CP_RATIO_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS) +#define SEC_ENG_SE_TRNG_0_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS)) +#define SEC_ENG_SE_TRNG_0_HT_RCT_C SEC_ENG_SE_TRNG_0_HT_RCT_C +#define SEC_ENG_SE_TRNG_0_HT_RCT_C_POS (8U) +#define SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN (8U) +#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS) +#define SEC_ENG_SE_TRNG_0_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS)) +#define SEC_ENG_SE_TRNG_0_HT_APT_C SEC_ENG_SE_TRNG_0_HT_APT_C +#define SEC_ENG_SE_TRNG_0_HT_APT_C_POS (16U) +#define SEC_ENG_SE_TRNG_0_HT_APT_C_LEN (10U) +#define SEC_ENG_SE_TRNG_0_HT_APT_C_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS) +#define SEC_ENG_SE_TRNG_0_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS)) +#define SEC_ENG_SE_TRNG_0_HT_OD_EN SEC_ENG_SE_TRNG_0_HT_OD_EN +#define SEC_ENG_SE_TRNG_0_HT_OD_EN_POS (26U) +#define SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_HT_OD_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS) +#define SEC_ENG_SE_TRNG_0_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS)) +#define SEC_ENG_SE_TRNG_0_ROSC_DIS SEC_ENG_SE_TRNG_0_ROSC_DIS +#define SEC_ENG_SE_TRNG_0_ROSC_DIS_POS (31U) +#define SEC_ENG_SE_TRNG_0_ROSC_DIS_LEN (1U) +#define SEC_ENG_SE_TRNG_0_ROSC_DIS_MSK (((1U << SEC_ENG_SE_TRNG_0_ROSC_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_DIS_POS) +#define SEC_ENG_SE_TRNG_0_ROSC_DIS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_ROSC_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_DIS_POS)) + +/* 0x240 : se_trng_0_test_out_0 */ +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0 SEC_ENG_SE_TRNG_0_TEST_OUT_0 +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN (32U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS)) + +/* 0x244 : se_trng_0_test_out_1 */ +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1 SEC_ENG_SE_TRNG_0_TEST_OUT_1 +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN (32U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS)) + +/* 0x248 : se_trng_0_test_out_2 */ +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2 SEC_ENG_SE_TRNG_0_TEST_OUT_2 +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN (32U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS)) + +/* 0x24C : se_trng_0_test_out_3 */ +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3 SEC_ENG_SE_TRNG_0_TEST_OUT_3 +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN (32U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS)) + +/* 0x2FC : se_trng_0_ctrl_prot */ +#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC) +#define SEC_ENG_SE_TRNG_PROT_EN SEC_ENG_SE_TRNG_PROT_EN +#define SEC_ENG_SE_TRNG_PROT_EN_POS (0U) +#define SEC_ENG_SE_TRNG_PROT_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_PROT_EN_MSK (((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS) +#define SEC_ENG_SE_TRNG_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS)) +#define SEC_ENG_SE_TRNG_ID0_EN SEC_ENG_SE_TRNG_ID0_EN +#define SEC_ENG_SE_TRNG_ID0_EN_POS (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS) +#define SEC_ENG_SE_TRNG_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)) +#define SEC_ENG_SE_TRNG_ID1_EN SEC_ENG_SE_TRNG_ID1_EN +#define SEC_ENG_SE_TRNG_ID1_EN_POS (2U) +#define SEC_ENG_SE_TRNG_ID1_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ID1_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS) +#define SEC_ENG_SE_TRNG_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)) + +/* 0x300 : se_pka_0_ctrl_0 */ +#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET (0x300) +#define SEC_ENG_SE_PKA_0_DONE SEC_ENG_SE_PKA_0_DONE +#define SEC_ENG_SE_PKA_0_DONE_POS (0U) +#define SEC_ENG_SE_PKA_0_DONE_LEN (1U) +#define SEC_ENG_SE_PKA_0_DONE_MSK (((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS) +#define SEC_ENG_SE_PKA_0_DONE_UMSK (~(((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS)) +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T SEC_ENG_SE_PKA_0_DONE_CLR_1T +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS (1U) +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN (1U) +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS) +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS)) +#define SEC_ENG_SE_PKA_0_BUSY SEC_ENG_SE_PKA_0_BUSY +#define SEC_ENG_SE_PKA_0_BUSY_POS (2U) +#define SEC_ENG_SE_PKA_0_BUSY_LEN (1U) +#define SEC_ENG_SE_PKA_0_BUSY_MSK (((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS) +#define SEC_ENG_SE_PKA_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS)) +#define SEC_ENG_SE_PKA_0_EN SEC_ENG_SE_PKA_0_EN +#define SEC_ENG_SE_PKA_0_EN_POS (3U) +#define SEC_ENG_SE_PKA_0_EN_LEN (1U) +#define SEC_ENG_SE_PKA_0_EN_MSK (((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS) +#define SEC_ENG_SE_PKA_0_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS)) +#define SEC_ENG_SE_PKA_0_PROT_MD SEC_ENG_SE_PKA_0_PROT_MD +#define SEC_ENG_SE_PKA_0_PROT_MD_POS (4U) +#define SEC_ENG_SE_PKA_0_PROT_MD_LEN (4U) +#define SEC_ENG_SE_PKA_0_PROT_MD_MSK (((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS) +#define SEC_ENG_SE_PKA_0_PROT_MD_UMSK (~(((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS)) +#define SEC_ENG_SE_PKA_0_INT SEC_ENG_SE_PKA_0_INT +#define SEC_ENG_SE_PKA_0_INT_POS (8U) +#define SEC_ENG_SE_PKA_0_INT_LEN (1U) +#define SEC_ENG_SE_PKA_0_INT_MSK (((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS) +#define SEC_ENG_SE_PKA_0_INT_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS)) +#define SEC_ENG_SE_PKA_0_INT_CLR_1T SEC_ENG_SE_PKA_0_INT_CLR_1T +#define SEC_ENG_SE_PKA_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_PKA_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_PKA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_PKA_0_INT_SET SEC_ENG_SE_PKA_0_INT_SET +#define SEC_ENG_SE_PKA_0_INT_SET_POS (10U) +#define SEC_ENG_SE_PKA_0_INT_SET_LEN (1U) +#define SEC_ENG_SE_PKA_0_INT_SET_MSK (((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS) +#define SEC_ENG_SE_PKA_0_INT_SET_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS)) +#define SEC_ENG_SE_PKA_0_INT_MASK SEC_ENG_SE_PKA_0_INT_MASK +#define SEC_ENG_SE_PKA_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_PKA_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_PKA_0_INT_MASK_MSK (((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS) +#define SEC_ENG_SE_PKA_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS)) +#define SEC_ENG_SE_PKA_0_ENDIAN SEC_ENG_SE_PKA_0_ENDIAN +#define SEC_ENG_SE_PKA_0_ENDIAN_POS (12U) +#define SEC_ENG_SE_PKA_0_ENDIAN_LEN (1U) +#define SEC_ENG_SE_PKA_0_ENDIAN_MSK (((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS) +#define SEC_ENG_SE_PKA_0_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS)) +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD SEC_ENG_SE_PKA_0_RAM_CLR_MD +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS (13U) +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN (1U) +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_MSK (((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS) +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_UMSK (~(((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS)) +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T SEC_ENG_SE_PKA_0_STATUS_CLR_1T +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS (16U) +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN (1U) +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS) +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS)) +#define SEC_ENG_SE_PKA_0_STATUS SEC_ENG_SE_PKA_0_STATUS +#define SEC_ENG_SE_PKA_0_STATUS_POS (17U) +#define SEC_ENG_SE_PKA_0_STATUS_LEN (15U) +#define SEC_ENG_SE_PKA_0_STATUS_MSK (((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS) +#define SEC_ENG_SE_PKA_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS)) + +/* 0x30C : se_pka_0_seed */ +#define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C) +#define SEC_ENG_SE_PKA_0_SEED SEC_ENG_SE_PKA_0_SEED +#define SEC_ENG_SE_PKA_0_SEED_POS (0U) +#define SEC_ENG_SE_PKA_0_SEED_LEN (32U) +#define SEC_ENG_SE_PKA_0_SEED_MSK (((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS) +#define SEC_ENG_SE_PKA_0_SEED_UMSK (~(((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS)) + +/* 0x310 : se_pka_0_ctrl_1 */ +#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310) +#define SEC_ENG_SE_PKA_0_HBURST SEC_ENG_SE_PKA_0_HBURST +#define SEC_ENG_SE_PKA_0_HBURST_POS (0U) +#define SEC_ENG_SE_PKA_0_HBURST_LEN (3U) +#define SEC_ENG_SE_PKA_0_HBURST_MSK (((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS) +#define SEC_ENG_SE_PKA_0_HBURST_UMSK (~(((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS)) +#define SEC_ENG_SE_PKA_0_HBYPASS SEC_ENG_SE_PKA_0_HBYPASS +#define SEC_ENG_SE_PKA_0_HBYPASS_POS (3U) +#define SEC_ENG_SE_PKA_0_HBYPASS_LEN (1U) +#define SEC_ENG_SE_PKA_0_HBYPASS_MSK (((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS) +#define SEC_ENG_SE_PKA_0_HBYPASS_UMSK (~(((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS)) + +/* 0x340 : se_pka_0_rw */ +#define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340) + +/* 0x360 : se_pka_0_rw_burst */ +#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360) + +/* 0x3FC : se_pka_0_ctrl_prot */ +#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC) +#define SEC_ENG_SE_PKA_PROT_EN SEC_ENG_SE_PKA_PROT_EN +#define SEC_ENG_SE_PKA_PROT_EN_POS (0U) +#define SEC_ENG_SE_PKA_PROT_EN_LEN (1U) +#define SEC_ENG_SE_PKA_PROT_EN_MSK (((1U << SEC_ENG_SE_PKA_PROT_EN_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_POS) +#define SEC_ENG_SE_PKA_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_PROT_EN_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_POS)) +#define SEC_ENG_SE_PKA_ID0_EN SEC_ENG_SE_PKA_ID0_EN +#define SEC_ENG_SE_PKA_ID0_EN_POS (1U) +#define SEC_ENG_SE_PKA_ID0_EN_LEN (1U) +#define SEC_ENG_SE_PKA_ID0_EN_MSK (((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS) +#define SEC_ENG_SE_PKA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS)) +#define SEC_ENG_SE_PKA_ID1_EN SEC_ENG_SE_PKA_ID1_EN +#define SEC_ENG_SE_PKA_ID1_EN_POS (2U) +#define SEC_ENG_SE_PKA_ID1_EN_LEN (1U) +#define SEC_ENG_SE_PKA_ID1_EN_MSK (((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS) +#define SEC_ENG_SE_PKA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS)) + +/* 0x400 : se_cdet_0_ctrl_0 */ +#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET (0x400) +#define SEC_ENG_SE_CDET_0_EN SEC_ENG_SE_CDET_0_EN +#define SEC_ENG_SE_CDET_0_EN_POS (0U) +#define SEC_ENG_SE_CDET_0_EN_LEN (1U) +#define SEC_ENG_SE_CDET_0_EN_MSK (((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS) +#define SEC_ENG_SE_CDET_0_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS)) +#define SEC_ENG_SE_CDET_0_ERROR SEC_ENG_SE_CDET_0_ERROR +#define SEC_ENG_SE_CDET_0_ERROR_POS (1U) +#define SEC_ENG_SE_CDET_0_ERROR_LEN (1U) +#define SEC_ENG_SE_CDET_0_ERROR_MSK (((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS) +#define SEC_ENG_SE_CDET_0_ERROR_UMSK (~(((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS)) +#define SEC_ENG_SE_CDET_0_STATUS SEC_ENG_SE_CDET_0_STATUS +#define SEC_ENG_SE_CDET_0_STATUS_POS (2U) +#define SEC_ENG_SE_CDET_0_STATUS_LEN (14U) +#define SEC_ENG_SE_CDET_0_STATUS_MSK (((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS) +#define SEC_ENG_SE_CDET_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS)) +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX SEC_ENG_SE_CDET_0_G_LOOP_MAX +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS (16U) +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN (8U) +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MSK (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS) +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS)) +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN SEC_ENG_SE_CDET_0_G_LOOP_MIN +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS (24U) +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN (8U) +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MSK (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS) +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS)) + +/* 0x404 : se_cdet_0_ctrl_1 */ +#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404) +#define SEC_ENG_SE_CDET_0_T_LOOP_N SEC_ENG_SE_CDET_0_T_LOOP_N +#define SEC_ENG_SE_CDET_0_T_LOOP_N_POS (0U) +#define SEC_ENG_SE_CDET_0_T_LOOP_N_LEN (8U) +#define SEC_ENG_SE_CDET_0_T_LOOP_N_MSK (((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS) +#define SEC_ENG_SE_CDET_0_T_LOOP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS)) +#define SEC_ENG_SE_CDET_0_T_DLY_N SEC_ENG_SE_CDET_0_T_DLY_N +#define SEC_ENG_SE_CDET_0_T_DLY_N_POS (8U) +#define SEC_ENG_SE_CDET_0_T_DLY_N_LEN (8U) +#define SEC_ENG_SE_CDET_0_T_DLY_N_MSK (((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS) +#define SEC_ENG_SE_CDET_0_T_DLY_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS)) +#define SEC_ENG_SE_CDET_0_G_SLP_N SEC_ENG_SE_CDET_0_G_SLP_N +#define SEC_ENG_SE_CDET_0_G_SLP_N_POS (16U) +#define SEC_ENG_SE_CDET_0_G_SLP_N_LEN (8U) +#define SEC_ENG_SE_CDET_0_G_SLP_N_MSK (((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS) +#define SEC_ENG_SE_CDET_0_G_SLP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS)) + +/* 0x4FC : se_cdet_0_ctrl_prot */ +#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC) +#define SEC_ENG_SE_CDET_PROT_EN SEC_ENG_SE_CDET_PROT_EN +#define SEC_ENG_SE_CDET_PROT_EN_POS (0U) +#define SEC_ENG_SE_CDET_PROT_EN_LEN (1U) +#define SEC_ENG_SE_CDET_PROT_EN_MSK (((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS) +#define SEC_ENG_SE_CDET_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS)) +#define SEC_ENG_SE_CDET_ID0_EN SEC_ENG_SE_CDET_ID0_EN +#define SEC_ENG_SE_CDET_ID0_EN_POS (1U) +#define SEC_ENG_SE_CDET_ID0_EN_LEN (1U) +#define SEC_ENG_SE_CDET_ID0_EN_MSK (((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS) +#define SEC_ENG_SE_CDET_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS)) +#define SEC_ENG_SE_CDET_ID1_EN SEC_ENG_SE_CDET_ID1_EN +#define SEC_ENG_SE_CDET_ID1_EN_POS (2U) +#define SEC_ENG_SE_CDET_ID1_EN_LEN (1U) +#define SEC_ENG_SE_CDET_ID1_EN_MSK (((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS) +#define SEC_ENG_SE_CDET_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS)) + +/* 0x500 : se_gmac_0_ctrl_0 */ +#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET (0x500) +#define SEC_ENG_SE_GMAC_0_BUSY SEC_ENG_SE_GMAC_0_BUSY +#define SEC_ENG_SE_GMAC_0_BUSY_POS (0U) +#define SEC_ENG_SE_GMAC_0_BUSY_LEN (1U) +#define SEC_ENG_SE_GMAC_0_BUSY_MSK (((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS) +#define SEC_ENG_SE_GMAC_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS)) +#define SEC_ENG_SE_GMAC_0_TRIG_1T SEC_ENG_SE_GMAC_0_TRIG_1T +#define SEC_ENG_SE_GMAC_0_TRIG_1T_POS (1U) +#define SEC_ENG_SE_GMAC_0_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_GMAC_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS) +#define SEC_ENG_SE_GMAC_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS)) +#define SEC_ENG_SE_GMAC_0_EN SEC_ENG_SE_GMAC_0_EN +#define SEC_ENG_SE_GMAC_0_EN_POS (2U) +#define SEC_ENG_SE_GMAC_0_EN_LEN (1U) +#define SEC_ENG_SE_GMAC_0_EN_MSK (((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS) +#define SEC_ENG_SE_GMAC_0_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS)) +#define SEC_ENG_SE_GMAC_0_INT SEC_ENG_SE_GMAC_0_INT +#define SEC_ENG_SE_GMAC_0_INT_POS (8U) +#define SEC_ENG_SE_GMAC_0_INT_LEN (1U) +#define SEC_ENG_SE_GMAC_0_INT_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS) +#define SEC_ENG_SE_GMAC_0_INT_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS)) +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T SEC_ENG_SE_GMAC_0_INT_CLR_1T +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_GMAC_0_INT_SET_1T SEC_ENG_SE_GMAC_0_INT_SET_1T +#define SEC_ENG_SE_GMAC_0_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_GMAC_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS) +#define SEC_ENG_SE_GMAC_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS)) +#define SEC_ENG_SE_GMAC_0_INT_MASK SEC_ENG_SE_GMAC_0_INT_MASK +#define SEC_ENG_SE_GMAC_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_GMAC_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_GMAC_0_INT_MASK_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS) +#define SEC_ENG_SE_GMAC_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS)) +#define SEC_ENG_SE_GMAC_0_T_ENDIAN SEC_ENG_SE_GMAC_0_T_ENDIAN +#define SEC_ENG_SE_GMAC_0_T_ENDIAN_POS (12U) +#define SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN (1U) +#define SEC_ENG_SE_GMAC_0_T_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS) +#define SEC_ENG_SE_GMAC_0_T_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS)) +#define SEC_ENG_SE_GMAC_0_H_ENDIAN SEC_ENG_SE_GMAC_0_H_ENDIAN +#define SEC_ENG_SE_GMAC_0_H_ENDIAN_POS (13U) +#define SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN (1U) +#define SEC_ENG_SE_GMAC_0_H_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS) +#define SEC_ENG_SE_GMAC_0_H_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS)) +#define SEC_ENG_SE_GMAC_0_X_ENDIAN SEC_ENG_SE_GMAC_0_X_ENDIAN +#define SEC_ENG_SE_GMAC_0_X_ENDIAN_POS (14U) +#define SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN (1U) +#define SEC_ENG_SE_GMAC_0_X_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS) +#define SEC_ENG_SE_GMAC_0_X_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS)) + +/* 0x504 : se_gmac_0_lca */ +#define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504) +#define SEC_ENG_SE_GMAC_0_LCA SEC_ENG_SE_GMAC_0_LCA +#define SEC_ENG_SE_GMAC_0_LCA_POS (0U) +#define SEC_ENG_SE_GMAC_0_LCA_LEN (32U) +#define SEC_ENG_SE_GMAC_0_LCA_MSK (((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS) +#define SEC_ENG_SE_GMAC_0_LCA_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS)) + +/* 0x508 : se_gmac_0_status */ +#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508) +#define SEC_ENG_SE_GMAC_0_STATUS SEC_ENG_SE_GMAC_0_STATUS +#define SEC_ENG_SE_GMAC_0_STATUS_POS (0U) +#define SEC_ENG_SE_GMAC_0_STATUS_LEN (32U) +#define SEC_ENG_SE_GMAC_0_STATUS_MSK (((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS) +#define SEC_ENG_SE_GMAC_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS)) + +/* 0x5FC : se_gmac_0_ctrl_prot */ +#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC) +#define SEC_ENG_SE_GMAC_PROT_EN SEC_ENG_SE_GMAC_PROT_EN +#define SEC_ENG_SE_GMAC_PROT_EN_POS (0U) +#define SEC_ENG_SE_GMAC_PROT_EN_LEN (1U) +#define SEC_ENG_SE_GMAC_PROT_EN_MSK (((1U << SEC_ENG_SE_GMAC_PROT_EN_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_POS) +#define SEC_ENG_SE_GMAC_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_PROT_EN_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_POS)) +#define SEC_ENG_SE_GMAC_ID0_EN SEC_ENG_SE_GMAC_ID0_EN +#define SEC_ENG_SE_GMAC_ID0_EN_POS (1U) +#define SEC_ENG_SE_GMAC_ID0_EN_LEN (1U) +#define SEC_ENG_SE_GMAC_ID0_EN_MSK (((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS) +#define SEC_ENG_SE_GMAC_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS)) +#define SEC_ENG_SE_GMAC_ID1_EN SEC_ENG_SE_GMAC_ID1_EN +#define SEC_ENG_SE_GMAC_ID1_EN_POS (2U) +#define SEC_ENG_SE_GMAC_ID1_EN_LEN (1U) +#define SEC_ENG_SE_GMAC_ID1_EN_MSK (((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS) +#define SEC_ENG_SE_GMAC_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS)) + +/* 0xF00 : se_ctrl_prot_rd */ +#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET (0xF00) +#define SEC_ENG_SE_SHA_PROT_EN_RD SEC_ENG_SE_SHA_PROT_EN_RD +#define SEC_ENG_SE_SHA_PROT_EN_RD_POS (0U) +#define SEC_ENG_SE_SHA_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_SHA_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_RD_POS) +#define SEC_ENG_SE_SHA_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_RD_POS)) +#define SEC_ENG_SE_SHA_ID0_EN_RD SEC_ENG_SE_SHA_ID0_EN_RD +#define SEC_ENG_SE_SHA_ID0_EN_RD_POS (1U) +#define SEC_ENG_SE_SHA_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_SHA_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS) +#define SEC_ENG_SE_SHA_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS)) +#define SEC_ENG_SE_SHA_ID1_EN_RD SEC_ENG_SE_SHA_ID1_EN_RD +#define SEC_ENG_SE_SHA_ID1_EN_RD_POS (2U) +#define SEC_ENG_SE_SHA_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_SHA_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS) +#define SEC_ENG_SE_SHA_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS)) +#define SEC_ENG_SE_AES_PROT_EN_RD SEC_ENG_SE_AES_PROT_EN_RD +#define SEC_ENG_SE_AES_PROT_EN_RD_POS (4U) +#define SEC_ENG_SE_AES_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_AES_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_AES_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_RD_POS) +#define SEC_ENG_SE_AES_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_RD_POS)) +#define SEC_ENG_SE_AES_ID0_EN_RD SEC_ENG_SE_AES_ID0_EN_RD +#define SEC_ENG_SE_AES_ID0_EN_RD_POS (5U) +#define SEC_ENG_SE_AES_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_AES_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS) +#define SEC_ENG_SE_AES_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS)) +#define SEC_ENG_SE_AES_ID1_EN_RD SEC_ENG_SE_AES_ID1_EN_RD +#define SEC_ENG_SE_AES_ID1_EN_RD_POS (6U) +#define SEC_ENG_SE_AES_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_AES_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS) +#define SEC_ENG_SE_AES_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS)) +#define SEC_ENG_SE_TRNG_PROT_EN_RD SEC_ENG_SE_TRNG_PROT_EN_RD +#define SEC_ENG_SE_TRNG_PROT_EN_RD_POS (8U) +#define SEC_ENG_SE_TRNG_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_TRNG_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_RD_POS) +#define SEC_ENG_SE_TRNG_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_RD_POS)) +#define SEC_ENG_SE_TRNG_ID0_EN_RD SEC_ENG_SE_TRNG_ID0_EN_RD +#define SEC_ENG_SE_TRNG_ID0_EN_RD_POS (9U) +#define SEC_ENG_SE_TRNG_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS) +#define SEC_ENG_SE_TRNG_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS)) +#define SEC_ENG_SE_TRNG_ID1_EN_RD SEC_ENG_SE_TRNG_ID1_EN_RD +#define SEC_ENG_SE_TRNG_ID1_EN_RD_POS (10U) +#define SEC_ENG_SE_TRNG_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_TRNG_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS) +#define SEC_ENG_SE_TRNG_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS)) +#define SEC_ENG_SE_PKA_PROT_EN_RD SEC_ENG_SE_PKA_PROT_EN_RD +#define SEC_ENG_SE_PKA_PROT_EN_RD_POS (12U) +#define SEC_ENG_SE_PKA_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_PKA_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_RD_POS) +#define SEC_ENG_SE_PKA_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_RD_POS)) +#define SEC_ENG_SE_PKA_ID0_EN_RD SEC_ENG_SE_PKA_ID0_EN_RD +#define SEC_ENG_SE_PKA_ID0_EN_RD_POS (13U) +#define SEC_ENG_SE_PKA_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_PKA_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS) +#define SEC_ENG_SE_PKA_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS)) +#define SEC_ENG_SE_PKA_ID1_EN_RD SEC_ENG_SE_PKA_ID1_EN_RD +#define SEC_ENG_SE_PKA_ID1_EN_RD_POS (14U) +#define SEC_ENG_SE_PKA_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_PKA_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS) +#define SEC_ENG_SE_PKA_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS)) +#define SEC_ENG_SE_CDET_PROT_EN_RD SEC_ENG_SE_CDET_PROT_EN_RD +#define SEC_ENG_SE_CDET_PROT_EN_RD_POS (16U) +#define SEC_ENG_SE_CDET_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_CDET_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_RD_POS) +#define SEC_ENG_SE_CDET_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_RD_POS)) +#define SEC_ENG_SE_CDET_ID0_EN_RD SEC_ENG_SE_CDET_ID0_EN_RD +#define SEC_ENG_SE_CDET_ID0_EN_RD_POS (17U) +#define SEC_ENG_SE_CDET_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_CDET_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS) +#define SEC_ENG_SE_CDET_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS)) +#define SEC_ENG_SE_CDET_ID1_EN_RD SEC_ENG_SE_CDET_ID1_EN_RD +#define SEC_ENG_SE_CDET_ID1_EN_RD_POS (18U) +#define SEC_ENG_SE_CDET_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_CDET_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS) +#define SEC_ENG_SE_CDET_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS)) +#define SEC_ENG_SE_GMAC_PROT_EN_RD SEC_ENG_SE_GMAC_PROT_EN_RD +#define SEC_ENG_SE_GMAC_PROT_EN_RD_POS (20U) +#define SEC_ENG_SE_GMAC_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_GMAC_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_RD_POS) +#define SEC_ENG_SE_GMAC_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_RD_POS)) +#define SEC_ENG_SE_GMAC_ID0_EN_RD SEC_ENG_SE_GMAC_ID0_EN_RD +#define SEC_ENG_SE_GMAC_ID0_EN_RD_POS (21U) +#define SEC_ENG_SE_GMAC_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_GMAC_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS) +#define SEC_ENG_SE_GMAC_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS)) +#define SEC_ENG_SE_GMAC_ID1_EN_RD SEC_ENG_SE_GMAC_ID1_EN_RD +#define SEC_ENG_SE_GMAC_ID1_EN_RD_POS (22U) +#define SEC_ENG_SE_GMAC_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_GMAC_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS) +#define SEC_ENG_SE_GMAC_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS)) +#define SEC_ENG_SE_DBG_DIS SEC_ENG_SE_DBG_DIS +#define SEC_ENG_SE_DBG_DIS_POS (31U) +#define SEC_ENG_SE_DBG_DIS_LEN (1U) +#define SEC_ENG_SE_DBG_DIS_MSK (((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS) +#define SEC_ENG_SE_DBG_DIS_UMSK (~(((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS)) + +/* 0xF04 : se_ctrl_reserved_0 */ +#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04) +#define SEC_ENG_SE_CTRL_RESERVED_0 SEC_ENG_SE_CTRL_RESERVED_0 +#define SEC_ENG_SE_CTRL_RESERVED_0_POS (0U) +#define SEC_ENG_SE_CTRL_RESERVED_0_LEN (32U) +#define SEC_ENG_SE_CTRL_RESERVED_0_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS) +#define SEC_ENG_SE_CTRL_RESERVED_0_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS)) + +/* 0xF08 : se_ctrl_reserved_1 */ +#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08) +#define SEC_ENG_SE_CTRL_RESERVED_1 SEC_ENG_SE_CTRL_RESERVED_1 +#define SEC_ENG_SE_CTRL_RESERVED_1_POS (0U) +#define SEC_ENG_SE_CTRL_RESERVED_1_LEN (32U) +#define SEC_ENG_SE_CTRL_RESERVED_1_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS) +#define SEC_ENG_SE_CTRL_RESERVED_1_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS)) + +/* 0xF0C : se_ctrl_reserved_2 */ +#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C) +#define SEC_ENG_SE_CTRL_RESERVED_2 SEC_ENG_SE_CTRL_RESERVED_2 +#define SEC_ENG_SE_CTRL_RESERVED_2_POS (0U) +#define SEC_ENG_SE_CTRL_RESERVED_2_LEN (32U) +#define SEC_ENG_SE_CTRL_RESERVED_2_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS) +#define SEC_ENG_SE_CTRL_RESERVED_2_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS)) + +struct sec_eng_reg { + /* 0x0 : se_sha_0_ctrl */ + union { + struct + { + uint32_t se_sha_0_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_sha_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_sha_0_mode : 3; /* [ 4: 2], r/w, 0x0 */ + uint32_t se_sha_0_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t se_sha_0_hash_sel : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t se_sha_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_sha_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_sha_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_sha_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_14 : 3; /* [14:12], rsvd, 0x0 */ + uint32_t se_sha_0_link_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t se_sha_0_msg_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_ctrl; + + /* 0x4 : se_sha_0_msa */ + union { + struct + { + uint32_t se_sha_0_msa : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_msa; + + /* 0x8 : se_sha_0_status */ + union { + struct + { + uint32_t se_sha_0_status : 32; /* [31: 0], r, 0x41 */ + } BF; + uint32_t WORD; + } se_sha_0_status; + + /* 0xC : se_sha_0_endian */ + union { + struct + { + uint32_t se_sha_0_dout_endian : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_endian; + + /* 0x10 : se_sha_0_hash_l_0 */ + union { + struct + { + uint32_t se_sha_0_hash_l_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_0; + + /* 0x14 : se_sha_0_hash_l_1 */ + union { + struct + { + uint32_t se_sha_0_hash_l_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_1; + + /* 0x18 : se_sha_0_hash_l_2 */ + union { + struct + { + uint32_t se_sha_0_hash_l_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_2; + + /* 0x1C : se_sha_0_hash_l_3 */ + union { + struct + { + uint32_t se_sha_0_hash_l_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_3; + + /* 0x20 : se_sha_0_hash_l_4 */ + union { + struct + { + uint32_t se_sha_0_hash_l_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_4; + + /* 0x24 : se_sha_0_hash_l_5 */ + union { + struct + { + uint32_t se_sha_0_hash_l_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_5; + + /* 0x28 : se_sha_0_hash_l_6 */ + union { + struct + { + uint32_t se_sha_0_hash_l_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_6; + + /* 0x2C : se_sha_0_hash_l_7 */ + union { + struct + { + uint32_t se_sha_0_hash_l_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_7; + + /* 0x30 : se_sha_0_hash_h_0 */ + union { + struct + { + uint32_t se_sha_0_hash_h_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_0; + + /* 0x34 : se_sha_0_hash_h_1 */ + union { + struct + { + uint32_t se_sha_0_hash_h_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_1; + + /* 0x38 : se_sha_0_hash_h_2 */ + union { + struct + { + uint32_t se_sha_0_hash_h_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_2; + + /* 0x3C : se_sha_0_hash_h_3 */ + union { + struct + { + uint32_t se_sha_0_hash_h_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_3; + + /* 0x40 : se_sha_0_hash_h_4 */ + union { + struct + { + uint32_t se_sha_0_hash_h_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_4; + + /* 0x44 : se_sha_0_hash_h_5 */ + union { + struct + { + uint32_t se_sha_0_hash_h_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_5; + + /* 0x48 : se_sha_0_hash_h_6 */ + union { + struct + { + uint32_t se_sha_0_hash_h_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_6; + + /* 0x4C : se_sha_0_hash_h_7 */ + union { + struct + { + uint32_t se_sha_0_hash_h_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_7; + + /* 0x50 : se_sha_0_link */ + union { + struct + { + uint32_t se_sha_0_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_link; + + /* 0x54 reserved */ + uint8_t RESERVED0x54[168]; + + /* 0xFC : se_sha_0_ctrl_prot */ + union { + struct + { + uint32_t se_sha_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_sha_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_sha_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_ctrl_prot; + + /* 0x100 : se_aes_0_ctrl */ + union { + struct + { + uint32_t se_aes_0_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_aes_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_aes_0_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_aes_0_mode : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t se_aes_0_dec_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t se_aes_0_dec_key_sel : 1; /* [ 6], r/w, 0x0 */ + uint32_t se_aes_0_hw_key_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t se_aes_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_aes_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_aes_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_aes_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t se_aes_0_block_mode : 2; /* [13:12], r/w, 0x0 */ + uint32_t se_aes_0_iv_sel : 1; /* [ 14], r/w, 0x0 */ + uint32_t se_aes_0_link_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t se_aes_0_msg_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_ctrl; + + /* 0x104 : se_aes_0_msa */ + union { + struct + { + uint32_t se_aes_0_msa : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_msa; + + /* 0x108 : se_aes_0_mda */ + union { + struct + { + uint32_t se_aes_0_mda : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_mda; + + /* 0x10C : se_aes_0_status */ + union { + struct + { + uint32_t se_aes_0_status : 32; /* [31: 0], r, 0x100 */ + } BF; + uint32_t WORD; + } se_aes_0_status; + + /* 0x110 : se_aes_0_iv_0 */ + union { + struct + { + uint32_t se_aes_0_iv_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_iv_0; + + /* 0x114 : se_aes_0_iv_1 */ + union { + struct + { + uint32_t se_aes_0_iv_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_iv_1; + + /* 0x118 : se_aes_0_iv_2 */ + union { + struct + { + uint32_t se_aes_0_iv_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_iv_2; + + /* 0x11C : se_aes_0_iv_3 */ + union { + struct + { + uint32_t se_aes_0_iv_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_iv_3; + + /* 0x120 : se_aes_0_key_0 */ + union { + struct + { + uint32_t se_aes_0_key_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_0; + + /* 0x124 : se_aes_0_key_1 */ + union { + struct + { + uint32_t se_aes_0_key_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_1; + + /* 0x128 : se_aes_0_key_2 */ + union { + struct + { + uint32_t se_aes_0_key_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_2; + + /* 0x12C : se_aes_0_key_3 */ + union { + struct + { + uint32_t se_aes_0_key_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_3; + + /* 0x130 : se_aes_0_key_4 */ + union { + struct + { + uint32_t se_aes_0_key_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_4; + + /* 0x134 : se_aes_0_key_5 */ + union { + struct + { + uint32_t se_aes_0_key_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_5; + + /* 0x138 : se_aes_0_key_6 */ + union { + struct + { + uint32_t se_aes_0_key_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_6; + + /* 0x13C : se_aes_0_key_7 */ + union { + struct + { + uint32_t se_aes_0_key_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_7; + + /* 0x140 : se_aes_0_key_sel_0 */ + union { + struct + { + uint32_t se_aes_0_key_sel_0 : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_sel_0; + + /* 0x144 : se_aes_0_key_sel_1 */ + union { + struct + { + uint32_t se_aes_0_key_sel_1 : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_sel_1; + + /* 0x148 : se_aes_0_endian */ + union { + struct + { + uint32_t se_aes_0_dout_endian : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_aes_0_din_endian : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_aes_0_key_endian : 1; /* [ 2], r/w, 0x1 */ + uint32_t se_aes_0_iv_endian : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_29 : 26; /* [29: 4], rsvd, 0x0 */ + uint32_t se_aes_0_ctr_len : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_endian; + + /* 0x14C : se_aes_0_sboot */ + union { + struct + { + uint32_t se_aes_0_sboot_key_sel : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_sboot; + + /* 0x150 : se_aes_0_link */ + union { + struct + { + uint32_t se_aes_0_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_link; + + /* 0x154 reserved */ + uint8_t RESERVED0x154[168]; + + /* 0x1FC : se_aes_0_ctrl_prot */ + union { + struct + { + uint32_t se_aes_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_aes_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_aes_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_ctrl_prot; + + /* 0x200 : se_trng_0_ctrl_0 */ + union { + struct + { + uint32_t se_trng_0_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_trng_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_trng_0_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_trng_0_dout_clr_1t : 1; /* [ 3], w1p, 0x0 */ + uint32_t se_trng_0_ht_error : 1; /* [ 4], r, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t se_trng_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_trng_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_trng_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_trng_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ + uint32_t se_trng_0_manual_fun_sel : 1; /* [ 13], r/w, 0x0 */ + uint32_t se_trng_0_manual_reseed : 1; /* [ 14], r/w, 0x0 */ + uint32_t se_trng_0_manual_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_0; + + /* 0x204 : se_trng_0_status */ + union { + struct + { + uint32_t se_trng_0_status : 32; /* [31: 0], r, 0x100020 */ + } BF; + uint32_t WORD; + } se_trng_0_status; + + /* 0x208 : se_trng_0_dout_0 */ + union { + struct + { + uint32_t se_trng_0_dout_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_0; + + /* 0x20C : se_trng_0_dout_1 */ + union { + struct + { + uint32_t se_trng_0_dout_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_1; + + /* 0x210 : se_trng_0_dout_2 */ + union { + struct + { + uint32_t se_trng_0_dout_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_2; + + /* 0x214 : se_trng_0_dout_3 */ + union { + struct + { + uint32_t se_trng_0_dout_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_3; + + /* 0x218 : se_trng_0_dout_4 */ + union { + struct + { + uint32_t se_trng_0_dout_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_4; + + /* 0x21C : se_trng_0_dout_5 */ + union { + struct + { + uint32_t se_trng_0_dout_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_5; + + /* 0x220 : se_trng_0_dout_6 */ + union { + struct + { + uint32_t se_trng_0_dout_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_6; + + /* 0x224 : se_trng_0_dout_7 */ + union { + struct + { + uint32_t se_trng_0_dout_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_7; + + /* 0x228 : se_trng_0_test */ + union { + struct + { + uint32_t se_trng_0_test_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t se_trng_0_cp_test_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t se_trng_0_cp_bypass : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_trng_0_ht_dis : 1; /* [ 3], r/w, 0x0 */ + uint32_t se_trng_0_ht_alarm_n : 8; /* [11: 4], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test; + + /* 0x22C : se_trng_0_ctrl_1 */ + union { + struct + { + uint32_t se_trng_0_reseed_n_lsb : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_1; + + /* 0x230 : se_trng_0_ctrl_2 */ + union { + struct + { + uint32_t se_trng_0_reseed_n_msb : 16; /* [15: 0], r/w, 0xff */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_2; + + /* 0x234 : se_trng_0_ctrl_3 */ + union { + struct + { + uint32_t se_trng_0_cp_ratio : 8; /* [ 7: 0], r/w, 0x3 */ + uint32_t se_trng_0_ht_rct_c : 8; /* [15: 8], r/w, 0x42 */ + uint32_t se_trng_0_ht_apt_c : 10; /* [25:16], r/w, 0x37a */ + uint32_t se_trng_0_ht_od_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */ + uint32_t se_trng_0_rosc_dis : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_3; + + /* 0x238 reserved */ + uint8_t RESERVED0x238[8]; + + /* 0x240 : se_trng_0_test_out_0 */ + union { + struct + { + uint32_t se_trng_0_test_out_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test_out_0; + + /* 0x244 : se_trng_0_test_out_1 */ + union { + struct + { + uint32_t se_trng_0_test_out_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test_out_1; + + /* 0x248 : se_trng_0_test_out_2 */ + union { + struct + { + uint32_t se_trng_0_test_out_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test_out_2; + + /* 0x24C : se_trng_0_test_out_3 */ + union { + struct + { + uint32_t se_trng_0_test_out_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test_out_3; + + /* 0x250 reserved */ + uint8_t RESERVED0x250[172]; + + /* 0x2FC : se_trng_0_ctrl_prot */ + union { + struct + { + uint32_t se_trng_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_trng_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_trng_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_prot; + + /* 0x300 : se_pka_0_ctrl_0 */ + union { + struct + { + uint32_t se_pka_0_done : 1; /* [ 0], r, 0x0 */ + uint32_t se_pka_0_done_clr_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_pka_0_busy : 1; /* [ 2], r, 0x0 */ + uint32_t se_pka_0_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t se_pka_0_prot_md : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t se_pka_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_pka_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_pka_0_int_set : 1; /* [ 10], r/w, 0x0 */ + uint32_t se_pka_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t se_pka_0_endian : 1; /* [ 12], r/w, 0x0 */ + uint32_t se_pka_0_ram_clr_md : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t se_pka_0_status_clr_1t : 1; /* [ 16], w1p, 0x0 */ + uint32_t se_pka_0_status : 15; /* [31:17], r, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_ctrl_0; + + /* 0x304 reserved */ + uint8_t RESERVED0x304[8]; + + /* 0x30C : se_pka_0_seed */ + union { + struct + { + uint32_t se_pka_0_seed : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_seed; + + /* 0x310 : se_pka_0_ctrl_1 */ + union { + struct + { + uint32_t se_pka_0_hburst : 3; /* [ 2: 0], r/w, 0x5 */ + uint32_t se_pka_0_hbypass : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_ctrl_1; + + /* 0x314 reserved */ + uint8_t RESERVED0x314[44]; + + /* 0x340 : se_pka_0_rw */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_rw; + + /* 0x344 reserved */ + uint8_t RESERVED0x344[28]; + + /* 0x360 : se_pka_0_rw_burst */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_rw_burst; + + /* 0x364 reserved */ + uint8_t RESERVED0x364[152]; + + /* 0x3FC : se_pka_0_ctrl_prot */ + union { + struct + { + uint32_t se_pka_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_pka_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_pka_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_ctrl_prot; + + /* 0x400 : se_cdet_0_ctrl_0 */ + union { + struct + { + uint32_t se_cdet_0_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t se_cdet_0_error : 1; /* [ 1], r, 0x0 */ + uint32_t se_cdet_0_status : 14; /* [15: 2], r, 0x1 */ + uint32_t se_cdet_0_g_loop_max : 8; /* [23:16], r/w, 0x64 */ + uint32_t se_cdet_0_g_loop_min : 8; /* [31:24], r/w, 0x21 */ + } BF; + uint32_t WORD; + } se_cdet_0_ctrl_0; + + /* 0x404 : se_cdet_0_ctrl_1 */ + union { + struct + { + uint32_t se_cdet_0_t_loop_n : 8; /* [ 7: 0], r/w, 0x32 */ + uint32_t se_cdet_0_t_dly_n : 8; /* [15: 8], r/w, 0x3 */ + uint32_t se_cdet_0_g_slp_n : 8; /* [23:16], r/w, 0xff */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_cdet_0_ctrl_1; + + /* 0x408 reserved */ + uint8_t RESERVED0x408[244]; + + /* 0x4FC : se_cdet_0_ctrl_prot */ + union { + struct + { + uint32_t se_cdet_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_cdet_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_cdet_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_cdet_0_ctrl_prot; + + /* 0x500 : se_gmac_0_ctrl_0 */ + union { + struct + { + uint32_t se_gmac_0_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_gmac_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_gmac_0_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ + uint32_t se_gmac_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_gmac_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_gmac_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_gmac_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t se_gmac_0_t_endian : 1; /* [ 12], r/w, 0x1 */ + uint32_t se_gmac_0_h_endian : 1; /* [ 13], r/w, 0x1 */ + uint32_t se_gmac_0_x_endian : 1; /* [ 14], r/w, 0x1 */ + uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_gmac_0_ctrl_0; + + /* 0x504 : se_gmac_0_lca */ + union { + struct + { + uint32_t se_gmac_0_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_gmac_0_lca; + + /* 0x508 : se_gmac_0_status */ + union { + struct + { + uint32_t se_gmac_0_status : 32; /* [31: 0], r, 0xf1000000L */ + } BF; + uint32_t WORD; + } se_gmac_0_status; + + /* 0x50c reserved */ + uint8_t RESERVED0x50c[240]; + + /* 0x5FC : se_gmac_0_ctrl_prot */ + union { + struct + { + uint32_t se_gmac_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_gmac_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_gmac_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_gmac_0_ctrl_prot; + + /* 0x600 reserved */ + uint8_t RESERVED0x600[2304]; + + /* 0xF00 : se_ctrl_prot_rd */ + union { + struct + { + uint32_t se_sha_prot_en_rd : 1; /* [ 0], r, 0x1 */ + uint32_t se_sha_id0_en_rd : 1; /* [ 1], r, 0x1 */ + uint32_t se_sha_id1_en_rd : 1; /* [ 2], r, 0x1 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t se_aes_prot_en_rd : 1; /* [ 4], r, 0x1 */ + uint32_t se_aes_id0_en_rd : 1; /* [ 5], r, 0x1 */ + uint32_t se_aes_id1_en_rd : 1; /* [ 6], r, 0x1 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t se_trng_prot_en_rd : 1; /* [ 8], r, 0x1 */ + uint32_t se_trng_id0_en_rd : 1; /* [ 9], r, 0x1 */ + uint32_t se_trng_id1_en_rd : 1; /* [ 10], r, 0x1 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t se_pka_prot_en_rd : 1; /* [ 12], r, 0x1 */ + uint32_t se_pka_id0_en_rd : 1; /* [ 13], r, 0x1 */ + uint32_t se_pka_id1_en_rd : 1; /* [ 14], r, 0x1 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t se_cdet_prot_en_rd : 1; /* [ 16], r, 0x1 */ + uint32_t se_cdet_id0_en_rd : 1; /* [ 17], r, 0x1 */ + uint32_t se_cdet_id1_en_rd : 1; /* [ 18], r, 0x1 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t se_gmac_prot_en_rd : 1; /* [ 20], r, 0x1 */ + uint32_t se_gmac_id0_en_rd : 1; /* [ 21], r, 0x1 */ + uint32_t se_gmac_id1_en_rd : 1; /* [ 22], r, 0x1 */ + uint32_t reserved_23_30 : 8; /* [30:23], rsvd, 0x0 */ + uint32_t se_dbg_dis : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } se_ctrl_prot_rd; + + /* 0xF04 : se_ctrl_reserved_0 */ + union { + struct + { + uint32_t se_ctrl_reserved_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_ctrl_reserved_0; + + /* 0xF08 : se_ctrl_reserved_1 */ + union { + struct + { + uint32_t se_ctrl_reserved_1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } se_ctrl_reserved_1; + + /* 0xF0C : se_ctrl_reserved_2 */ + union { + struct + { + uint32_t se_ctrl_reserved_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_ctrl_reserved_2; +}; + +typedef volatile struct sec_eng_reg sec_eng_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : se_sha_ctrl */ +#define SEC_ENG_SE_SHA_CTRL_OFFSET (0x0) +#define SEC_ENG_SE_SHA_BUSY SEC_ENG_SE_SHA_BUSY +#define SEC_ENG_SE_SHA_BUSY_POS (0U) +#define SEC_ENG_SE_SHA_BUSY_LEN (1U) +#define SEC_ENG_SE_SHA_BUSY_MSK (((1U << SEC_ENG_SE_SHA_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_BUSY_POS) +#define SEC_ENG_SE_SHA_BUSY_UMSK (~(((1U << SEC_ENG_SE_SHA_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_BUSY_POS)) +#define SEC_ENG_SE_SHA_TRIG_1T SEC_ENG_SE_SHA_TRIG_1T +#define SEC_ENG_SE_SHA_TRIG_1T_POS (1U) +#define SEC_ENG_SE_SHA_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_SHA_TRIG_1T_MSK (((1U << SEC_ENG_SE_SHA_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_TRIG_1T_POS) +#define SEC_ENG_SE_SHA_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_TRIG_1T_POS)) +#define SEC_ENG_SE_SHA_MODE SEC_ENG_SE_SHA_MODE +#define SEC_ENG_SE_SHA_MODE_POS (2U) +#define SEC_ENG_SE_SHA_MODE_LEN (3U) +#define SEC_ENG_SE_SHA_MODE_MSK (((1U << SEC_ENG_SE_SHA_MODE_LEN) - 1) << SEC_ENG_SE_SHA_MODE_POS) +#define SEC_ENG_SE_SHA_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_MODE_LEN) - 1) << SEC_ENG_SE_SHA_MODE_POS)) +#define SEC_ENG_SE_SHA_EN SEC_ENG_SE_SHA_EN +#define SEC_ENG_SE_SHA_EN_POS (5U) +#define SEC_ENG_SE_SHA_EN_LEN (1U) +#define SEC_ENG_SE_SHA_EN_MSK (((1U << SEC_ENG_SE_SHA_EN_LEN) - 1) << SEC_ENG_SE_SHA_EN_POS) +#define SEC_ENG_SE_SHA_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_EN_LEN) - 1) << SEC_ENG_SE_SHA_EN_POS)) +#define SEC_ENG_SE_SHA_HASH_SEL SEC_ENG_SE_SHA_HASH_SEL +#define SEC_ENG_SE_SHA_HASH_SEL_POS (6U) +#define SEC_ENG_SE_SHA_HASH_SEL_LEN (1U) +#define SEC_ENG_SE_SHA_HASH_SEL_MSK (((1U << SEC_ENG_SE_SHA_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_HASH_SEL_POS) +#define SEC_ENG_SE_SHA_HASH_SEL_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_HASH_SEL_POS)) +#define SEC_ENG_SE_SHA_INT SEC_ENG_SE_SHA_INT +#define SEC_ENG_SE_SHA_INT_POS (8U) +#define SEC_ENG_SE_SHA_INT_LEN (1U) +#define SEC_ENG_SE_SHA_INT_MSK (((1U << SEC_ENG_SE_SHA_INT_LEN) - 1) << SEC_ENG_SE_SHA_INT_POS) +#define SEC_ENG_SE_SHA_INT_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_LEN) - 1) << SEC_ENG_SE_SHA_INT_POS)) +#define SEC_ENG_SE_SHA_INT_CLR_1T SEC_ENG_SE_SHA_INT_CLR_1T +#define SEC_ENG_SE_SHA_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_SHA_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_SHA_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_SHA_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_CLR_1T_POS) +#define SEC_ENG_SE_SHA_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_CLR_1T_POS)) +#define SEC_ENG_SE_SHA_INT_SET_1T SEC_ENG_SE_SHA_INT_SET_1T +#define SEC_ENG_SE_SHA_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_SHA_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_SHA_INT_SET_1T_MSK (((1U << SEC_ENG_SE_SHA_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_SET_1T_POS) +#define SEC_ENG_SE_SHA_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_SET_1T_POS)) +#define SEC_ENG_SE_SHA_INT_MASK SEC_ENG_SE_SHA_INT_MASK +#define SEC_ENG_SE_SHA_INT_MASK_POS (11U) +#define SEC_ENG_SE_SHA_INT_MASK_LEN (1U) +#define SEC_ENG_SE_SHA_INT_MASK_MSK (((1U << SEC_ENG_SE_SHA_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_INT_MASK_POS) +#define SEC_ENG_SE_SHA_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_INT_MASK_POS)) +#define SEC_ENG_SE_SHA_LINK_MODE SEC_ENG_SE_SHA_LINK_MODE +#define SEC_ENG_SE_SHA_LINK_MODE_POS (15U) +#define SEC_ENG_SE_SHA_LINK_MODE_LEN (1U) +#define SEC_ENG_SE_SHA_LINK_MODE_MSK (((1U << SEC_ENG_SE_SHA_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_LINK_MODE_POS) +#define SEC_ENG_SE_SHA_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_LINK_MODE_POS)) +#define SEC_ENG_SE_SHA_MSG_LEN SEC_ENG_SE_SHA_MSG_LEN +#define SEC_ENG_SE_SHA_MSG_LEN_POS (16U) +#define SEC_ENG_SE_SHA_MSG_LEN_LEN (16U) +#define SEC_ENG_SE_SHA_MSG_LEN_MSK (((1U << SEC_ENG_SE_SHA_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_MSG_LEN_POS) +#define SEC_ENG_SE_SHA_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_SHA_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_MSG_LEN_POS)) + +/* 0x4 : se_sha_msa */ +#define SEC_ENG_SE_SHA_MSA_OFFSET (0x4) +#define SEC_ENG_SE_SHA_MSA SEC_ENG_SE_SHA_MSA +#define SEC_ENG_SE_SHA_MSA_POS (0U) +#define SEC_ENG_SE_SHA_MSA_LEN (32U) +#define SEC_ENG_SE_SHA_MSA_MSK (((1U << SEC_ENG_SE_SHA_MSA_LEN) - 1) << SEC_ENG_SE_SHA_MSA_POS) +#define SEC_ENG_SE_SHA_MSA_UMSK (~(((1U << SEC_ENG_SE_SHA_MSA_LEN) - 1) << SEC_ENG_SE_SHA_MSA_POS)) + +/* 0x8 : se_sha_status */ +#define SEC_ENG_SE_SHA_STATUS_OFFSET (0x8) +#define SEC_ENG_SE_SHA_STATUS SEC_ENG_SE_SHA_STATUS +#define SEC_ENG_SE_SHA_STATUS_POS (0U) +#define SEC_ENG_SE_SHA_STATUS_LEN (32U) +#define SEC_ENG_SE_SHA_STATUS_MSK (((1U << SEC_ENG_SE_SHA_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_STATUS_POS) +#define SEC_ENG_SE_SHA_STATUS_UMSK (~(((1U << SEC_ENG_SE_SHA_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_STATUS_POS)) + +/* 0xc : se_sha_endian */ +#define SEC_ENG_SE_SHA_ENDIAN_OFFSET (0xc) +#define SEC_ENG_SE_SHA_DOUT_ENDIAN SEC_ENG_SE_SHA_DOUT_ENDIAN +#define SEC_ENG_SE_SHA_DOUT_ENDIAN_POS (0U) +#define SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN (1U) +#define SEC_ENG_SE_SHA_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_DOUT_ENDIAN_POS) +#define SEC_ENG_SE_SHA_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_DOUT_ENDIAN_POS)) + +/* 0x10 : se_sha_hash_l_0 */ +#define SEC_ENG_SE_SHA_HASH_L_0_OFFSET (0x10) +#define SEC_ENG_SE_SHA_HASH_L_0 SEC_ENG_SE_SHA_HASH_L_0 +#define SEC_ENG_SE_SHA_HASH_L_0_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_0_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_0_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_0_POS) +#define SEC_ENG_SE_SHA_HASH_L_0_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_0_POS)) + +/* 0x14 : se_sha_hash_l_1 */ +#define SEC_ENG_SE_SHA_HASH_L_1_OFFSET (0x14) +#define SEC_ENG_SE_SHA_HASH_L_1 SEC_ENG_SE_SHA_HASH_L_1 +#define SEC_ENG_SE_SHA_HASH_L_1_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_1_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_1_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_1_POS) +#define SEC_ENG_SE_SHA_HASH_L_1_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_1_POS)) + +/* 0x18 : se_sha_hash_l_2 */ +#define SEC_ENG_SE_SHA_HASH_L_2_OFFSET (0x18) +#define SEC_ENG_SE_SHA_HASH_L_2 SEC_ENG_SE_SHA_HASH_L_2 +#define SEC_ENG_SE_SHA_HASH_L_2_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_2_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_2_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_2_POS) +#define SEC_ENG_SE_SHA_HASH_L_2_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_2_POS)) + +/* 0x1c : se_sha_hash_l_3 */ +#define SEC_ENG_SE_SHA_HASH_L_3_OFFSET (0x1c) +#define SEC_ENG_SE_SHA_HASH_L_3 SEC_ENG_SE_SHA_HASH_L_3 +#define SEC_ENG_SE_SHA_HASH_L_3_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_3_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_3_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_3_POS) +#define SEC_ENG_SE_SHA_HASH_L_3_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_3_POS)) + +/* 0x20 : se_sha_hash_l_4 */ +#define SEC_ENG_SE_SHA_HASH_L_4_OFFSET (0x20) +#define SEC_ENG_SE_SHA_HASH_L_4 SEC_ENG_SE_SHA_HASH_L_4 +#define SEC_ENG_SE_SHA_HASH_L_4_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_4_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_4_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_4_POS) +#define SEC_ENG_SE_SHA_HASH_L_4_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_4_POS)) + +/* 0x24 : se_sha_hash_l_5 */ +#define SEC_ENG_SE_SHA_HASH_L_5_OFFSET (0x24) +#define SEC_ENG_SE_SHA_HASH_L_5 SEC_ENG_SE_SHA_HASH_L_5 +#define SEC_ENG_SE_SHA_HASH_L_5_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_5_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_5_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_5_POS) +#define SEC_ENG_SE_SHA_HASH_L_5_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_5_POS)) + +/* 0x28 : se_sha_hash_l_6 */ +#define SEC_ENG_SE_SHA_HASH_L_6_OFFSET (0x28) +#define SEC_ENG_SE_SHA_HASH_L_6 SEC_ENG_SE_SHA_HASH_L_6 +#define SEC_ENG_SE_SHA_HASH_L_6_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_6_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_6_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_6_POS) +#define SEC_ENG_SE_SHA_HASH_L_6_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_6_POS)) + +/* 0x2c : se_sha_hash_l_7 */ +#define SEC_ENG_SE_SHA_HASH_L_7_OFFSET (0x2c) +#define SEC_ENG_SE_SHA_HASH_L_7 SEC_ENG_SE_SHA_HASH_L_7 +#define SEC_ENG_SE_SHA_HASH_L_7_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_7_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_7_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_7_POS) +#define SEC_ENG_SE_SHA_HASH_L_7_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_7_POS)) + +/* 0x30 : se_sha_hash_h_0 */ +#define SEC_ENG_SE_SHA_HASH_H_0_OFFSET (0x30) +#define SEC_ENG_SE_SHA_HASH_H_0 SEC_ENG_SE_SHA_HASH_H_0 +#define SEC_ENG_SE_SHA_HASH_H_0_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_0_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_0_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_0_POS) +#define SEC_ENG_SE_SHA_HASH_H_0_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_0_POS)) + +/* 0x34 : se_sha_hash_h_1 */ +#define SEC_ENG_SE_SHA_HASH_H_1_OFFSET (0x34) +#define SEC_ENG_SE_SHA_HASH_H_1 SEC_ENG_SE_SHA_HASH_H_1 +#define SEC_ENG_SE_SHA_HASH_H_1_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_1_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_1_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_1_POS) +#define SEC_ENG_SE_SHA_HASH_H_1_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_1_POS)) + +/* 0x38 : se_sha_hash_h_2 */ +#define SEC_ENG_SE_SHA_HASH_H_2_OFFSET (0x38) +#define SEC_ENG_SE_SHA_HASH_H_2 SEC_ENG_SE_SHA_HASH_H_2 +#define SEC_ENG_SE_SHA_HASH_H_2_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_2_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_2_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_2_POS) +#define SEC_ENG_SE_SHA_HASH_H_2_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_2_POS)) + +/* 0x3c : se_sha_hash_h_3 */ +#define SEC_ENG_SE_SHA_HASH_H_3_OFFSET (0x3c) +#define SEC_ENG_SE_SHA_HASH_H_3 SEC_ENG_SE_SHA_HASH_H_3 +#define SEC_ENG_SE_SHA_HASH_H_3_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_3_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_3_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_3_POS) +#define SEC_ENG_SE_SHA_HASH_H_3_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_3_POS)) + +/* 0x40 : se_sha_hash_h_4 */ +#define SEC_ENG_SE_SHA_HASH_H_4_OFFSET (0x40) +#define SEC_ENG_SE_SHA_HASH_H_4 SEC_ENG_SE_SHA_HASH_H_4 +#define SEC_ENG_SE_SHA_HASH_H_4_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_4_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_4_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_4_POS) +#define SEC_ENG_SE_SHA_HASH_H_4_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_4_POS)) + +/* 0x44 : se_sha_hash_h_5 */ +#define SEC_ENG_SE_SHA_HASH_H_5_OFFSET (0x44) +#define SEC_ENG_SE_SHA_HASH_H_5 SEC_ENG_SE_SHA_HASH_H_5 +#define SEC_ENG_SE_SHA_HASH_H_5_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_5_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_5_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_5_POS) +#define SEC_ENG_SE_SHA_HASH_H_5_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_5_POS)) + +/* 0x48 : se_sha_hash_h_6 */ +#define SEC_ENG_SE_SHA_HASH_H_6_OFFSET (0x48) +#define SEC_ENG_SE_SHA_HASH_H_6 SEC_ENG_SE_SHA_HASH_H_6 +#define SEC_ENG_SE_SHA_HASH_H_6_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_6_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_6_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_6_POS) +#define SEC_ENG_SE_SHA_HASH_H_6_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_6_POS)) + +/* 0x4c : se_sha_hash_h_7 */ +#define SEC_ENG_SE_SHA_HASH_H_7_OFFSET (0x4c) +#define SEC_ENG_SE_SHA_HASH_H_7 SEC_ENG_SE_SHA_HASH_H_7 +#define SEC_ENG_SE_SHA_HASH_H_7_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_7_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_7_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_7_POS) +#define SEC_ENG_SE_SHA_HASH_H_7_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_7_POS)) + +/* 0x50 : se_sha_link */ +#define SEC_ENG_SE_SHA_LINK_OFFSET (0x50) +#define SEC_ENG_SE_SHA_LCA SEC_ENG_SE_SHA_LCA +#define SEC_ENG_SE_SHA_LCA_POS (0U) +#define SEC_ENG_SE_SHA_LCA_LEN (32U) +#define SEC_ENG_SE_SHA_LCA_MSK (((1U << SEC_ENG_SE_SHA_LCA_LEN) - 1) << SEC_ENG_SE_SHA_LCA_POS) +#define SEC_ENG_SE_SHA_LCA_UMSK (~(((1U << SEC_ENG_SE_SHA_LCA_LEN) - 1) << SEC_ENG_SE_SHA_LCA_POS)) + +/* 0xfc : se_sha_ctrl_prot */ +#define SEC_ENG_SE_SHA_CTRL_PROT_OFFSET (0xfc) +#define SEC_ENG_SE_SHA_PROT_EN SEC_ENG_SE_SHA_PROT_EN +#define SEC_ENG_SE_SHA_PROT_EN_POS (0U) +#define SEC_ENG_SE_SHA_PROT_EN_LEN (1U) +#define SEC_ENG_SE_SHA_PROT_EN_MSK (((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS) +#define SEC_ENG_SE_SHA_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS)) +#define SEC_ENG_SE_SHA_ID0_EN SEC_ENG_SE_SHA_ID0_EN +#define SEC_ENG_SE_SHA_ID0_EN_POS (1U) +#define SEC_ENG_SE_SHA_ID0_EN_LEN (1U) +#define SEC_ENG_SE_SHA_ID0_EN_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS) +#define SEC_ENG_SE_SHA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)) +#define SEC_ENG_SE_SHA_ID1_EN SEC_ENG_SE_SHA_ID1_EN +#define SEC_ENG_SE_SHA_ID1_EN_POS (2U) +#define SEC_ENG_SE_SHA_ID1_EN_LEN (1U) +#define SEC_ENG_SE_SHA_ID1_EN_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS) +#define SEC_ENG_SE_SHA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)) + +struct sec_eng_sha_reg { + /* 0x0 : se_sha_ctrl */ + union { + struct + { + uint32_t se_sha_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_sha_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_sha_mode : 3; /* [ 4: 2], r/w, 0x0 */ + uint32_t se_sha_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t se_sha_hash_sel : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t se_sha_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_sha_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_sha_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_sha_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_14 : 3; /* [14:12], rsvd, 0x0 */ + uint32_t se_sha_link_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t se_sha_msg_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_ctrl; + + /* 0x4 : se_sha_msa */ + union { + struct + { + uint32_t se_sha_msa : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_msa; + + /* 0x8 : se_sha_status */ + union { + struct + { + uint32_t se_sha_status : 32; /* [31: 0], r, 0x41 */ + } BF; + uint32_t WORD; + } se_sha_status; + + /* 0xc : se_sha_endian */ + union { + struct + { + uint32_t se_sha_dout_endian : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_endian; + + /* 0x10 : se_sha_hash_l_0 */ + union { + struct + { + uint32_t se_sha_hash_l_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_0; + + /* 0x14 : se_sha_hash_l_1 */ + union { + struct + { + uint32_t se_sha_hash_l_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_1; + + /* 0x18 : se_sha_hash_l_2 */ + union { + struct + { + uint32_t se_sha_hash_l_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_2; + + /* 0x1c : se_sha_hash_l_3 */ + union { + struct + { + uint32_t se_sha_hash_l_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_3; + + /* 0x20 : se_sha_hash_l_4 */ + union { + struct + { + uint32_t se_sha_hash_l_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_4; + + /* 0x24 : se_sha_hash_l_5 */ + union { + struct + { + uint32_t se_sha_hash_l_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_5; + + /* 0x28 : se_sha_hash_l_6 */ + union { + struct + { + uint32_t se_sha_hash_l_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_6; + + /* 0x2c : se_sha_hash_l_7 */ + union { + struct + { + uint32_t se_sha_hash_l_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_7; + + /* 0x30 : se_sha_hash_h_0 */ + union { + struct + { + uint32_t se_sha_hash_h_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_0; + + /* 0x34 : se_sha_hash_h_1 */ + union { + struct + { + uint32_t se_sha_hash_h_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_1; + + /* 0x38 : se_sha_hash_h_2 */ + union { + struct + { + uint32_t se_sha_hash_h_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_2; + + /* 0x3c : se_sha_hash_h_3 */ + union { + struct + { + uint32_t se_sha_hash_h_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_3; + + /* 0x40 : se_sha_hash_h_4 */ + union { + struct + { + uint32_t se_sha_hash_h_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_4; + + /* 0x44 : se_sha_hash_h_5 */ + union { + struct + { + uint32_t se_sha_hash_h_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_5; + + /* 0x48 : se_sha_hash_h_6 */ + union { + struct + { + uint32_t se_sha_hash_h_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_6; + + /* 0x4c : se_sha_hash_h_7 */ + union { + struct + { + uint32_t se_sha_hash_h_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_7; + + /* 0x50 : se_sha_link */ + union { + struct + { + uint32_t se_sha_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_link; + + /* 0x54 reserved */ + uint8_t RESERVED0x54[168]; + + /* 0xfc : se_sha_ctrl_prot */ + union { + struct + { + uint32_t se_sha_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_sha_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_sha_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_ctrl_prot; +}; + +typedef volatile struct sec_eng_sha_reg sec_eng_sha_reg_t; + +#define SEC_ENG_SHA_OFFSET 0x000 + +/*Following is reg patch*/ + +/* 0x0 : se_aes_ctrl */ +#define SEC_ENG_SE_AES_CTRL_OFFSET (0x0) +#define SEC_ENG_SE_AES_BUSY SEC_ENG_SE_AES_BUSY +#define SEC_ENG_SE_AES_BUSY_POS (0U) +#define SEC_ENG_SE_AES_BUSY_LEN (1U) +#define SEC_ENG_SE_AES_BUSY_MSK (((1U << SEC_ENG_SE_AES_BUSY_LEN) - 1) << SEC_ENG_SE_AES_BUSY_POS) +#define SEC_ENG_SE_AES_BUSY_UMSK (~(((1U << SEC_ENG_SE_AES_BUSY_LEN) - 1) << SEC_ENG_SE_AES_BUSY_POS)) +#define SEC_ENG_SE_AES_TRIG_1T SEC_ENG_SE_AES_TRIG_1T +#define SEC_ENG_SE_AES_TRIG_1T_POS (1U) +#define SEC_ENG_SE_AES_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_AES_TRIG_1T_MSK (((1U << SEC_ENG_SE_AES_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_TRIG_1T_POS) +#define SEC_ENG_SE_AES_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_AES_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_TRIG_1T_POS)) +#define SEC_ENG_SE_AES_EN SEC_ENG_SE_AES_EN +#define SEC_ENG_SE_AES_EN_POS (2U) +#define SEC_ENG_SE_AES_EN_LEN (1U) +#define SEC_ENG_SE_AES_EN_MSK (((1U << SEC_ENG_SE_AES_EN_LEN) - 1) << SEC_ENG_SE_AES_EN_POS) +#define SEC_ENG_SE_AES_EN_UMSK (~(((1U << SEC_ENG_SE_AES_EN_LEN) - 1) << SEC_ENG_SE_AES_EN_POS)) +#define SEC_ENG_SE_AES_MODE SEC_ENG_SE_AES_MODE +#define SEC_ENG_SE_AES_MODE_POS (3U) +#define SEC_ENG_SE_AES_MODE_LEN (2U) +#define SEC_ENG_SE_AES_MODE_MSK (((1U << SEC_ENG_SE_AES_MODE_LEN) - 1) << SEC_ENG_SE_AES_MODE_POS) +#define SEC_ENG_SE_AES_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_MODE_LEN) - 1) << SEC_ENG_SE_AES_MODE_POS)) +#define SEC_ENG_SE_AES_DEC_EN SEC_ENG_SE_AES_DEC_EN +#define SEC_ENG_SE_AES_DEC_EN_POS (5U) +#define SEC_ENG_SE_AES_DEC_EN_LEN (1U) +#define SEC_ENG_SE_AES_DEC_EN_MSK (((1U << SEC_ENG_SE_AES_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_DEC_EN_POS) +#define SEC_ENG_SE_AES_DEC_EN_UMSK (~(((1U << SEC_ENG_SE_AES_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_DEC_EN_POS)) +#define SEC_ENG_SE_AES_DEC_KEY_SEL SEC_ENG_SE_AES_DEC_KEY_SEL +#define SEC_ENG_SE_AES_DEC_KEY_SEL_POS (6U) +#define SEC_ENG_SE_AES_DEC_KEY_SEL_LEN (1U) +#define SEC_ENG_SE_AES_DEC_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_DEC_KEY_SEL_POS) +#define SEC_ENG_SE_AES_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_DEC_KEY_SEL_POS)) +#define SEC_ENG_SE_AES_HW_KEY_EN SEC_ENG_SE_AES_HW_KEY_EN +#define SEC_ENG_SE_AES_HW_KEY_EN_POS (7U) +#define SEC_ENG_SE_AES_HW_KEY_EN_LEN (1U) +#define SEC_ENG_SE_AES_HW_KEY_EN_MSK (((1U << SEC_ENG_SE_AES_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_HW_KEY_EN_POS) +#define SEC_ENG_SE_AES_HW_KEY_EN_UMSK (~(((1U << SEC_ENG_SE_AES_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_HW_KEY_EN_POS)) +#define SEC_ENG_SE_AES_INT SEC_ENG_SE_AES_INT +#define SEC_ENG_SE_AES_INT_POS (8U) +#define SEC_ENG_SE_AES_INT_LEN (1U) +#define SEC_ENG_SE_AES_INT_MSK (((1U << SEC_ENG_SE_AES_INT_LEN) - 1) << SEC_ENG_SE_AES_INT_POS) +#define SEC_ENG_SE_AES_INT_UMSK (~(((1U << SEC_ENG_SE_AES_INT_LEN) - 1) << SEC_ENG_SE_AES_INT_POS)) +#define SEC_ENG_SE_AES_INT_CLR_1T SEC_ENG_SE_AES_INT_CLR_1T +#define SEC_ENG_SE_AES_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_AES_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_AES_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_AES_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_CLR_1T_POS) +#define SEC_ENG_SE_AES_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_AES_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_CLR_1T_POS)) +#define SEC_ENG_SE_AES_INT_SET_1T SEC_ENG_SE_AES_INT_SET_1T +#define SEC_ENG_SE_AES_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_AES_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_AES_INT_SET_1T_MSK (((1U << SEC_ENG_SE_AES_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_SET_1T_POS) +#define SEC_ENG_SE_AES_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_AES_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_SET_1T_POS)) +#define SEC_ENG_SE_AES_INT_MASK SEC_ENG_SE_AES_INT_MASK +#define SEC_ENG_SE_AES_INT_MASK_POS (11U) +#define SEC_ENG_SE_AES_INT_MASK_LEN (1U) +#define SEC_ENG_SE_AES_INT_MASK_MSK (((1U << SEC_ENG_SE_AES_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_INT_MASK_POS) +#define SEC_ENG_SE_AES_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_AES_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_INT_MASK_POS)) +#define SEC_ENG_SE_AES_BLOCK_MODE SEC_ENG_SE_AES_BLOCK_MODE +#define SEC_ENG_SE_AES_BLOCK_MODE_POS (12U) +#define SEC_ENG_SE_AES_BLOCK_MODE_LEN (2U) +#define SEC_ENG_SE_AES_BLOCK_MODE_MSK (((1U << SEC_ENG_SE_AES_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_BLOCK_MODE_POS) +#define SEC_ENG_SE_AES_BLOCK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_BLOCK_MODE_POS)) +#define SEC_ENG_SE_AES_IV_SEL SEC_ENG_SE_AES_IV_SEL +#define SEC_ENG_SE_AES_IV_SEL_POS (14U) +#define SEC_ENG_SE_AES_IV_SEL_LEN (1U) +#define SEC_ENG_SE_AES_IV_SEL_MSK (((1U << SEC_ENG_SE_AES_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_IV_SEL_POS) +#define SEC_ENG_SE_AES_IV_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_IV_SEL_POS)) +#define SEC_ENG_SE_AES_LINK_MODE SEC_ENG_SE_AES_LINK_MODE +#define SEC_ENG_SE_AES_LINK_MODE_POS (15U) +#define SEC_ENG_SE_AES_LINK_MODE_LEN (1U) +#define SEC_ENG_SE_AES_LINK_MODE_MSK (((1U << SEC_ENG_SE_AES_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_LINK_MODE_POS) +#define SEC_ENG_SE_AES_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_LINK_MODE_POS)) +#define SEC_ENG_SE_AES_MSG_LEN SEC_ENG_SE_AES_MSG_LEN +#define SEC_ENG_SE_AES_MSG_LEN_POS (16U) +#define SEC_ENG_SE_AES_MSG_LEN_LEN (16U) +#define SEC_ENG_SE_AES_MSG_LEN_MSK (((1U << SEC_ENG_SE_AES_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_MSG_LEN_POS) +#define SEC_ENG_SE_AES_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_MSG_LEN_POS)) + +/* 0x4 : se_aes_msa */ +#define SEC_ENG_SE_AES_MSA_OFFSET (0x4) +#define SEC_ENG_SE_AES_MSA SEC_ENG_SE_AES_MSA +#define SEC_ENG_SE_AES_MSA_POS (0U) +#define SEC_ENG_SE_AES_MSA_LEN (32U) +#define SEC_ENG_SE_AES_MSA_MSK (((1U << SEC_ENG_SE_AES_MSA_LEN) - 1) << SEC_ENG_SE_AES_MSA_POS) +#define SEC_ENG_SE_AES_MSA_UMSK (~(((1U << SEC_ENG_SE_AES_MSA_LEN) - 1) << SEC_ENG_SE_AES_MSA_POS)) + +/* 0x8 : se_aes_mda */ +#define SEC_ENG_SE_AES_MDA_OFFSET (0x8) +#define SEC_ENG_SE_AES_MDA SEC_ENG_SE_AES_MDA +#define SEC_ENG_SE_AES_MDA_POS (0U) +#define SEC_ENG_SE_AES_MDA_LEN (32U) +#define SEC_ENG_SE_AES_MDA_MSK (((1U << SEC_ENG_SE_AES_MDA_LEN) - 1) << SEC_ENG_SE_AES_MDA_POS) +#define SEC_ENG_SE_AES_MDA_UMSK (~(((1U << SEC_ENG_SE_AES_MDA_LEN) - 1) << SEC_ENG_SE_AES_MDA_POS)) + +/* 0xc : se_aes_status */ +#define SEC_ENG_SE_AES_STATUS_OFFSET (0xc) +#define SEC_ENG_SE_AES_STATUS SEC_ENG_SE_AES_STATUS +#define SEC_ENG_SE_AES_STATUS_POS (0U) +#define SEC_ENG_SE_AES_STATUS_LEN (32U) +#define SEC_ENG_SE_AES_STATUS_MSK (((1U << SEC_ENG_SE_AES_STATUS_LEN) - 1) << SEC_ENG_SE_AES_STATUS_POS) +#define SEC_ENG_SE_AES_STATUS_UMSK (~(((1U << SEC_ENG_SE_AES_STATUS_LEN) - 1) << SEC_ENG_SE_AES_STATUS_POS)) + +/* 0x10 : se_aes_iv_0 */ +#define SEC_ENG_SE_AES_IV_0_OFFSET (0x10) +#define SEC_ENG_SE_AES_IV_0 SEC_ENG_SE_AES_IV_0 +#define SEC_ENG_SE_AES_IV_0_POS (0U) +#define SEC_ENG_SE_AES_IV_0_LEN (32U) +#define SEC_ENG_SE_AES_IV_0_MSK (((1U << SEC_ENG_SE_AES_IV_0_LEN) - 1) << SEC_ENG_SE_AES_IV_0_POS) +#define SEC_ENG_SE_AES_IV_0_UMSK (~(((1U << SEC_ENG_SE_AES_IV_0_LEN) - 1) << SEC_ENG_SE_AES_IV_0_POS)) + +/* 0x14 : se_aes_iv_1 */ +#define SEC_ENG_SE_AES_IV_1_OFFSET (0x14) +#define SEC_ENG_SE_AES_IV_1 SEC_ENG_SE_AES_IV_1 +#define SEC_ENG_SE_AES_IV_1_POS (0U) +#define SEC_ENG_SE_AES_IV_1_LEN (32U) +#define SEC_ENG_SE_AES_IV_1_MSK (((1U << SEC_ENG_SE_AES_IV_1_LEN) - 1) << SEC_ENG_SE_AES_IV_1_POS) +#define SEC_ENG_SE_AES_IV_1_UMSK (~(((1U << SEC_ENG_SE_AES_IV_1_LEN) - 1) << SEC_ENG_SE_AES_IV_1_POS)) + +/* 0x18 : se_aes_iv_2 */ +#define SEC_ENG_SE_AES_IV_2_OFFSET (0x18) +#define SEC_ENG_SE_AES_IV_2 SEC_ENG_SE_AES_IV_2 +#define SEC_ENG_SE_AES_IV_2_POS (0U) +#define SEC_ENG_SE_AES_IV_2_LEN (32U) +#define SEC_ENG_SE_AES_IV_2_MSK (((1U << SEC_ENG_SE_AES_IV_2_LEN) - 1) << SEC_ENG_SE_AES_IV_2_POS) +#define SEC_ENG_SE_AES_IV_2_UMSK (~(((1U << SEC_ENG_SE_AES_IV_2_LEN) - 1) << SEC_ENG_SE_AES_IV_2_POS)) + +/* 0x1c : se_aes_iv_3 */ +#define SEC_ENG_SE_AES_IV_3_OFFSET (0x1c) +#define SEC_ENG_SE_AES_IV_3 SEC_ENG_SE_AES_IV_3 +#define SEC_ENG_SE_AES_IV_3_POS (0U) +#define SEC_ENG_SE_AES_IV_3_LEN (32U) +#define SEC_ENG_SE_AES_IV_3_MSK (((1U << SEC_ENG_SE_AES_IV_3_LEN) - 1) << SEC_ENG_SE_AES_IV_3_POS) +#define SEC_ENG_SE_AES_IV_3_UMSK (~(((1U << SEC_ENG_SE_AES_IV_3_LEN) - 1) << SEC_ENG_SE_AES_IV_3_POS)) + +/* 0x20 : se_aes_key_0 */ +#define SEC_ENG_SE_AES_KEY_0_OFFSET (0x20) +#define SEC_ENG_SE_AES_KEY_0 SEC_ENG_SE_AES_KEY_0 +#define SEC_ENG_SE_AES_KEY_0_POS (0U) +#define SEC_ENG_SE_AES_KEY_0_LEN (32U) +#define SEC_ENG_SE_AES_KEY_0_MSK (((1U << SEC_ENG_SE_AES_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_0_POS) +#define SEC_ENG_SE_AES_KEY_0_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_0_POS)) + +/* 0x24 : se_aes_key_1 */ +#define SEC_ENG_SE_AES_KEY_1_OFFSET (0x24) +#define SEC_ENG_SE_AES_KEY_1 SEC_ENG_SE_AES_KEY_1 +#define SEC_ENG_SE_AES_KEY_1_POS (0U) +#define SEC_ENG_SE_AES_KEY_1_LEN (32U) +#define SEC_ENG_SE_AES_KEY_1_MSK (((1U << SEC_ENG_SE_AES_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_1_POS) +#define SEC_ENG_SE_AES_KEY_1_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_1_POS)) + +/* 0x28 : se_aes_key_2 */ +#define SEC_ENG_SE_AES_KEY_2_OFFSET (0x28) +#define SEC_ENG_SE_AES_KEY_2 SEC_ENG_SE_AES_KEY_2 +#define SEC_ENG_SE_AES_KEY_2_POS (0U) +#define SEC_ENG_SE_AES_KEY_2_LEN (32U) +#define SEC_ENG_SE_AES_KEY_2_MSK (((1U << SEC_ENG_SE_AES_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_KEY_2_POS) +#define SEC_ENG_SE_AES_KEY_2_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_KEY_2_POS)) + +/* 0x2c : se_aes_key_3 */ +#define SEC_ENG_SE_AES_KEY_3_OFFSET (0x2c) +#define SEC_ENG_SE_AES_KEY_3 SEC_ENG_SE_AES_KEY_3 +#define SEC_ENG_SE_AES_KEY_3_POS (0U) +#define SEC_ENG_SE_AES_KEY_3_LEN (32U) +#define SEC_ENG_SE_AES_KEY_3_MSK (((1U << SEC_ENG_SE_AES_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_KEY_3_POS) +#define SEC_ENG_SE_AES_KEY_3_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_KEY_3_POS)) + +/* 0x30 : se_aes_key_4 */ +#define SEC_ENG_SE_AES_KEY_4_OFFSET (0x30) +#define SEC_ENG_SE_AES_KEY_4 SEC_ENG_SE_AES_KEY_4 +#define SEC_ENG_SE_AES_KEY_4_POS (0U) +#define SEC_ENG_SE_AES_KEY_4_LEN (32U) +#define SEC_ENG_SE_AES_KEY_4_MSK (((1U << SEC_ENG_SE_AES_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_KEY_4_POS) +#define SEC_ENG_SE_AES_KEY_4_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_KEY_4_POS)) + +/* 0x34 : se_aes_key_5 */ +#define SEC_ENG_SE_AES_KEY_5_OFFSET (0x34) +#define SEC_ENG_SE_AES_KEY_5 SEC_ENG_SE_AES_KEY_5 +#define SEC_ENG_SE_AES_KEY_5_POS (0U) +#define SEC_ENG_SE_AES_KEY_5_LEN (32U) +#define SEC_ENG_SE_AES_KEY_5_MSK (((1U << SEC_ENG_SE_AES_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_KEY_5_POS) +#define SEC_ENG_SE_AES_KEY_5_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_KEY_5_POS)) + +/* 0x38 : se_aes_key_6 */ +#define SEC_ENG_SE_AES_KEY_6_OFFSET (0x38) +#define SEC_ENG_SE_AES_KEY_6 SEC_ENG_SE_AES_KEY_6 +#define SEC_ENG_SE_AES_KEY_6_POS (0U) +#define SEC_ENG_SE_AES_KEY_6_LEN (32U) +#define SEC_ENG_SE_AES_KEY_6_MSK (((1U << SEC_ENG_SE_AES_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_KEY_6_POS) +#define SEC_ENG_SE_AES_KEY_6_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_KEY_6_POS)) + +/* 0x3c : se_aes_key_7 */ +#define SEC_ENG_SE_AES_KEY_7_OFFSET (0x3c) +#define SEC_ENG_SE_AES_KEY_7 SEC_ENG_SE_AES_KEY_7 +#define SEC_ENG_SE_AES_KEY_7_POS (0U) +#define SEC_ENG_SE_AES_KEY_7_LEN (32U) +#define SEC_ENG_SE_AES_KEY_7_MSK (((1U << SEC_ENG_SE_AES_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_KEY_7_POS) +#define SEC_ENG_SE_AES_KEY_7_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_KEY_7_POS)) + +/* 0x40 : se_aes_key_sel_0 */ +#define SEC_ENG_SE_AES_KEY_SEL_0_OFFSET (0x40) +#define SEC_ENG_SE_AES_KEY_SEL_0 SEC_ENG_SE_AES_KEY_SEL_0 +#define SEC_ENG_SE_AES_KEY_SEL_0_POS (0U) +#define SEC_ENG_SE_AES_KEY_SEL_0_LEN (2U) +#define SEC_ENG_SE_AES_KEY_SEL_0_MSK (((1U << SEC_ENG_SE_AES_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_0_POS) +#define SEC_ENG_SE_AES_KEY_SEL_0_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_0_POS)) + +/* 0x44 : se_aes_key_sel_1 */ +#define SEC_ENG_SE_AES_KEY_SEL_1_OFFSET (0x44) +#define SEC_ENG_SE_AES_KEY_SEL_1 SEC_ENG_SE_AES_KEY_SEL_1 +#define SEC_ENG_SE_AES_KEY_SEL_1_POS (0U) +#define SEC_ENG_SE_AES_KEY_SEL_1_LEN (2U) +#define SEC_ENG_SE_AES_KEY_SEL_1_MSK (((1U << SEC_ENG_SE_AES_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_1_POS) +#define SEC_ENG_SE_AES_KEY_SEL_1_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_1_POS)) + +/* 0x48 : se_aes_endian */ +#define SEC_ENG_SE_AES_ENDIAN_OFFSET (0x48) +#define SEC_ENG_SE_AES_DOUT_ENDIAN SEC_ENG_SE_AES_DOUT_ENDIAN +#define SEC_ENG_SE_AES_DOUT_ENDIAN_POS (0U) +#define SEC_ENG_SE_AES_DOUT_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DOUT_ENDIAN_POS) +#define SEC_ENG_SE_AES_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DOUT_ENDIAN_POS)) +#define SEC_ENG_SE_AES_DIN_ENDIAN SEC_ENG_SE_AES_DIN_ENDIAN +#define SEC_ENG_SE_AES_DIN_ENDIAN_POS (1U) +#define SEC_ENG_SE_AES_DIN_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_DIN_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DIN_ENDIAN_POS) +#define SEC_ENG_SE_AES_DIN_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DIN_ENDIAN_POS)) +#define SEC_ENG_SE_AES_KEY_ENDIAN SEC_ENG_SE_AES_KEY_ENDIAN +#define SEC_ENG_SE_AES_KEY_ENDIAN_POS (2U) +#define SEC_ENG_SE_AES_KEY_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_KEY_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_KEY_ENDIAN_POS) +#define SEC_ENG_SE_AES_KEY_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_KEY_ENDIAN_POS)) +#define SEC_ENG_SE_AES_IV_ENDIAN SEC_ENG_SE_AES_IV_ENDIAN +#define SEC_ENG_SE_AES_IV_ENDIAN_POS (3U) +#define SEC_ENG_SE_AES_IV_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_IV_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_IV_ENDIAN_POS) +#define SEC_ENG_SE_AES_IV_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_IV_ENDIAN_POS)) +#define SEC_ENG_SE_AES_CTR_LEN SEC_ENG_SE_AES_CTR_LEN +#define SEC_ENG_SE_AES_CTR_LEN_POS (30U) +#define SEC_ENG_SE_AES_CTR_LEN_LEN (2U) +#define SEC_ENG_SE_AES_CTR_LEN_MSK (((1U << SEC_ENG_SE_AES_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_CTR_LEN_POS) +#define SEC_ENG_SE_AES_CTR_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_CTR_LEN_POS)) + +/* 0x4c : se_aes_sboot */ +#define SEC_ENG_SE_AES_SBOOT_OFFSET (0x4c) +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL SEC_ENG_SE_AES_SBOOT_KEY_SEL +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS (0U) +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN (1U) +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS) +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS)) + +/* 0x50 : se_aes_link */ +#define SEC_ENG_SE_AES_LINK_OFFSET (0x50) +#define SEC_ENG_SE_AES_LCA SEC_ENG_SE_AES_LCA +#define SEC_ENG_SE_AES_LCA_POS (0U) +#define SEC_ENG_SE_AES_LCA_LEN (32U) +#define SEC_ENG_SE_AES_LCA_MSK (((1U << SEC_ENG_SE_AES_LCA_LEN) - 1) << SEC_ENG_SE_AES_LCA_POS) +#define SEC_ENG_SE_AES_LCA_UMSK (~(((1U << SEC_ENG_SE_AES_LCA_LEN) - 1) << SEC_ENG_SE_AES_LCA_POS)) + +/* 0xfc : se_aes_ctrl_prot */ +#define SEC_ENG_SE_AES_CTRL_PROT_OFFSET (0xfc) +#define SEC_ENG_SE_AES_PROT_EN SEC_ENG_SE_AES_PROT_EN +#define SEC_ENG_SE_AES_PROT_EN_POS (0U) +#define SEC_ENG_SE_AES_PROT_EN_LEN (1U) +#define SEC_ENG_SE_AES_PROT_EN_MSK (((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS) +#define SEC_ENG_SE_AES_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS)) +#define SEC_ENG_SE_AES_ID0_EN SEC_ENG_SE_AES_ID0_EN +#define SEC_ENG_SE_AES_ID0_EN_POS (1U) +#define SEC_ENG_SE_AES_ID0_EN_LEN (1U) +#define SEC_ENG_SE_AES_ID0_EN_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS) +#define SEC_ENG_SE_AES_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)) +#define SEC_ENG_SE_AES_ID1_EN SEC_ENG_SE_AES_ID1_EN +#define SEC_ENG_SE_AES_ID1_EN_POS (2U) +#define SEC_ENG_SE_AES_ID1_EN_LEN (1U) +#define SEC_ENG_SE_AES_ID1_EN_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS) +#define SEC_ENG_SE_AES_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)) + +struct sec_eng_aes_reg { + /* 0x0 : se_aes_ctrl */ + union { + struct + { + uint32_t se_aes_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_aes_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_aes_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_aes_mode : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t se_aes_dec_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t se_aes_dec_key_sel : 1; /* [ 6], r/w, 0x0 */ + uint32_t se_aes_hw_key_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t se_aes_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_aes_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_aes_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_aes_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t se_aes_block_mode : 2; /* [13:12], r/w, 0x0 */ + uint32_t se_aes_iv_sel : 1; /* [ 14], r/w, 0x0 */ + uint32_t se_aes_link_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t se_aes_msg_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_ctrl; + + /* 0x4 : se_aes_msa */ + union { + struct + { + uint32_t se_aes_msa : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_msa; + + /* 0x8 : se_aes_mda */ + union { + struct + { + uint32_t se_aes_mda : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_mda; + + /* 0xc : se_aes_status */ + union { + struct + { + uint32_t se_aes_status : 32; /* [31: 0], r, 0x100 */ + } BF; + uint32_t WORD; + } se_aes_status; + + /* 0x10 : se_aes_iv_0 */ + union { + struct + { + uint32_t se_aes_iv_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_iv_0; + + /* 0x14 : se_aes_iv_1 */ + union { + struct + { + uint32_t se_aes_iv_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_iv_1; + + /* 0x18 : se_aes_iv_2 */ + union { + struct + { + uint32_t se_aes_iv_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_iv_2; + + /* 0x1c : se_aes_iv_3 */ + union { + struct + { + uint32_t se_aes_iv_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_iv_3; + + /* 0x20 : se_aes_key_0 */ + union { + struct + { + uint32_t se_aes_key_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_0; + + /* 0x24 : se_aes_key_1 */ + union { + struct + { + uint32_t se_aes_key_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_1; + + /* 0x28 : se_aes_key_2 */ + union { + struct + { + uint32_t se_aes_key_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_2; + + /* 0x2c : se_aes_key_3 */ + union { + struct + { + uint32_t se_aes_key_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_3; + + /* 0x30 : se_aes_key_4 */ + union { + struct + { + uint32_t se_aes_key_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_4; + + /* 0x34 : se_aes_key_5 */ + union { + struct + { + uint32_t se_aes_key_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_5; + + /* 0x38 : se_aes_key_6 */ + union { + struct + { + uint32_t se_aes_key_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_6; + + /* 0x3c : se_aes_key_7 */ + union { + struct + { + uint32_t se_aes_key_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_7; + + /* 0x40 : se_aes_key_sel_0 */ + union { + struct + { + uint32_t se_aes_key_sel_0 : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_sel_0; + + /* 0x44 : se_aes_key_sel_1 */ + union { + struct + { + uint32_t se_aes_key_sel_1 : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_sel_1; + + /* 0x48 : se_aes_endian */ + union { + struct + { + uint32_t se_aes_dout_endian : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_aes_din_endian : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_aes_key_endian : 1; /* [ 2], r/w, 0x1 */ + uint32_t se_aes_iv_endian : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_29 : 26; /* [29: 4], rsvd, 0x0 */ + uint32_t se_aes_ctr_len : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_endian; + + /* 0x4c : se_aes_sboot */ + union { + struct + { + uint32_t se_aes_sboot_key_sel : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_sboot; + + /* 0x50 : se_aes_link */ + union { + struct + { + uint32_t se_aes_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_link; + + /* 0x54 reserved */ + uint8_t RESERVED0x54[168]; + + /* 0xfc : se_aes_ctrl_prot */ + union { + struct + { + uint32_t se_aes_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_aes_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_aes_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_ctrl_prot; +}; + +typedef volatile struct sec_eng_aes_reg sec_eng_aes_reg_t; + +#define SEC_ENG_AES_OFFSET 0x100 + +/*Following is reg patch*/ + +/* 0x0 : se_trng_ctrl_0 */ +#define SEC_ENG_SE_TRNG_CTRL_0_OFFSET (0x0) +#define SEC_ENG_SE_TRNG_BUSY SEC_ENG_SE_TRNG_BUSY +#define SEC_ENG_SE_TRNG_BUSY_POS (0U) +#define SEC_ENG_SE_TRNG_BUSY_LEN (1U) +#define SEC_ENG_SE_TRNG_BUSY_MSK (((1U << SEC_ENG_SE_TRNG_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_BUSY_POS) +#define SEC_ENG_SE_TRNG_BUSY_UMSK (~(((1U << SEC_ENG_SE_TRNG_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_BUSY_POS)) +#define SEC_ENG_SE_TRNG_TRIG_1T SEC_ENG_SE_TRNG_TRIG_1T +#define SEC_ENG_SE_TRNG_TRIG_1T_POS (1U) +#define SEC_ENG_SE_TRNG_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_TRIG_1T_MSK (((1U << SEC_ENG_SE_TRNG_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_TRIG_1T_POS) +#define SEC_ENG_SE_TRNG_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_TRIG_1T_POS)) +#define SEC_ENG_SE_TRNG_EN SEC_ENG_SE_TRNG_EN +#define SEC_ENG_SE_TRNG_EN_POS (2U) +#define SEC_ENG_SE_TRNG_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_EN_MSK (((1U << SEC_ENG_SE_TRNG_EN_LEN) - 1) << SEC_ENG_SE_TRNG_EN_POS) +#define SEC_ENG_SE_TRNG_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_EN_LEN) - 1) << SEC_ENG_SE_TRNG_EN_POS)) +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T SEC_ENG_SE_TRNG_DOUT_CLR_1T +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS (3U) +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS) +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS)) +#define SEC_ENG_SE_TRNG_HT_ERROR SEC_ENG_SE_TRNG_HT_ERROR +#define SEC_ENG_SE_TRNG_HT_ERROR_POS (4U) +#define SEC_ENG_SE_TRNG_HT_ERROR_LEN (1U) +#define SEC_ENG_SE_TRNG_HT_ERROR_MSK (((1U << SEC_ENG_SE_TRNG_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ERROR_POS) +#define SEC_ENG_SE_TRNG_HT_ERROR_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ERROR_POS)) +#define SEC_ENG_SE_TRNG_INT SEC_ENG_SE_TRNG_INT +#define SEC_ENG_SE_TRNG_INT_POS (8U) +#define SEC_ENG_SE_TRNG_INT_LEN (1U) +#define SEC_ENG_SE_TRNG_INT_MSK (((1U << SEC_ENG_SE_TRNG_INT_LEN) - 1) << SEC_ENG_SE_TRNG_INT_POS) +#define SEC_ENG_SE_TRNG_INT_UMSK (~(((1U << SEC_ENG_SE_TRNG_INT_LEN) - 1) << SEC_ENG_SE_TRNG_INT_POS)) +#define SEC_ENG_SE_TRNG_INT_CLR_1T SEC_ENG_SE_TRNG_INT_CLR_1T +#define SEC_ENG_SE_TRNG_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_TRNG_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_CLR_1T_POS) +#define SEC_ENG_SE_TRNG_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_CLR_1T_POS)) +#define SEC_ENG_SE_TRNG_INT_SET_1T SEC_ENG_SE_TRNG_INT_SET_1T +#define SEC_ENG_SE_TRNG_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_TRNG_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_INT_SET_1T_MSK (((1U << SEC_ENG_SE_TRNG_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_SET_1T_POS) +#define SEC_ENG_SE_TRNG_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_SET_1T_POS)) +#define SEC_ENG_SE_TRNG_INT_MASK SEC_ENG_SE_TRNG_INT_MASK +#define SEC_ENG_SE_TRNG_INT_MASK_POS (11U) +#define SEC_ENG_SE_TRNG_INT_MASK_LEN (1U) +#define SEC_ENG_SE_TRNG_INT_MASK_MSK (((1U << SEC_ENG_SE_TRNG_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_INT_MASK_POS) +#define SEC_ENG_SE_TRNG_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_TRNG_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_INT_MASK_POS)) +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL SEC_ENG_SE_TRNG_MANUAL_FUN_SEL +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS (13U) +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN (1U) +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_MSK (((1U << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS) +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS)) +#define SEC_ENG_SE_TRNG_MANUAL_RESEED SEC_ENG_SE_TRNG_MANUAL_RESEED +#define SEC_ENG_SE_TRNG_MANUAL_RESEED_POS (14U) +#define SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN (1U) +#define SEC_ENG_SE_TRNG_MANUAL_RESEED_MSK (((1U << SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_RESEED_POS) +#define SEC_ENG_SE_TRNG_MANUAL_RESEED_UMSK (~(((1U << SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_RESEED_POS)) +#define SEC_ENG_SE_TRNG_MANUAL_EN SEC_ENG_SE_TRNG_MANUAL_EN +#define SEC_ENG_SE_TRNG_MANUAL_EN_POS (15U) +#define SEC_ENG_SE_TRNG_MANUAL_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_MANUAL_EN_MSK (((1U << SEC_ENG_SE_TRNG_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_EN_POS) +#define SEC_ENG_SE_TRNG_MANUAL_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_EN_POS)) + +/* 0x4 : se_trng_status */ +#define SEC_ENG_SE_TRNG_STATUS_OFFSET (0x4) +#define SEC_ENG_SE_TRNG_STATUS SEC_ENG_SE_TRNG_STATUS +#define SEC_ENG_SE_TRNG_STATUS_POS (0U) +#define SEC_ENG_SE_TRNG_STATUS_LEN (32U) +#define SEC_ENG_SE_TRNG_STATUS_MSK (((1U << SEC_ENG_SE_TRNG_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_STATUS_POS) +#define SEC_ENG_SE_TRNG_STATUS_UMSK (~(((1U << SEC_ENG_SE_TRNG_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_STATUS_POS)) + +/* 0x8 : se_trng_dout_0 */ +#define SEC_ENG_SE_TRNG_DOUT_0_OFFSET (0x8) +#define SEC_ENG_SE_TRNG_DOUT_0 SEC_ENG_SE_TRNG_DOUT_0 +#define SEC_ENG_SE_TRNG_DOUT_0_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_0_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_0_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_0_POS) +#define SEC_ENG_SE_TRNG_DOUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_0_POS)) + +/* 0xc : se_trng_dout_1 */ +#define SEC_ENG_SE_TRNG_DOUT_1_OFFSET (0xc) +#define SEC_ENG_SE_TRNG_DOUT_1 SEC_ENG_SE_TRNG_DOUT_1 +#define SEC_ENG_SE_TRNG_DOUT_1_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_1_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_1_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_1_POS) +#define SEC_ENG_SE_TRNG_DOUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_1_POS)) + +/* 0x10 : se_trng_dout_2 */ +#define SEC_ENG_SE_TRNG_DOUT_2_OFFSET (0x10) +#define SEC_ENG_SE_TRNG_DOUT_2 SEC_ENG_SE_TRNG_DOUT_2 +#define SEC_ENG_SE_TRNG_DOUT_2_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_2_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_2_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_2_POS) +#define SEC_ENG_SE_TRNG_DOUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_2_POS)) + +/* 0x14 : se_trng_dout_3 */ +#define SEC_ENG_SE_TRNG_DOUT_3_OFFSET (0x14) +#define SEC_ENG_SE_TRNG_DOUT_3 SEC_ENG_SE_TRNG_DOUT_3 +#define SEC_ENG_SE_TRNG_DOUT_3_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_3_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_3_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_3_POS) +#define SEC_ENG_SE_TRNG_DOUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_3_POS)) + +/* 0x18 : se_trng_dout_4 */ +#define SEC_ENG_SE_TRNG_DOUT_4_OFFSET (0x18) +#define SEC_ENG_SE_TRNG_DOUT_4 SEC_ENG_SE_TRNG_DOUT_4 +#define SEC_ENG_SE_TRNG_DOUT_4_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_4_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_4_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_4_POS) +#define SEC_ENG_SE_TRNG_DOUT_4_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_4_POS)) + +/* 0x1c : se_trng_dout_5 */ +#define SEC_ENG_SE_TRNG_DOUT_5_OFFSET (0x1c) +#define SEC_ENG_SE_TRNG_DOUT_5 SEC_ENG_SE_TRNG_DOUT_5 +#define SEC_ENG_SE_TRNG_DOUT_5_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_5_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_5_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_5_POS) +#define SEC_ENG_SE_TRNG_DOUT_5_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_5_POS)) + +/* 0x20 : se_trng_dout_6 */ +#define SEC_ENG_SE_TRNG_DOUT_6_OFFSET (0x20) +#define SEC_ENG_SE_TRNG_DOUT_6 SEC_ENG_SE_TRNG_DOUT_6 +#define SEC_ENG_SE_TRNG_DOUT_6_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_6_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_6_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_6_POS) +#define SEC_ENG_SE_TRNG_DOUT_6_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_6_POS)) + +/* 0x24 : se_trng_dout_7 */ +#define SEC_ENG_SE_TRNG_DOUT_7_OFFSET (0x24) +#define SEC_ENG_SE_TRNG_DOUT_7 SEC_ENG_SE_TRNG_DOUT_7 +#define SEC_ENG_SE_TRNG_DOUT_7_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_7_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_7_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_7_POS) +#define SEC_ENG_SE_TRNG_DOUT_7_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_7_POS)) + +/* 0x28 : se_trng_test */ +#define SEC_ENG_SE_TRNG_TEST_OFFSET (0x28) +#define SEC_ENG_SE_TRNG_TEST_EN SEC_ENG_SE_TRNG_TEST_EN +#define SEC_ENG_SE_TRNG_TEST_EN_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_EN_POS) +#define SEC_ENG_SE_TRNG_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_EN_POS)) +#define SEC_ENG_SE_TRNG_CP_TEST_EN SEC_ENG_SE_TRNG_CP_TEST_EN +#define SEC_ENG_SE_TRNG_CP_TEST_EN_POS (1U) +#define SEC_ENG_SE_TRNG_CP_TEST_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_CP_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_CP_TEST_EN_POS) +#define SEC_ENG_SE_TRNG_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_CP_TEST_EN_POS)) +#define SEC_ENG_SE_TRNG_CP_BYPASS SEC_ENG_SE_TRNG_CP_BYPASS +#define SEC_ENG_SE_TRNG_CP_BYPASS_POS (2U) +#define SEC_ENG_SE_TRNG_CP_BYPASS_LEN (1U) +#define SEC_ENG_SE_TRNG_CP_BYPASS_MSK (((1U << SEC_ENG_SE_TRNG_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_CP_BYPASS_POS) +#define SEC_ENG_SE_TRNG_CP_BYPASS_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_CP_BYPASS_POS)) +#define SEC_ENG_SE_TRNG_HT_DIS SEC_ENG_SE_TRNG_HT_DIS +#define SEC_ENG_SE_TRNG_HT_DIS_POS (3U) +#define SEC_ENG_SE_TRNG_HT_DIS_LEN (1U) +#define SEC_ENG_SE_TRNG_HT_DIS_MSK (((1U << SEC_ENG_SE_TRNG_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_HT_DIS_POS) +#define SEC_ENG_SE_TRNG_HT_DIS_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_HT_DIS_POS)) +#define SEC_ENG_SE_TRNG_HT_ALARM_N SEC_ENG_SE_TRNG_HT_ALARM_N +#define SEC_ENG_SE_TRNG_HT_ALARM_N_POS (4U) +#define SEC_ENG_SE_TRNG_HT_ALARM_N_LEN (8U) +#define SEC_ENG_SE_TRNG_HT_ALARM_N_MSK (((1U << SEC_ENG_SE_TRNG_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ALARM_N_POS) +#define SEC_ENG_SE_TRNG_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ALARM_N_POS)) + +/* 0x2c : se_trng_ctrl_1 */ +#define SEC_ENG_SE_TRNG_CTRL_1_OFFSET (0x2c) +#define SEC_ENG_SE_TRNG_RESEED_N_LSB SEC_ENG_SE_TRNG_RESEED_N_LSB +#define SEC_ENG_SE_TRNG_RESEED_N_LSB_POS (0U) +#define SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN (32U) +#define SEC_ENG_SE_TRNG_RESEED_N_LSB_MSK (((1U << SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_LSB_POS) +#define SEC_ENG_SE_TRNG_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_LSB_POS)) + +/* 0x30 : se_trng_ctrl_2 */ +#define SEC_ENG_SE_TRNG_CTRL_2_OFFSET (0x30) +#define SEC_ENG_SE_TRNG_RESEED_N_MSB SEC_ENG_SE_TRNG_RESEED_N_MSB +#define SEC_ENG_SE_TRNG_RESEED_N_MSB_POS (0U) +#define SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN (16U) +#define SEC_ENG_SE_TRNG_RESEED_N_MSB_MSK (((1U << SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_MSB_POS) +#define SEC_ENG_SE_TRNG_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_MSB_POS)) + +/* 0x34 : se_trng_ctrl_3 */ +#define SEC_ENG_SE_TRNG_CTRL_3_OFFSET (0x34) +#define SEC_ENG_SE_TRNG_CP_RATIO SEC_ENG_SE_TRNG_CP_RATIO +#define SEC_ENG_SE_TRNG_CP_RATIO_POS (0U) +#define SEC_ENG_SE_TRNG_CP_RATIO_LEN (8U) +#define SEC_ENG_SE_TRNG_CP_RATIO_MSK (((1U << SEC_ENG_SE_TRNG_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_CP_RATIO_POS) +#define SEC_ENG_SE_TRNG_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_CP_RATIO_POS)) +#define SEC_ENG_SE_TRNG_HT_RCT_C SEC_ENG_SE_TRNG_HT_RCT_C +#define SEC_ENG_SE_TRNG_HT_RCT_C_POS (8U) +#define SEC_ENG_SE_TRNG_HT_RCT_C_LEN (8U) +#define SEC_ENG_SE_TRNG_HT_RCT_C_MSK (((1U << SEC_ENG_SE_TRNG_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_RCT_C_POS) +#define SEC_ENG_SE_TRNG_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_RCT_C_POS)) +#define SEC_ENG_SE_TRNG_HT_APT_C SEC_ENG_SE_TRNG_HT_APT_C +#define SEC_ENG_SE_TRNG_HT_APT_C_POS (16U) +#define SEC_ENG_SE_TRNG_HT_APT_C_LEN (10U) +#define SEC_ENG_SE_TRNG_HT_APT_C_MSK (((1U << SEC_ENG_SE_TRNG_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_APT_C_POS) +#define SEC_ENG_SE_TRNG_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_APT_C_POS)) +#define SEC_ENG_SE_TRNG_HT_OD_EN SEC_ENG_SE_TRNG_HT_OD_EN +#define SEC_ENG_SE_TRNG_HT_OD_EN_POS (26U) +#define SEC_ENG_SE_TRNG_HT_OD_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_HT_OD_EN_MSK (((1U << SEC_ENG_SE_TRNG_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_HT_OD_EN_POS) +#define SEC_ENG_SE_TRNG_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_HT_OD_EN_POS)) +#define SEC_ENG_SE_TRNG_ROSC_DIS SEC_ENG_SE_TRNG_ROSC_DIS +#define SEC_ENG_SE_TRNG_ROSC_DIS_POS (31U) +#define SEC_ENG_SE_TRNG_ROSC_DIS_LEN (1U) +#define SEC_ENG_SE_TRNG_ROSC_DIS_MSK (((1U << SEC_ENG_SE_TRNG_ROSC_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_ROSC_DIS_POS) +#define SEC_ENG_SE_TRNG_ROSC_DIS_UMSK (~(((1U << SEC_ENG_SE_TRNG_ROSC_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_ROSC_DIS_POS)) + +/* 0x40 : se_trng_test_out_0 */ +#define SEC_ENG_SE_TRNG_TEST_OUT_0_OFFSET (0x40) +#define SEC_ENG_SE_TRNG_TEST_OUT_0 SEC_ENG_SE_TRNG_TEST_OUT_0 +#define SEC_ENG_SE_TRNG_TEST_OUT_0_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_OUT_0_LEN (32U) +#define SEC_ENG_SE_TRNG_TEST_OUT_0_MSK (((1U << SEC_ENG_SE_TRNG_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_0_POS) +#define SEC_ENG_SE_TRNG_TEST_OUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_0_POS)) + +/* 0x44 : se_trng_test_out_1 */ +#define SEC_ENG_SE_TRNG_TEST_OUT_1_OFFSET (0x44) +#define SEC_ENG_SE_TRNG_TEST_OUT_1 SEC_ENG_SE_TRNG_TEST_OUT_1 +#define SEC_ENG_SE_TRNG_TEST_OUT_1_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_OUT_1_LEN (32U) +#define SEC_ENG_SE_TRNG_TEST_OUT_1_MSK (((1U << SEC_ENG_SE_TRNG_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_1_POS) +#define SEC_ENG_SE_TRNG_TEST_OUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_1_POS)) + +/* 0x48 : se_trng_test_out_2 */ +#define SEC_ENG_SE_TRNG_TEST_OUT_2_OFFSET (0x48) +#define SEC_ENG_SE_TRNG_TEST_OUT_2 SEC_ENG_SE_TRNG_TEST_OUT_2 +#define SEC_ENG_SE_TRNG_TEST_OUT_2_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_OUT_2_LEN (32U) +#define SEC_ENG_SE_TRNG_TEST_OUT_2_MSK (((1U << SEC_ENG_SE_TRNG_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_2_POS) +#define SEC_ENG_SE_TRNG_TEST_OUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_2_POS)) + +/* 0x4c : se_trng_test_out_3 */ +#define SEC_ENG_SE_TRNG_TEST_OUT_3_OFFSET (0x4c) +#define SEC_ENG_SE_TRNG_TEST_OUT_3 SEC_ENG_SE_TRNG_TEST_OUT_3 +#define SEC_ENG_SE_TRNG_TEST_OUT_3_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_OUT_3_LEN (32U) +#define SEC_ENG_SE_TRNG_TEST_OUT_3_MSK (((1U << SEC_ENG_SE_TRNG_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_3_POS) +#define SEC_ENG_SE_TRNG_TEST_OUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_3_POS)) + +/* 0xfc : se_trng_ctrl_prot */ +#define SEC_ENG_SE_TRNG_CTRL_PROT_OFFSET (0xfc) +#define SEC_ENG_SE_TRNG_PROT_EN SEC_ENG_SE_TRNG_PROT_EN +#define SEC_ENG_SE_TRNG_PROT_EN_POS (0U) +#define SEC_ENG_SE_TRNG_PROT_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_PROT_EN_MSK (((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS) +#define SEC_ENG_SE_TRNG_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS)) +#define SEC_ENG_SE_TRNG_ID0_EN SEC_ENG_SE_TRNG_ID0_EN +#define SEC_ENG_SE_TRNG_ID0_EN_POS (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS) +#define SEC_ENG_SE_TRNG_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)) +#define SEC_ENG_SE_TRNG_ID1_EN SEC_ENG_SE_TRNG_ID1_EN +#define SEC_ENG_SE_TRNG_ID1_EN_POS (2U) +#define SEC_ENG_SE_TRNG_ID1_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ID1_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS) +#define SEC_ENG_SE_TRNG_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)) + +struct sec_eng_trng_reg { + /* 0x0 : se_trng_ctrl_0 */ + union { + struct + { + uint32_t se_trng_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_trng_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_trng_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_trng_dout_clr_1t : 1; /* [ 3], w1p, 0x0 */ + uint32_t se_trng_ht_error : 1; /* [ 4], r, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t se_trng_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_trng_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_trng_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_trng_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ + uint32_t se_trng_manual_fun_sel : 1; /* [ 13], r/w, 0x0 */ + uint32_t se_trng_manual_reseed : 1; /* [ 14], r/w, 0x0 */ + uint32_t se_trng_manual_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_ctrl_0; + + /* 0x4 : se_trng_status */ + union { + struct + { + uint32_t se_trng_status : 32; /* [31: 0], r, 0x100020 */ + } BF; + uint32_t WORD; + } se_trng_status; + + /* 0x8 : se_trng_dout_0 */ + union { + struct + { + uint32_t se_trng_dout_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_0; + + /* 0xc : se_trng_dout_1 */ + union { + struct + { + uint32_t se_trng_dout_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_1; + + /* 0x10 : se_trng_dout_2 */ + union { + struct + { + uint32_t se_trng_dout_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_2; + + /* 0x14 : se_trng_dout_3 */ + union { + struct + { + uint32_t se_trng_dout_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_3; + + /* 0x18 : se_trng_dout_4 */ + union { + struct + { + uint32_t se_trng_dout_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_4; + + /* 0x1c : se_trng_dout_5 */ + union { + struct + { + uint32_t se_trng_dout_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_5; + + /* 0x20 : se_trng_dout_6 */ + union { + struct + { + uint32_t se_trng_dout_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_6; + + /* 0x24 : se_trng_dout_7 */ + union { + struct + { + uint32_t se_trng_dout_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_7; + + /* 0x28 : se_trng_test */ + union { + struct + { + uint32_t se_trng_test_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t se_trng_cp_test_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t se_trng_cp_bypass : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_trng_ht_dis : 1; /* [ 3], r/w, 0x0 */ + uint32_t se_trng_ht_alarm_n : 8; /* [11: 4], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test; + + /* 0x2c : se_trng_ctrl_1 */ + union { + struct + { + uint32_t se_trng_reseed_n_lsb : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } se_trng_ctrl_1; + + /* 0x30 : se_trng_ctrl_2 */ + union { + struct + { + uint32_t se_trng_reseed_n_msb : 16; /* [15: 0], r/w, 0xff */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_ctrl_2; + + /* 0x34 : se_trng_ctrl_3 */ + union { + struct + { + uint32_t se_trng_cp_ratio : 8; /* [ 7: 0], r/w, 0x3 */ + uint32_t se_trng_ht_rct_c : 8; /* [15: 8], r/w, 0x42 */ + uint32_t se_trng_ht_apt_c : 10; /* [25:16], r/w, 0x37a */ + uint32_t se_trng_ht_od_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */ + uint32_t se_trng_rosc_dis : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } se_trng_ctrl_3; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[8]; + + /* 0x40 : se_trng_test_out_0 */ + union { + struct + { + uint32_t se_trng_test_out_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test_out_0; + + /* 0x44 : se_trng_test_out_1 */ + union { + struct + { + uint32_t se_trng_test_out_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test_out_1; + + /* 0x48 : se_trng_test_out_2 */ + union { + struct + { + uint32_t se_trng_test_out_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test_out_2; + + /* 0x4c : se_trng_test_out_3 */ + union { + struct + { + uint32_t se_trng_test_out_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test_out_3; + + /* 0x50 reserved */ + uint8_t RESERVED0x50[172]; + + /* 0xfc : se_trng_ctrl_prot */ + union { + struct + { + uint32_t se_trng_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_trng_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_trng_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_ctrl_prot; +}; + +typedef volatile struct sec_eng_trng_reg sec_eng_trng_reg_t; + +#define SEC_ENG_TRNG_OFFSET 0x200 + +#endif /* __SEC_ENG_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sf_ctrl_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sf_ctrl_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..5c36954592ba1689c6d88b7448b046cd7735e690 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/sf_ctrl_reg.h @@ -0,0 +1,2450 @@ +/** + ****************************************************************************** + * @file sf_ctrl_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SF_CTRL_REG_H__ +#define __SF_CTRL_REG_H__ + +#include "bl602.h" + +/* 0x0 : sf_ctrl_0 */ +#define SF_CTRL_0_OFFSET (0x0) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL SF_CTRL_SF_CLK_SF_RX_INV_SEL +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS (2U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)) +#define SF_CTRL_SF_CLK_OUT_GATE_EN SF_CTRL_SF_CLK_OUT_GATE_EN +#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS (3U) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN (1U) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)) +#define SF_CTRL_SF_CLK_OUT_INV_SEL SF_CTRL_SF_CLK_OUT_INV_SEL +#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS (4U) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL SF_CTRL_SF_CLK_SAHB_SRAM_SEL +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS (5U) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_MSK (((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS)) +#define SF_CTRL_SF_IF_READ_DLY_N SF_CTRL_SF_IF_READ_DLY_N +#define SF_CTRL_SF_IF_READ_DLY_N_POS (8U) +#define SF_CTRL_SF_IF_READ_DLY_N_LEN (3U) +#define SF_CTRL_SF_IF_READ_DLY_N_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS) +#define SF_CTRL_SF_IF_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)) +#define SF_CTRL_SF_IF_READ_DLY_EN SF_CTRL_SF_IF_READ_DLY_EN +#define SF_CTRL_SF_IF_READ_DLY_EN_POS (11U) +#define SF_CTRL_SF_IF_READ_DLY_EN_LEN (1U) +#define SF_CTRL_SF_IF_READ_DLY_EN_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS) +#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)) +#define SF_CTRL_SF_IF_INT SF_CTRL_SF_IF_INT +#define SF_CTRL_SF_IF_INT_POS (16U) +#define SF_CTRL_SF_IF_INT_LEN (1U) +#define SF_CTRL_SF_IF_INT_MSK (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS) +#define SF_CTRL_SF_IF_INT_UMSK (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)) +#define SF_CTRL_SF_IF_INT_CLR SF_CTRL_SF_IF_INT_CLR +#define SF_CTRL_SF_IF_INT_CLR_POS (17U) +#define SF_CTRL_SF_IF_INT_CLR_LEN (1U) +#define SF_CTRL_SF_IF_INT_CLR_MSK (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS) +#define SF_CTRL_SF_IF_INT_CLR_UMSK (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)) +#define SF_CTRL_SF_IF_INT_SET SF_CTRL_SF_IF_INT_SET +#define SF_CTRL_SF_IF_INT_SET_POS (18U) +#define SF_CTRL_SF_IF_INT_SET_LEN (1U) +#define SF_CTRL_SF_IF_INT_SET_MSK (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS) +#define SF_CTRL_SF_IF_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)) +#define SF_CTRL_SF_AES_DLY_MODE SF_CTRL_SF_AES_DLY_MODE +#define SF_CTRL_SF_AES_DLY_MODE_POS (19U) +#define SF_CTRL_SF_AES_DLY_MODE_LEN (1U) +#define SF_CTRL_SF_AES_DLY_MODE_MSK (((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS) +#define SF_CTRL_SF_AES_DLY_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS)) +#define SF_CTRL_SF_AES_DOUT_ENDIAN SF_CTRL_SF_AES_DOUT_ENDIAN +#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS (20U) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)) +#define SF_CTRL_SF_AES_CTR_PLUS_EN SF_CTRL_SF_AES_CTR_PLUS_EN +#define SF_CTRL_SF_AES_CTR_PLUS_EN_POS (21U) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_LEN (1U) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_MSK (((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_UMSK (~(((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS)) +#define SF_CTRL_SF_AES_KEY_ENDIAN SF_CTRL_SF_AES_KEY_ENDIAN +#define SF_CTRL_SF_AES_KEY_ENDIAN_POS (22U) +#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS) +#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)) +#define SF_CTRL_SF_AES_IV_ENDIAN SF_CTRL_SF_AES_IV_ENDIAN +#define SF_CTRL_SF_AES_IV_ENDIAN_POS (23U) +#define SF_CTRL_SF_AES_IV_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_IV_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS) +#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)) +#define SF_CTRL_SF_ID SF_CTRL_SF_ID +#define SF_CTRL_SF_ID_POS (24U) +#define SF_CTRL_SF_ID_LEN (8U) +#define SF_CTRL_SF_ID_MSK (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS) +#define SF_CTRL_SF_ID_UMSK (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)) + +/* 0x4 : sf_ctrl_1 */ +#define SF_CTRL_1_OFFSET (0x4) +#define SF_CTRL_SF_IF_SR_PAT_MASK SF_CTRL_SF_IF_SR_PAT_MASK +#define SF_CTRL_SF_IF_SR_PAT_MASK_POS (0U) +#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN (8U) +#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS) +#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)) +#define SF_CTRL_SF_IF_SR_PAT SF_CTRL_SF_IF_SR_PAT +#define SF_CTRL_SF_IF_SR_PAT_POS (8U) +#define SF_CTRL_SF_IF_SR_PAT_LEN (8U) +#define SF_CTRL_SF_IF_SR_PAT_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS) +#define SF_CTRL_SF_IF_SR_PAT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)) +#define SF_CTRL_SF_IF_SR_INT SF_CTRL_SF_IF_SR_INT +#define SF_CTRL_SF_IF_SR_INT_POS (16U) +#define SF_CTRL_SF_IF_SR_INT_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_MSK (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS) +#define SF_CTRL_SF_IF_SR_INT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)) +#define SF_CTRL_SF_IF_SR_INT_EN SF_CTRL_SF_IF_SR_INT_EN +#define SF_CTRL_SF_IF_SR_INT_EN_POS (17U) +#define SF_CTRL_SF_IF_SR_INT_EN_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_EN_MSK (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS) +#define SF_CTRL_SF_IF_SR_INT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)) +#define SF_CTRL_SF_IF_SR_INT_SET SF_CTRL_SF_IF_SR_INT_SET +#define SF_CTRL_SF_IF_SR_INT_SET_POS (18U) +#define SF_CTRL_SF_IF_SR_INT_SET_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_SET_MSK (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS) +#define SF_CTRL_SF_IF_SR_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)) +#define SF_CTRL_SF_IF_0_ACK_LAT SF_CTRL_SF_IF_0_ACK_LAT +#define SF_CTRL_SF_IF_0_ACK_LAT_POS (20U) +#define SF_CTRL_SF_IF_0_ACK_LAT_LEN (3U) +#define SF_CTRL_SF_IF_0_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS) +#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)) +#define SF_CTRL_SF_IF_REG_HOLD SF_CTRL_SF_IF_REG_HOLD +#define SF_CTRL_SF_IF_REG_HOLD_POS (24U) +#define SF_CTRL_SF_IF_REG_HOLD_LEN (1U) +#define SF_CTRL_SF_IF_REG_HOLD_MSK (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS) +#define SF_CTRL_SF_IF_REG_HOLD_UMSK (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)) +#define SF_CTRL_SF_IF_REG_WP SF_CTRL_SF_IF_REG_WP +#define SF_CTRL_SF_IF_REG_WP_POS (25U) +#define SF_CTRL_SF_IF_REG_WP_LEN (1U) +#define SF_CTRL_SF_IF_REG_WP_MSK (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS) +#define SF_CTRL_SF_IF_REG_WP_UMSK (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)) +#define SF_CTRL_SF_AHB2SIF_STOPPED SF_CTRL_SF_AHB2SIF_STOPPED +#define SF_CTRL_SF_AHB2SIF_STOPPED_POS (26U) +#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS) +#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)) +#define SF_CTRL_SF_AHB2SIF_STOP SF_CTRL_SF_AHB2SIF_STOP +#define SF_CTRL_SF_AHB2SIF_STOP_POS (27U) +#define SF_CTRL_SF_AHB2SIF_STOP_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_STOP_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS) +#define SF_CTRL_SF_AHB2SIF_STOP_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)) +#define SF_CTRL_SF_IF_FN_SEL SF_CTRL_SF_IF_FN_SEL +#define SF_CTRL_SF_IF_FN_SEL_POS (28U) +#define SF_CTRL_SF_IF_FN_SEL_LEN (1U) +#define SF_CTRL_SF_IF_FN_SEL_MSK (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS) +#define SF_CTRL_SF_IF_FN_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)) +#define SF_CTRL_SF_IF_EN SF_CTRL_SF_IF_EN +#define SF_CTRL_SF_IF_EN_POS (29U) +#define SF_CTRL_SF_IF_EN_LEN (1U) +#define SF_CTRL_SF_IF_EN_MSK (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS) +#define SF_CTRL_SF_IF_EN_UMSK (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)) +#define SF_CTRL_SF_AHB2SIF_EN SF_CTRL_SF_AHB2SIF_EN +#define SF_CTRL_SF_AHB2SIF_EN_POS (30U) +#define SF_CTRL_SF_AHB2SIF_EN_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_EN_MSK (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS) +#define SF_CTRL_SF_AHB2SIF_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)) +#define SF_CTRL_SF_AHB2SRAM_EN SF_CTRL_SF_AHB2SRAM_EN +#define SF_CTRL_SF_AHB2SRAM_EN_POS (31U) +#define SF_CTRL_SF_AHB2SRAM_EN_LEN (1U) +#define SF_CTRL_SF_AHB2SRAM_EN_MSK (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS) +#define SF_CTRL_SF_AHB2SRAM_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)) + +/* 0x8 : sf_if_sahb_0 */ +#define SF_CTRL_SF_IF_SAHB_0_OFFSET (0x8) +#define SF_CTRL_SF_IF_BUSY SF_CTRL_SF_IF_BUSY +#define SF_CTRL_SF_IF_BUSY_POS (0U) +#define SF_CTRL_SF_IF_BUSY_LEN (1U) +#define SF_CTRL_SF_IF_BUSY_MSK (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS) +#define SF_CTRL_SF_IF_BUSY_UMSK (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)) +#define SF_CTRL_SF_IF_0_TRIG SF_CTRL_SF_IF_0_TRIG +#define SF_CTRL_SF_IF_0_TRIG_POS (1U) +#define SF_CTRL_SF_IF_0_TRIG_LEN (1U) +#define SF_CTRL_SF_IF_0_TRIG_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS) +#define SF_CTRL_SF_IF_0_TRIG_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)) +#define SF_CTRL_SF_IF_0_DAT_BYTE SF_CTRL_SF_IF_0_DAT_BYTE +#define SF_CTRL_SF_IF_0_DAT_BYTE_POS (2U) +#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN (10U) +#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS) +#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)) +#define SF_CTRL_SF_IF_0_DMY_BYTE SF_CTRL_SF_IF_0_DMY_BYTE +#define SF_CTRL_SF_IF_0_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_0_ADR_BYTE SF_CTRL_SF_IF_0_ADR_BYTE +#define SF_CTRL_SF_IF_0_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_0_CMD_BYTE SF_CTRL_SF_IF_0_CMD_BYTE +#define SF_CTRL_SF_IF_0_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_0_DAT_RW SF_CTRL_SF_IF_0_DAT_RW +#define SF_CTRL_SF_IF_0_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_0_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_0_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS) +#define SF_CTRL_SF_IF_0_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)) +#define SF_CTRL_SF_IF_0_DAT_EN SF_CTRL_SF_IF_0_DAT_EN +#define SF_CTRL_SF_IF_0_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_0_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS) +#define SF_CTRL_SF_IF_0_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)) +#define SF_CTRL_SF_IF_0_DMY_EN SF_CTRL_SF_IF_0_DMY_EN +#define SF_CTRL_SF_IF_0_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_0_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS) +#define SF_CTRL_SF_IF_0_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)) +#define SF_CTRL_SF_IF_0_ADR_EN SF_CTRL_SF_IF_0_ADR_EN +#define SF_CTRL_SF_IF_0_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_0_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS) +#define SF_CTRL_SF_IF_0_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)) +#define SF_CTRL_SF_IF_0_CMD_EN SF_CTRL_SF_IF_0_CMD_EN +#define SF_CTRL_SF_IF_0_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_0_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS) +#define SF_CTRL_SF_IF_0_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)) +#define SF_CTRL_SF_IF_0_SPI_MODE SF_CTRL_SF_IF_0_SPI_MODE +#define SF_CTRL_SF_IF_0_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_0_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_0_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS) +#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN SF_CTRL_SF_IF_0_QPI_MODE_EN +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)) + +/* 0xC : sf_if_sahb_1 */ +#define SF_CTRL_SF_IF_SAHB_1_OFFSET (0xC) +#define SF_CTRL_SF_IF_0_CMD_BUF_0 SF_CTRL_SF_IF_0_CMD_BUF_0 +#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)) + +/* 0x10 : sf_if_sahb_2 */ +#define SF_CTRL_SF_IF_SAHB_2_OFFSET (0x10) +#define SF_CTRL_SF_IF_0_CMD_BUF_1 SF_CTRL_SF_IF_0_CMD_BUF_1 +#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)) + +/* 0x14 : sf_if_iahb_0 */ +#define SF_CTRL_SF_IF_IAHB_0_OFFSET (0x14) +#define SF_CTRL_SF_IF_1_DMY_BYTE SF_CTRL_SF_IF_1_DMY_BYTE +#define SF_CTRL_SF_IF_1_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_1_ADR_BYTE SF_CTRL_SF_IF_1_ADR_BYTE +#define SF_CTRL_SF_IF_1_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_1_CMD_BYTE SF_CTRL_SF_IF_1_CMD_BYTE +#define SF_CTRL_SF_IF_1_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_1_DAT_RW SF_CTRL_SF_IF_1_DAT_RW +#define SF_CTRL_SF_IF_1_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_1_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_1_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS) +#define SF_CTRL_SF_IF_1_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)) +#define SF_CTRL_SF_IF_1_DAT_EN SF_CTRL_SF_IF_1_DAT_EN +#define SF_CTRL_SF_IF_1_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_1_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS) +#define SF_CTRL_SF_IF_1_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)) +#define SF_CTRL_SF_IF_1_DMY_EN SF_CTRL_SF_IF_1_DMY_EN +#define SF_CTRL_SF_IF_1_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_1_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS) +#define SF_CTRL_SF_IF_1_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)) +#define SF_CTRL_SF_IF_1_ADR_EN SF_CTRL_SF_IF_1_ADR_EN +#define SF_CTRL_SF_IF_1_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_1_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS) +#define SF_CTRL_SF_IF_1_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)) +#define SF_CTRL_SF_IF_1_CMD_EN SF_CTRL_SF_IF_1_CMD_EN +#define SF_CTRL_SF_IF_1_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_1_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS) +#define SF_CTRL_SF_IF_1_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)) +#define SF_CTRL_SF_IF_1_SPI_MODE SF_CTRL_SF_IF_1_SPI_MODE +#define SF_CTRL_SF_IF_1_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_1_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_1_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS) +#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN SF_CTRL_SF_IF_1_QPI_MODE_EN +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)) + +/* 0x18 : sf_if_iahb_1 */ +#define SF_CTRL_SF_IF_IAHB_1_OFFSET (0x18) +#define SF_CTRL_SF_IF_1_CMD_BUF_0 SF_CTRL_SF_IF_1_CMD_BUF_0 +#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)) + +/* 0x1C : sf_if_iahb_2 */ +#define SF_CTRL_SF_IF_IAHB_2_OFFSET (0x1C) +#define SF_CTRL_SF_IF_1_CMD_BUF_1 SF_CTRL_SF_IF_1_CMD_BUF_1 +#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)) + +/* 0x20 : sf_if_status_0 */ +#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20) +#define SF_CTRL_SF_IF_STATUS_0 SF_CTRL_SF_IF_STATUS_0 +#define SF_CTRL_SF_IF_STATUS_0_POS (0U) +#define SF_CTRL_SF_IF_STATUS_0_LEN (32U) +#define SF_CTRL_SF_IF_STATUS_0_MSK (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS) +#define SF_CTRL_SF_IF_STATUS_0_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)) + +/* 0x24 : sf_if_status_1 */ +#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24) +#define SF_CTRL_SF_IF_STATUS_1 SF_CTRL_SF_IF_STATUS_1 +#define SF_CTRL_SF_IF_STATUS_1_POS (0U) +#define SF_CTRL_SF_IF_STATUS_1_LEN (32U) +#define SF_CTRL_SF_IF_STATUS_1_MSK (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS) +#define SF_CTRL_SF_IF_STATUS_1_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)) + +/* 0x28 : sf_aes */ +#define SF_CTRL_SF_AES_OFFSET (0x28) +#define SF_CTRL_SF_AES_EN SF_CTRL_SF_AES_EN +#define SF_CTRL_SF_AES_EN_POS (0U) +#define SF_CTRL_SF_AES_EN_LEN (1U) +#define SF_CTRL_SF_AES_EN_MSK (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS) +#define SF_CTRL_SF_AES_EN_UMSK (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)) +#define SF_CTRL_SF_AES_MODE SF_CTRL_SF_AES_MODE +#define SF_CTRL_SF_AES_MODE_POS (1U) +#define SF_CTRL_SF_AES_MODE_LEN (2U) +#define SF_CTRL_SF_AES_MODE_MSK (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS) +#define SF_CTRL_SF_AES_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)) +#define SF_CTRL_SF_AES_PREF_TRIG SF_CTRL_SF_AES_PREF_TRIG +#define SF_CTRL_SF_AES_PREF_TRIG_POS (3U) +#define SF_CTRL_SF_AES_PREF_TRIG_LEN (1U) +#define SF_CTRL_SF_AES_PREF_TRIG_MSK (((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS) +#define SF_CTRL_SF_AES_PREF_TRIG_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS)) +#define SF_CTRL_SF_AES_PREF_BUSY SF_CTRL_SF_AES_PREF_BUSY +#define SF_CTRL_SF_AES_PREF_BUSY_POS (4U) +#define SF_CTRL_SF_AES_PREF_BUSY_LEN (1U) +#define SF_CTRL_SF_AES_PREF_BUSY_MSK (((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS) +#define SF_CTRL_SF_AES_PREF_BUSY_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS)) +#define SF_CTRL_SF_AES_STATUS SF_CTRL_SF_AES_STATUS +#define SF_CTRL_SF_AES_STATUS_POS (5U) +#define SF_CTRL_SF_AES_STATUS_LEN (27U) +#define SF_CTRL_SF_AES_STATUS_MSK (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS) +#define SF_CTRL_SF_AES_STATUS_UMSK (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)) + +/* 0x2C : sf_ahb2sif_status */ +#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C) +#define SF_CTRL_SF_AHB2SIF_STATUS SF_CTRL_SF_AHB2SIF_STATUS +#define SF_CTRL_SF_AHB2SIF_STATUS_POS (0U) +#define SF_CTRL_SF_AHB2SIF_STATUS_LEN (32U) +#define SF_CTRL_SF_AHB2SIF_STATUS_MSK (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS) +#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)) + +/* 0x30 : sf_if_io_dly_0 */ +#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET (0x30) +#define SF_CTRL_SF_CS_DLY_SEL SF_CTRL_SF_CS_DLY_SEL +#define SF_CTRL_SF_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS) +#define SF_CTRL_SF_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL SF_CTRL_SF_CLK_OUT_DLY_SEL +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_OE_DLY_SEL SF_CTRL_SF_DQS_OE_DLY_SEL +#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_DI_DLY_SEL SF_CTRL_SF_DQS_DI_DLY_SEL +#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_DO_DLY_SEL SF_CTRL_SF_DQS_DO_DLY_SEL +#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)) + +/* 0x34 : sf_if_io_dly_1 */ +#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET (0x34) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL SF_CTRL_SF_IO_0_OE_DLY_SEL +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL SF_CTRL_SF_IO_0_DI_DLY_SEL +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL SF_CTRL_SF_IO_0_DO_DLY_SEL +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)) + +/* 0x38 : sf_if_io_dly_2 */ +#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET (0x38) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL SF_CTRL_SF_IO_1_OE_DLY_SEL +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL SF_CTRL_SF_IO_1_DI_DLY_SEL +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL SF_CTRL_SF_IO_1_DO_DLY_SEL +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)) + +/* 0x3C : sf_if_io_dly_3 */ +#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET (0x3C) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL SF_CTRL_SF_IO_2_OE_DLY_SEL +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL SF_CTRL_SF_IO_2_DI_DLY_SEL +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL SF_CTRL_SF_IO_2_DO_DLY_SEL +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)) + +/* 0x40 : sf_if_io_dly_4 */ +#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET (0x40) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL SF_CTRL_SF_IO_3_OE_DLY_SEL +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL SF_CTRL_SF_IO_3_DI_DLY_SEL +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL SF_CTRL_SF_IO_3_DO_DLY_SEL +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)) + +/* 0x44 : sf_reserved */ +#define SF_CTRL_SF_RESERVED_OFFSET (0x44) +#define SF_CTRL_SF_RESERVED SF_CTRL_SF_RESERVED +#define SF_CTRL_SF_RESERVED_POS (0U) +#define SF_CTRL_SF_RESERVED_LEN (32U) +#define SF_CTRL_SF_RESERVED_MSK (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS) +#define SF_CTRL_SF_RESERVED_UMSK (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)) + +/* 0x48 : sf2_if_io_dly_0 */ +#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET (0x48) +#define SF_CTRL_SF2_CS_DLY_SEL SF_CTRL_SF2_CS_DLY_SEL +#define SF_CTRL_SF2_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS) +#define SF_CTRL_SF2_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL SF_CTRL_SF2_CLK_OUT_DLY_SEL +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL SF_CTRL_SF2_DQS_OE_DLY_SEL +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL SF_CTRL_SF2_DQS_DI_DLY_SEL +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL SF_CTRL_SF2_DQS_DO_DLY_SEL +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)) + +/* 0x4C : sf2_if_io_dly_1 */ +#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET (0x4C) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL SF_CTRL_SF2_IO_0_OE_DLY_SEL +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL SF_CTRL_SF2_IO_0_DI_DLY_SEL +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL SF_CTRL_SF2_IO_0_DO_DLY_SEL +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)) + +/* 0x50 : sf2_if_io_dly_2 */ +#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET (0x50) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL SF_CTRL_SF2_IO_1_OE_DLY_SEL +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL SF_CTRL_SF2_IO_1_DI_DLY_SEL +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL SF_CTRL_SF2_IO_1_DO_DLY_SEL +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)) + +/* 0x54 : sf2_if_io_dly_3 */ +#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET (0x54) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL SF_CTRL_SF2_IO_2_OE_DLY_SEL +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL SF_CTRL_SF2_IO_2_DI_DLY_SEL +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL SF_CTRL_SF2_IO_2_DO_DLY_SEL +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)) + +/* 0x58 : sf2_if_io_dly_4 */ +#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET (0x58) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL SF_CTRL_SF2_IO_3_OE_DLY_SEL +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL SF_CTRL_SF2_IO_3_DI_DLY_SEL +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL SF_CTRL_SF2_IO_3_DO_DLY_SEL +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)) + +/* 0x5C : sf3_if_io_dly_0 */ +#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET (0x5C) +#define SF_CTRL_SF3_CS_DLY_SEL SF_CTRL_SF3_CS_DLY_SEL +#define SF_CTRL_SF3_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS) +#define SF_CTRL_SF3_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL SF_CTRL_SF3_CLK_OUT_DLY_SEL +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL SF_CTRL_SF3_DQS_OE_DLY_SEL +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL SF_CTRL_SF3_DQS_DI_DLY_SEL +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL SF_CTRL_SF3_DQS_DO_DLY_SEL +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)) + +/* 0x60 : sf3_if_io_dly_1 */ +#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET (0x60) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL SF_CTRL_SF3_IO_0_OE_DLY_SEL +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL SF_CTRL_SF3_IO_0_DI_DLY_SEL +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL SF_CTRL_SF3_IO_0_DO_DLY_SEL +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)) + +/* 0x64 : sf3_if_io_dly_2 */ +#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET (0x64) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL SF_CTRL_SF3_IO_1_OE_DLY_SEL +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL SF_CTRL_SF3_IO_1_DI_DLY_SEL +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL SF_CTRL_SF3_IO_1_DO_DLY_SEL +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)) + +/* 0x68 : sf3_if_io_dly_3 */ +#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET (0x68) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL SF_CTRL_SF3_IO_2_OE_DLY_SEL +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL SF_CTRL_SF3_IO_2_DI_DLY_SEL +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL SF_CTRL_SF3_IO_2_DO_DLY_SEL +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)) + +/* 0x6C : sf3_if_io_dly_4 */ +#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET (0x6C) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL SF_CTRL_SF3_IO_3_OE_DLY_SEL +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL SF_CTRL_SF3_IO_3_DI_DLY_SEL +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL SF_CTRL_SF3_IO_3_DO_DLY_SEL +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)) + +/* 0x70 : sf_ctrl_2 */ +#define SF_CTRL_2_OFFSET (0x70) +#define SF_CTRL_SF_IF_PAD_SEL SF_CTRL_SF_IF_PAD_SEL +#define SF_CTRL_SF_IF_PAD_SEL_POS (0U) +#define SF_CTRL_SF_IF_PAD_SEL_LEN (2U) +#define SF_CTRL_SF_IF_PAD_SEL_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS) +#define SF_CTRL_SF_IF_PAD_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK SF_CTRL_SF_IF_PAD_SEL_LOCK +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS (3U) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN (1U) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)) +#define SF_CTRL_SF_IF_DTR_EN SF_CTRL_SF_IF_DTR_EN +#define SF_CTRL_SF_IF_DTR_EN_POS (4U) +#define SF_CTRL_SF_IF_DTR_EN_LEN (1U) +#define SF_CTRL_SF_IF_DTR_EN_MSK (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS) +#define SF_CTRL_SF_IF_DTR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)) +#define SF_CTRL_SF_IF_DQS_EN SF_CTRL_SF_IF_DQS_EN +#define SF_CTRL_SF_IF_DQS_EN_POS (5U) +#define SF_CTRL_SF_IF_DQS_EN_LEN (1U) +#define SF_CTRL_SF_IF_DQS_EN_MSK (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS) +#define SF_CTRL_SF_IF_DQS_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)) + +/* 0x74 : sf_ctrl_3 */ +#define SF_CTRL_3_OFFSET (0x74) +#define SF_CTRL_SF_CMDS_WRAP_LEN SF_CTRL_SF_CMDS_WRAP_LEN +#define SF_CTRL_SF_CMDS_WRAP_LEN_POS (0U) +#define SF_CTRL_SF_CMDS_WRAP_LEN_LEN (4U) +#define SF_CTRL_SF_CMDS_WRAP_LEN_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS) +#define SF_CTRL_SF_CMDS_WRAP_LEN_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS)) +#define SF_CTRL_SF_CMDS_EN SF_CTRL_SF_CMDS_EN +#define SF_CTRL_SF_CMDS_EN_POS (4U) +#define SF_CTRL_SF_CMDS_EN_LEN (1U) +#define SF_CTRL_SF_CMDS_EN_MSK (((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS) +#define SF_CTRL_SF_CMDS_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS)) +#define SF_CTRL_SF_CMDS_BT_DLY SF_CTRL_SF_CMDS_BT_DLY +#define SF_CTRL_SF_CMDS_BT_DLY_POS (5U) +#define SF_CTRL_SF_CMDS_BT_DLY_LEN (3U) +#define SF_CTRL_SF_CMDS_BT_DLY_MSK (((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS) +#define SF_CTRL_SF_CMDS_BT_DLY_UMSK (~(((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS)) +#define SF_CTRL_SF_CMDS_BT_EN SF_CTRL_SF_CMDS_BT_EN +#define SF_CTRL_SF_CMDS_BT_EN_POS (8U) +#define SF_CTRL_SF_CMDS_BT_EN_LEN (1U) +#define SF_CTRL_SF_CMDS_BT_EN_MSK (((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS) +#define SF_CTRL_SF_CMDS_BT_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS)) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI SF_CTRL_SF_CMDS_WRAP_Q_INI +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_POS (9U) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN (1U) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS)) +#define SF_CTRL_SF_CMDS_WRAP_MODE SF_CTRL_SF_CMDS_WRAP_MODE +#define SF_CTRL_SF_CMDS_WRAP_MODE_POS (10U) +#define SF_CTRL_SF_CMDS_WRAP_MODE_LEN (1U) +#define SF_CTRL_SF_CMDS_WRAP_MODE_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS) +#define SF_CTRL_SF_CMDS_WRAP_MODE_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS)) +#define SF_CTRL_SF_IF_1_ACK_LAT SF_CTRL_SF_IF_1_ACK_LAT +#define SF_CTRL_SF_IF_1_ACK_LAT_POS (29U) +#define SF_CTRL_SF_IF_1_ACK_LAT_LEN (3U) +#define SF_CTRL_SF_IF_1_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS) +#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)) + +/* 0x78 : sf_if_iahb_3 */ +#define SF_CTRL_SF_IF_IAHB_3_OFFSET (0x78) +#define SF_CTRL_SF_IF_2_DMY_BYTE SF_CTRL_SF_IF_2_DMY_BYTE +#define SF_CTRL_SF_IF_2_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_2_ADR_BYTE SF_CTRL_SF_IF_2_ADR_BYTE +#define SF_CTRL_SF_IF_2_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_2_CMD_BYTE SF_CTRL_SF_IF_2_CMD_BYTE +#define SF_CTRL_SF_IF_2_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_2_DAT_RW SF_CTRL_SF_IF_2_DAT_RW +#define SF_CTRL_SF_IF_2_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_2_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_2_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS) +#define SF_CTRL_SF_IF_2_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)) +#define SF_CTRL_SF_IF_2_DAT_EN SF_CTRL_SF_IF_2_DAT_EN +#define SF_CTRL_SF_IF_2_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_2_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS) +#define SF_CTRL_SF_IF_2_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)) +#define SF_CTRL_SF_IF_2_DMY_EN SF_CTRL_SF_IF_2_DMY_EN +#define SF_CTRL_SF_IF_2_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_2_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS) +#define SF_CTRL_SF_IF_2_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)) +#define SF_CTRL_SF_IF_2_ADR_EN SF_CTRL_SF_IF_2_ADR_EN +#define SF_CTRL_SF_IF_2_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_2_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS) +#define SF_CTRL_SF_IF_2_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)) +#define SF_CTRL_SF_IF_2_CMD_EN SF_CTRL_SF_IF_2_CMD_EN +#define SF_CTRL_SF_IF_2_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_2_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS) +#define SF_CTRL_SF_IF_2_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)) +#define SF_CTRL_SF_IF_2_SPI_MODE SF_CTRL_SF_IF_2_SPI_MODE +#define SF_CTRL_SF_IF_2_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_2_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_2_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS) +#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN SF_CTRL_SF_IF_2_QPI_MODE_EN +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)) + +/* 0x7C : sf_if_iahb_4 */ +#define SF_CTRL_SF_IF_IAHB_4_OFFSET (0x7C) +#define SF_CTRL_SF_IF_2_CMD_BUF_0 SF_CTRL_SF_IF_2_CMD_BUF_0 +#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)) + +/* 0x80 : sf_if_iahb_5 */ +#define SF_CTRL_SF_IF_IAHB_5_OFFSET (0x80) +#define SF_CTRL_SF_IF_2_CMD_BUF_1 SF_CTRL_SF_IF_2_CMD_BUF_1 +#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)) + +/* 0x84 : sf_if_iahb_6 */ +#define SF_CTRL_SF_IF_IAHB_6_OFFSET (0x84) +#define SF_CTRL_SF_IF_3_CMD_BYTE SF_CTRL_SF_IF_3_CMD_BYTE +#define SF_CTRL_SF_IF_3_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_3_SPI_MODE SF_CTRL_SF_IF_3_SPI_MODE +#define SF_CTRL_SF_IF_3_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_3_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_3_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS) +#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN SF_CTRL_SF_IF_3_QPI_MODE_EN +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)) + +/* 0x88 : sf_if_iahb_7 */ +#define SF_CTRL_SF_IF_IAHB_7_OFFSET (0x88) +#define SF_CTRL_SF_IF_3_CMD_BUF_0 SF_CTRL_SF_IF_3_CMD_BUF_0 +#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)) + +/* 0x100 : sf_ctrl_prot_en_rd */ +#define SF_CTRL_PROT_EN_RD_OFFSET (0x100) +#define SF_CTRL_PROT_EN_RD SF_CTRL_PROT_EN_RD +#define SF_CTRL_PROT_EN_RD_POS (0U) +#define SF_CTRL_PROT_EN_RD_LEN (1U) +#define SF_CTRL_PROT_EN_RD_MSK (((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS) +#define SF_CTRL_PROT_EN_RD_UMSK (~(((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS)) +#define SF_CTRL_ID0_EN_RD SF_CTRL_ID0_EN_RD +#define SF_CTRL_ID0_EN_RD_POS (1U) +#define SF_CTRL_ID0_EN_RD_LEN (1U) +#define SF_CTRL_ID0_EN_RD_MSK (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS) +#define SF_CTRL_ID0_EN_RD_UMSK (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)) +#define SF_CTRL_ID1_EN_RD SF_CTRL_ID1_EN_RD +#define SF_CTRL_ID1_EN_RD_POS (2U) +#define SF_CTRL_ID1_EN_RD_LEN (1U) +#define SF_CTRL_ID1_EN_RD_MSK (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS) +#define SF_CTRL_ID1_EN_RD_UMSK (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK SF_CTRL_SF_IF_0_TRIG_WR_LOCK +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS (30U) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN (1U) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)) +#define SF_CTRL_SF_DBG_DIS SF_CTRL_SF_DBG_DIS +#define SF_CTRL_SF_DBG_DIS_POS (31U) +#define SF_CTRL_SF_DBG_DIS_LEN (1U) +#define SF_CTRL_SF_DBG_DIS_MSK (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS) +#define SF_CTRL_SF_DBG_DIS_UMSK (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)) + +/* 0x104 : sf_ctrl_prot_en */ +#define SF_CTRL_PROT_EN_OFFSET (0x104) +#define SF_CTRL_PROT_EN SF_CTRL_PROT_EN +#define SF_CTRL_PROT_EN_POS (0U) +#define SF_CTRL_PROT_EN_LEN (1U) +#define SF_CTRL_PROT_EN_MSK (((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS) +#define SF_CTRL_PROT_EN_UMSK (~(((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS)) +#define SF_CTRL_ID0_EN SF_CTRL_ID0_EN +#define SF_CTRL_ID0_EN_POS (1U) +#define SF_CTRL_ID0_EN_LEN (1U) +#define SF_CTRL_ID0_EN_MSK (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS) +#define SF_CTRL_ID0_EN_UMSK (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)) +#define SF_CTRL_ID1_EN SF_CTRL_ID1_EN +#define SF_CTRL_ID1_EN_POS (2U) +#define SF_CTRL_ID1_EN_LEN (1U) +#define SF_CTRL_ID1_EN_MSK (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS) +#define SF_CTRL_ID1_EN_UMSK (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)) + +/* 0x200 : sf_aes_key_r0_0 */ +#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200) +#define SF_CTRL_SF_AES_KEY_R0_0 SF_CTRL_SF_AES_KEY_R0_0 +#define SF_CTRL_SF_AES_KEY_R0_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS) +#define SF_CTRL_SF_AES_KEY_R0_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)) + +/* 0x204 : sf_aes_key_r0_1 */ +#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204) +#define SF_CTRL_SF_AES_KEY_R0_1 SF_CTRL_SF_AES_KEY_R0_1 +#define SF_CTRL_SF_AES_KEY_R0_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS) +#define SF_CTRL_SF_AES_KEY_R0_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)) + +/* 0x208 : sf_aes_key_r0_2 */ +#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208) +#define SF_CTRL_SF_AES_KEY_R0_2 SF_CTRL_SF_AES_KEY_R0_2 +#define SF_CTRL_SF_AES_KEY_R0_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS) +#define SF_CTRL_SF_AES_KEY_R0_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)) + +/* 0x20C : sf_aes_key_r0_3 */ +#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C) +#define SF_CTRL_SF_AES_KEY_R0_3 SF_CTRL_SF_AES_KEY_R0_3 +#define SF_CTRL_SF_AES_KEY_R0_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS) +#define SF_CTRL_SF_AES_KEY_R0_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)) + +/* 0x210 : sf_aes_key_r0_4 */ +#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210) +#define SF_CTRL_SF_AES_KEY_R0_4 SF_CTRL_SF_AES_KEY_R0_4 +#define SF_CTRL_SF_AES_KEY_R0_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS) +#define SF_CTRL_SF_AES_KEY_R0_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)) + +/* 0x214 : sf_aes_key_r0_5 */ +#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214) +#define SF_CTRL_SF_AES_KEY_R0_5 SF_CTRL_SF_AES_KEY_R0_5 +#define SF_CTRL_SF_AES_KEY_R0_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS) +#define SF_CTRL_SF_AES_KEY_R0_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)) + +/* 0x218 : sf_aes_key_r0_6 */ +#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218) +#define SF_CTRL_SF_AES_KEY_R0_6 SF_CTRL_SF_AES_KEY_R0_6 +#define SF_CTRL_SF_AES_KEY_R0_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS) +#define SF_CTRL_SF_AES_KEY_R0_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)) + +/* 0x21C : sf_aes_key_r0_7 */ +#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C) +#define SF_CTRL_SF_AES_KEY_R0_7 SF_CTRL_SF_AES_KEY_R0_7 +#define SF_CTRL_SF_AES_KEY_R0_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS) +#define SF_CTRL_SF_AES_KEY_R0_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)) + +/* 0x220 : sf_aes_iv_r0_w0 */ +#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220) +#define SF_CTRL_SF_AES_IV_R0_W0 SF_CTRL_SF_AES_IV_R0_W0 +#define SF_CTRL_SF_AES_IV_R0_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS) +#define SF_CTRL_SF_AES_IV_R0_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)) + +/* 0x224 : sf_aes_iv_r0_w1 */ +#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224) +#define SF_CTRL_SF_AES_IV_R0_W1 SF_CTRL_SF_AES_IV_R0_W1 +#define SF_CTRL_SF_AES_IV_R0_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS) +#define SF_CTRL_SF_AES_IV_R0_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)) + +/* 0x228 : sf_aes_iv_r0_w2 */ +#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228) +#define SF_CTRL_SF_AES_IV_R0_W2 SF_CTRL_SF_AES_IV_R0_W2 +#define SF_CTRL_SF_AES_IV_R0_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS) +#define SF_CTRL_SF_AES_IV_R0_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)) + +/* 0x22C : sf_aes_iv_r0_w3 */ +#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C) +#define SF_CTRL_SF_AES_IV_R0_W3 SF_CTRL_SF_AES_IV_R0_W3 +#define SF_CTRL_SF_AES_IV_R0_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS) +#define SF_CTRL_SF_AES_IV_R0_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)) + +/* 0x230 : sf_aes_cfg_r0 */ +#define SF_CTRL_SF_AES_CFG_R0_OFFSET (0x230) +#define SF_CTRL_SF_AES_REGION_R0_END SF_CTRL_SF_AES_REGION_R0_END +#define SF_CTRL_SF_AES_REGION_R0_END_POS (0U) +#define SF_CTRL_SF_AES_REGION_R0_END_LEN (14U) +#define SF_CTRL_SF_AES_REGION_R0_END_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS) +#define SF_CTRL_SF_AES_REGION_R0_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)) +#define SF_CTRL_SF_AES_REGION_R0_START SF_CTRL_SF_AES_REGION_R0_START +#define SF_CTRL_SF_AES_REGION_R0_START_POS (14U) +#define SF_CTRL_SF_AES_REGION_R0_START_LEN (14U) +#define SF_CTRL_SF_AES_REGION_R0_START_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS) +#define SF_CTRL_SF_AES_REGION_R0_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_REGION_R0_EN SF_CTRL_SF_AES_REGION_R0_EN +#define SF_CTRL_SF_AES_REGION_R0_EN_POS (30U) +#define SF_CTRL_SF_AES_REGION_R0_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS) +#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)) +#define SF_CTRL_SF_AES_REGION_R0_LOCK SF_CTRL_SF_AES_REGION_R0_LOCK +#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS (31U) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)) + +/* 0x300 : sf_aes_key_r1_0 */ +#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x300) +#define SF_CTRL_SF_AES_KEY_R1_0 SF_CTRL_SF_AES_KEY_R1_0 +#define SF_CTRL_SF_AES_KEY_R1_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS) +#define SF_CTRL_SF_AES_KEY_R1_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)) + +/* 0x304 : sf_aes_key_r1_1 */ +#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x304) +#define SF_CTRL_SF_AES_KEY_R1_1 SF_CTRL_SF_AES_KEY_R1_1 +#define SF_CTRL_SF_AES_KEY_R1_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS) +#define SF_CTRL_SF_AES_KEY_R1_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)) + +/* 0x308 : sf_aes_key_r1_2 */ +#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x308) +#define SF_CTRL_SF_AES_KEY_R1_2 SF_CTRL_SF_AES_KEY_R1_2 +#define SF_CTRL_SF_AES_KEY_R1_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS) +#define SF_CTRL_SF_AES_KEY_R1_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)) + +/* 0x30C : sf_aes_key_r1_3 */ +#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x30C) +#define SF_CTRL_SF_AES_KEY_R1_3 SF_CTRL_SF_AES_KEY_R1_3 +#define SF_CTRL_SF_AES_KEY_R1_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS) +#define SF_CTRL_SF_AES_KEY_R1_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)) + +/* 0x310 : sf_aes_key_r1_4 */ +#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x310) +#define SF_CTRL_SF_AES_KEY_R1_4 SF_CTRL_SF_AES_KEY_R1_4 +#define SF_CTRL_SF_AES_KEY_R1_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS) +#define SF_CTRL_SF_AES_KEY_R1_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)) + +/* 0x314 : sf_aes_key_r1_5 */ +#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x314) +#define SF_CTRL_SF_AES_KEY_R1_5 SF_CTRL_SF_AES_KEY_R1_5 +#define SF_CTRL_SF_AES_KEY_R1_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS) +#define SF_CTRL_SF_AES_KEY_R1_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)) + +/* 0x318 : sf_aes_key_r1_6 */ +#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x318) +#define SF_CTRL_SF_AES_KEY_R1_6 SF_CTRL_SF_AES_KEY_R1_6 +#define SF_CTRL_SF_AES_KEY_R1_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS) +#define SF_CTRL_SF_AES_KEY_R1_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)) + +/* 0x31C : sf_aes_key_r1_7 */ +#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x31C) +#define SF_CTRL_SF_AES_KEY_R1_7 SF_CTRL_SF_AES_KEY_R1_7 +#define SF_CTRL_SF_AES_KEY_R1_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS) +#define SF_CTRL_SF_AES_KEY_R1_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)) + +/* 0x320 : sf_aes_iv_r1_w0 */ +#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x320) +#define SF_CTRL_SF_AES_IV_R1_W0 SF_CTRL_SF_AES_IV_R1_W0 +#define SF_CTRL_SF_AES_IV_R1_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS) +#define SF_CTRL_SF_AES_IV_R1_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)) + +/* 0x324 : sf_aes_iv_r1_w1 */ +#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x324) +#define SF_CTRL_SF_AES_IV_R1_W1 SF_CTRL_SF_AES_IV_R1_W1 +#define SF_CTRL_SF_AES_IV_R1_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS) +#define SF_CTRL_SF_AES_IV_R1_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)) + +/* 0x328 : sf_aes_iv_r1_w2 */ +#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x328) +#define SF_CTRL_SF_AES_IV_R1_W2 SF_CTRL_SF_AES_IV_R1_W2 +#define SF_CTRL_SF_AES_IV_R1_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS) +#define SF_CTRL_SF_AES_IV_R1_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)) + +/* 0x32C : sf_aes_iv_r1_w3 */ +#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x32C) +#define SF_CTRL_SF_AES_IV_R1_W3 SF_CTRL_SF_AES_IV_R1_W3 +#define SF_CTRL_SF_AES_IV_R1_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS) +#define SF_CTRL_SF_AES_IV_R1_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)) + +/* 0x330 : sf_aes_r1 */ +#define SF_CTRL_SF_AES_R1_OFFSET (0x330) +#define SF_CTRL_SF_AES_R1_END SF_CTRL_SF_AES_R1_END +#define SF_CTRL_SF_AES_R1_END_POS (0U) +#define SF_CTRL_SF_AES_R1_END_LEN (14U) +#define SF_CTRL_SF_AES_R1_END_MSK (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS) +#define SF_CTRL_SF_AES_R1_END_UMSK (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)) +#define SF_CTRL_SF_AES_R1_START SF_CTRL_SF_AES_R1_START +#define SF_CTRL_SF_AES_R1_START_POS (14U) +#define SF_CTRL_SF_AES_R1_START_LEN (14U) +#define SF_CTRL_SF_AES_R1_START_MSK (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS) +#define SF_CTRL_SF_AES_R1_START_UMSK (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN SF_CTRL_SF_AES_R1_HW_KEY_EN +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_R1_EN SF_CTRL_SF_AES_R1_EN +#define SF_CTRL_SF_AES_R1_EN_POS (30U) +#define SF_CTRL_SF_AES_R1_EN_LEN (1U) +#define SF_CTRL_SF_AES_R1_EN_MSK (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS) +#define SF_CTRL_SF_AES_R1_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)) +#define SF_CTRL_SF_AES_R1_LOCK SF_CTRL_SF_AES_R1_LOCK +#define SF_CTRL_SF_AES_R1_LOCK_POS (31U) +#define SF_CTRL_SF_AES_R1_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_R1_LOCK_MSK (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS) +#define SF_CTRL_SF_AES_R1_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)) + +/* 0x400 : sf_aes_key_r2_0 */ +#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x400) +#define SF_CTRL_SF_AES_KEY_R2_0 SF_CTRL_SF_AES_KEY_R2_0 +#define SF_CTRL_SF_AES_KEY_R2_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS) +#define SF_CTRL_SF_AES_KEY_R2_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)) + +/* 0x404 : sf_aes_key_r2_1 */ +#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x404) +#define SF_CTRL_SF_AES_KEY_R2_1 SF_CTRL_SF_AES_KEY_R2_1 +#define SF_CTRL_SF_AES_KEY_R2_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS) +#define SF_CTRL_SF_AES_KEY_R2_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)) + +/* 0x408 : sf_aes_key_r2_2 */ +#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x408) +#define SF_CTRL_SF_AES_KEY_R2_2 SF_CTRL_SF_AES_KEY_R2_2 +#define SF_CTRL_SF_AES_KEY_R2_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS) +#define SF_CTRL_SF_AES_KEY_R2_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)) + +/* 0x40C : sf_aes_key_r2_3 */ +#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x40C) +#define SF_CTRL_SF_AES_KEY_R2_3 SF_CTRL_SF_AES_KEY_R2_3 +#define SF_CTRL_SF_AES_KEY_R2_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS) +#define SF_CTRL_SF_AES_KEY_R2_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)) + +/* 0x410 : sf_aes_key_r2_4 */ +#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x410) +#define SF_CTRL_SF_AES_KEY_R2_4 SF_CTRL_SF_AES_KEY_R2_4 +#define SF_CTRL_SF_AES_KEY_R2_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS) +#define SF_CTRL_SF_AES_KEY_R2_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)) + +/* 0x414 : sf_aes_key_r2_5 */ +#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x414) +#define SF_CTRL_SF_AES_KEY_R2_5 SF_CTRL_SF_AES_KEY_R2_5 +#define SF_CTRL_SF_AES_KEY_R2_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS) +#define SF_CTRL_SF_AES_KEY_R2_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)) + +/* 0x418 : sf_aes_key_r2_6 */ +#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x418) +#define SF_CTRL_SF_AES_KEY_R2_6 SF_CTRL_SF_AES_KEY_R2_6 +#define SF_CTRL_SF_AES_KEY_R2_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS) +#define SF_CTRL_SF_AES_KEY_R2_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)) + +/* 0x41C : sf_aes_key_r2_7 */ +#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x41C) +#define SF_CTRL_SF_AES_KEY_R2_7 SF_CTRL_SF_AES_KEY_R2_7 +#define SF_CTRL_SF_AES_KEY_R2_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS) +#define SF_CTRL_SF_AES_KEY_R2_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)) + +/* 0x420 : sf_aes_iv_r2_w0 */ +#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x420) +#define SF_CTRL_SF_AES_IV_R2_W0 SF_CTRL_SF_AES_IV_R2_W0 +#define SF_CTRL_SF_AES_IV_R2_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS) +#define SF_CTRL_SF_AES_IV_R2_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)) + +/* 0x424 : sf_aes_iv_r2_w1 */ +#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x424) +#define SF_CTRL_SF_AES_IV_R2_W1 SF_CTRL_SF_AES_IV_R2_W1 +#define SF_CTRL_SF_AES_IV_R2_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS) +#define SF_CTRL_SF_AES_IV_R2_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)) + +/* 0x428 : sf_aes_iv_r2_w2 */ +#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x428) +#define SF_CTRL_SF_AES_IV_R2_W2 SF_CTRL_SF_AES_IV_R2_W2 +#define SF_CTRL_SF_AES_IV_R2_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS) +#define SF_CTRL_SF_AES_IV_R2_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)) + +/* 0x42C : sf_aes_iv_r2_w3 */ +#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x42C) +#define SF_CTRL_SF_AES_IV_R2_W3 SF_CTRL_SF_AES_IV_R2_W3 +#define SF_CTRL_SF_AES_IV_R2_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS) +#define SF_CTRL_SF_AES_IV_R2_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)) + +/* 0x430 : sf_aes_r2 */ +#define SF_CTRL_SF_AES_R2_OFFSET (0x430) +#define SF_CTRL_SF_AES_R2_END SF_CTRL_SF_AES_R2_END +#define SF_CTRL_SF_AES_R2_END_POS (0U) +#define SF_CTRL_SF_AES_R2_END_LEN (14U) +#define SF_CTRL_SF_AES_R2_END_MSK (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS) +#define SF_CTRL_SF_AES_R2_END_UMSK (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)) +#define SF_CTRL_SF_AES_R2_START SF_CTRL_SF_AES_R2_START +#define SF_CTRL_SF_AES_R2_START_POS (14U) +#define SF_CTRL_SF_AES_R2_START_LEN (14U) +#define SF_CTRL_SF_AES_R2_START_MSK (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS) +#define SF_CTRL_SF_AES_R2_START_UMSK (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN SF_CTRL_SF_AES_R2_HW_KEY_EN +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_R2_EN SF_CTRL_SF_AES_R2_EN +#define SF_CTRL_SF_AES_R2_EN_POS (30U) +#define SF_CTRL_SF_AES_R2_EN_LEN (1U) +#define SF_CTRL_SF_AES_R2_EN_MSK (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS) +#define SF_CTRL_SF_AES_R2_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)) +#define SF_CTRL_SF_AES_R2_LOCK SF_CTRL_SF_AES_R2_LOCK +#define SF_CTRL_SF_AES_R2_LOCK_POS (31U) +#define SF_CTRL_SF_AES_R2_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_R2_LOCK_MSK (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS) +#define SF_CTRL_SF_AES_R2_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)) + +/* 0x434 : sf_id0_offset */ +#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0x434) +#define SF_CTRL_SF_ID0_OFFSET SF_CTRL_SF_ID0_OFFSET +#define SF_CTRL_SF_ID0_OFFSET_POS (0U) +#define SF_CTRL_SF_ID0_OFFSET_LEN (24U) +#define SF_CTRL_SF_ID0_OFFSET_MSK (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS) +#define SF_CTRL_SF_ID0_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)) + +/* 0x438 : sf_id1_offset */ +#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0x438) +#define SF_CTRL_SF_ID1_OFFSET SF_CTRL_SF_ID1_OFFSET +#define SF_CTRL_SF_ID1_OFFSET_POS (0U) +#define SF_CTRL_SF_ID1_OFFSET_LEN (24U) +#define SF_CTRL_SF_ID1_OFFSET_MSK (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS) +#define SF_CTRL_SF_ID1_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)) + +struct sf_ctrl_reg { + /* 0x0 : sf_ctrl_0 */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t sf_clk_sf_rx_inv_sel : 1; /* [ 2], r/w, 0x1 */ + uint32_t sf_clk_out_gate_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t sf_clk_out_inv_sel : 1; /* [ 4], r/w, 0x1 */ + uint32_t sf_clk_sahb_sram_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t sf_if_read_dly_n : 3; /* [10: 8], r/w, 0x0 */ + uint32_t sf_if_read_dly_en : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t sf_if_int : 1; /* [ 16], r, 0x0 */ + uint32_t sf_if_int_clr : 1; /* [ 17], r/w, 0x1 */ + uint32_t sf_if_int_set : 1; /* [ 18], r/w, 0x0 */ + uint32_t sf_aes_dly_mode : 1; /* [ 19], r/w, 0x0 */ + uint32_t sf_aes_dout_endian : 1; /* [ 20], r/w, 0x1 */ + uint32_t sf_aes_ctr_plus_en : 1; /* [ 21], r/w, 0x0 */ + uint32_t sf_aes_key_endian : 1; /* [ 22], r/w, 0x1 */ + uint32_t sf_aes_iv_endian : 1; /* [ 23], r/w, 0x1 */ + uint32_t sf_id : 8; /* [31:24], r/w, 0x1a */ + } BF; + uint32_t WORD; + } sf_ctrl_0; + + /* 0x4 : sf_ctrl_1 */ + union { + struct + { + uint32_t sf_if_sr_pat_mask : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t sf_if_sr_pat : 8; /* [15: 8], r/w, 0x0 */ + uint32_t sf_if_sr_int : 1; /* [ 16], r, 0x0 */ + uint32_t sf_if_sr_int_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t sf_if_sr_int_set : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t sf_if_0_ack_lat : 3; /* [22:20], r/w, 0x6 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t sf_if_reg_hold : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_reg_wp : 1; /* [ 25], r/w, 0x1 */ + uint32_t sf_ahb2sif_stopped : 1; /* [ 26], r, 0x0 */ + uint32_t sf_ahb2sif_stop : 1; /* [ 27], r/w, 0x0 */ + uint32_t sf_if_fn_sel : 1; /* [ 28], r/w, 0x1 */ + uint32_t sf_if_en : 1; /* [ 29], r/w, 0x1 */ + uint32_t sf_ahb2sif_en : 1; /* [ 30], r/w, 0x1 */ + uint32_t sf_ahb2sram_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_ctrl_1; + + /* 0x8 : sf_if_sahb_0 */ + union { + struct sf_if_sahb { + uint32_t sf_if_busy : 1; /* [ 0], r, 0x0 */ + uint32_t sf_if_0_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t sf_if_0_dat_byte : 10; /* [11: 2], r/w, 0x0 */ + uint32_t sf_if_0_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_0_adr_byte : 3; /* [19:17], r/w, 0x0 */ + uint32_t sf_if_0_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_0_dat_rw : 1; /* [ 23], r/w, 0x0 */ + uint32_t sf_if_0_dat_en : 1; /* [ 24], r/w, 0x0 */ + uint32_t sf_if_0_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_0_adr_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t sf_if_0_cmd_en : 1; /* [ 27], r/w, 0x0 */ + uint32_t sf_if_0_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_0_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_0; + + /* 0xC : sf_if_sahb_1 */ + union { + struct + { + uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_1; + + /* 0x10 : sf_if_sahb_2 */ + union { + struct + { + uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_2; + + /* 0x14 : sf_if_iahb_0 */ + union { + struct sf_if_iahb { + uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ + uint32_t sf_if_1_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_1_adr_byte : 3; /* [19:17], r/w, 0x2 */ + uint32_t sf_if_1_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_1_dat_rw : 1; /* [ 23], r/w, 0x0 */ + uint32_t sf_if_1_dat_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_1_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_1_adr_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t sf_if_1_cmd_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t sf_if_1_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_1_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_0; + + /* 0x18 : sf_if_iahb_1 */ + union { + struct + { + uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0], r/w, 0x3000000 */ + } BF; + uint32_t WORD; + } sf_if_iahb_1; + + /* 0x1C : sf_if_iahb_2 */ + union { + struct + { + uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_2; + + /* 0x20 : sf_if_status_0 */ + union { + struct + { + uint32_t sf_if_status_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_status_0; + + /* 0x24 : sf_if_status_1 */ + union { + struct + { + uint32_t sf_if_status_1 : 32; /* [31: 0], r, 0x20000000 */ + } BF; + uint32_t WORD; + } sf_if_status_1; + + /* 0x28 : sf_aes */ + union { + struct + { + uint32_t sf_aes_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t sf_aes_mode : 2; /* [ 2: 1], r/w, 0x0 */ + uint32_t sf_aes_pref_trig : 1; /* [ 3], r/w, 0x0 */ + uint32_t sf_aes_pref_busy : 1; /* [ 4], r, 0x0 */ + uint32_t sf_aes_status : 27; /* [31: 5], r, 0x2 */ + } BF; + uint32_t WORD; + } sf_aes; + + /* 0x2C : sf_ahb2sif_status */ + union { + struct + { + uint32_t sf_ahb2sif_status : 32; /* [31: 0], r, 0x10000003 */ + } BF; + uint32_t WORD; + } sf_ahb2sif_status; + + /* 0x30 : sf_if_io_dly_0 */ + union { + struct + { + uint32_t sf_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_0; + + /* 0x34 : sf_if_io_dly_1 */ + union { + struct + { + uint32_t sf_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_1; + + /* 0x38 : sf_if_io_dly_2 */ + union { + struct + { + uint32_t sf_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_2; + + /* 0x3C : sf_if_io_dly_3 */ + union { + struct + { + uint32_t sf_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_3; + + /* 0x40 : sf_if_io_dly_4 */ + union { + struct + { + uint32_t sf_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_4; + + /* 0x44 : sf_reserved */ + union { + struct + { + uint32_t sf_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } sf_reserved; + + /* 0x48 : sf2_if_io_dly_0 */ + union { + struct + { + uint32_t sf2_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf2_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf2_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf2_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_0; + + /* 0x4C : sf2_if_io_dly_1 */ + union { + struct + { + uint32_t sf2_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_1; + + /* 0x50 : sf2_if_io_dly_2 */ + union { + struct + { + uint32_t sf2_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_2; + + /* 0x54 : sf2_if_io_dly_3 */ + union { + struct + { + uint32_t sf2_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_3; + + /* 0x58 : sf2_if_io_dly_4 */ + union { + struct + { + uint32_t sf2_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_4; + + /* 0x5C : sf3_if_io_dly_0 */ + union { + struct + { + uint32_t sf3_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf3_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf3_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf3_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_0; + + /* 0x60 : sf3_if_io_dly_1 */ + union { + struct + { + uint32_t sf3_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_1; + + /* 0x64 : sf3_if_io_dly_2 */ + union { + struct + { + uint32_t sf3_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_2; + + /* 0x68 : sf3_if_io_dly_3 */ + union { + struct + { + uint32_t sf3_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_3; + + /* 0x6C : sf3_if_io_dly_4 */ + union { + struct + { + uint32_t sf3_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_4; + + /* 0x70 : sf_ctrl_2 */ + union { + struct + { + uint32_t sf_if_pad_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */ + uint32_t sf_if_pad_sel_lock : 1; /* [ 3], r/w, 0x0 */ + uint32_t sf_if_dtr_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t sf_if_dqs_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_2; + + /* 0x74 : sf_ctrl_3 */ + union { + struct + { + uint32_t sf_cmds_wrap_len : 4; /* [ 3: 0], r/w, 0x6 */ + uint32_t sf_cmds_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t sf_cmds_bt_dly : 3; /* [ 7: 5], r/w, 0x2 */ + uint32_t sf_cmds_bt_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t sf_cmds_wrap_q_ini : 1; /* [ 9], r/w, 0x0 */ + uint32_t sf_cmds_wrap_mode : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_28 : 18; /* [28:11], rsvd, 0x0 */ + uint32_t sf_if_1_ack_lat : 3; /* [31:29], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_ctrl_3; + + /* 0x78 : sf_if_iahb_3 */ + union { + struct + { + uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ + uint32_t sf_if_2_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_2_adr_byte : 3; /* [19:17], r/w, 0x2 */ + uint32_t sf_if_2_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_2_dat_rw : 1; /* [ 23], r/w, 0x1 */ + uint32_t sf_if_2_dat_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_2_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_2_adr_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t sf_if_2_cmd_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t sf_if_2_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_2_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_if_iahb_3; + + /* 0x7C : sf_if_iahb_4 */ + union { + struct + { + uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0], r/w, 0x38000000 */ + } BF; + uint32_t WORD; + } sf_if_iahb_4; + + /* 0x80 : sf_if_iahb_5 */ + union { + struct + { + uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_5; + + /* 0x84 : sf_if_iahb_6 */ + union { + struct + { + uint32_t reserved_0_19 : 20; /* [19: 0], rsvd, 0x0 */ + uint32_t sf_if_3_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_27 : 5; /* [27:23], rsvd, 0x0 */ + uint32_t sf_if_3_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_3_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_if_iahb_6; + + /* 0x88 : sf_if_iahb_7 */ + union { + struct + { + uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0], r/w, 0xc0000000L */ + } BF; + uint32_t WORD; + } sf_if_iahb_7; + + /* 0x8c reserved */ + uint8_t RESERVED0x8c[116]; + + /* 0x100 : sf_ctrl_prot_en_rd */ + union { + struct + { + uint32_t sf_ctrl_prot_en_rd : 1; /* [ 0], r, 0x1 */ + uint32_t sf_ctrl_id0_en_rd : 1; /* [ 1], r, 0x1 */ + uint32_t sf_ctrl_id1_en_rd : 1; /* [ 2], r, 0x1 */ + uint32_t reserved_3_29 : 27; /* [29: 3], rsvd, 0x0 */ + uint32_t sf_if_0_trig_wr_lock : 1; /* [ 30], r, 0x0 */ + uint32_t sf_dbg_dis : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_prot_en_rd; + + /* 0x104 : sf_ctrl_prot_en */ + union { + struct + { + uint32_t sf_ctrl_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t sf_ctrl_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t sf_ctrl_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_prot_en; + + /* 0x108 reserved */ + uint8_t RESERVED0x108[248]; + + /* 0x200 : sf_aes_key_r0_0 */ + union { + struct + { + uint32_t sf_aes_key_r0_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_0; + + /* 0x204 : sf_aes_key_r0_1 */ + union { + struct + { + uint32_t sf_aes_key_r0_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_1; + + /* 0x208 : sf_aes_key_r0_2 */ + union { + struct + { + uint32_t sf_aes_key_r0_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_2; + + /* 0x20C : sf_aes_key_r0_3 */ + union { + struct + { + uint32_t sf_aes_key_r0_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_3; + + /* 0x210 : sf_aes_key_r0_4 */ + union { + struct + { + uint32_t sf_aes_key_r0_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_4; + + /* 0x214 : sf_aes_key_r0_5 */ + union { + struct + { + uint32_t sf_aes_key_r0_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_5; + + /* 0x218 : sf_aes_key_r0_6 */ + union { + struct + { + uint32_t sf_aes_key_r0_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_6; + + /* 0x21C : sf_aes_key_r0_7 */ + union { + struct + { + uint32_t sf_aes_key_r0_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_7; + + /* 0x220 : sf_aes_iv_r0_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w0; + + /* 0x224 : sf_aes_iv_r0_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w1; + + /* 0x228 : sf_aes_iv_r0_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w2; + + /* 0x22C : sf_aes_iv_r0_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w3; + + /* 0x230 : sf_aes_cfg_r0 */ + union { + struct + { + uint32_t sf_aes_region_r0_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_region_r0_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_region_r0_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_region_r0_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_region_r0_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_cfg_r0; + + /* 0x234 reserved */ + uint8_t RESERVED0x234[204]; + + /* 0x300 : sf_aes_key_r1_0 */ + union { + struct + { + uint32_t sf_aes_key_r1_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_0; + + /* 0x304 : sf_aes_key_r1_1 */ + union { + struct + { + uint32_t sf_aes_key_r1_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_1; + + /* 0x308 : sf_aes_key_r1_2 */ + union { + struct + { + uint32_t sf_aes_key_r1_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_2; + + /* 0x30C : sf_aes_key_r1_3 */ + union { + struct + { + uint32_t sf_aes_key_r1_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_3; + + /* 0x310 : sf_aes_key_r1_4 */ + union { + struct + { + uint32_t sf_aes_key_r1_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_4; + + /* 0x314 : sf_aes_key_r1_5 */ + union { + struct + { + uint32_t sf_aes_key_r1_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_5; + + /* 0x318 : sf_aes_key_r1_6 */ + union { + struct + { + uint32_t sf_aes_key_r1_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_6; + + /* 0x31C : sf_aes_key_r1_7 */ + union { + struct + { + uint32_t sf_aes_key_r1_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_7; + + /* 0x320 : sf_aes_iv_r1_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w0; + + /* 0x324 : sf_aes_iv_r1_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w1; + + /* 0x328 : sf_aes_iv_r1_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w2; + + /* 0x32C : sf_aes_iv_r1_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w3; + + /* 0x330 : sf_aes_r1 */ + union { + struct + { + uint32_t sf_aes_r1_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_r1_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_r1_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_r1_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_r1_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_r1; + + /* 0x334 reserved */ + uint8_t RESERVED0x334[204]; + + /* 0x400 : sf_aes_key_r2_0 */ + union { + struct + { + uint32_t sf_aes_key_r2_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_0; + + /* 0x404 : sf_aes_key_r2_1 */ + union { + struct + { + uint32_t sf_aes_key_r2_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_1; + + /* 0x408 : sf_aes_key_r2_2 */ + union { + struct + { + uint32_t sf_aes_key_r2_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_2; + + /* 0x40C : sf_aes_key_r2_3 */ + union { + struct + { + uint32_t sf_aes_key_r2_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_3; + + /* 0x410 : sf_aes_key_r2_4 */ + union { + struct + { + uint32_t sf_aes_key_r2_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_4; + + /* 0x414 : sf_aes_key_r2_5 */ + union { + struct + { + uint32_t sf_aes_key_r2_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_5; + + /* 0x418 : sf_aes_key_r2_6 */ + union { + struct + { + uint32_t sf_aes_key_r2_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_6; + + /* 0x41C : sf_aes_key_r2_7 */ + union { + struct + { + uint32_t sf_aes_key_r2_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_7; + + /* 0x420 : sf_aes_iv_r2_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w0; + + /* 0x424 : sf_aes_iv_r2_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w1; + + /* 0x428 : sf_aes_iv_r2_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w2; + + /* 0x42C : sf_aes_iv_r2_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w3; + + /* 0x430 : sf_aes_r2 */ + union { + struct + { + uint32_t sf_aes_r2_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_r2_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_r2_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_r2_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_r2_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_r2; + + /* 0x434 : sf_id0_offset */ + union { + struct + { + uint32_t sf_id0_offset : 24; /* [23: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_id0_offset; + + /* 0x438 : sf_id1_offset */ + union { + struct + { + uint32_t sf_id1_offset : 24; /* [23: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_id1_offset; +}; + +typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t; + +/* 0x0 : sf_aes_key_0 */ +#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0) +#define SF_CTRL_SF_AES_KEY_0 SF_CTRL_SF_AES_KEY_0 +#define SF_CTRL_SF_AES_KEY_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_0_MSK (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS) +#define SF_CTRL_SF_AES_KEY_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)) + +/* 0x4 : sf_aes_key_1 */ +#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4) +#define SF_CTRL_SF_AES_KEY_1 SF_CTRL_SF_AES_KEY_1 +#define SF_CTRL_SF_AES_KEY_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_1_MSK (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS) +#define SF_CTRL_SF_AES_KEY_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)) + +/* 0x8 : sf_aes_key_2 */ +#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8) +#define SF_CTRL_SF_AES_KEY_2 SF_CTRL_SF_AES_KEY_2 +#define SF_CTRL_SF_AES_KEY_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_2_MSK (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS) +#define SF_CTRL_SF_AES_KEY_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)) + +/* 0xc : sf_aes_key_3 */ +#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc) +#define SF_CTRL_SF_AES_KEY_3 SF_CTRL_SF_AES_KEY_3 +#define SF_CTRL_SF_AES_KEY_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_3_MSK (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS) +#define SF_CTRL_SF_AES_KEY_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)) + +/* 0x10 : sf_aes_key_4 */ +#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10) +#define SF_CTRL_SF_AES_KEY_4 SF_CTRL_SF_AES_KEY_4 +#define SF_CTRL_SF_AES_KEY_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_4_MSK (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS) +#define SF_CTRL_SF_AES_KEY_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)) + +/* 0x14 : sf_aes_key_5 */ +#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14) +#define SF_CTRL_SF_AES_KEY_5 SF_CTRL_SF_AES_KEY_5 +#define SF_CTRL_SF_AES_KEY_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_5_MSK (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS) +#define SF_CTRL_SF_AES_KEY_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)) + +/* 0x18 : sf_aes_key_6 */ +#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18) +#define SF_CTRL_SF_AES_KEY_6 SF_CTRL_SF_AES_KEY_6 +#define SF_CTRL_SF_AES_KEY_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_6_MSK (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS) +#define SF_CTRL_SF_AES_KEY_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)) + +/* 0x1c : sf_aes_key_7 */ +#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c) +#define SF_CTRL_SF_AES_KEY_7 SF_CTRL_SF_AES_KEY_7 +#define SF_CTRL_SF_AES_KEY_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_7_MSK (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS) +#define SF_CTRL_SF_AES_KEY_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)) + +/* 0x20 : sf_aes_iv_w0 */ +#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20) +#define SF_CTRL_SF_AES_IV_W0 SF_CTRL_SF_AES_IV_W0 +#define SF_CTRL_SF_AES_IV_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_W0_MSK (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS) +#define SF_CTRL_SF_AES_IV_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)) + +/* 0x24 : sf_aes_iv_w1 */ +#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24) +#define SF_CTRL_SF_AES_IV_W1 SF_CTRL_SF_AES_IV_W1 +#define SF_CTRL_SF_AES_IV_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_W1_MSK (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS) +#define SF_CTRL_SF_AES_IV_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)) + +/* 0x28 : sf_aes_iv_w2 */ +#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28) +#define SF_CTRL_SF_AES_IV_W2 SF_CTRL_SF_AES_IV_W2 +#define SF_CTRL_SF_AES_IV_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_W2_MSK (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS) +#define SF_CTRL_SF_AES_IV_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)) + +/* 0x2c : sf_aes_iv_w3 */ +#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c) +#define SF_CTRL_SF_AES_IV_W3 SF_CTRL_SF_AES_IV_W3 +#define SF_CTRL_SF_AES_IV_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_W3_MSK (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS) +#define SF_CTRL_SF_AES_IV_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)) + +/* 0x30 : sf_aes_cfg */ +#define SF_CTRL_SF_AES_CFG_OFFSET (0x30) +#define SF_CTRL_SF_AES_REGION_END SF_CTRL_SF_AES_REGION_END +#define SF_CTRL_SF_AES_REGION_END_POS (0U) +#define SF_CTRL_SF_AES_REGION_END_LEN (14U) +#define SF_CTRL_SF_AES_REGION_END_MSK (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS) +#define SF_CTRL_SF_AES_REGION_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)) +#define SF_CTRL_SF_AES_REGION_START SF_CTRL_SF_AES_REGION_START +#define SF_CTRL_SF_AES_REGION_START_POS (14U) +#define SF_CTRL_SF_AES_REGION_START_LEN (14U) +#define SF_CTRL_SF_AES_REGION_START_MSK (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS) +#define SF_CTRL_SF_AES_REGION_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN SF_CTRL_SF_AES_REGION_HW_KEY_EN +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_REGION_EN SF_CTRL_SF_AES_REGION_EN +#define SF_CTRL_SF_AES_REGION_EN_POS (30U) +#define SF_CTRL_SF_AES_REGION_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS) +#define SF_CTRL_SF_AES_REGION_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)) +#define SF_CTRL_SF_AES_REGION_LOCK SF_CTRL_SF_AES_REGION_LOCK +#define SF_CTRL_SF_AES_REGION_LOCK_POS (31U) +#define SF_CTRL_SF_AES_REGION_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_REGION_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS) +#define SF_CTRL_SF_AES_REGION_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)) + +struct sf_ctrl_aes_region_reg { + /* 0x0 : sf_aes_key_0 */ + union { + struct + { + uint32_t sf_aes_key_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_0; + + /* 0x4 : sf_aes_key_1 */ + union { + struct + { + uint32_t sf_aes_key_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_1; + + /* 0x8 : sf_aes_key_2 */ + union { + struct + { + uint32_t sf_aes_key_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_2; + + /* 0xc : sf_aes_key_3 */ + union { + struct + { + uint32_t sf_aes_key_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_3; + + /* 0x10 : sf_aes_key_4 */ + union { + struct + { + uint32_t sf_aes_key_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_4; + + /* 0x14 : sf_aes_key_5 */ + union { + struct + { + uint32_t sf_aes_key_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_5; + + /* 0x18 : sf_aes_key_6 */ + union { + struct + { + uint32_t sf_aes_key_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_6; + + /* 0x1c : sf_aes_key_7 */ + union { + struct + { + uint32_t sf_aes_key_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_7; + + /* 0x20 : sf_aes_iv_w0 */ + union { + struct + { + uint32_t sf_aes_iv_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w0; + + /* 0x24 : sf_aes_iv_w1 */ + union { + struct + { + uint32_t sf_aes_iv_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w1; + + /* 0x28 : sf_aes_iv_w2 */ + union { + struct + { + uint32_t sf_aes_iv_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w2; + + /* 0x2c : sf_aes_iv_w3 */ + union { + struct + { + uint32_t sf_aes_iv_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w3; + + /* 0x30 : sf_aes_cfg */ + union { + struct + { + uint32_t sf_aes_region_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_region_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_region_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_region_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_region_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_cfg; +}; + +typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t; + +#define SF_CTRL_AES_REGION_OFFSET 0x200 + +#endif /* __SF_CTRL_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/soc602_reg.svd b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/soc602_reg.svd new file mode 100644 index 0000000000000000000000000000000000000000..5c9862274b14665335438c1ea236c2e0675d74b5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/soc602_reg.svd @@ -0,0 +1,14899 @@ + + + bouffalolab + bouffalolab + 602 + WiFi BT + high-performance, 32-bit RV32IMAFC core + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + 602 + little + + + + glb + glb. + 0x40000000 + glb + 32 + read-write + + 0 + 0x1000 + registers + + + + clk_cfg0 + clk_cfg0. + 0x0 + + + glb_id + 28 + 31 + + + chip_rdy + 27 + 27 + + + fclk_sw_state + 24 + 26 + + + reg_bclk_div + 16 + 23 + + + reg_hclk_div + 8 + 15 + + + hbn_root_clk_sel + 6 + 7 + + + reg_pll_sel + 4 + 5 + + + reg_bclk_en + 3 + 3 + + + reg_hclk_en + 2 + 2 + + + reg_fclk_en + 1 + 1 + + + reg_pll_en + 0 + 0 + + + + + clk_cfg1 + clk_cfg1. + 0x4 + + + ble_en + 24 + 24 + + + ble_clk_sel + 16 + 21 + + + wifi_mac_wt_div + 4 + 7 + + + wifi_mac_core_div + 0 + 3 + + + + + clk_cfg2 + clk_cfg2. + 0x8 + + + dma_clk_en + 24 + 31 + + + ir_clk_en + 23 + 23 + + + ir_clk_div + 16 + 21 + + + sf_clk_sel2 + 14 + 15 + + + sf_clk_sel + 12 + 13 + + + sf_clk_en + 11 + 11 + + + sf_clk_div + 8 + 10 + + + hbn_uart_clk_sel + 7 + 7 + + + uart_clk_en + 4 + 4 + + + uart_clk_div + 0 + 2 + + + + + clk_cfg3 + clk_cfg3. + 0xC + + + i2c_clk_en + 24 + 24 + + + i2c_clk_div + 16 + 23 + + + spi_clk_en + 8 + 8 + + + spi_clk_div + 0 + 4 + + + + + swrst_cfg0 + swrst_cfg0. + 0x10 + + + swrst_s30 + 8 + 8 + + + swrst_s20 + 4 + 4 + + + swrst_s01 + 1 + 1 + + + swrst_s00 + 0 + 0 + + + + + swrst_cfg1 + swrst_cfg1. + 0x14 + + + swrst_s1a7 + 23 + 23 + + + swrst_s1a6 + 22 + 22 + + + swrst_s1a5 + 21 + 21 + + + swrst_s1a4 + 20 + 20 + + + swrst_s1a3 + 19 + 19 + + + swrst_s1a2 + 18 + 18 + + + swrst_s1a1 + 17 + 17 + + + swrst_s1a0 + 16 + 16 + + + swrst_s1f + 15 + 15 + + + swrst_s1e + 14 + 14 + + + swrst_s1d + 13 + 13 + + + swrst_s1c + 12 + 12 + + + swrst_s1b + 11 + 11 + + + swrst_s1a + 10 + 10 + + + swrst_s19 + 9 + 9 + + + swrst_s18 + 8 + 8 + + + swrst_s17 + 7 + 7 + + + swrst_s16 + 6 + 6 + + + swrst_s15 + 5 + 5 + + + swrst_s14 + 4 + 4 + + + swrst_s13 + 3 + 3 + + + swrst_s12 + 2 + 2 + + + swrst_s11 + 1 + 1 + + + swrst_s10 + 0 + 0 + + + + + swrst_cfg2 + swrst_cfg2. + 0x18 + + + pka_clk_sel + 24 + 24 + + + reg_ctrl_reset_dummy + 4 + 7 + + + reg_ctrl_sys_reset + 2 + 2 + + + reg_ctrl_cpu_reset + 1 + 1 + + + reg_ctrl_pwron_rst + 0 + 0 + + + + + swrst_cfg3 + swrst_cfg3. + 0x1C + + + + cgen_cfg0 + cgen_cfg0. + 0x20 + + + cgen_m + 0 + 7 + + + + + cgen_cfg1 + cgen_cfg1. + 0x24 + + + cgen_s1a + 16 + 23 + + + cgen_s1 + 0 + 15 + + + + + cgen_cfg2 + cgen_cfg2. + 0x28 + + + cgen_s3 + 4 + 4 + + + cgen_s2 + 0 + 0 + + + + + cgen_cfg3 + cgen_cfg3. + 0x2C + + + + MBIST_CTL + MBIST_CTL. + 0x30 + + + reg_mbist_rst_n + 31 + 31 + + + wifi_mbist_mode + 4 + 4 + + + ocram_mbist_mode + 3 + 3 + + + tag_mbist_mode + 2 + 2 + + + hsram_mbist_mode + 1 + 1 + + + irom_mbist_mode + 0 + 0 + + + + + MBIST_STAT + MBIST_STAT. + 0x34 + + + wifi_mbist_fail + 20 + 20 + + + ocram_mbist_fail + 19 + 19 + + + tag_mbist_fail + 18 + 18 + + + hsram_mbist_fail + 17 + 17 + + + irom_mbist_fail + 16 + 16 + + + wifi_mbist_done + 4 + 4 + + + ocram_mbist_done + 3 + 3 + + + tag_mbist_done + 2 + 2 + + + hsram_mbist_done + 1 + 1 + + + irom_mbist_done + 0 + 0 + + + + + bmx_cfg1 + bmx_cfg1. + 0x50 + + + hbn_apb_cfg + 24 + 31 + + + pds_apb_cfg + 16 + 23 + + + hsel_option + 12 + 15 + + + bmx_gating_dis + 10 + 10 + + + bmx_busy_option_dis + 9 + 9 + + + bmx_err_en + 8 + 8 + + + bmx_arb_mode + 4 + 5 + + + bmx_timeout_en + 0 + 3 + + + + + bmx_cfg2 + bmx_cfg2. + 0x54 + + + bmx_dbg_sel + 28 + 31 + + + bmx_err_tz + 5 + 5 + + + bmx_err_dec + 4 + 4 + + + bmx_err_addr_dis + 0 + 0 + + + + + bmx_err_addr + bmx_err_addr. + 0x58 + + + bmx_err_addr + 0 + 31 + + + + + bmx_dbg_out + bmx_dbg_out. + 0x5C + + + bmx_dbg_out + 0 + 31 + + + + + rsv0 + rsv0. + 0x60 + + + rsvd_31_0 + 0 + 31 + + + + + rsv1 + rsv1. + 0x64 + + + rsvd_31_0 + 0 + 31 + + + + + rsv2 + rsv2. + 0x68 + + + rsvd_31_0 + 0 + 31 + + + + + rsv3 + rsv3. + 0x6C + + + rsvd_31_0 + 0 + 31 + + + + + sram_ret + sram_ret. + 0x70 + + + reg_sram_ret + 0 + 31 + + + + + sram_slp + sram_slp. + 0x74 + + + reg_sram_slp + 0 + 31 + + + + + sram_parm + sram_parm. + 0x78 + + + reg_sram_parm + 0 + 31 + + + + + seam_misc + seam_misc. + 0x7C + + + em_sel + 0 + 3 + + + + + glb_parm + glb_parm. + 0x80 + + + uart_swap_set + 24 + 26 + + + p7_jtag_use_io_2_5 + 23 + 23 + + + p6_sdio_use_io_0_5 + 22 + 22 + + + p5_dac_test_with_jtag + 21 + 21 + + + p4_adc_test_with_jtag + 20 + 20 + + + p3_cci_use_io_2_5 + 19 + 19 + + + p2_dac_test_with_cci + 18 + 18 + + + p1_adc_test_with_cci + 17 + 17 + + + reg_cci_use_sdio_pin + 16 + 16 + + + reg_cci_use_jtag_pin + 15 + 15 + + + reg_spi_0_swap + 13 + 13 + + + reg_spi_0_master_mode + 12 + 12 + + + sel_embedded_sflash + 9 + 9 + + + swap_sflash_io_3_io_0 + 8 + 8 + + + jtag_swap_set + 2 + 7 + + + reg_ext_rst_smt + 1 + 1 + + + reg_bd_en + 0 + 0 + + + + + CPU_CLK_CFG + CPU_CLK_CFG. + 0x90 + + + debug_ndreset_gate + 20 + 20 + + + cpu_rtc_sel + 19 + 19 + + + cpu_rtc_en + 18 + 18 + + + cpu_rtc_div + 0 + 16 + + + + + GPADC_32M_SRC_CTRL + GPADC_32M_SRC_CTRL. + 0xA4 + + + gpadc_32m_div_en + 8 + 8 + + + gpadc_32m_clk_sel + 7 + 7 + + + gpadc_32m_clk_div + 0 + 5 + + + + + DIG32K_WAKEUP_CTRL + DIG32K_WAKEUP_CTRL. + 0xA8 + + + reg_en_platform_wakeup + 31 + 31 + + + dig_clk_src_sel + 28 + 28 + + + dig_512k_comp + 25 + 25 + + + dig_512k_en + 24 + 24 + + + dig_512k_div + 16 + 22 + + + dig_32k_comp + 13 + 13 + + + dig_32k_en + 12 + 12 + + + dig_32k_div + 0 + 10 + + + + + WIFI_BT_COEX_CTRL + WIFI_BT_COEX_CTRL. + 0xAC + + + en_gpio_bt_coex + 12 + 12 + + + coex_bt_bw + 11 + 11 + + + coex_bt_pti + 7 + 10 + + + coex_bt_channel + 0 + 6 + + + + + UART_SIG_SEL_0 + UART_SIG_SEL_0. + 0xC0 + + + uart_sig_7_sel + 28 + 31 + + + uart_sig_6_sel + 24 + 27 + + + uart_sig_5_sel + 20 + 23 + + + uart_sig_4_sel + 16 + 19 + + + uart_sig_3_sel + 12 + 15 + + + uart_sig_2_sel + 8 + 11 + + + uart_sig_1_sel + 4 + 7 + + + uart_sig_0_sel + 0 + 3 + + + + + DBG_SEL_LL + DBG_SEL_LL. + 0xD0 + + + reg_dbg_ll_ctrl + 0 + 31 + + + + + DBG_SEL_LH + DBG_SEL_LH. + 0xD4 + + + reg_dbg_lh_ctrl + 0 + 31 + + + + + DBG_SEL_HL + DBG_SEL_HL. + 0xD8 + + + reg_dbg_hl_ctrl + 0 + 31 + + + + + DBG_SEL_HH + DBG_SEL_HH. + 0xDC + + + reg_dbg_hh_ctrl + 0 + 31 + + + + + debug + debug. + 0xE0 + + + debug_i + 1 + 31 + + + debug_oe + 0 + 0 + + + + + GPIO_CFGCTL0 + GPIO_CFGCTL0. + 0x100 + + + real_gpio_1_func_sel + 28 + 31 + + + reg_gpio_1_func_sel + 24 + 27 + + + reg_gpio_1_pd + 21 + 21 + + + reg_gpio_1_pu + 20 + 20 + + + reg_gpio_1_drv + 18 + 19 + + + reg_gpio_1_smt + 17 + 17 + + + reg_gpio_1_ie + 16 + 16 + + + real_gpio_0_func_sel + 12 + 15 + + + reg_gpio_0_func_sel + 8 + 11 + + + reg_gpio_0_pd + 5 + 5 + + + reg_gpio_0_pu + 4 + 4 + + + reg_gpio_0_drv + 2 + 3 + + + reg_gpio_0_smt + 1 + 1 + + + reg_gpio_0_ie + 0 + 0 + + + + + GPIO_CFGCTL1 + GPIO_CFGCTL1. + 0x104 + + + real_gpio_3_func_sel + 28 + 31 + + + reg_gpio_3_func_sel + 24 + 27 + + + reg_gpio_3_pd + 21 + 21 + + + reg_gpio_3_pu + 20 + 20 + + + reg_gpio_3_drv + 18 + 19 + + + reg_gpio_3_smt + 17 + 17 + + + reg_gpio_3_ie + 16 + 16 + + + real_gpio_2_func_sel + 12 + 15 + + + reg_gpio_2_func_sel + 8 + 11 + + + reg_gpio_2_pd + 5 + 5 + + + reg_gpio_2_pu + 4 + 4 + + + reg_gpio_2_drv + 2 + 3 + + + reg_gpio_2_smt + 1 + 1 + + + reg_gpio_2_ie + 0 + 0 + + + + + GPIO_CFGCTL2 + GPIO_CFGCTL2. + 0x108 + + + real_gpio_5_func_sel + 28 + 31 + + + reg_gpio_5_func_sel + 24 + 27 + + + reg_gpio_5_pd + 21 + 21 + + + reg_gpio_5_pu + 20 + 20 + + + reg_gpio_5_drv + 18 + 19 + + + reg_gpio_5_smt + 17 + 17 + + + reg_gpio_5_ie + 16 + 16 + + + real_gpio_4_func_sel + 12 + 15 + + + reg_gpio_4_func_sel + 8 + 11 + + + reg_gpio_4_pd + 5 + 5 + + + reg_gpio_4_pu + 4 + 4 + + + reg_gpio_4_drv + 2 + 3 + + + reg_gpio_4_smt + 1 + 1 + + + reg_gpio_4_ie + 0 + 0 + + + + + GPIO_CFGCTL3 + GPIO_CFGCTL3. + 0x10C + + + reg_gpio_7_func_sel + 24 + 27 + + + reg_gpio_7_pd + 21 + 21 + + + reg_gpio_7_pu + 20 + 20 + + + reg_gpio_7_drv + 18 + 19 + + + reg_gpio_7_smt + 17 + 17 + + + reg_gpio_7_ie + 16 + 16 + + + reg_gpio_6_func_sel + 8 + 11 + + + reg_gpio_6_pd + 5 + 5 + + + reg_gpio_6_pu + 4 + 4 + + + reg_gpio_6_drv + 2 + 3 + + + reg_gpio_6_smt + 1 + 1 + + + reg_gpio_6_ie + 0 + 0 + + + + + GPIO_CFGCTL4 + GPIO_CFGCTL4. + 0x110 + + + reg_gpio_9_func_sel + 24 + 27 + + + reg_gpio_9_pd + 21 + 21 + + + reg_gpio_9_pu + 20 + 20 + + + reg_gpio_9_drv + 18 + 19 + + + reg_gpio_9_smt + 17 + 17 + + + reg_gpio_9_ie + 16 + 16 + + + reg_gpio_8_func_sel + 8 + 11 + + + reg_gpio_8_pd + 5 + 5 + + + reg_gpio_8_pu + 4 + 4 + + + reg_gpio_8_drv + 2 + 3 + + + reg_gpio_8_smt + 1 + 1 + + + reg_gpio_8_ie + 0 + 0 + + + + + GPIO_CFGCTL5 + GPIO_CFGCTL5. + 0x114 + + + reg_gpio_11_func_sel + 24 + 27 + + + reg_gpio_11_pd + 21 + 21 + + + reg_gpio_11_pu + 20 + 20 + + + reg_gpio_11_drv + 18 + 19 + + + reg_gpio_11_smt + 17 + 17 + + + reg_gpio_11_ie + 16 + 16 + + + reg_gpio_10_func_sel + 8 + 11 + + + reg_gpio_10_pd + 5 + 5 + + + reg_gpio_10_pu + 4 + 4 + + + reg_gpio_10_drv + 2 + 3 + + + reg_gpio_10_smt + 1 + 1 + + + reg_gpio_10_ie + 0 + 0 + + + + + GPIO_CFGCTL6 + GPIO_CFGCTL6. + 0x118 + + + reg_gpio_13_func_sel + 24 + 27 + + + reg_gpio_13_pd + 21 + 21 + + + reg_gpio_13_pu + 20 + 20 + + + reg_gpio_13_drv + 18 + 19 + + + reg_gpio_13_smt + 17 + 17 + + + reg_gpio_13_ie + 16 + 16 + + + reg_gpio_12_func_sel + 8 + 11 + + + reg_gpio_12_pd + 5 + 5 + + + reg_gpio_12_pu + 4 + 4 + + + reg_gpio_12_drv + 2 + 3 + + + reg_gpio_12_smt + 1 + 1 + + + reg_gpio_12_ie + 0 + 0 + + + + + GPIO_CFGCTL7 + GPIO_CFGCTL7. + 0x11C + + + reg_gpio_15_func_sel + 24 + 27 + + + reg_gpio_15_pd + 21 + 21 + + + reg_gpio_15_pu + 20 + 20 + + + reg_gpio_15_drv + 18 + 19 + + + reg_gpio_15_smt + 17 + 17 + + + reg_gpio_15_ie + 16 + 16 + + + reg_gpio_14_func_sel + 8 + 11 + + + reg_gpio_14_pd + 5 + 5 + + + reg_gpio_14_pu + 4 + 4 + + + reg_gpio_14_drv + 2 + 3 + + + reg_gpio_14_smt + 1 + 1 + + + reg_gpio_14_ie + 0 + 0 + + + + + GPIO_CFGCTL8 + GPIO_CFGCTL8. + 0x120 + + + reg_gpio_17_func_sel + 24 + 27 + + + reg_gpio_17_pd + 21 + 21 + + + reg_gpio_17_pu + 20 + 20 + + + reg_gpio_17_drv + 18 + 19 + + + reg_gpio_17_smt + 17 + 17 + + + reg_gpio_17_ie + 16 + 16 + + + reg_gpio_16_func_sel + 8 + 11 + + + reg_gpio_16_pd + 5 + 5 + + + reg_gpio_16_pu + 4 + 4 + + + reg_gpio_16_drv + 2 + 3 + + + reg_gpio_16_smt + 1 + 1 + + + reg_gpio_16_ie + 0 + 0 + + + + + GPIO_CFGCTL9 + GPIO_CFGCTL9. + 0x124 + + + reg_gpio_19_func_sel + 24 + 27 + + + reg_gpio_19_pd + 21 + 21 + + + reg_gpio_19_pu + 20 + 20 + + + reg_gpio_19_drv + 18 + 19 + + + reg_gpio_19_smt + 17 + 17 + + + reg_gpio_19_ie + 16 + 16 + + + reg_gpio_18_func_sel + 8 + 11 + + + reg_gpio_18_pd + 5 + 5 + + + reg_gpio_18_pu + 4 + 4 + + + reg_gpio_18_drv + 2 + 3 + + + reg_gpio_18_smt + 1 + 1 + + + reg_gpio_18_ie + 0 + 0 + + + + + GPIO_CFGCTL10 + GPIO_CFGCTL10. + 0x128 + + + reg_gpio_21_func_sel + 24 + 27 + + + reg_gpio_21_pd + 21 + 21 + + + reg_gpio_21_pu + 20 + 20 + + + reg_gpio_21_drv + 18 + 19 + + + reg_gpio_21_smt + 17 + 17 + + + reg_gpio_21_ie + 16 + 16 + + + reg_gpio_20_func_sel + 8 + 11 + + + reg_gpio_20_pd + 5 + 5 + + + reg_gpio_20_pu + 4 + 4 + + + reg_gpio_20_drv + 2 + 3 + + + reg_gpio_20_smt + 1 + 1 + + + reg_gpio_20_ie + 0 + 0 + + + + + GPIO_CFGCTL11 + GPIO_CFGCTL11. + 0x12C + + + reg_gpio_23_pd + 21 + 21 + + + reg_gpio_23_pu + 20 + 20 + + + reg_gpio_23_drv + 18 + 19 + + + reg_gpio_23_smt + 17 + 17 + + + reg_gpio_23_ie + 16 + 16 + + + reg_gpio_22_func_sel + 8 + 11 + + + reg_gpio_22_pd + 5 + 5 + + + reg_gpio_22_pu + 4 + 4 + + + reg_gpio_22_drv + 2 + 3 + + + reg_gpio_22_smt + 1 + 1 + + + reg_gpio_22_ie + 0 + 0 + + + + + GPIO_CFGCTL12 + GPIO_CFGCTL12. + 0x130 + + + reg_gpio_25_pd + 21 + 21 + + + reg_gpio_25_pu + 20 + 20 + + + reg_gpio_25_drv + 18 + 19 + + + reg_gpio_25_smt + 17 + 17 + + + reg_gpio_25_ie + 16 + 16 + + + reg_gpio_24_pd + 5 + 5 + + + reg_gpio_24_pu + 4 + 4 + + + reg_gpio_24_drv + 2 + 3 + + + reg_gpio_24_smt + 1 + 1 + + + reg_gpio_24_ie + 0 + 0 + + + + + GPIO_CFGCTL13 + GPIO_CFGCTL13. + 0x134 + + + reg_gpio_27_pd + 21 + 21 + + + reg_gpio_27_pu + 20 + 20 + + + reg_gpio_27_drv + 18 + 19 + + + reg_gpio_27_smt + 17 + 17 + + + reg_gpio_27_ie + 16 + 16 + + + reg_gpio_26_pd + 5 + 5 + + + reg_gpio_26_pu + 4 + 4 + + + reg_gpio_26_drv + 2 + 3 + + + reg_gpio_26_smt + 1 + 1 + + + reg_gpio_26_ie + 0 + 0 + + + + + GPIO_CFGCTL14 + GPIO_CFGCTL14. + 0x138 + + + reg_gpio_28_pd + 5 + 5 + + + reg_gpio_28_pu + 4 + 4 + + + reg_gpio_28_drv + 2 + 3 + + + reg_gpio_28_smt + 1 + 1 + + + reg_gpio_28_ie + 0 + 0 + + + + + GPIO_CFGCTL30 + GPIO_CFGCTL30. + 0x180 + + + reg_gpio_22_i + 22 + 22 + + + reg_gpio_21_i + 21 + 21 + + + reg_gpio_20_i + 20 + 20 + + + reg_gpio_19_i + 19 + 19 + + + reg_gpio_18_i + 18 + 18 + + + reg_gpio_17_i + 17 + 17 + + + reg_gpio_16_i + 16 + 16 + + + reg_gpio_15_i + 15 + 15 + + + reg_gpio_14_i + 14 + 14 + + + reg_gpio_13_i + 13 + 13 + + + reg_gpio_12_i + 12 + 12 + + + reg_gpio_11_i + 11 + 11 + + + reg_gpio_10_i + 10 + 10 + + + reg_gpio_9_i + 9 + 9 + + + reg_gpio_8_i + 8 + 8 + + + reg_gpio_7_i + 7 + 7 + + + reg_gpio_6_i + 6 + 6 + + + reg_gpio_5_i + 5 + 5 + + + reg_gpio_4_i + 4 + 4 + + + reg_gpio_3_i + 3 + 3 + + + reg_gpio_2_i + 2 + 2 + + + reg_gpio_1_i + 1 + 1 + + + reg_gpio_0_i + 0 + 0 + + + + + GPIO_CFGCTL31 + GPIO_CFGCTL31. + 0x184 + + + + GPIO_CFGCTL32 + GPIO_CFGCTL32. + 0x188 + + + reg_gpio_22_o + 22 + 22 + + + reg_gpio_21_o + 21 + 21 + + + reg_gpio_20_o + 20 + 20 + + + reg_gpio_19_o + 19 + 19 + + + reg_gpio_18_o + 18 + 18 + + + reg_gpio_17_o + 17 + 17 + + + reg_gpio_16_o + 16 + 16 + + + reg_gpio_15_o + 15 + 15 + + + reg_gpio_14_o + 14 + 14 + + + reg_gpio_13_o + 13 + 13 + + + reg_gpio_12_o + 12 + 12 + + + reg_gpio_11_o + 11 + 11 + + + reg_gpio_10_o + 10 + 10 + + + reg_gpio_9_o + 9 + 9 + + + reg_gpio_8_o + 8 + 8 + + + reg_gpio_7_o + 7 + 7 + + + reg_gpio_6_o + 6 + 6 + + + reg_gpio_5_o + 5 + 5 + + + reg_gpio_4_o + 4 + 4 + + + reg_gpio_3_o + 3 + 3 + + + reg_gpio_2_o + 2 + 2 + + + reg_gpio_1_o + 1 + 1 + + + reg_gpio_0_o + 0 + 0 + + + + + GPIO_CFGCTL33 + GPIO_CFGCTL33. + 0x18C + + + + GPIO_CFGCTL34 + GPIO_CFGCTL34. + 0x190 + + + reg_gpio_22_oe + 22 + 22 + + + reg_gpio_21_oe + 21 + 21 + + + reg_gpio_20_oe + 20 + 20 + + + reg_gpio_19_oe + 19 + 19 + + + reg_gpio_18_oe + 18 + 18 + + + reg_gpio_17_oe + 17 + 17 + + + reg_gpio_16_oe + 16 + 16 + + + reg_gpio_15_oe + 15 + 15 + + + reg_gpio_14_oe + 14 + 14 + + + reg_gpio_13_oe + 13 + 13 + + + reg_gpio_12_oe + 12 + 12 + + + reg_gpio_11_oe + 11 + 11 + + + reg_gpio_10_oe + 10 + 10 + + + reg_gpio_9_oe + 9 + 9 + + + reg_gpio_8_oe + 8 + 8 + + + reg_gpio_7_oe + 7 + 7 + + + reg_gpio_6_oe + 6 + 6 + + + reg_gpio_5_oe + 5 + 5 + + + reg_gpio_4_oe + 4 + 4 + + + reg_gpio_3_oe + 3 + 3 + + + reg_gpio_2_oe + 2 + 2 + + + reg_gpio_1_oe + 1 + 1 + + + reg_gpio_0_oe + 0 + 0 + + + + + GPIO_CFGCTL35 + GPIO_CFGCTL35. + 0x194 + + + + GPIO_INT_MASK1 + GPIO_INT_MASK1. + 0x1A0 + + + reg_gpio_int_mask1 + 0 + 31 + + + + + GPIO_INT_STAT1 + GPIO_INT_STAT1. + 0x1A8 + + + gpio_int_stat1 + 0 + 31 + + + + + GPIO_INT_CLR1 + GPIO_INT_CLR1. + 0x1B0 + + + reg_gpio_int_clr1 + 0 + 31 + + + + + GPIO_INT_MODE_SET1 + GPIO_INT_MODE_SET1. + 0x1C0 + + + reg_gpio_int_mode_set1 + 0 + 31 + + + + + GPIO_INT_MODE_SET2 + GPIO_INT_MODE_SET2. + 0x1C4 + + + reg_gpio_int_mode_set2 + 0 + 31 + + + + + GPIO_INT_MODE_SET3 + GPIO_INT_MODE_SET3. + 0x1C8 + + + reg_gpio_int_mode_set3 + 0 + 31 + + + + + led_driver + led_driver. + 0x224 + + + pu_leddrv + 31 + 31 + + + ir_rx_gpio_sel + 8 + 9 + + + leddrv_ibias + 4 + 7 + + + led_din_polarity_sel + 2 + 2 + + + led_din_sel + 1 + 1 + + + led_din_reg + 0 + 0 + + + + + gpdac_ctrl + gpdac_ctrl. + 0x308 + + + gpdac_reserved + 24 + 31 + + + gpdac_test_sel + 9 + 11 + + + gpdac_ref_sel + 8 + 8 + + + gpdac_test_en + 7 + 7 + + + gpdacb_rstn_ana + 1 + 1 + + + gpdaca_rstn_ana + 0 + 0 + + + + + gpdac_actrl + gpdac_actrl. + 0x30C + + + gpdac_a_outmux + 20 + 22 + + + gpdac_a_rng + 18 + 19 + + + gpdac_ioa_en + 1 + 1 + + + gpdac_a_en + 0 + 0 + + + + + gpdac_bctrl + gpdac_bctrl. + 0x310 + + + gpdac_b_outmux + 20 + 22 + + + gpdac_b_rng + 18 + 19 + + + gpdac_iob_en + 1 + 1 + + + gpdac_b_en + 0 + 0 + + + + + gpdac_data + gpdac_data. + 0x314 + + + gpdac_a_data + 16 + 25 + + + gpdac_b_data + 0 + 9 + + + + + tzc_glb_ctrl_0 + tzc_glb_ctrl_0. + 0xF00 + + + tzc_glb_clk_lock + 31 + 31 + + + tzc_glb_mbist_lock + 30 + 30 + + + tzc_glb_dbg_lock + 29 + 29 + + + tzc_glb_bmx_lock + 28 + 28 + + + tzc_glb_l2c_lock + 27 + 27 + + + tzc_glb_sram_lock + 26 + 26 + + + tzc_glb_misc_lock + 25 + 25 + + + tzc_glb_ctrl_ungated_ap_lock + 15 + 15 + + + tzc_glb_ctrl_sys_reset_lock + 14 + 14 + + + tzc_glb_ctrl_cpu_reset_lock + 13 + 13 + + + tzc_glb_ctrl_pwron_rst_lock + 12 + 12 + + + tzc_glb_swrst_s30_lock + 8 + 8 + + + tzc_glb_swrst_s01_lock + 1 + 1 + + + tzc_glb_swrst_s00_lock + 0 + 0 + + + + + tzc_glb_ctrl_1 + tzc_glb_ctrl_1. + 0xF04 + + + tzc_glb_swrst_s1f_lock + 31 + 31 + + + tzc_glb_swrst_s1e_lock + 30 + 30 + + + tzc_glb_swrst_s1d_lock + 29 + 29 + + + tzc_glb_swrst_s1c_lock + 28 + 28 + + + tzc_glb_swrst_s1b_lock + 27 + 27 + + + tzc_glb_swrst_s1a_lock + 26 + 26 + + + tzc_glb_swrst_s19_lock + 25 + 25 + + + tzc_glb_swrst_s18_lock + 24 + 24 + + + tzc_glb_swrst_s17_lock + 23 + 23 + + + tzc_glb_swrst_s16_lock + 22 + 22 + + + tzc_glb_swrst_s15_lock + 21 + 21 + + + tzc_glb_swrst_s14_lock + 20 + 20 + + + tzc_glb_swrst_s13_lock + 19 + 19 + + + tzc_glb_swrst_s12_lock + 18 + 18 + + + tzc_glb_swrst_s11_lock + 17 + 17 + + + tzc_glb_swrst_s10_lock + 16 + 16 + + + tzc_glb_swrst_s2f_lock + 15 + 15 + + + tzc_glb_swrst_s2e_lock + 14 + 14 + + + tzc_glb_swrst_s2d_lock + 13 + 13 + + + tzc_glb_swrst_s2c_lock + 12 + 12 + + + tzc_glb_swrst_s2b_lock + 11 + 11 + + + tzc_glb_swrst_s2a_lock + 10 + 10 + + + tzc_glb_swrst_s29_lock + 9 + 9 + + + tzc_glb_swrst_s28_lock + 8 + 8 + + + tzc_glb_swrst_s27_lock + 7 + 7 + + + tzc_glb_swrst_s26_lock + 6 + 6 + + + tzc_glb_swrst_s25_lock + 5 + 5 + + + tzc_glb_swrst_s24_lock + 4 + 4 + + + tzc_glb_swrst_s23_lock + 3 + 3 + + + tzc_glb_swrst_s22_lock + 2 + 2 + + + tzc_glb_swrst_s21_lock + 1 + 1 + + + tzc_glb_swrst_s20_lock + 0 + 0 + + + + + tzc_glb_ctrl_2 + tzc_glb_ctrl_2. + 0xF08 + + + tzc_glb_gpio_28_lock + 28 + 28 + + + tzc_glb_gpio_27_lock + 27 + 27 + + + tzc_glb_gpio_26_lock + 26 + 26 + + + tzc_glb_gpio_25_lock + 25 + 25 + + + tzc_glb_gpio_24_lock + 24 + 24 + + + tzc_glb_gpio_23_lock + 23 + 23 + + + tzc_glb_gpio_22_lock + 22 + 22 + + + tzc_glb_gpio_21_lock + 21 + 21 + + + tzc_glb_gpio_20_lock + 20 + 20 + + + tzc_glb_gpio_19_lock + 19 + 19 + + + tzc_glb_gpio_18_lock + 18 + 18 + + + tzc_glb_gpio_17_lock + 17 + 17 + + + tzc_glb_gpio_16_lock + 16 + 16 + + + tzc_glb_gpio_15_lock + 15 + 15 + + + tzc_glb_gpio_14_lock + 14 + 14 + + + tzc_glb_gpio_13_lock + 13 + 13 + + + tzc_glb_gpio_12_lock + 12 + 12 + + + tzc_glb_gpio_11_lock + 11 + 11 + + + tzc_glb_gpio_10_lock + 10 + 10 + + + tzc_glb_gpio_9_lock + 9 + 9 + + + tzc_glb_gpio_8_lock + 8 + 8 + + + tzc_glb_gpio_7_lock + 7 + 7 + + + tzc_glb_gpio_6_lock + 6 + 6 + + + tzc_glb_gpio_5_lock + 5 + 5 + + + tzc_glb_gpio_4_lock + 4 + 4 + + + tzc_glb_gpio_3_lock + 3 + 3 + + + tzc_glb_gpio_2_lock + 2 + 2 + + + tzc_glb_gpio_1_lock + 1 + 1 + + + tzc_glb_gpio_0_lock + 0 + 0 + + + + + tzc_glb_ctrl_3 + tzc_glb_ctrl_3. + 0xF0C + + + + + + gpip + gpip. + 0x40002000 + gpip + 32 + read-write + + 0 + 0x1000 + registers + + + + gpadc_config + gpadc_config. + 0x0 + + + rsvd_31_24 + 24 + 31 + + + gpadc_fifo_thl + 22 + 23 + + + gpadc_fifo_data_count + 16 + 21 + + + gpadc_fifo_underrun_mask + 14 + 14 + + + gpadc_fifo_overrun_mask + 13 + 13 + + + gpadc_rdy_mask + 12 + 12 + + + gpadc_fifo_underrun_clr + 10 + 10 + + + gpadc_fifo_overrun_clr + 9 + 9 + + + gpadc_rdy_clr + 8 + 8 + + + gpadc_fifo_underrun + 6 + 6 + + + gpadc_fifo_overrun + 5 + 5 + + + gpadc_rdy + 4 + 4 + + + gpadc_fifo_full + 3 + 3 + + + gpadc_fifo_ne + 2 + 2 + + + gpadc_fifo_clr + 1 + 1 + + + gpadc_dma_en + 0 + 0 + + + + + gpadc_dma_rdata + gpadc_dma_rdata. + 0x4 + + + rsvd_31_26 + 26 + 31 + + + gpadc_dma_rdata + 0 + 25 + + + + + gpdac_config + gpdac_config. + 0x40 + + + rsvd_31_24 + 24 + 31 + + + gpdac_ch_b_sel + 20 + 23 + + + gpdac_ch_a_sel + 16 + 19 + + + gpdac_mode + 8 + 10 + + + dsm_mode + 4 + 5 + + + gpdac_en2 + 1 + 1 + + + gpdac_en + 0 + 0 + + + + + gpdac_dma_config + gpdac_dma_config. + 0x44 + + + gpdac_dma_format + 4 + 5 + + + gpdac_dma_tx_en + 0 + 0 + + + + + gpdac_dma_wdata + gpdac_dma_wdata. + 0x48 + + + gpdac_dma_wdata + 0 + 31 + + + + + gpdac_tx_fifo_status + gpdac_tx_fifo_status. + 0x4C + + + TxFifoWrPtr + 8 + 9 + + + TxFifoRdPtr + 4 + 6 + + + tx_cs + 2 + 3 + + + tx_fifo_full + 1 + 1 + + + tx_fifo_empty + 0 + 0 + + + + + + + sec_dbg + sec_dbg. + 0x40003000 + sec_dbg + 32 + read-write + + 0 + 0x1000 + registers + + + + sd_chip_id_low + sd_chip_id_low. + 0x0 + + + sd_chip_id_low + 0 + 31 + + + + + sd_chip_id_high + sd_chip_id_high. + 0x4 + + + sd_chip_id_high + 0 + 31 + + + + + sd_wifi_mac_low + sd_wifi_mac_low. + 0x8 + + + sd_wifi_mac_low + 0 + 31 + + + + + sd_wifi_mac_high + sd_wifi_mac_high. + 0xC + + + sd_wifi_mac_high + 0 + 31 + + + + + sd_dbg_pwd_low + sd_dbg_pwd_low. + 0x10 + + + sd_dbg_pwd_low + 0 + 31 + + + + + sd_dbg_pwd_high + sd_dbg_pwd_high. + 0x14 + + + sd_dbg_pwd_high + 0 + 31 + + + + + sd_status + sd_status. + 0x18 + + + sd_dbg_ena + 28 + 31 + + + sd_dbg_mode + 24 + 27 + + + sd_dbg_pwd_cnt + 4 + 23 + + + sd_dbg_cci_clk_sel + 3 + 3 + + + sd_dbg_cci_read_en + 2 + 2 + + + sd_dbg_pwd_trig + 1 + 1 + + + sd_dbg_pwd_busy + 0 + 0 + + + + + sd_dbg_reserved + sd_dbg_reserved. + 0x1C + + + sd_dbg_reserved + 0 + 31 + + + + + + + sec_eng + sec_eng. + 0x40004000 + sec_eng + 32 + read-write + + 0 + 0x1000 + registers + + + + se_sha_0_ctrl + se_sha_0_ctrl. + 0x0 + + + se_sha_0_msg_len + 16 + 31 + + + se_sha_0_link_mode + 15 + 15 + + + se_sha_0_int_mask + 11 + 11 + + + se_sha_0_int_set_1t + 10 + 10 + + + se_sha_0_int_clr_1t + 9 + 9 + + + se_sha_0_int + 8 + 8 + + + se_sha_0_hash_sel + 6 + 6 + + + se_sha_0_en + 5 + 5 + + + se_sha_0_mode + 2 + 4 + + + se_sha_0_trig_1t + 1 + 1 + + + se_sha_0_busy + 0 + 0 + + + + + se_sha_0_msa + se_sha_0_msa. + 0x4 + + + se_sha_0_msa + 0 + 31 + + + + + se_sha_0_status + se_sha_0_status. + 0x8 + + + se_sha_0_status + 0 + 31 + + + + + se_sha_0_endian + se_sha_0_endian. + 0xC + + + se_sha_0_dout_endian + 0 + 0 + + + + + se_sha_0_hash_l_0 + se_sha_0_hash_l_0. + 0x10 + + + se_sha_0_hash_l_0 + 0 + 31 + + + + + se_sha_0_hash_l_1 + se_sha_0_hash_l_1. + 0x14 + + + se_sha_0_hash_l_1 + 0 + 31 + + + + + se_sha_0_hash_l_2 + se_sha_0_hash_l_2. + 0x18 + + + se_sha_0_hash_l_2 + 0 + 31 + + + + + se_sha_0_hash_l_3 + se_sha_0_hash_l_3. + 0x1C + + + se_sha_0_hash_l_3 + 0 + 31 + + + + + se_sha_0_hash_l_4 + se_sha_0_hash_l_4. + 0x20 + + + se_sha_0_hash_l_4 + 0 + 31 + + + + + se_sha_0_hash_l_5 + se_sha_0_hash_l_5. + 0x24 + + + se_sha_0_hash_l_5 + 0 + 31 + + + + + se_sha_0_hash_l_6 + se_sha_0_hash_l_6. + 0x28 + + + se_sha_0_hash_l_6 + 0 + 31 + + + + + se_sha_0_hash_l_7 + se_sha_0_hash_l_7. + 0x2C + + + se_sha_0_hash_l_7 + 0 + 31 + + + + + se_sha_0_hash_h_0 + se_sha_0_hash_h_0. + 0x30 + + + se_sha_0_hash_h_0 + 0 + 31 + + + + + se_sha_0_hash_h_1 + se_sha_0_hash_h_1. + 0x34 + + + se_sha_0_hash_h_1 + 0 + 31 + + + + + se_sha_0_hash_h_2 + se_sha_0_hash_h_2. + 0x38 + + + se_sha_0_hash_h_2 + 0 + 31 + + + + + se_sha_0_hash_h_3 + se_sha_0_hash_h_3. + 0x3C + + + se_sha_0_hash_h_3 + 0 + 31 + + + + + se_sha_0_hash_h_4 + se_sha_0_hash_h_4. + 0x40 + + + se_sha_0_hash_h_4 + 0 + 31 + + + + + se_sha_0_hash_h_5 + se_sha_0_hash_h_5. + 0x44 + + + se_sha_0_hash_h_5 + 0 + 31 + + + + + se_sha_0_hash_h_6 + se_sha_0_hash_h_6. + 0x48 + + + se_sha_0_hash_h_6 + 0 + 31 + + + + + se_sha_0_hash_h_7 + se_sha_0_hash_h_7. + 0x4C + + + se_sha_0_hash_h_7 + 0 + 31 + + + + + se_sha_0_link + se_sha_0_link. + 0x50 + + + se_sha_0_lca + 0 + 31 + + + + + se_sha_0_ctrl_prot + se_sha_0_ctrl_prot. + 0xFC + + + se_sha_id1_en + 2 + 2 + + + se_sha_id0_en + 1 + 1 + + + se_sha_prot_en + 0 + 0 + + + + + se_aes_0_ctrl + se_aes_0_ctrl. + 0x100 + + + se_aes_0_msg_len + 16 + 31 + + + se_aes_0_link_mode + 15 + 15 + + + se_aes_0_iv_sel + 14 + 14 + + + se_aes_0_block_mode + 12 + 13 + + + se_aes_0_int_mask + 11 + 11 + + + se_aes_0_int_set_1t + 10 + 10 + + + se_aes_0_int_clr_1t + 9 + 9 + + + se_aes_0_int + 8 + 8 + + + se_aes_0_hw_key_en + 7 + 7 + + + se_aes_0_dec_key_sel + 6 + 6 + + + se_aes_0_dec_en + 5 + 5 + + + se_aes_0_mode + 3 + 4 + + + se_aes_0_en + 2 + 2 + + + se_aes_0_trig_1t + 1 + 1 + + + se_aes_0_busy + 0 + 0 + + + + + se_aes_0_msa + se_aes_0_msa. + 0x104 + + + se_aes_0_msa + 0 + 31 + + + + + se_aes_0_mda + se_aes_0_mda. + 0x108 + + + se_aes_0_mda + 0 + 31 + + + + + se_aes_0_status + se_aes_0_status. + 0x10C + + + se_aes_0_status + 0 + 31 + + + + + se_aes_0_iv_0 + se_aes_0_iv_0. + 0x110 + + + se_aes_0_iv_0 + 0 + 31 + + + + + se_aes_0_iv_1 + se_aes_0_iv_1. + 0x114 + + + se_aes_0_iv_1 + 0 + 31 + + + + + se_aes_0_iv_2 + se_aes_0_iv_2. + 0x118 + + + se_aes_0_iv_2 + 0 + 31 + + + + + se_aes_0_iv_3 + se_aes_0_iv_3. + 0x11C + + + se_aes_0_iv_3 + 0 + 31 + + + + + se_aes_0_key_0 + se_aes_0_key_0. + 0x120 + + + se_aes_0_key_0 + 0 + 31 + + + + + se_aes_0_key_1 + se_aes_0_key_1. + 0x124 + + + se_aes_0_key_1 + 0 + 31 + + + + + se_aes_0_key_2 + se_aes_0_key_2. + 0x128 + + + se_aes_0_key_2 + 0 + 31 + + + + + se_aes_0_key_3 + se_aes_0_key_3. + 0x12C + + + se_aes_0_key_3 + 0 + 31 + + + + + se_aes_0_key_4 + se_aes_0_key_4. + 0x130 + + + se_aes_0_key_4 + 0 + 31 + + + + + se_aes_0_key_5 + se_aes_0_key_5. + 0x134 + + + se_aes_0_key_5 + 0 + 31 + + + + + se_aes_0_key_6 + se_aes_0_key_6. + 0x138 + + + se_aes_0_key_6 + 0 + 31 + + + + + se_aes_0_key_7 + se_aes_0_key_7. + 0x13C + + + se_aes_0_key_7 + 0 + 31 + + + + + se_aes_0_key_sel_0 + se_aes_0_key_sel_0. + 0x140 + + + se_aes_0_key_sel_0 + 0 + 1 + + + + + se_aes_0_key_sel_1 + se_aes_0_key_sel_1. + 0x144 + + + se_aes_0_key_sel_1 + 0 + 1 + + + + + se_aes_0_endian + se_aes_0_endian. + 0x148 + + + se_aes_0_ctr_len + 30 + 31 + + + se_aes_0_iv_endian + 3 + 3 + + + se_aes_0_key_endian + 2 + 2 + + + se_aes_0_din_endian + 1 + 1 + + + se_aes_0_dout_endian + 0 + 0 + + + + + se_aes_0_sboot + se_aes_0_sboot. + 0x14C + + + se_aes_0_sboot_key_sel + 0 + 0 + + + + + se_aes_0_link + se_aes_0_link. + 0x150 + + + se_aes_0_lca + 0 + 31 + + + + + se_aes_0_ctrl_prot + se_aes_0_ctrl_prot. + 0x1FC + + + se_aes_id1_en + 2 + 2 + + + se_aes_id0_en + 1 + 1 + + + se_aes_prot_en + 0 + 0 + + + + + se_trng_0_ctrl_0 + se_trng_0_ctrl_0. + 0x200 + + + se_trng_0_manual_en + 15 + 15 + + + se_trng_0_manual_reseed + 14 + 14 + + + se_trng_0_manual_fun_sel + 13 + 13 + + + se_trng_0_int_mask + 11 + 11 + + + se_trng_0_int_set_1t + 10 + 10 + + + se_trng_0_int_clr_1t + 9 + 9 + + + se_trng_0_int + 8 + 8 + + + se_trng_0_ht_error + 4 + 4 + + + se_trng_0_dout_clr_1t + 3 + 3 + + + se_trng_0_en + 2 + 2 + + + se_trng_0_trig_1t + 1 + 1 + + + se_trng_0_busy + 0 + 0 + + + + + se_trng_0_status + se_trng_0_status. + 0x204 + + + se_trng_0_status + 0 + 31 + + + + + se_trng_0_dout_0 + se_trng_0_dout_0. + 0x208 + + + se_trng_0_dout_0 + 0 + 31 + + + + + se_trng_0_dout_1 + se_trng_0_dout_1. + 0x20C + + + se_trng_0_dout_1 + 0 + 31 + + + + + se_trng_0_dout_2 + se_trng_0_dout_2. + 0x210 + + + se_trng_0_dout_2 + 0 + 31 + + + + + se_trng_0_dout_3 + se_trng_0_dout_3. + 0x214 + + + se_trng_0_dout_3 + 0 + 31 + + + + + se_trng_0_dout_4 + se_trng_0_dout_4. + 0x218 + + + se_trng_0_dout_4 + 0 + 31 + + + + + se_trng_0_dout_5 + se_trng_0_dout_5. + 0x21C + + + se_trng_0_dout_5 + 0 + 31 + + + + + se_trng_0_dout_6 + se_trng_0_dout_6. + 0x220 + + + se_trng_0_dout_6 + 0 + 31 + + + + + se_trng_0_dout_7 + se_trng_0_dout_7. + 0x224 + + + se_trng_0_dout_7 + 0 + 31 + + + + + se_trng_0_test + se_trng_0_test. + 0x228 + + + se_trng_0_ht_alarm_n + 4 + 11 + + + se_trng_0_ht_dis + 3 + 3 + + + se_trng_0_cp_bypass + 2 + 2 + + + se_trng_0_cp_test_en + 1 + 1 + + + se_trng_0_test_en + 0 + 0 + + + + + se_trng_0_ctrl_1 + se_trng_0_ctrl_1. + 0x22C + + + se_trng_0_reseed_n_lsb + 0 + 31 + + + + + se_trng_0_ctrl_2 + se_trng_0_ctrl_2. + 0x230 + + + se_trng_0_reseed_n_msb + 0 + 15 + + + + + se_trng_0_ctrl_3 + se_trng_0_ctrl_3. + 0x234 + + + se_trng_0_rosc_en + 31 + 31 + + + se_trng_0_ht_od_en + 26 + 26 + + + se_trng_0_ht_apt_c + 16 + 25 + + + se_trng_0_ht_rct_c + 8 + 15 + + + se_trng_0_cp_ratio + 0 + 7 + + + + + se_trng_0_test_out_0 + se_trng_0_test_out_0. + 0x240 + + + se_trng_0_test_out_0 + 0 + 31 + + + + + se_trng_0_test_out_1 + se_trng_0_test_out_1. + 0x244 + + + se_trng_0_test_out_1 + 0 + 31 + + + + + se_trng_0_test_out_2 + se_trng_0_test_out_2. + 0x248 + + + se_trng_0_test_out_2 + 0 + 31 + + + + + se_trng_0_test_out_3 + se_trng_0_test_out_3. + 0x24C + + + se_trng_0_test_out_3 + 0 + 31 + + + + + se_trng_0_ctrl_prot + se_trng_0_ctrl_prot. + 0x2FC + + + se_trng_id1_en + 2 + 2 + + + se_trng_id0_en + 1 + 1 + + + se_trng_prot_en + 0 + 0 + + + + + se_pka_0_ctrl_0 + se_pka_0_ctrl_0. + 0x300 + + + se_pka_0_status + 17 + 31 + + + se_pka_0_status_clr_1t + 16 + 16 + + + se_pka_0_ram_clr_md + 13 + 13 + + + se_pka_0_endian + 12 + 12 + + + se_pka_0_int_mask + 11 + 11 + + + se_pka_0_int_set + 10 + 10 + + + se_pka_0_int_clr_1t + 9 + 9 + + + se_pka_0_int + 8 + 8 + + + se_pka_0_prot_md + 4 + 7 + + + se_pka_0_en + 3 + 3 + + + se_pka_0_busy + 2 + 2 + + + se_pka_0_done_clr_1t + 1 + 1 + + + se_pka_0_done + 0 + 0 + + + + + se_pka_0_seed + se_pka_0_seed. + 0x30C + + + se_pka_0_seed + 0 + 31 + + + + + se_pka_0_ctrl_1 + se_pka_0_ctrl_1. + 0x310 + + + se_pka_0_hbypass + 3 + 3 + + + se_pka_0_hburst + 0 + 2 + + + + + se_pka_0_rw + se_pka_0_rw. + 0x340 + + + + se_pka_0_rw_burst + se_pka_0_rw_burst. + 0x360 + + + + se_pka_0_ctrl_prot + se_pka_0_ctrl_prot. + 0x3FC + + + se_pka_id1_en + 2 + 2 + + + se_pka_id0_en + 1 + 1 + + + se_pka_prot_en + 0 + 0 + + + + + se_cdet_0_ctrl_0 + se_cdet_0_ctrl_0. + 0x400 + + + se_cdet_0_g_loop_min + 24 + 31 + + + se_cdet_0_g_loop_max + 16 + 23 + + + se_cdet_0_status + 2 + 15 + + + se_cdet_0_error + 1 + 1 + + + se_cdet_0_en + 0 + 0 + + + + + se_cdet_0_ctrl_1 + se_cdet_0_ctrl_1. + 0x404 + + + se_cdet_0_g_slp_n + 16 + 23 + + + se_cdet_0_t_dly_n + 8 + 15 + + + se_cdet_0_t_loop_n + 0 + 7 + + + + + se_cdet_0_ctrl_prot + se_cdet_0_ctrl_prot. + 0x4FC + + + se_cdet_id1_en + 2 + 2 + + + se_cdet_id0_en + 1 + 1 + + + se_cdet_prot_en + 0 + 0 + + + + + se_gmac_0_ctrl_0 + se_gmac_0_ctrl_0. + 0x500 + + + se_gmac_0_x_endian + 14 + 14 + + + se_gmac_0_h_endian + 13 + 13 + + + se_gmac_0_t_endian + 12 + 12 + + + se_gmac_0_int_mask + 11 + 11 + + + se_gmac_0_int_set_1t + 10 + 10 + + + se_gmac_0_int_clr_1t + 9 + 9 + + + se_gmac_0_int + 8 + 8 + + + se_gmac_0_en + 2 + 2 + + + se_gmac_0_trig_1t + 1 + 1 + + + se_gmac_0_busy + 0 + 0 + + + + + se_gmac_0_lca + se_gmac_0_lca. + 0x504 + + + se_gmac_0_lca + 0 + 31 + + + + + se_gmac_0_status + se_gmac_0_status. + 0x508 + + + se_gmac_0_status + 0 + 31 + + + + + se_gmac_0_ctrl_prot + se_gmac_0_ctrl_prot. + 0x5FC + + + se_gmac_id1_en + 2 + 2 + + + se_gmac_id0_en + 1 + 1 + + + se_gmac_prot_en + 0 + 0 + + + + + se_ctrl_prot_rd + se_ctrl_prot_rd. + 0xF00 + + + se_dbg_dis + 31 + 31 + + + se_gmac_id1_en_rd + 22 + 22 + + + se_gmac_id0_en_rd + 21 + 21 + + + se_gmac_prot_en_rd + 20 + 20 + + + se_cdet_id1_en_rd + 18 + 18 + + + se_cdet_id0_en_rd + 17 + 17 + + + se_cdet_prot_en_rd + 16 + 16 + + + se_pka_id1_en_rd + 14 + 14 + + + se_pka_id0_en_rd + 13 + 13 + + + se_pka_prot_en_rd + 12 + 12 + + + se_trng_id1_en_rd + 10 + 10 + + + se_trng_id0_en_rd + 9 + 9 + + + se_trng_prot_en_rd + 8 + 8 + + + se_aes_id1_en_rd + 6 + 6 + + + se_aes_id0_en_rd + 5 + 5 + + + se_aes_prot_en_rd + 4 + 4 + + + se_sha_id1_en_rd + 2 + 2 + + + se_sha_id0_en_rd + 1 + 1 + + + se_sha_prot_en_rd + 0 + 0 + + + + + se_ctrl_reserved_0 + se_ctrl_reserved_0. + 0xF04 + + + se_ctrl_reserved_0 + 0 + 31 + + + + + se_ctrl_reserved_1 + se_ctrl_reserved_1. + 0xF08 + + + se_ctrl_reserved_1 + 0 + 31 + + + + + se_ctrl_reserved_2 + se_ctrl_reserved_2. + 0xF0C + + + se_ctrl_reserved_2 + 0 + 31 + + + + + + + tzc_sec + tzc_sec. + 0x40005000 + tzc_sec + 32 + read-write + + 0 + 0x1000 + registers + + + + tzc_rom_ctrl + tzc_rom_ctrl. + 0x40 + + + tzc_sboot_done + 28 + 31 + + + tzc_rom1_r1_lock + 27 + 27 + + + tzc_rom1_r0_lock + 26 + 26 + + + tzc_rom0_r1_lock + 25 + 25 + + + tzc_rom0_r0_lock + 24 + 24 + + + tzc_rom1_r1_en + 19 + 19 + + + tzc_rom1_r0_en + 18 + 18 + + + tzc_rom0_r1_en + 17 + 17 + + + tzc_rom0_r0_en + 16 + 16 + + + tzc_rom1_r1_id1_en + 11 + 11 + + + tzc_rom1_r0_id1_en + 10 + 10 + + + tzc_rom0_r1_id1_en + 9 + 9 + + + tzc_rom0_r0_id1_en + 8 + 8 + + + tzc_rom1_r1_id0_en + 3 + 3 + + + tzc_rom1_r0_id0_en + 2 + 2 + + + tzc_rom0_r1_id0_en + 1 + 1 + + + tzc_rom0_r0_id0_en + 0 + 0 + + + + + tzc_rom0_r0 + tzc_rom0_r0. + 0x44 + + + tzc_rom0_r0_start + 16 + 31 + + + tzc_rom0_r0_end + 0 + 15 + + + + + tzc_rom0_r1 + tzc_rom0_r1. + 0x48 + + + tzc_rom0_r1_start + 16 + 31 + + + tzc_rom0_r1_end + 0 + 15 + + + + + tzc_rom1_r0 + tzc_rom1_r0. + 0x4C + + + tzc_rom1_r0_start + 16 + 31 + + + tzc_rom1_r0_end + 0 + 15 + + + + + tzc_rom1_r1 + tzc_rom1_r1. + 0x50 + + + tzc_rom1_r1_start + 16 + 31 + + + tzc_rom1_r1_end + 0 + 15 + + + + + + + tzc_nsec + tzc_nsec. + 0x40006000 + tzc_nsec + 32 + read-write + + 0 + 0x1000 + registers + + + + tzc_rom_ctrl + tzc_rom_ctrl. + 0x40 + + + tzc_sboot_done + 28 + 31 + + + tzc_rom1_r1_lock + 27 + 27 + + + tzc_rom1_r0_lock + 26 + 26 + + + tzc_rom0_r1_lock + 25 + 25 + + + tzc_rom0_r0_lock + 24 + 24 + + + tzc_rom1_r1_en + 19 + 19 + + + tzc_rom1_r0_en + 18 + 18 + + + tzc_rom0_r1_en + 17 + 17 + + + tzc_rom0_r0_en + 16 + 16 + + + tzc_rom1_r1_id1_en + 11 + 11 + + + tzc_rom1_r0_id1_en + 10 + 10 + + + tzc_rom0_r1_id1_en + 9 + 9 + + + tzc_rom0_r0_id1_en + 8 + 8 + + + tzc_rom1_r1_id0_en + 3 + 3 + + + tzc_rom1_r0_id0_en + 2 + 2 + + + tzc_rom0_r1_id0_en + 1 + 1 + + + tzc_rom0_r0_id0_en + 0 + 0 + + + + + tzc_rom0_r0 + tzc_rom0_r0. + 0x44 + + + tzc_rom0_r0_start + 16 + 31 + + + tzc_rom0_r0_end + 0 + 15 + + + + + tzc_rom0_r1 + tzc_rom0_r1. + 0x48 + + + tzc_rom0_r1_start + 16 + 31 + + + tzc_rom0_r1_end + 0 + 15 + + + + + tzc_rom1_r0 + tzc_rom1_r0. + 0x4C + + + tzc_rom1_r0_start + 16 + 31 + + + tzc_rom1_r0_end + 0 + 15 + + + + + tzc_rom1_r1 + tzc_rom1_r1. + 0x50 + + + tzc_rom1_r1_start + 16 + 31 + + + tzc_rom1_r1_end + 0 + 15 + + + + + + + ef_data_0 + ef_data_0. + 0x40007000 + ef_data_0 + 32 + read-write + + 0 + 0x1000 + registers + + + + ef_cfg_0 + ef_cfg_0. + 0x0 + + + ef_dbg_mode + 28 + 31 + + + ef_dbg_jtag_0_dis + 26 + 27 + + + ef_dbg_jtag_1_dis + 24 + 25 + + + ef_efuse_dbg_dis + 23 + 23 + + + ef_se_dbg_dis + 22 + 22 + + + ef_cpu_rst_dbg_dis + 21 + 21 + + + ef_cpu1_dis + 20 + 20 + + + ef_sf_dis + 19 + 19 + + + ef_cam_dis + 18 + 18 + + + ef_0_key_enc_en + 17 + 17 + + + ef_wifi_dis + 16 + 16 + + + ef_ble_dis + 15 + 15 + + + ef_sdu_dis + 14 + 14 + + + ef_sw_usage_1 + 12 + 13 + + + ef_boot_sel + 8 + 11 + + + ef_cpu0_enc_en + 7 + 7 + + + ef_cpu1_enc_en + 6 + 6 + + + ef_sboot_en + 4 + 5 + + + ef_sboot_sign_mode + 2 + 3 + + + ef_sf_aes_mode + 0 + 1 + + + + + ef_dbg_pwd_low + ef_dbg_pwd_low. + 0x4 + + + ef_dbg_pwd_low + 0 + 31 + + + + + ef_dbg_pwd_high + ef_dbg_pwd_high. + 0x8 + + + ef_dbg_pwd_high + 0 + 31 + + + + + ef_ana_trim_0 + ef_ana_trim_0. + 0xC + + + ef_ana_trim_0 + 0 + 31 + + + + + ef_sw_usage_0 + ef_sw_usage_0. + 0x10 + + + ef_sw_usage_0 + 0 + 31 + + + + + ef_wifi_mac_low + ef_wifi_mac_low. + 0x14 + + + ef_wifi_mac_low + 0 + 31 + + + + + ef_wifi_mac_high + ef_wifi_mac_high. + 0x18 + + + ef_wifi_mac_high + 0 + 31 + + + + + ef_key_slot_0_w0 + ef_key_slot_0_w0. + 0x1C + + + ef_key_slot_0_w0 + 0 + 31 + + + + + ef_key_slot_0_w1 + ef_key_slot_0_w1. + 0x20 + + + ef_key_slot_0_w1 + 0 + 31 + + + + + ef_key_slot_0_w2 + ef_key_slot_0_w2. + 0x24 + + + ef_key_slot_0_w2 + 0 + 31 + + + + + ef_key_slot_0_w3 + ef_key_slot_0_w3. + 0x28 + + + ef_key_slot_0_w3 + 0 + 31 + + + + + ef_key_slot_1_w0 + ef_key_slot_1_w0. + 0x2C + + + ef_key_slot_1_w0 + 0 + 31 + + + + + ef_key_slot_1_w1 + ef_key_slot_1_w1. + 0x30 + + + ef_key_slot_1_w1 + 0 + 31 + + + + + ef_key_slot_1_w2 + ef_key_slot_1_w2. + 0x34 + + + ef_key_slot_1_w2 + 0 + 31 + + + + + ef_key_slot_1_w3 + ef_key_slot_1_w3. + 0x38 + + + ef_key_slot_1_w3 + 0 + 31 + + + + + ef_key_slot_2_w0 + ef_key_slot_2_w0. + 0x3C + + + ef_key_slot_2_w0 + 0 + 31 + + + + + ef_key_slot_2_w1 + ef_key_slot_2_w1. + 0x40 + + + ef_key_slot_2_w1 + 0 + 31 + + + + + ef_key_slot_2_w2 + ef_key_slot_2_w2. + 0x44 + + + ef_key_slot_2_w2 + 0 + 31 + + + + + ef_key_slot_2_w3 + ef_key_slot_2_w3. + 0x48 + + + ef_key_slot_2_w3 + 0 + 31 + + + + + ef_key_slot_3_w0 + ef_key_slot_3_w0. + 0x4C + + + ef_key_slot_3_w0 + 0 + 31 + + + + + ef_key_slot_3_w1 + ef_key_slot_3_w1. + 0x50 + + + ef_key_slot_3_w1 + 0 + 31 + + + + + ef_key_slot_3_w2 + ef_key_slot_3_w2. + 0x54 + + + ef_key_slot_3_w2 + 0 + 31 + + + + + ef_key_slot_3_w3 + ef_key_slot_3_w3. + 0x58 + + + ef_key_slot_3_w3 + 0 + 31 + + + + + ef_key_slot_4_w0 + ef_key_slot_4_w0. + 0x5C + + + ef_key_slot_4_w0 + 0 + 31 + + + + + ef_key_slot_4_w1 + ef_key_slot_4_w1. + 0x60 + + + ef_key_slot_4_w1 + 0 + 31 + + + + + ef_key_slot_4_w2 + ef_key_slot_4_w2. + 0x64 + + + ef_key_slot_4_w2 + 0 + 31 + + + + + ef_key_slot_4_w3 + ef_key_slot_4_w3. + 0x68 + + + ef_key_slot_4_w3 + 0 + 31 + + + + + ef_key_slot_5_w0 + ef_key_slot_5_w0. + 0x6C + + + ef_key_slot_5_w0 + 0 + 31 + + + + + ef_key_slot_5_w1 + ef_key_slot_5_w1. + 0x70 + + + ef_key_slot_5_w1 + 0 + 31 + + + + + ef_key_slot_5_w2 + ef_key_slot_5_w2. + 0x74 + + + ef_key_slot_5_w2 + 0 + 31 + + + + + ef_key_slot_5_w3 + ef_key_slot_5_w3. + 0x78 + + + ef_key_slot_5_w3 + 0 + 31 + + + + + ef_data_0_lock + ef_data_0_lock. + 0x7C + + + rd_lock_key_slot_5 + 31 + 31 + + + rd_lock_key_slot_4 + 30 + 30 + + + rd_lock_key_slot_3 + 29 + 29 + + + rd_lock_key_slot_2 + 28 + 28 + + + rd_lock_key_slot_1 + 27 + 27 + + + rd_lock_key_slot_0 + 26 + 26 + + + rd_lock_dbg_pwd + 25 + 25 + + + wr_lock_key_slot_5_h + 24 + 24 + + + wr_lock_key_slot_4_h + 23 + 23 + + + wr_lock_key_slot_3 + 22 + 22 + + + wr_lock_key_slot_2 + 21 + 21 + + + wr_lock_key_slot_1 + 20 + 20 + + + wr_lock_key_slot_0 + 19 + 19 + + + wr_lock_wifi_mac + 18 + 18 + + + wr_lock_sw_usage_0 + 17 + 17 + + + wr_lock_dbg_pwd + 16 + 16 + + + wr_lock_boot_mode + 15 + 15 + + + wr_lock_key_slot_5_l + 14 + 14 + + + wr_lock_key_slot_4_l + 13 + 13 + + + ef_ana_trim_1 + 0 + 12 + + + + + + + ef_data_1 + ef_data_1. + 0x40007000 + ef_data_1 + 32 + read-write + + 0 + 0x1000 + registers + + + + reg_key_slot_6_w0 + reg_key_slot_6_w0. + 0x80 + + + reg_key_slot_6_w0 + 0 + 31 + + + + + reg_key_slot_6_w1 + reg_key_slot_6_w1. + 0x84 + + + reg_key_slot_6_w1 + 0 + 31 + + + + + reg_key_slot_6_w2 + reg_key_slot_6_w2. + 0x88 + + + reg_key_slot_6_w2 + 0 + 31 + + + + + reg_key_slot_6_w3 + reg_key_slot_6_w3. + 0x8C + + + reg_key_slot_6_w3 + 0 + 31 + + + + + reg_key_slot_7_w0 + reg_key_slot_7_w0. + 0x90 + + + reg_key_slot_7_w0 + 0 + 31 + + + + + reg_key_slot_7_w1 + reg_key_slot_7_w1. + 0x94 + + + reg_key_slot_7_w1 + 0 + 31 + + + + + reg_key_slot_7_w2 + reg_key_slot_7_w2. + 0x98 + + + reg_key_slot_7_w2 + 0 + 31 + + + + + reg_key_slot_7_w3 + reg_key_slot_7_w3. + 0x9C + + + reg_key_slot_7_w3 + 0 + 31 + + + + + reg_key_slot_8_w0 + reg_key_slot_8_w0. + 0xA0 + + + reg_key_slot_8_w0 + 0 + 31 + + + + + reg_key_slot_8_w1 + reg_key_slot_8_w1. + 0xA4 + + + reg_key_slot_8_w1 + 0 + 31 + + + + + reg_key_slot_8_w2 + reg_key_slot_8_w2. + 0xA8 + + + reg_key_slot_8_w2 + 0 + 31 + + + + + reg_key_slot_8_w3 + reg_key_slot_8_w3. + 0xAC + + + reg_key_slot_8_w3 + 0 + 31 + + + + + reg_key_slot_9_w0 + reg_key_slot_9_w0. + 0xB0 + + + reg_key_slot_9_w0 + 0 + 31 + + + + + reg_key_slot_9_w1 + reg_key_slot_9_w1. + 0xB4 + + + reg_key_slot_9_w1 + 0 + 31 + + + + + reg_key_slot_9_w2 + reg_key_slot_9_w2. + 0xB8 + + + reg_key_slot_9_w2 + 0 + 31 + + + + + reg_key_slot_9_w3 + reg_key_slot_9_w3. + 0xBC + + + reg_key_slot_9_w3 + 0 + 31 + + + + + reg_key_slot_10_w0 + reg_key_slot_10_w0. + 0xC0 + + + + reg_key_slot_10_w1 + reg_key_slot_10_w1. + 0xC4 + + + + reg_key_slot_10_w2 + reg_key_slot_10_w2. + 0xC8 + + + + reg_key_slot_10_w3 + reg_key_slot_10_w3. + 0xCC + + + + reg_key_slot_11_w0 + reg_key_slot_11_w0. + 0xD0 + + + + reg_key_slot_11_w1 + reg_key_slot_11_w1. + 0xD4 + + + + reg_key_slot_11_w2 + reg_key_slot_11_w2. + 0xD8 + + + + reg_key_slot_11_w3 + reg_key_slot_11_w3. + 0xDC + + + + reg_data_1_lock + reg_data_1_lock. + 0xE0 + + + rd_lock_key_slot_9 + 29 + 29 + + + rd_lock_key_slot_8 + 28 + 28 + + + rd_lock_key_slot_7 + 27 + 27 + + + rd_lock_key_slot_6 + 26 + 26 + + + RESERVED_25_16 + 16 + 25 + + + wr_lock_key_slot_9 + 13 + 13 + + + wr_lock_key_slot_8 + 12 + 12 + + + wr_lock_key_slot_7 + 11 + 11 + + + wr_lock_key_slot_6 + 10 + 10 + + + RESERVED_9_0 + 0 + 9 + + + + + + + ef_ctrl + ef_ctrl. + 0x40007000 + ef_ctrl + 32 + read-write + + 0 + 0x1000 + registers + + + + ef_if_ctrl_0 + ef_if_ctrl_0. + 0x800 + + + ef_if_prot_code_cyc + 24 + 31 + + + ef_if_0_int_set + 22 + 22 + + + ef_if_0_int_clr + 21 + 21 + + + ef_if_0_int + 20 + 20 + + + ef_if_cyc_modify_lock + 19 + 19 + + + ef_if_auto_rd_en + 18 + 18 + + + ef_clk_sahb_data_gate + 17 + 17 + + + ef_if_por_dig + 16 + 16 + + + ef_if_prot_code_ctrl + 8 + 15 + + + ef_clk_sahb_data_sel + 7 + 7 + + + ef_if_0_cyc_modify + 6 + 6 + + + ef_if_0_manual_en + 5 + 5 + + + ef_if_0_trig + 4 + 4 + + + ef_if_0_rw + 3 + 3 + + + ef_if_0_busy + 2 + 2 + + + ef_if_0_autoload_done + 1 + 1 + + + ef_if_0_autoload_p1_done + 0 + 0 + + + + + ef_if_cyc_0 + ef_if_cyc_0. + 0x804 + + + ef_if_cyc_pd_cs_s + 24 + 31 + + + ef_if_cyc_cs + 18 + 23 + + + ef_if_cyc_rd_adr + 12 + 17 + + + ef_if_cyc_rd_dat + 6 + 11 + + + ef_if_cyc_rd_dmy + 0 + 5 + + + + + ef_if_cyc_1 + ef_if_cyc_1. + 0x808 + + + ef_if_cyc_pd_cs_h + 26 + 31 + + + ef_if_cyc_ps_cs + 20 + 25 + + + ef_if_cyc_wr_adr + 14 + 19 + + + ef_if_cyc_pp + 6 + 13 + + + ef_if_cyc_pi + 0 + 5 + + + + + ef_if_0_manual + ef_if_0_manual. + 0x80C + + + ef_if_prot_code_manual + 24 + 31 + + + ef_if_0_q + 16 + 23 + + + ef_if_csb + 15 + 15 + + + ef_if_load + 14 + 14 + + + ef_if_pgenb + 13 + 13 + + + ef_if_strobe + 12 + 12 + + + ef_if_ps + 11 + 11 + + + ef_if_pd + 10 + 10 + + + ef_if_a + 0 + 9 + + + + + ef_if_0_status + ef_if_0_status. + 0x810 + + + ef_if_0_status + 0 + 31 + + + + + ef_if_cfg_0 + ef_if_cfg_0. + 0x814 + + + ef_if_dbg_mode + 28 + 31 + + + ef_if_dbg_jtag_0_dis + 26 + 27 + + + ef_if_dbg_jtag_1_dis + 24 + 25 + + + ef_if_efuse_dbg_dis + 23 + 23 + + + ef_if_se_dbg_dis + 22 + 22 + + + ef_if_cpu_rst_dbg_dis + 21 + 21 + + + ef_if_cpu1_dis + 20 + 20 + + + ef_if_sf_dis + 19 + 19 + + + ef_if_cam_dis + 18 + 18 + + + ef_if_0_key_enc_en + 17 + 17 + + + ef_if_wifi_dis + 16 + 16 + + + ef_if_ble_dis + 15 + 15 + + + ef_if_sdu_dis + 14 + 14 + + + ef_if_sw_usage_1 + 12 + 13 + + + ef_if_boot_sel + 8 + 11 + + + ef_if_cpu0_enc_en + 7 + 7 + + + ef_if_cpu1_enc_en + 6 + 6 + + + ef_if_sboot_en + 4 + 5 + + + ef_if_sboot_sign_mode + 2 + 3 + + + ef_if_sf_aes_mode + 0 + 1 + + + + + ef_sw_cfg_0 + ef_sw_cfg_0. + 0x818 + + + ef_sw_dbg_mode + 28 + 31 + + + ef_sw_dbg_jtag_0_dis + 26 + 27 + + + ef_sw_dbg_jtag_1_dis + 24 + 25 + + + ef_sw_efuse_dbg_dis + 23 + 23 + + + ef_sw_se_dbg_dis + 22 + 22 + + + ef_sw_cpu_rst_dbg_dis + 21 + 21 + + + ef_sw_cpu1_dis + 20 + 20 + + + ef_sw_sf_dis + 19 + 19 + + + ef_sw_cam_dis + 18 + 18 + + + ef_sw_0_key_enc_en + 17 + 17 + + + ef_sw_wifi_dis + 16 + 16 + + + ef_sw_ble_dis + 15 + 15 + + + ef_sw_sdu_dis + 14 + 14 + + + ef_sw_sw_usage_1 + 12 + 13 + + + ef_sw_cpu0_enc_en + 7 + 7 + + + ef_sw_cpu1_enc_en + 6 + 6 + + + ef_sw_sboot_en + 4 + 5 + + + ef_sw_sboot_sign_mode + 2 + 3 + + + ef_sw_sf_aes_mode + 0 + 1 + + + + + ef_reserved + ef_reserved. + 0x81C + + + ef_reserved + 0 + 31 + + + + + ef_if_ana_trim_0 + ef_if_ana_trim_0. + 0x820 + + + ef_if_ana_trim_0 + 0 + 31 + + + + + ef_if_sw_usage_0 + ef_if_sw_usage_0. + 0x824 + + + ef_if_sw_usage_0 + 0 + 31 + + + + + ef_crc_ctrl_0 + ef_crc_ctrl_0. + 0xA00 + + + ef_crc_slp_n + 16 + 31 + + + ef_crc_lock + 11 + 11 + + + ef_crc_int_set + 10 + 10 + + + ef_crc_int_clr + 9 + 9 + + + ef_crc_int + 8 + 8 + + + ef_crc_din_endian + 7 + 7 + + + ef_crc_dout_endian + 6 + 6 + + + ef_crc_dout_inv_en + 5 + 5 + + + ef_crc_error + 4 + 4 + + + ef_crc_mode + 3 + 3 + + + ef_crc_en + 2 + 2 + + + ef_crc_trig + 1 + 1 + + + ef_crc_busy + 0 + 0 + + + + + ef_crc_ctrl_1 + ef_crc_ctrl_1. + 0xA04 + + + ef_crc_data_0_en + 0 + 31 + + + + + ef_crc_ctrl_2 + ef_crc_ctrl_2. + 0xA08 + + + ef_crc_data_1_en + 0 + 31 + + + + + ef_crc_ctrl_3 + ef_crc_ctrl_3. + 0xA0C + + + ef_crc_iv + 0 + 31 + + + + + ef_crc_ctrl_4 + ef_crc_ctrl_4. + 0xA10 + + + ef_crc_golden + 0 + 31 + + + + + ef_crc_ctrl_5 + ef_crc_ctrl_5. + 0xA14 + + + ef_crc_dout + 0 + 31 + + + + + + + cci + cci. + 0x40008000 + cci + 32 + read-write + + 0 + 0x1000 + registers + + + + cci_cfg + cci_cfg. + 0x0 + + + reg_mcci_clk_inv + 9 + 9 + + + reg_scci_clk_inv + 8 + 8 + + + cfg_cci1_pre_read + 7 + 7 + + + reg_div_m_cci_sclk + 5 + 6 + + + reg_m_cci_sclk_en + 4 + 4 + + + cci_mas_hw_mode + 3 + 3 + + + cci_mas_sel_cci2 + 2 + 2 + + + cci_slv_sel_cci2 + 1 + 1 + + + cci_en + 0 + 0 + + + + + cci_addr + cci_addr. + 0x4 + + + apb_cci_addr + 0 + 31 + + + + + cci_wdata + cci_wdata. + 0x8 + + + apb_cci_wdata + 0 + 31 + + + + + cci_rdata + cci_rdata. + 0xC + + + apb_cci_rdata + 0 + 31 + + + + + cci_ctl + cci_ctl. + 0x10 + + + ahb_state + 2 + 3 + + + cci_read_flag + 1 + 1 + + + cci_write_flag + 0 + 0 + + + + + + + l1c + l1c. + 0x40009000 + l1c + 32 + read-write + + 0 + 0x1000 + registers + + + + l1c_config + l1c_config. + 0x0 + + + wrap_dis + 26 + 26 + + + early_resp_dis + 25 + 25 + + + l1c_bmx_busy_option_dis + 24 + 24 + + + l1c_bmx_timeout_en + 20 + 23 + + + l1c_bmx_arb_mode + 16 + 17 + + + l1c_bmx_err_en + 15 + 15 + + + l1c_bypass + 14 + 14 + + + irom_2t_access + 12 + 12 + + + l1c_way_dis + 8 + 11 + + + l1c_invalid_done + 3 + 3 + + + l1c_invalid_en + 2 + 2 + + + l1c_cnt_en + 1 + 1 + + + l1c_cacheable + 0 + 0 + + + + + hit_cnt_lsb + hit_cnt_lsb. + 0x4 + + + hit_cnt_lsb + 0 + 31 + + + + + hit_cnt_msb + hit_cnt_msb. + 0x8 + + + hit_cnt_msb + 0 + 31 + + + + + miss_cnt + miss_cnt. + 0xC + + + miss_cnt + 0 + 31 + + + + + l1c_range + l1c_range. + 0x10 + + + + l1c_bmx_err_addr_en + l1c_bmx_err_addr_en. + 0x200 + + + l1c_hsel_option + 16 + 19 + + + l1c_bmx_err_tz + 5 + 5 + + + l1c_bmx_err_dec + 4 + 4 + + + l1c_bmx_err_addr_dis + 0 + 0 + + + + + l1c_bmx_err_addr + l1c_bmx_err_addr. + 0x204 + + + l1c_bmx_err_addr + 0 + 31 + + + + + irom1_misr_dataout_0 + irom1_misr_dataout_0. + 0x208 + + + irom1_misr_dataout_0 + 0 + 31 + + + + + irom1_misr_dataout_1 + irom1_misr_dataout_1. + 0x20C + + + + cpu_clk_gate + cpu_clk_gate. + 0x210 + + + force_e21_clock_on_2 + 2 + 2 + + + force_e21_clock_on_1 + 1 + 1 + + + force_e21_clock_on_0 + 0 + 0 + + + + + + + uart + uart. + 0x4000A000 + uart + 32 + read-write + + 0 + 0x1000 + registers + + + + utx_config + utx_config. + 0x0 + + + cr_utx_len + 16 + 31 + + + cr_utx_bit_cnt_p + 12 + 13 + + + cr_utx_bit_cnt_d + 8 + 10 + + + cr_utx_ir_inv + 7 + 7 + + + cr_utx_ir_en + 6 + 6 + + + cr_utx_prt_sel + 5 + 5 + + + cr_utx_prt_en + 4 + 4 + + + cr_utx_frm_en + 2 + 2 + + + cr_utx_cts_en + 1 + 1 + + + cr_utx_en + 0 + 0 + + + + + urx_config + urx_config. + 0x4 + + + cr_urx_len + 16 + 31 + + + cr_urx_deg_cnt + 12 + 15 + + + cr_urx_deg_en + 11 + 11 + + + cr_urx_bit_cnt_d + 8 + 10 + + + cr_urx_ir_inv + 7 + 7 + + + cr_urx_ir_en + 6 + 6 + + + cr_urx_prt_sel + 5 + 5 + + + cr_urx_prt_en + 4 + 4 + + + cr_urx_abr_en + 3 + 3 + + + cr_urx_rts_sw_val + 2 + 2 + + + cr_urx_rts_sw_mode + 1 + 1 + + + cr_urx_en + 0 + 0 + + + + + uart_bit_prd + uart_bit_prd. + 0x8 + + + cr_urx_bit_prd + 16 + 31 + + + cr_utx_bit_prd + 0 + 15 + + + + + data_config + data_config. + 0xC + + + cr_uart_bit_inv + 0 + 0 + + + + + utx_ir_position + utx_ir_position. + 0x10 + + + cr_utx_ir_pos_p + 16 + 31 + + + cr_utx_ir_pos_s + 0 + 15 + + + + + urx_ir_position + urx_ir_position. + 0x14 + + + cr_urx_ir_pos_s + 0 + 15 + + + + + urx_rto_timer + urx_rto_timer. + 0x18 + + + cr_urx_rto_value + 0 + 7 + + + + + uart_int_sts + UART interrupt status + 0x20 + + + urx_fer_int + 7 + 7 + + + utx_fer_int + 6 + 6 + + + urx_pce_int + 5 + 5 + + + urx_rto_int + 4 + 4 + + + urx_fifo_int + 3 + 3 + + + utx_fifo_int + 2 + 2 + + + urx_end_int + 1 + 1 + + + utx_end_int + 0 + 0 + + + + + uart_int_mask + UART interrupt mask + 0x24 + + + cr_urx_fer_mask + 7 + 7 + + + cr_utx_fer_mask + 6 + 6 + + + cr_urx_pce_mask + 5 + 5 + + + cr_urx_rto_mask + 4 + 4 + + + cr_urx_fifo_mask + 3 + 3 + + + cr_utx_fifo_mask + 2 + 2 + + + cr_urx_end_mask + 1 + 1 + + + cr_utx_end_mask + 0 + 0 + + + + + uart_int_clear + UART interrupt clear + 0x28 + + + rsvd_7 + 7 + 7 + + + rsvd_6 + 6 + 6 + + + cr_urx_pce_clr + 5 + 5 + + + cr_urx_rto_clr + 4 + 4 + + + rsvd_3 + 3 + 3 + + + rsvd_2 + 2 + 2 + + + cr_urx_end_clr + 1 + 1 + + + cr_utx_end_clr + 0 + 0 + + + + + uart_int_en + UART interrupt enable + 0x2C + + + cr_urx_fer_en + 7 + 7 + + + cr_utx_fer_en + 6 + 6 + + + cr_urx_pce_en + 5 + 5 + + + cr_urx_rto_en + 4 + 4 + + + cr_urx_fifo_en + 3 + 3 + + + cr_utx_fifo_en + 2 + 2 + + + cr_urx_end_en + 1 + 1 + + + cr_utx_end_en + 0 + 0 + + + + + uart_status + uart_status. + 0x30 + + + sts_urx_bus_busy + 1 + 1 + + + sts_utx_bus_busy + 0 + 0 + + + + + sts_urx_abr_prd + sts_urx_abr_prd. + 0x34 + + + sts_urx_abr_prd_0x55 + 16 + 31 + + + sts_urx_abr_prd_start + 0 + 15 + + + + + uart_fifo_config_0 + uart_fifo_config_0. + 0x80 + + + rx_fifo_underflow + 7 + 7 + + + rx_fifo_overflow + 6 + 6 + + + tx_fifo_underflow + 5 + 5 + + + tx_fifo_overflow + 4 + 4 + + + rx_fifo_clr + 3 + 3 + + + tx_fifo_clr + 2 + 2 + + + uart_dma_rx_en + 1 + 1 + + + uart_dma_tx_en + 0 + 0 + + + + + uart_fifo_config_1 + uart_fifo_config_1. + 0x84 + + + rx_fifo_th + 24 + 28 + + + tx_fifo_th + 16 + 20 + + + rx_fifo_cnt + 8 + 13 + + + tx_fifo_cnt + 0 + 5 + + + + + uart_fifo_wdata + uart_fifo_wdata. + 0x88 + + + uart_fifo_wdata + 0 + 7 + + + + + uart_fifo_rdata + uart_fifo_rdata. + 0x8C + + + uart_fifo_rdata + 0 + 7 + + + + + + + spi + spi. + 0x4000A200 + spi + 32 + read-write + + 0 + 0x1000 + registers + + + + spi_config + spi_config. + 0x0 + + + cr_spi_deg_cnt + 12 + 15 + + + cr_spi_deg_en + 11 + 11 + + + cr_spi_m_cont_en + 9 + 9 + + + cr_spi_rxd_ignr_en + 8 + 8 + + + cr_spi_byte_inv + 7 + 7 + + + cr_spi_bit_inv + 6 + 6 + + + cr_spi_sclk_ph + 5 + 5 + + + cr_spi_sclk_pol + 4 + 4 + + + cr_spi_frame_size + 2 + 3 + + + cr_spi_s_en + 1 + 1 + + + cr_spi_m_en + 0 + 0 + + + + + spi_int_sts + spi_int_sts. + 0x4 + + + cr_spi_fer_en + 29 + 29 + + + cr_spi_txu_en + 28 + 28 + + + cr_spi_sto_en + 27 + 27 + + + cr_spi_rxf_en + 26 + 26 + + + cr_spi_txf_en + 25 + 25 + + + cr_spi_end_en + 24 + 24 + + + rsvd_21 + 21 + 21 + + + cr_spi_txu_clr + 20 + 20 + + + cr_spi_sto_clr + 19 + 19 + + + rsvd_18 + 18 + 18 + + + rsvd_17 + 17 + 17 + + + cr_spi_end_clr + 16 + 16 + + + cr_spi_fer_mask + 13 + 13 + + + cr_spi_txu_mask + 12 + 12 + + + cr_spi_sto_mask + 11 + 11 + + + cr_spi_rxf_mask + 10 + 10 + + + cr_spi_txf_mask + 9 + 9 + + + cr_spi_end_mask + 8 + 8 + + + spi_fer_int + 5 + 5 + + + spi_txu_int + 4 + 4 + + + spi_sto_int + 3 + 3 + + + spi_rxf_int + 2 + 2 + + + spi_txf_int + 1 + 1 + + + spi_end_int + 0 + 0 + + + + + spi_bus_busy + spi_bus_busy. + 0x8 + + + sts_spi_bus_busy + 0 + 0 + + + + + spi_prd_0 + spi_prd_0. + 0x10 + + + cr_spi_prd_d_ph_1 + 24 + 31 + + + cr_spi_prd_d_ph_0 + 16 + 23 + + + cr_spi_prd_p + 8 + 15 + + + cr_spi_prd_s + 0 + 7 + + + + + spi_prd_1 + spi_prd_1. + 0x14 + + + cr_spi_prd_i + 0 + 7 + + + + + spi_rxd_ignr + spi_rxd_ignr. + 0x18 + + + cr_spi_rxd_ignr_s + 16 + 20 + + + cr_spi_rxd_ignr_p + 0 + 4 + + + + + spi_sto_value + spi_sto_value. + 0x1C + + + cr_spi_sto_value + 0 + 11 + + + + + spi_fifo_config_0 + spi_fifo_config_0. + 0x80 + + + rx_fifo_underflow + 7 + 7 + + + rx_fifo_overflow + 6 + 6 + + + tx_fifo_underflow + 5 + 5 + + + tx_fifo_overflow + 4 + 4 + + + rx_fifo_clr + 3 + 3 + + + tx_fifo_clr + 2 + 2 + + + spi_dma_rx_en + 1 + 1 + + + spi_dma_tx_en + 0 + 0 + + + + + spi_fifo_config_1 + spi_fifo_config_1. + 0x84 + + + rx_fifo_th + 24 + 25 + + + tx_fifo_th + 16 + 17 + + + rx_fifo_cnt + 8 + 10 + + + tx_fifo_cnt + 0 + 2 + + + + + spi_fifo_wdata + spi_fifo_wdata. + 0x88 + + + spi_fifo_wdata + 0 + 31 + + + + + spi_fifo_rdata + spi_fifo_rdata. + 0x8C + + + spi_fifo_rdata + 0 + 31 + + + + + + + i2c + i2c. + 0x4000A300 + i2c + 32 + read-write + + 0 + 0x1000 + registers + + + + i2c_config + i2c_config. + 0x0 + + + cr_i2c_deg_cnt + 28 + 31 + + + cr_i2c_pkt_len + 16 + 23 + + + cr_i2c_slv_addr + 8 + 14 + + + cr_i2c_sub_addr_bc + 5 + 6 + + + cr_i2c_sub_addr_en + 4 + 4 + + + cr_i2c_scl_sync_en + 3 + 3 + + + cr_i2c_deg_en + 2 + 2 + + + cr_i2c_pkt_dir + 1 + 1 + + + cr_i2c_m_en + 0 + 0 + + + + + i2c_int_sts + i2c_int_sts. + 0x4 + + + cr_i2c_fer_en + 29 + 29 + + + cr_i2c_arb_en + 28 + 28 + + + cr_i2c_nak_en + 27 + 27 + + + cr_i2c_rxf_en + 26 + 26 + + + cr_i2c_txf_en + 25 + 25 + + + cr_i2c_end_en + 24 + 24 + + + rsvd_21 + 21 + 21 + + + cr_i2c_arb_clr + 20 + 20 + + + cr_i2c_nak_clr + 19 + 19 + + + rsvd_18 + 18 + 18 + + + rsvd_17 + 17 + 17 + + + cr_i2c_end_clr + 16 + 16 + + + cr_i2c_fer_mask + 13 + 13 + + + cr_i2c_arb_mask + 12 + 12 + + + cr_i2c_nak_mask + 11 + 11 + + + cr_i2c_rxf_mask + 10 + 10 + + + cr_i2c_txf_mask + 9 + 9 + + + cr_i2c_end_mask + 8 + 8 + + + i2c_fer_int + 5 + 5 + + + i2c_arb_int + 4 + 4 + + + i2c_nak_int + 3 + 3 + + + i2c_rxf_int + 2 + 2 + + + i2c_txf_int + 1 + 1 + + + i2c_end_int + 0 + 0 + + + + + i2c_sub_addr + i2c_sub_addr. + 0x8 + + + cr_i2c_sub_addr_b3 + 24 + 31 + + + cr_i2c_sub_addr_b2 + 16 + 23 + + + cr_i2c_sub_addr_b1 + 8 + 15 + + + cr_i2c_sub_addr_b0 + 0 + 7 + + + + + i2c_bus_busy + i2c_bus_busy. + 0xC + + + cr_i2c_bus_busy_clr + 1 + 1 + + + sts_i2c_bus_busy + 0 + 0 + + + + + i2c_prd_start + i2c_prd_start. + 0x10 + + + cr_i2c_prd_s_ph_3 + 24 + 31 + + + cr_i2c_prd_s_ph_2 + 16 + 23 + + + cr_i2c_prd_s_ph_1 + 8 + 15 + + + cr_i2c_prd_s_ph_0 + 0 + 7 + + + + + i2c_prd_stop + i2c_prd_stop. + 0x14 + + + cr_i2c_prd_p_ph_3 + 24 + 31 + + + cr_i2c_prd_p_ph_2 + 16 + 23 + + + cr_i2c_prd_p_ph_1 + 8 + 15 + + + cr_i2c_prd_p_ph_0 + 0 + 7 + + + + + i2c_prd_data + i2c_prd_data. + 0x18 + + + cr_i2c_prd_d_ph_3 + 24 + 31 + + + cr_i2c_prd_d_ph_2 + 16 + 23 + + + cr_i2c_prd_d_ph_1 + 8 + 15 + + + cr_i2c_prd_d_ph_0 + 0 + 7 + + + + + i2c_fifo_config_0 + i2c_fifo_config_0. + 0x80 + + + rx_fifo_underflow + 7 + 7 + + + rx_fifo_overflow + 6 + 6 + + + tx_fifo_underflow + 5 + 5 + + + tx_fifo_overflow + 4 + 4 + + + rx_fifo_clr + 3 + 3 + + + tx_fifo_clr + 2 + 2 + + + i2c_dma_rx_en + 1 + 1 + + + i2c_dma_tx_en + 0 + 0 + + + + + i2c_fifo_config_1 + i2c_fifo_config_1. + 0x84 + + + rx_fifo_th + 24 + 24 + + + tx_fifo_th + 16 + 16 + + + rx_fifo_cnt + 8 + 9 + + + tx_fifo_cnt + 0 + 1 + + + + + i2c_fifo_wdata + i2c_fifo_wdata. + 0x88 + + + i2c_fifo_wdata + 0 + 31 + + + + + i2c_fifo_rdata + i2c_fifo_rdata. + 0x8C + + + i2c_fifo_rdata + 0 + 31 + + + + + + + pwm + pwm. + 0x4000A400 + pwm + 32 + read-write + + 0 + 0x1000 + registers + + + + pwm_int_config + pwm_int_config. + 0x0 + + + pwm_int_clear + 8 + 13 + + + pwm_interrupt_sts + 0 + 5 + + + + + pwm0_clkdiv + pwm0_clkdiv. + 0x20 + + + pwm_clk_div + 0 + 15 + + + + + pwm0_thre1 + pwm0_thre1. + 0x24 + + + pwm_thre1 + 0 + 15 + + + + + pwm0_thre2 + pwm0_thre2. + 0x28 + + + pwm_thre2 + 0 + 15 + + + + + pwm0_period + pwm0_period. + 0x2C + + + pwm_period + 0 + 15 + + + + + pwm0_config + pwm0_config. + 0x30 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm0_interrupt + pwm0_interrupt. + 0x34 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + pwm1_clkdiv + pwm1_clkdiv. + 0x40 + + + pwm_clk_div + 0 + 15 + + + + + pwm1_thre1 + pwm1_thre1. + 0x44 + + + pwm_thre1 + 0 + 15 + + + + + pwm1_thre2 + pwm1_thre2. + 0x48 + + + pwm_thre2 + 0 + 15 + + + + + pwm1_period + pwm1_period. + 0x4C + + + pwm_period + 0 + 15 + + + + + pwm1_config + pwm1_config. + 0x50 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm1_interrupt + pwm1_interrupt. + 0x54 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + pwm2_clkdiv + pwm2_clkdiv. + 0x60 + + + pwm_clk_div + 0 + 15 + + + + + pwm2_thre1 + pwm2_thre1. + 0x64 + + + pwm_thre1 + 0 + 15 + + + + + pwm2_thre2 + pwm2_thre2. + 0x68 + + + pwm_thre2 + 0 + 15 + + + + + pwm2_period + pwm2_period. + 0x6C + + + pwm_period + 0 + 15 + + + + + pwm2_config + pwm2_config. + 0x70 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm2_interrupt + pwm2_interrupt. + 0x74 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + pwm3_clkdiv + pwm3_clkdiv. + 0x80 + + + pwm_clk_div + 0 + 15 + + + + + pwm3_thre1 + pwm3_thre1. + 0x84 + + + pwm_thre1 + 0 + 15 + + + + + pwm3_thre2 + pwm3_thre2. + 0x88 + + + pwm_thre2 + 0 + 15 + + + + + pwm3_period + pwm3_period. + 0x8C + + + pwm_period + 0 + 15 + + + + + pwm3_config + pwm3_config. + 0x90 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm3_interrupt + pwm3_interrupt. + 0x94 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + pwm4_clkdiv + pwm4_clkdiv. + 0xA0 + + + pwm_clk_div + 0 + 15 + + + + + pwm4_thre1 + pwm4_thre1. + 0xA4 + + + pwm_thre1 + 0 + 15 + + + + + pwm4_thre2 + pwm4_thre2. + 0xA8 + + + pwm_thre2 + 0 + 15 + + + + + pwm4_period + pwm4_period. + 0xAC + + + pwm_period + 0 + 15 + + + + + pwm4_config + pwm4_config. + 0xB0 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm4_interrupt + pwm4_interrupt. + 0xB4 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + + + timer + timer. + 0x4000A500 + timer + 32 + read-write + + 0 + 0x1000 + registers + + + + TCCR + TCCR. + 0x0 + + + cs_wdt + 8 + 9 + + + RESERVED_7 + 7 + 7 + + + cs_2 + 5 + 6 + + + RESERVED_4 + 4 + 4 + + + cs_1 + 2 + 3 + + + + + TMR2_0 + TMR2_0. + 0x10 + + + tmr + 0 + 31 + + + + + TMR2_1 + TMR2_1. + 0x14 + + + tmr + 0 + 31 + + + + + TMR2_2 + TMR2_2. + 0x18 + + + tmr + 0 + 31 + + + + + TMR3_0 + TMR3_0. + 0x1C + + + tmr + 0 + 31 + + + + + TMR3_1 + TMR3_1. + 0x20 + + + tmr + 0 + 31 + + + + + TMR3_2 + TMR3_2. + 0x24 + + + tmr + 0 + 31 + + + + + TCR2 + TCR2. + 0x2C + + + tcr + 0 + 31 + + + + + TCR3 + TCR3. + 0x30 + + + tcr3_counter + 0 + 31 + + + + + TMSR2 + TMSR2. + 0x38 + + + tmsr_2 + 2 + 2 + + + tmsr_1 + 1 + 1 + + + tmsr_0 + 0 + 0 + + + + + TMSR3 + TMSR3. + 0x3C + + + tmsr_2 + 2 + 2 + + + tmsr_1 + 1 + 1 + + + tmsr_0 + 0 + 0 + + + + + TIER2 + TIER2. + 0x44 + + + tier_2 + 2 + 2 + + + tier_1 + 1 + 1 + + + tier_0 + 0 + 0 + + + + + TIER3 + TIER3. + 0x48 + + + tier_2 + 2 + 2 + + + tier_1 + 1 + 1 + + + tier_0 + 0 + 0 + + + + + TPLVR2 + TPLVR2. + 0x50 + + + tplvr + 0 + 31 + + + + + TPLVR3 + TPLVR3. + 0x54 + + + tplvr + 0 + 31 + + + + + TPLCR2 + TPLCR2. + 0x5C + + + tplcr + 0 + 1 + + + + + TPLCR3 + TPLCR3. + 0x60 + + + tplcr + 0 + 1 + + + + + WMER + WMER. + 0x64 + + + wrie + 1 + 1 + + + we + 0 + 0 + + + + + WMR + WMR. + 0x68 + + + wmr + 0 + 15 + + + + + WVR + WVR. + 0x6C + + + wvr + 0 + 15 + + + + + WSR + WSR. + 0x70 + + + wts + 0 + 0 + + + + + TICR2 + TICR2. + 0x78 + + + tclr_2 + 2 + 2 + + + tclr_1 + 1 + 1 + + + tclr_0 + 0 + 0 + + + + + TICR3 + TICR3. + 0x7C + + + tclr_2 + 2 + 2 + + + tclr_1 + 1 + 1 + + + tclr_0 + 0 + 0 + + + + + WICR + WICR. + 0x80 + + + wiclr + 0 + 0 + + + + + TCER + TCER. + 0x84 + + + timer3_en + 2 + 2 + + + timer2_en + 1 + 1 + + + + + TCMR + TCMR. + 0x88 + + + timer3_mode + 2 + 2 + + + timer2_mode + 1 + 1 + + + + + TILR2 + TILR2. + 0x90 + + + tilr_2 + 2 + 2 + + + tilr_1 + 1 + 1 + + + tilr_0 + 0 + 0 + + + + + TILR3 + TILR3. + 0x94 + + + tilr_2 + 2 + 2 + + + tilr_1 + 1 + 1 + + + tilr_0 + 0 + 0 + + + + + WCR + WCR. + 0x98 + + + wcr + 0 + 0 + + + + + WFAR + WFAR. + 0x9C + + + wfar + 0 + 15 + + + + + WSAR + WSAR. + 0xA0 + + + wsar + 0 + 15 + + + + + TCVWR2 + TCVWR2. + 0xA8 + + + tcvwr + 0 + 31 + + + + + TCVWR3 + TCVWR3. + 0xAC + + + tcvwr + 0 + 31 + + + + + TCVSYN2 + TCVSYN2. + 0xB4 + + + tcvsyn2 + 0 + 31 + + + + + TCVSYN3 + TCVSYN3. + 0xB8 + + + tcvsyn3 + 0 + 31 + + + + + TCDR + TCDR. + 0xBC + + + wcdr + 24 + 31 + + + tcdr3 + 16 + 23 + + + tcdr2 + 8 + 15 + + + + + + + ir + ir. + 0x4000A600 + ir + 32 + read-write + + 0 + 0x1000 + registers + + + + irtx_config + irtx_config. + 0x0 + + + cr_irtx_data_num + 12 + 17 + + + cr_irtx_tail_hl_inv + 11 + 11 + + + cr_irtx_tail_en + 10 + 10 + + + cr_irtx_head_hl_inv + 9 + 9 + + + cr_irtx_head_en + 8 + 8 + + + cr_irtx_logic1_hl_inv + 6 + 6 + + + cr_irtx_logic0_hl_inv + 5 + 5 + + + cr_irtx_data_en + 4 + 4 + + + cr_irtx_swm_en + 3 + 3 + + + cr_irtx_mod_en + 2 + 2 + + + cr_irtx_out_inv + 1 + 1 + + + cr_irtx_en + 0 + 0 + + + + + irtx_int_sts + irtx_int_sts. + 0x4 + + + cr_irtx_end_en + 24 + 24 + + + cr_irtx_end_clr + 16 + 16 + + + cr_irtx_end_mask + 8 + 8 + + + irtx_end_int + 0 + 0 + + + + + irtx_data_word0 + irtx_data_word0. + 0x8 + + + cr_irtx_data_word0 + 0 + 31 + + + + + irtx_data_word1 + irtx_data_word1. + 0xC + + + cr_irtx_data_word1 + 0 + 31 + + + + + irtx_pulse_width + irtx_pulse_width. + 0x10 + + + cr_irtx_mod_ph1_w + 24 + 31 + + + cr_irtx_mod_ph0_w + 16 + 23 + + + cr_irtx_pw_unit + 0 + 11 + + + + + irtx_pw + irtx_pw. + 0x14 + + + cr_irtx_tail_ph1_w + 28 + 31 + + + cr_irtx_tail_ph0_w + 24 + 27 + + + cr_irtx_head_ph1_w + 20 + 23 + + + cr_irtx_head_ph0_w + 16 + 19 + + + cr_irtx_logic1_ph1_w + 12 + 15 + + + cr_irtx_logic1_ph0_w + 8 + 11 + + + cr_irtx_logic0_ph1_w + 4 + 7 + + + cr_irtx_logic0_ph0_w + 0 + 3 + + + + + irtx_swm_pw_0 + irtx_swm_pw_0. + 0x40 + + + cr_irtx_swm_pw_0 + 0 + 31 + + + + + irtx_swm_pw_1 + irtx_swm_pw_1. + 0x44 + + + cr_irtx_swm_pw_1 + 0 + 31 + + + + + irtx_swm_pw_2 + irtx_swm_pw_2. + 0x48 + + + cr_irtx_swm_pw_2 + 0 + 31 + + + + + irtx_swm_pw_3 + irtx_swm_pw_3. + 0x4C + + + cr_irtx_swm_pw_3 + 0 + 31 + + + + + irtx_swm_pw_4 + irtx_swm_pw_4. + 0x50 + + + cr_irtx_swm_pw_4 + 0 + 31 + + + + + irtx_swm_pw_5 + irtx_swm_pw_5. + 0x54 + + + cr_irtx_swm_pw_5 + 0 + 31 + + + + + irtx_swm_pw_6 + irtx_swm_pw_6. + 0x58 + + + cr_irtx_swm_pw_6 + 0 + 31 + + + + + irtx_swm_pw_7 + irtx_swm_pw_7. + 0x5C + + + cr_irtx_swm_pw_7 + 0 + 31 + + + + + irrx_config + irrx_config. + 0x80 + + + cr_irrx_deg_cnt + 8 + 11 + + + cr_irrx_deg_en + 4 + 4 + + + cr_irrx_mode + 2 + 3 + + + cr_irrx_in_inv + 1 + 1 + + + cr_irrx_en + 0 + 0 + + + + + irrx_int_sts + irrx_int_sts. + 0x84 + + + cr_irrx_end_en + 24 + 24 + + + cr_irrx_end_clr + 16 + 16 + + + cr_irrx_end_mask + 8 + 8 + + + irrx_end_int + 0 + 0 + + + + + irrx_pw_config + irrx_pw_config. + 0x88 + + + cr_irrx_end_th + 16 + 31 + + + cr_irrx_data_th + 0 + 15 + + + + + irrx_data_count + irrx_data_count. + 0x90 + + + sts_irrx_data_cnt + 0 + 6 + + + + + irrx_data_word0 + irrx_data_word0. + 0x94 + + + sts_irrx_data_word0 + 0 + 31 + + + + + irrx_data_word1 + irrx_data_word1. + 0x98 + + + sts_irrx_data_word1 + 0 + 31 + + + + + irrx_swm_fifo_config_0 + irrx_swm_fifo_config_0. + 0xC0 + + + rx_fifo_cnt + 4 + 10 + + + rx_fifo_underflow + 3 + 3 + + + rx_fifo_overflow + 2 + 2 + + + rx_fifo_clr + 0 + 0 + + + + + irrx_swm_fifo_rdata + irrx_swm_fifo_rdata. + 0xC4 + + + rx_fifo_rdata + 0 + 15 + + + + + + + cks + cks. + 0x4000A000 + cks + 32 + read-write + + 0 + 0x1000 + registers + + + + cks_config + cks_config. + 0x0 + + + cr_cks_byte_swap + 1 + 1 + + + cr_cks_clr + 0 + 0 + + + + + data_in + data_in. + 0x4 + + + data_in + 0 + 7 + + + + + cks_out + cks_out. + 0x8 + + + cks_out + 0 + 15 + + + + + + + sf_ctrl + sf_ctrl. + 0x4000B000 + sf_ctrl + 32 + read-write + + 0 + 0x1000 + registers + + + + sf_ctrl_0 + sf_ctrl_0. + 0x0 + + + sf_id + 24 + 31 + + + sf_aes_iv_endian + 23 + 23 + + + sf_aes_key_endian + 22 + 22 + + + sf_aes_ctr_plus_en + 21 + 21 + + + sf_aes_dout_endian + 20 + 20 + + + sf_aes_dly_mode + 19 + 19 + + + sf_if_int_set + 18 + 18 + + + sf_if_int_clr + 17 + 17 + + + sf_if_int + 16 + 16 + + + sf_if_read_dly_en + 11 + 11 + + + sf_if_read_dly_n + 8 + 10 + + + sf_clk_sahb_sram_sel + 5 + 5 + + + sf_clk_out_inv_sel + 4 + 4 + + + sf_clk_out_gate_en + 3 + 3 + + + sf_clk_sf_rx_inv_sel + 2 + 2 + + + + + sf_ctrl_1 + sf_ctrl_1. + 0x4 + + + sf_ahb2sram_en + 31 + 31 + + + sf_ahb2sif_en + 30 + 30 + + + sf_if_en + 29 + 29 + + + sf_if_fn_sel + 28 + 28 + + + sf_ahb2sif_stop + 27 + 27 + + + sf_ahb2sif_stopped + 26 + 26 + + + sf_if_reg_wp + 25 + 25 + + + sf_if_reg_hold + 24 + 24 + + + sf_if_0_ack_lat + 20 + 22 + + + sf_if_sr_int_set + 18 + 18 + + + sf_if_sr_int_en + 17 + 17 + + + sf_if_sr_int + 16 + 16 + + + sf_if_sr_pat + 8 + 15 + + + sf_if_sr_pat_mask + 0 + 7 + + + + + sf_if_sahb_0 + sf_if_sahb_0. + 0x8 + + + sf_if_0_qpi_mode_en + 31 + 31 + + + sf_if_0_spi_mode + 28 + 30 + + + sf_if_0_cmd_en + 27 + 27 + + + sf_if_0_adr_en + 26 + 26 + + + sf_if_0_dmy_en + 25 + 25 + + + sf_if_0_dat_en + 24 + 24 + + + sf_if_0_dat_rw + 23 + 23 + + + sf_if_0_cmd_byte + 20 + 22 + + + sf_if_0_adr_byte + 17 + 19 + + + sf_if_0_dmy_byte + 12 + 16 + + + sf_if_0_dat_byte + 2 + 11 + + + sf_if_0_trig + 1 + 1 + + + sf_if_busy + 0 + 0 + + + + + sf_if_sahb_1 + sf_if_sahb_1. + 0xC + + + sf_if_0_cmd_buf_0 + 0 + 31 + + + + + sf_if_sahb_2 + sf_if_sahb_2. + 0x10 + + + sf_if_0_cmd_buf_1 + 0 + 31 + + + + + sf_if_iahb_0 + sf_if_iahb_0. + 0x14 + + + sf_if_1_qpi_mode_en + 31 + 31 + + + sf_if_1_spi_mode + 28 + 30 + + + sf_if_1_cmd_en + 27 + 27 + + + sf_if_1_adr_en + 26 + 26 + + + sf_if_1_dmy_en + 25 + 25 + + + sf_if_1_dat_en + 24 + 24 + + + sf_if_1_dat_rw + 23 + 23 + + + sf_if_1_cmd_byte + 20 + 22 + + + sf_if_1_adr_byte + 17 + 19 + + + sf_if_1_dmy_byte + 12 + 16 + + + + + sf_if_iahb_1 + sf_if_iahb_1. + 0x18 + + + sf_if_1_cmd_buf_0 + 0 + 31 + + + + + sf_if_iahb_2 + sf_if_iahb_2. + 0x1C + + + sf_if_1_cmd_buf_1 + 0 + 31 + + + + + sf_if_status_0 + sf_if_status_0. + 0x20 + + + sf_if_status_0 + 0 + 31 + + + + + sf_if_status_1 + sf_if_status_1. + 0x24 + + + sf_if_status_1 + 0 + 31 + + + + + sf_aes + sf_aes. + 0x28 + + + sf_aes_status + 5 + 31 + + + sf_aes_pref_busy + 4 + 4 + + + sf_aes_pref_trig + 3 + 3 + + + sf_aes_mode + 1 + 2 + + + sf_aes_en + 0 + 0 + + + + + sf_ahb2sif_status + sf_ahb2sif_status. + 0x2C + + + sf_ahb2sif_status + 0 + 31 + + + + + sf_if_io_dly_0 + sf_if_io_dly_0. + 0x30 + + + sf_dqs_do_dly_sel + 30 + 31 + + + sf_dqs_di_dly_sel + 28 + 29 + + + sf_dqs_oe_dly_sel + 26 + 27 + + + sf_clk_out_dly_sel + 8 + 9 + + + sf_cs_dly_sel + 0 + 1 + + + + + sf_if_io_dly_1 + sf_if_io_dly_1. + 0x34 + + + sf_io_0_do_dly_sel + 16 + 17 + + + sf_io_0_di_dly_sel + 8 + 9 + + + sf_io_0_oe_dly_sel + 0 + 1 + + + + + sf_if_io_dly_2 + sf_if_io_dly_2. + 0x38 + + + sf_io_1_do_dly_sel + 16 + 17 + + + sf_io_1_di_dly_sel + 8 + 9 + + + sf_io_1_oe_dly_sel + 0 + 1 + + + + + sf_if_io_dly_3 + sf_if_io_dly_3. + 0x3C + + + sf_io_2_do_dly_sel + 16 + 17 + + + sf_io_2_di_dly_sel + 8 + 9 + + + sf_io_2_oe_dly_sel + 0 + 1 + + + + + sf_if_io_dly_4 + sf_if_io_dly_4. + 0x40 + + + sf_io_3_do_dly_sel + 16 + 17 + + + sf_io_3_di_dly_sel + 8 + 9 + + + sf_io_3_oe_dly_sel + 0 + 1 + + + + + sf_reserved + sf_reserved. + 0x44 + + + sf_reserved + 0 + 31 + + + + + sf2_if_io_dly_0 + sf2_if_io_dly_0. + 0x48 + + + sf2_dqs_do_dly_sel + 30 + 31 + + + sf2_dqs_di_dly_sel + 28 + 29 + + + sf2_dqs_oe_dly_sel + 26 + 27 + + + sf2_clk_out_dly_sel + 8 + 9 + + + sf2_cs_dly_sel + 0 + 1 + + + + + sf2_if_io_dly_1 + sf2_if_io_dly_1. + 0x4C + + + sf2_io_0_do_dly_sel + 16 + 17 + + + sf2_io_0_di_dly_sel + 8 + 9 + + + sf2_io_0_oe_dly_sel + 0 + 1 + + + + + sf2_if_io_dly_2 + sf2_if_io_dly_2. + 0x50 + + + sf2_io_1_do_dly_sel + 16 + 17 + + + sf2_io_1_di_dly_sel + 8 + 9 + + + sf2_io_1_oe_dly_sel + 0 + 1 + + + + + sf2_if_io_dly_3 + sf2_if_io_dly_3. + 0x54 + + + sf2_io_2_do_dly_sel + 16 + 17 + + + sf2_io_2_di_dly_sel + 8 + 9 + + + sf2_io_2_oe_dly_sel + 0 + 1 + + + + + sf2_if_io_dly_4 + sf2_if_io_dly_4. + 0x58 + + + sf2_io_3_do_dly_sel + 16 + 17 + + + sf2_io_3_di_dly_sel + 8 + 9 + + + sf2_io_3_oe_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_0 + sf3_if_io_dly_0. + 0x5C + + + sf3_dqs_do_dly_sel + 30 + 31 + + + sf3_dqs_di_dly_sel + 28 + 29 + + + sf3_dqs_oe_dly_sel + 26 + 27 + + + sf3_clk_out_dly_sel + 8 + 9 + + + sf3_cs_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_1 + sf3_if_io_dly_1. + 0x60 + + + sf3_io_0_do_dly_sel + 16 + 17 + + + sf3_io_0_di_dly_sel + 8 + 9 + + + sf3_io_0_oe_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_2 + sf3_if_io_dly_2. + 0x64 + + + sf3_io_1_do_dly_sel + 16 + 17 + + + sf3_io_1_di_dly_sel + 8 + 9 + + + sf3_io_1_oe_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_3 + sf3_if_io_dly_3. + 0x68 + + + sf3_io_2_do_dly_sel + 16 + 17 + + + sf3_io_2_di_dly_sel + 8 + 9 + + + sf3_io_2_oe_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_4 + sf3_if_io_dly_4. + 0x6C + + + sf3_io_3_do_dly_sel + 16 + 17 + + + sf3_io_3_di_dly_sel + 8 + 9 + + + sf3_io_3_oe_dly_sel + 0 + 1 + + + + + sf_ctrl_2 + sf_ctrl_2. + 0x70 + + + sf_if_dqs_en + 5 + 5 + + + sf_if_dtr_en + 4 + 4 + + + sf_if_pad_sel_lock + 3 + 3 + + + sf_if_pad_sel + 0 + 1 + + + + + sf_ctrl_3 + sf_ctrl_3. + 0x74 + + + sf_if_1_ack_lat + 29 + 31 + + + sf_cmds_wrap_mode + 10 + 10 + + + sf_cmds_wrap_q_ini + 9 + 9 + + + sf_cmds_bt_en + 8 + 8 + + + sf_cmds_bt_dly + 5 + 7 + + + sf_cmds_en + 4 + 4 + + + sf_cmds_wrap_len + 0 + 3 + + + + + sf_if_iahb_3 + sf_if_iahb_3. + 0x78 + + + sf_if_2_qpi_mode_en + 31 + 31 + + + sf_if_2_spi_mode + 28 + 30 + + + sf_if_2_cmd_en + 27 + 27 + + + sf_if_2_adr_en + 26 + 26 + + + sf_if_2_dmy_en + 25 + 25 + + + sf_if_2_dat_en + 24 + 24 + + + sf_if_2_dat_rw + 23 + 23 + + + sf_if_2_cmd_byte + 20 + 22 + + + sf_if_2_adr_byte + 17 + 19 + + + sf_if_2_dmy_byte + 12 + 16 + + + + + sf_if_iahb_4 + sf_if_iahb_4. + 0x7C + + + sf_if_2_cmd_buf_0 + 0 + 31 + + + + + sf_if_iahb_5 + sf_if_iahb_5. + 0x80 + + + sf_if_2_cmd_buf_1 + 0 + 31 + + + + + sf_if_iahb_6 + sf_if_iahb_6. + 0x84 + + + sf_if_3_qpi_mode_en + 31 + 31 + + + sf_if_3_spi_mode + 28 + 30 + + + sf_if_3_cmd_byte + 20 + 22 + + + + + sf_if_iahb_7 + sf_if_iahb_7. + 0x88 + + + sf_if_3_cmd_buf_0 + 0 + 31 + + + + + sf_ctrl_prot_en_rd + sf_ctrl_prot_en_rd. + 0x100 + + + sf_dbg_dis + 31 + 31 + + + sf_if_0_trig_wr_lock + 30 + 30 + + + sf_ctrl_id1_en_rd + 2 + 2 + + + sf_ctrl_id0_en_rd + 1 + 1 + + + sf_ctrl_prot_en_rd + 0 + 0 + + + + + sf_ctrl_prot_en + sf_ctrl_prot_en. + 0x104 + + + sf_ctrl_id1_en + 2 + 2 + + + sf_ctrl_id0_en + 1 + 1 + + + sf_ctrl_prot_en + 0 + 0 + + + + + sf_aes_key_r0_0 + sf_aes_key_r0_0. + 0x200 + + + sf_aes_key_r0_0 + 0 + 31 + + + + + sf_aes_key_r0_1 + sf_aes_key_r0_1. + 0x204 + + + sf_aes_key_r0_1 + 0 + 31 + + + + + sf_aes_key_r0_2 + sf_aes_key_r0_2. + 0x208 + + + sf_aes_key_r0_2 + 0 + 31 + + + + + sf_aes_key_r0_3 + sf_aes_key_r0_3. + 0x20C + + + sf_aes_key_r0_3 + 0 + 31 + + + + + sf_aes_key_r0_4 + sf_aes_key_r0_4. + 0x210 + + + sf_aes_key_r0_4 + 0 + 31 + + + + + sf_aes_key_r0_5 + sf_aes_key_r0_5. + 0x214 + + + sf_aes_key_r0_5 + 0 + 31 + + + + + sf_aes_key_r0_6 + sf_aes_key_r0_6. + 0x218 + + + sf_aes_key_r0_6 + 0 + 31 + + + + + sf_aes_key_r0_7 + sf_aes_key_r0_7. + 0x21C + + + sf_aes_key_r0_7 + 0 + 31 + + + + + sf_aes_iv_r0_w0 + sf_aes_iv_r0_w0. + 0x220 + + + sf_aes_iv_r0_w0 + 0 + 31 + + + + + sf_aes_iv_r0_w1 + sf_aes_iv_r0_w1. + 0x224 + + + sf_aes_iv_r0_w1 + 0 + 31 + + + + + sf_aes_iv_r0_w2 + sf_aes_iv_r0_w2. + 0x228 + + + sf_aes_iv_r0_w2 + 0 + 31 + + + + + sf_aes_iv_r0_w3 + sf_aes_iv_r0_w3. + 0x22C + + + sf_aes_iv_r0_w3 + 0 + 31 + + + + + sf_aes_cfg_r0 + sf_aes_cfg_r0. + 0x230 + + + sf_aes_region_r0_lock + 31 + 31 + + + sf_aes_region_r0_en + 30 + 30 + + + sf_aes_region_r0_hw_key_en + 29 + 29 + + + sf_aes_region_r0_start + 14 + 27 + + + sf_aes_region_r0_end + 0 + 13 + + + + + sf_aes_key_r1_0 + sf_aes_key_r1_0. + 0x300 + + + sf_aes_key_r1_0 + 0 + 31 + + + + + sf_aes_key_r1_1 + sf_aes_key_r1_1. + 0x304 + + + sf_aes_key_r1_1 + 0 + 31 + + + + + sf_aes_key_r1_2 + sf_aes_key_r1_2. + 0x308 + + + sf_aes_key_r1_2 + 0 + 31 + + + + + sf_aes_key_r1_3 + sf_aes_key_r1_3. + 0x30C + + + sf_aes_key_r1_3 + 0 + 31 + + + + + sf_aes_key_r1_4 + sf_aes_key_r1_4. + 0x310 + + + sf_aes_key_r1_4 + 0 + 31 + + + + + sf_aes_key_r1_5 + sf_aes_key_r1_5. + 0x314 + + + sf_aes_key_r1_5 + 0 + 31 + + + + + sf_aes_key_r1_6 + sf_aes_key_r1_6. + 0x318 + + + sf_aes_key_r1_6 + 0 + 31 + + + + + sf_aes_key_r1_7 + sf_aes_key_r1_7. + 0x31C + + + sf_aes_key_r1_7 + 0 + 31 + + + + + sf_aes_iv_r1_w0 + sf_aes_iv_r1_w0. + 0x320 + + + sf_aes_iv_r1_w0 + 0 + 31 + + + + + sf_aes_iv_r1_w1 + sf_aes_iv_r1_w1. + 0x324 + + + sf_aes_iv_r1_w1 + 0 + 31 + + + + + sf_aes_iv_r1_w2 + sf_aes_iv_r1_w2. + 0x328 + + + sf_aes_iv_r1_w2 + 0 + 31 + + + + + sf_aes_iv_r1_w3 + sf_aes_iv_r1_w3. + 0x32C + + + sf_aes_iv_r1_w3 + 0 + 31 + + + + + sf_aes_r1 + sf_aes_r1. + 0x330 + + + sf_aes_r1_lock + 31 + 31 + + + sf_aes_r1_en + 30 + 30 + + + sf_aes_r1_hw_key_en + 29 + 29 + + + sf_aes_r1_start + 14 + 27 + + + sf_aes_r1_end + 0 + 13 + + + + + sf_aes_key_r2_0 + sf_aes_key_r2_0. + 0x400 + + + sf_aes_key_r2_0 + 0 + 31 + + + + + sf_aes_key_r2_1 + sf_aes_key_r2_1. + 0x404 + + + sf_aes_key_r2_1 + 0 + 31 + + + + + sf_aes_key_r2_2 + sf_aes_key_r2_2. + 0x408 + + + sf_aes_key_r2_2 + 0 + 31 + + + + + sf_aes_key_r2_3 + sf_aes_key_r2_3. + 0x40C + + + sf_aes_key_r2_3 + 0 + 31 + + + + + sf_aes_key_r2_4 + sf_aes_key_r2_4. + 0x410 + + + sf_aes_key_r2_4 + 0 + 31 + + + + + sf_aes_key_r2_5 + sf_aes_key_r2_5. + 0x414 + + + sf_aes_key_r2_5 + 0 + 31 + + + + + sf_aes_key_r2_6 + sf_aes_key_r2_6. + 0x418 + + + sf_aes_key_r2_6 + 0 + 31 + + + + + sf_aes_key_r2_7 + sf_aes_key_r2_7. + 0x41C + + + sf_aes_key_r2_7 + 0 + 31 + + + + + sf_aes_iv_r2_w0 + sf_aes_iv_r2_w0. + 0x420 + + + sf_aes_iv_r2_w0 + 0 + 31 + + + + + sf_aes_iv_r2_w1 + sf_aes_iv_r2_w1. + 0x424 + + + sf_aes_iv_r2_w1 + 0 + 31 + + + + + sf_aes_iv_r2_w2 + sf_aes_iv_r2_w2. + 0x428 + + + sf_aes_iv_r2_w2 + 0 + 31 + + + + + sf_aes_iv_r2_w3 + sf_aes_iv_r2_w3. + 0x42C + + + sf_aes_iv_r2_w3 + 0 + 31 + + + + + sf_aes_r2 + sf_aes_r2. + 0x430 + + + sf_aes_r2_lock + 31 + 31 + + + sf_aes_r2_en + 30 + 30 + + + sf_aes_r2_hw_key_en + 29 + 29 + + + sf_aes_r2_start + 14 + 27 + + + sf_aes_r2_end + 0 + 13 + + + + + sf_id0_offset + sf_id0_offset. + 0x434 + + + sf_id0_offset + 0 + 23 + + + + + sf_id1_offset + sf_id1_offset. + 0x438 + + + sf_id1_offset + 0 + 23 + + + + + + + dma + dma. + 0x4000C000 + dma + 32 + read-write + + 0 + 0x1000 + registers + + + + DMA_IntStatus + DMA_IntStatus. + 0x0 + + + IntStatus + 0 + 7 + + + + + DMA_IntTCStatus + DMA_IntTCStatus. + 0x4 + + + IntTCStatus + 0 + 7 + + + + + DMA_IntTCClear + DMA_IntTCClear. + 0x8 + + + IntTCClear + 0 + 7 + + + + + DMA_IntErrorStatus + DMA_IntErrorStatus. + 0xC + + + IntErrorStatus + 0 + 7 + + + + + DMA_IntErrClr + DMA_IntErrClr. + 0x10 + + + IntErrClr + 0 + 7 + + + + + DMA_RawIntTCStatus + DMA_RawIntTCStatus. + 0x14 + + + RawIntTCStatus + 0 + 7 + + + + + DMA_RawIntErrorStatus + DMA_RawIntErrorStatus. + 0x18 + + + RawIntErrorStatus + 0 + 7 + + + + + DMA_EnbldChns + DMA_EnbldChns. + 0x1C + + + EnabledChannels + 0 + 7 + + + + + DMA_SoftBReq + DMA_SoftBReq. + 0x20 + + + SoftBReq + 0 + 31 + + + + + DMA_SoftSReq + DMA_SoftSReq. + 0x24 + + + SoftSReq + 0 + 31 + + + + + DMA_SoftLBReq + DMA_SoftLBReq. + 0x28 + + + SoftLBReq + 0 + 31 + + + + + DMA_SoftLSReq + DMA_SoftLSReq. + 0x2C + + + SoftLSReq + 0 + 31 + + + + + DMA_Top_Config + DMA_Top_Config. + 0x30 + + + M + 1 + 1 + + + E + 0 + 0 + + + + + DMA_Sync + DMA_Sync. + 0x34 + + + DMA_Sync + 0 + 31 + + + + + DMA_C0SrcAddr + DMA_C0SrcAddr. + 0x100 + + + SrcAddr + 0 + 31 + + + + + DMA_C0DstAddr + DMA_C0DstAddr. + 0x104 + + + DstAddr + 0 + 31 + + + + + DMA_C0LLI + DMA_C0LLI. + 0x108 + + + LLI + 0 + 31 + + + + + DMA_C0Control + DMA_C0Control. + 0x10C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + SLargerD + 24 + 24 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + DBSize + 15 + 17 + + + SBSize + 12 + 14 + + + TransferSize + 0 + 11 + + + + + DMA_C0Config + DMA_C0Config. + 0x110 + + + LLICounter + 20 + 29 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C1SrcAddr + DMA_C1SrcAddr. + 0x200 + + + SrcAddr + 0 + 31 + + + + + DMA_C1DstAddr + DMA_C1DstAddr. + 0x204 + + + DstAddr + 0 + 31 + + + + + DMA_C1LLI + DMA_C1LLI. + 0x208 + + + LLI + 2 + 31 + + + + + DMA_C1Control + DMA_C1Control. + 0x20C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + DBSize + 15 + 17 + + + SBSize + 12 + 14 + + + TransferSize + 0 + 11 + + + + + DMA_C1Config + DMA_C1Config. + 0x210 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C2SrcAddr + DMA_C2SrcAddr. + 0x300 + + + SrcAddr + 0 + 31 + + + + + DMA_C2DstAddr + DMA_C2DstAddr. + 0x304 + + + DstAddr + 0 + 31 + + + + + DMA_C2LLI + DMA_C2LLI. + 0x308 + + + LLI + 2 + 31 + + + + + DMA_C2Control + DMA_C2Control. + 0x30C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + DBSize + 15 + 17 + + + SBSize + 12 + 14 + + + TransferSize + 0 + 11 + + + + + DMA_C2Config + DMA_C2Config. + 0x310 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C3SrcAddr + DMA_C3SrcAddr. + 0x400 + + + SrcAddr + 0 + 31 + + + + + DMA_C3DstAddr + DMA_C3DstAddr. + 0x404 + + + DstAddr + 0 + 31 + + + + + DMA_C3LLI + DMA_C3LLI. + 0x408 + + + LLI + 2 + 31 + + + + + DMA_C3Control + DMA_C3Control. + 0x40C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + DBSize + 15 + 17 + + + SBSize + 12 + 14 + + + TransferSize + 0 + 11 + + + + + DMA_C3Config + DMA_C3Config. + 0x410 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + + + pds + pds. + 0x4000E000 + pds + 32 + read-write + + 0 + 0x1000 + registers + + + + PDS_CTL + PDS_CTL. + 0x0 + + + cr_pds_ctrl_pll + 30 + 31 + + + cr_pds_ctrl_rf + 28 + 29 + + + cr_pds_ldo_vol + 24 + 27 + + + cr_pds_pd_ldo11 + 22 + 22 + + + cr_np_wfi_mask + 21 + 21 + + + cr_pds_ldo_vsel_en + 18 + 18 + + + cr_pds_rc32m_off_dis + 17 + 17 + + + cr_pds_rst_soc_en + 16 + 16 + + + cr_pds_soc_enb_force_on + 15 + 15 + + + cr_pds_pd_xtal + 14 + 14 + + + cr_pds_pwr_off + 13 + 13 + + + cr_pds_wait_xtal_rdy + 12 + 12 + + + cr_pds_iso_en + 11 + 11 + + + cr_pds_mem_stby + 9 + 9 + + + cr_pds_gate_clk + 8 + 8 + + + cr_pds_pd_bg_sys + 5 + 5 + + + cr_pds_pd_dcdc18 + 4 + 4 + + + cr_wifi_pds_save_state + 3 + 3 + + + cr_xtal_force_off + 2 + 2 + + + cr_sleep_forever + 1 + 1 + + + pds_start_ps + 0 + 0 + + + + + PDS_TIME1 + PDS_TIME1. + 0x4 + + + cr_sleep_duration + 0 + 31 + + + + + PDS_INT + PDS_INT. + 0xC + + + cr_pds_int_clr + 16 + 16 + + + cr_pds_pll_done_int_mask + 11 + 11 + + + cr_pds_rf_done_int_mask + 10 + 10 + + + cr_pds_irq_in_dis + 9 + 9 + + + cr_pds_wake_int_mask + 8 + 8 + + + ro_pds_pll_done_int + 3 + 3 + + + ro_pds_rf_done_int + 2 + 2 + + + ro_pds_irq_in + 1 + 1 + + + ro_pds_wake_int + 0 + 0 + + + + + PDS_CTL2 + PDS_CTL2. + 0x10 + + + cr_pds_force_wb_gate_clk + 18 + 18 + + + cr_pds_force_np_gate_clk + 16 + 16 + + + cr_pds_force_wb_mem_stby + 14 + 14 + + + cr_pds_force_np_mem_stby + 12 + 12 + + + cr_pds_force_wb_pds_rst + 10 + 10 + + + cr_pds_force_np_pds_rst + 8 + 8 + + + cr_pds_force_wb_iso_en + 6 + 6 + + + cr_pds_force_np_iso_en + 4 + 4 + + + cr_pds_force_wb_pwr_off + 2 + 2 + + + cr_pds_force_np_pwr_off + 0 + 0 + + + + + PDS_CTL3 + PDS_CTL3. + 0x14 + + + cr_pds_misc_iso_en + 30 + 30 + + + cr_pds_wb_iso_en + 27 + 27 + + + cr_pds_np_iso_en + 24 + 24 + + + cr_pds_force_misc_gate_clk + 13 + 13 + + + cr_pds_force_misc_mem_stby + 10 + 10 + + + cr_pds_force_misc_pds_rst + 7 + 7 + + + cr_pds_force_misc_iso_en + 4 + 4 + + + cr_pds_force_misc_pwr_off + 1 + 1 + + + + + PDS_CTL4 + PDS_CTL4. + 0x18 + + + cr_pds_misc_gate_clk + 27 + 27 + + + cr_pds_misc_mem_stby + 26 + 26 + + + cr_pds_misc_reset + 25 + 25 + + + cr_pds_misc_pwr_off + 24 + 24 + + + cr_pds_wb_gate_clk + 15 + 15 + + + cr_pds_wb_mem_stby + 14 + 14 + + + cr_pds_wb_reset + 13 + 13 + + + cr_pds_wb_pwr_off + 12 + 12 + + + cr_pds_np_gate_clk + 3 + 3 + + + cr_pds_np_mem_stby + 2 + 2 + + + cr_pds_np_reset + 1 + 1 + + + cr_pds_np_pwr_off + 0 + 0 + + + + + pds_stat + pds_stat. + 0x1C + + + ro_pds_pll_state + 16 + 17 + + + ro_pds_rf_state + 8 + 11 + + + ro_pds_state + 0 + 3 + + + + + pds_ram1 + pds_ram1. + 0x20 + + + cr_np_sram_pwr + 0 + 7 + + + + + rc32m_ctrl0 + rc32m_ctrl0. + 0x300 + + + rc32m_code_fr_ext + 22 + 29 + + + rc32m_pd + 21 + 21 + + + rc32m_cal_en + 20 + 20 + + + rc32m_ext_code_en + 19 + 19 + + + rc32m_refclk_half + 18 + 18 + + + rc32m_allow_cal + 17 + 17 + + + rc32m_dig_code_fr_cal + 6 + 13 + + + rc32m_cal_precharge + 5 + 5 + + + rc32m_cal_div + 3 + 4 + + + rc32m_cal_inprogress + 2 + 2 + + + rc32m_rdy + 1 + 1 + + + rc32m_cal_done + 0 + 0 + + + + + rc32m_ctrl1 + rc32m_ctrl1. + 0x304 + + + rc32m_reserved + 24 + 31 + + + rc32m_clk_force_on + 4 + 4 + + + rc32m_clk_inv + 3 + 3 + + + rc32m_clk_soft_rst + 2 + 2 + + + rc32m_soft_rst + 1 + 1 + + + rc32m_test_en + 0 + 0 + + + + + pu_rst_clkpll + pu_rst_clkpll. + 0x400 + + + pu_clkpll + 10 + 10 + + + pu_clkpll_sfreg + 9 + 9 + + + clkpll_pu_cp + 8 + 8 + + + clkpll_pu_pfd + 7 + 7 + + + clkpll_pu_clamp_op + 6 + 6 + + + clkpll_pu_fbdv + 5 + 5 + + + clkpll_pu_postdiv + 4 + 4 + + + clkpll_reset_refdiv + 3 + 3 + + + clkpll_reset_fbdv + 2 + 2 + + + clkpll_reset_postdiv + 1 + 1 + + + clkpll_sdm_reset + 0 + 0 + + + + + clkpll_top_ctrl + clkpll_top_ctrl. + 0x404 + + + clkpll_vg13_sel + 24 + 25 + + + clkpll_vg11_sel + 20 + 21 + + + clkpll_refclk_sel + 16 + 16 + + + clkpll_xtal_rc32m_sel + 12 + 12 + + + clkpll_refdiv_ratio + 8 + 11 + + + clkpll_postdiv + 0 + 6 + + + + + clkpll_cp + clkpll_cp. + 0x408 + + + clkpll_cp_opamp_en + 10 + 10 + + + clkpll_cp_startup_en + 9 + 9 + + + clkpll_int_frac_sw + 8 + 8 + + + clkpll_icp_1u + 6 + 7 + + + clkpll_icp_5u + 4 + 5 + + + clkpll_sel_cp_bias + 0 + 0 + + + + + clkpll_rz + clkpll_rz. + 0x40C + + + clkpll_rz + 16 + 18 + + + clkpll_cz + 14 + 15 + + + clkpll_c3 + 12 + 13 + + + clkpll_r4_short + 8 + 8 + + + clkpll_r4 + 4 + 5 + + + clkpll_c4_en + 0 + 0 + + + + + clkpll_fbdv + clkpll_fbdv. + 0x410 + + + clkpll_sel_fb_clk + 2 + 3 + + + clkpll_sel_sample_clk + 0 + 1 + + + + + clkpll_vco + clkpll_vco. + 0x414 + + + clkpll_shrtr + 3 + 3 + + + clkpll_vco_speed + 0 + 2 + + + + + clkpll_sdm + clkpll_sdm. + 0x418 + + + clkpll_sdm_bypass + 29 + 29 + + + clkpll_sdm_flag + 28 + 28 + + + clkpll_dither_sel + 24 + 25 + + + clkpll_sdmin + 0 + 23 + + + + + clkpll_output_en + clkpll_output_en. + 0x41C + + + clkpll_en_div2_480m + 9 + 9 + + + clkpll_en_32m + 8 + 8 + + + clkpll_en_48m + 7 + 7 + + + clkpll_en_80m + 6 + 6 + + + clkpll_en_96m + 5 + 5 + + + clkpll_en_120m + 4 + 4 + + + clkpll_en_160m + 3 + 3 + + + clkpll_en_192m + 2 + 2 + + + clkpll_en_240m + 1 + 1 + + + clkpll_en_480m + 0 + 0 + + + + + + + HBN + HBN. + 0x4000F000 + HBN + 32 + read-write + + 0 + 0x1000 + registers + + + + HBN_CTL + HBN_CTL. + 0x0 + + + hbn_state + 28 + 31 + + + sram_slp + 27 + 27 + + + sram_slp_option + 26 + 26 + + + pwr_on_option + 25 + 25 + + + rtc_dly_option + 24 + 24 + + + pu_dcdc18_aon + 23 + 23 + + + hbn_ldo11_aon_vout_sel + 19 + 22 + + + hbn_ldo11_rt_vout_sel + 15 + 18 + + + hbn_dis_pwr_off_ldo11_rt + 14 + 14 + + + hbn_dis_pwr_off_ldo11 + 13 + 13 + + + sw_rst + 12 + 12 + + + pwrdn_hbn_rtc + 11 + 11 + + + pwrdn_hbn_core + 9 + 9 + + + trap_mode + 8 + 8 + + + hbn_mode + 7 + 7 + + + rtc_ctl + 0 + 6 + + + + + HBN_TIME_L + HBN_TIME_L. + 0x4 + + + hbn_time_l + 0 + 31 + + + + + HBN_TIME_H + HBN_TIME_H. + 0x8 + + + hbn_time_h + 0 + 7 + + + + + RTC_TIME_L + RTC_TIME_L. + 0xC + + + rtc_time_latch_l + 0 + 31 + + + + + RTC_TIME_H + RTC_TIME_H. + 0x10 + + + rtc_time_latch + 31 + 31 + + + rtc_time_latch_h + 0 + 7 + + + + + HBN_IRQ_MODE + HBN_IRQ_MODE. + 0x14 + + + pin_wakeup_en + 27 + 27 + + + pin_wakeup_sel + 24 + 26 + + + irq_acomp1_en + 22 + 23 + + + irq_acomp0_en + 20 + 21 + + + irq_bor_en + 18 + 18 + + + reg_en_hw_pu_pd + 16 + 16 + + + reg_aon_pad_ie_smt + 8 + 8 + + + hbn_pin_wakeup_mask + 3 + 4 + + + hbn_pin_wakeup_mode + 0 + 2 + + + + + HBN_IRQ_STAT + HBN_IRQ_STAT. + 0x18 + + + irq_stat + 0 + 31 + + + + + HBN_IRQ_CLR + HBN_IRQ_CLR. + 0x1C + + + irq_clr + 0 + 31 + + + + + HBN_PIR_CFG + HBN_PIR_CFG. + 0x20 + + + gpadc_nosync + 9 + 9 + + + gpadc_cgen + 8 + 8 + + + pir_en + 7 + 7 + + + pir_dis + 4 + 5 + + + pir_lpf_sel + 2 + 2 + + + pir_hpf_sel + 0 + 1 + + + + + HBN_PIR_VTH + HBN_PIR_VTH. + 0x24 + + + pir_vth + 0 + 13 + + + + + HBN_PIR_INTERVAL + HBN_PIR_INTERVAL. + 0x28 + + + pir_interval + 0 + 11 + + + + + HBN_BOR_CFG + HBN_BOR_CFG. + 0x2C + + + r_bor_out + 3 + 3 + + + pu_bor + 2 + 2 + + + bor_vth + 1 + 1 + + + bor_sel + 0 + 0 + + + + + HBN_GLB + HBN_GLB. + 0x30 + + + sw_ldo11_aon_vout_sel + 28 + 31 + + + sw_ldo11_rt_vout_sel + 24 + 27 + + + sw_ldo11soc_vout_sel_aon + 16 + 19 + + + hbn_pu_rc32k + 5 + 5 + + + hbn_f32k_sel + 3 + 4 + + + hbn_uart_clk_sel + 2 + 2 + + + hbn_root_clk_sel + 0 + 1 + + + + + HBN_SRAM + HBN_SRAM. + 0x34 + + + retram_slp + 7 + 7 + + + retram_ret + 6 + 6 + + + + + HBN_RSV0 + HBN_RSV0. + 0x100 + + + HBN_RSV0 + 0 + 31 + + + + + HBN_RSV1 + HBN_RSV1. + 0x104 + + + HBN_RSV1 + 0 + 31 + + + + + HBN_RSV2 + HBN_RSV2. + 0x108 + + + HBN_RSV2 + 0 + 31 + + + + + HBN_RSV3 + HBN_RSV3. + 0x10C + + + HBN_RSV3 + 0 + 31 + + + + + rc32k_ctrl0 + rc32k_ctrl0. + 0x200 + + + rc32k_code_fr_ext + 22 + 31 + + + rc32k_cal_en + 20 + 20 + + + rc32k_ext_code_en + 19 + 19 + + + rc32k_allow_cal + 18 + 18 + + + rc32k_vref_dly + 16 + 17 + + + rc32k_dig_code_fr_cal + 6 + 15 + + + rc32k_cal_precharge + 5 + 5 + + + rc32k_cal_div + 3 + 4 + + + rc32k_cal_inprogress + 2 + 2 + + + rc32k_rdy + 1 + 1 + + + rc32k_cal_done + 0 + 0 + + + + + xtal32k + xtal32k. + 0x204 + + + pu_xtal32k + 19 + 19 + + + pu_xtal32k_buf + 18 + 18 + + + xtal32k_ac_cap_short + 17 + 17 + + + xtal32k_capbank + 11 + 16 + + + xtal32k_inv_stre + 9 + 10 + + + xtal32k_otf_short + 8 + 8 + + + xtal32k_outbuf_stre + 7 + 7 + + + xtal32k_reg + 5 + 6 + + + xtal32k_amp_ctrl + 3 + 4 + + + xtal32k_ext_sel + 2 + 2 + + + + + + + AON + AON. + 0x4000F800 + AON + 32 + read-write + + 0 + 0x1000 + registers + + + + aon + aon. + 0x800 + + + sw_pu_ldo11_rt + 22 + 22 + + + ldo11_rt_pulldown_sel + 21 + 21 + + + ldo11_rt_pulldown + 20 + 20 + + + pu_aon_dc_tbuf + 12 + 12 + + + aon_resv + 0 + 7 + + + + + aon_common + aon_common. + 0x804 + + + ten_cip_misc_aon + 20 + 20 + + + ten_mbg_aon + 19 + 19 + + + dten_xtal_aon + 18 + 18 + + + ten_xtal_aon + 17 + 17 + + + ten_ldo15rf_aon + 16 + 16 + + + ten_bg_sys_aon + 12 + 12 + + + ten_dcdc18_1_aon + 11 + 11 + + + ten_dcdc18_0_aon + 10 + 10 + + + ten_ldo11soc_aon + 9 + 9 + + + ten_vddcore_aon + 8 + 8 + + + ten_xtal32k + 6 + 6 + + + dten_xtal32k + 5 + 5 + + + ten_aon + 4 + 4 + + + tmux_aon + 0 + 2 + + + + + aon_misc + aon_misc. + 0x808 + + + sw_wb_en_aon + 1 + 1 + + + sw_soc_en_aon + 0 + 0 + + + + + bg_sys_top + bg_sys_top. + 0x810 + + + bg_sys_start_ctrl_aon + 12 + 12 + + + pu_bg_sys_aon + 8 + 8 + + + pmip_resv + 0 + 7 + + + + + dcdc18_top_0 + dcdc18_top_0. + 0x814 + + + dcdc18_rdy_aon + 31 + 31 + + + dcdc18_sstart_time_aon + 28 + 29 + + + dcdc18_osc_inhibit_t2_aon + 27 + 27 + + + dcdc18_slow_osc_aon + 26 + 26 + + + dcdc18_stop_osc_aon + 25 + 25 + + + dcdc18_slope_curr_sel_aon + 20 + 24 + + + dcdc18_osc_freq_trim_aon + 16 + 19 + + + dcdc18_osc_2m_mode_aon + 12 + 12 + + + dcdc18_vpfm_aon + 8 + 11 + + + dcdc18_vout_sel_aon + 1 + 5 + + + + + dcdc18_top_1 + dcdc18_top_1. + 0x818 + + + dcdc18_pulldown_aon + 29 + 29 + + + dcdc18_en_antiring_aon + 28 + 28 + + + dcdc18_cfb_sel_aon + 24 + 27 + + + dcdc18_chf_sel_aon + 20 + 23 + + + dcdc18_rc_sel_aon + 16 + 19 + + + dcdc18_nonoverlap_td_aon + 8 + 12 + + + dcdc18_zvs_td_opt_aon + 4 + 6 + + + dcdc18_cs_delay_aon + 1 + 3 + + + dcdc18_force_cs_zvs_aon + 0 + 0 + + + + + ldo11soc_and_dctest + ldo11soc_and_dctest. + 0x81C + + + pmip_dc_tp_out_en_aon + 31 + 31 + + + pu_vddcore_misc_aon + 30 + 30 + + + ldo11soc_power_good_aon + 29 + 29 + + + ldo11soc_rdy_aon + 28 + 28 + + + ldo11soc_cc_aon + 24 + 25 + + + ldo11soc_vth_sel_aon + 12 + 13 + + + ldo11soc_pulldown_sel_aon + 11 + 11 + + + ldo11soc_pulldown_aon + 10 + 10 + + + ldo11soc_sstart_delay_aon + 8 + 9 + + + ldo11soc_sstart_sel_aon + 4 + 4 + + + pu_ldo11soc_aon + 0 + 0 + + + + + psw_irrcv + psw_irrcv. + 0x820 + + + pu_ir_psw_aon + 0 + 0 + + + + + rf_top_aon + rf_top_aon. + 0x880 + + + ldo15rf_bypass_aon + 28 + 28 + + + ldo15rf_cc_aon + 24 + 25 + + + ldo15rf_vout_sel_aon + 16 + 18 + + + ldo15rf_pulldown_sel_aon + 13 + 13 + + + ldo15rf_pulldown_aon + 12 + 12 + + + ldo15rf_sstart_delay_aon + 9 + 10 + + + ldo15rf_sstart_sel_aon + 8 + 8 + + + pu_xtal_aon + 5 + 5 + + + pu_xtal_buf_aon + 4 + 4 + + + pu_sfreg_aon + 2 + 2 + + + pu_ldo15rf_aon + 1 + 1 + + + pu_mbg_aon + 0 + 0 + + + + + xtal_cfg + xtal_cfg. + 0x884 + + + xtal_rdy_sel_aon + 30 + 31 + + + xtal_gm_boost_aon + 28 + 29 + + + xtal_capcode_in_aon + 22 + 27 + + + xtal_capcode_out_aon + 16 + 21 + + + xtal_amp_ctrl_aon + 14 + 15 + + + xtal_sleep_aon + 13 + 13 + + + xtal_fast_startup_aon + 12 + 12 + + + xtal_buf_hp_aon + 8 + 11 + + + xtal_buf_en_aon + 4 + 7 + + + xtal_ext_sel_aon + 3 + 3 + + + xtal_capcode_extra_aon + 2 + 2 + + + xtal_bk_aon + 0 + 1 + + + + + tsen + tsen. + 0x888 + + + xtal_rdy_int_sel_aon + 30 + 31 + + + xtal_inn_cfg_en_aon + 29 + 29 + + + xtal_rdy + 28 + 28 + + + tsen_refcode_rfcal + 16 + 27 + + + tsen_refcode_corner + 0 + 11 + + + + + acomp0_ctrl + acomp0_ctrl. + 0x900 + + + acomp0_muxen + 26 + 26 + + + acomp0_pos_sel + 22 + 25 + + + acomp0_neg_sel + 18 + 21 + + + acomp0_level_sel + 12 + 17 + + + acomp0_bias_prog + 10 + 11 + + + acomp0_hyst_selp + 7 + 9 + + + acomp0_hyst_seln + 4 + 6 + + + acomp0_en + 0 + 0 + + + + + acomp1_ctrl + acomp1_ctrl. + 0x904 + + + acomp1_muxen + 26 + 26 + + + acomp1_pos_sel + 22 + 25 + + + acomp1_neg_sel + 18 + 21 + + + acomp1_level_sel + 12 + 17 + + + acomp1_bias_prog + 10 + 11 + + + acomp1_hyst_selp + 7 + 9 + + + acomp1_hyst_seln + 4 + 6 + + + acomp1_en + 0 + 0 + + + + + acomp_ctrl + acomp_ctrl. + 0x908 + + + acomp_reserved + 24 + 31 + + + acomp0_out_raw + 19 + 19 + + + acomp1_out_raw + 17 + 17 + + + acomp0_test_sel + 12 + 13 + + + acomp1_test_sel + 10 + 11 + + + acomp0_test_en + 9 + 9 + + + acomp1_test_en + 8 + 8 + + + acomp0_rstn_ana + 1 + 1 + + + acomp1_rstn_ana + 0 + 0 + + + + + gpadc_reg_cmd + gpadc_reg_cmd. + 0x90C + + + gpadc_sen_test_en + 30 + 30 + + + gpadc_sen_sel + 28 + 29 + + + gpadc_chip_sen_pu + 27 + 27 + + + gpadc_micboost_32db_en + 23 + 23 + + + gpadc_mic_pga2_gain + 21 + 22 + + + gpadc_mic1_diff + 20 + 20 + + + gpadc_mic2_diff + 19 + 19 + + + gpadc_dwa_en + 18 + 18 + + + gpadc_byp_micboost + 16 + 16 + + + gpadc_micpga_en + 15 + 15 + + + gpadc_micbias_en + 14 + 14 + + + gpadc_neg_gnd + 13 + 13 + + + gpadc_pos_sel + 8 + 12 + + + gpadc_neg_sel + 3 + 7 + + + gpadc_soft_rst + 2 + 2 + + + gpadc_conv_start + 1 + 1 + + + gpadc_global_en + 0 + 0 + + + + + gpadc_reg_config1 + gpadc_reg_config1. + 0x910 + + + gpadc_v18_sel + 29 + 30 + + + gpadc_v11_sel + 27 + 28 + + + gpadc_dither_en + 26 + 26 + + + gpadc_scan_en + 25 + 25 + + + gpadc_scan_length + 21 + 24 + + + gpadc_clk_div_ratio + 18 + 20 + + + gpadc_clk_ana_inv + 17 + 17 + + + gpadc_res_sel + 2 + 4 + + + gpadc_cont_conv_en + 1 + 1 + + + gpadc_cal_os_en + 0 + 0 + + + + + gpadc_reg_config2 + gpadc_reg_config2. + 0x914 + + + gpadc_tsvbe_low + 31 + 31 + + + gpadc_dly_sel + 28 + 30 + + + gpadc_pga1_gain + 25 + 27 + + + gpadc_pga2_gain + 22 + 24 + + + gpadc_test_sel + 19 + 21 + + + gpadc_test_en + 18 + 18 + + + gpadc_bias_sel + 17 + 17 + + + gpadc_chop_mode + 15 + 16 + + + gpadc_pga_vcmi_en + 14 + 14 + + + gpadc_pga_en + 13 + 13 + + + gpadc_pga_os_cal + 9 + 12 + + + gpadc_pga_vcm + 7 + 8 + + + gpadc_ts_en + 6 + 6 + + + gpadc_tsext_sel + 5 + 5 + + + gpadc_vbat_en + 4 + 4 + + + gpadc_vref_sel + 3 + 3 + + + gpadc_diff_mode + 2 + 2 + + + + + gpadc_reg_scn_pos1 + adc converation sequence 1 + 0x918 + + + gpadc_scan_pos_5 + 25 + 29 + + + gpadc_scan_pos_4 + 20 + 24 + + + gpadc_scan_pos_3 + 15 + 19 + + + gpadc_scan_pos_2 + 10 + 14 + + + gpadc_scan_pos_1 + 5 + 9 + + + gpadc_scan_pos_0 + 0 + 4 + + + + + gpadc_reg_scn_pos2 + adc converation sequence 2 + 0x91C + + + gpadc_scan_pos_11 + 25 + 29 + + + gpadc_scan_pos_10 + 20 + 24 + + + gpadc_scan_pos_9 + 15 + 19 + + + gpadc_scan_pos_8 + 10 + 14 + + + gpadc_scan_pos_7 + 5 + 9 + + + gpadc_scan_pos_6 + 0 + 4 + + + + + gpadc_reg_scn_neg1 + adc converation sequence 3 + 0x920 + + + gpadc_scan_neg_5 + 25 + 29 + + + gpadc_scan_neg_4 + 20 + 24 + + + gpadc_scan_neg_3 + 15 + 19 + + + gpadc_scan_neg_2 + 10 + 14 + + + gpadc_scan_neg_1 + 5 + 9 + + + gpadc_scan_neg_0 + 0 + 4 + + + + + gpadc_reg_scn_neg2 + adc converation sequence 4 + 0x924 + + + gpadc_scan_neg_11 + 25 + 29 + + + gpadc_scan_neg_10 + 20 + 24 + + + gpadc_scan_neg_9 + 15 + 19 + + + gpadc_scan_neg_8 + 10 + 14 + + + gpadc_scan_neg_7 + 5 + 9 + + + gpadc_scan_neg_6 + 0 + 4 + + + + + gpadc_reg_status + gpadc_reg_status. + 0x928 + + + gpadc_reserved + 16 + 31 + + + gpadc_data_rdy + 0 + 0 + + + + + gpadc_reg_isr + gpadc_reg_isr. + 0x92C + + + gpadc_pos_satur_mask + 9 + 9 + + + gpadc_neg_satur_mask + 8 + 8 + + + gpadc_pos_satur_clr + 5 + 5 + + + gpadc_neg_satur_clr + 4 + 4 + + + gpadc_pos_satur + 1 + 1 + + + gpadc_neg_satur + 0 + 0 + + + + + gpadc_reg_result + gpadc_reg_result. + 0x930 + + + gpadc_data_out + 0 + 25 + + + + + gpadc_reg_raw_result + gpadc_reg_raw_result. + 0x934 + + + gpadc_raw_data + 0 + 11 + + + + + gpadc_reg_define + gpadc_reg_define. + 0x938 + + + gpadc_os_cal_data + 0 + 15 + + + + + hbncore_resv0 + hbncore_resv0. + 0x93C + + + hbncore_resv0_data + 0 + 31 + + + + + hbncore_resv1 + hbncore_resv1. + 0x940 + + + hbncore_resv1_data + 0 + 31 + + + + + + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/spi_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/spi_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..5c282c0b8c4cd17e62bc431b7d763f142d6c17ab --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/spi_reg.h @@ -0,0 +1,521 @@ +/** + ****************************************************************************** + * @file spi_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +#include "bl602.h" + +/* 0x0 : spi_config */ +#define SPI_CONFIG_OFFSET (0x0) +#define SPI_CR_SPI_M_EN SPI_CR_SPI_M_EN +#define SPI_CR_SPI_M_EN_POS (0U) +#define SPI_CR_SPI_M_EN_LEN (1U) +#define SPI_CR_SPI_M_EN_MSK (((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS) +#define SPI_CR_SPI_M_EN_UMSK (~(((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS)) +#define SPI_CR_SPI_S_EN SPI_CR_SPI_S_EN +#define SPI_CR_SPI_S_EN_POS (1U) +#define SPI_CR_SPI_S_EN_LEN (1U) +#define SPI_CR_SPI_S_EN_MSK (((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS) +#define SPI_CR_SPI_S_EN_UMSK (~(((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS)) +#define SPI_CR_SPI_FRAME_SIZE SPI_CR_SPI_FRAME_SIZE +#define SPI_CR_SPI_FRAME_SIZE_POS (2U) +#define SPI_CR_SPI_FRAME_SIZE_LEN (2U) +#define SPI_CR_SPI_FRAME_SIZE_MSK (((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS) +#define SPI_CR_SPI_FRAME_SIZE_UMSK (~(((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS)) +#define SPI_CR_SPI_SCLK_POL SPI_CR_SPI_SCLK_POL +#define SPI_CR_SPI_SCLK_POL_POS (4U) +#define SPI_CR_SPI_SCLK_POL_LEN (1U) +#define SPI_CR_SPI_SCLK_POL_MSK (((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS) +#define SPI_CR_SPI_SCLK_POL_UMSK (~(((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS)) +#define SPI_CR_SPI_SCLK_PH SPI_CR_SPI_SCLK_PH +#define SPI_CR_SPI_SCLK_PH_POS (5U) +#define SPI_CR_SPI_SCLK_PH_LEN (1U) +#define SPI_CR_SPI_SCLK_PH_MSK (((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS) +#define SPI_CR_SPI_SCLK_PH_UMSK (~(((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS)) +#define SPI_CR_SPI_BIT_INV SPI_CR_SPI_BIT_INV +#define SPI_CR_SPI_BIT_INV_POS (6U) +#define SPI_CR_SPI_BIT_INV_LEN (1U) +#define SPI_CR_SPI_BIT_INV_MSK (((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS) +#define SPI_CR_SPI_BIT_INV_UMSK (~(((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS)) +#define SPI_CR_SPI_BYTE_INV SPI_CR_SPI_BYTE_INV +#define SPI_CR_SPI_BYTE_INV_POS (7U) +#define SPI_CR_SPI_BYTE_INV_LEN (1U) +#define SPI_CR_SPI_BYTE_INV_MSK (((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS) +#define SPI_CR_SPI_BYTE_INV_UMSK (~(((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS)) +#define SPI_CR_SPI_RXD_IGNR_EN SPI_CR_SPI_RXD_IGNR_EN +#define SPI_CR_SPI_RXD_IGNR_EN_POS (8U) +#define SPI_CR_SPI_RXD_IGNR_EN_LEN (1U) +#define SPI_CR_SPI_RXD_IGNR_EN_MSK (((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS) +#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS)) +#define SPI_CR_SPI_M_CONT_EN SPI_CR_SPI_M_CONT_EN +#define SPI_CR_SPI_M_CONT_EN_POS (9U) +#define SPI_CR_SPI_M_CONT_EN_LEN (1U) +#define SPI_CR_SPI_M_CONT_EN_MSK (((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS) +#define SPI_CR_SPI_M_CONT_EN_UMSK (~(((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS)) +#define SPI_CR_SPI_DEG_EN SPI_CR_SPI_DEG_EN +#define SPI_CR_SPI_DEG_EN_POS (11U) +#define SPI_CR_SPI_DEG_EN_LEN (1U) +#define SPI_CR_SPI_DEG_EN_MSK (((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS) +#define SPI_CR_SPI_DEG_EN_UMSK (~(((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS)) +#define SPI_CR_SPI_DEG_CNT SPI_CR_SPI_DEG_CNT +#define SPI_CR_SPI_DEG_CNT_POS (12U) +#define SPI_CR_SPI_DEG_CNT_LEN (4U) +#define SPI_CR_SPI_DEG_CNT_MSK (((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS) +#define SPI_CR_SPI_DEG_CNT_UMSK (~(((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS)) + +/* 0x4 : spi_int_sts */ +#define SPI_INT_STS_OFFSET (0x4) +#define SPI_END_INT SPI_END_INT +#define SPI_END_INT_POS (0U) +#define SPI_END_INT_LEN (1U) +#define SPI_END_INT_MSK (((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS) +#define SPI_END_INT_UMSK (~(((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS)) +#define SPI_TXF_INT SPI_TXF_INT +#define SPI_TXF_INT_POS (1U) +#define SPI_TXF_INT_LEN (1U) +#define SPI_TXF_INT_MSK (((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS) +#define SPI_TXF_INT_UMSK (~(((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS)) +#define SPI_RXF_INT SPI_RXF_INT +#define SPI_RXF_INT_POS (2U) +#define SPI_RXF_INT_LEN (1U) +#define SPI_RXF_INT_MSK (((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS) +#define SPI_RXF_INT_UMSK (~(((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS)) +#define SPI_STO_INT SPI_STO_INT +#define SPI_STO_INT_POS (3U) +#define SPI_STO_INT_LEN (1U) +#define SPI_STO_INT_MSK (((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS) +#define SPI_STO_INT_UMSK (~(((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS)) +#define SPI_TXU_INT SPI_TXU_INT +#define SPI_TXU_INT_POS (4U) +#define SPI_TXU_INT_LEN (1U) +#define SPI_TXU_INT_MSK (((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS) +#define SPI_TXU_INT_UMSK (~(((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS)) +#define SPI_FER_INT SPI_FER_INT +#define SPI_FER_INT_POS (5U) +#define SPI_FER_INT_LEN (1U) +#define SPI_FER_INT_MSK (((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS) +#define SPI_FER_INT_UMSK (~(((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS)) +#define SPI_CR_SPI_END_MASK SPI_CR_SPI_END_MASK +#define SPI_CR_SPI_END_MASK_POS (8U) +#define SPI_CR_SPI_END_MASK_LEN (1U) +#define SPI_CR_SPI_END_MASK_MSK (((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS) +#define SPI_CR_SPI_END_MASK_UMSK (~(((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS)) +#define SPI_CR_SPI_TXF_MASK SPI_CR_SPI_TXF_MASK +#define SPI_CR_SPI_TXF_MASK_POS (9U) +#define SPI_CR_SPI_TXF_MASK_LEN (1U) +#define SPI_CR_SPI_TXF_MASK_MSK (((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS) +#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS)) +#define SPI_CR_SPI_RXF_MASK SPI_CR_SPI_RXF_MASK +#define SPI_CR_SPI_RXF_MASK_POS (10U) +#define SPI_CR_SPI_RXF_MASK_LEN (1U) +#define SPI_CR_SPI_RXF_MASK_MSK (((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS) +#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS)) +#define SPI_CR_SPI_STO_MASK SPI_CR_SPI_STO_MASK +#define SPI_CR_SPI_STO_MASK_POS (11U) +#define SPI_CR_SPI_STO_MASK_LEN (1U) +#define SPI_CR_SPI_STO_MASK_MSK (((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS) +#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS)) +#define SPI_CR_SPI_TXU_MASK SPI_CR_SPI_TXU_MASK +#define SPI_CR_SPI_TXU_MASK_POS (12U) +#define SPI_CR_SPI_TXU_MASK_LEN (1U) +#define SPI_CR_SPI_TXU_MASK_MSK (((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS) +#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS)) +#define SPI_CR_SPI_FER_MASK SPI_CR_SPI_FER_MASK +#define SPI_CR_SPI_FER_MASK_POS (13U) +#define SPI_CR_SPI_FER_MASK_LEN (1U) +#define SPI_CR_SPI_FER_MASK_MSK (((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS) +#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS)) +#define SPI_CR_SPI_END_CLR SPI_CR_SPI_END_CLR +#define SPI_CR_SPI_END_CLR_POS (16U) +#define SPI_CR_SPI_END_CLR_LEN (1U) +#define SPI_CR_SPI_END_CLR_MSK (((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS) +#define SPI_CR_SPI_END_CLR_UMSK (~(((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS)) +#define SPI_CR_SPI_STO_CLR SPI_CR_SPI_STO_CLR +#define SPI_CR_SPI_STO_CLR_POS (19U) +#define SPI_CR_SPI_STO_CLR_LEN (1U) +#define SPI_CR_SPI_STO_CLR_MSK (((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS) +#define SPI_CR_SPI_STO_CLR_UMSK (~(((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS)) +#define SPI_CR_SPI_TXU_CLR SPI_CR_SPI_TXU_CLR +#define SPI_CR_SPI_TXU_CLR_POS (20U) +#define SPI_CR_SPI_TXU_CLR_LEN (1U) +#define SPI_CR_SPI_TXU_CLR_MSK (((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS) +#define SPI_CR_SPI_TXU_CLR_UMSK (~(((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS)) +#define SPI_CR_SPI_END_EN SPI_CR_SPI_END_EN +#define SPI_CR_SPI_END_EN_POS (24U) +#define SPI_CR_SPI_END_EN_LEN (1U) +#define SPI_CR_SPI_END_EN_MSK (((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS) +#define SPI_CR_SPI_END_EN_UMSK (~(((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS)) +#define SPI_CR_SPI_TXF_EN SPI_CR_SPI_TXF_EN +#define SPI_CR_SPI_TXF_EN_POS (25U) +#define SPI_CR_SPI_TXF_EN_LEN (1U) +#define SPI_CR_SPI_TXF_EN_MSK (((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS) +#define SPI_CR_SPI_TXF_EN_UMSK (~(((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS)) +#define SPI_CR_SPI_RXF_EN SPI_CR_SPI_RXF_EN +#define SPI_CR_SPI_RXF_EN_POS (26U) +#define SPI_CR_SPI_RXF_EN_LEN (1U) +#define SPI_CR_SPI_RXF_EN_MSK (((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS) +#define SPI_CR_SPI_RXF_EN_UMSK (~(((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS)) +#define SPI_CR_SPI_STO_EN SPI_CR_SPI_STO_EN +#define SPI_CR_SPI_STO_EN_POS (27U) +#define SPI_CR_SPI_STO_EN_LEN (1U) +#define SPI_CR_SPI_STO_EN_MSK (((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS) +#define SPI_CR_SPI_STO_EN_UMSK (~(((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS)) +#define SPI_CR_SPI_TXU_EN SPI_CR_SPI_TXU_EN +#define SPI_CR_SPI_TXU_EN_POS (28U) +#define SPI_CR_SPI_TXU_EN_LEN (1U) +#define SPI_CR_SPI_TXU_EN_MSK (((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS) +#define SPI_CR_SPI_TXU_EN_UMSK (~(((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS)) +#define SPI_CR_SPI_FER_EN SPI_CR_SPI_FER_EN +#define SPI_CR_SPI_FER_EN_POS (29U) +#define SPI_CR_SPI_FER_EN_LEN (1U) +#define SPI_CR_SPI_FER_EN_MSK (((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS) +#define SPI_CR_SPI_FER_EN_UMSK (~(((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS)) + +/* 0x8 : spi_bus_busy */ +#define SPI_BUS_BUSY_OFFSET (0x8) +#define SPI_STS_SPI_BUS_BUSY SPI_STS_SPI_BUS_BUSY +#define SPI_STS_SPI_BUS_BUSY_POS (0U) +#define SPI_STS_SPI_BUS_BUSY_LEN (1U) +#define SPI_STS_SPI_BUS_BUSY_MSK (((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS) +#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS)) + +/* 0x10 : spi_prd_0 */ +#define SPI_PRD_0_OFFSET (0x10) +#define SPI_CR_SPI_PRD_S SPI_CR_SPI_PRD_S +#define SPI_CR_SPI_PRD_S_POS (0U) +#define SPI_CR_SPI_PRD_S_LEN (8U) +#define SPI_CR_SPI_PRD_S_MSK (((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS) +#define SPI_CR_SPI_PRD_S_UMSK (~(((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS)) +#define SPI_CR_SPI_PRD_P SPI_CR_SPI_PRD_P +#define SPI_CR_SPI_PRD_P_POS (8U) +#define SPI_CR_SPI_PRD_P_LEN (8U) +#define SPI_CR_SPI_PRD_P_MSK (((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS) +#define SPI_CR_SPI_PRD_P_UMSK (~(((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS)) +#define SPI_CR_SPI_PRD_D_PH_0 SPI_CR_SPI_PRD_D_PH_0 +#define SPI_CR_SPI_PRD_D_PH_0_POS (16U) +#define SPI_CR_SPI_PRD_D_PH_0_LEN (8U) +#define SPI_CR_SPI_PRD_D_PH_0_MSK (((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS) +#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS)) +#define SPI_CR_SPI_PRD_D_PH_1 SPI_CR_SPI_PRD_D_PH_1 +#define SPI_CR_SPI_PRD_D_PH_1_POS (24U) +#define SPI_CR_SPI_PRD_D_PH_1_LEN (8U) +#define SPI_CR_SPI_PRD_D_PH_1_MSK (((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS) +#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS)) + +/* 0x14 : spi_prd_1 */ +#define SPI_PRD_1_OFFSET (0x14) +#define SPI_CR_SPI_PRD_I SPI_CR_SPI_PRD_I +#define SPI_CR_SPI_PRD_I_POS (0U) +#define SPI_CR_SPI_PRD_I_LEN (8U) +#define SPI_CR_SPI_PRD_I_MSK (((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS) +#define SPI_CR_SPI_PRD_I_UMSK (~(((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS)) + +/* 0x18 : spi_rxd_ignr */ +#define SPI_RXD_IGNR_OFFSET (0x18) +#define SPI_CR_SPI_RXD_IGNR_P SPI_CR_SPI_RXD_IGNR_P +#define SPI_CR_SPI_RXD_IGNR_P_POS (0U) +#define SPI_CR_SPI_RXD_IGNR_P_LEN (5U) +#define SPI_CR_SPI_RXD_IGNR_P_MSK (((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS) +#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS)) +#define SPI_CR_SPI_RXD_IGNR_S SPI_CR_SPI_RXD_IGNR_S +#define SPI_CR_SPI_RXD_IGNR_S_POS (16U) +#define SPI_CR_SPI_RXD_IGNR_S_LEN (5U) +#define SPI_CR_SPI_RXD_IGNR_S_MSK (((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS) +#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS)) + +/* 0x1C : spi_sto_value */ +#define SPI_STO_VALUE_OFFSET (0x1C) +#define SPI_CR_SPI_STO_VALUE SPI_CR_SPI_STO_VALUE +#define SPI_CR_SPI_STO_VALUE_POS (0U) +#define SPI_CR_SPI_STO_VALUE_LEN (12U) +#define SPI_CR_SPI_STO_VALUE_MSK (((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS) +#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS)) + +/* 0x80 : spi_fifo_config_0 */ +#define SPI_FIFO_CONFIG_0_OFFSET (0x80) +#define SPI_DMA_TX_EN SPI_DMA_TX_EN +#define SPI_DMA_TX_EN_POS (0U) +#define SPI_DMA_TX_EN_LEN (1U) +#define SPI_DMA_TX_EN_MSK (((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS) +#define SPI_DMA_TX_EN_UMSK (~(((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS)) +#define SPI_DMA_RX_EN SPI_DMA_RX_EN +#define SPI_DMA_RX_EN_POS (1U) +#define SPI_DMA_RX_EN_LEN (1U) +#define SPI_DMA_RX_EN_MSK (((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS) +#define SPI_DMA_RX_EN_UMSK (~(((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS)) +#define SPI_TX_FIFO_CLR SPI_TX_FIFO_CLR +#define SPI_TX_FIFO_CLR_POS (2U) +#define SPI_TX_FIFO_CLR_LEN (1U) +#define SPI_TX_FIFO_CLR_MSK (((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS) +#define SPI_TX_FIFO_CLR_UMSK (~(((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS)) +#define SPI_RX_FIFO_CLR SPI_RX_FIFO_CLR +#define SPI_RX_FIFO_CLR_POS (3U) +#define SPI_RX_FIFO_CLR_LEN (1U) +#define SPI_RX_FIFO_CLR_MSK (((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS) +#define SPI_RX_FIFO_CLR_UMSK (~(((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS)) +#define SPI_TX_FIFO_OVERFLOW SPI_TX_FIFO_OVERFLOW +#define SPI_TX_FIFO_OVERFLOW_POS (4U) +#define SPI_TX_FIFO_OVERFLOW_LEN (1U) +#define SPI_TX_FIFO_OVERFLOW_MSK (((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS) +#define SPI_TX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS)) +#define SPI_TX_FIFO_UNDERFLOW SPI_TX_FIFO_UNDERFLOW +#define SPI_TX_FIFO_UNDERFLOW_POS (5U) +#define SPI_TX_FIFO_UNDERFLOW_LEN (1U) +#define SPI_TX_FIFO_UNDERFLOW_MSK (((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS) +#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS)) +#define SPI_RX_FIFO_OVERFLOW SPI_RX_FIFO_OVERFLOW +#define SPI_RX_FIFO_OVERFLOW_POS (6U) +#define SPI_RX_FIFO_OVERFLOW_LEN (1U) +#define SPI_RX_FIFO_OVERFLOW_MSK (((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS) +#define SPI_RX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS)) +#define SPI_RX_FIFO_UNDERFLOW SPI_RX_FIFO_UNDERFLOW +#define SPI_RX_FIFO_UNDERFLOW_POS (7U) +#define SPI_RX_FIFO_UNDERFLOW_LEN (1U) +#define SPI_RX_FIFO_UNDERFLOW_MSK (((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS) +#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS)) + +/* 0x84 : spi_fifo_config_1 */ +#define SPI_FIFO_CONFIG_1_OFFSET (0x84) +#define SPI_TX_FIFO_CNT SPI_TX_FIFO_CNT +#define SPI_TX_FIFO_CNT_POS (0U) +#define SPI_TX_FIFO_CNT_LEN (3U) +#define SPI_TX_FIFO_CNT_MSK (((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS) +#define SPI_TX_FIFO_CNT_UMSK (~(((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS)) +#define SPI_RX_FIFO_CNT SPI_RX_FIFO_CNT +#define SPI_RX_FIFO_CNT_POS (8U) +#define SPI_RX_FIFO_CNT_LEN (3U) +#define SPI_RX_FIFO_CNT_MSK (((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS) +#define SPI_RX_FIFO_CNT_UMSK (~(((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS)) +#define SPI_TX_FIFO_TH SPI_TX_FIFO_TH +#define SPI_TX_FIFO_TH_POS (16U) +#define SPI_TX_FIFO_TH_LEN (2U) +#define SPI_TX_FIFO_TH_MSK (((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS) +#define SPI_TX_FIFO_TH_UMSK (~(((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS)) +#define SPI_RX_FIFO_TH SPI_RX_FIFO_TH +#define SPI_RX_FIFO_TH_POS (24U) +#define SPI_RX_FIFO_TH_LEN (2U) +#define SPI_RX_FIFO_TH_MSK (((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS) +#define SPI_RX_FIFO_TH_UMSK (~(((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS)) + +/* 0x88 : spi_fifo_wdata */ +#define SPI_FIFO_WDATA_OFFSET (0x88) +#define SPI_FIFO_WDATA SPI_FIFO_WDATA +#define SPI_FIFO_WDATA_POS (0U) +#define SPI_FIFO_WDATA_LEN (32U) +#define SPI_FIFO_WDATA_MSK (((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS) +#define SPI_FIFO_WDATA_UMSK (~(((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS)) + +/* 0x8C : spi_fifo_rdata */ +#define SPI_FIFO_RDATA_OFFSET (0x8C) +#define SPI_FIFO_RDATA SPI_FIFO_RDATA +#define SPI_FIFO_RDATA_POS (0U) +#define SPI_FIFO_RDATA_LEN (32U) +#define SPI_FIFO_RDATA_MSK (((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS) +#define SPI_FIFO_RDATA_UMSK (~(((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS)) + +struct spi_reg { + /* 0x0 : spi_config */ + union { + struct + { + uint32_t cr_spi_m_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_spi_s_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_spi_frame_size : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t cr_spi_sclk_pol : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_spi_sclk_ph : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_spi_bit_inv : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_spi_byte_inv : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_spi_rxd_ignr_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t cr_spi_m_cont_en : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ + uint32_t cr_spi_deg_en : 1; /* [ 11], r/w, 0x0 */ + uint32_t cr_spi_deg_cnt : 4; /* [15:12], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_config; + + /* 0x4 : spi_int_sts */ + union { + struct + { + uint32_t spi_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t spi_txf_int : 1; /* [ 1], r, 0x0 */ + uint32_t spi_rxf_int : 1; /* [ 2], r, 0x0 */ + uint32_t spi_sto_int : 1; /* [ 3], r, 0x0 */ + uint32_t spi_txu_int : 1; /* [ 4], r, 0x0 */ + uint32_t spi_fer_int : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t cr_spi_end_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_spi_txf_mask : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_spi_rxf_mask : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_spi_sto_mask : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_spi_txu_mask : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_spi_fer_mask : 1; /* [ 13], r/w, 0x1 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t cr_spi_end_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t cr_spi_sto_clr : 1; /* [ 19], w1c, 0x0 */ + uint32_t cr_spi_txu_clr : 1; /* [ 20], w1c, 0x0 */ + uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t cr_spi_end_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t cr_spi_txf_en : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_spi_rxf_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t cr_spi_sto_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t cr_spi_txu_en : 1; /* [ 28], r/w, 0x1 */ + uint32_t cr_spi_fer_en : 1; /* [ 29], r/w, 0x1 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_int_sts; + + /* 0x8 : spi_bus_busy */ + union { + struct + { + uint32_t sts_spi_bus_busy : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_bus_busy; + + /* 0xc reserved */ + uint8_t RESERVED0xc[4]; + + /* 0x10 : spi_prd_0 */ + union { + struct + { + uint32_t cr_spi_prd_s : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t cr_spi_prd_p : 8; /* [15: 8], r/w, 0xf */ + uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */ + uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } spi_prd_0; + + /* 0x14 : spi_prd_1 */ + union { + struct + { + uint32_t cr_spi_prd_i : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_prd_1; + + /* 0x18 : spi_rxd_ignr */ + union { + struct + { + uint32_t cr_spi_rxd_ignr_p : 5; /* [ 4: 0], r/w, 0x0 */ + uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ + uint32_t cr_spi_rxd_ignr_s : 5; /* [20:16], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_rxd_ignr; + + /* 0x1C : spi_sto_value */ + union { + struct + { + uint32_t cr_spi_sto_value : 12; /* [11: 0], r/w, 0xfff */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_sto_value; + + /* 0x20 reserved */ + uint8_t RESERVED0x20[96]; + + /* 0x80 : spi_fifo_config_0 */ + union { + struct + { + uint32_t spi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t spi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_fifo_config_0; + + /* 0x84 : spi_fifo_config_1 */ + union { + struct + { + uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */ + uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ + uint32_t rx_fifo_cnt : 3; /* [10: 8], r, 0x0 */ + uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ + uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */ + uint32_t rx_fifo_th : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_fifo_config_1; + + /* 0x88 : spi_fifo_wdata */ + union { + struct + { + uint32_t spi_fifo_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } spi_fifo_wdata; + + /* 0x8C : spi_fifo_rdata */ + union { + struct + { + uint32_t spi_fifo_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } spi_fifo_rdata; +}; + +typedef volatile struct spi_reg spi_reg_t; + +#endif /* __SPI_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/timer_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/timer_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..548ad8e523fc8ad4c9e1e00a09de3f90f1e1275e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/timer_reg.h @@ -0,0 +1,852 @@ +/** + ****************************************************************************** + * @file timer_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#include "bl602.h" + +/* 0x0 : TCCR */ +#define TIMER_TCCR_OFFSET (0x0) +#define TIMER_CS_1 TIMER_CS_1 +#define TIMER_CS_1_POS (2U) +#define TIMER_CS_1_LEN (2U) +#define TIMER_CS_1_MSK (((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS) +#define TIMER_CS_1_UMSK (~(((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS)) +#define TIMER_CS_2 TIMER_CS_2 +#define TIMER_CS_2_POS (5U) +#define TIMER_CS_2_LEN (2U) +#define TIMER_CS_2_MSK (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS) +#define TIMER_CS_2_UMSK (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)) +#define TIMER_CS_WDT TIMER_CS_WDT +#define TIMER_CS_WDT_POS (8U) +#define TIMER_CS_WDT_LEN (2U) +#define TIMER_CS_WDT_MSK (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS) +#define TIMER_CS_WDT_UMSK (~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)) + +/* 0x10 : TMR2_0 */ +#define TIMER_TMR2_0_OFFSET (0x10) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x14 : TMR2_1 */ +#define TIMER_TMR2_1_OFFSET (0x14) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x18 : TMR2_2 */ +#define TIMER_TMR2_2_OFFSET (0x18) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x1C : TMR3_0 */ +#define TIMER_TMR3_0_OFFSET (0x1C) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x20 : TMR3_1 */ +#define TIMER_TMR3_1_OFFSET (0x20) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x24 : TMR3_2 */ +#define TIMER_TMR3_2_OFFSET (0x24) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x2C : TCR2 */ +#define TIMER_TCR2_OFFSET (0x2C) +#define TIMER_TCR TIMER_TCR +#define TIMER_TCR_POS (0U) +#define TIMER_TCR_LEN (32U) +#define TIMER_TCR_MSK (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS) +#define TIMER_TCR_UMSK (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)) + +/* 0x30 : TCR3 */ +#define TIMER_TCR3_OFFSET (0x30) +#define TIMER_TCR3_COUNTER TIMER_TCR3_COUNTER +#define TIMER_TCR3_COUNTER_POS (0U) +#define TIMER_TCR3_COUNTER_LEN (32U) +#define TIMER_TCR3_COUNTER_MSK (((1U << TIMER_TCR3_COUNTER_LEN) - 1) << TIMER_TCR3_COUNTER_POS) +#define TIMER_TCR3_COUNTER_UMSK (~(((1U << TIMER_TCR3_COUNTER_LEN) - 1) << TIMER_TCR3_COUNTER_POS)) + +/* 0x38 : TMSR2 */ +#define TIMER_TMSR2_OFFSET (0x38) +#define TIMER_TMSR_0 TIMER_TMSR_0 +#define TIMER_TMSR_0_POS (0U) +#define TIMER_TMSR_0_LEN (1U) +#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS) +#define TIMER_TMSR_0_UMSK (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)) +#define TIMER_TMSR_1 TIMER_TMSR_1 +#define TIMER_TMSR_1_POS (1U) +#define TIMER_TMSR_1_LEN (1U) +#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS) +#define TIMER_TMSR_1_UMSK (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)) +#define TIMER_TMSR_2 TIMER_TMSR_2 +#define TIMER_TMSR_2_POS (2U) +#define TIMER_TMSR_2_LEN (1U) +#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS) +#define TIMER_TMSR_2_UMSK (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)) + +/* 0x3C : TMSR3 */ +#define TIMER_TMSR3_OFFSET (0x3C) +#define TIMER_TMSR_0 TIMER_TMSR_0 +#define TIMER_TMSR_0_POS (0U) +#define TIMER_TMSR_0_LEN (1U) +#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS) +#define TIMER_TMSR_0_UMSK (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)) +#define TIMER_TMSR_1 TIMER_TMSR_1 +#define TIMER_TMSR_1_POS (1U) +#define TIMER_TMSR_1_LEN (1U) +#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS) +#define TIMER_TMSR_1_UMSK (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)) +#define TIMER_TMSR_2 TIMER_TMSR_2 +#define TIMER_TMSR_2_POS (2U) +#define TIMER_TMSR_2_LEN (1U) +#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS) +#define TIMER_TMSR_2_UMSK (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)) + +/* 0x44 : TIER2 */ +#define TIMER_TIER2_OFFSET (0x44) +#define TIMER_TIER_0 TIMER_TIER_0 +#define TIMER_TIER_0_POS (0U) +#define TIMER_TIER_0_LEN (1U) +#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS) +#define TIMER_TIER_0_UMSK (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)) +#define TIMER_TIER_1 TIMER_TIER_1 +#define TIMER_TIER_1_POS (1U) +#define TIMER_TIER_1_LEN (1U) +#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS) +#define TIMER_TIER_1_UMSK (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)) +#define TIMER_TIER_2 TIMER_TIER_2 +#define TIMER_TIER_2_POS (2U) +#define TIMER_TIER_2_LEN (1U) +#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS) +#define TIMER_TIER_2_UMSK (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)) + +/* 0x48 : TIER3 */ +#define TIMER_TIER3_OFFSET (0x48) +#define TIMER_TIER_0 TIMER_TIER_0 +#define TIMER_TIER_0_POS (0U) +#define TIMER_TIER_0_LEN (1U) +#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS) +#define TIMER_TIER_0_UMSK (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)) +#define TIMER_TIER_1 TIMER_TIER_1 +#define TIMER_TIER_1_POS (1U) +#define TIMER_TIER_1_LEN (1U) +#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS) +#define TIMER_TIER_1_UMSK (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)) +#define TIMER_TIER_2 TIMER_TIER_2 +#define TIMER_TIER_2_POS (2U) +#define TIMER_TIER_2_LEN (1U) +#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS) +#define TIMER_TIER_2_UMSK (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)) + +/* 0x50 : TPLVR2 */ +#define TIMER_TPLVR2_OFFSET (0x50) +#define TIMER_TPLVR TIMER_TPLVR +#define TIMER_TPLVR_POS (0U) +#define TIMER_TPLVR_LEN (32U) +#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS) +#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)) + +/* 0x54 : TPLVR3 */ +#define TIMER_TPLVR3_OFFSET (0x54) +#define TIMER_TPLVR TIMER_TPLVR +#define TIMER_TPLVR_POS (0U) +#define TIMER_TPLVR_LEN (32U) +#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS) +#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)) + +/* 0x5C : TPLCR2 */ +#define TIMER_TPLCR2_OFFSET (0x5C) +#define TIMER_TPLCR TIMER_TPLCR +#define TIMER_TPLCR_POS (0U) +#define TIMER_TPLCR_LEN (2U) +#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS) +#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)) + +/* 0x60 : TPLCR3 */ +#define TIMER_TPLCR3_OFFSET (0x60) +#define TIMER_TPLCR TIMER_TPLCR +#define TIMER_TPLCR_POS (0U) +#define TIMER_TPLCR_LEN (2U) +#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS) +#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)) + +/* 0x64 : WMER */ +#define TIMER_WMER_OFFSET (0x64) +#define TIMER_WE TIMER_WE +#define TIMER_WE_POS (0U) +#define TIMER_WE_LEN (1U) +#define TIMER_WE_MSK (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS) +#define TIMER_WE_UMSK (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)) +#define TIMER_WRIE TIMER_WRIE +#define TIMER_WRIE_POS (1U) +#define TIMER_WRIE_LEN (1U) +#define TIMER_WRIE_MSK (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS) +#define TIMER_WRIE_UMSK (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)) + +/* 0x68 : WMR */ +#define TIMER_WMR_OFFSET (0x68) +#define TIMER_WMR TIMER_WMR +#define TIMER_WMR_POS (0U) +#define TIMER_WMR_LEN (16U) +#define TIMER_WMR_MSK (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS) +#define TIMER_WMR_UMSK (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)) + +/* 0x6C : WVR */ +#define TIMER_WVR_OFFSET (0x6C) +#define TIMER_WVR TIMER_WVR +#define TIMER_WVR_POS (0U) +#define TIMER_WVR_LEN (16U) +#define TIMER_WVR_MSK (((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS) +#define TIMER_WVR_UMSK (~(((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS)) + +/* 0x70 : WSR */ +#define TIMER_WSR_OFFSET (0x70) +#define TIMER_WTS TIMER_WTS +#define TIMER_WTS_POS (0U) +#define TIMER_WTS_LEN (1U) +#define TIMER_WTS_MSK (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS) +#define TIMER_WTS_UMSK (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)) + +/* 0x78 : TICR2 */ +#define TIMER_TICR2_OFFSET (0x78) +#define TIMER_TCLR_0 TIMER_TCLR_0 +#define TIMER_TCLR_0_POS (0U) +#define TIMER_TCLR_0_LEN (1U) +#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS) +#define TIMER_TCLR_0_UMSK (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)) +#define TIMER_TCLR_1 TIMER_TCLR_1 +#define TIMER_TCLR_1_POS (1U) +#define TIMER_TCLR_1_LEN (1U) +#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS) +#define TIMER_TCLR_1_UMSK (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)) +#define TIMER_TCLR_2 TIMER_TCLR_2 +#define TIMER_TCLR_2_POS (2U) +#define TIMER_TCLR_2_LEN (1U) +#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS) +#define TIMER_TCLR_2_UMSK (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)) + +/* 0x7C : TICR3 */ +#define TIMER_TICR3_OFFSET (0x7C) +#define TIMER_TCLR_0 TIMER_TCLR_0 +#define TIMER_TCLR_0_POS (0U) +#define TIMER_TCLR_0_LEN (1U) +#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS) +#define TIMER_TCLR_0_UMSK (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)) +#define TIMER_TCLR_1 TIMER_TCLR_1 +#define TIMER_TCLR_1_POS (1U) +#define TIMER_TCLR_1_LEN (1U) +#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS) +#define TIMER_TCLR_1_UMSK (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)) +#define TIMER_TCLR_2 TIMER_TCLR_2 +#define TIMER_TCLR_2_POS (2U) +#define TIMER_TCLR_2_LEN (1U) +#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS) +#define TIMER_TCLR_2_UMSK (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)) + +/* 0x80 : WICR */ +#define TIMER_WICR_OFFSET (0x80) +#define TIMER_WICLR TIMER_WICLR +#define TIMER_WICLR_POS (0U) +#define TIMER_WICLR_LEN (1U) +#define TIMER_WICLR_MSK (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS) +#define TIMER_WICLR_UMSK (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)) + +/* 0x84 : TCER */ +#define TIMER_TCER_OFFSET (0x84) +#define TIMER2_EN TIMER2_EN +#define TIMER2_EN_POS (1U) +#define TIMER2_EN_LEN (1U) +#define TIMER2_EN_MSK (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS) +#define TIMER2_EN_UMSK (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)) +#define TIMER3_EN TIMER3_EN +#define TIMER3_EN_POS (2U) +#define TIMER3_EN_LEN (1U) +#define TIMER3_EN_MSK (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS) +#define TIMER3_EN_UMSK (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)) + +/* 0x88 : TCMR */ +#define TIMER_TCMR_OFFSET (0x88) +#define TIMER2_MODE TIMER2_MODE +#define TIMER2_MODE_POS (1U) +#define TIMER2_MODE_LEN (1U) +#define TIMER2_MODE_MSK (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS) +#define TIMER2_MODE_UMSK (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)) +#define TIMER3_MODE TIMER3_MODE +#define TIMER3_MODE_POS (2U) +#define TIMER3_MODE_LEN (1U) +#define TIMER3_MODE_MSK (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS) +#define TIMER3_MODE_UMSK (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)) + +/* 0x90 : TILR2 */ +#define TIMER_TILR2_OFFSET (0x90) +#define TIMER_TILR_0 TIMER_TILR_0 +#define TIMER_TILR_0_POS (0U) +#define TIMER_TILR_0_LEN (1U) +#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS) +#define TIMER_TILR_0_UMSK (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)) +#define TIMER_TILR_1 TIMER_TILR_1 +#define TIMER_TILR_1_POS (1U) +#define TIMER_TILR_1_LEN (1U) +#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS) +#define TIMER_TILR_1_UMSK (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)) +#define TIMER_TILR_2 TIMER_TILR_2 +#define TIMER_TILR_2_POS (2U) +#define TIMER_TILR_2_LEN (1U) +#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS) +#define TIMER_TILR_2_UMSK (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)) + +/* 0x94 : TILR3 */ +#define TIMER_TILR3_OFFSET (0x94) +#define TIMER_TILR_0 TIMER_TILR_0 +#define TIMER_TILR_0_POS (0U) +#define TIMER_TILR_0_LEN (1U) +#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS) +#define TIMER_TILR_0_UMSK (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)) +#define TIMER_TILR_1 TIMER_TILR_1 +#define TIMER_TILR_1_POS (1U) +#define TIMER_TILR_1_LEN (1U) +#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS) +#define TIMER_TILR_1_UMSK (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)) +#define TIMER_TILR_2 TIMER_TILR_2 +#define TIMER_TILR_2_POS (2U) +#define TIMER_TILR_2_LEN (1U) +#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS) +#define TIMER_TILR_2_UMSK (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)) + +/* 0x98 : WCR */ +#define TIMER_WCR_OFFSET (0x98) +#define TIMER_WCR TIMER_WCR +#define TIMER_WCR_POS (0U) +#define TIMER_WCR_LEN (1U) +#define TIMER_WCR_MSK (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS) +#define TIMER_WCR_UMSK (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)) + +/* 0x9C : WFAR */ +#define TIMER_WFAR_OFFSET (0x9C) +#define TIMER_WFAR TIMER_WFAR +#define TIMER_WFAR_POS (0U) +#define TIMER_WFAR_LEN (16U) +#define TIMER_WFAR_MSK (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS) +#define TIMER_WFAR_UMSK (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)) + +/* 0xA0 : WSAR */ +#define TIMER_WSAR_OFFSET (0xA0) +#define TIMER_WSAR TIMER_WSAR +#define TIMER_WSAR_POS (0U) +#define TIMER_WSAR_LEN (16U) +#define TIMER_WSAR_MSK (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS) +#define TIMER_WSAR_UMSK (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)) + +/* 0xA8 : TCVWR2 */ +#define TIMER_TCVWR2_OFFSET (0xA8) +#define TIMER_TCVWR TIMER_TCVWR +#define TIMER_TCVWR_POS (0U) +#define TIMER_TCVWR_LEN (32U) +#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS) +#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)) + +/* 0xAC : TCVWR3 */ +#define TIMER_TCVWR3_OFFSET (0xAC) +#define TIMER_TCVWR TIMER_TCVWR +#define TIMER_TCVWR_POS (0U) +#define TIMER_TCVWR_LEN (32U) +#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS) +#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)) + +/* 0xB4 : TCVSYN2 */ +#define TIMER_TCVSYN2_OFFSET (0xB4) +#define TIMER_TCVSYN2 TIMER_TCVSYN2 +#define TIMER_TCVSYN2_POS (0U) +#define TIMER_TCVSYN2_LEN (32U) +#define TIMER_TCVSYN2_MSK (((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS) +#define TIMER_TCVSYN2_UMSK (~(((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS)) + +/* 0xB8 : TCVSYN3 */ +#define TIMER_TCVSYN3_OFFSET (0xB8) +#define TIMER_TCVSYN3 TIMER_TCVSYN3 +#define TIMER_TCVSYN3_POS (0U) +#define TIMER_TCVSYN3_LEN (32U) +#define TIMER_TCVSYN3_MSK (((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS) +#define TIMER_TCVSYN3_UMSK (~(((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS)) + +/* 0xBC : TCDR */ +#define TIMER_TCDR_OFFSET (0xBC) +#define TIMER_TCDR2 TIMER_TCDR2 +#define TIMER_TCDR2_POS (8U) +#define TIMER_TCDR2_LEN (8U) +#define TIMER_TCDR2_MSK (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS) +#define TIMER_TCDR2_UMSK (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)) +#define TIMER_TCDR3 TIMER_TCDR3 +#define TIMER_TCDR3_POS (16U) +#define TIMER_TCDR3_LEN (8U) +#define TIMER_TCDR3_MSK (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS) +#define TIMER_TCDR3_UMSK (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)) +#define TIMER_WCDR TIMER_WCDR +#define TIMER_WCDR_POS (24U) +#define TIMER_WCDR_LEN (8U) +#define TIMER_WCDR_MSK (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS) +#define TIMER_WCDR_UMSK (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)) + +struct timer_reg { + /* 0x0 : TCCR */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t cs_1 : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t RESERVED_4 : 1; /* [ 4], rsvd, 0x0 */ + uint32_t cs_2 : 2; /* [ 6: 5], r/w, 0x0 */ + uint32_t RESERVED_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cs_wdt : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TCCR; + + /* 0x4 reserved */ + uint8_t RESERVED0x4[12]; + + /* 0x10 : TMR2_0 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR2_0; + + /* 0x14 : TMR2_1 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR2_1; + + /* 0x18 : TMR2_2 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR2_2; + + /* 0x1C : TMR3_0 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR3_0; + + /* 0x20 : TMR3_1 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR3_1; + + /* 0x24 : TMR3_2 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR3_2; + + /* 0x28 reserved */ + uint8_t RESERVED0x28[4]; + + /* 0x2C : TCR2 */ + union { + struct + { + uint32_t tcr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCR2; + + /* 0x30 : TCR3 */ + union { + struct + { + uint32_t tcr3_counter : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCR3; + + /* 0x34 reserved */ + uint8_t RESERVED0x34[4]; + + /* 0x38 : TMSR2 */ + union { + struct + { + uint32_t tmsr_0 : 1; /* [ 0], r, 0x0 */ + uint32_t tmsr_1 : 1; /* [ 1], r, 0x0 */ + uint32_t tmsr_2 : 1; /* [ 2], r, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TMSR2; + + /* 0x3C : TMSR3 */ + union { + struct + { + uint32_t tmsr_0 : 1; /* [ 0], r, 0x0 */ + uint32_t tmsr_1 : 1; /* [ 1], r, 0x0 */ + uint32_t tmsr_2 : 1; /* [ 2], r, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TMSR3; + + /* 0x40 reserved */ + uint8_t RESERVED0x40[4]; + + /* 0x44 : TIER2 */ + union { + struct + { + uint32_t tier_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t tier_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t tier_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TIER2; + + /* 0x48 : TIER3 */ + union { + struct + { + uint32_t tier_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t tier_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t tier_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TIER3; + + /* 0x4c reserved */ + uint8_t RESERVED0x4c[4]; + + /* 0x50 : TPLVR2 */ + union { + struct + { + uint32_t tplvr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } TPLVR2; + + /* 0x54 : TPLVR3 */ + union { + struct + { + uint32_t tplvr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } TPLVR3; + + /* 0x58 reserved */ + uint8_t RESERVED0x58[4]; + + /* 0x5C : TPLCR2 */ + union { + struct + { + uint32_t tplcr : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TPLCR2; + + /* 0x60 : TPLCR3 */ + union { + struct + { + uint32_t tplcr : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TPLCR3; + + /* 0x64 : WMER */ + union { + struct + { + uint32_t we : 1; /* [ 0], r/w, 0x0 */ + uint32_t wrie : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WMER; + + /* 0x68 : WMR */ + union { + struct + { + uint32_t wmr : 16; /* [15: 0], r/w, 0xffff */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WMR; + + /* 0x6C : WVR */ + union { + struct + { + uint32_t wvr : 16; /* [15: 0], r, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WVR; + + /* 0x70 : WSR */ + union { + struct + { + uint32_t wts : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WSR; + + /* 0x74 reserved */ + uint8_t RESERVED0x74[4]; + + /* 0x78 : TICR2 */ + union { + struct + { + uint32_t tclr_0 : 1; /* [ 0], w, 0x0 */ + uint32_t tclr_1 : 1; /* [ 1], w, 0x0 */ + uint32_t tclr_2 : 1; /* [ 2], w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TICR2; + + /* 0x7C : TICR3 */ + union { + struct + { + uint32_t tclr_0 : 1; /* [ 0], w, 0x0 */ + uint32_t tclr_1 : 1; /* [ 1], w, 0x0 */ + uint32_t tclr_2 : 1; /* [ 2], w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TICR3; + + /* 0x80 : WICR */ + union { + struct + { + uint32_t wiclr : 1; /* [ 0], w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WICR; + + /* 0x84 : TCER */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t timer2_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t timer3_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TCER; + + /* 0x88 : TCMR */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t timer2_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t timer3_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TCMR; + + /* 0x8c reserved */ + uint8_t RESERVED0x8c[4]; + + /* 0x90 : TILR2 */ + union { + struct + { + uint32_t tilr_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t tilr_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t tilr_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TILR2; + + /* 0x94 : TILR3 */ + union { + struct + { + uint32_t tilr_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t tilr_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t tilr_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TILR3; + + /* 0x98 : WCR */ + union { + struct + { + uint32_t wcr : 1; /* [ 0], w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WCR; + + /* 0x9C : WFAR */ + union { + struct + { + uint32_t wfar : 16; /* [15: 0], w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WFAR; + + /* 0xA0 : WSAR */ + union { + struct + { + uint32_t wsar : 16; /* [15: 0], w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WSAR; + + /* 0xa4 reserved */ + uint8_t RESERVED0xa4[4]; + + /* 0xA8 : TCVWR2 */ + union { + struct + { + uint32_t tcvwr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCVWR2; + + /* 0xAC : TCVWR3 */ + union { + struct + { + uint32_t tcvwr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCVWR3; + + /* 0xb0 reserved */ + uint8_t RESERVED0xb0[4]; + + /* 0xB4 : TCVSYN2 */ + union { + struct + { + uint32_t tcvsyn2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCVSYN2; + + /* 0xB8 : TCVSYN3 */ + union { + struct + { + uint32_t tcvsyn3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCVSYN3; + + /* 0xBC : TCDR */ + union { + struct + { + uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ + uint32_t tcdr2 : 8; /* [15: 8], r/w, 0x0 */ + uint32_t tcdr3 : 8; /* [23:16], r/w, 0x0 */ + uint32_t wcdr : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } TCDR; +}; + +typedef volatile struct timer_reg timer_reg_t; + +#endif /* __TIMER_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/tzc_sec_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/tzc_sec_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..8ba37e34d229f3165da75befcde29e63f5095ff9 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/tzc_sec_reg.h @@ -0,0 +1,256 @@ +/** + ****************************************************************************** + * @file tzc_sec_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TZC_SEC_REG_H__ +#define __TZC_SEC_REG_H__ + +#include "bl602.h" + +/* 0x40 : tzc_rom_ctrl */ +#define TZC_SEC_TZC_ROM_CTRL_OFFSET (0x40) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN TZC_SEC_TZC_ROM0_R0_ID0_EN +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS (0U) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN TZC_SEC_TZC_ROM0_R1_ID0_EN +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS (1U) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN TZC_SEC_TZC_ROM1_R0_ID0_EN +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS (2U) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN TZC_SEC_TZC_ROM1_R1_ID0_EN +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS (3U) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN TZC_SEC_TZC_ROM0_R0_ID1_EN +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS (8U) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN TZC_SEC_TZC_ROM0_R1_ID1_EN +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS (9U) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN TZC_SEC_TZC_ROM1_R0_ID1_EN +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS (10U) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN TZC_SEC_TZC_ROM1_R1_ID1_EN +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS (11U) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_EN TZC_SEC_TZC_ROM0_R0_EN +#define TZC_SEC_TZC_ROM0_R0_EN_POS (16U) +#define TZC_SEC_TZC_ROM0_R0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_EN TZC_SEC_TZC_ROM0_R1_EN +#define TZC_SEC_TZC_ROM0_R1_EN_POS (17U) +#define TZC_SEC_TZC_ROM0_R1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_EN TZC_SEC_TZC_ROM1_R0_EN +#define TZC_SEC_TZC_ROM1_R0_EN_POS (18U) +#define TZC_SEC_TZC_ROM1_R0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_EN TZC_SEC_TZC_ROM1_R1_EN +#define TZC_SEC_TZC_ROM1_R1_EN_POS (19U) +#define TZC_SEC_TZC_ROM1_R1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_LOCK TZC_SEC_TZC_ROM0_R0_LOCK +#define TZC_SEC_TZC_ROM0_R0_LOCK_POS (24U) +#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS) +#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)) +#define TZC_SEC_TZC_ROM0_R1_LOCK TZC_SEC_TZC_ROM0_R1_LOCK +#define TZC_SEC_TZC_ROM0_R1_LOCK_POS (25U) +#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS) +#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)) +#define TZC_SEC_TZC_ROM1_R0_LOCK TZC_SEC_TZC_ROM1_R0_LOCK +#define TZC_SEC_TZC_ROM1_R0_LOCK_POS (26U) +#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS) +#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)) +#define TZC_SEC_TZC_ROM1_R1_LOCK TZC_SEC_TZC_ROM1_R1_LOCK +#define TZC_SEC_TZC_ROM1_R1_LOCK_POS (27U) +#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS) +#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)) +#define TZC_SEC_TZC_SBOOT_DONE TZC_SEC_TZC_SBOOT_DONE +#define TZC_SEC_TZC_SBOOT_DONE_POS (28U) +#define TZC_SEC_TZC_SBOOT_DONE_LEN (4U) +#define TZC_SEC_TZC_SBOOT_DONE_MSK (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS) +#define TZC_SEC_TZC_SBOOT_DONE_UMSK (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)) + +/* 0x44 : tzc_rom0_r0 */ +#define TZC_SEC_TZC_ROM0_R0_OFFSET (0x44) +#define TZC_SEC_TZC_ROM0_R0_END TZC_SEC_TZC_ROM0_R0_END +#define TZC_SEC_TZC_ROM0_R0_END_POS (0U) +#define TZC_SEC_TZC_ROM0_R0_END_LEN (16U) +#define TZC_SEC_TZC_ROM0_R0_END_MSK (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS) +#define TZC_SEC_TZC_ROM0_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)) +#define TZC_SEC_TZC_ROM0_R0_START TZC_SEC_TZC_ROM0_R0_START +#define TZC_SEC_TZC_ROM0_R0_START_POS (16U) +#define TZC_SEC_TZC_ROM0_R0_START_LEN (16U) +#define TZC_SEC_TZC_ROM0_R0_START_MSK (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS) +#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)) + +/* 0x48 : tzc_rom0_r1 */ +#define TZC_SEC_TZC_ROM0_R1_OFFSET (0x48) +#define TZC_SEC_TZC_ROM0_R1_END TZC_SEC_TZC_ROM0_R1_END +#define TZC_SEC_TZC_ROM0_R1_END_POS (0U) +#define TZC_SEC_TZC_ROM0_R1_END_LEN (16U) +#define TZC_SEC_TZC_ROM0_R1_END_MSK (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS) +#define TZC_SEC_TZC_ROM0_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)) +#define TZC_SEC_TZC_ROM0_R1_START TZC_SEC_TZC_ROM0_R1_START +#define TZC_SEC_TZC_ROM0_R1_START_POS (16U) +#define TZC_SEC_TZC_ROM0_R1_START_LEN (16U) +#define TZC_SEC_TZC_ROM0_R1_START_MSK (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS) +#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)) + +/* 0x4C : tzc_rom1_r0 */ +#define TZC_SEC_TZC_ROM1_R0_OFFSET (0x4C) +#define TZC_SEC_TZC_ROM1_R0_END TZC_SEC_TZC_ROM1_R0_END +#define TZC_SEC_TZC_ROM1_R0_END_POS (0U) +#define TZC_SEC_TZC_ROM1_R0_END_LEN (16U) +#define TZC_SEC_TZC_ROM1_R0_END_MSK (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS) +#define TZC_SEC_TZC_ROM1_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)) +#define TZC_SEC_TZC_ROM1_R0_START TZC_SEC_TZC_ROM1_R0_START +#define TZC_SEC_TZC_ROM1_R0_START_POS (16U) +#define TZC_SEC_TZC_ROM1_R0_START_LEN (16U) +#define TZC_SEC_TZC_ROM1_R0_START_MSK (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS) +#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)) + +/* 0x50 : tzc_rom1_r1 */ +#define TZC_SEC_TZC_ROM1_R1_OFFSET (0x50) +#define TZC_SEC_TZC_ROM1_R1_END TZC_SEC_TZC_ROM1_R1_END +#define TZC_SEC_TZC_ROM1_R1_END_POS (0U) +#define TZC_SEC_TZC_ROM1_R1_END_LEN (16U) +#define TZC_SEC_TZC_ROM1_R1_END_MSK (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS) +#define TZC_SEC_TZC_ROM1_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)) +#define TZC_SEC_TZC_ROM1_R1_START TZC_SEC_TZC_ROM1_R1_START +#define TZC_SEC_TZC_ROM1_R1_START_POS (16U) +#define TZC_SEC_TZC_ROM1_R1_START_LEN (16U) +#define TZC_SEC_TZC_ROM1_R1_START_MSK (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS) +#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)) + +struct tzc_sec_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[64]; + + /* 0x40 : tzc_rom_ctrl */ + union { + struct + { + uint32_t tzc_rom0_r0_id0_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t tzc_rom0_r1_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t tzc_rom1_r0_id0_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t tzc_rom1_r1_id0_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_id1_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t tzc_rom0_r1_id1_en : 1; /* [ 9], r/w, 0x1 */ + uint32_t tzc_rom1_r0_id1_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t tzc_rom1_r1_id1_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_en : 1; /* [ 16], r/w, 0x0 */ + uint32_t tzc_rom0_r1_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t tzc_rom1_r0_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t tzc_rom1_r1_en : 1; /* [ 19], r/w, 0x0 */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_lock : 1; /* [ 24], r/w, 0x0 */ + uint32_t tzc_rom0_r1_lock : 1; /* [ 25], r/w, 0x0 */ + uint32_t tzc_rom1_r0_lock : 1; /* [ 26], r/w, 0x0 */ + uint32_t tzc_rom1_r1_lock : 1; /* [ 27], r/w, 0x0 */ + uint32_t tzc_sboot_done : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom_ctrl; + + /* 0x44 : tzc_rom0_r0 */ + union { + struct + { + uint32_t tzc_rom0_r0_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom0_r0_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom0_r0; + + /* 0x48 : tzc_rom0_r1 */ + union { + struct + { + uint32_t tzc_rom0_r1_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom0_r1_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom0_r1; + + /* 0x4C : tzc_rom1_r0 */ + union { + struct + { + uint32_t tzc_rom1_r0_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom1_r0_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom1_r0; + + /* 0x50 : tzc_rom1_r1 */ + union { + struct + { + uint32_t tzc_rom1_r1_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom1_r1_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom1_r1; +}; + +typedef volatile struct tzc_sec_reg tzc_sec_reg_t; + +#endif /* __TZC_SEC_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/uart_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/uart_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..e2e2943f1148b66b6168358e242222a7369af561 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/regs/uart_reg.h @@ -0,0 +1,710 @@ +/** + ****************************************************************************** + * @file uart_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#include "bl602.h" + +/* 0x0 : utx_config */ +#define UART_UTX_CONFIG_OFFSET (0x0) +#define UART_CR_UTX_EN UART_CR_UTX_EN +#define UART_CR_UTX_EN_POS (0U) +#define UART_CR_UTX_EN_LEN (1U) +#define UART_CR_UTX_EN_MSK (((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS) +#define UART_CR_UTX_EN_UMSK (~(((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)) +#define UART_CR_UTX_CTS_EN UART_CR_UTX_CTS_EN +#define UART_CR_UTX_CTS_EN_POS (1U) +#define UART_CR_UTX_CTS_EN_LEN (1U) +#define UART_CR_UTX_CTS_EN_MSK (((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS) +#define UART_CR_UTX_CTS_EN_UMSK (~(((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)) +#define UART_CR_UTX_FRM_EN UART_CR_UTX_FRM_EN +#define UART_CR_UTX_FRM_EN_POS (2U) +#define UART_CR_UTX_FRM_EN_LEN (1U) +#define UART_CR_UTX_FRM_EN_MSK (((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS) +#define UART_CR_UTX_FRM_EN_UMSK (~(((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)) +#define UART_CR_UTX_PRT_EN UART_CR_UTX_PRT_EN +#define UART_CR_UTX_PRT_EN_POS (4U) +#define UART_CR_UTX_PRT_EN_LEN (1U) +#define UART_CR_UTX_PRT_EN_MSK (((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS) +#define UART_CR_UTX_PRT_EN_UMSK (~(((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)) +#define UART_CR_UTX_PRT_SEL UART_CR_UTX_PRT_SEL +#define UART_CR_UTX_PRT_SEL_POS (5U) +#define UART_CR_UTX_PRT_SEL_LEN (1U) +#define UART_CR_UTX_PRT_SEL_MSK (((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS) +#define UART_CR_UTX_PRT_SEL_UMSK (~(((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)) +#define UART_CR_UTX_IR_EN UART_CR_UTX_IR_EN +#define UART_CR_UTX_IR_EN_POS (6U) +#define UART_CR_UTX_IR_EN_LEN (1U) +#define UART_CR_UTX_IR_EN_MSK (((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS) +#define UART_CR_UTX_IR_EN_UMSK (~(((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)) +#define UART_CR_UTX_IR_INV UART_CR_UTX_IR_INV +#define UART_CR_UTX_IR_INV_POS (7U) +#define UART_CR_UTX_IR_INV_LEN (1U) +#define UART_CR_UTX_IR_INV_MSK (((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS) +#define UART_CR_UTX_IR_INV_UMSK (~(((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)) +#define UART_CR_UTX_BIT_CNT_D UART_CR_UTX_BIT_CNT_D +#define UART_CR_UTX_BIT_CNT_D_POS (8U) +#define UART_CR_UTX_BIT_CNT_D_LEN (3U) +#define UART_CR_UTX_BIT_CNT_D_MSK (((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS) +#define UART_CR_UTX_BIT_CNT_D_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)) +#define UART_CR_UTX_BIT_CNT_P UART_CR_UTX_BIT_CNT_P +#define UART_CR_UTX_BIT_CNT_P_POS (12U) +#define UART_CR_UTX_BIT_CNT_P_LEN (2U) +#define UART_CR_UTX_BIT_CNT_P_MSK (((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS) +#define UART_CR_UTX_BIT_CNT_P_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)) +#define UART_CR_UTX_LEN UART_CR_UTX_LEN +#define UART_CR_UTX_LEN_POS (16U) +#define UART_CR_UTX_LEN_LEN (16U) +#define UART_CR_UTX_LEN_MSK (((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS) +#define UART_CR_UTX_LEN_UMSK (~(((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)) + +/* 0x4 : urx_config */ +#define UART_URX_CONFIG_OFFSET (0x4) +#define UART_CR_URX_EN UART_CR_URX_EN +#define UART_CR_URX_EN_POS (0U) +#define UART_CR_URX_EN_LEN (1U) +#define UART_CR_URX_EN_MSK (((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS) +#define UART_CR_URX_EN_UMSK (~(((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)) +#define UART_CR_URX_RTS_SW_MODE UART_CR_URX_RTS_SW_MODE +#define UART_CR_URX_RTS_SW_MODE_POS (1U) +#define UART_CR_URX_RTS_SW_MODE_LEN (1U) +#define UART_CR_URX_RTS_SW_MODE_MSK (((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS) +#define UART_CR_URX_RTS_SW_MODE_UMSK (~(((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS)) +#define UART_CR_URX_RTS_SW_VAL UART_CR_URX_RTS_SW_VAL +#define UART_CR_URX_RTS_SW_VAL_POS (2U) +#define UART_CR_URX_RTS_SW_VAL_LEN (1U) +#define UART_CR_URX_RTS_SW_VAL_MSK (((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS) +#define UART_CR_URX_RTS_SW_VAL_UMSK (~(((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)) +#define UART_CR_URX_ABR_EN UART_CR_URX_ABR_EN +#define UART_CR_URX_ABR_EN_POS (3U) +#define UART_CR_URX_ABR_EN_LEN (1U) +#define UART_CR_URX_ABR_EN_MSK (((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS) +#define UART_CR_URX_ABR_EN_UMSK (~(((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)) +#define UART_CR_URX_PRT_EN UART_CR_URX_PRT_EN +#define UART_CR_URX_PRT_EN_POS (4U) +#define UART_CR_URX_PRT_EN_LEN (1U) +#define UART_CR_URX_PRT_EN_MSK (((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS) +#define UART_CR_URX_PRT_EN_UMSK (~(((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)) +#define UART_CR_URX_PRT_SEL UART_CR_URX_PRT_SEL +#define UART_CR_URX_PRT_SEL_POS (5U) +#define UART_CR_URX_PRT_SEL_LEN (1U) +#define UART_CR_URX_PRT_SEL_MSK (((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS) +#define UART_CR_URX_PRT_SEL_UMSK (~(((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)) +#define UART_CR_URX_IR_EN UART_CR_URX_IR_EN +#define UART_CR_URX_IR_EN_POS (6U) +#define UART_CR_URX_IR_EN_LEN (1U) +#define UART_CR_URX_IR_EN_MSK (((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS) +#define UART_CR_URX_IR_EN_UMSK (~(((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)) +#define UART_CR_URX_IR_INV UART_CR_URX_IR_INV +#define UART_CR_URX_IR_INV_POS (7U) +#define UART_CR_URX_IR_INV_LEN (1U) +#define UART_CR_URX_IR_INV_MSK (((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS) +#define UART_CR_URX_IR_INV_UMSK (~(((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)) +#define UART_CR_URX_BIT_CNT_D UART_CR_URX_BIT_CNT_D +#define UART_CR_URX_BIT_CNT_D_POS (8U) +#define UART_CR_URX_BIT_CNT_D_LEN (3U) +#define UART_CR_URX_BIT_CNT_D_MSK (((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS) +#define UART_CR_URX_BIT_CNT_D_UMSK (~(((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)) +#define UART_CR_URX_DEG_EN UART_CR_URX_DEG_EN +#define UART_CR_URX_DEG_EN_POS (11U) +#define UART_CR_URX_DEG_EN_LEN (1U) +#define UART_CR_URX_DEG_EN_MSK (((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS) +#define UART_CR_URX_DEG_EN_UMSK (~(((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)) +#define UART_CR_URX_DEG_CNT UART_CR_URX_DEG_CNT +#define UART_CR_URX_DEG_CNT_POS (12U) +#define UART_CR_URX_DEG_CNT_LEN (4U) +#define UART_CR_URX_DEG_CNT_MSK (((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS) +#define UART_CR_URX_DEG_CNT_UMSK (~(((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)) +#define UART_CR_URX_LEN UART_CR_URX_LEN +#define UART_CR_URX_LEN_POS (16U) +#define UART_CR_URX_LEN_LEN (16U) +#define UART_CR_URX_LEN_MSK (((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS) +#define UART_CR_URX_LEN_UMSK (~(((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)) + +/* 0x8 : uart_bit_prd */ +#define UART_BIT_PRD_OFFSET (0x8) +#define UART_CR_UTX_BIT_PRD UART_CR_UTX_BIT_PRD +#define UART_CR_UTX_BIT_PRD_POS (0U) +#define UART_CR_UTX_BIT_PRD_LEN (16U) +#define UART_CR_UTX_BIT_PRD_MSK (((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS) +#define UART_CR_UTX_BIT_PRD_UMSK (~(((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)) +#define UART_CR_URX_BIT_PRD UART_CR_URX_BIT_PRD +#define UART_CR_URX_BIT_PRD_POS (16U) +#define UART_CR_URX_BIT_PRD_LEN (16U) +#define UART_CR_URX_BIT_PRD_MSK (((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS) +#define UART_CR_URX_BIT_PRD_UMSK (~(((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)) + +/* 0xC : data_config */ +#define UART_DATA_CONFIG_OFFSET (0xC) +#define UART_CR_UART_BIT_INV UART_CR_UART_BIT_INV +#define UART_CR_UART_BIT_INV_POS (0U) +#define UART_CR_UART_BIT_INV_LEN (1U) +#define UART_CR_UART_BIT_INV_MSK (((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS) +#define UART_CR_UART_BIT_INV_UMSK (~(((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)) + +/* 0x10 : utx_ir_position */ +#define UART_UTX_IR_POSITION_OFFSET (0x10) +#define UART_CR_UTX_IR_POS_S UART_CR_UTX_IR_POS_S +#define UART_CR_UTX_IR_POS_S_POS (0U) +#define UART_CR_UTX_IR_POS_S_LEN (16U) +#define UART_CR_UTX_IR_POS_S_MSK (((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS) +#define UART_CR_UTX_IR_POS_S_UMSK (~(((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)) +#define UART_CR_UTX_IR_POS_P UART_CR_UTX_IR_POS_P +#define UART_CR_UTX_IR_POS_P_POS (16U) +#define UART_CR_UTX_IR_POS_P_LEN (16U) +#define UART_CR_UTX_IR_POS_P_MSK (((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS) +#define UART_CR_UTX_IR_POS_P_UMSK (~(((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)) + +/* 0x14 : urx_ir_position */ +#define UART_URX_IR_POSITION_OFFSET (0x14) +#define UART_CR_URX_IR_POS_S UART_CR_URX_IR_POS_S +#define UART_CR_URX_IR_POS_S_POS (0U) +#define UART_CR_URX_IR_POS_S_LEN (16U) +#define UART_CR_URX_IR_POS_S_MSK (((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS) +#define UART_CR_URX_IR_POS_S_UMSK (~(((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)) + +/* 0x18 : urx_rto_timer */ +#define UART_URX_RTO_TIMER_OFFSET (0x18) +#define UART_CR_URX_RTO_VALUE UART_CR_URX_RTO_VALUE +#define UART_CR_URX_RTO_VALUE_POS (0U) +#define UART_CR_URX_RTO_VALUE_LEN (8U) +#define UART_CR_URX_RTO_VALUE_MSK (((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS) +#define UART_CR_URX_RTO_VALUE_UMSK (~(((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)) + +/* 0x20 : UART interrupt status */ +#define UART_INT_STS_OFFSET (0x20) +#define UART_UTX_END_INT UART_UTX_END_INT +#define UART_UTX_END_INT_POS (0U) +#define UART_UTX_END_INT_LEN (1U) +#define UART_UTX_END_INT_MSK (((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS) +#define UART_UTX_END_INT_UMSK (~(((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)) +#define UART_URX_END_INT UART_URX_END_INT +#define UART_URX_END_INT_POS (1U) +#define UART_URX_END_INT_LEN (1U) +#define UART_URX_END_INT_MSK (((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS) +#define UART_URX_END_INT_UMSK (~(((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)) +#define UART_UTX_FIFO_INT UART_UTX_FIFO_INT +#define UART_UTX_FIFO_INT_POS (2U) +#define UART_UTX_FIFO_INT_LEN (1U) +#define UART_UTX_FIFO_INT_MSK (((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS) +#define UART_UTX_FIFO_INT_UMSK (~(((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS)) +#define UART_URX_FIFO_INT UART_URX_FIFO_INT +#define UART_URX_FIFO_INT_POS (3U) +#define UART_URX_FIFO_INT_LEN (1U) +#define UART_URX_FIFO_INT_MSK (((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS) +#define UART_URX_FIFO_INT_UMSK (~(((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS)) +#define UART_URX_RTO_INT UART_URX_RTO_INT +#define UART_URX_RTO_INT_POS (4U) +#define UART_URX_RTO_INT_LEN (1U) +#define UART_URX_RTO_INT_MSK (((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS) +#define UART_URX_RTO_INT_UMSK (~(((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)) +#define UART_URX_PCE_INT UART_URX_PCE_INT +#define UART_URX_PCE_INT_POS (5U) +#define UART_URX_PCE_INT_LEN (1U) +#define UART_URX_PCE_INT_MSK (((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS) +#define UART_URX_PCE_INT_UMSK (~(((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)) +#define UART_UTX_FER_INT UART_UTX_FER_INT +#define UART_UTX_FER_INT_POS (6U) +#define UART_UTX_FER_INT_LEN (1U) +#define UART_UTX_FER_INT_MSK (((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS) +#define UART_UTX_FER_INT_UMSK (~(((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)) +#define UART_URX_FER_INT UART_URX_FER_INT +#define UART_URX_FER_INT_POS (7U) +#define UART_URX_FER_INT_LEN (1U) +#define UART_URX_FER_INT_MSK (((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS) +#define UART_URX_FER_INT_UMSK (~(((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)) + +/* 0x24 : UART interrupt mask */ +#define UART_INT_MASK_OFFSET (0x24) +#define UART_CR_UTX_END_MASK UART_CR_UTX_END_MASK +#define UART_CR_UTX_END_MASK_POS (0U) +#define UART_CR_UTX_END_MASK_LEN (1U) +#define UART_CR_UTX_END_MASK_MSK (((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS) +#define UART_CR_UTX_END_MASK_UMSK (~(((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)) +#define UART_CR_URX_END_MASK UART_CR_URX_END_MASK +#define UART_CR_URX_END_MASK_POS (1U) +#define UART_CR_URX_END_MASK_LEN (1U) +#define UART_CR_URX_END_MASK_MSK (((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS) +#define UART_CR_URX_END_MASK_UMSK (~(((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)) +#define UART_CR_UTX_FIFO_MASK UART_CR_UTX_FIFO_MASK +#define UART_CR_UTX_FIFO_MASK_POS (2U) +#define UART_CR_UTX_FIFO_MASK_LEN (1U) +#define UART_CR_UTX_FIFO_MASK_MSK (((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS) +#define UART_CR_UTX_FIFO_MASK_UMSK (~(((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS)) +#define UART_CR_URX_FIFO_MASK UART_CR_URX_FIFO_MASK +#define UART_CR_URX_FIFO_MASK_POS (3U) +#define UART_CR_URX_FIFO_MASK_LEN (1U) +#define UART_CR_URX_FIFO_MASK_MSK (((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS) +#define UART_CR_URX_FIFO_MASK_UMSK (~(((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS)) +#define UART_CR_URX_RTO_MASK UART_CR_URX_RTO_MASK +#define UART_CR_URX_RTO_MASK_POS (4U) +#define UART_CR_URX_RTO_MASK_LEN (1U) +#define UART_CR_URX_RTO_MASK_MSK (((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS) +#define UART_CR_URX_RTO_MASK_UMSK (~(((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)) +#define UART_CR_URX_PCE_MASK UART_CR_URX_PCE_MASK +#define UART_CR_URX_PCE_MASK_POS (5U) +#define UART_CR_URX_PCE_MASK_LEN (1U) +#define UART_CR_URX_PCE_MASK_MSK (((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS) +#define UART_CR_URX_PCE_MASK_UMSK (~(((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)) +#define UART_CR_UTX_FER_MASK UART_CR_UTX_FER_MASK +#define UART_CR_UTX_FER_MASK_POS (6U) +#define UART_CR_UTX_FER_MASK_LEN (1U) +#define UART_CR_UTX_FER_MASK_MSK (((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS) +#define UART_CR_UTX_FER_MASK_UMSK (~(((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)) +#define UART_CR_URX_FER_MASK UART_CR_URX_FER_MASK +#define UART_CR_URX_FER_MASK_POS (7U) +#define UART_CR_URX_FER_MASK_LEN (1U) +#define UART_CR_URX_FER_MASK_MSK (((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS) +#define UART_CR_URX_FER_MASK_UMSK (~(((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)) + +/* 0x28 : UART interrupt clear */ +#define UART_INT_CLEAR_OFFSET (0x28) +#define UART_CR_UTX_END_CLR UART_CR_UTX_END_CLR +#define UART_CR_UTX_END_CLR_POS (0U) +#define UART_CR_UTX_END_CLR_LEN (1U) +#define UART_CR_UTX_END_CLR_MSK (((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS) +#define UART_CR_UTX_END_CLR_UMSK (~(((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)) +#define UART_CR_URX_END_CLR UART_CR_URX_END_CLR +#define UART_CR_URX_END_CLR_POS (1U) +#define UART_CR_URX_END_CLR_LEN (1U) +#define UART_CR_URX_END_CLR_MSK (((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS) +#define UART_CR_URX_END_CLR_UMSK (~(((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)) +#define UART_CR_URX_RTO_CLR UART_CR_URX_RTO_CLR +#define UART_CR_URX_RTO_CLR_POS (4U) +#define UART_CR_URX_RTO_CLR_LEN (1U) +#define UART_CR_URX_RTO_CLR_MSK (((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS) +#define UART_CR_URX_RTO_CLR_UMSK (~(((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)) +#define UART_CR_URX_PCE_CLR UART_CR_URX_PCE_CLR +#define UART_CR_URX_PCE_CLR_POS (5U) +#define UART_CR_URX_PCE_CLR_LEN (1U) +#define UART_CR_URX_PCE_CLR_MSK (((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS) +#define UART_CR_URX_PCE_CLR_UMSK (~(((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)) + +/* 0x2C : UART interrupt enable */ +#define UART_INT_EN_OFFSET (0x2C) +#define UART_CR_UTX_END_EN UART_CR_UTX_END_EN +#define UART_CR_UTX_END_EN_POS (0U) +#define UART_CR_UTX_END_EN_LEN (1U) +#define UART_CR_UTX_END_EN_MSK (((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS) +#define UART_CR_UTX_END_EN_UMSK (~(((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)) +#define UART_CR_URX_END_EN UART_CR_URX_END_EN +#define UART_CR_URX_END_EN_POS (1U) +#define UART_CR_URX_END_EN_LEN (1U) +#define UART_CR_URX_END_EN_MSK (((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS) +#define UART_CR_URX_END_EN_UMSK (~(((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)) +#define UART_CR_UTX_FIFO_EN UART_CR_UTX_FIFO_EN +#define UART_CR_UTX_FIFO_EN_POS (2U) +#define UART_CR_UTX_FIFO_EN_LEN (1U) +#define UART_CR_UTX_FIFO_EN_MSK (((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS) +#define UART_CR_UTX_FIFO_EN_UMSK (~(((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS)) +#define UART_CR_URX_FIFO_EN UART_CR_URX_FIFO_EN +#define UART_CR_URX_FIFO_EN_POS (3U) +#define UART_CR_URX_FIFO_EN_LEN (1U) +#define UART_CR_URX_FIFO_EN_MSK (((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS) +#define UART_CR_URX_FIFO_EN_UMSK (~(((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS)) +#define UART_CR_URX_RTO_EN UART_CR_URX_RTO_EN +#define UART_CR_URX_RTO_EN_POS (4U) +#define UART_CR_URX_RTO_EN_LEN (1U) +#define UART_CR_URX_RTO_EN_MSK (((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS) +#define UART_CR_URX_RTO_EN_UMSK (~(((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)) +#define UART_CR_URX_PCE_EN UART_CR_URX_PCE_EN +#define UART_CR_URX_PCE_EN_POS (5U) +#define UART_CR_URX_PCE_EN_LEN (1U) +#define UART_CR_URX_PCE_EN_MSK (((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS) +#define UART_CR_URX_PCE_EN_UMSK (~(((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)) +#define UART_CR_UTX_FER_EN UART_CR_UTX_FER_EN +#define UART_CR_UTX_FER_EN_POS (6U) +#define UART_CR_UTX_FER_EN_LEN (1U) +#define UART_CR_UTX_FER_EN_MSK (((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS) +#define UART_CR_UTX_FER_EN_UMSK (~(((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)) +#define UART_CR_URX_FER_EN UART_CR_URX_FER_EN +#define UART_CR_URX_FER_EN_POS (7U) +#define UART_CR_URX_FER_EN_LEN (1U) +#define UART_CR_URX_FER_EN_MSK (((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS) +#define UART_CR_URX_FER_EN_UMSK (~(((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)) + +/* 0x30 : uart_status */ +#define UART_STATUS_OFFSET (0x30) +#define UART_STS_UTX_BUS_BUSY UART_STS_UTX_BUS_BUSY +#define UART_STS_UTX_BUS_BUSY_POS (0U) +#define UART_STS_UTX_BUS_BUSY_LEN (1U) +#define UART_STS_UTX_BUS_BUSY_MSK (((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS) +#define UART_STS_UTX_BUS_BUSY_UMSK (~(((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)) +#define UART_STS_URX_BUS_BUSY UART_STS_URX_BUS_BUSY +#define UART_STS_URX_BUS_BUSY_POS (1U) +#define UART_STS_URX_BUS_BUSY_LEN (1U) +#define UART_STS_URX_BUS_BUSY_MSK (((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS) +#define UART_STS_URX_BUS_BUSY_UMSK (~(((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)) + +/* 0x34 : sts_urx_abr_prd */ +#define UART_STS_URX_ABR_PRD_OFFSET (0x34) +#define UART_STS_URX_ABR_PRD_START UART_STS_URX_ABR_PRD_START +#define UART_STS_URX_ABR_PRD_START_POS (0U) +#define UART_STS_URX_ABR_PRD_START_LEN (16U) +#define UART_STS_URX_ABR_PRD_START_MSK (((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS) +#define UART_STS_URX_ABR_PRD_START_UMSK (~(((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS)) +#define UART_STS_URX_ABR_PRD_0X55 UART_STS_URX_ABR_PRD_0X55 +#define UART_STS_URX_ABR_PRD_0X55_POS (16U) +#define UART_STS_URX_ABR_PRD_0X55_LEN (16U) +#define UART_STS_URX_ABR_PRD_0X55_MSK (((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS) +#define UART_STS_URX_ABR_PRD_0X55_UMSK (~(((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS)) + +/* 0x80 : uart_fifo_config_0 */ +#define UART_FIFO_CONFIG_0_OFFSET (0x80) +#define UART_DMA_TX_EN UART_DMA_TX_EN +#define UART_DMA_TX_EN_POS (0U) +#define UART_DMA_TX_EN_LEN (1U) +#define UART_DMA_TX_EN_MSK (((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS) +#define UART_DMA_TX_EN_UMSK (~(((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)) +#define UART_DMA_RX_EN UART_DMA_RX_EN +#define UART_DMA_RX_EN_POS (1U) +#define UART_DMA_RX_EN_LEN (1U) +#define UART_DMA_RX_EN_MSK (((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS) +#define UART_DMA_RX_EN_UMSK (~(((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)) +#define UART_TX_FIFO_CLR UART_TX_FIFO_CLR +#define UART_TX_FIFO_CLR_POS (2U) +#define UART_TX_FIFO_CLR_LEN (1U) +#define UART_TX_FIFO_CLR_MSK (((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS) +#define UART_TX_FIFO_CLR_UMSK (~(((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)) +#define UART_RX_FIFO_CLR UART_RX_FIFO_CLR +#define UART_RX_FIFO_CLR_POS (3U) +#define UART_RX_FIFO_CLR_LEN (1U) +#define UART_RX_FIFO_CLR_MSK (((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS) +#define UART_RX_FIFO_CLR_UMSK (~(((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)) +#define UART_TX_FIFO_OVERFLOW UART_TX_FIFO_OVERFLOW +#define UART_TX_FIFO_OVERFLOW_POS (4U) +#define UART_TX_FIFO_OVERFLOW_LEN (1U) +#define UART_TX_FIFO_OVERFLOW_MSK (((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS) +#define UART_TX_FIFO_OVERFLOW_UMSK (~(((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)) +#define UART_TX_FIFO_UNDERFLOW UART_TX_FIFO_UNDERFLOW +#define UART_TX_FIFO_UNDERFLOW_POS (5U) +#define UART_TX_FIFO_UNDERFLOW_LEN (1U) +#define UART_TX_FIFO_UNDERFLOW_MSK (((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS) +#define UART_TX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)) +#define UART_RX_FIFO_OVERFLOW UART_RX_FIFO_OVERFLOW +#define UART_RX_FIFO_OVERFLOW_POS (6U) +#define UART_RX_FIFO_OVERFLOW_LEN (1U) +#define UART_RX_FIFO_OVERFLOW_MSK (((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS) +#define UART_RX_FIFO_OVERFLOW_UMSK (~(((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)) +#define UART_RX_FIFO_UNDERFLOW UART_RX_FIFO_UNDERFLOW +#define UART_RX_FIFO_UNDERFLOW_POS (7U) +#define UART_RX_FIFO_UNDERFLOW_LEN (1U) +#define UART_RX_FIFO_UNDERFLOW_MSK (((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS) +#define UART_RX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)) + +/* 0x84 : uart_fifo_config_1 */ +#define UART_FIFO_CONFIG_1_OFFSET (0x84) +#define UART_TX_FIFO_CNT UART_TX_FIFO_CNT +#define UART_TX_FIFO_CNT_POS (0U) +#define UART_TX_FIFO_CNT_LEN (6U) +#define UART_TX_FIFO_CNT_MSK (((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS) +#define UART_TX_FIFO_CNT_UMSK (~(((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)) +#define UART_RX_FIFO_CNT UART_RX_FIFO_CNT +#define UART_RX_FIFO_CNT_POS (8U) +#define UART_RX_FIFO_CNT_LEN (6U) +#define UART_RX_FIFO_CNT_MSK (((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS) +#define UART_RX_FIFO_CNT_UMSK (~(((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)) +#define UART_TX_FIFO_TH UART_TX_FIFO_TH +#define UART_TX_FIFO_TH_POS (16U) +#define UART_TX_FIFO_TH_LEN (5U) +#define UART_TX_FIFO_TH_MSK (((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS) +#define UART_TX_FIFO_TH_UMSK (~(((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)) +#define UART_RX_FIFO_TH UART_RX_FIFO_TH +#define UART_RX_FIFO_TH_POS (24U) +#define UART_RX_FIFO_TH_LEN (5U) +#define UART_RX_FIFO_TH_MSK (((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS) +#define UART_RX_FIFO_TH_UMSK (~(((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)) + +/* 0x88 : uart_fifo_wdata */ +#define UART_FIFO_WDATA_OFFSET (0x88) +#define UART_FIFO_WDATA UART_FIFO_WDATA +#define UART_FIFO_WDATA_POS (0U) +#define UART_FIFO_WDATA_LEN (8U) +#define UART_FIFO_WDATA_MSK (((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS) +#define UART_FIFO_WDATA_UMSK (~(((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)) + +/* 0x8C : uart_fifo_rdata */ +#define UART_FIFO_RDATA_OFFSET (0x8C) +#define UART_FIFO_RDATA UART_FIFO_RDATA +#define UART_FIFO_RDATA_POS (0U) +#define UART_FIFO_RDATA_LEN (8U) +#define UART_FIFO_RDATA_MSK (((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS) +#define UART_FIFO_RDATA_UMSK (~(((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)) + +struct uart_reg { + /* 0x0 : utx_config */ + union { + struct + { + uint32_t cr_utx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_utx_cts_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_utx_frm_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t cr_utx_prt_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_utx_prt_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_utx_ir_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_utx_ir_inv : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_utx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t cr_utx_bit_cnt_p : 2; /* [13:12], r/w, 0x1 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t cr_utx_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } utx_config; + + /* 0x4 : urx_config */ + union { + struct + { + uint32_t cr_urx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_urx_rts_sw_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_urx_rts_sw_val : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_urx_abr_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_urx_prt_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_urx_prt_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_urx_ir_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_urx_ir_inv : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_urx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ + uint32_t cr_urx_deg_en : 1; /* [ 11], r/w, 0x0 */ + uint32_t cr_urx_deg_cnt : 4; /* [15:12], r/w, 0x0 */ + uint32_t cr_urx_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } urx_config; + + /* 0x8 : uart_bit_prd */ + union { + struct + { + uint32_t cr_utx_bit_prd : 16; /* [15: 0], r/w, 0xff */ + uint32_t cr_urx_bit_prd : 16; /* [31:16], r/w, 0xff */ + } BF; + uint32_t WORD; + } uart_bit_prd; + + /* 0xC : data_config */ + union { + struct + { + uint32_t cr_uart_bit_inv : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } data_config; + + /* 0x10 : utx_ir_position */ + union { + struct + { + uint32_t cr_utx_ir_pos_s : 16; /* [15: 0], r/w, 0x70 */ + uint32_t cr_utx_ir_pos_p : 16; /* [31:16], r/w, 0x9f */ + } BF; + uint32_t WORD; + } utx_ir_position; + + /* 0x14 : urx_ir_position */ + union { + struct + { + uint32_t cr_urx_ir_pos_s : 16; /* [15: 0], r/w, 0x6f */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } urx_ir_position; + + /* 0x18 : urx_rto_timer */ + union { + struct + { + uint32_t cr_urx_rto_value : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } urx_rto_timer; + + /* 0x1c reserved */ + uint8_t RESERVED0x1c[4]; + + /* 0x20 : UART interrupt status */ + union { + struct + { + uint32_t utx_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t urx_end_int : 1; /* [ 1], r, 0x0 */ + uint32_t utx_fifo_int : 1; /* [ 2], r, 0x0 */ + uint32_t urx_fifo_int : 1; /* [ 3], r, 0x0 */ + uint32_t urx_rto_int : 1; /* [ 4], r, 0x0 */ + uint32_t urx_pce_int : 1; /* [ 5], r, 0x0 */ + uint32_t utx_fer_int : 1; /* [ 6], r, 0x0 */ + uint32_t urx_fer_int : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_int_sts; + + /* 0x24 : UART interrupt mask */ + union { + struct + { + uint32_t cr_utx_end_mask : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_urx_end_mask : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_utx_fifo_mask : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_urx_fifo_mask : 1; /* [ 3], r/w, 0x1 */ + uint32_t cr_urx_rto_mask : 1; /* [ 4], r/w, 0x1 */ + uint32_t cr_urx_pce_mask : 1; /* [ 5], r/w, 0x1 */ + uint32_t cr_utx_fer_mask : 1; /* [ 6], r/w, 0x1 */ + uint32_t cr_urx_fer_mask : 1; /* [ 7], r/w, 0x1 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_int_mask; + + /* 0x28 : UART interrupt clear */ + union { + struct + { + uint32_t cr_utx_end_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t cr_urx_end_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */ + uint32_t rsvd_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t cr_urx_rto_clr : 1; /* [ 4], w1c, 0x0 */ + uint32_t cr_urx_pce_clr : 1; /* [ 5], w1c, 0x0 */ + uint32_t rsvd_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t rsvd_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_int_clear; + + /* 0x2C : UART interrupt enable */ + union { + struct + { + uint32_t cr_utx_end_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_urx_end_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_utx_fifo_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_urx_fifo_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t cr_urx_rto_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t cr_urx_pce_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t cr_utx_fer_en : 1; /* [ 6], r/w, 0x1 */ + uint32_t cr_urx_fer_en : 1; /* [ 7], r/w, 0x1 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_int_en; + + /* 0x30 : uart_status */ + union { + struct + { + uint32_t sts_utx_bus_busy : 1; /* [ 0], r, 0x0 */ + uint32_t sts_urx_bus_busy : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_status; + + /* 0x34 : sts_urx_abr_prd */ + union { + struct + { + uint32_t sts_urx_abr_prd_start : 16; /* [15: 0], r, 0x0 */ + uint32_t sts_urx_abr_prd_0x55 : 16; /* [31:16], r, 0x0 */ + } BF; + uint32_t WORD; + } sts_urx_abr_prd; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[72]; + + /* 0x80 : uart_fifo_config_0 */ + union { + struct + { + uint32_t uart_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t uart_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_fifo_config_0; + + /* 0x84 : uart_fifo_config_1 */ + union { + struct + { + uint32_t tx_fifo_cnt : 6; /* [ 5: 0], r, 0x20 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t rx_fifo_cnt : 6; /* [13: 8], r, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t tx_fifo_th : 5; /* [20:16], r/w, 0x0 */ + uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ + uint32_t rx_fifo_th : 5; /* [28:24], r/w, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_fifo_config_1; + + /* 0x88 : uart_fifo_wdata */ + union { + struct + { + uint32_t uart_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_fifo_wdata; + + /* 0x8C : uart_fifo_rdata */ + union { + struct + { + uint32_t uart_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_fifo_rdata; +}; + +typedef volatile struct uart_reg uart_reg_t; + +#endif /* __UART_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/clic.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/clic.h new file mode 100644 index 0000000000000000000000000000000000000000..3ea51390b87ce351bd17dbcf794ba8294e8dae2d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/clic.h @@ -0,0 +1,21 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_CLIC_H +#define _SIFIVE_CLIC_H + +#define CLIC_CTRL_ADDR 0x02000000UL +#define CLIC_HART0_ADDR 0x02800000UL + +#define CLIC_MSIP 0x0000 +#define CLIC_MSIP_size 0x4 +#define CLIC_MTIMECMP 0x4000 +#define CLIC_MTIMECMP_size 0x8 +#define CLIC_MTIME 0xBFF8 +#define CLIC_MTIME_size 0x8 + +#define CLIC_INTIP 0x000 +#define CLIC_INTIE 0x400 +#define CLIC_INTCFG 0x800 +#define CLIC_CFG 0xc00 + +#endif /* _SIFIVE_CLIC_H */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/cmsis_compatible_gcc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/cmsis_compatible_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..88c7963f05f05812317b245ebd8f28e386671db5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/cmsis_compatible_gcc.h @@ -0,0 +1,132 @@ +#ifndef __CMSIS_COMPATIBLE_GCC_H +#define __CMSIS_COMPATIBLE_GCC_H + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __ALWAYS_INLINE +#define __ALWAYS_INLINE inline __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __IRQ +#define __IRQ __attribute__((interrupt)) +#endif +#ifndef __IRQ_ALIGN64 +#define __IRQ_ALIGN64 __attribute__((interrupt, aligned(64))) +#endif +#ifndef ALIGN4 +#define ALIGN4 __attribute((aligned(4))) +#endif +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */ + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */ + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */ + +static uint8_t nesting2 = 0; + +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + nesting2--; + if (nesting2 == 0) { + __ASM volatile("csrsi mstatus, 8"); + } +} + +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("csrci mstatus, 8"); + nesting2++; +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + //return __builtin_bswap32(value); + uint32_t res = 0; + + res = (value << 24) | (value >> 24); + res &= 0xFF0000FF; /* only for sure */ + res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000); + + return res; +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + return __builtin_bswap16(value); +} + +extern void clic_enable_interrupt(uint32_t source); +extern void clic_disable_interrupt(uint32_t source); +extern void clic_set_pending(uint32_t source); +extern void clic_clear_pending(uint32_t source); + +#define CPU_Interrupt_Enable clic_enable_interrupt + +#define CPU_Interrupt_Disable clic_disable_interrupt + +#define CPU_Interrupt_Pending_Clear clic_clear_pending + +//#define __set_MSP(val) __ASM volatile ("lw sp,0(%0)":: "r"(val)) +#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp)) + +#endif /* __CMSIS_COMPATIBLE_GCC_H */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_bits.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_bits.h new file mode 100644 index 0000000000000000000000000000000000000000..16b15bcddd5678feb76eae1241bce61d2674985a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) +#define ROUNDDOWN(a, b) ((a) / (b) * (b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +#define SLL32 sllw +#define STORE sd +#define LOAD ld +#define LWU lwu +#define LOG_REGBYTES 3 +#else +#define SLL32 sll +#define STORE sw +#define LOAD lw +#define LWU lw +#define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_const.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_const.h new file mode 100644 index 0000000000000000000000000000000000000000..109d1dff7649554b214619fce2272ce093af51eb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details. +/* Derived from */ + +#ifndef _RISCV_CONST_H +#define _RISCV_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X, Y) X +#define _AT(T, X) X +#else +#define _AC(X, Y) (X##Y) +#define _AT(T, X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1, UL) << (x)) +#define _BITULL(x) (_AC(1, ULL) << (x)) + +#endif /* _NUCLEI_CONST_H */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_encoding.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_encoding.h new file mode 100644 index 0000000000000000000000000000000000000000..103b839a83f7244c1729bf466ae2059a95d74f5b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/risc-v/Core/Include/riscv_encoding.h @@ -0,0 +1,1360 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U << 30) +#define DCSR_NDRESET (1 << 29) +#define DCSR_FULLRESET (1 << 28) +#define DCSR_EBREAKM (1 << 15) +#define DCSR_EBREAKH (1 << 14) +#define DCSR_EBREAKS (1 << 13) +#define DCSR_EBREAKU (1 << 12) +#define DCSR_STOPCYCLE (1 << 10) +#define DCSR_STOPTIME (1 << 9) +#define DCSR_CAUSE (7 << 6) +#define DCSR_DEBUGINT (1 << 5) +#define DCSR_HALT (1 << 3) +#define DCSR_STEP (1 << 2) +#define DCSR_PRV (3 << 0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) + +#define MCONTROL_SELECT (1 << 19) +#define MCONTROL_TIMING (1 << 18) +#define MCONTROL_ACTION (0x3f << 12) +#define MCONTROL_CHAIN (1 << 11) +#define MCONTROL_MATCH (0xf << 7) +#define MCONTROL_M (1 << 6) +#define MCONTROL_H (1 << 5) +#define MCONTROL_S (1 << 4) +#define MCONTROL_U (1 << 3) +#define MCONTROL_EXECUTE (1 << 2) +#define MCONTROL_STORE (1 << 1) +#define MCONTROL_LOAD (1 << 0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define MIE_SSIE MIP_SSIP +#define MIE_HSIE MIP_HSIP +#define MIE_MSIE MIP_MSIP +#define MIE_STIE MIP_STIP +#define MIE_HTIE MIP_HTIP +#define MIE_MTIE MIP_MTIP +#define MIE_SEIE MIP_SEIP +#define MIE_HEIE MIP_HEIP +#define MIE_MEIE MIP_MEIP + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +#define MSTATUS_SD MSTATUS64_SD +#define SSTATUS_SD SSTATUS64_SD +#define RISCV_PGLEVEL_BITS 9 +#else +#define MSTATUS_SD MSTATUS32_SD +#define SSTATUS_SD SSTATUS32_SD +#define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define asm __asm + +#define read_fpu(reg) ({ unsigned long __tmp; \ + asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_fpu(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 + +#define CSR_MCOUNTINHIBIT 0x320 + +#define CSR_MNVEC 0x7C3 + +#define CSR_MTVT2 0x7EC +#define CSR_JALMNXTI 0x7ED +#define CSR_PUSHMCAUSE 0x7EE +#define CSR_PUSHMEPC 0x7EF +#define CSR_PUSHMSUBM 0x7EB + +#define CSR_WFE 0x810 +#define CSR_SLEEPVALUE 0x811 +#define CSR_TXEVT 0x812 + +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MSUBM 0x7c4 + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, + MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, + MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, + MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, + MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/GCC/entry.S b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/GCC/entry.S new file mode 100644 index 0000000000000000000000000000000000000000..b5bab3be07deb72ed461cb9da3fb2d6951c9c12b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/GCC/entry.S @@ -0,0 +1,120 @@ +/* Copyright 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +#include "riscv_encoding.h" + +/* This code executes before _start, which is contained inside the C library. + * In embedded systems we want to ensure that _enter, which contains the first + * code to be executed, can be loaded at a specific address. To enable this + * feature we provide the '.text.metal.init.enter' section, which is + * defined to have the first address being where execution should start. */ +.section .text.metal.init.enter +.global _enter +_enter: + .cfi_startproc + + /* Inform the debugger that there is nowhere to backtrace past _enter. */ + .cfi_undefined ra + + /* The absolute first thing that must happen is configuring the global + * pointer register, which must be done with relaxation disabled because + * it's not valid to obtain the address of any symbol without GP + * configured. The C environment might go ahead and do this again, but + * that's safe as it's a fixed register. */ +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + /* Disable global interrupt */ + /*clear_csr(mstatus, MSTATUS_MIE);*/ + csrci mstatus,8 + + /* If there is a clint then interrupts can branch directly to the + * trap handler. Otherwise the interrupt controller will need to be configured + * outside of this file. */ +#ifndef TRAP_ENRTY + la t0, Trap_Handler_Stub +#else + la t0, TRAP_ENRTY +#endif + ori t0, t0, 2 + csrw mtvec, t0 + + /* enable chicken bit if core is bullet series*/ + la t0, __metal_chicken_bit + beqz t0, 1f + csrwi 0x7C1, 0 +1: + + /* There may be pre-initialization routines inside the MBI code that run in + * C, so here we set up a C environment. First we set up a stack pointer, + * which is left as a weak reference in order to allow initialization + * routines that do not need a stack to be set up to transparently be + * called. */ + .weak __StackTop + la sp, __StackTop +#ifdef __riscv_float_abi_single + /* deal with FP */ + /* Is F extension present? */ + csrr t0, misa + andi t0, t0, (1 << ('F' - 'A')) + beqz t0, 1f + /* If so, enable it */ + li t0, MSTATUS_FS + csrs mstatus, t0 + fssr x0 +1: +#endif + + /* Check for an initialization routine and call it if one exists, otherwise + * just skip over the call entirely. Note that __metal_initialize isn't + * actually a full C function, as it doesn't end up with the .bss or .data + * segments having been initialized. This is done to avoid putting a + * burden on systems that can be initialized without having a C environment + * set up. */ + call SystemInit + + /* start load code to itcm like. */ + call start_load + + jal System_Post_Init + /* At this point we can enter the C runtime's startup file. The arguments + * to this function are designed to match those provided to the SEE, just + * so we don't have to write another ABI. */ + csrr a0, mhartid + li a1, 0 + li a2, 0 + call entry + + csrci mstatus, (1 << 3) + +__exit: + j __exit + + .cfi_endproc + +/* For sanity's sake we set up an early trap vector that just does nothing. If + * you end up here then there's a bug in the early boot code somewhere. */ +.weak Trap_Handler_Stub +.section .text.metal.init.trapvec +.align 2 +Trap_Handler_Stub: + .cfi_startproc + csrr t0, mcause + csrr t1, mepc + csrr t2, mtval + j Trap_Handler_Stub + .cfi_endproc + +/* The GCC port might not emit a __register_frame_info symbol, which eventually + * results in a weak undefined reference that eventually causes crash when it + * is dereference early in boot. We really shouldn't need to put this here, + * but to deal with what I think is probably a bug in the linker script I'm + * going to leave this in for now. At least it's fairly cheap :) */ +.weak __register_frame_info +.global __register_frame_info +.section .text.metal.init.__register_frame_info +__register_frame_info: + .cfi_startproc + ret + .cfi_endproc diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/GCC/start_load.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/GCC/start_load.c new file mode 100644 index 0000000000000000000000000000000000000000..372cd1f9fc81730c9fefac3258321d9181e37c7d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/GCC/start_load.c @@ -0,0 +1,90 @@ +#include +#include "bl602.h" + +#define __STARTUP_CLEAR_BSS 1 + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __itcm_load_addr; +extern uint32_t __dtcm_load_addr; +extern uint32_t __system_ram_load_addr; +extern uint32_t __ram_load_addr; + +extern uint32_t __text_code_start__; +extern uint32_t __text_code_end__; +extern uint32_t __tcm_code_start__; +extern uint32_t __tcm_code_end__; +extern uint32_t __tcm_data_start__; +extern uint32_t __tcm_data_end__; +extern uint32_t __system_ram_data_start__; +extern uint32_t __system_ram_data_end__; +extern uint32_t __ram_data_start__; +extern uint32_t __ram_data_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __noinit_data_start__; +extern uint32_t __noinit_data_end__; + +extern uint32_t __StackTop; +extern uint32_t __StackLimit; + +//extern uint32_t __copy_table_start__; +//extern uint32_t __copy_table_end__; +//extern uint32_t __zero_table_start__; +//extern uint32_t __zero_table_end__; + +void start_load(void) +{ + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + + /* Copy ITCM code */ + pSrc = &__itcm_load_addr; + pDest = &__tcm_code_start__; + + for (; pDest < &__tcm_code_end__;) { + *pDest++ = *pSrc++; + } + + /* Copy DTCM code */ + pSrc = &__dtcm_load_addr; + pDest = &__tcm_data_start__; + + for (; pDest < &__tcm_data_end__;) { + *pDest++ = *pSrc++; + } + + /* BF Add system RAM data copy */ + pSrc = &__system_ram_load_addr; + pDest = &__system_ram_data_start__; + + for (; pDest < &__system_ram_data_end__;) { + *pDest++ = *pSrc++; + } + + /* BF Add OCARAM data copy */ + pSrc = &__ram_load_addr; + pDest = &__ram_data_start__; + + for (; pDest < &__ram_data_end__;) { + *pDest++ = *pSrc++; + } + +#ifdef __STARTUP_CLEAR_BSS + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for (; pDest < &__bss_end__;) { + *pDest++ = 0ul; + } + +#endif +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/interrupt.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..062596d4ea305214030f252542c7895be05b4cc1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/interrupt.c @@ -0,0 +1,191 @@ +#include + +#include "../risc-v/Core/Include/clic.h" +#include "../risc-v/Core/Include/cmsis_compatible_gcc.h" + +typedef void (*pFunc)(void); +extern void trap_handler(void); +extern void Interrupt_Handler(void); +void Interrupt_Handler_Stub(void); + +void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void clic_mtimer_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void clic_mext_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void clic_csoft_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void L1C_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void L1C_BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void RF_TOP_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void RF_TOP_INT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SDIO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void DMA_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_GMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_CDET_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_PKA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_TRNG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_SHA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void DMA_ALL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void IRTX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void IRRX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SF_CTRL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void GPADC_DMA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void EFUSE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SPI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void UART0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void UART1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void I2C_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void PWM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_CH0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_CH1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_WDT_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void GPIO_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void PDS_WAKEUP_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void HBN_OUT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void HBN_OUT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BOR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void WIFI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BZ_PHY_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BLE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TXRX_TIMER_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TXRX_MISC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_RX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_GEN_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_PORT_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void WIFI_IPC_PUBLIC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); + +const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = { + 0, /* */ + 0, /* */ + 0, /* */ + clic_msip_handler_Wrapper, /* */ + 0, /* */ + 0, /* */ + 0, /* */ + clic_mtimer_handler_Wrapper, /* */ + (pFunc)0x00000004, /* */ + (pFunc)0x00001007, /* */ + (pFunc)0x00010102, /* */ //disable log as default + clic_mext_handler_Wrapper, /* */ + clic_csoft_handler_Wrapper, /* */ + (pFunc)2000000, /* */ + 0, /* */ + 0, /* */ + BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */ + BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */ + L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */ + L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */ + SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */ + RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */ + RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */ + SDIO_IRQHandler_Wrapper, /* 16 + 7 */ + DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */ + SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */ + SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */ + SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */ + SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */ + SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */ + SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */ + DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */ + 0, /* 16 + 16 */ + 0, /* 16 + 17 */ + 0, /* 16 + 18 */ + IRTX_IRQHandler_Wrapper, /* 16 + 19 */ + IRRX_IRQHandler_Wrapper, /* 16 + 20 */ + 0, /* 16 + 21 */ + 0, /* 16 + 22 */ + SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */ + 0, /* 16 + 24 */ + GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */ + EFUSE_IRQHandler_Wrapper, /* 16 + 26 */ + SPI_IRQHandler_Wrapper, /* 16 + 27 */ + 0, /* 16 + 28 */ + UART0_IRQHandler_Wrapper, /* 16 + 29 */ + UART1_IRQHandler_Wrapper, /* 16 + 30 */ + 0, /* 16 + 31 */ + I2C_IRQHandler_Wrapper, /* 16 + 32 */ + 0, /* 16 + 33 */ + PWM_IRQHandler_Wrapper, /* 16 + 34 */ + 0, /* 16 + 35 */ + TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */ + TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */ + TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */ + 0, /* 16 + 39 */ + 0, /* 16 + 40 */ + 0, /* 16 + 41 */ + 0, /* 16 + 42 */ + 0, /* 16 + 43 */ + GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */ + 0, /* 16 + 45 */ + 0, /* 16 + 46 */ + 0, /* 16 + 47 */ + 0, /* 16 + 48 */ + 0, /* 16 + 49 */ + PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */ + HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */ + HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */ + BOR_IRQHandler_Wrapper, /* 16 + 53 */ + WIFI_IRQHandler_Wrapper, /* 16 + 54 */ + BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */ + BLE_IRQHandler_Wrapper, /* 16 + 56 */ + MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */ + MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */ + MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */ + MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */ + MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */ + MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */ + WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */ +}; + +void __IRQ_ALIGN64 Trap_Handler_Stub(void) +{ + trap_handler(); +} + +void __IRQ Interrupt_Handler_Stub(void) +{ + Interrupt_Handler(); +} + +void clic_enable_interrupt(uint32_t source) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1; +} + +void clic_disable_interrupt(uint32_t source) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0; +} + +void clic_set_pending(uint32_t source) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1; +} + +void clic_clear_pending(uint32_t source) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0; +} + +void clic_set_intcfg(uint32_t source, uint32_t intcfg) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source) = intcfg; +} + +uint8_t clic_get_intcfg(uint32_t source) +{ + return *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source); +} + +void clic_set_cliccfg(uint32_t cfg) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_CFG) = cfg; +} + +uint8_t clic_get_cliccfg(void) +{ + return *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_CFG); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/system_bl602.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/system_bl602.c new file mode 100644 index 0000000000000000000000000000000000000000..38102373b53bc922338ac9214fead1f640fbe9df --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/system_bl602.c @@ -0,0 +1,96 @@ +#include "bl602.h" +#include "bl602_glb.h" +#include "bl602_hbn.h" +#include "system_bl602.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define SYSTEM_CLOCK (32000000UL) + +/*---------------------------------------------------------------------------- + Vector Table + *----------------------------------------------------------------------------*/ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ + +void system_bor_init(void) +{ + HBN_BOR_CFG_Type borCfg = { 1 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 1 /* bor_sel */ }; + HBN_Set_BOR_Cfg(&borCfg); +} + +void SystemInit(void) +{ + uint32_t *p; + uint32_t i = 0; + uint32_t tmpVal = 0; + + __disable_irq(); + + /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + /* GLB_Set_EM_Sel(GLB_EM_0KB); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB); + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + /* Fix 26M xtal clkpll_sdmin */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); + + if (0x49D39D == BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN)) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D89E); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal); + } + + /* Restore default setting*/ + /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + /* GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, JTAG_SIG_SWAP_NONE); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + /* CLear all interrupt */ + p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + /* init bor for all platform */ + system_bor_init(); + /* global IRQ enable */ + __enable_irq(); +} + +/*identify flash config automaticly*/ +extern BL_Err_Type flash_init(void); +extern void bflb_platform_print_set(uint8_t disable); +void System_Post_Init(void) +{ + PDS_Trim_RC32M(); + HBN_Trim_RC32K(); + bflb_platform_print_set(1); + flash_init(); + bflb_platform_print_set(0); +} + +void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/system_bl602.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/system_bl602.h new file mode 100644 index 0000000000000000000000000000000000000000..f1e3380fde70fa5ba20011a5afccb080042c14d0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/startup/system_bl602.h @@ -0,0 +1,16 @@ +#ifndef __SYSTEM_BL602_H__ +#define __SYSTEM_BL602_H__ + +/** + * @brief PLL Clock type definition + */ + +extern uint32_t SystemCoreClock; + +extern void SystemCoreClockUpdate(void); +extern void SystemInit(void); +extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +extern void Systick_Stop(void); +extern void Systick_Start(void); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_acomp.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_acomp.h new file mode 100644 index 0000000000000000000000000000000000000000..c52de8ed359f5c1d120b1fbea135b3cf3c5cfafd --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_acomp.h @@ -0,0 +1,213 @@ +/** + ****************************************************************************** + * @file bl602_acomp.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_ACOMP_H__ +#define __BL602_ACOMP_H__ + +#include "aon_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ACOMP + * @{ + */ + +/** @defgroup ACOMP_Public_Types + * @{ + */ + +/** + * @brief Analog compare id type definition + */ +typedef enum { + AON_ACOMP0_ID, /*!< Analog compare 0 */ + AON_ACOMP1_ID, /*!< Analog compare 1 */ +} AON_ACOMP_ID_Type; + +/** + * @brief Analog compare level type definition + */ +typedef enum { + AON_ACOMP_LEVEL_FACTOR_0P25, /*!< Analog compare level scaling factor 0.25 */ + AON_ACOMP_LEVEL_FACTOR_0P5, /*!< Analog compare level scaling factor 0.5 */ + AON_ACOMP_LEVEL_FACTOR_0P75, /*!< Analog compare level scaling factor 0.75 */ + AON_ACOMP_LEVEL_FACTOR_1, /*!< Analog compare level scaling factor 1 */ +} AON_ACOMP_Level_Factor_Type; + +/** + * @brief Analog compare channel type definition + */ +typedef enum { + AON_ACOMP_CHAN_ADC0, /*!< Analog compare channel,ADC input channel 0 */ + AON_ACOMP_CHAN_ADC1, /*!< Analog compare channel,ADC input channel 1 */ + AON_ACOMP_CHAN_ADC2, /*!< Analog compare channel,ADC input channel 2 */ + AON_ACOMP_CHAN_ADC3, /*!< Analog compare channel,ADC input channel 3 */ + AON_ACOMP_CHAN_ADC4, /*!< Analog compare channel,ADC input channel 4 */ + AON_ACOMP_CHAN_ADC5, /*!< Analog compare channel,ADC input channel 5 */ + AON_ACOMP_CHAN_ADC6, /*!< Analog compare channel,ADC input channel 6 */ + AON_ACOMP_CHAN_ADC7, /*!< Analog compare channel,ADC input channel 7 */ + AON_ACOMP_CHAN_DACA, /*!< Analog compare channel,DAC output channel A */ + AON_ACOMP_CHAN_DACB, /*!< Analog compare channel,DAC output channel B */ + AON_ACOMP_CHAN_VREF_1P2V, /*!< Analog compare channel,1.2V ref voltage */ + AON_ACOMP_CHAN_0P375VBAT_NOT_IMP, /*!< Analog compare channel,6/16Vbat */ + AON_ACOMP_CHAN_0P25VBAT, /*!< Analog compare channel,4/16Vbat */ + AON_ACOMP_CHAN_0P1875VBAT, /*!< Analog compare channel,3/16Vbat */ + AON_ACOMP_CHAN_0P3125VBAT, /*!< Analog compare channel,5/16Vbat */ + AON_ACOMP_CHAN_VSS, /*!< Analog compare channel,vss */ +} AON_ACOMP_Chan_Type; + +/** + * @brief Analog compare bias current control type definition + */ +typedef enum { + AON_ACOMP_BIAS_POWER_MODE1, /*!< Analog compare power mode 1,slow response mode */ + AON_ACOMP_BIAS_POWER_MODE2, /*!< Analog compare power mode 2,medium response mode */ + AON_ACOMP_BIAS_POWER_MODE3, /*!< Analog compare power mode 3,fast response mode */ + AON_ACOMP_BIAS_POWER_NONE, /*!< Analog compare power mode none */ +} AON_ACOMP_Bias_Prog_Type; + +/** + * @brief Analog compare hysteresis voltage type definition + */ +typedef enum { + AON_ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */ + AON_ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */ + AON_ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */ + AON_ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */ + AON_ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */ + AON_ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */ + AON_ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */ + AON_ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */ +} AON_ACOMP_Hysteresis_Volt_Type; + +/** + * @brief AON ACOMP configuration type definition + */ +typedef struct +{ + BL_Fun_Type muxEn; /*!< ACOMP mux enable */ + uint8_t posChanSel; /*!< ACOMP positive channel select */ + uint8_t negChanSel; /*!< ACOMP negtive channel select */ + AON_ACOMP_Level_Factor_Type levelFactor; /*!< ACOMP level select factor */ + AON_ACOMP_Bias_Prog_Type biasProg; /*!< ACOMP bias current control */ + AON_ACOMP_Hysteresis_Volt_Type hysteresisPosVolt; /*!< ACOMP hysteresis voltage for positive */ + AON_ACOMP_Hysteresis_Volt_Type hysteresisNegVolt; /*!< ACOMP hysteresis voltage for negtive */ +} AON_ACOMP_CFG_Type; + +/*@} end of group ACOMP_Public_Types */ + +/** @defgroup ACOMP_Public_Constants + * @{ + */ + +/** @defgroup AON_ACOMP_ID_TYPE + * @{ + */ +#define IS_AON_ACOMP_ID_TYPE(type) (((type) == AON_ACOMP0_ID) || \ + ((type) == AON_ACOMP1_ID)) + +/** @defgroup AON_ACOMP_LEVEL_FACTOR_TYPE + * @{ + */ +#define IS_AON_ACOMP_LEVEL_FACTOR_TYPE(type) (((type) == AON_ACOMP_LEVEL_FACTOR_0P25) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_0P5) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_0P75) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_1)) + +/** @defgroup AON_ACOMP_CHAN_TYPE + * @{ + */ +#define IS_AON_ACOMP_CHAN_TYPE(type) (((type) == AON_ACOMP_CHAN_ADC0) || \ + ((type) == AON_ACOMP_CHAN_ADC1) || \ + ((type) == AON_ACOMP_CHAN_ADC2) || \ + ((type) == AON_ACOMP_CHAN_ADC3) || \ + ((type) == AON_ACOMP_CHAN_ADC4) || \ + ((type) == AON_ACOMP_CHAN_ADC5) || \ + ((type) == AON_ACOMP_CHAN_ADC6) || \ + ((type) == AON_ACOMP_CHAN_ADC7) || \ + ((type) == AON_ACOMP_CHAN_DACA) || \ + ((type) == AON_ACOMP_CHAN_DACB) || \ + ((type) == AON_ACOMP_CHAN_VREF_1P2V) || \ + ((type) == AON_ACOMP_CHAN_0P375VBAT_NOT_IMP) || \ + ((type) == AON_ACOMP_CHAN_0P25VBAT) || \ + ((type) == AON_ACOMP_CHAN_0P1875VBAT) || \ + ((type) == AON_ACOMP_CHAN_0P3125VBAT) || \ + ((type) == AON_ACOMP_CHAN_VSS)) + +/** @defgroup AON_ACOMP_BIAS_PROG_TYPE + * @{ + */ +#define IS_AON_ACOMP_BIAS_PROG_TYPE(type) (((type) == AON_ACOMP_BIAS_POWER_MODE1) || \ + ((type) == AON_ACOMP_BIAS_POWER_MODE2) || \ + ((type) == AON_ACOMP_BIAS_POWER_MODE3) || \ + ((type) == AON_ACOMP_BIAS_POWER_NONE)) + +/** @defgroup AON_ACOMP_HYSTERESIS_VOLT_TYPE + * @{ + */ +#define IS_AON_ACOMP_HYSTERESIS_VOLT_TYPE(type) (((type) == AON_ACOMP_HYSTERESIS_VOLT_NONE) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_10MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_20MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_30MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_40MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_50MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_60MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_70MV)) + +/*@} end of group ACOMP_Public_Constants */ + +/** @defgroup ACOMP_Public_Macros + * @{ + */ + +/*@} end of group ACOMP_Public_Macros */ + +/** @defgroup ACOMP_Public_Functions + * @{ + */ +void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg); +void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo); +BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo); + +/*@} end of group ACOMP_Public_Functions */ + +/*@} end of group ACOMP */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_ACOMP_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_adc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..77d0fda377638cd7403de89d03723e2ffa187183 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_adc.h @@ -0,0 +1,546 @@ +/** + ****************************************************************************** + * @file bl602_adc.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_ADC_H__ +#define __BL602_ADC_H__ + +#include "aon_reg.h" +#include "gpip_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Public_Types + * @{ + */ + +/** + * @brief ADC channel type definition + */ +typedef enum { + ADC_CHAN0, /*!< GPIO 0, ADC channel 0 */ + ADC_CHAN1, /*!< GPIO 1, ADC channel 1 */ + ADC_CHAN2, /*!< GPIO 2, ADC channel 2 */ + ADC_CHAN3, /*!< GPIO 3, ADC channel 3 */ + ADC_CHAN4, /*!< GPIO 4, ADC channel 4 */ + ADC_CHAN5, /*!< GPIO 5, ADC channel 5 */ + ADC_CHAN6, /*!< GPIO 6, ADC channel 6 */ + ADC_CHAN7, /*!< GPIO 7, ADC channel 7 */ + ADC_CHAN8, /*!< GPIO 8, ADC channel 8 */ + ADC_CHAN9, /*!< GPIO 9, ADC channel 9 */ + ADC_CHAN10, /*!< GPIO 10, ADC channel 10 */ + ADC_CHAN11, /*!< GPIO 11, ADC channel 11 */ + ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */ + ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */ + ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */ + ADC_CHAN_TSEN_N, /*!< TSenn, ADC channel 15 */ + ADC_CHAN_VREF, /*!< Vref, ADC channel 16 */ + ADC_CHAN_DCTEST, /*!< DCTest, ADC channel 17 */ + ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */ + ADC_CHAN_SENP3, /*!< SenVP3, ADC channel 19 */ + ADC_CHAN_SENP2, /*!< SenVP2, ADC channel 20 */ + ADC_CHAN_SENP1, /*!< SenVP1, ADC channel 21 */ + ADC_CHAN_SENP0, /*!< SenVP0, ADC channel 22 */ + ADC_CHAN_GND, /*!< GND, ADC channel 23 */ +} ADC_Chan_Type; + +/** + * @brief ADC V18 selection type definition + */ +typedef enum { + ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */ + ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */ + ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */ + ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */ +} ADC_V18_SEL_Type; + +/** + * @brief ADC V11 selection type definition + */ +typedef enum { + ADC_V11_SEL_1P0V, /*!< V11 select 1.0V */ + ADC_V11_SEL_1P1V, /*!< V11 select 1.1V */ + ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */ + ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */ +} ADC_V11_SEL_Type; + +/** + * @brief ADC clock type definition + */ +typedef enum { + ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ + ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ + ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ + ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ + ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ + ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ + ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ + ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ +} ADC_CLK_Type; + +/** + * @brief ADC conversion speed type definition + */ +typedef enum { + ADC_DELAY_SEL_0, /*!< Select delay 0 */ + ADC_DELAY_SEL_1, /*!< Select delay 1 */ + ADC_DELAY_SEL_2, /*!< Select delay 2 */ + ADC_DELAY_SEL_3, /*!< Select delay 3 */ + ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */ + ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */ + ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */ + ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */ +} ADC_DELAY_SEL_Type; + +/** + * @brief ADC PGA gain type definition + */ +typedef enum { + ADC_PGA_GAIN_NONE, /*!< No PGA gain */ + ADC_PGA_GAIN_1, /*!< PGA gain 1 */ + ADC_PGA_GAIN_2, /*!< PGA gain 2 */ + ADC_PGA_GAIN_4, /*!< PGA gain 4 */ + ADC_PGA_GAIN_8, /*!< PGA gain 8 */ + ADC_PGA_GAIN_16, /*!< PGA gain 16 */ + ADC_PGA_GAIN_32, /*!< PGA gain 32 */ +} ADC_PGA_GAIN_Type; + +/** + * @brief ADC analog portion low power mode selection type definition + */ +typedef enum { + ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */ + ADC_BIAS_SEL_AON_BANDGAP, /*!< ADC current from aon bandgap for HBN mode */ +} ADC_BIAS_SEL_Type; + +/** + * @brief ADC chop mode type definition + */ +typedef enum { + ADC_CHOP_MOD_ALL_OFF, /*!< all off */ + ADC_CHOP_MOD_AZ_ON, /*!< Vref AZ on */ + ADC_CHOP_MOD_AZ_PGA_ON, /*!< Vref AZ and PGA chop on */ + ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */ +} ADC_CHOP_MOD_Type; + +/** + * @brief ADC audio PGA output common mode control type definition + */ +typedef enum { + ADC_PGA_VCM_1V, /*!< ADC VCM=1V */ + ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */ + ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */ + ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */ +} ADC_PGA_VCM_Type; + +/** + * @brief ADC tsen diode mode type definition + */ +typedef enum { + ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */ + ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */ +} ADC_TSEN_MOD_Type; + +/** + * @brief ADC voltage reference type definition + */ +typedef enum { + ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */ + ADC_VREF_2V, /*!< ADC select 2V as reference voltage */ +} ADC_VREF_Type; + +/** + * @brief ADC signal input type definition + */ +typedef enum { + ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */ + ADC_INPUT_DIFF, /*!< ADC signal is differential */ +} ADC_SIG_INPUT_Type; + +/** + * @brief ADC data width type definition + */ +typedef enum { + ADC_DATA_WIDTH_12, /*!< ADC 12 bits */ + ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ + ADC_DATA_WIDTH_16_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */ + ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ + ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ +} ADC_Data_Width_Type; + +/** + * @brief ADC micboost 32db type definition + */ +typedef enum { + ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */ + ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */ +} ADC_MICBOOST_DB_Type; + +/** + * @brief ADC pga2 gain type definition + */ +typedef enum { + ADC_PGA2_GAIN_0DB, /*!< MIC pga2 gain 0db */ + ADC_PGA2_GAIN_6DB, /*!< MIC pga2 gain 6db */ + ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */ + ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */ +} ADC_PGA2_GAIN_Type; + +/** + * @brief ADC mic mode type definition + */ +typedef enum { + ADC_MIC_MODE_SINGLE, /*!< MIC single mode */ + ADC_MIC_MODE_DIFF, /*!< MIC diff mode */ +} ADC_MIC_MODE_Type; + +/** + * @brief ADC mic type definition + */ +typedef struct +{ + ADC_MICBOOST_DB_Type micboostDb; /*!< MIC boost db */ + ADC_PGA2_GAIN_Type micPga2Gain; /*!< MIC pga2 gain */ + ADC_MIC_MODE_Type mic1Mode; /*!< MIC1 single or diff */ + ADC_MIC_MODE_Type mic2Mode; /*!< MIC2 single or diff */ + BL_Fun_Type dwaEn; /*!< Improve dynamic performance */ + BL_Fun_Type micboostBypassEn; /*!< MIC boost amp bypass enable or disable */ + BL_Fun_Type micPgaEn; /*!< MIC pga enable or disable */ + BL_Fun_Type micBiasEn; /*!< MIC bias enable or disable */ +} ADC_MIC_Type; + +/** + * @brief ADC configuration type definition + */ +typedef struct +{ + ADC_V18_SEL_Type v18Sel; /*!< ADC 1.8V select */ + ADC_V11_SEL_Type v11Sel; /*!< ADC 1.1V select */ + ADC_CLK_Type clkDiv; /*!< Clock divider */ + ADC_PGA_GAIN_Type gain1; /*!< PGA gain 1 */ + ADC_PGA_GAIN_Type gain2; /*!< PGA gain 2 */ + ADC_CHOP_MOD_Type chopMode; /*!< ADC chop mode select */ + ADC_BIAS_SEL_Type biasSel; /*!< ADC current form main bandgap or aon bandgap */ + ADC_PGA_VCM_Type vcm; /*!< ADC VCM value */ + ADC_VREF_Type vref; /*!< ADC voltage reference */ + ADC_SIG_INPUT_Type inputMode; /*!< ADC input signal type */ + ADC_Data_Width_Type resWidth; /*!< ADC resolution and oversample rate */ + BL_Fun_Type offsetCalibEn; /*!< Offset calibration enable */ + int16_t offsetCalibVal; /*!< Offset calibration value */ +} ADC_CFG_Type; + +/** + * @brief ADC configuration type definition + */ +typedef struct +{ + int8_t posChan; /*!< Positive channel */ + int8_t negChan; /*!< Negative channel */ + uint16_t value; /*!< ADC value */ + float volt; /*!< ADC voltage result */ +} ADC_Result_Type; + +/** + * @brief ADC FIFO threshold type definition + */ +typedef enum { + ADC_FIFO_THRESHOLD_1, /*!< ADC FIFO threshold is 1 */ + ADC_FIFO_THRESHOLD_4, /*!< ADC FIFO threshold is 4 */ + ADC_FIFO_THRESHOLD_8, /*!< ADC FIFO threshold is 8 */ + ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */ +} ADC_FIFO_Threshold_Type; + +/** + * @brief ADC interrupt type definition + */ +typedef enum { + ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */ + ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */ + ADC_INT_FIFO_UNDERRUN, /*!< ADC FIFO underrun interrupt */ + ADC_INT_FIFO_OVERRUN, /*!< ADC FIFO overrun interrupt */ + ADC_INT_ADC_READY, /*!< ADC data ready interrupt */ + ADC_INT_ALL, /*!< ADC all the interrupt */ +} ADC_INT_Type; + +/** + * @brief ADC FIFO configuration structure type definition + */ +typedef struct +{ + ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */ + BL_Fun_Type dmaEn; /*!< ADC DMA enable */ +} ADC_FIFO_Cfg_Type; + +/** + * @brief ADC REG GAIN CAL + */ +typedef struct +{ + BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */ + uint16_t adcgainCoeffVal; /*!< ADC_Gain_Coeff value */ + float coe; /*!< ADC_Gain_Coeff result */ +} ADC_Gain_Coeff_Type; + +/*@} end of group ADC_Public_Types */ + +/** @defgroup ADC_Public_Constants + * @{ + */ + +/** @defgroup ADC_CHAN_TYPE + * @{ + */ +#define IS_ADC_CHAN_TYPE(type) (((type) == ADC_CHAN0) || \ + ((type) == ADC_CHAN1) || \ + ((type) == ADC_CHAN2) || \ + ((type) == ADC_CHAN3) || \ + ((type) == ADC_CHAN4) || \ + ((type) == ADC_CHAN5) || \ + ((type) == ADC_CHAN6) || \ + ((type) == ADC_CHAN7) || \ + ((type) == ADC_CHAN8) || \ + ((type) == ADC_CHAN9) || \ + ((type) == ADC_CHAN10) || \ + ((type) == ADC_CHAN11) || \ + ((type) == ADC_CHAN_DAC_OUTA) || \ + ((type) == ADC_CHAN_DAC_OUTB) || \ + ((type) == ADC_CHAN_TSEN_P) || \ + ((type) == ADC_CHAN_TSEN_N) || \ + ((type) == ADC_CHAN_VREF) || \ + ((type) == ADC_CHAN_DCTEST) || \ + ((type) == ADC_CHAN_VABT_HALF) || \ + ((type) == ADC_CHAN_SENP3) || \ + ((type) == ADC_CHAN_SENP2) || \ + ((type) == ADC_CHAN_SENP1) || \ + ((type) == ADC_CHAN_SENP0) || \ + ((type) == ADC_CHAN_GND)) + +/** @defgroup ADC_V18_SEL_TYPE + * @{ + */ +#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || \ + ((type) == ADC_V18_SEL_1P72V) || \ + ((type) == ADC_V18_SEL_1P82V) || \ + ((type) == ADC_V18_SEL_1P92V)) + +/** @defgroup ADC_V11_SEL_TYPE + * @{ + */ +#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || \ + ((type) == ADC_V11_SEL_1P1V) || \ + ((type) == ADC_V11_SEL_1P18V) || \ + ((type) == ADC_V11_SEL_1P26V)) + +/** @defgroup ADC_CLK_TYPE + * @{ + */ +#define IS_ADC_CLK_TYPE(type) (((type) == ADC_CLK_DIV_1) || \ + ((type) == ADC_CLK_DIV_4) || \ + ((type) == ADC_CLK_DIV_8) || \ + ((type) == ADC_CLK_DIV_12) || \ + ((type) == ADC_CLK_DIV_16) || \ + ((type) == ADC_CLK_DIV_20) || \ + ((type) == ADC_CLK_DIV_24) || \ + ((type) == ADC_CLK_DIV_32)) + +/** @defgroup ADC_DELAY_SEL_TYPE + * @{ + */ +#define IS_ADC_DELAY_SEL_TYPE(type) (((type) == ADC_DELAY_SEL_0) || \ + ((type) == ADC_DELAY_SEL_1) || \ + ((type) == ADC_DELAY_SEL_2) || \ + ((type) == ADC_DELAY_SEL_3) || \ + ((type) == ADC_DELAY_SEL_4) || \ + ((type) == ADC_DELAY_SEL_5) || \ + ((type) == ADC_DELAY_SEL_6) || \ + ((type) == ADC_DELAY_SEL_7)) + +/** @defgroup ADC_PGA_GAIN_TYPE + * @{ + */ +#define IS_ADC_PGA_GAIN_TYPE(type) (((type) == ADC_PGA_GAIN_NONE) || \ + ((type) == ADC_PGA_GAIN_1) || \ + ((type) == ADC_PGA_GAIN_2) || \ + ((type) == ADC_PGA_GAIN_4) || \ + ((type) == ADC_PGA_GAIN_8) || \ + ((type) == ADC_PGA_GAIN_16) || \ + ((type) == ADC_PGA_GAIN_32)) + +/** @defgroup ADC_BIAS_SEL_TYPE + * @{ + */ +#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || \ + ((type) == ADC_BIAS_SEL_AON_BANDGAP)) + +/** @defgroup ADC_CHOP_MOD_TYPE + * @{ + */ +#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || \ + ((type) == ADC_CHOP_MOD_AZ_ON) || \ + ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || \ + ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON)) + +/** @defgroup ADC_PGA_VCM_TYPE + * @{ + */ +#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || \ + ((type) == ADC_PGA_VCM_1P2V) || \ + ((type) == ADC_PGA_VCM_1P4V) || \ + ((type) == ADC_PGA_VCM_1P6V)) + +/** @defgroup ADC_TSEN_MOD_TYPE + * @{ + */ +#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || \ + ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE)) + +/** @defgroup ADC_VREF_TYPE + * @{ + */ +#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P2V) || \ + ((type) == ADC_VREF_2V)) + +/** @defgroup ADC_SIG_INPUT_TYPE + * @{ + */ +#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || \ + ((type) == ADC_INPUT_DIFF)) + +/** @defgroup ADC_DATA_WIDTH_TYPE + * @{ + */ +#define IS_ADC_DATA_WIDTH_TYPE(type) (((type) == ADC_DATA_WIDTH_12) || \ + ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_64_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) + +/** @defgroup ADC_MICBOOST_DB_TYPE + * @{ + */ +#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || \ + ((type) == ADC_MICBOOST_DB_32DB)) + +/** @defgroup ADC_PGA2_GAIN_TYPE + * @{ + */ +#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || \ + ((type) == ADC_PGA2_GAIN_6DB) || \ + ((type) == ADC_PGA2_GAIN_N6DB) || \ + ((type) == ADC_PGA2_GAIN_12DB)) + +/** @defgroup ADC_MIC_MODE_TYPE + * @{ + */ +#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || \ + ((type) == ADC_MIC_MODE_DIFF)) + +/** @defgroup ADC_FIFO_THRESHOLD_TYPE + * @{ + */ +#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || \ + ((type) == ADC_FIFO_THRESHOLD_4) || \ + ((type) == ADC_FIFO_THRESHOLD_8) || \ + ((type) == ADC_FIFO_THRESHOLD_16)) + +/** @defgroup ADC_INT_TYPE + * @{ + */ +#define IS_ADC_INT_TYPE(type) (((type) == ADC_INT_POS_SATURATION) || \ + ((type) == ADC_INT_NEG_SATURATION) || \ + ((type) == ADC_INT_FIFO_UNDERRUN) || \ + ((type) == ADC_INT_FIFO_OVERRUN) || \ + ((type) == ADC_INT_ADC_READY) || \ + ((type) == ADC_INT_ALL)) + +/*@} end of group ADC_Public_Constants */ + +/** @defgroup ADC_Public_Macros + * @{ + */ + +/*@} end of group ADC_Public_Macros */ + +/** @defgroup ADC_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void GPADC_DMA_IRQHandler(void); +#endif +void ADC_Vbat_Enable(void); +void ADC_Vbat_Disable(void); +void ADC_Reset(void); +void ADC_Enable(void); +void ADC_Disable(void); +void ADC_Init(ADC_CFG_Type *cfg); +void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn); +void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn); +void ADC_Start(void); +void ADC_Stop(void); +void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg); +uint8_t ADC_Get_FIFO_Count(void); +BL_Sts_Type ADC_FIFO_Is_Empty(void); +BL_Sts_Type ADC_FIFO_Is_Full(void); +uint32_t ADC_Read_FIFO(void); +void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result); +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); +void ADC_IntClr(ADC_INT_Type intType); +BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType); +void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun); +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); +void ADC_SET_TSVBE_LOW(void); +void ADC_SET_TSVBE_HIGH(void); +void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod); +BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config); +void ADC_MIC_Bias_Disable(void); +void ADC_MIC_Bias_Enable(void); +BL_Err_Type ADC_Trim_TSEN(uint16_t *tsen_offset); +BL_Err_Type ADC_Gain_Trim(void); +uint32_t ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg); +float TSEN_Get_Temp(uint32_t tsen_offset); + +/*@} end of group ADC_Public_Functions */ + +/*@} end of group ADC */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_ADC_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_aon.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_aon.h new file mode 100644 index 0000000000000000000000000000000000000000..7762aefbf9fe70bb69bca851b85afaadf143c824 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_aon.h @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file bl602_aon.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_AON_H__ +#define __BL602_AON_H__ + +#include "aon_reg.h" +#include "glb_reg.h" +#include "hbn_reg.h" +#include "pds_reg.h" +#include "bl602_ef_ctrl.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Public_Types + * @{ + */ + +/*@} end of group AON_Public_Types */ + +/** @defgroup AON_Public_Constants + * @{ + */ + +/*@} end of group AON_Public_Constants */ + +/** @defgroup AON_Public_Macros + * @{ + */ + +/*@} end of group AON_Public_Macros */ + +/** @defgroup AON_Public_Functions + * @{ + */ +/*----------*/ +BL_Err_Type AON_Power_On_MBG(void); +BL_Err_Type AON_Power_Off_MBG(void); +/*----------*/ +BL_Err_Type AON_Power_On_XTAL(void); +BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut); +uint8_t AON_Get_Xtal_CapCode(void); +BL_Err_Type AON_Power_Off_XTAL(void); +/*----------*/ +BL_Err_Type AON_Power_On_BG(void); +BL_Err_Type AON_Power_Off_BG(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO11_SOC(void); +BL_Err_Type AON_Power_Off_LDO11_SOC(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO15_RF(void); +BL_Err_Type AON_Power_Off_LDO15_RF(void); +/*----------*/ +BL_Err_Type AON_Power_On_SFReg(void); +BL_Err_Type AON_Power_Off_SFReg(void); +/*----------*/ +BL_Err_Type AON_LowPower_Enter_PDS0(void); +BL_Err_Type AON_LowPower_Exit_PDS0(void); +/*----------*/ +BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay); +/*----------*/; + +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_AON_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_common.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_common.h new file mode 100644 index 0000000000000000000000000000000000000000..ad4b12c31d311973fea21c4203447216580e876a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_common.h @@ -0,0 +1,58 @@ +#ifndef __BL602_COMMON_H__ +#define __BL602_COMMON_H__ + +#include "bl602.h" +#include "bflb_platform.h" + +/** @addtogroup BL606_Peripheral_Driver + * @{ + */ + +/** @addtogroup COMMON + * @{ + */ + +/** @defgroup COMMON_Public_Types + * @{ + */ + +/*@} end of group COMMON_Public_Types */ + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** @defgroup DRIVER_INT_PERIPH + * @{ + */ +#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) + +/*@} end of group DRIVER_INT_PERIPH */ + +/** @defgroup DRIVER_INT_MASK + * @{ + */ +#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) + +/*@} end of group COMMON_Public_Constants */ + +/** @defgroup COMMON_Public_Macros + * @{ + */ + +/*@} end of group DRIVER_Public_Macro */ + +/** @defgroup DRIVER_Public_FunctionDeclaration + * @brief DRIVER functions declaration + * @{ + */ + +#define ARCH_Delay_US BL602_Delay_US +#define ARCH_Delay_MS BL602_Delay_MS + +void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); +void ASM_Delay_Us(uint32_t core, uint32_t cnt); +void BL602_Delay_US(uint32_t cnt); +void BL602_Delay_MS(uint32_t cnt); + +#endif /* __BL602_COMMON_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_dac.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..8563cc04af922bae19c4d294c16818c1a63f0f10 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_dac.h @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file bl602_dac.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_DAC_H__ +#define __BL602_DAC_H__ + +#include "aon_reg.h" +#include "glb_reg.h" +#include "gpip_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Public_Types + * @{ + */ + +/** + * @brief DAC reference voltage definition + */ +typedef enum { + GLB_DAC_REF_SEL_INTERNAL, /*!< DAC reference select internal */ + GLB_DAC_REF_SEL_EXTERNAL, /*!< DAC reference select external */ +} GLB_DAC_Ref_Sel_Type; + +/** + * @brief DAC reference voltage definition + */ +typedef enum { + GLB_DAC_Output_Volt_0P2_1, /*!< DAC output voltage is 0.2-1V */ + GLB_DAC_Output_Volt_0P225_1P425, /*!< DAC output voltage is 0.225-1.425V */ + GLB_DAC_Output_Volt_RESEVED, /*!< DAC output voltage is 0.225-1.425V */ + GLB_DAC_Output_Volt_0P2_1P8, /*!< DAC output voltage is 0.2-1.8V */ +} GLB_DAC_Output_Volt_Range_Type; + +/** + * @brief DAC channel type definition + */ +typedef enum { + GLB_DAC_CHAN0, /*!< DAC channel 0 */ + GLB_DAC_CHAN1, /*!< DAC channel 1 */ + GLB_DAC_CHAN2, /*!< DAC channel 2 */ + GLB_DAC_CHAN3, /*!< DAC channel 3 */ + GLB_DAC_CHAN4, /*!< DAC channel 4 */ + GLB_DAC_CHAN5, /*!< DAC channel 5 */ + GLB_DAC_CHAN6, /*!< DAC channel 6 */ + GLB_DAC_CHAN7, /*!< DAC channel 7 */ + GLB_DAC_CHAN_ALL, /*!< DAC channel all */ +} GLB_DAC_Chan_Type; + +/** + * @brief DAC channel configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + GLB_DAC_Chan_Type outMux; /*!< DAC output mux,NOT implement yet,DAC use fixed GPIO9 and GPIO10 */ + GLB_DAC_Output_Volt_Range_Type outRange; /*!< DAC output voltage range */ +} GLB_DAC_Chan_Cfg_Type; + +/** + * @brief DAC configuration structure type definition + */ +typedef struct +{ + GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ + BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ + BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ +} GLB_DAC_Cfg_Type; + +/** + * @brief DAC channel B source selection type definition + */ +typedef enum { + GPIP_DAC_ChanB_SRC_REG, /*!< select Reg as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_DMA, /*!< select DMA as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_A, /*!< select channel A as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_INVERSE_A, /*!< select inverse of channel A as source of DAC channel B */ +} GPIP_DAC_ChanB_SRC_Type; + +/** + * @brief DAC channel A source selection type definition + */ +typedef enum { + GPIP_DAC_ChanA_SRC_REG, /*!< select Reg as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_DMA, /*!< select DMA as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel A */ +} GPIP_DAC_ChanA_SRC_Type; + +/** + * @brief DAC mode selection type definition + */ +typedef enum { + GPIP_DAC_MOD_32K, /*!< select 32K as DAC mode */ + GPIP_DAC_MOD_16K, /*!< select 16K as DAC mode */ + GPIP_DAC_MOD_RESERVE, /*!< reserved */ + GPIP_DAC_MOD_8K, /*!< select 8K as DAC mode */ + GPIP_DAC_MOD_512K, /*!< select 512 as DAC mode Only For DMA Mode */ +} GPIP_DAC_MOD_Type; + +/** + * @brief DAC DMA TX format selection type definition + */ +typedef enum { + GPIP_DAC_DMA_FORMAT_0, /*!< {A0},{A1},{A2},... */ + GPIP_DAC_DMA_FORMAT_1, /*!< {B0,A0},{B1,A1},{B2,A2},... */ + GPIP_DAC_DMA_FORMAT_2, /*!< {A1,A0},{A3,A2},{A5,A4},... */ +} GPIP_DAC_DMA_TX_FORMAT_Type; + +/** + * @brief AON and GPIP DAC configuration structure type definition + */ +typedef struct +{ + GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ + BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ + BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ + GPIP_DAC_MOD_Type mod; /*!< DAC mode selection */ + BL_Fun_Type dmaEn; /*!< DAC DMA transfer enable */ + GPIP_DAC_DMA_TX_FORMAT_Type dmaFmt; /*!< DAC DMA TX format selection */ +} GLB_GPIP_DAC_Cfg_Type; + +/** + * @brief AON and GPIP DAC channel A configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + GPIP_DAC_ChanA_SRC_Type src; /*!< DAC channel A source */ +} GLB_GPIP_DAC_ChanA_Cfg_Type; + +/** + * @brief AON and GPIP DAC channel B configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + GPIP_DAC_ChanB_SRC_Type src; /*!< DAC channel B source */ +} GLB_GPIP_DAC_ChanB_Cfg_Type; + +/*@} end of group DAC_Public_Types */ + +/** @defgroup DAC_Public_Constants + * @{ + */ + +/** @defgroup GLB_DAC_REF_SEL_TYPE + * @{ + */ +#define IS_GLB_DAC_REF_SEL_TYPE(type) (((type) == GLB_DAC_REF_SEL_INTERNAL) || \ + ((type) == GLB_DAC_REF_SEL_EXTERNAL)) + +/** @defgroup GLB_DAC_OUTPUT_VOLT_RANGE_TYPE + * @{ + */ +#define IS_GLB_DAC_OUTPUT_VOLT_RANGE_TYPE(type) (((type) == GLB_DAC_Output_Volt_0P2_1) || \ + ((type) == GLB_DAC_Output_Volt_0P225_1P425) || \ + ((type) == GLB_DAC_Output_Volt_RESEVED) || \ + ((type) == GLB_DAC_Output_Volt_0P2_1P8)) + +/** @defgroup GLB_DAC_CHAN_TYPE + * @{ + */ +#define IS_GLB_DAC_CHAN_TYPE(type) (((type) == GLB_DAC_CHAN0) || \ + ((type) == GLB_DAC_CHAN1) || \ + ((type) == GLB_DAC_CHAN2) || \ + ((type) == GLB_DAC_CHAN3) || \ + ((type) == GLB_DAC_CHAN4) || \ + ((type) == GLB_DAC_CHAN5) || \ + ((type) == GLB_DAC_CHAN6) || \ + ((type) == GLB_DAC_CHAN7) || \ + ((type) == GLB_DAC_CHAN_ALL)) + +/** @defgroup GPIP_DAC_CHANB_SRC_TYPE + * @{ + */ +#define IS_GPIP_DAC_CHANB_SRC_TYPE(type) (((type) == GPIP_DAC_ChanB_SRC_REG) || \ + ((type) == GPIP_DAC_ChanB_SRC_DMA) || \ + ((type) == GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER) || \ + ((type) == GPIP_DAC_ChanB_SRC_SIN_GEN) || \ + ((type) == GPIP_DAC_ChanB_SRC_A) || \ + ((type) == GPIP_DAC_ChanB_SRC_INVERSE_A)) + +/** @defgroup GPIP_DAC_CHANA_SRC_TYPE + * @{ + */ +#define IS_GPIP_DAC_CHANA_SRC_TYPE(type) (((type) == GPIP_DAC_ChanA_SRC_REG) || \ + ((type) == GPIP_DAC_ChanA_SRC_DMA) || \ + ((type) == GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER) || \ + ((type) == GPIP_DAC_ChanA_SRC_SIN_GEN)) + +/** @defgroup GPIP_DAC_MOD_TYPE + * @{ + */ +#define IS_GPIP_DAC_MOD_TYPE(type) (((type) == GPIP_DAC_MOD_32K) || \ + ((type) == GPIP_DAC_MOD_16K) || \ + ((type) == GPIP_DAC_MOD_RESERVE) || \ + ((type) == GPIP_DAC_MOD_8K) || \ + ((type) == GPIP_DAC_MOD_512K)) + +/** @defgroup GPIP_DAC_DMA_TX_FORMAT_TYPE + * @{ + */ +#define IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(type) (((type) == GPIP_DAC_DMA_FORMAT_0) || \ + ((type) == GPIP_DAC_DMA_FORMAT_1) || \ + ((type) == GPIP_DAC_DMA_FORMAT_2)) + +/*@} end of group DAC_Public_Constants */ + +/** @defgroup DAC_Public_Macros + * @{ + */ + +/*@} end of group DAC_Public_Macros */ + +/** @defgroup DAC_Public_Functions + * @{ + */ +void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg); +void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg); +void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg); +void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src); +void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src); +void GPIP_Set_DAC_Mod_SEL(GPIP_DAC_MOD_Type mod); +void GPIP_DAC_ChanB_Enable(void); +void GPIP_DAC_ChanB_Disable(void); +void GPIP_DAC_ChanA_Enable(void); +void GPIP_DAC_ChanA_Disable(void); +void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt); +void GPIP_Set_DAC_DMA_TX_Enable(void); +void GPIP_Set_DAC_DMA_TX_Disable(void); +void GPIP_DAC_DMA_WriteData(uint32_t data); +BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg); +void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg); +void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg); +void GLB_DAC_Set_ChanA_Value(uint16_t val); +void GLB_DAC_Set_ChanB_Value(uint16_t val); + +/*@} end of group DAC_Public_Functions */ + +/*@} end of group DAC */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_DAC_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_dma.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..c54459e67d9bee33b520667edf1b471bac0f21aa --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_dma.h @@ -0,0 +1,348 @@ +/** + ****************************************************************************** + * @file bl602_dma.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_DMA_H__ +#define __BL602_DMA_H__ + +#include "dma_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Public_Types + * @{ + */ + +/** + * @brief DMA endian type definition + */ +typedef enum { + DMA_LITTLE_ENDIAN = 0, /*!< DMA use little endian */ + DMA_BIG_ENDIAN, /*!< DMA use big endian */ +} DMA_Endian_Type; + +/** + * @brief DMA synchronization logic type definition + */ +typedef enum { + DMA_SYNC_LOGIC_ENABLE = 0, /*!< DMA synchronization logic enable */ + DMA_SYNC_LOGIC_DISABLE, /*!< DMA synchronization logic disable */ +} DMA_Sync_Logic_Type; + +/** + * @brief DMA transfer width type definition + */ +typedef enum { + DMA_TRNS_WIDTH_8BITS = 0, /*!< DMA transfer width:8 bits */ + DMA_TRNS_WIDTH_16BITS, /*!< DMA transfer width:16 bits */ + DMA_TRNS_WIDTH_32BITS, /*!< DMA transfer width:32 bits */ +} DMA_Trans_Width_Type; + +/** + * @brief DMA transfer direction type definition + */ +typedef enum { + DMA_TRNS_M2M = 0, /*!< DMA transfer tyep:memory to memory */ + DMA_TRNS_M2P, /*!< DMA transfer tyep:memory to peripheral */ + DMA_TRNS_P2M, /*!< DMA transfer tyep:peripheral to memory */ + DMA_TRNS_P2P, /*!< DMA transfer tyep:peripheral to peripheral */ +} DMA_Trans_Dir_Type; + +/** + * @brief DMA burst size type definition + */ +typedef enum { + DMA_BURST_SIZE_1 = 0, /*!< DMA transfer width:8 bits */ + DMA_BURST_SIZE_4, /*!< DMA transfer width:16 bits */ + DMA_BURST_SIZE_8, /*!< DMA transfer width:32 bits */ + DMA_BURST_SIZE_16, /*!< DMA transfer width:64 bits */ +} DMA_Burst_Size_Type; + +/** + * @brief DMA destination peripheral type definition + */ +typedef enum { + DMA_REQ_UART0_RX = 0, /*!< DMA request peripheral:UART0 RX */ + DMA_REQ_UART0_TX, /*!< DMA request peripheral:UART0 TX */ + DMA_REQ_UART1_RX, /*!< DMA request peripheral:UART1 RX */ + DMA_REQ_UART1_TX, /*!< DMA request peripheral:UART1 TX */ + DMA_REQ_I2C_RX = 6, /*!< DMA request peripheral:I2C RX */ + DMA_REQ_I2C_TX, /*!< DMA request peripheral:I2C TX */ + DMA_REQ_SPI_RX = 10, /*!< DMA request peripheral:SPI RX */ + DMA_REQ_SPI_TX, /*!< DMA request peripheral:SPI TX */ + DMA_REQ_GPADC0 = 22, /*!< DMA request peripheral:GPADC0 */ + DMA_REQ_GPADC1, /*!< DMA request peripheral:GPADC1 */ + DMA_REQ_NONE = 0, /*!< DMA request peripheral:None */ +} DMA_Periph_Req_Type; + +/** + * @brief DMA channel type definition + */ +typedef enum { + DMA_CH0 = 0, /*!< DMA channel 0 */ + DMA_CH1, /*!< DMA channel 1 */ + DMA_CH2, /*!< DMA channel 2 */ + DMA_CH3, /*!< DMA channel 3 */ + DMA_CH_MAX, /*!< */ +} DMA_Chan_Type; + +/** + * @brief DMA interrupt type definition + */ +typedef enum { + DMA_INT_TCOMPLETED = 0, /*!< DMA completed interrupt */ + DMA_INT_ERR, /*!< DMA error interrupt */ + DMA_INT_ALL, /*!< All the interrupt */ +} DMA_INT_Type; + +/** + * @brief DMA LLI Structure PING-PONG + */ +typedef enum { + PING_INDEX = 0, /*!< PING INDEX */ + PONG_INDEX, /*!< PONG INDEX */ +} DMA_LLI_PP_Index_Type; + +/** + * @brief DMA Configuration Structure type definition + */ +typedef struct +{ + DMA_Endian_Type endian; /*!< DMA endian type */ + DMA_Sync_Logic_Type syncLogic; /*!< DMA synchronization logic */ +} DMA_Cfg_Type; + +/** + * @brief DMA channel Configuration Structure type definition + */ +typedef struct +{ + uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ + uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ + uint32_t transfLength; /*!< Transfer length, 0~4095, this is burst count */ + DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ + DMA_Chan_Type ch; /*!< Channel select 0-4 */ + DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */ + DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */ + DMA_Burst_Size_Type srcBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. + 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ + DMA_Burst_Size_Type dstBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. + 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ + uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */ + uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */ + DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ + DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ +} DMA_Channel_Cfg_Type; + +/** + * @brief DMA LLI control structure type definition + */ +typedef struct +{ + uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ + uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ + uint32_t nextLLI; /*!< Next LLI address */ + struct DMA_Control_Reg dmaCtrl; /*!< DMA transaction control */ +} DMA_LLI_Ctrl_Type; + +/** + * @brief DMA LLI configuration structure type definition + */ +typedef struct +{ + DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ + DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ + DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ +} DMA_LLI_Cfg_Type; + +/** + * @brief DMA LLI Ping-Pong Buf definition + */ +typedef struct +{ + uint8_t idleIndex; /*!< Index Idle lliListHeader */ + uint8_t dmaChan; /*!< DMA LLI Channel used */ + DMA_LLI_Ctrl_Type *lliListHeader[2]; /*!< Ping-Pong BUf List Header */ + void (*onTransCompleted)(DMA_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */ +} DMA_LLI_PP_Buf; + +/** + * @brief DMA LLI Ping-Pong Structure definition + */ +typedef struct +{ + uint8_t trans_index; /*!< Ping or Pong Trigger TC */ + uint8_t dmaChan; /*!< DMA LLI Channel used */ + struct DMA_Control_Reg dmaCtrlRegVal; /*!< DMA Basic Pararmeter */ + DMA_LLI_Cfg_Type *DMA_LLI_Cfg; /*!< LLI Config parameter */ + uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */ + uint32_t chache_buf_addr[2]; /*!< Ping-Pong structure chache */ + BL_Fun_Type is_single_mode; /*!< is Ping-pong running forever or single mode ,if is single mode ping-pong will run only once + after one start */ +} DMA_LLI_PP_Struct; + +/*@} end of group DMA_Public_Types */ + +/** @defgroup DMA_Public_Constants + * @{ + */ + +/** @defgroup DMA_ENDIAN_TYPE + * @{ + */ +#define IS_DMA_ENDIAN_TYPE(type) (((type) == DMA_LITTLE_ENDIAN) || \ + ((type) == DMA_BIG_ENDIAN)) + +/** @defgroup DMA_SYNC_LOGIC_TYPE + * @{ + */ +#define IS_DMA_SYNC_LOGIC_TYPE(type) (((type) == DMA_SYNC_LOGIC_ENABLE) || \ + ((type) == DMA_SYNC_LOGIC_DISABLE)) + +/** @defgroup DMA_TRANS_WIDTH_TYPE + * @{ + */ +#define IS_DMA_TRANS_WIDTH_TYPE(type) (((type) == DMA_TRNS_WIDTH_8BITS) || \ + ((type) == DMA_TRNS_WIDTH_16BITS) || \ + ((type) == DMA_TRNS_WIDTH_32BITS)) + +/** @defgroup DMA_TRANS_DIR_TYPE + * @{ + */ +#define IS_DMA_TRANS_DIR_TYPE(type) (((type) == DMA_TRNS_M2M) || \ + ((type) == DMA_TRNS_M2P) || \ + ((type) == DMA_TRNS_P2M) || \ + ((type) == DMA_TRNS_P2P)) + +/** @defgroup DMA_BURST_SIZE_TYPE + * @{ + */ +#define IS_DMA_BURST_SIZE_TYPE(type) (((type) == DMA_BURST_SIZE_1) || \ + ((type) == DMA_BURST_SIZE_4) || \ + ((type) == DMA_BURST_SIZE_8) || \ + ((type) == DMA_BURST_SIZE_16)) + +/** @defgroup DMA_PERIPH_REQ_TYPE + * @{ + */ +#define IS_DMA_PERIPH_REQ_TYPE(type) (((type) == DMA_REQ_UART0_RX) || \ + ((type) == DMA_REQ_UART0_TX) || \ + ((type) == DMA_REQ_UART1_RX) || \ + ((type) == DMA_REQ_UART1_TX) || \ + ((type) == DMA_REQ_I2C_RX) || \ + ((type) == DMA_REQ_I2C_TX) || \ + ((type) == DMA_REQ_SPI_RX) || \ + ((type) == DMA_REQ_SPI_TX) || \ + ((type) == DMA_REQ_GPADC0) || \ + ((type) == DMA_REQ_GPADC1) || \ + ((type) == DMA_REQ_NONE)) + +/** @defgroup DMA_CHAN_TYPE + * @{ + */ +#define IS_DMA_CHAN_TYPE(type) (((type) == DMA_CH0) || \ + ((type) == DMA_CH1) || \ + ((type) == DMA_CH2) || \ + ((type) == DMA_CH3) || \ + ((type) == DMA_CH_MAX)) + +/** @defgroup DMA_INT_TYPE + * @{ + */ +#define IS_DMA_INT_TYPE(type) (((type) == DMA_INT_TCOMPLETED) || \ + ((type) == DMA_INT_ERR) || \ + ((type) == DMA_INT_ALL)) + +/** @defgroup DMA_LLI_PP_INDEX_TYPE + * @{ + */ +#define IS_DMA_LLI_PP_INDEX_TYPE(type) (((type) == PING_INDEX) || \ + ((type) == PONG_INDEX)) + +/*@} end of group DMA_Public_Constants */ + +/** @defgroup DMA_Public_Macros + * @{ + */ +#define DMA_PINC_ENABLE 1 +#define DMA_PINC_DISABLE 0 +#define DMA_MINC_ENABLE 1 +#define DMA_MINC_DISABLE 0 + +/*@} end of group DMA_Public_Macros */ + +/** @defgroup DMA_Public_Functions + * @{ + */ + +/** + * @brief DMA Functions + */ +void DMA_Enable(void); +void DMA_Disable(void); +void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg); +void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len); +void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len); +uint32_t DMA_Channel_TranferSize(uint8_t ch); +BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch); +void DMA_Channel_Enable(uint8_t ch); +void DMA_Channel_Disable(uint8_t ch); +void DMA_LLI_Init(uint8_t ch, DMA_LLI_Cfg_Type *lliCfg); +void DMA_LLI_Update(uint8_t ch, uint32_t LLI); +void DMA_IntMask(uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct); +DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf); +void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList); +void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf); +void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun); +void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf); +void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct); +void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct); +BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, + uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len); + +/*@} end of group DMA_Public_Functions */ + +/*@} end of group DMA */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_DMA_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_ef_ctrl.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_ef_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..d1481498385813530d9c78e1d5547ae17bbfe3cb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_ef_ctrl.h @@ -0,0 +1,351 @@ +/** + ****************************************************************************** + * @file bl602_ef_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_EF_CTRL_H__ +#define __BL602_EF_CTRL_H__ + +#include "ef_ctrl_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup EF_CTRL + * @{ + */ + +/** @defgroup EF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Efuse Ctrl key slot type definition + */ +typedef enum { + EF_CTRL_KEY_SLOT0, /*!< key slot 0 */ + EF_CTRL_KEY_SLOT1, /*!< key slot 1 */ + EF_CTRL_KEY_SLOT2, /*!< key slot 2 */ + EF_CTRL_KEY_SLOT3, /*!< key slot 3 */ + EF_CTRL_KEY_SLOT4, /*!< key slot 4 */ + EF_CTRL_KEY_SLOT5, /*!< key slot 5 */ + EF_CTRL_KEY_MAX, /*!< */ +} EF_Ctrl_Key_Type; + +/** + * @brief Efuse Ctrl sign type definition + */ +typedef enum { + EF_CTRL_SIGN_NONE, /*!< no sign */ + EF_CTRL_SIGN_RSA, /*!< use RSA to sign */ + EF_CTRL_SIGN_ECC, /*!< use ECC to sign */ +} EF_Ctrl_Sign_Type; + +/** + * @brief Efuse Ctrl flash AES type definition + */ +typedef enum { + EF_CTRL_SF_AES_NONE, /*!< No AES */ + EF_CTRL_SF_AES_128, /*!< AES 128 */ + EF_CTRL_SF_AES_192, /*!< AES 192 */ + EF_CTRL_SF_AES_256, /*!< AES 256 */ +} EF_Ctrl_SF_AES_Type; + +/** + * @brief Efuse Ctrl Dbg type definition + */ +typedef enum { + EF_CTRL_DBG_OPEN = 0, /*!< Open debug */ + EF_CTRL_DBG_PASSWORD, /*!< Open debug with password */ + EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */ +} EF_Ctrl_Dbg_Mode_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_EF_CLK, /*!< Select efuse clock */ + EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */ +} EF_Ctrl_CLK_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_PARA_DFT, /*!< Select default cyc parameter */ + EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */ +} EF_Ctrl_CYC_PARA_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_OP_MODE_AUTO, /*!< Select efuse program auto mode */ + EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */ +} EF_Ctrl_OP_MODE_Type; + +/** + * @brief Efuse Ctrl secure configuration structure type definition + */ +typedef struct +{ + EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */ + uint8_t ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */ + uint8_t ef_sboot_en; /*!< Secure boot enable config value */ + uint8_t ef_no_hd_boot_en; /*!< No header boot enable */ +} EF_Ctrl_Sec_Param_Type; + +/** + * @brief Efuse analog RC32M trim type definition + */ +typedef struct +{ + uint32_t trimRc32mCodeFrExt : 8; /*!< Efuse analog trim:trim_rc32m_code_fr_ext */ + uint32_t trimRc32mCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */ + uint32_t trimRc32mExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en */ + uint32_t reserved : 22; /*!< Efuse analog trim:reserved */ +} Efuse_Ana_RC32M_Trim_Type; + +/** + * @brief Efuse analog RC32K trim type definition + */ +typedef struct +{ + uint32_t trimRc32kCodeFrExt : 10; /*!< Efuse analog trim:trim_rc32k_code_fr_ext */ + uint32_t trimRc32kCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */ + uint32_t trimRc32kExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32k_ext_code_en */ + uint32_t reserved : 20; /*!< Efuse analog trim:reserved */ +} Efuse_Ana_RC32K_Trim_Type; + +/** + * @brief Efuse analog TSEN trim type definition + */ +typedef struct +{ + uint32_t tsenRefcodeCorner : 12; /*!< TSEN refcode */ + uint32_t tsenRefcodeCornerParity : 1; /*!< TSEN refcode parity */ + uint32_t tsenRefcodeCornerEn : 1; /*!< TSEN refcode enable */ + uint32_t tsenRefcodeCornerVersion : 1; /*!< TSEN refcode version */ + uint32_t reserved : 17; /*!< TSEN analog trim:reserved */ +} Efuse_TSEN_Refcode_Corner_Type; + +/** + * @brief Efuse analog ADC Gain trim type definition + */ +typedef struct +{ + uint32_t adcGainCoeff : 12; /*!< ADC gain coeff */ + uint32_t adcGainCoeffParity : 1; /*!< ADC gain coeff parity */ + uint32_t adcGainCoeffEn : 1; /*!< ADC gain coeff enable */ + uint32_t reserved : 18; /*!< ADC gain coeff:reserved */ +} Efuse_ADC_Gain_Coeff_Type; + +/** + * @brief Efuse analog device info type definition + */ +typedef struct +{ + uint32_t rsvd : 22; /*!< Reserved */ + uint32_t customerID : 2; /*!< Efuse customer ID information */ + uint32_t rsvd_info : 3; /*!< Efuse device info extension: 1:BL602C, 2:BL602L, 3:BL602E */ + uint32_t memoryInfo : 2; /*!< Efuse memory info 0:no memory, 1:1MB flash, 2:2MB flash */ + uint32_t coreInfo : 1; /*!< Efuse reserved */ + uint32_t mcuInfo : 1; /*!< Efuse mcu info 0:wifi, 1:mcu */ + uint32_t pinInfo : 1; /*!< Efuse pin info 0:QFN32, 1:QFN40 */ +} Efuse_Device_Info_Type; + +/** + * @brief Efuse Capcode type definition + */ +typedef struct +{ + uint32_t capCode : 6; /*!< Cap code value */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 24; /*!< Reserved */ +} Efuse_Capcode_Info_Type; + +/** + * @brief Efuse Ldo11 Vout Sel Trim definition + */ +typedef struct { + uint32_t sel_value : 4; /*!< value trim */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 26; /*!< Reserved */ +} Efuse_Ldo11VoutSelTrim_Info_Type; + +/** + * @brief Efuse Tx Power definition + */ +typedef struct { + uint32_t txpower : 5; /*!< txpower value */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 25; /*!< Reserved */ +} Efuse_TxPower_Info_Type; + +/*@} end of group EF_CTRL_Public_Types */ + +/** @defgroup EF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup EF_CTRL_KEY_TYPE + * @{ + */ +#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \ + ((type) == EF_CTRL_KEY_SLOT1) || \ + ((type) == EF_CTRL_KEY_SLOT2) || \ + ((type) == EF_CTRL_KEY_SLOT3) || \ + ((type) == EF_CTRL_KEY_SLOT4) || \ + ((type) == EF_CTRL_KEY_SLOT5) || \ + ((type) == EF_CTRL_KEY_MAX)) + +/** @defgroup EF_CTRL_SIGN_TYPE + * @{ + */ +#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \ + ((type) == EF_CTRL_SIGN_RSA) || \ + ((type) == EF_CTRL_SIGN_ECC)) + +/** @defgroup EF_CTRL_SF_AES_TYPE + * @{ + */ +#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \ + ((type) == EF_CTRL_SF_AES_128) || \ + ((type) == EF_CTRL_SF_AES_192) || \ + ((type) == EF_CTRL_SF_AES_256)) + +/** @defgroup EF_CTRL_DBG_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) || \ + ((type) == EF_CTRL_DBG_PASSWORD) || \ + ((type) == EF_CTRL_DBG_CLOSE)) + +/** @defgroup EF_CTRL_CLK_TYPE + * @{ + */ +#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \ + ((type) == EF_CTRL_SAHB_CLK)) + +/** @defgroup EF_CTRL_CYC_PARA_TYPE + * @{ + */ +#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || \ + ((type) == EF_CTRL_PARA_MANUAL)) + +/** @defgroup EF_CTRL_OP_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || \ + ((type) == EF_CTRL_OP_MODE_MANUAL)) + +/*@} end of group EF_CTRL_Public_Constants */ + +/** @defgroup EF_CTRL_Public_Macros + * @{ + */ +#define EF_CTRL_EFUSE_R0_SIZE 128 + +/*@} end of group EF_CTRL_Public_Macros */ + +/** @defgroup EF_CTRL_Public_Functions + * @{ + */ +void EF_Ctrl_Load_Efuse_R0(void); +void EF_Ctrl_Program_Efuse_0(void); +BL_Sts_Type EF_Ctrl_Busy(void); +BL_Sts_Type EF_Ctrl_AutoLoad_Done(void); +void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program); +void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh); +void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program); +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg); +void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program); +void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]); +void EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled, uint8_t *npDisabled, uint8_t *npCpuType); +uint8_t EF_Ctrl_Get_Trim_Enable(void); +uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len); +void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program); +void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim); +void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim); +void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim); +void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim); +void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim); +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program); +void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage); +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program); +void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]); +BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]); +void EF_Ctrl_Writelock_MAC_Address(uint8_t program); +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]); +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo); +void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program); +void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len); +void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program); +void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program); +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Clear(uint32_t index, uint32_t len); +void EF_Ctrl_Crc_Enable(void); +BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void); +void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue); +BL_Err_Type EF_Ctrl_Crc_Result(void); +void EF_Ctrl_Sw_AHB_Clk_0(void); +uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload); +uint8_t EF_Ctrl_Is_CapCode_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program); +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload); +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program); +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload); +void EF_Ctrl_Write_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_R0(uint32_t index, uint32_t *data, uint32_t len); + +/*@} end of group EF_CTRL_Public_Functions */ + +/*@} end of group EF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_EF_CTRL_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_glb.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_glb.h new file mode 100644 index 0000000000000000000000000000000000000000..958b86f18efff5104b408b9ea5d0eb4b43e23aa4 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_glb.h @@ -0,0 +1,667 @@ +/** + ****************************************************************************** + * @file bl602_glb.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_GLB_H__ +#define __BL602_GLB_H__ + +#include "glb_reg.h" +#include "pds_reg.h" +#include "bl602_gpio.h" +#include "bl602_l1c.h" +#include "bl602_hbn.h" +#include "bl602_sf_ctrl.h" +#include "bl602_sf_cfg.h" +#include "bl602_aon.h" +#include "bl602_ef_ctrl.h" +#include "bl602_pds.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Public_Types + * @{ + */ + +/** + * @brief GLB root clock type definition + */ +typedef enum { + GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */ + GLB_ROOT_CLK_XTAL, /*!< root clock select XTAL */ + GLB_ROOT_CLK_PLL, /*!< root clock select PLL others */ +} GLB_ROOT_CLK_Type; + +/** + * @brief GLB system clock type definition + */ +typedef enum { + GLB_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ + GLB_SYS_CLK_XTAL, /*!< use XTAL as system clock */ + GLB_SYS_CLK_PLL48M, /*!< use PLL output 48M as system clock */ + GLB_SYS_CLK_PLL120M, /*!< use PLL output 120M as system clock */ + GLB_SYS_CLK_PLL160M, /*!< use PLL output 160M as system clock */ + GLB_SYS_CLK_PLL192M, /*!< use PLL output 192M as system clock */ +} GLB_SYS_CLK_Type; + +/** + * @brief GLB DMA clock ID type definition + */ +typedef enum { + GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */ + GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */ + GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */ + GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */ +} GLB_DMA_CLK_ID_Type; + +/** + * @brief GLB clock source type definition + */ +typedef enum { + GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */ +} GLB_IR_CLK_SRC_Type; + +/** + * @brief GLB flash clock type definition + */ +typedef enum { + GLB_SFLASH_CLK_120M, /*!< Select 120M as flash clock */ + GLB_SFLASH_CLK_XTAL, /*!< Select XTAL as flash clock */ + GLB_SFLASH_CLK_48M, /*!< Select 48M as flash clock */ + GLB_SFLASH_CLK_80M, /*!< Select 80M as flash clock */ + GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */ + GLB_SFLASH_CLK_96M, /*!< Select 96M as flash clock */ +} GLB_SFLASH_CLK_Type; + +/** + * @brief GLB SPI pad action type definition + */ +typedef enum { + GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */ + GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */ +} GLB_SPI_PAD_ACT_AS_Type; + +/** + * @brief GLB PKA clock type definition + */ +typedef enum { + GLB_PKA_CLK_HCLK, /*!< Select HCLK as PKA clock */ + GLB_PKA_CLK_PLL120M, /*!< Select PLL 120M as PKA clock */ +} GLB_PKA_CLK_Type; + +/** + * @brief BMX arb mode type definition + */ +typedef enum { + BMX_ARB_FIX, /*!< 0->fix */ + BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + BMX_ARB_RANDOM, /*!< 3->random */ +} BMX_ARB_Type; + +/** + * @brief BMX configuration structure type definition + */ +typedef struct +{ + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +} BMX_Cfg_Type; + +/** + * @brief BMX bus err type definition + */ +typedef enum { + BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +} BMX_BUS_ERR_Type; + +/** + * @brief BMX bus err interrupt type definition + */ +typedef enum { + BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */ + BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */ +} BMX_ERR_INT_Type; + +/** + * @brief BMX time out interrupt type definition + */ +typedef enum { + BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */ + BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */ +} BMX_TO_INT_Type; + +/** + * @brief GLB EM type definition + */ +typedef enum { + GLB_EM_0KB = 0x0, /*!< 0x0 --> 0KB */ + GLB_EM_8KB = 0x3, /*!< 0x3 --> 8KB */ + GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */ +} GLB_EM_Type; + +/** + * @brief GLB RTC clock type definition + */ +typedef enum { + GLB_MTIMER_CLK_BCLK, /*!< BUS clock */ + GLB_MTIMER_CLK_32K, /*!< 32KHz */ +} GLB_MTIMER_CLK_Type; + +/** + * @brief GLB ADC clock type definition + */ +typedef enum { + GLB_ADC_CLK_96M, /*!< use 96M as ADC clock */ + GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */ +} GLB_ADC_CLK_Type; + +/** + * @brief GLB DAC clock type definition + */ +typedef enum { + GLB_DAC_CLK_32M, /*!< use 32M as DAC clock */ + GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */ +} GLB_DAC_CLK_Type; + +/** + * @brief GLB DIG clock source select type definition + */ +typedef enum { + GLB_DIG_CLK_PLL_32M, /*!< select PLL 32M as DIG clock source */ + GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */ +} GLB_DIG_CLK_Type; + +/** + * @brief GLB 512K clock out select type definition + */ +typedef enum { + GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */ + GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */ + GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */ +} GLB_512K_CLK_OUT_Type; + +/** + * @brief GLB BT bandwidth type definition + */ +typedef enum { + GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */ + GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */ +} GLB_BT_BANDWIDTH_Type; + +/** + * @brief GLB UART signal type definition + */ +typedef enum { + GLB_UART_SIG_0, /*!< UART signal 0 */ + GLB_UART_SIG_1, /*!< UART signal 1 */ + GLB_UART_SIG_2, /*!< UART signal 2 */ + GLB_UART_SIG_3, /*!< UART signal 3 */ + GLB_UART_SIG_4, /*!< UART signal 4 */ + GLB_UART_SIG_5, /*!< UART signal 5 */ + GLB_UART_SIG_6, /*!< UART signal 6 */ + GLB_UART_SIG_7, /*!< UART signal 7 */ +} GLB_UART_SIG_Type; + +/** + * @brief GLB UART signal function type definition + */ +typedef enum { + GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */ + GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */ + GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */ + GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */ + GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */ + GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */ + GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */ + GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */ +} GLB_UART_SIG_FUN_Type; + +/** + * @brief GLB GPIO real mode type definition + */ +typedef enum { + GLB_GPIO_REAL_MODE_REG, /*!< GPIO real function is reg_gpio_x_func_sel */ + GLB_GPIO_REAL_MODE_SDIO = 0x1, /*!< GPIO real function is SDIO */ + GLB_GPIO_REAL_MODE_RF = 0xC, /*!< GPIO real function is RF */ + GLB_GPIO_REAL_MODE_JTAG = 0xE, /*!< GPIO real function is JTAG */ + GLB_GPIO_REAL_MODE_CCI = 0xF, /*!< GPIO real function is CCI */ +} GLB_GPIO_REAL_MODE_Type; + +/** + * @brief GLB GPIO interrupt trigger mode type definition + */ +typedef enum { + GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */ + GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */ + GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */ + GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */ +} GLB_GPIO_INT_TRIG_Type; + +/** + * @brief GLB GPIO interrupt control mode type definition + */ +typedef enum { + GLB_GPIO_INT_CONTROL_SYNC, /*!< GPIO interrupt sync mode */ + GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */ +} GLB_GPIO_INT_CONTROL_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + GLB_PLL_XTAL_NONE, /*!< XTAL is none */ + GLB_PLL_XTAL_24M, /*!< XTAL is 24M */ + GLB_PLL_XTAL_32M, /*!< XTAL is 32M */ + GLB_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */ + GLB_PLL_XTAL_40M, /*!< XTAL is 40M */ + GLB_PLL_XTAL_26M, /*!< XTAL is 26M */ + GLB_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ +} GLB_PLL_XTAL_Type; + +/** + * @brief PLL output clock type definition + */ +typedef enum { + GLB_PLL_CLK_480M, /*!< PLL output clock:480M */ + GLB_PLL_CLK_240M, /*!< PLL output clock:240M */ + GLB_PLL_CLK_192M, /*!< PLL output clock:192M */ + GLB_PLL_CLK_160M, /*!< PLL output clock:160M */ + GLB_PLL_CLK_120M, /*!< PLL output clock:120M */ + GLB_PLL_CLK_96M, /*!< PLL output clock:96M */ + GLB_PLL_CLK_80M, /*!< PLL output clock:80M */ + GLB_PLL_CLK_48M, /*!< PLL output clock:48M */ + GLB_PLL_CLK_32M, /*!< PLL output clock:32M */ +} GLB_PLL_CLK_Type; + +/** + * @brief PLL configuration structure type definition + */ +typedef struct +{ + uint8_t clkpllIcp1u; /*!< int mode:0, frac mode:1 */ + uint8_t clkpllIcp5u; /*!< int mode:2, frac mode:0 */ + uint8_t clkpllIntFracSw; /*!< 0:int mode, 1:frac mode */ + uint8_t clkpllC3; /*!< int:3, frac:2 */ + uint8_t clkpllCz; /*!< int:1, frac:2 */ + uint8_t clkpllRz; /*!< int:1, frac:5 */ + uint8_t clkpllR4; /*!< int:2, frac:2 */ + uint8_t clkpllR4Short; /*!< int:1, frac:0 */ + uint8_t clkpllRefdivRatio; /*!< ref divider ratio */ + uint8_t clkpllPostdiv; /*!< >=8 and should be even number */ + uint32_t clkpllSdmin; /*!< sdmin */ + uint8_t clkpllSelFbClk; /*!< 0:mod1, 1:mod2, 2:mod3 */ + uint8_t clkpllSelSampleClk; /*!< 0:[16,63)mod3, 1:[32:127)mod4, 2:[64,255)mod5 */ +} GLB_PLL_Cfg_Type; + +/*@} end of group GLB_Public_Types */ + +/** @defgroup GLB_Public_Constants + * @{ + */ + +/** @defgroup GLB_ROOT_CLK_TYPE + * @{ + */ +#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \ + ((type) == GLB_ROOT_CLK_XTAL) || \ + ((type) == GLB_ROOT_CLK_PLL)) + +/** @defgroup GLB_SYS_CLK_TYPE + * @{ + */ +#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) || \ + ((type) == GLB_SYS_CLK_XTAL) || \ + ((type) == GLB_SYS_CLK_PLL48M) || \ + ((type) == GLB_SYS_CLK_PLL120M) || \ + ((type) == GLB_SYS_CLK_PLL160M) || \ + ((type) == GLB_SYS_CLK_PLL192M)) + +/** @defgroup GLB_DMA_CLK_ID_TYPE + * @{ + */ +#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \ + ((type) == GLB_DMA_CLK_DMA0_CH1) || \ + ((type) == GLB_DMA_CLK_DMA0_CH2) || \ + ((type) == GLB_DMA_CLK_DMA0_CH3)) + +/** @defgroup GLB_IR_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK)) + +/** @defgroup GLB_SFLASH_CLK_TYPE + * @{ + */ +#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_120M) || \ + ((type) == GLB_SFLASH_CLK_XTAL) || \ + ((type) == GLB_SFLASH_CLK_48M) || \ + ((type) == GLB_SFLASH_CLK_80M) || \ + ((type) == GLB_SFLASH_CLK_BCLK) || \ + ((type) == GLB_SFLASH_CLK_96M)) + +/** @defgroup GLB_SPI_PAD_ACT_AS_TYPE + * @{ + */ +#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \ + ((type) == GLB_SPI_PAD_ACT_AS_MASTER)) + +/** @defgroup GLB_PKA_CLK_TYPE + * @{ + */ +#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \ + ((type) == GLB_PKA_CLK_PLL120M)) + +/** @defgroup BMX_ARB_TYPE + * @{ + */ +#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) || \ + ((type) == BMX_ARB_ROUND_ROBIN) || \ + ((type) == BMX_ARB_RANDOM)) + +/** @defgroup BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup BMX_ERR_INT_TYPE + * @{ + */ +#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \ + ((type) == BMX_ERR_INT_ALL)) + +/** @defgroup BMX_TO_INT_TYPE + * @{ + */ +#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \ + ((type) == BMX_TO_INT_ALL)) + +/** @defgroup GLB_EM_TYPE + * @{ + */ +#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \ + ((type) == GLB_EM_8KB) || \ + ((type) == GLB_EM_16KB)) + +/** @defgroup GLB_MTIMER_CLK_TYPE + * @{ + */ +#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \ + ((type) == GLB_MTIMER_CLK_32K)) + +/** @defgroup GLB_ADC_CLK_TYPE + * @{ + */ +#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_96M) || \ + ((type) == GLB_ADC_CLK_XCLK)) + +/** @defgroup GLB_DAC_CLK_TYPE + * @{ + */ +#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \ + ((type) == GLB_DAC_CLK_XCLK)) + +/** @defgroup GLB_DIG_CLK_TYPE + * @{ + */ +#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \ + ((type) == GLB_DIG_CLK_XCLK)) + +/** @defgroup GLB_512K_CLK_OUT_TYPE + * @{ + */ +#define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \ + ((type) == GLB_512K_CLK_OUT_256K) || \ + ((type) == GLB_512K_CLK_OUT_128K)) + +/** @defgroup GLB_BT_BANDWIDTH_TYPE + * @{ + */ +#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \ + ((type) == GLB_BT_BANDWIDTH_2M)) + +/** @defgroup GLB_UART_SIG_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \ + ((type) == GLB_UART_SIG_1) || \ + ((type) == GLB_UART_SIG_2) || \ + ((type) == GLB_UART_SIG_3) || \ + ((type) == GLB_UART_SIG_4) || \ + ((type) == GLB_UART_SIG_5) || \ + ((type) == GLB_UART_SIG_6) || \ + ((type) == GLB_UART_SIG_7)) + +/** @defgroup GLB_UART_SIG_FUN_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RXD)) + +/** @defgroup GLB_GPIO_REAL_MODE_TYPE + * @{ + */ +#define IS_GLB_GPIO_REAL_MODE_TYPE(type) (((type) == GLB_GPIO_REAL_MODE_REG) || \ + ((type) == GLB_GPIO_REAL_MODE_SDIO) || \ + ((type) == GLB_GPIO_REAL_MODE_RF) || \ + ((type) == GLB_GPIO_REAL_MODE_JTAG) || \ + ((type) == GLB_GPIO_REAL_MODE_CCI)) + +/** @defgroup GLB_GPIO_INT_TRIG_TYPE + * @{ + */ +#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \ + ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \ + ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \ + ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL)) + +/** @defgroup GLB_GPIO_INT_CONTROL_TYPE + * @{ + */ +#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \ + ((type) == GLB_GPIO_INT_CONTROL_ASYNC)) + +/** @defgroup GLB_PLL_XTAL_TYPE + * @{ + */ +#define IS_GLB_PLL_XTAL_TYPE(type) (((type) == GLB_PLL_XTAL_NONE) || \ + ((type) == GLB_PLL_XTAL_24M) || \ + ((type) == GLB_PLL_XTAL_32M) || \ + ((type) == GLB_PLL_XTAL_38P4M) || \ + ((type) == GLB_PLL_XTAL_40M) || \ + ((type) == GLB_PLL_XTAL_26M) || \ + ((type) == GLB_PLL_XTAL_RC32M)) + +/** @defgroup GLB_PLL_CLK_TYPE + * @{ + */ +#define IS_GLB_PLL_CLK_TYPE(type) (((type) == GLB_PLL_CLK_480M) || \ + ((type) == GLB_PLL_CLK_240M) || \ + ((type) == GLB_PLL_CLK_192M) || \ + ((type) == GLB_PLL_CLK_160M) || \ + ((type) == GLB_PLL_CLK_120M) || \ + ((type) == GLB_PLL_CLK_96M) || \ + ((type) == GLB_PLL_CLK_80M) || \ + ((type) == GLB_PLL_CLK_48M) || \ + ((type) == GLB_PLL_CLK_32M)) + +/*@} end of group GLB_Public_Constants */ + +/** @defgroup GLB_Public_Macros + * @{ + */ +#define UART_SIG_SWAP_GPIO0_GPIO7 0x01 /* GPIO0-7 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_GPIO8_GPIO15 0x02 /* GPIO8-15 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_NONE 0x00 /* GPIO0-22 uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */ +#define JTAG_SIG_SWAP_GPIO0_GPIO3 0x01 /* GPIO0-3 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO4_GPIO7 0x02 /* GPIO4-7 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO8_GPIO11 0x04 /* GPIO8-11 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */ + +/*@} end of group GLB_Public_Macros */ + +/** @defgroup GLB_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void); +void BMX_TO_IRQHandler(void); +void GPIO_INT0_IRQHandler(void); +#endif +/*----------*/ +GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void); +BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv); +uint8_t GLB_Get_BCLK_Div(void); +uint8_t GLB_Get_HCLK_Div(void); +BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType); +BL_Err_Type GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq); +BL_Err_Type System_Core_Clock_Update_From_RC32M(void); +/*----------*/ +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable); +BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv); +BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv); +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk); +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div); +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel); +BL_Err_Type GLB_SW_System_Reset(void); +BL_Err_Type GLB_SW_CPU_Reset(void); +BL_Err_Type GLB_SW_POR_Reset(void); +BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1); +BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1); +/*----------*/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg); +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void); +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void); +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType); +uint32_t GLB_BMX_Get_Err_Addr(void); +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type GLB_Set_OCRAM_Idle(void); +BL_Err_Type GLB_Set_SRAM_RET(uint32_t value); +uint32_t GLB_Get_SRAM_RET(void); +BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value); +uint32_t GLB_Get_SRAM_SLP(void); +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value); +uint32_t GLB_Get_SRAM_PARM(void); +/*----------*/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType); +/*----------*/ +BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState); +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod); +BL_Err_Type GLB_Select_Internal_Flash(void); +BL_Err_Type GLB_Select_External_Flash(void); +BL_Err_Type GLB_Deswap_Flash_Pin(void); +BL_Err_Type GLB_Swap_Flash_Pin(void); +/*----------*/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div); +/*----------*/ +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Platform_Wakeup_Enable(void); +BL_Err_Type GLB_Platform_Wakeup_Disable(void); +/*----------*/ +BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel); +BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div); +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, + uint8_t pti, uint8_t channel); +/*----------*/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun); +/*----------*/ +BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio); +BL_Err_Type GLB_IR_LED_Driver_Enable(void); +BL_Err_Type GLB_IR_LED_Driver_Disable(void); +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias); +/*----------*/ +BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg); +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt); +BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin); +uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin); +GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val); +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); +BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear); +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, + GLB_GPIO_INT_TRIG_Type intTrgMod); +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void); +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_GLB_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_gpio.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..5b96dab75c434c9204466877636c84ef34d21735 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_gpio.h @@ -0,0 +1,444 @@ +/** + + ****************************************************************************** + + * @file bl602_gpio.h + + * @version V1.2 + + * @date 2019-12-14 + + * @brief This file is the description of.IP register + + ****************************************************************************** + + * @attention + + * + + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ + * + + * Redistribution and use in source and binary forms, with or without modification, + + * are permitted provided that the following conditions are met: + + * 1. Redistributions of source code must retain the above copyright notice, + + * this list of conditions and the following disclaimer. + + * 2. Redistributions in binary form must reproduce the above copyright notice, + + * this list of conditions and the following disclaimer in the documentation + + * and/or other materials provided with the distribution. + + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + + * may be used to endorse or promote products derived from this software + + * without specific prior written permission. + + * + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + * + + ****************************************************************************** + + */ + +#ifndef __BL602_GPIO_H__ +#define __BL602_GPIO_H__ + +typedef enum { + GLB_GPIO_PIN_0 = 0, + GLB_GPIO_PIN_1, + GLB_GPIO_PIN_2, + GLB_GPIO_PIN_3, + GLB_GPIO_PIN_4, + GLB_GPIO_PIN_5, + GLB_GPIO_PIN_6, + GLB_GPIO_PIN_7, + GLB_GPIO_PIN_8, + GLB_GPIO_PIN_9, + GLB_GPIO_PIN_10, + GLB_GPIO_PIN_11, + GLB_GPIO_PIN_12, + GLB_GPIO_PIN_13, + GLB_GPIO_PIN_14, + GLB_GPIO_PIN_15, + GLB_GPIO_PIN_16, + GLB_GPIO_PIN_17, + GLB_GPIO_PIN_18, + GLB_GPIO_PIN_19, + GLB_GPIO_PIN_20, + GLB_GPIO_PIN_21, + GLB_GPIO_PIN_22, + GLB_GPIO_PIN_MAX, +} GLB_GPIO_Type; + +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_AF ((uint32_t)0x00000002U) /*!< Alternate function */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function */ +#define GPIO_PULL_UP ((uint32_t)0x00000000U) /*!< GPIO pull up */ +#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) /*!< GPIO pull down */ +#define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */ + +typedef enum { + GPIO_FUN_SDIO = 1, + GPIO_FUN_FLASH = 2, + GPIO_FUN_SPI = 4, + GPIO_FUN_I2C = 6, + GPIO_FUN_UART = 7, + GPIO_FUN_PWM = 8, + GPIO_FUN_EXT_PA = 9, + GPIO_FUN_ANALOG = 10, + GPIO_FUN_SWGPIO = 11, + GPIO_FUN_GPIO = 11, + GPIO_FUN_JTAG = 14, + GPIO_FUN_UART0_RTS = 0x70, + GPIO_FUN_UART0_CTS = 0x71, + GPIO_FUN_UART0_TX = 0x72, + GPIO_FUN_UART0_RX = 0x73, + GPIO_FUN_UART1_RTS = 0x74, + GPIO_FUN_UART1_CTS = 0x75, + GPIO_FUN_UART1_TX = 0x76, + GPIO_FUN_UART1_RX = 0x77, + GPIO_FUN_GPIO_OUTPUT = 0x80, + GPIO_FUN_GPIO_INPUT = 0x81, + GPIO_FUN_UNUSED = 255, +} GLB_GPIO_FUNC_Type; + +typedef struct +{ + uint8_t gpioPin; + uint8_t gpioFun; + uint8_t gpioMode; + uint8_t pullType; + uint8_t drive; + uint8_t smtCtrl; +} GLB_GPIO_Cfg_Type; + +/* GPIO0 function definition */ +#define GPIO0_FUN_SDIO_CLK 1 +#define GPIO0_FUN_SF_D1 2 +#define GPIO0_FUN_UNUSED3 3 +#define GPIO0_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO0_FUN_UNUSED5 5 +#define GPIO0_FUN_I2C_SCL 6 +#define GPIO0_FUN_UART_SIG0 7 +#define GPIO0_FUN_PWM_CH0 8 +#define GPIO0_FUN_FEM_GPIO_0 9 +#define GPIO0_FUN_ATEST_IN 10 +#define GPIO0_FUN_SWGPIO_0 11 +#define GPIO0_FUN_E21_TMS 14 +/* GPIO1 function definition */ +#define GPIO1_FUN_SDIO_CMD 1 +#define GPIO1_FUN_SF_D2 2 +#define GPIO1_FUN_UNUSED3 3 +#define GPIO1_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO1_FUN_UNUSED5 5 +#define GPIO1_FUN_I2C_SDA 6 +#define GPIO1_FUN_UART_SIG1 7 +#define GPIO1_FUN_PWM_CH1 8 +#define GPIO1_FUN_FEM_GPIO_1 9 +#define GPIO1_FUN_ATEST_IP 10 +#define GPIO1_FUN_SWGPIO_1 11 +#define GPIO1_FUN_E21_TDI 14 +/* GPIO2 function definition */ +#define GPIO2_FUN_SDIO_DAT0 1 +#define GPIO2_FUN_SF_D3 2 +#define GPIO2_FUN_UNUSED3 3 +#define GPIO2_FUN_SPI_SS 4 +#define GPIO2_FUN_UNUSED5 5 +#define GPIO2_FUN_I2C_SCL 6 +#define GPIO2_FUN_UART_SIG2 7 +#define GPIO2_FUN_PWM_CH2 8 +#define GPIO2_FUN_FEM_GPIO_2 9 +#define GPIO2_FUN_ATEST_QN 10 +#define GPIO2_FUN_SWGPIO_2 11 +#define GPIO2_FUN_E21_TCK 14 +/* GPIO3 function definition */ +#define GPIO3_FUN_SDIO_DAT1 1 +#define GPIO3_FUN_UNUSED2 2 +#define GPIO3_FUN_UNUSED3 3 +#define GPIO3_FUN_SPI_SCLK 4 +#define GPIO3_FUN_UNUSED5 5 +#define GPIO3_FUN_I2C_SDA 6 +#define GPIO3_FUN_UART_SIG3 7 +#define GPIO3_FUN_PWM_CH3 8 +#define GPIO3_FUN_FEM_GPIO_3 9 +#define GPIO3_FUN_ATEST_QP 10 +#define GPIO3_FUN_SWGPIO_3 11 +#define GPIO3_FUN_E21_TDO 14 +/* GPIO4 function definition */ +#define GPIO4_FUN_SDIO_DAT2 1 +#define GPIO4_FUN_UNUSED2 2 +#define GPIO4_FUN_UNUSED3 3 +#define GPIO4_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO4_FUN_UNUSED5 5 +#define GPIO4_FUN_I2C_SCL 6 +#define GPIO4_FUN_UART_SIG4 7 +#define GPIO4_FUN_PWM_CH4 8 +#define GPIO4_FUN_FEM_GPIO_0 9 +#define GPIO4_FUN_GPIP_CH1 10 +#define GPIO4_FUN_SWGPIO_4 11 +#define GPIO4_FUN_E21_TMS 14 +/* GPIO5 function definition */ +#define GPIO5_FUN_SDIO_DAT3 1 +#define GPIO5_FUN_UNUSED2 2 +#define GPIO5_FUN_UNUSED3 3 +#define GPIO5_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO5_FUN_UNUSED5 5 +#define GPIO5_FUN_I2C_SDA 6 +#define GPIO5_FUN_UART_SIG5 7 +#define GPIO5_FUN_PWM_CH0 8 +#define GPIO5_FUN_FEM_GPIO_1 9 +#define GPIO5_FUN_GPIP_CH4 10 +#define GPIO5_FUN_SWGPIO_5 11 +#define GPIO5_FUN_E21_TDI 14 +/* GPIO6 function definition */ +#define GPIO6_FUN_UNUSED1 1 +#define GPIO6_FUN_UNUSED2 2 +#define GPIO6_FUN_UNUSED3 3 +#define GPIO6_FUN_SPI_SS 4 +#define GPIO6_FUN_UNUSED5 5 +#define GPIO6_FUN_I2C_SCL 6 +#define GPIO6_FUN_UART_SIG6 7 +#define GPIO6_FUN_PWM_CH1 8 +#define GPIO6_FUN_FEM_GPIO_2 9 +#define GPIO6_FUN_GPIP_CH5 10 +#define GPIO6_FUN_SWGPIO_6 11 +#define GPIO6_FUN_E21_TCK 14 +/* GPIO7 function definition */ +#define GPIO7_FUN_UNUSED1 1 +#define GPIO7_FUN_UNUSED2 2 +#define GPIO7_FUN_UNUSED3 3 +#define GPIO7_FUN_SPI_SCLK 4 +#define GPIO7_FUN_UNUSED5 5 +#define GPIO7_FUN_I2C_SDA 6 +#define GPIO7_FUN_UART_SIG7 7 +#define GPIO7_FUN_PWM_CH2 8 +#define GPIO7_FUN_FEM_GPIO_3 9 +#define GPIO7_FUN_UNUSED10 10 +#define GPIO7_FUN_SWGPIO_7 11 +#define GPIO7_FUN_E21_TDO 14 +/* GPIO8 function definition */ +#define GPIO8_FUN_UNUSED1 1 +#define GPIO8_FUN_UNUSED2 2 +#define GPIO8_FUN_UNUSED3 3 +#define GPIO8_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO8_FUN_UNUSED5 5 +#define GPIO8_FUN_I2C_SCL 6 +#define GPIO8_FUN_UART_SIG0 7 +#define GPIO8_FUN_PWM_CH3 8 +#define GPIO8_FUN_FEM_GPIO_0 9 +#define GPIO8_FUN_UNUSED10 10 +#define GPIO8_FUN_SWGPIO_8 11 +#define GPIO8_FUN_E21_TMS 14 +/* GPIO9 function definition */ +#define GPIO9_FUN_UNUSED1 1 +#define GPIO9_FUN_UNUSED2 2 +#define GPIO9_FUN_UNUSED3 3 +#define GPIO9_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO9_FUN_UNUSED5 5 +#define GPIO9_FUN_I2C_SDA 6 +#define GPIO9_FUN_UART_SIG1 7 +#define GPIO9_FUN_PWM_CH4 8 +#define GPIO9_FUN_FEM_GPIO_1 9 +#define GPIO9_FUN_GPIP_CH6_GPIP_CH7 10 +#define GPIO9_FUN_SWGPIO_9 11 +#define GPIO9_FUN_E21_TDI 14 +/* GPIO10 function definition */ +#define GPIO10_FUN_UNUSED1 1 +#define GPIO10_FUN_UNUSED2 2 +#define GPIO10_FUN_UNUSED3 3 +#define GPIO10_FUN_SPI_SS 4 +#define GPIO10_FUN_UNUSED5 5 +#define GPIO10_FUN_I2C_SCL 6 +#define GPIO10_FUN_UART_SIG2 7 +#define GPIO10_FUN_PWM_CH0 8 +#define GPIO10_FUN_FEM_GPIO_2 9 +#define GPIO10_FUN_MICBIAS_GPIP_CH8_GPIP_CH9 10 +#define GPIO10_FUN_SWGPIO_10 11 +#define GPIO10_FUN_E21_TCK 14 +/* GPIO11 function definition */ +#define GPIO11_FUN_UNUSED1 1 +#define GPIO11_FUN_UNUSED2 2 +#define GPIO11_FUN_UNUSED3 3 +#define GPIO11_FUN_SPI_SCLK 4 +#define GPIO11_FUN_UNUSED5 5 +#define GPIO11_FUN_I2C_SDA 6 +#define GPIO11_FUN_UART_SIG3 7 +#define GPIO11_FUN_PWM_CH1 8 +#define GPIO11_FUN_FEM_GPIO_3 9 +#define GPIO11_FUN_IRLED_OUT_GPIP_CH10 10 +#define GPIO11_FUN_SWGPIO_11 11 +#define GPIO11_FUN_E21_TDO 14 +/* GPIO12 function definition */ +#define GPIO12_FUN_UNUSED1 1 +#define GPIO12_FUN_UNUSED2 2 +#define GPIO12_FUN_UNUSED3 3 +#define GPIO12_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO12_FUN_UNUSED5 5 +#define GPIO12_FUN_I2C_SCL 6 +#define GPIO12_FUN_UART_SIG4 7 +#define GPIO12_FUN_PWM_CH2 8 +#define GPIO12_FUN_FEM_GPIO_0 9 +#define GPIO12_FUN_GPIP_CH0_GPADC_VREF_EXT 10 +#define GPIO12_FUN_SWGPIO_12 11 +#define GPIO12_FUN_E21_TMS 14 +/* GPIO13 function definition */ +#define GPIO13_FUN_UNUSED1 1 +#define GPIO13_FUN_UNUSED2 2 +#define GPIO13_FUN_UNUSED3 3 +#define GPIO13_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO13_FUN_UNUSED5 5 +#define GPIO13_FUN_I2C_SDA 6 +#define GPIO13_FUN_UART_SIG5 7 +#define GPIO13_FUN_PWM_CH3 8 +#define GPIO13_FUN_FEM_GPIO_1 9 +#define GPIO13_FUN_GPIP_CH3 10 +#define GPIO13_FUN_SWGPIO_13 11 +#define GPIO13_FUN_E21_TDI 14 +/* GPIO14 function definition */ +#define GPIO14_FUN_UNUSED1 1 +#define GPIO14_FUN_UNUSED2 2 +#define GPIO14_FUN_UNUSED3 3 +#define GPIO14_FUN_SPI_SS 4 +#define GPIO14_FUN_UNUSED5 5 +#define GPIO14_FUN_I2C_SCL 6 +#define GPIO14_FUN_UART_SIG6 7 +#define GPIO14_FUN_PWM_CH4 8 +#define GPIO14_FUN_FEM_GPIO_2 9 +#define GPIO14_FUN_GPIP_CH2 10 +#define GPIO14_FUN_SWGPIO_14 11 +#define GPIO14_FUN_E21_TCK 14 +/* GPIO15 function definition */ +#define GPIO15_FUN_UNUSED1 1 +#define GPIO15_FUN_UNUSED2 2 +#define GPIO15_FUN_UNUSED3 3 +#define GPIO15_FUN_SPI_SCLK 4 +#define GPIO15_FUN_UNUSED5 5 +#define GPIO15_FUN_I2C_SDA 6 +#define GPIO15_FUN_UART_SIG7 7 +#define GPIO15_FUN_PWM_CH0 8 +#define GPIO15_FUN_FEM_GPIO_3 9 +#define GPIO15_FUN_PSW_IRRCV_OUT_GPIP_CH11 10 +#define GPIO15_FUN_SWGPIO_15 11 +#define GPIO15_FUN_E21_TDO 14 +/* GPIO16 function definition */ +#define GPIO16_FUN_UNUSED1 1 +#define GPIO16_FUN_UNUSED2 2 +#define GPIO16_FUN_UNUSED3 3 +#define GPIO16_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO16_FUN_UNUSED5 5 +#define GPIO16_FUN_I2C_SCL 6 +#define GPIO16_FUN_UART_SIG0 7 +#define GPIO16_FUN_PWM_CH1 8 +#define GPIO16_FUN_FEM_GPIO_0 9 +#define GPIO16_FUN_UNUSED10 10 +#define GPIO16_FUN_SWGPIO_16 11 +#define GPIO16_FUN_E21_TMS 14 +/* GPIO17 function definition */ +#define GPIO17_FUN_UNUSED1 1 +#define GPIO17_FUN_SF_D3 2 +#define GPIO17_FUN_UNUSED3 3 +#define GPIO17_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO17_FUN_UNUSED5 5 +#define GPIO17_FUN_I2C_SDA 6 +#define GPIO17_FUN_UART_SIG1 7 +#define GPIO17_FUN_PWM_CH2 8 +#define GPIO17_FUN_FEM_GPIO_1 9 +#define GPIO17_FUN_PMIP_DC_TP_OUT 10 +#define GPIO17_FUN_SWGPIO_17 11 +#define GPIO17_FUN_E21_TDI 14 +/* GPIO18 function definition */ +#define GPIO18_FUN_UNUSED1 1 +#define GPIO18_FUN_SF_D2 2 +#define GPIO18_FUN_UNUSED3 3 +#define GPIO18_FUN_SPI_SS 4 +#define GPIO18_FUN_UNUSED5 5 +#define GPIO18_FUN_I2C_SCL 6 +#define GPIO18_FUN_UART_SIG2 7 +#define GPIO18_FUN_PWM_CH3 8 +#define GPIO18_FUN_FEM_GPIO_2 9 +#define GPIO18_FUN_UNUSED10 10 +#define GPIO18_FUN_SWGPIO_18 11 +#define GPIO18_FUN_E21_TCK 14 +/* GPIO19 function definition */ +#define GPIO19_FUN_UNUSED1 1 +#define GPIO19_FUN_SF_D1 2 +#define GPIO19_FUN_UNUSED3 3 +#define GPIO19_FUN_SPI_SCLK 4 +#define GPIO19_FUN_UNUSED5 5 +#define GPIO19_FUN_I2C_SDA 6 +#define GPIO19_FUN_UART_SIG3 7 +#define GPIO19_FUN_PWM_CH4 8 +#define GPIO19_FUN_FEM_GPIO_3 9 +#define GPIO19_FUN_UNUSED10 10 +#define GPIO19_FUN_SWGPIO_19 11 +#define GPIO19_FUN_E21_TDO 14 +/* GPIO20 function definition */ +#define GPIO20_FUN_UNUSED1 1 +#define GPIO20_FUN_SF_D0 2 +#define GPIO20_FUN_UNUSED3 3 +#define GPIO20_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO20_FUN_UNUSED5 5 +#define GPIO20_FUN_I2C_SCL 6 +#define GPIO20_FUN_UART_SIG4 7 +#define GPIO20_FUN_PWM_CH0 8 +#define GPIO20_FUN_FEM_GPIO_0 9 +#define GPIO20_FUN_UNUSED10 10 +#define GPIO20_FUN_SWGPIO_20 11 +#define GPIO20_FUN_E21_TMS 14 +/* GPIO21 function definition */ +#define GPIO21_FUN_UNUSED1 1 +#define GPIO21_FUN_SF_CS 2 +#define GPIO21_FUN_UNUSED3 3 +#define GPIO21_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO21_FUN_UNUSED5 5 +#define GPIO21_FUN_I2C_SDA 6 +#define GPIO21_FUN_UART_SIG5 7 +#define GPIO21_FUN_PWM_CH1 8 +#define GPIO21_FUN_FEM_GPIO_1 9 +#define GPIO21_FUN_UNUSED10 10 +#define GPIO21_FUN_SWGPIO_21 11 +#define GPIO21_FUN_E21_TDI 14 +/* GPIO22 function definition */ +#define GPIO22_FUN_UNUSED1 1 +#define GPIO22_FUN_SF_CLK_OUT 2 +#define GPIO22_FUN_UNUSED3 3 +#define GPIO22_FUN_SPI_SS 4 +#define GPIO22_FUN_UNUSED5 5 +#define GPIO22_FUN_I2C_SCL 6 +#define GPIO22_FUN_UART_SIG6 7 +#define GPIO22_FUN_PWM_CH2 8 +#define GPIO22_FUN_FEM_GPIO_2 9 +#define GPIO22_FUN_UNUSED10 10 +#define GPIO22_FUN_SWGPIO_22 11 +#define GPIO22_FUN_E21_TCK 14 + +#endif /*__BL602_GPIO_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_hbn.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_hbn.h new file mode 100644 index 0000000000000000000000000000000000000000..63e185b02a107c5c4ae47fafbe5908d5cb84d508 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_hbn.h @@ -0,0 +1,499 @@ +/** + ****************************************************************************** + * @file bl602_hbn.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_HBN_H__ +#define __BL602_HBN_H__ + +#include "hbn_reg.h" +#include "bl602_aon.h" +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Public_Types + * @{ + */ + +/** + * @brief HBN PIR interrupt configuration type definition + */ +typedef struct +{ + BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */ + BL_Fun_Type highIntEn; /*!< High will trigger interrupt */ +} HBN_PIR_INT_CFG_Type; + +/** + * @brief HBN PIR low pass filter type definition + */ +typedef enum { + HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */ + HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */ +} HBN_PIR_LPF_Type; + +/** + * @brief HBN PIR high pass filter type definition + */ +typedef enum { + HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */ + HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */ + HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */ +} HBN_PIR_HPF_Type; + +/** + * @brief HBN BOR threshold type definition + */ +typedef enum { + HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */ + HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */ +} HBN_BOR_THRES_Type; + +/** + * @brief HBN BOR mode type definition + */ +typedef enum { + HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ + HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ +} HBN_BOR_MODE_Type; + +/** + * @brief HBN 32K clock type definition + */ +typedef enum { + HBN_32K_RC = 0, /*!< HBN use rc 32k */ + HBN_32K_XTAL, /*!< HBN use xtal 32k */ + HBN_32K_DIG = 3, /*!< HBN use dig 32k */ +} HBN_32K_CLK_Type; + +/** + * @brief HBN xclk clock type definition + */ +typedef enum { + HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */ + HBN_XCLK_CLK_XTAL, /*!< use XTAL as xclk clock */ +} HBN_XCLK_CLK_Type; + +/** + * @brief HBN root clock type definition + */ +typedef enum { + HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */ + HBN_ROOT_CLK_XTAL, /*!< use XTAL as root clock */ + HBN_ROOT_CLK_PLL, /*!< use PLL as root clock */ +} HBN_ROOT_CLK_Type; + +/** + * @brief HBN UART clock type definition + */ +typedef enum { + HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */ + HBN_UART_CLK_160M, /*!< Select 160M as UART clock */ +} HBN_UART_CLK_Type; + +/** + * @brief HBN RTC interrupt delay type definition + */ +typedef enum { + HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */ + HBN_RTC_INT_DELAY_0T = 1, /*!< HBN RTC interrupt delay 0T */ +} HBN_RTC_INT_Delay_Type; + +/** + * @brief HBN interrupt type definition + */ +typedef enum { + HBN_INT_GPIO7 = 0, /*!< HBN interrupt type: GPIO7 */ + HBN_INT_GPIO8 = 1, /*!< HBN interrupt type: GPIO8 */ + HBN_INT_RTC = 16, /*!< HBN interrupt type: RTC */ + HBN_INT_PIR = 17, /*!< HBN interrupt type: PIR */ + HBN_INT_BOR = 18, /*!< HBN interrupt type: BOR */ + HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */ + HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */ +} HBN_INT_Type; + +/** + * @brief HBN acomp interrupt type definition + */ +typedef enum { + HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */ + HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */ +} HBN_ACOMP_INT_EDGE_Type; + +/** + * @brief HBN GPIO interrupt trigger type definition + */ +typedef enum { + HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: sync falling edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: sync rising edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: sync low level trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: sync high level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: async rising edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: async low level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: async high level trigger */ +} HBN_GPIO_INT_Trigger_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT0_INT_GPIO7 = 0, /*!< HBN out 0 interrupt type: GPIO7 */ + HBN_OUT0_INT_GPIO8, /*!< HBN out 0 interrupt type: GPIO8 */ + HBN_OUT0_INT_RTC, /*!< HBN out 0 interrupt type: RTC */ +} HBN_OUT0_INT_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT1_INT_PIR, /*!< HBN out 1 interrupt type: PIR */ + HBN_OUT1_INT_BOR, /*!< HBN out 1 interrupt type: BOR */ + HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */ + HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */ +} HBN_OUT1_INT_Type; + +/** + * @brief HBN LDO level type definition + */ +typedef enum { + HBN_LDO_LEVEL_0P60V = 0, /*!< HBN LDO voltage 0.60V */ + HBN_LDO_LEVEL_0P65V = 1, /*!< HBN LDO voltage 0.65V */ + HBN_LDO_LEVEL_0P70V = 2, /*!< HBN LDO voltage 0.70V */ + HBN_LDO_LEVEL_0P75V = 3, /*!< HBN LDO voltage 0.75V */ + HBN_LDO_LEVEL_0P80V = 4, /*!< HBN LDO voltage 0.80V */ + HBN_LDO_LEVEL_0P85V = 5, /*!< HBN LDO voltage 0.85V */ + HBN_LDO_LEVEL_0P90V = 6, /*!< HBN LDO voltage 0.90V */ + HBN_LDO_LEVEL_0P95V = 7, /*!< HBN LDO voltage 0.95V */ + HBN_LDO_LEVEL_1P00V = 8, /*!< HBN LDO voltage 1.00V */ + HBN_LDO_LEVEL_1P05V = 9, /*!< HBN LDO voltage 1.05V */ + HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */ + HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */ + HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */ + HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */ + HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */ + HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */ +} HBN_LDO_LEVEL_Type; + +/** + * @brief HBN level type definition + */ +typedef enum { + HBN_LEVEL_0, /*!< HBN pd_core */ + HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */ + HBN_LEVEL_2, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ + HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ +} HBN_LEVEL_Type; + +/** + * @brief HBN BOR configuration type definition + */ +typedef struct +{ + uint8_t enableBor; /*!< Enable BOR or not */ + uint8_t enableBorInt; /*!< Enable BOR interrupt or not */ + uint8_t borThreshold; /*!< BOR threshold */ + uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */ +} HBN_BOR_CFG_Type; + +/** + * @brief HBN APP configuration type definition + */ +typedef struct +{ + uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */ + uint32_t sleepTime; /*!< HBN sleep time */ + uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ + HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ + SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + HBN_LEVEL_Type hbnLevel; /*!< HBN level */ + HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ +} HBN_APP_CFG_Type; + +/*@} end of group HBN_Public_Types */ + +/** @defgroup HBN_Public_Constants + * @{ + */ + +/** @defgroup HBN_PIR_LPF_TYPE + * @{ + */ +#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \ + ((type) == HBN_PIR_LPF_DIV2)) + +/** @defgroup HBN_PIR_HPF_TYPE + * @{ + */ +#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \ + ((type) == HBN_PIR_HPF_METHOD1) || \ + ((type) == HBN_PIR_HPF_METHOD2)) + +/** @defgroup HBN_BOR_THRES_TYPE + * @{ + */ +#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \ + ((type) == HBN_BOR_THRES_2P4V)) + +/** @defgroup HBN_BOR_MODE_TYPE + * @{ + */ +#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \ + ((type) == HBN_BOR_MODE_POR_RELEVANT)) + +/** @defgroup HBN_32K_CLK_TYPE + * @{ + */ +#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \ + ((type) == HBN_32K_XTAL) || \ + ((type) == HBN_32K_DIG)) + +/** @defgroup HBN_XCLK_CLK_TYPE + * @{ + */ +#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \ + ((type) == HBN_XCLK_CLK_XTAL)) + +/** @defgroup HBN_ROOT_CLK_TYPE + * @{ + */ +#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \ + ((type) == HBN_ROOT_CLK_XTAL) || \ + ((type) == HBN_ROOT_CLK_PLL)) + +/** @defgroup HBN_UART_CLK_TYPE + * @{ + */ +#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \ + ((type) == HBN_UART_CLK_160M)) + +/** @defgroup HBN_RTC_INT_DELAY_TYPE + * @{ + */ +#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \ + ((type) == HBN_RTC_INT_DELAY_0T)) + +/** @defgroup HBN_INT_TYPE + * @{ + */ +#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO7) || \ + ((type) == HBN_INT_GPIO8) || \ + ((type) == HBN_INT_RTC) || \ + ((type) == HBN_INT_PIR) || \ + ((type) == HBN_INT_BOR) || \ + ((type) == HBN_INT_ACOMP0) || \ + ((type) == HBN_INT_ACOMP1)) + +/** @defgroup HBN_ACOMP_INT_EDGE_TYPE + * @{ + */ +#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \ + ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE)) + +/** @defgroup HBN_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + +/** @defgroup HBN_OUT0_INT_TYPE + * @{ + */ +#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO7) || \ + ((type) == HBN_OUT0_INT_GPIO8) || \ + ((type) == HBN_OUT0_INT_RTC)) + +/** @defgroup HBN_OUT1_INT_TYPE + * @{ + */ +#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \ + ((type) == HBN_OUT1_INT_BOR) || \ + ((type) == HBN_OUT1_INT_ACOMP0) || \ + ((type) == HBN_OUT1_INT_ACOMP1)) + +/** @defgroup HBN_LDO_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \ + ((type) == HBN_LDO_LEVEL_0P65V) || \ + ((type) == HBN_LDO_LEVEL_0P70V) || \ + ((type) == HBN_LDO_LEVEL_0P75V) || \ + ((type) == HBN_LDO_LEVEL_0P80V) || \ + ((type) == HBN_LDO_LEVEL_0P85V) || \ + ((type) == HBN_LDO_LEVEL_0P90V) || \ + ((type) == HBN_LDO_LEVEL_0P95V) || \ + ((type) == HBN_LDO_LEVEL_1P00V) || \ + ((type) == HBN_LDO_LEVEL_1P05V) || \ + ((type) == HBN_LDO_LEVEL_1P10V) || \ + ((type) == HBN_LDO_LEVEL_1P15V) || \ + ((type) == HBN_LDO_LEVEL_1P20V) || \ + ((type) == HBN_LDO_LEVEL_1P25V) || \ + ((type) == HBN_LDO_LEVEL_1P30V) || \ + ((type) == HBN_LDO_LEVEL_1P35V)) + +/** @defgroup HBN_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \ + ((type) == HBN_LEVEL_1) || \ + ((type) == HBN_LEVEL_2) || \ + ((type) == HBN_LEVEL_3)) + +/*@} end of group HBN_Public_Constants */ + +/** @defgroup HBN_Public_Macros + * @{ + */ +#define HBN_RAM_SIZE (4 * 1024) +#define HBN_RTC_COMP_BIT0_39 0x01 +#define HBN_RTC_COMP_BIT0_23 0x02 +#define HBN_RTC_COMP_BIT13_39 0x04 +#define HBN_STATUS_ENTER_FLAG 0x4e424845 +#define HBN_STATUS_WAKEUP_FLAG 0x4e424857 +#define HBN_WAKEUP_GPIO_NONE 0x00 +#define HBN_WAKEUP_GPIO_7 0x01 +#define HBN_WAKEUP_GPIO_8 0x02 +#define HBN_WAKEUP_GPIO_ALL 0x03 + +/*@} end of group HBN_Public_Macros */ + +/** @defgroup HBN_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void); +void HBN_OUT1_IRQHandler(void); +#endif +/*----------*/ +void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg); +void HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg); +void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg); +void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); +void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); +BL_Err_Type HBN_Reset(void); +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv); +BL_Err_Type HBN_Disable(void); +/*----------*/ +BL_Err_Type HBN_PIR_Enable(void); +BL_Err_Type HBN_PIR_Disable(void); +BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg); +BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf); +BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf); +BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold); +uint16_t HBN_Get_PIR_Threshold(void); +BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval); +uint16_t HBN_Get_PIR_Interval(void); +/*----------*/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void); +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode); +/*----------*/ +BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel); +/*----------*/ +BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType); +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel); +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk); +HBN_ROOT_CLK_Type HBN_Get_Root_CLK_Sel(void); +BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk); +/*----------*/ +BL_Err_Type HBN_Set_HRAM_slp(void); +BL_Err_Type HBN_Set_HRAM_Ret(void); +/*----------*/ +uint32_t HBN_Get_Status_Flag(void); +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag); +uint32_t HBN_Get_Wakeup_Addr(void); +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr); +/*----------*/ +BL_Err_Type HBN_Clear_RTC_Counter(void); +BL_Err_Type HBN_Enable_RTC_Counter(void); +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode); +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh); +BL_Err_Type HBN_Clear_RTC_IRQ(void); +/*----------*/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType); +BL_Err_Type HBN_GPIO_INT_Disable(void); +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType); +uint8_t HBN_Get_Pin_Wakeup_Mode(void); +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType); +BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable); +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); +BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal); +/*----------*/ +BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +/*----------*/ +BL_Err_Type HBN_Enable_BOR_IRQ(void); +BL_Err_Type HBN_Disable_BOR_IRQ(void); +/*----------*/ +BL_Err_Type HBN_Out0_IRQHandler_Install(void); +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type HBN_Out1_IRQHandler_Install(void); +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, + BL_Fun_Type dlyEn, uint8_t dlySec); +/*----------*/ +BL_Err_Type HBN_Power_On_Xtal_32K(void); +BL_Err_Type HBN_Power_Off_Xtal_32K(void); +BL_Err_Type HBN_Power_On_RC32K(void); +BL_Err_Type HBN_Power_Off_RC32K(void); +BL_Err_Type HBN_Trim_RC32K(void); +BL_Err_Type HBN_Set_Embedded_Flash_Pullup(uint8_t enable); +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg); + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_HBN_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_i2c.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..0b267f9fba1c4d461ea56c8659341fa50665b434 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_i2c.h @@ -0,0 +1,198 @@ +/** + ****************************************************************************** + * @file bl602_i2c.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_I2C_H__ +#define __BL602_I2C_H__ + +#include "i2c_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types + * @{ + */ + +/** + * @brief I2C No. type definition + */ +typedef enum { + I2C0_ID = 0, /*!< I2C0 define */ + I2C_ID_MAX, /*!< I2C max define */ +} I2C_ID_Type; + +/** + * @brief I2C read/write type definition + */ +typedef enum { + I2C_WRITE = 0, /*!< I2C write direction */ + I2C_READ, /*!< I2C read direction */ +} I2C_Direction_Type; + +/** + * @brief I2C interrupt type definition + */ +typedef enum { + I2C_TRANS_END_INT, /*!< I2C transfer end interrupt */ + I2C_TX_FIFO_READY_INT, /*!< I2C TX fifo ready interrupt */ + I2C_RX_FIFO_READY_INT, /*!< I2C RX fifo ready interrupt */ + I2C_NACK_RECV_INT, /*!< I2C nack received interrupt */ + I2C_ARB_LOST_INT, /*!< I2C arbitration lost interrupt */ + I2C_FIFO_ERR_INT, /*!< I2C TX/RX FIFO error interrupt */ + I2C_INT_ALL, /*!< I2C interrupt all type */ +} I2C_INT_Type; + +/** + * @brief I2S start condition phase structure type definition + */ +typedef struct +{ + uint8_t len0; /*!< Length of START condition phase 0 */ + uint8_t len1; /*!< Length of START condition phase 1 */ + uint8_t len2; /*!< Length of START condition phase 2 */ + uint8_t len3; /*!< Length of START condition phase 3 */ +} I2C_Start_Condition_Phase_Type; + +/** + * @brief I2S stop condition phase structure type definition + */ +typedef struct +{ + uint8_t len0; /*!< Length of STOP condition phase 0 */ + uint8_t len1; /*!< Length of STOP condition phase 1 */ + uint8_t len2; /*!< Length of STOP condition phase 2 */ + uint8_t len3; /*!< Length of STOP condition phase 3 */ +} I2C_Stop_Condition_Phase_Type; + +/** + * @brief I2S data phase structure type definition + */ +typedef struct +{ + uint8_t len0; /*!< Length of DATA phase 0 */ + uint8_t len1; /*!< Length of DATA phase 1 */ + uint8_t len2; /*!< Length of DATA phase 2 */ + uint8_t len3; /*!< Length of DATA phase 3 */ +} I2C_Data_Phase_Type; + +/** + * @brief I2S transfer structure type definition + */ +typedef struct +{ + uint8_t slaveAddr; /*!< I2C slave address */ + BL_Fun_Type stopEveryByte; /*!< I2C all data byte with stop bit */ + uint8_t subAddrSize; /*!< Specifies the size of I2C sub address section */ + uint32_t subAddr; /*!< I2C sub address */ + uint16_t dataSize; /*!< Specifies the size of I2C data section */ + uint8_t *data; /*!< Specifies the pointer of I2C R/W data */ +} I2C_Transfer_Cfg; + +/*@} end of group I2C_Public_Types */ + +/** @defgroup I2C_Public_Constants + * @{ + */ + +/** @defgroup I2C_ID_TYPE + * @{ + */ +#define IS_I2C_ID_TYPE(type) (((type) == I2C0_ID) || \ + ((type) == I2C_ID_MAX)) + +/** @defgroup I2C_DIRECTION_TYPE + * @{ + */ +#define IS_I2C_DIRECTION_TYPE(type) (((type) == I2C_WRITE) || \ + ((type) == I2C_READ)) + +/** @defgroup I2C_INT_TYPE + * @{ + */ +#define IS_I2C_INT_TYPE(type) (((type) == I2C_TRANS_END_INT) || \ + ((type) == I2C_TX_FIFO_READY_INT) || \ + ((type) == I2C_RX_FIFO_READY_INT) || \ + ((type) == I2C_NACK_RECV_INT) || \ + ((type) == I2C_ARB_LOST_INT) || \ + ((type) == I2C_FIFO_ERR_INT) || \ + ((type) == I2C_INT_ALL)) + +/*@} end of group I2C_Public_Constants */ + +/** @defgroup I2C_Public_Macros + * @{ + */ + +/*@} end of group I2C_Public_Macros */ + +/** @defgroup I2C_Public_Functions + * @{ + */ + +/** + * @brief I2C Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_IRQHandler(void); +void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun); +#endif +void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data); +uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo); +void I2C_Enable(I2C_ID_Type i2cNo); +void I2C_Disable(I2C_ID_Type i2cNo); +BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt); +BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo); +void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase); +void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk); +void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable); +void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg); +BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo); +BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); +BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); +void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask); + +/*@} end of group I2C_Public_Functions */ + +/*@} end of group I2C */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_I2C_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_ir.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_ir.h new file mode 100644 index 0000000000000000000000000000000000000000..5c0f9ef6f68e34c8d072e9724c9856bf464d6d7b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_ir.h @@ -0,0 +1,257 @@ +/** + ****************************************************************************** + * @file bl602_ir.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_IR_H__ +#define __BL602_IR_H__ + +#include "ir_reg.h" +#include "bl602_common.h" +#include "bl602_hbn.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup IR + * @{ + */ + +/** @defgroup IR_Public_Types + * @{ + */ + +/** + * @brief IR direction type definition + */ +typedef enum { + IR_TX, /*!< IR TX direction */ + IR_RX, /*!< IR RX direction */ + IR_TXRX, /*!< IR TX and RX direction */ +} IR_Direction_Type; + +/** + * @brief IR word type definition + */ +typedef enum { + IR_WORD_0, /*!< IR data word 0 */ + IR_WORD_1, /*!< IR data word 1 */ +} IR_Word_Type; + +/** + * @brief IR RX mode type definition + */ +typedef enum { + IR_RX_NEC, /*!< IR RX NEC mode */ + IR_RX_RC5, /*!< IR RX RC5 mode */ + IR_RX_SWM, /*!< IR RX software pulse-width detection mode */ +} IR_RxMode_Type; + +/** + * @brief IR interrupt type definition + */ +typedef enum { + IR_INT_TX, /*!< IR TX transfer end interrupt */ + IR_INT_RX, /*!< IR RX transfer end interrupt */ + IR_INT_ALL, /*!< IR all interrupt */ +} IR_INT_Type; + +/** + * @brief IR fifo underflow or overflow type definition + */ +typedef enum { + IR_RX_FIFO_UNDERFLOW, /*!< Underflow flag of rx fifo */ + IR_RX_FIFO_OVERFLOW, /*!< Overflow flag of rx fifo */ +} IR_FifoStatus_Type; + +/** + * @brief IR TX configuration structure type definition + */ +typedef struct +{ + uint8_t dataBits; /*!< Bit count of data phase */ + BL_Fun_Type tailPulseInverse; /*!< Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type tailPulse; /*!< Enable or disable signal of tail pulse (don't care if SWM is enabled) */ + BL_Fun_Type headPulseInverse; /*!< Enable or disable signal of head pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type headPulse; /*!< Enable or disable signal of head pulse (don't care if SWM is enabled) */ + BL_Fun_Type logic1PulseInverse; /*!< Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type logic0PulseInverse; /*!< Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type dataPulse; /*!< Enable or disable signal of data pulse (don't care if SWM is enabled) */ + BL_Fun_Type outputModulation; /*!< Enable or disable signal of output modulation */ + BL_Fun_Type outputInverse; /*!< Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high */ +} IR_TxCfg_Type; + +/** + * @brief IR TX pulse width configuration structure type definition + */ +typedef struct +{ + uint8_t logic0PulseWidth_1; /*!< Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) */ + uint8_t logic0PulseWidth_0; /*!< Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) */ + uint8_t logic1PulseWidth_1; /*!< Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled) */ + uint8_t logic1PulseWidth_0; /*!< Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled) */ + uint8_t headPulseWidth_1; /*!< Pulse width of head pulse phase 1 (don't care if SWM is enabled) */ + uint8_t headPulseWidth_0; /*!< Pulse width of head pulse phase 0 (don't care if SWM is enabled) */ + uint8_t tailPulseWidth_1; /*!< Pulse width of tail pulse phase 1 (don't care if SWM is enabled) */ + uint8_t tailPulseWidth_0; /*!< Pulse width of tail pulse phase 0 (don't care if SWM is enabled) */ + uint8_t moduWidth_1; /*!< Modulation phase 1 width */ + uint8_t moduWidth_0; /*!< Modulation phase 0 width */ + uint16_t pulseWidthUnit; /*!< Pulse width unit */ +} IR_TxPulseWidthCfg_Type; + +/** + * @brief IR TX software mode pulse width(multiples of pulse width unit) configuration structure type definition + */ +typedef struct +{ + uint32_t swmData0; /*!< SWM pulse width data 0~7,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData1; /*!< SWM pulse width data 8~15,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData2; /*!< SWM pulse width data 16~23,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData3; /*!< SWM pulse width data 24~31,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData4; /*!< SWM pulse width data 32~39,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData5; /*!< SWM pulse width data 40~47,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData6; /*!< SWM pulse width data 48~55,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData7; /*!< SWM pulse width data 56~63,multiples of pulse width unit,each pulse is represented by 4-bit */ +} IR_TxSWMPulseWidthCfg_Type; + +/** + * @brief IR RX configuration structure type definition + */ +typedef struct +{ + IR_RxMode_Type rxMode; /*!< Set ir rx mode */ + BL_Fun_Type inputInverse; /*!< Enable or disable signal of input inverse */ + uint16_t endThreshold; /*!< Pulse width threshold to trigger end condition */ + uint16_t dataThreshold; /*!< Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled) */ + BL_Fun_Type rxDeglitch; /*!< Enable or disable signal of rx input de-glitch function */ + uint8_t DeglitchCnt; /*!< De-glitch function cycle count */ +} IR_RxCfg_Type; + +/*@} end of group IR_Public_Types */ + +/** @defgroup IR_Public_Constants + * @{ + */ + +/** @defgroup IR_DIRECTION_TYPE + * @{ + */ +#define IS_IR_DIRECTION_TYPE(type) (((type) == IR_TX) || \ + ((type) == IR_RX) || \ + ((type) == IR_TXRX)) + +/** @defgroup IR_WORD_TYPE + * @{ + */ +#define IS_IR_WORD_TYPE(type) (((type) == IR_WORD_0) || \ + ((type) == IR_WORD_1)) + +/** @defgroup IR_RXMODE_TYPE + * @{ + */ +#define IS_IR_RXMODE_TYPE(type) (((type) == IR_RX_NEC) || \ + ((type) == IR_RX_RC5) || \ + ((type) == IR_RX_SWM)) + +/** @defgroup IR_INT_TYPE + * @{ + */ +#define IS_IR_INT_TYPE(type) (((type) == IR_INT_TX) || \ + ((type) == IR_INT_RX) || \ + ((type) == IR_INT_ALL)) + +/** @defgroup IR_FIFOSTATUS_TYPE + * @{ + */ +#define IS_IR_FIFOSTATUS_TYPE(type) (((type) == IR_RX_FIFO_UNDERFLOW) || \ + ((type) == IR_RX_FIFO_OVERFLOW)) + +/*@} end of group IR_Public_Constants */ + +/** @defgroup IR_Public_Macros + * @{ + */ +#define IR_RX_FIFO_SIZE 64 + +/*@} end of group IR_Public_Macros */ + +/** @defgroup IR_Public_Functions + * @{ + */ + +/** + * @brief IR Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void IRRX_IRQHandler(void); +void IRTX_IRQHandler(void); +#endif +BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg); +BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg); +BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg); +BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg); +BL_Err_Type IR_DeInit(void); +BL_Err_Type IR_Enable(IR_Direction_Type direct); +BL_Err_Type IR_Disable(IR_Direction_Type direct); +BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM); +BL_Err_Type IR_RxFIFOClear(void); +BL_Err_Type IR_SendData(IR_Word_Type irWord, uint32_t data); +BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length); +BL_Err_Type IR_SendCommand(uint32_t word1, uint32_t word0); +BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length); +BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command); +BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType); +BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun); +BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType); +BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts); +uint32_t IR_ReceiveData(IR_Word_Type irWord); +uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length); +BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command); +uint8_t IR_GetRxDataBitCount(void); +uint8_t IR_GetRxFIFOCount(void); +IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length); +BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length); +uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data); +BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, + uint8_t code1L); +BL_Err_Type IR_LEDSend(uint32_t data); + +/*@} end of group IR_Public_Functions */ + +/*@} end of group IR */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_IR_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_it.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_it.h new file mode 100644 index 0000000000000000000000000000000000000000..fd81b204c09cd6e380f8f9918e80ba2690d5dcc7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_it.h @@ -0,0 +1,49 @@ +#ifndef __BL602_IT_H__ +#define __BL602_IT_H__ + +#include "bl602.h" +#include "bl_common.h" + +/** @addtogroup BL606_Peripheral_Driver + * @{ + */ + +/** @addtogroup COMMON + * @{ + */ + +/** @defgroup COMMON_Public_Types + * @{ + */ + +/*@} end of group COMMON_Public_Types */ + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** @defgroup DRIVER_INT_PERIPH + * @{ + */ +#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) + +/*@} end of group DRIVER_INT_PERIPH */ + +/** @defgroup DRIVER_INT_MASK + * @{ + */ +#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) + +/*@} end of group COMMON_Public_Constants */ + +/*@} end of group DRIVER_Public_Macro */ + +/** @defgroup DRIVER_Public_FunctionDeclaration + * @brief DRIVER functions declaration + * @{ + */ +void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); + +/*@} end of group DRIVER_COMMON */ + +#endif /* __BL602_COMMON_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_l1c.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_l1c.h new file mode 100644 index 0000000000000000000000000000000000000000..e8fccde77e4207fa3cab459982e3b6e31ded5f1a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_l1c.h @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file bl602_l1c.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_L1C_H__ +#define __BL602_L1C_H__ + +#include "l1c_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup L1C + * @{ + */ + +/** @defgroup L1C_Public_Types + * @{ + */ + +/** + * @brief L1C configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type wrapDis; /*!< wrap disable */ + BL_Fun_Type bypassEn; /*!< bypass cache enable */ + uint8_t wayDis; /*!< Disable part of cache ways & used as ITCM */ + BL_Fun_Type cntEn; /*!< l1c count enable */ +} L1C_CACHE_Cfg_Type; + +/** + * @brief L1C BMX arb mode type definition + */ +typedef enum { + L1C_BMX_ARB_FIX, /*!< 0->fix */ + L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + L1C_BMX_ARB_RANDOM, /*!< 3->random */ +} L1C_BMX_ARB_Type; + +/** + * @brief L1C BMX configuration structure type definition + */ +typedef struct +{ + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +} L1C_BMX_Cfg_Type; + +/** + * @brief L1C BMX bus err type definition + */ +typedef enum { + L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + L1C_BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +} L1C_BMX_BUS_ERR_Type; + +/** + * @brief L1C BMX bus err interrupt type definition + */ +typedef enum { + L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */ + L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */ +} L1C_BMX_ERR_INT_Type; + +/** + * @brief L1C BMX time out interrupt type definition + */ +typedef enum { + L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */ + L1C_BMX_TO_INT_ALL, /*!< L1C_BMX timeout interrupt max num */ +} L1C_BMX_TO_INT_Type; + +/*@} end of group L1C_Public_Types */ + +/** @defgroup L1C_Public_Constants + * @{ + */ + +/** @defgroup L1C_BMX_ARB_TYPE + * @{ + */ +#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) || \ + ((type) == L1C_BMX_ARB_ROUND_ROBIN) || \ + ((type) == L1C_BMX_ARB_RANDOM)) + +/** @defgroup L1C_BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == L1C_BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup L1C_BMX_ERR_INT_TYPE + * @{ + */ +#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \ + ((type) == L1C_BMX_ERR_INT_ALL)) + +/** @defgroup L1C_BMX_TO_INT_TYPE + * @{ + */ +#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \ + ((type) == L1C_BMX_TO_INT_ALL)) + +/*@} end of group L1C_Public_Constants */ + +/** @defgroup L1C_Public_Macros + * @{ + */ +#if 1 +/*NP config address */ +#define L1C_CONF_REG_NP (L1C_BASE + 0x00) +#define L1C_HIT_CNT_LSB_REG_NP (L1C_BASE + 0x04) +#define L1C_HIT_CNT_MSB_REG_NP (L1C_BASE + 0x08) +#define L1C_MISS_CNT_REG_NP (L1C_BASE + 0x0C) +/* Get miss and hit count */ +#define L1C_Get_Miss_Cnt_NP() BL602_REG_RD(L1C_MISS_CNT_REG_NP) +#define L1C_Get_Hit_Cnt_LSB_NP() BL602_REG_RD(L1C_HIT_CNT_LSB_REG_NP) +#define L1C_Get_Hit_Cnt_MSB_NP() BL602_REG_RD(L1C_HIT_CNT_MSB_REG_NP) +#endif + +/*@} end of group L1C_Public_Macros */ + +/** @defgroup L1C_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_ERR_IRQHandler(void); +void L1C_BMX_TO_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap); +BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal); +BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable); +/*----------*/ +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg); +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void); +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void); +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void); +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void); +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType); +uint32_t L1C_BMX_Get_Err_Addr(void); +BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, + intCallback_Type *cbFun); +/*----------*/; + +/*@} end of group L1C_Public_Functions */ + +/*@} end of group L1C */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_L1C_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_mfg_efuse.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_mfg_efuse.h new file mode 100644 index 0000000000000000000000000000000000000000..3c4ec09824e6ecd53af3828b7d12a154da394443 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_mfg_efuse.h @@ -0,0 +1,24 @@ +#ifndef __BL602_MFG_EFUSE_H__ +#define __BL602_MFG_EFUSE_H__ + +#include "stdint.h" + +uint8_t mfg_efuse_get_rf_cal_slots(void); +void mfg_efuse_set_rf_cal_slots(uint8_t slots); +uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload); +int8_t mfg_efuse_write_xtal_capcode_pre(uint8_t capcode, uint8_t program); +void mfg_efuse_write_xtal_capcode(void); +int8_t mfg_efuse_read_xtal_capcode(uint8_t *capcode, uint8_t reload); +uint8_t mfg_efuse_is_poweroffset_slot_empty(uint8_t reload); +int8_t mfg_efuse_write_poweroffset_pre(int8_t pwrOffset[14], uint8_t program); +void mfg_efuse_write_poweroffset(void); +int8_t mfg_efuse_read_poweroffset(int8_t pwrOffset[14], uint8_t reload); +uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload); +int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6], uint8_t program); +void mfg_efuse_write_macaddr(void); +int8_t mfg_efuse_read_macaddr(uint8_t mac[6], uint8_t reload); +int8_t mfg_efuse_read(uint32_t addr, uint32_t *data, uint32_t countInword, uint8_t reload); +int8_t mfg_efuse_program(void); +int8_t mfg_efuse_write_pre(uint32_t addr, uint32_t *data, uint32_t countInword); + +#endif /*__MFG_GPIO_API_H__*/ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_pds.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_pds.h new file mode 100644 index 0000000000000000000000000000000000000000..f6b8ccd07b3617271cd5114b06a6c3d36fe5858a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_pds.h @@ -0,0 +1,502 @@ +/** + ****************************************************************************** + * @file bl602_pds.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_PDS_H__ +#define __BL602_PDS_H__ + +#include "pds_reg.h" +#include "bl602_ef_ctrl.h" +#include "bl602_aon.h" +#include "bl602_hbn.h" +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Public_Types + * @{ + */ + +/** + * @brief PDS LDO level type definition + */ +typedef enum { + PDS_LDO_LEVEL_0P60V = 0, /*!< PDS LDO voltage 0.60V */ + PDS_LDO_LEVEL_0P65V = 1, /*!< PDS LDO voltage 0.65V */ + PDS_LDO_LEVEL_0P70V = 2, /*!< PDS LDO voltage 0.70V */ + PDS_LDO_LEVEL_0P75V = 3, /*!< PDS LDO voltage 0.75V */ + PDS_LDO_LEVEL_0P80V = 4, /*!< PDS LDO voltage 0.80V */ + PDS_LDO_LEVEL_0P85V = 5, /*!< PDS LDO voltage 0.85V */ + PDS_LDO_LEVEL_0P90V = 6, /*!< PDS LDO voltage 0.90V */ + PDS_LDO_LEVEL_0P95V = 7, /*!< PDS LDO voltage 0.95V */ + PDS_LDO_LEVEL_1P00V = 8, /*!< PDS LDO voltage 1.00V */ + PDS_LDO_LEVEL_1P05V = 9, /*!< PDS LDO voltage 1.05V */ + PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */ + PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */ + PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */ + PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */ + PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */ + PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */ +} PDS_LDO_LEVEL_Type; + +/** + * @brief PDS configuration type definition + */ +typedef struct +{ + uint32_t pdsStart : 1; /*!< [0]PDS Start */ + uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */ + uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */ + uint32_t saveWiFiState : 1; /*!< [3]Save WIFI State Before Enter PDS */ + uint32_t dcdc18Off : 1; /*!< [4]power down dcdc18 during PDS */ + uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */ + uint32_t rsv6_7 : 2; /*!< [7:6]reserve */ + uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */ + uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */ + uint32_t rsv10 : 1; /*!< [10]reserve */ + uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */ + uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */ + uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */ + uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */ + uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */ + uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */ + uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */ + uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */ + uint32_t rsv19_20 : 2; /*!< [20:19]reserve */ + uint32_t wfiMask : 1; /*!< [21]pds start condition mask np_wfi */ + uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */ + uint32_t rsv23 : 1; /*!< [23]reserve */ + uint32_t pdsLdoVol : 4; /*!< [27:24]LDO voltage value in PDS mode */ + uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */ + uint32_t pdsCtlPllSel : 2; /*!< [31:30]select the way PLL controlled by PDS */ +} PDS_CTL_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t cpuPwrOff : 1; /*!< [0] */ + uint32_t cpuRst : 1; /*!< [1] */ + uint32_t cpuMemStby : 1; /*!< [2] */ + uint32_t cpuGateClk : 1; /*!< [3] */ + uint32_t rsv4_11 : 8; /*!< [11:4]reserve */ + uint32_t WbPwrOff : 1; /*!< [12] */ + uint32_t WbRst : 1; /*!< [13] */ + uint32_t WbMemStby : 1; /*!< [14] */ + uint32_t WbGateClk : 1; /*!< [15] */ + uint32_t rsv16_23 : 8; /*!< [23:16]reserve */ + uint32_t MiscPwrOff : 1; /*!< [24] */ + uint32_t MiscRst : 1; /*!< [25] */ + uint32_t MiscMemStby : 1; /*!< [26] */ + uint32_t MiscGateClk : 1; /*!< [27] */ + uint32_t rsv28_31 : 4; /*!< [31:28]reserve */ +} PDS_CTL4_Type; + +/** + * @brief PDS interrupt type definition + */ +typedef enum { + PDS_INT_WAKEUP = 0, /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */ + PDS_INT_HBN_GPIO_IRRX_BLE_WIFI = 1, /*!< PDS in interrupt source HBN_Wakeup_Source/All_GPIO_Wakeup/IRRX/BLE_Wakeup_Eveent/WIFI_Wakeup_Event */ + PDS_INT_RF_DONE = 2, /*!< PDS RF done interrupt */ + PDS_INT_PLL_DONE = 3, /*!< PDS PLL done interrupt */ + PDS_INT_MAX = 4, /*!< PDS int max number */ +} PDS_INT_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t forceCpuPwrOff : 1; /*!< [0]manual force NP power off */ + uint32_t rsv1 : 1; /*!< [1]reserve */ + uint32_t forceWbPwrOff : 1; /*!< [2]manual force WB power off */ + uint32_t rsv3 : 1; /*!< [3]reserve */ + uint32_t forceCpuIsoPwrOff : 1; /*!< [4]manual force NP isolation */ + uint32_t rsv5 : 1; /*!< [5]reserve */ + uint32_t forceWbIsoPwrOff : 1; /*!< [6]manual force WB isolation */ + uint32_t rsv7 : 1; /*!< [7]reserve */ + uint32_t forceCpuPdsRst : 1; /*!< [8]manual force NP pds reset */ + uint32_t rsv9 : 1; /*!< [9]reserve */ + uint32_t forceWbPdsRst : 1; /*!< [10]manual force WB pds reset */ + uint32_t rsv11 : 1; /*!< [11]reserve */ + uint32_t forceCpuMemStby : 1; /*!< [12]manual force NP memory sleep */ + uint32_t rsv13 : 1; /*!< [13]reserve */ + uint32_t forceWbMemStby : 1; /*!< [14]manual force WB memory sleep */ + uint32_t rsv15 : 1; /*!< [15]reserve */ + uint32_t forceCpuGateClk : 1; /*!< [16]manual force NP clock gated */ + uint32_t rsv17 : 1; /*!< [17]reserve */ + uint32_t forceWbGateClk : 1; /*!< [18]manual force WB clock gated */ + uint32_t rsv19_31 : 12; /*!< [31:19]reserve */ +} PDS_CTL2_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t rsv0 : 1; /*!< [0]reserve */ + uint32_t forceMiscPwrOff : 1; /*!< [1]manual force MISC pwr_off */ + uint32_t rsv2_3 : 2; /*!< [3:2]reserve */ + uint32_t forceMiscIsoEn : 1; /*!< [4]manual force MISC iso_en */ + uint32_t rsv5_6 : 2; /*!< [6:5]reserve */ + uint32_t forceMiscPdsRst : 1; /*!< [7]manual force MISC pds_rst */ + uint32_t rsv8_9 : 2; /*!< [9:8]reserve */ + uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */ + uint32_t rsv11_12 : 2; /*!< [12:11]reserve */ + uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */ + uint32_t rsv14_23 : 10; /*!< [23:14]reserve */ + uint32_t CpuIsoEn : 1; /*!< [24]make NP isolated at PDS Sleep state */ + uint32_t rsv25_26 : 2; /*!< [26:25]reserve */ + uint32_t WbIsoEn : 1; /*!< [27]make WB isolated at PDS Sleep state */ + uint32_t rsv28_29 : 2; /*!< [29:28]reserve */ + uint32_t MiscIsoEn : 1; /*!< [30]make misc isolated at PDS Sleep state */ + uint32_t rsv31 : 1; /*!< [31]reserve */ +} PDS_CTL3_Type; + +/** + * @brief PDS default level configuration type definition + */ +typedef struct +{ + PDS_CTL_Type pdsCtl; /*!< PDS_CTL configuration */ + PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */ + PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */ + PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */ +} PDS_DEFAULT_LV_CFG_Type; + +/** + * @brief PDS PLL status type definition + */ +typedef enum { + PDS_PLL_STS_OFF = 0, /*!< 2'b00 */ + PDS_PLL_STS_SFREG = 1, /*!< 2'b01 */ + PDS_PLL_STS_PU = 2, /*!< 2'b10 */ + PDS_PLL_STS_RDY = 3, /*!< 2'b11 */ +} PDS_PLL_STS_Type; + +/** + * @brief PDS RF status type definition + */ +typedef enum { + PDS_RF_STS_OFF = 0, /*!< 4'b0000 */ + PDS_RF_STS_PU_MBG = 1, /*!< 4'b0001 */ + PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */ + PDS_RF_STS_PU_SFREG = 7, /*!< 4'b0111 */ + PDS_RF_STS_WB_EN_AON = 15, /*!< 4'b1111 */ +} PDS_RF_STS_Type; + +/** + * @brief PDS status type definition + */ +typedef enum { + PDS_STS_IDLE = 0, /*!< 4'b0000 */ + PDS_STS_ECG = 8, /*!< 4'b1000 */ + PDS_STS_ERST = 12, /*!< 4'b1100 */ + PDS_STS_EISO = 15, /*!< 4'b1111 */ + PDS_STS_POFF = 7, /*!< 4'b0111 */ + PDS_STS_PRE_BGON = 3, /*!< 4'b0011 */ + PDS_STS_PRE_BGON1 = 1, /*!< 4'b0001 */ + PDS_STS_BGON = 5, /*!< 4'b0101 */ + PDS_STS_CLK_SW_32M = 4, /*!< 4'b0100 */ + PDS_STS_PON_DCDC = 6, /*!< 4'b0110 */ + PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */ + PDS_STS_PON = 10, /*!< 4'b1010 */ + PDS_STS_DISO = 2, /*!< 4'b0010 */ + PDS_STS_DCG = 13, /*!< 4'b1101 */ + PDS_STS_DRST = 11, /*!< 4'b1011 */ + PDS_STS_WAIT_EFUSE = 9, /*!< 4'b1001 */ +} PDS_STS_Type; + +/** + * @brief PDS RAM configuration type definition + */ +typedef struct +{ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET : 1; /*!< [0] 0~16KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET : 1; /*!< [1] 16~32KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET : 1; /*!< [2] 32~48KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET : 1; /*!< [3] 48~64KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_SLP : 1; /*!< [4] 0~16KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_SLP : 1; /*!< [5] 16~32KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_SLP : 1; /*!< [6] 32~48KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_SLP : 1; /*!< [7] 48~64KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_RSV : 24; /*!< [31:8]reserve */ +} PDS_RAM_CFG_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + PDS_PLL_XTAL_NONE, /*!< XTAL is none */ + PDS_PLL_XTAL_24M, /*!< XTAL is 24M */ + PDS_PLL_XTAL_32M, /*!< XTAL is 32M */ + PDS_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */ + PDS_PLL_XTAL_40M, /*!< XTAL is 40M */ + PDS_PLL_XTAL_26M, /*!< XTAL is 26M */ + PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ +} PDS_PLL_XTAL_Type; + +/** + * @brief PLL output clock type definition + */ +typedef enum { + PDS_PLL_CLK_480M, /*!< PLL output clock:480M */ + PDS_PLL_CLK_240M, /*!< PLL output clock:240M */ + PDS_PLL_CLK_192M, /*!< PLL output clock:192M */ + PDS_PLL_CLK_160M, /*!< PLL output clock:160M */ + PDS_PLL_CLK_120M, /*!< PLL output clock:120M */ + PDS_PLL_CLK_96M, /*!< PLL output clock:96M */ + PDS_PLL_CLK_80M, /*!< PLL output clock:80M */ + PDS_PLL_CLK_48M, /*!< PLL output clock:48M */ + PDS_PLL_CLK_32M, /*!< PLL output clock:32M */ +} PDS_PLL_CLK_Type; + +/** + * @brief PDS level 0/1/2/3 mode HBN GPIO interrupt trigger type definition + */ +typedef enum { + PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync falling edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync low level trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync high level trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async falling edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async rising edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async low level trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async high level trigger */ +} PDS_AON_GPIO_INT_Trigger_Type; + +/** + * @brief PDS APP configuration type definition + */ +typedef struct +{ + uint8_t pdsLevel; /*!< PDS level */ + uint8_t turnOffRF; /*!< Wheather turn off RF */ + uint8_t useXtal32k; /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */ + uint8_t pdsAonGpioWakeupSrc; /*!< PDS level 0/1/2/3 mode always on GPIO Wakeup source(HBN wakeup pin) */ + PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0/1/2/3 mode always on GPIO Triger type(HBN wakeup pin) */ + uint8_t powerDownFlash; /*!< Whether power down flash */ + uint8_t turnOffFlashPad; /*!< Whether turn off embedded flash pad */ + uint8_t ocramRetetion; /*!< Whether OCRAM Retention */ + uint8_t turnoffPLL; /*!< Whether trun off PLL */ + uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ + uint8_t flashContRead; /*!< Whether enable flash continue read */ + uint32_t sleepTime; /*!< PDS sleep time */ + SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ + void (*preCbFun)(void); /*!< Pre callback function */ + void (*postCbFun)(void); /*!< Post callback function */ +} PDS_APP_CFG_Type; + +/*@} end of group PDS_Public_Types */ + +/** @defgroup PDS_Public_Constants + * @{ + */ + +/** @defgroup PDS_LDO_LEVEL_TYPE + * @{ + */ +#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \ + ((type) == PDS_LDO_LEVEL_0P65V) || \ + ((type) == PDS_LDO_LEVEL_0P70V) || \ + ((type) == PDS_LDO_LEVEL_0P75V) || \ + ((type) == PDS_LDO_LEVEL_0P80V) || \ + ((type) == PDS_LDO_LEVEL_0P85V) || \ + ((type) == PDS_LDO_LEVEL_0P90V) || \ + ((type) == PDS_LDO_LEVEL_0P95V) || \ + ((type) == PDS_LDO_LEVEL_1P00V) || \ + ((type) == PDS_LDO_LEVEL_1P05V) || \ + ((type) == PDS_LDO_LEVEL_1P10V) || \ + ((type) == PDS_LDO_LEVEL_1P15V) || \ + ((type) == PDS_LDO_LEVEL_1P20V) || \ + ((type) == PDS_LDO_LEVEL_1P25V) || \ + ((type) == PDS_LDO_LEVEL_1P30V) || \ + ((type) == PDS_LDO_LEVEL_1P35V)) + +/** @defgroup PDS_INT_TYPE + * @{ + */ +#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) || \ + ((type) == PDS_INT_HBN_GPIO_IRRX_BLE_WIFI) || \ + ((type) == PDS_INT_RF_DONE) || \ + ((type) == PDS_INT_PLL_DONE) || \ + ((type) == PDS_INT_MAX)) + +/** @defgroup PDS_PLL_STS_TYPE + * @{ + */ +#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) || \ + ((type) == PDS_PLL_STS_SFREG) || \ + ((type) == PDS_PLL_STS_PU) || \ + ((type) == PDS_PLL_STS_RDY)) + +/** @defgroup PDS_RF_STS_TYPE + * @{ + */ +#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) || \ + ((type) == PDS_RF_STS_PU_MBG) || \ + ((type) == PDS_RF_STS_PU_LDO15RF) || \ + ((type) == PDS_RF_STS_PU_SFREG) || \ + ((type) == PDS_RF_STS_WB_EN_AON)) + +/** @defgroup PDS_STS_TYPE + * @{ + */ +#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) || \ + ((type) == PDS_STS_ECG) || \ + ((type) == PDS_STS_ERST) || \ + ((type) == PDS_STS_EISO) || \ + ((type) == PDS_STS_POFF) || \ + ((type) == PDS_STS_PRE_BGON) || \ + ((type) == PDS_STS_PRE_BGON1) || \ + ((type) == PDS_STS_BGON) || \ + ((type) == PDS_STS_CLK_SW_32M) || \ + ((type) == PDS_STS_PON_DCDC) || \ + ((type) == PDS_STS_PON_LDO11_MISC) || \ + ((type) == PDS_STS_PON) || \ + ((type) == PDS_STS_DISO) || \ + ((type) == PDS_STS_DCG) || \ + ((type) == PDS_STS_DRST) || \ + ((type) == PDS_STS_WAIT_EFUSE)) + +/** @defgroup PDS_PLL_XTAL_TYPE + * @{ + */ +#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \ + ((type) == PDS_PLL_XTAL_24M) || \ + ((type) == PDS_PLL_XTAL_32M) || \ + ((type) == PDS_PLL_XTAL_38P4M) || \ + ((type) == PDS_PLL_XTAL_40M) || \ + ((type) == PDS_PLL_XTAL_26M) || \ + ((type) == PDS_PLL_XTAL_RC32M)) + +/** @defgroup PDS_PLL_CLK_TYPE + * @{ + */ +#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \ + ((type) == PDS_PLL_CLK_240M) || \ + ((type) == PDS_PLL_CLK_192M) || \ + ((type) == PDS_PLL_CLK_160M) || \ + ((type) == PDS_PLL_CLK_120M) || \ + ((type) == PDS_PLL_CLK_96M) || \ + ((type) == PDS_PLL_CLK_80M) || \ + ((type) == PDS_PLL_CLK_48M) || \ + ((type) == PDS_PLL_CLK_32M)) + +/** @defgroup PDS_AON_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + +/*@} end of group PDS_Public_Constants */ + +/** @defgroup PDS_Public_Macros + * @{ + */ +#define PDS_LDO_MIN_PU_CNT (25) /* LDO need 25 cycles to power up */ +#define PDS_WARMUP_LATENCY_CNT (38) /* LDO hw warmup compensation latency cycles */ +#define PDS_FORCE_PWR_OFF_OFFSET (0) +#define PDS_FORCE_ISO_EN_OFFSET (4) +#define PDS_FORCE_PDS_RST_OFFSET (8) +#define PDS_FORCE_MEM_STBY_OFFSET (12) +#define PDS_FORCE_GATE_CLK_OFFSET (16) +#define PDS_INT_MASK_BIT_OFFSET (8) +#define PDS_AON_WAKEUP_GPIO_NONE (0x00) +#define PDS_AON_WAKEUP_GPIO_7 (0x01) +#define PDS_AON_WAKEUP_GPIO_8 (0x02) +#define PDS_AON_WAKEUP_GPIO_ALL (0x03) + +/*@} end of group PDS_Public_Macros */ + +/** @defgroup PDS_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void PDS_WAKEUP_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type PDS_Reset(void); +BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt); +BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3); +BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg); +/*----------*/ +BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, + PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt); +/*----------*/ +BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask); +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType); +BL_Err_Type PDS_IntClear(void); +PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void); +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void); +PDS_STS_Type PDS_Get_PdsStstus(void); +BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void); +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type PDS_Trim_RC32M(void); +BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void); +BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void); +BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType); +BL_Err_Type PDS_Fix_Xtal_Settig(void); +BL_Err_Type PDS_Enable_PLL_All_Clks(void); +BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk); +BL_Err_Type PDS_Disable_PLL_All_Clks(void); +BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk); +BL_Err_Type PDS_Power_Off_PLL(void); +/*----------*/; + +/*@} end of group PDS_Public_Functions */ + +/*@} end of group PDS */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_PDS_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_pwm.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..620dd68941ba7a49b74e6ea15cc8bcc03c404b0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_pwm.h @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file bl602_pwm.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_PWM_H__ +#define __BL602_PWM_H__ + +#include "pwm_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PWM + * @{ + */ + +/** @defgroup PWM_Public_Types + * @{ + */ + +/** + * @brief PWM No. type definition + */ +typedef enum { + PWM_CH0 = 0, /*!< PWM Channel 0 define */ + PWM_CH1, /*!< PWM Channel 1 define */ + PWM_CH2, /*!< PWM Channel 2 define */ + PWM_CH3, /*!< PWM Channel 3 define */ + PWM_CH4, /*!< PWM Channel 4 define */ + PWM_CH_MAX, /*!< */ +} PWM_CH_ID_Type; + +/** + * @brief PWM Clock definition + */ +typedef enum { + PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */ + PWM_CLK_BCLK, /*!< PWM Clock source :Bus CLK */ + PWM_CLK_32K, /*!< PWM Clock source :32K CLK */ +} PWM_Clk_Type; + +/** + * @brief PWM Stop Mode definition + */ +typedef enum { + PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */ + PWM_STOP_GRACEFUL, /*!< PWM stop graceful select define */ +} PWM_Stop_Mode_Type; + +/** + * @brief PWM mode type def + */ +typedef enum { + PWM_POL_NORMAL = 0, /*!< PWM normal polarity mode define */ + PWM_POL_INVERT, /*!< PWM invert polarity mode define */ +} PWM_Polarity_Type; + +/** + * @brief PWM interrupt type def + */ +typedef enum { + PWM_INT_PULSE_CNT = 0, /*!< PWM Pulse count interrupt define */ + PWM_INT_ALL, /*!< */ +} PWM_INT_Type; + +/** + * @brief PWM configuration structure type definition + */ +typedef struct +{ + PWM_CH_ID_Type ch; /*!< PWM channel */ + PWM_Clk_Type clk; /*!< PWM Clock */ + PWM_Stop_Mode_Type stopMode; /*!< PWM Stop Mode */ + PWM_Polarity_Type pol; /*!< PWM mode type */ + uint16_t clkDiv; /*!< PWM clkDiv num */ + uint16_t period; /*!< PWM period set */ + uint16_t threshold1; /*!< PWM threshold1 num */ + uint16_t threshold2; /*!< PWM threshold2 num */ + uint16_t intPulseCnt; /*!< PWM interrupt pulse count */ +} PWM_CH_CFG_Type; + +/*@} end of group PWM_Public_Types */ + +/** @defgroup PWM_Public_Constants + * @{ + */ + +/** @defgroup PWM_CH_ID_TYPE + * @{ + */ +#define IS_PWM_CH_ID_TYPE(type) (((type) == PWM_CH0) || \ + ((type) == PWM_CH1) || \ + ((type) == PWM_CH2) || \ + ((type) == PWM_CH3) || \ + ((type) == PWM_CH4) || \ + ((type) == PWM_CH_MAX)) + +/** @defgroup PWM_CLK_TYPE + * @{ + */ +#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK) || \ + ((type) == PWM_CLK_BCLK) || \ + ((type) == PWM_CLK_32K)) + +/** @defgroup PWM_STOP_MODE_TYPE + * @{ + */ +#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT) || \ + ((type) == PWM_STOP_GRACEFUL)) + +/** @defgroup PWM_POLARITY_TYPE + * @{ + */ +#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_NORMAL) || \ + ((type) == PWM_POL_INVERT)) + +/** @defgroup PWM_INT_TYPE + * @{ + */ +#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_PULSE_CNT) || \ + ((type) == PWM_INT_ALL)) + +/*@} end of group PWM_Public_Constants */ + +/** @defgroup PWM_Public_Macros + * @{ + */ +#define IS_PWM_CH(CH) ((CH) < PWM_CH_MAX) + +/*@} end of group PWM_Public_Macros */ + +/** @defgroup PWM_Public_Functions + * @{ + */ + +/** + * @brief PWM Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void PWM_IRQHandler(void); +#endif +BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg); +void PWM_Channel_Update(PWM_CH_ID_Type ch, uint16_t period, uint16_t threshold1, uint16_t threshold2); +void PWM_Channel_Set_Div(PWM_CH_ID_Type ch, uint16_t div); +void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch, uint16_t threshold1); +void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch, uint16_t threshold2); +void PWM_Channel_Set_Period(PWM_CH_ID_Type ch, uint16_t period); +void PWM_Channel_Get(PWM_CH_ID_Type ch, uint16_t *period, uint16_t *threshold1, uint16_t *threshold2); +void PWM_IntMask(PWM_CH_ID_Type ch, PWM_INT_Type intType, BL_Mask_Type intMask); +void PWM_Channel_Enable(PWM_CH_ID_Type ch); +void PWM_Channel_Disable(PWM_CH_ID_Type ch); +void PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable); +void PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value); +void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun); +BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle); + +/*@} end of group PWM_Public_Functions */ + +/*@} end of group PWM */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_PWM_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_romdriver.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_romdriver.h new file mode 100644 index 0000000000000000000000000000000000000000..440ee27c71f3b44c6595595da02700bdc25e9fb2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_romdriver.h @@ -0,0 +1,807 @@ +/** + ****************************************************************************** + * @file bl602_romdriver.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_ROMDRIVER_H__ +#define __BL602_ROMDRIVER_H__ + +#include "bl602_common.h" +#include "bl602_aon.h" +#include "bl602_glb.h" +#include "bl602_hbn.h" +#include "bl602_xip_sflash.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" +#include "bl602_sec_eng.h" +#include "softcrc.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ROMDRIVER + * @{ + */ + +/** @defgroup ROMDRIVER_Public_Types + * @{ + */ + +#define ROMAPI_INDEX_SECT_SIZE (0x800) +#define ROMAPI_INDEX_MAX (ROMAPI_INDEX_SECT_SIZE / 4 - 1) + +typedef enum { + ROM_API_INDEX_VERSION = 0, + ROM_API_INDEX_RSVD_0, + ROM_API_INDEX_RSVD_1, + ROM_API_INDEX_RSVD_LAST, + + ROM_API_INDEX_AON_Power_On_MBG, + ROM_API_INDEX_AON_Power_Off_MBG, + ROM_API_INDEX_AON_Power_On_XTAL, + ROM_API_INDEX_AON_Set_Xtal_CapCode, + ROM_API_INDEX_AON_Get_Xtal_CapCode, + ROM_API_INDEX_AON_Power_Off_XTAL, + ROM_API_INDEX_AON_Power_On_BG, + ROM_API_INDEX_AON_Power_Off_BG, + ROM_API_INDEX_AON_Power_On_LDO11_SOC, + ROM_API_INDEX_AON_Power_Off_LDO11_SOC, + ROM_API_INDEX_AON_Power_On_LDO15_RF, + ROM_API_INDEX_AON_Power_Off_LDO15_RF, + ROM_API_INDEX_AON_Power_On_SFReg, + ROM_API_INDEX_AON_Power_Off_SFReg, + ROM_API_INDEX_AON_LowPower_Enter_PDS0, + ROM_API_INDEX_AON_LowPower_Exit_PDS0, + + ROM_API_INDEX_ASM_Delay_Us, + + ROM_API_INDEX_BL602_Delay_US, + ROM_API_INDEX_BL602_Delay_MS, + ROM_API_INDEX_BL602_MemCpy, + ROM_API_INDEX_BL602_MemCpy4, + ROM_API_INDEX_BL602_MemCpy_Fast, + ROM_API_INDEX_BL602_MemSet, + ROM_API_INDEX_BL602_MemSet4, + ROM_API_INDEX_BL602_MemCmp, + + ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0, + ROM_API_INDEX_EF_Ctrl_Program_Efuse_0, + ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0, + ROM_API_INDEX_EF_Ctrl_Busy, + ROM_API_INDEX_EF_Ctrl_AutoLoad_Done, + ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity, + ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim, + ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim, + ROM_API_INDEX_EF_Ctrl_Clear, + + ROM_API_INDEX_GLB_Get_Root_CLK_Sel, + ROM_API_INDEX_GLB_Set_System_CLK_Div, + ROM_API_INDEX_GLB_Get_BCLK_Div, + ROM_API_INDEX_GLB_Get_HCLK_Div, + + ROM_API_INDEX_Update_SystemCoreClockWith_XTAL, + + ROM_API_INDEX_GLB_Set_System_CLK, + + ROM_API_INDEX_System_Core_Clock_Update_From_RC32M, + + ROM_API_INDEX_GLB_Set_SF_CLK, + ROM_API_INDEX_GLB_Set_PKA_CLK_Sel, + ROM_API_INDEX_GLB_SW_System_Reset, + ROM_API_INDEX_GLB_SW_CPU_Reset, + ROM_API_INDEX_GLB_SW_POR_Reset, + ROM_API_INDEX_GLB_Select_Internal_Flash, + ROM_API_INDEX_GLB_Select_External_Flash, + ROM_API_INDEX_GLB_Deswap_Flash_Pin, + ROM_API_INDEX_GLB_Swap_Flash_Pin, + ROM_API_INDEX_GLB_GPIO_Init, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable, + ROM_API_INDEX_GLB_GPIO_Set_HZ, + ROM_API_INDEX_GLB_GPIO_Get_Fun, + + ROM_API_INDEX_HBN_Mode_Enter, + ROM_API_INDEX_HBN_Power_Down_Flash, + ROM_API_INDEX_HBN_Enable, + ROM_API_INDEX_HBN_Reset, + ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout, + ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout, + ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout, + ROM_API_INDEX_HBN_32K_Sel, + ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel, + ROM_API_INDEX_HBN_Power_On_Xtal_32K, + ROM_API_INDEX_HBN_Power_Off_Xtal_32K, + ROM_API_INDEX_HBN_Power_On_RC32K, + ROM_API_INDEX_HBN_Power_Off_RC32K, + ROM_API_INDEX_HBN_Trim_RC32K, + ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg, + ROM_API_INDEX_HBN_Pin_WakeUp_Mask, + ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg, + ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup, + + ROM_API_INDEX_L1C_Set_Wrap, + ROM_API_INDEX_L1C_Set_Way_Disable, + ROM_API_INDEX_L1C_IROM_2T_Access_Set, + + ROM_API_INDEX_PDS_Reset, + ROM_API_INDEX_PDS_Enable, + ROM_API_INDEX_PDS_Force_Config, + ROM_API_INDEX_PDS_RAM_Config, + ROM_API_INDEX_PDS_Default_Level_Config, + ROM_API_INDEX_PDS_Trim_RC32M, + ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref, + ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref, + ROM_API_INDEX_PDS_Power_On_PLL, + ROM_API_INDEX_PDS_Enable_PLL_All_Clks, + ROM_API_INDEX_PDS_Disable_PLL_All_Clks, + ROM_API_INDEX_PDS_Enable_PLL_Clk, + ROM_API_INDEX_PDS_Disable_PLL_Clk, + ROM_API_INDEX_PDS_Power_Off_PLL, + + ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring, + ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring, + + ROM_API_INDEX_SFlash_Init, + ROM_API_INDEX_SFlash_SetSPIMode, + ROM_API_INDEX_SFlash_Read_Reg, + ROM_API_INDEX_SFlash_Write_Reg, + ROM_API_INDEX_SFlash_Busy, + ROM_API_INDEX_SFlash_Write_Enable, + ROM_API_INDEX_SFlash_Qspi_Enable, + ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable, + ROM_API_INDEX_SFlash_Chip_Erase, + ROM_API_INDEX_SFlash_Sector_Erase, + ROM_API_INDEX_SFlash_Blk32_Erase, + ROM_API_INDEX_SFlash_Blk64_Erase, + ROM_API_INDEX_SFlash_Erase, + ROM_API_INDEX_SFlash_Program, + ROM_API_INDEX_SFlash_GetUniqueId, + ROM_API_INDEX_SFlash_GetJedecId, + ROM_API_INDEX_SFlash_GetDeviceId, + ROM_API_INDEX_SFlash_Powerdown, + ROM_API_INDEX_SFlash_Releae_Powerdown, + ROM_API_INDEX_SFlash_SetBurstWrap, + ROM_API_INDEX_SFlash_DisableBurstWrap, + ROM_API_INDEX_SFlash_Software_Reset, + ROM_API_INDEX_SFlash_Reset_Continue_Read, + ROM_API_INDEX_SFlash_Set_IDbus_Cfg, + ROM_API_INDEX_SFlash_IDbus_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Enable_Set, + ROM_API_INDEX_SFlash_Cache_Flush, + ROM_API_INDEX_SFlash_Cache_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Hit_Count_Get, + ROM_API_INDEX_SFlash_Cache_Miss_Count_Get, + ROM_API_INDEX_SFlash_Cache_Read_Disable, + ROM_API_INDEX_SFlash_Read, + ROM_API_INDEX_SFlash_Read_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Write_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Restore_From_Powerdown, + + ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun, + ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock, + ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Flash_Identify, + ROM_API_INDEX_SF_Ctrl_Enable, + ROM_API_INDEX_SF_Ctrl_Select_Pad, + ROM_API_INDEX_SF_Ctrl_Set_Owner, + ROM_API_INDEX_SF_Ctrl_Disable, + ROM_API_INDEX_SF_Ctrl_AES_Enable_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable_LE, + ROM_API_INDEX_SF_Ctrl_AES_Set_Region, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable, + ROM_API_INDEX_SF_Ctrl_AES_Disable, + ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Select_Clock, + ROM_API_INDEX_SF_Ctrl_SendCmd, + ROM_API_INDEX_SF_Ctrl_Icache_Set, + ROM_API_INDEX_SF_Ctrl_Icache2_Set, + ROM_API_INDEX_SF_Ctrl_GetBusyState, + ROM_API_INDEX_SF_Ctrl_Is_AES_Enable, + ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay, + ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay, + + ROM_API_INDEX_XIP_SFlash_State_Save, + ROM_API_INDEX_XIP_SFlash_State_Restore, + ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Write_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_With_Lock, + ROM_API_INDEX_XIP_SFlash_Write_With_Lock, + ROM_API_INDEX_XIP_SFlash_Erase_With_Lock, + ROM_API_INDEX_XIP_SFlash_Opt_Enter, + ROM_API_INDEX_XIP_SFlash_Opt_Exit, + + ROM_API_INDEX_BFLB_Soft_CRC32, + + ROM_API_INDEX_FUNC_EMPTY_START, + + ROM_API_INDEX_FUNC_EMPTY_END = ROMAPI_INDEX_MAX + +} ROM_API_INDEX_e; + +/*@} end of group ROMDRIVER_Public_Types */ + +/** @defgroup ROMDRIVER_Public_Constants + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Constants */ + +/** @defgroup ROMDRIVER_Public_Macros + * @{ + */ + +#define ROM_APITABLE ((uint32_t *)0x21010800) + +#define RomDriver_AON_Power_On_MBG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG]) + +#define RomDriver_AON_Power_Off_MBG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG]) + +#define RomDriver_AON_Power_On_XTAL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL]) + +#define RomDriver_AON_Set_Xtal_CapCode \ + ((BL_Err_Type(*)(uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode]) + +#define RomDriver_AON_Get_Xtal_CapCode \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Get_Xtal_CapCode]) + +#define RomDriver_AON_Power_Off_XTAL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL]) + +#define RomDriver_AON_Power_On_BG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_BG]) + +#define RomDriver_AON_Power_Off_BG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_BG]) + +#define RomDriver_AON_Power_On_LDO11_SOC \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO11_SOC]) + +#define RomDriver_AON_Power_Off_LDO11_SOC \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO11_SOC]) + +#define RomDriver_AON_Power_On_LDO15_RF \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO15_RF]) + +#define RomDriver_AON_Power_Off_LDO15_RF \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO15_RF]) + +#define RomDriver_AON_Power_On_SFReg \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_SFReg]) + +#define RomDriver_AON_Power_Off_SFReg \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_SFReg]) + +#define RomDriver_AON_LowPower_Enter_PDS0 \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Enter_PDS0]) + +#define RomDriver_AON_LowPower_Exit_PDS0 \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Exit_PDS0]) + +#define RomDriver_ASM_Delay_Us \ + ((void (*)(uint32_t core, uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us]) + +#define RomDriver_BL602_Delay_US \ + ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_US]) + +#define RomDriver_BL602_Delay_MS \ + ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_MS]) + +#define RomDriver_BL602_MemCpy \ + ((void *(*)(void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy]) + +#define RomDriver_BL602_MemCpy4 \ + ((uint32_t * (*)(uint32_t * dst, const uint32_t *src, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy4]) + +#define RomDriver_BL602_MemCpy_Fast \ + ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy_Fast]) + +#define RomDriver_BL602_MemSet \ + ((void *(*)(void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemSet]) + +#define RomDriver_BL602_MemSet4 \ + ((uint32_t * (*)(uint32_t * dst, const uint32_t val, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL602_MemSet4]) + +#define RomDriver_BL602_MemCmp \ + ((int (*)(const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCmp]) + +#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0]) + +#define RomDriver_EF_Ctrl_Program_Efuse_0 \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0]) + +#define RomDriver_EF_Ctrl_Load_Efuse_R0 \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0]) + +#define RomDriver_EF_Ctrl_Busy \ + ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy]) + +#define RomDriver_EF_Ctrl_AutoLoad_Done \ + ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_AutoLoad_Done]) + +#define RomDriver_EF_Ctrl_Get_Trim_Parity \ + ((uint8_t(*)(uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity]) + +#define RomDriver_EF_Ctrl_Read_RC32M_Trim \ + ((void (*)(Efuse_Ana_RC32M_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim]) + +#define RomDriver_EF_Ctrl_Read_RC32K_Trim \ + ((void (*)(Efuse_Ana_RC32K_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim]) + +#define RomDriver_EF_Ctrl_Clear \ + ((void (*)(uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear]) + +#define RomDriver_GLB_Get_Root_CLK_Sel \ + ((GLB_ROOT_CLK_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel]) + +#define RomDriver_GLB_Set_System_CLK_Div \ + ((BL_Err_Type(*)(uint8_t hclkDiv, uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div]) + +#define RomDriver_GLB_Get_BCLK_Div \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div]) + +#define RomDriver_GLB_Get_HCLK_Div \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div]) + +#define RomDriver_Update_SystemCoreClockWith_XTAL \ + ((BL_Err_Type(*)(GLB_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL]) + +#define RomDriver_GLB_Set_System_CLK \ + ((BL_Err_Type(*)(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK]) + +#define RomDriver_System_Core_Clock_Update_From_RC32M \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M]) + +#define RomDriver_GLB_Set_SF_CLK \ + ((BL_Err_Type(*)(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK]) + +#define RomDriver_GLB_Set_PKA_CLK_Sel \ + ((BL_Err_Type(*)(GLB_PKA_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel]) + +#define RomDriver_GLB_SW_System_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset]) + +#define RomDriver_GLB_SW_CPU_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset]) + +#define RomDriver_GLB_SW_POR_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset]) + +#define RomDriver_GLB_Select_Internal_Flash \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash]) + +#define RomDriver_GLB_Select_External_Flash \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash]) + +#define RomDriver_GLB_Deswap_Flash_Pin \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin]) + +#define RomDriver_GLB_Swap_Flash_Pin \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin]) + +#define RomDriver_GLB_GPIO_Init \ + ((BL_Err_Type(*)(GLB_GPIO_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init]) + +#define RomDriver_GLB_GPIO_OUTPUT_Enable \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable]) + +#define RomDriver_GLB_GPIO_OUTPUT_Disable \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable]) + +#define RomDriver_GLB_GPIO_Set_HZ \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ]) + +#define RomDriver_GLB_GPIO_Get_Fun \ + ((uint8_t(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun]) + +#define RomDriver_HBN_Mode_Enter \ + ((void (*)(HBN_APP_CFG_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter]) + +#define RomDriver_HBN_Power_Down_Flash \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash]) + +#define RomDriver_HBN_Enable \ + ((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable]) + +#define RomDriver_HBN_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset]) + +#define RomDriver_HBN_Set_Ldo11_Aon_Vout \ + ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout]) + +#define RomDriver_HBN_Set_Ldo11_Rt_Vout \ + ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout]) + +#define RomDriver_HBN_Set_Ldo11_Soc_Vout \ + ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout]) + +#define RomDriver_HBN_32K_Sel \ + ((BL_Err_Type(*)(HBN_32K_CLK_Type clkType))ROM_APITABLE[ROM_API_INDEX_HBN_32K_Sel]) + +#define RomDriver_HBN_Set_ROOT_CLK_Sel \ + ((BL_Err_Type(*)(HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel]) + +#define RomDriver_HBN_Power_On_Xtal_32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_Xtal_32K]) + +#define RomDriver_HBN_Power_Off_Xtal_32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_Xtal_32K]) + +#define RomDriver_HBN_Power_On_RC32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_RC32K]) + +#define RomDriver_HBN_Power_Off_RC32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_RC32K]) + +#define RomDriver_HBN_Trim_RC32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K]) + +#define RomDriver_HBN_Hw_Pu_Pd_Cfg \ + ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg]) + +#define RomDriver_HBN_Pin_WakeUp_Mask \ + ((BL_Err_Type(*)(uint8_t maskVal))ROM_APITABLE[ROM_API_INDEX_HBN_Pin_WakeUp_Mask]) + +#define RomDriver_HBN_GPIO7_Dbg_Pull_Cfg \ + ((BL_Err_Type(*)(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg]) + +#define RomDriver_HBN_Set_Embedded_Flash_Pullup \ + ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup]) + +#define RomDriver_L1C_Set_Wrap \ + ((BL_Err_Type(*)(BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap]) + +#define RomDriver_L1C_Set_Way_Disable \ + ((BL_Err_Type(*)(uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable]) + +#define RomDriver_L1C_IROM_2T_Access_Set \ + ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set]) + +#define RomDriver_PDS_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset]) + +#define RomDriver_PDS_Enable \ + ((BL_Err_Type(*)(PDS_CTL_Type * cfg, PDS_CTL4_Type * cfg4, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Enable]) + +#define RomDriver_PDS_Force_Config \ + ((BL_Err_Type(*)(PDS_CTL2_Type * cfg2, PDS_CTL3_Type * cfg3)) ROM_APITABLE[ROM_API_INDEX_PDS_Force_Config]) + +#define RomDriver_PDS_RAM_Config \ + ((BL_Err_Type(*)(PDS_RAM_CFG_Type * ramCfg)) ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config]) + +#define RomDriver_PDS_Default_Level_Config \ + ((BL_Err_Type(*)(PDS_DEFAULT_LV_CFG_Type * defaultLvCfg, PDS_RAM_CFG_Type * ramCfg, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config]) + +#define RomDriver_PDS_Trim_RC32M \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M]) + +#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref]) + +#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref]) + +#define RomDriver_PDS_Power_On_PLL \ + ((BL_Err_Type(*)(PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL]) + +#define RomDriver_PDS_Enable_PLL_All_Clks \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks]) + +#define RomDriver_PDS_Disable_PLL_All_Clks \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks]) + +#define RomDriver_PDS_Enable_PLL_Clk \ + ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk]) + +#define RomDriver_PDS_Disable_PLL_Clk \ + ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk]) + +#define RomDriver_PDS_Power_Off_PLL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL]) + +#define RomDriver_SEC_Eng_Turn_On_Sec_Ring \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring]) + +#define RomDriver_SEC_Eng_Turn_Off_Sec_Ring \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring]) + +#define RomDriver_SFlash_Init \ + ((void (*)(const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) + +#define RomDriver_SFlash_SetSPIMode \ + ((BL_Err_Type(*)(SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) + +#define RomDriver_SFlash_Read_Reg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) + +#define RomDriver_SFlash_Write_Reg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) + +#define RomDriver_SFlash_Busy \ + ((BL_Sts_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) + +#define RomDriver_SFlash_Write_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) + +#define RomDriver_SFlash_Qspi_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) + +#define RomDriver_SFlash_Volatile_Reg_Write_Enable \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) + +#define RomDriver_SFlash_Chip_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) + +#define RomDriver_SFlash_Sector_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) + +#define RomDriver_SFlash_Blk32_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) + +#define RomDriver_SFlash_Blk64_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) + +#define RomDriver_SFlash_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) + +#define RomDriver_SFlash_Program \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) + +#define RomDriver_SFlash_GetUniqueId \ + ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId]) + +#define RomDriver_SFlash_GetJedecId \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) + +#define RomDriver_SFlash_GetDeviceId \ + ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) + +#define RomDriver_SFlash_Powerdown \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown]) + +#define RomDriver_SFlash_Releae_Powerdown \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) + +#define RomDriver_SFlash_SetBurstWrap \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) + +#define RomDriver_SFlash_DisableBurstWrap \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) + +#define RomDriver_SFlash_Software_Reset \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) + +#define RomDriver_SFlash_Reset_Continue_Read \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) + +#define RomDriver_SFlash_Set_IDbus_Cfg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) + +#define RomDriver_SFlash_IDbus_Read_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) + +#define RomDriver_SFlash_Cache_Enable_Set \ + ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set]) + +#define RomDriver_SFlash_Cache_Flush \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush]) + +#define RomDriver_SFlash_Cache_Read_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) + +#define RomDriver_SFlash_Cache_Hit_Count_Get \ + ((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Hit_Count_Get]) + +#define RomDriver_SFlash_Cache_Miss_Count_Get \ + ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Miss_Count_Get]) + +#define RomDriver_SFlash_Cache_Read_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable]) + +#define RomDriver_SFlash_Read \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) + +#define RomDriver_SFlash_Read_Reg_With_Cmd \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) + +#define RomDriver_SFlash_Write_Reg_With_Cmd \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) + +#define RomDriver_SFlash_Restore_From_Powerdown \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) + +#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \ + ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Init_Internal_Flash_Gpio \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \ + ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Restore_GPIO17_Fun \ + ((void (*)(uint8_t fun))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun]) + +#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \ + ((BL_Err_Type(*)(uint32_t flashID, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) + +#define RomDriver_SF_Cfg_Init_Flash_Gpio \ + ((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Flash_Identify \ + ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) + +#define RomDriver_SF_Ctrl_Enable \ + ((void (*)(const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) + +#define RomDriver_SF_Ctrl_Select_Pad \ + ((void (*)(SF_Ctrl_Pad_Sel sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) + +#define RomDriver_SF_Ctrl_Set_Owner \ + ((void (*)(SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) + +#define RomDriver_SF_Ctrl_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable]) + +#define RomDriver_SF_Ctrl_AES_Enable_BE \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE]) + +#define RomDriver_SF_Ctrl_AES_Enable_LE \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE]) + +#define RomDriver_SF_Ctrl_AES_Set_Region \ + ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region]) + +#define RomDriver_SF_Ctrl_AES_Set_Key \ + ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) + +#define RomDriver_SF_Ctrl_AES_Set_Key_BE \ + ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) + +#define RomDriver_SF_Ctrl_AES_Set_IV \ + ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV]) + +#define RomDriver_SF_Ctrl_AES_Set_IV_BE \ + ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE]) + +#define RomDriver_SF_Ctrl_AES_Enable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable]) + +#define RomDriver_SF_Ctrl_AES_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable]) + +#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \ + ((void (*)(uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset]) + +#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \ + ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) + +#define RomDriver_SF_Ctrl_Select_Clock \ + ((void (*)(SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock]) + +#define RomDriver_SF_Ctrl_SendCmd \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) + +#define RomDriver_SF_Ctrl_Icache_Set \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set]) + +#define RomDriver_SF_Ctrl_Icache2_Set \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set]) + +#define RomDriver_SF_Ctrl_GetBusyState \ + ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) + +#define RomDriver_SF_Ctrl_Is_AES_Enable \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]) + +#define RomDriver_SF_Ctrl_Get_Clock_Delay \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]) + +#define RomDriver_SF_Ctrl_Set_Clock_Delay \ + ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]) + +#define RomDriver_XIP_SFlash_State_Save \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) + +#define RomDriver_XIP_SFlash_State_Restore \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) + +#define RomDriver_XIP_SFlash_Erase_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) + +#define RomDriver_XIP_SFlash_Write_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \ + ((BL_Err_Type(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_With_Lock \ + ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * dst, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock]) + +#define RomDriver_XIP_SFlash_Write_With_Lock \ + ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * src, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock]) + +#define RomDriver_XIP_SFlash_Erase_With_Lock \ + ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock]) + +#define RomDriver_XIP_SFlash_Opt_Enter \ + ((void (*)(uint8_t * aesEnable)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter]) + +#define RomDriver_XIP_SFlash_Opt_Exit \ + ((void (*)(uint8_t aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Exit]) + +#define RomDriver_BFLB_Soft_CRC32 \ + ((uint32_t(*)(void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32]) + +/*@} end of group ROMDRIVER_Public_Macros */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_ROMDRIVER_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sdu.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sdu.h new file mode 100644 index 0000000000000000000000000000000000000000..25fb979ae7566791709416bc720ba787d0ca1b70 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sdu.h @@ -0,0 +1,184 @@ +#ifndef __BL602_SDU_H__ +#define __BL602_SDU_H__ + +#include "bl602.h" +#include "bl602_common.h" + +#define NUM_FUNC 1 +#define FUNC_WIFI 0 + +// SDIO I/O Enable +#define BL_SDIO_IO_ENABLE SDU_BASE + 0x00000002 +//CCCR (Fn0) Registers + +// SDIO Device Sleep +#define BL_SDIO_DEV_SLEEP SDU_BASE + 0x00000092 + +// Start Address of CCR +#define BL_SDIO_CCR_BASE SDU_BASE + 0x00000100 +// Address offset of CCR between two functions +#define BL_SDIO_CCR_FUNC_OFFSET 0x00000100 + +// Address for sdio block size information +#define SDIO_FN1_BLK_SIZE_0 (SDU_BASE + 0x00000028) +#define SDIO_FN1_BLK_SIZE_1 (SDU_BASE + 0x00000029) +#define SDIO_FN1_BLK_SIZE_1_MASK 0x01 + +#define BL_FUNC_SCRATCH_BASE SDU_BASE + 0x00000160 + +typedef struct +{ + uint8_t HostToCardEvent; // 0x100/200 + uint8_t HostIntCause; // 0x101/201 + uint8_t HostIntMask; // 0x102/202 + uint8_t HostIntStatus; // 0x103/203 + uint16_t RdBitMap; // 0x104/204 + uint16_t WrBitMap; // 0x106/206 + uint16_t RdLen[16]; // 0x108/208 + uint8_t HostTransferStatus; // 0x128/228 + uint8_t reserved1[0x130 - 0x128 - 1]; + uint8_t CardToHostEvent; // 0x130/230 + uint8_t reserved2[3]; + uint8_t CardIntMask; // 0x134/234 + uint8_t reserved3[3]; + uint8_t CardIntStatus; // 0x138/238 + uint8_t reserved4[3]; + uint8_t CardIntMode; // 0x13C/23C + uint8_t reserved5[3]; + uint32_t SqReadBase; // 0x140/240 + uint32_t SqWriteBase; // 0x144/244 + uint8_t RdIdx; // 0x148/248 + uint8_t WrIdx; // 0x149/249 + uint8_t DnldQueueWrPtr; // 0x14A/24A + uint8_t UpldQueueWrPtr; // 0x14B/24B + uint8_t DnldQueue[8]; // 0x14C/24C + uint8_t UpldQueue[8]; // 0x154/254 + uint8_t ChipRev; // 0x15C //RO + uint8_t reserved6; // 0x15D //NOT_DEFINE + uint8_t IPRev0; // 0x15E //RO + uint8_t IPRev1; // 0x15F //RO + uint8_t reserved7[4]; // 0x160/260 + uint16_t Scratch2; // 0x164/264 + uint16_t Scratch1; // 0x166/266 + uint8_t Ocr0; // 0x168/268 + uint8_t Ocr1; // 0x169/269 + uint8_t Ocr2; // 0x16A/26A + uint8_t Config; // 0x16B/26B + uint32_t Config2; // 0x16C/26C + uint32_t Debug; // 0x170/270 + uint32_t DmaAddr; // 0x174/274 + uint8_t IoPort[3]; // 0x178/278 +} __attribute__((packed)) HidSdio_RegMap_t, *pHidSdio_RegMap_t; + +// Common I/O Area Registers (CIA) Offset +// +// Bit Def. Host To Card Interrupt Event (Offset 0x100/200) +#define SDIO_HCR_CONFIG_HostPwrUp (1 << 1) + +// Bit Def. Host Transfer Status (Offset 0x128/228) +#define SDIO_CCR_HOST_INT_DnLdReStart (1 << 0) +#define SDIO_CCR_HOST_INT_UpLdReStart (1 << 1) +#define SDIO_CCR_HOST_INT_DnLdCRC_err (1 << 2) + +// Bit Def. Card To Host Interrupt Event (Offset 0x130/230) +#define SDIO_CCR_CS_DnLdRdy (1 << 0) +#define SDIO_CCR_CS_UpLdRdy (1 << 1) +#define SDIO_CCR_CS_ReadCISRdy (1 << 2) +#define SDIO_CCR_CS_IORdy (1 << 3) + +// Bit Def. Card Interrupt Mask (Offset 0x134/234) +#define SDIO_CCR_CIM_DnLdOvr (1 << 0) +#define SDIO_CCR_CIM_UpLdOvr (1 << 1) +#define SDIO_CCR_CIM_Abort (1 << 2) +#define SDIO_CCR_CIM_PwrDn (1 << 3) +#define SDIO_CCR_CIM_PwrUp (1 << 4) + +#define SDIO_CCR_CIM_MASK 0x0007 + +// Bit Def. Card Interrupt Status (Offset 0x138/238) +#define SDIO_CCR_CIC_DnLdOvr (1 << 0) +#define SDIO_CCR_CIC_UpLdOvr (1 << 1) +#define SDIO_CCR_CIC_Abort (1 << 2) +#define SDIO_CCR_CIC_PwrDn (1 << 3) +#define SDIO_CCR_CIC_PwrUp (1 << 4) + +#define SDIO_CCR_CIC_MASK 0x001F + +// Bit Def. Card Interrupt RSR (Offset 0x13C/23C) +#define SDIO_CCR_CIO_DnLdOvr (1 << 0) +#define SDIO_CCR_CIO_UpLdOvr (1 << 1) +#define SDIO_CCR_CIO_Abort (1 << 2) +#define SDIO_CCR_CIO_PwrDn (1 << 3) +#define SDIO_CCR_CIO_PwrUp (1 << 4) +#define SDIO_CCR_CIO_MASK 0x001F + +//Config2 register mask +#define CONFIG2_MSK 0x00000C00 + +//CardIntMode register mask + +#define CARD_INT_MODE_MSK 0x00000003 +#define HOST_INT_MSK 0x00000002 + +//============================================================================= +// PUBLIC MACROS +//============================================================================= + +#define BL_REGS8(x) (*(volatile unsigned char *)(x)) +#define BL_REGS16(x) (*(volatile unsigned short *)(x)) +#define BL_REGS32(x) (*(volatile unsigned long *)(x)) + +#define BL_READ_REGS8(reg, val) ((val) = BL_REGS8(reg)) +#define BL_READ_REGS16(reg, val) ((val) = BL_REGS16(reg)) +#define BL_READ_REGS32(reg, val) ((val) = BL_REGS32(reg)) +#define BL_READ_BYTE(reg, val) ((val) = BL_REGS8(reg)) +#define BL_READ_HWORD(reg, val) ((val) = BL_REGS16(reg)) /*half word; */ +#define BL_READ_WORD(reg, val) ((val) = BL_REGS32(reg)) /*32 bits */ + +#define BL_WRITE_REGS8(reg, val) (BL_REGS8(reg) = (val)) +#define BL_WRITE_REGS16(reg, val) (BL_REGS16(reg) = (val)) +#define BL_WRITE_REGS32(reg, val) (BL_REGS32(reg) = (val)) +#define BL_WRITE_BYTE(reg, val) (BL_REGS8(reg) = (val)) +#define BL_WRITE_HWORD(reg, val) (BL_REGS16(reg) = (val)) /*half word; */ +#define BL_WRITE_WORD(reg, val) (BL_REGS32(reg) = (val)) /*32 bits */ +// Write uint32 to a low 16-bit register and a high 16-bit register +#define WRITE2REGS(lo, hi, u32) \ + BL_WRITE_HWORD(lo, (uint16_t)((u32)&0xffff)); \ + BL_WRITE_HWORD(hi, (uint16_t)(((u32) >> 16) & 0xffff)) + +#define BL_REGS8_SETBITS(reg, val) (BL_REGS8(reg) |= (uint8)(val)) +#define BL_REGS16_SETBITS(reg, val) (BL_REGS16(reg) |= (uint16)(val)) +#define BL_REGS32_SETBITS(reg, val) (BL_REGS32(reg) |= (val)) +#define BL_REGS8_CLRBITS(reg, val) (BL_REGS8(reg) = (uint8)(BL_REGS8(reg) & ~(val))) +#define BL_REGS16_CLRBITS(reg, val) (BL_REGS16(reg) = (uint16)(BL_REGS16(reg) & ~(val))) +#define BL_REGS32_CLRBITS(reg, val) (BL_REGS32(reg) = (BL_REGS32(reg) & ~(val))) + +//============================================================================= +// ENUM TYPE DEFINITION +//============================================================================= + +/******************************************************************/ +/*! + * \enum SDIO_CMD_TYPE + * + *******************************************************************/ +typedef enum { + IOCTL_GET_CONFIG = 0, /*!< Get configuration info */ + + /* HID IOCTLs*/ + IOCTL_HID_GET_BLOCK_SIZE, /*!< Get Block size */ + +} SDIO_CMD_TYPE; + +//============================================================================= +// FUNCTION DECLARATION +//============================================================================= +extern void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value); +extern uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg); + +//============================================================================= +// Variable DECLARATION +//============================================================================= +extern volatile pHidSdio_RegMap_t SdioFuncReg[]; +extern uint8_t flag_mport[]; +#endif /* __BL602_SDU_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sec_dbg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sec_dbg.h new file mode 100644 index 0000000000000000000000000000000000000000..b8843c6bb3e37b2a98702e29e6570a23e214b782 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sec_dbg.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file bl602_sec_dbg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SEC_DBG_H__ +#define __BL602_SEC_DBG_H__ + +#include "sec_dbg_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_DBG + * @{ + */ + +/** @defgroup SEC_DBG_Public_Types + * @{ + */ + +/*@} end of group SEC_DBG_Public_Types */ + +/** @defgroup SEC_DBG_Public_Constants + * @{ + */ + +/*@} end of group SEC_DBG_Public_Constants */ + +/** @defgroup SEC_DBG_Public_Macros + * @{ + */ + +/*@} end of group SEC_DBG_Public_Macros */ + +/** @defgroup SEC_DBG_Public_Functions + * @{ + */ +void Sec_Dbg_Read_Chip_ID(uint8_t id[8]); +void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]); +uint32_t Sec_Dbg_Read_Dbg_Mode(void); +uint32_t Sec_Dbg_Read_Dbg_Enable(void); + +/*@} end of group SEC_DBG_Public_Functions */ + +/*@} end of group SEC_DBG */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SEC_DBG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sec_eng.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sec_eng.h new file mode 100644 index 0000000000000000000000000000000000000000..49f5147be3e2d1224e5c49c060b4973a970c2659 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sec_eng.h @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file bl602_sec_eng.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SEC_ENG_H__ +#define __BL602_SEC_ENG_H__ + +#include "sec_eng_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_ENG + * @{ + */ + +/** @defgroup SEC_ENG_Public_Types + * @{ + */ + +/** + * @brief AES port type definition + */ +typedef enum { + SEC_ENG_AES_ID0, /*!< AES0 port define */ +} SEC_ENG_AES_ID_Type; + +/** + * @brief SHA port type definition + */ +typedef enum { + SEC_ENG_SHA_ID0, /*!< SHA0 port define */ +} SEC_ENG_SHA_ID_Type; + +/** + * @brief SHA type definition + */ +typedef enum { + SEC_ENG_SHA256, /*!< SHA type:SHA256 */ + SEC_ENG_SHA224, /*!< SHA type:SHA224 */ + SEC_ENG_SHA1, /*!< SHA type:SHA1 */ + SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */ +} SEC_ENG_SHA_Type; + +/** + * @brief AES type definition + */ +typedef enum { + SEC_ENG_AES_ECB, /*!< AES mode type:ECB */ + SEC_ENG_AES_CTR, /*!< AES mode type:CTR */ + SEC_ENG_AES_CBC, /*!< AES mode type:CBC */ +} SEC_ENG_AES_Type; + +/** + * @brief AES KEY type definition + */ +typedef enum { + SEC_ENG_AES_KEY_128BITS, /*!< AES KEY type:128 bits */ + SEC_ENG_AES_KEY_256BITS, /*!< AES KEY type:256 bits */ + SEC_ENG_AES_KEY_192BITS, /*!< AES KEY type:192 bits */ + SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */ +} SEC_ENG_AES_Key_Type; + +/** + * @brief AES CTR mode counter type definition + */ +typedef enum { + SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */ + SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */ + SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */ + SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */ +} SEC_ENG_AES_Counter_Type; + +/** + * @brief AES use new or old value type definition + */ +typedef enum { + SEC_ENG_AES_USE_NEW, /*!< Use new value */ + SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */ +} SEC_ENG_AES_ValueUsed_Type; + +/** + * @brief AES KEY source type definition + */ +typedef enum { + SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */ + SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */ +} SEC_ENG_AES_Key_Src_Type; + +/** + * @brief AES KEY source type definition + */ +typedef enum { + SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */ + SEC_ENG_AES_DECRYPTION, /*!< AES decryption */ +} SEC_ENG_AES_EnDec_Type; + +/** + * @brief AES PKA register size type definition + */ +typedef enum { + SEC_ENG_PKA_REG_SIZE_8 = 1, /*!< Register size is 8 Bytes */ + SEC_ENG_PKA_REG_SIZE_16, /*!< Register size is 16 Bytes */ + SEC_ENG_PKA_REG_SIZE_32, /*!< Register size is 32 Bytes */ + SEC_ENG_PKA_REG_SIZE_64, /*!< Register size is 64 Bytes */ + SEC_ENG_PKA_REG_SIZE_96, /*!< Register size is 96 Bytes */ + SEC_ENG_PKA_REG_SIZE_128, /*!< Register size is 128 Bytes */ + SEC_ENG_PKA_REG_SIZE_192, /*!< Register size is 192 Bytes */ + SEC_ENG_PKA_REG_SIZE_256, /*!< Register size is 256 Bytes */ + SEC_ENG_PKA_REG_SIZE_384, /*!< Register size is 384 Bytes */ + SEC_ENG_PKA_REG_SIZE_512, /*!< Register size is 512 Bytes */ +} SEC_ENG_PKA_REG_SIZE_Type; + +/** + * @brief AES PKA register size type definition + */ +typedef enum { + SEC_ENG_PKA_OP_PPSEL, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MOD2N = 0x11, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LDIV2N = 0x12, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LMUL2N = 0x13, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LDIV = 0x14, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LSQR = 0x15, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LMUL = 0x16, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LSUB = 0x17, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LADD = 0x18, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LCMP = 0x19, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MDIV2 = 0x21, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MINV = 0x22, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MEXP = 0x23, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MSQR = 0x24, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MMUL = 0x25, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MREM = 0x26, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MSUB = 0x27, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MADD = 0x28, /*!< PKA operation type */ + SEC_ENG_PKA_OP_RESIZE = 0x31, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MOVDAT = 0x32, /*!< PKA operation type */ + SEC_ENG_PKA_OP_NLIR = 0x33, /*!< PKA operation type */ + SEC_ENG_PKA_OP_SLIR = 0x34, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CLIR = 0x35, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CFLIRI_BUFFER = 0x36, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CTLIRI_PLD = 0x37, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CFLIR_BUFFER = 0x38, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CTLIR_PLD = 0x39, /*!< PKA operation type */ +} SEC_ENG_PKA_OP_Type; + +/** + * @brief Sec Eng Interrupt Type Def + */ +typedef enum { + SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */ + SEC_ENG_INT_AES, /*!< Sec Eng Aes Interrupt Type */ + SEC_ENG_INT_SHA, /*!< Sec Eng Sha Interrupt Type */ + SEC_ENG_INT_PKA, /*!< Sec Eng Pka Interrupt Type */ + SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */ + SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */ + SEC_ENG_INT_ALL, /*!< Sec Eng All Interrupt Types */ +} SEC_ENG_INT_Type; + +/** + * @brief SEC_ENG SHA context + */ +typedef struct +{ + uint32_t total[2]; /*!< Number of bytes processed */ + uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ + uint32_t *shaPadding; /*!< Padding data */ + uint8_t shaFeed; /*!< Sha has feed data */ +} SEC_Eng_SHA256_Ctx; + +/** + * @brief SEC_ENG SHA link mode context + */ +typedef struct +{ + uint32_t total[2]; /*!< Number of bytes processed */ + uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ + uint32_t *shaPadding; /*!< Padding data */ + uint32_t linkAddr; /*!< Link configure address */ +} SEC_Eng_SHA256_Link_Ctx; + +/** + * @brief SEC_ENG AES context + */ +typedef struct +{ + uint8_t aesFeed; /*!< AES has feed data */ + SEC_ENG_AES_Type mode; /*!< AES mode */ +} SEC_Eng_AES_Ctx; + +/** + * @brief SEC_ENG SHA link config structure type definition + */ +typedef struct +{ + uint32_t : 2; /*!< [1:0]reserved */ + uint32_t shaMode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1 */ + uint32_t : 1; /*!< [5]reserved */ + uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */ + uint32_t : 2; /*!< [8:7]reserved */ + uint32_t shaIntClr : 1; /*!< [9]Clear interrupt */ + uint32_t shaIntSet : 1; /*!< [10]Set interrupt */ + uint32_t : 5; /*!< [15:11]reserved */ + uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */ + uint32_t shaSrcAddr; /*!< Message source address */ + uint32_t result[8]; /*!< Result of SHA */ +} __attribute__((aligned(4))) SEC_Eng_SHA_Link_Config_Type; + +/** + * @brief SEC_ENG AES link config structure type definition + */ +typedef struct +{ + uint32_t : 3; /*!< [2:0]Reserved */ + uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ + uint32_t aesDecEn : 1; /*!< [5]Encode or decode */ + uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */ + uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */ + uint32_t : 1; /*!< [8]Reserved */ + uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */ + uint32_t aesIntSet : 1; /*!< [10]Set interrupt */ + uint32_t : 1; /*!< [11]Reserved */ + uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ + uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */ + uint32_t : 1; /*!< [15]Reserved */ + uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */ + uint32_t aesSrcAddr; /*!< Message source address */ + uint32_t aesDstAddr; /*!< Message destination address */ + uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ + uint32_t aesIV1; /*!< Big endian initial vector */ + uint32_t aesIV2; /*!< Big endian initial vector */ + uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ + uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */ + uint32_t aesKey1; /*!< Big endian aes key */ + uint32_t aesKey2; /*!< Big endian aes key */ + uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */ + uint32_t aesKey4; /*!< Big endian aes key */ + uint32_t aesKey5; /*!< Big endian aes key */ + uint32_t aesKey6; /*!< Big endian aes key */ + uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */ +} __attribute__((aligned(4))) SEC_Eng_AES_Link_Config_Type; + +/** + * @brief SEC_ENG GMAC link config structure type definition + */ +typedef struct +{ + uint32_t : 9; /*!< [8:0]reserved */ + uint32_t gmacIntClr : 1; /*!< [9]Clear interrupt */ + uint32_t gmacIntSet : 1; /*!< [10]Set interrupt */ + uint32_t : 5; /*!< [15:11]reserved */ + uint32_t gmacMsgLen : 16; /*!< [31:16]Number of 128-bit block */ + uint32_t gmacSrcAddr; /*!< Message source address */ + uint32_t gmacKey0; /*!< GMAC key */ + uint32_t gmacKey1; /*!< GMAC key */ + uint32_t gmacKey2; /*!< GMAC key */ + uint32_t gmacKey3; /*!< GMAC key */ + uint32_t result[4]; /*!< Result of GMAC */ +} __attribute__((aligned(4))) SEC_Eng_GMAC_Link_Config_Type; + +/*@} end of group SEC_ENG_Public_Types */ + +/** @defgroup SEC_ENG_Public_Constants + * @{ + */ + +/** @defgroup SEC_ENG_AES_ID_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0)) + +/** @defgroup SEC_ENG_SHA_ID_TYPE + * @{ + */ +#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0)) + +/** @defgroup SEC_ENG_SHA_TYPE + * @{ + */ +#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || \ + ((type) == SEC_ENG_SHA224) || \ + ((type) == SEC_ENG_SHA1) || \ + ((type) == SEC_ENG_SHA1_RSVD)) + +/** @defgroup SEC_ENG_AES_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || \ + ((type) == SEC_ENG_AES_CTR) || \ + ((type) == SEC_ENG_AES_CBC)) + +/** @defgroup SEC_ENG_AES_KEY_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || \ + ((type) == SEC_ENG_AES_KEY_256BITS) || \ + ((type) == SEC_ENG_AES_KEY_192BITS) || \ + ((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS)) + +/** @defgroup SEC_ENG_AES_COUNTER_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_COUNTER_TYPE(type) (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_1) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_2) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_3)) + +/** @defgroup SEC_ENG_AES_VALUEUSED_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || \ + ((type) == SEC_ENG_AES_USE_OLD)) + +/** @defgroup SEC_ENG_AES_KEY_SRC_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || \ + ((type) == SEC_ENG_AES_KEY_HW)) + +/** @defgroup SEC_ENG_AES_ENDEC_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || \ + ((type) == SEC_ENG_AES_DECRYPTION)) + +/** @defgroup SEC_ENG_PKA_REG_SIZE_TYPE + * @{ + */ +#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type) (((type) == SEC_ENG_PKA_REG_SIZE_8) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_16) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_32) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_64) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_96) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_128) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_192) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_256) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_384) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_512)) + +/** @defgroup SEC_ENG_PKA_OP_TYPE + * @{ + */ +#define IS_SEC_ENG_PKA_OP_TYPE(type) (((type) == SEC_ENG_PKA_OP_PPSEL) || \ + ((type) == SEC_ENG_PKA_OP_MOD2N) || \ + ((type) == SEC_ENG_PKA_OP_LDIV2N) || \ + ((type) == SEC_ENG_PKA_OP_LMUL2N) || \ + ((type) == SEC_ENG_PKA_OP_LDIV) || \ + ((type) == SEC_ENG_PKA_OP_LSQR) || \ + ((type) == SEC_ENG_PKA_OP_LMUL) || \ + ((type) == SEC_ENG_PKA_OP_LSUB) || \ + ((type) == SEC_ENG_PKA_OP_LADD) || \ + ((type) == SEC_ENG_PKA_OP_LCMP) || \ + ((type) == SEC_ENG_PKA_OP_MDIV2) || \ + ((type) == SEC_ENG_PKA_OP_MINV) || \ + ((type) == SEC_ENG_PKA_OP_MEXP) || \ + ((type) == SEC_ENG_PKA_OP_MSQR) || \ + ((type) == SEC_ENG_PKA_OP_MMUL) || \ + ((type) == SEC_ENG_PKA_OP_MREM) || \ + ((type) == SEC_ENG_PKA_OP_MSUB) || \ + ((type) == SEC_ENG_PKA_OP_MADD) || \ + ((type) == SEC_ENG_PKA_OP_RESIZE) || \ + ((type) == SEC_ENG_PKA_OP_MOVDAT) || \ + ((type) == SEC_ENG_PKA_OP_NLIR) || \ + ((type) == SEC_ENG_PKA_OP_SLIR) || \ + ((type) == SEC_ENG_PKA_OP_CLIR) || \ + ((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || \ + ((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) || \ + ((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) || \ + ((type) == SEC_ENG_PKA_OP_CTLIR_PLD)) + +/** @defgroup SEC_ENG_INT_TYPE + * @{ + */ +#define IS_SEC_ENG_INT_TYPE(type) (((type) == SEC_ENG_INT_TRNG) || \ + ((type) == SEC_ENG_INT_AES) || \ + ((type) == SEC_ENG_INT_SHA) || \ + ((type) == SEC_ENG_INT_PKA) || \ + ((type) == SEC_ENG_INT_CDET) || \ + ((type) == SEC_ENG_INT_GMAC) || \ + ((type) == SEC_ENG_INT_ALL)) + +/*@} end of group SEC_ENG_Public_Constants */ + +/** @defgroup SEC_ENG_Public_Macros + * @{ + */ +#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24 +#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK 0x01000000 + +/*@} end of group SEC_ENG_Public_Macros */ + +/** @defgroup SEC_ENG_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SEC_GMAC_IRQHandler(void); +void SEC_CDET_IRQHandler(void); +void SEC_TRNG_IRQHandler(void); +void SEC_PKA_IRQHandler(void); +void SEC_AES_IRQHandler(void); +void SEC_SHA_IRQHandler(void); +#endif +void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type type, + uint32_t shaTmpBuf[16], + uint32_t padding[16]); +void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo); +BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, + uint32_t len); +BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash); +void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo); +void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo); +void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, + uint32_t shaTmpBuf[16], uint32_t padding[16]); +BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, + const uint8_t *input, uint32_t len); +BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, + uint8_t *hash); +BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, + SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType); +void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo); +BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, + uint8_t *out); +void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src); +void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, + const uint8_t *iv); +void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, + const uint8_t *iv); +void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType); +BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, + uint8_t *out); +BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo); +BL_Err_Type Sec_Eng_Trng_Enable(void); +void Sec_Eng_Trng_Int_Enable(void); +void Sec_Eng_Trng_Int_Disable(void); +BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]); +BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len); +void Sec_Eng_Trng_Int_Read_Trigger(void); +void Sec_Eng_Trng_Int_Read(uint8_t data[32]); +void Sec_Eng_Trng_Disable(void); +void Sec_Eng_PKA_Reset(void); +void Sec_Eng_PKA_BigEndian_Enable(void); +void Sec_Eng_PKA_LittleEndian_Enable(void); +void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, + uint8_t lastOp); +void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize); +void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp); +void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp); +void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx); +void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx, uint32_t size, + uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx); +void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType, + uint8_t invrRegIdx, + uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx); +void Sec_Eng_GMAC_Enable_LE(void); +void Sec_Eng_GMAC_Enable_BE(void); +void Sec_Eng_GMAC_Enable_Link(void); +void Sec_Eng_GMAC_Disable_Link(void); +BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out); +void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask); +void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType); +void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun); +BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType); +/*----------*/ +void SEC_Eng_Turn_On_Sec_Ring(void); +void SEC_Eng_Turn_Off_Sec_Ring(void); +/*----------*/; + +/*@} end of group SEC_ENG_Public_Functions */ + +/*@} end of group SEC_ENG */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SEC_ENG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..cb2cd5037cb6f9c0069302250e0de02be8409efd --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg.h @@ -0,0 +1,112 @@ +/** + ****************************************************************************** + * @file bl602_sf_cfg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CFG_H__ +#define __BL602_SF_CFG_H__ + +#include "string.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_Public_Types */ + +/** @defgroup SF_CFG_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_Public_Constants */ + +/** @defgroup SF_CFG_Public_Macros + * @{ + */ +/*Flash option 0*/ +/*Flash CLK*/ +#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_22 +/*FLASH CS*/ +#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_21 +/*FLASH DATA*/ +#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_20 +#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_19 +#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_18 +#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_17 +/*Flash option 1*/ +/*Flash CLK*/ +#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_22 +/*FLASH CS*/ +#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_21 +/*FLASH DATA*/ +#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_20 +#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_0 +#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_1 +#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_2 +#define BFLB_FLASH_CFG_DESWAP 1 +#define BFLB_FLASH_CFG_EXT0_17_22 2 +#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3 +#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 +#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF + +/*@} end of group SF_CFG_Public_Macros */ + +/** @defgroup SF_CFG_Public_Functions + * @{ + */ +BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); +void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault); +void SF_Cfg_Restore_GPIO17_Fun(uint8_t fun); +uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, + SPI_Flash_Cfg_Type *pFlashCfg); +void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); +void SF_Cfg_Init_Internal_Flash_Gpio(void); +void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); + +/*@} end of group SF_CFG_Public_Functions */ + +/*@} end of group SF_CFG */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CFG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg_ext.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..f3fbdfcb4ae9f6c772ba0a4fbefce6ea630b415d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg_ext.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file bl602_sf_cfg_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CFG_EXT_H__ +#define __BL602_SF_CFG_EXT_H__ + +#include "string.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG_EXT + * @{ + */ + +/** @defgroup SF_CFG_EXT_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Types */ + +/** @defgroup SF_CFG_EXT_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Constants */ + +/** @defgroup SF_CFG_EXT_Public_Macros + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Macros */ + +/** @defgroup SF_CFG_EXT_Public_Functions + * @{ + */ +BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); +uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, + uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg); + +/*@} end of group SF_CFG_EXT_Public_Functions */ + +/*@} end of group SF_CFG_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CFG_EXT_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_ctrl.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..b5b882ea5754435a7b4779bfb55a653808b73e13 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sf_ctrl.h @@ -0,0 +1,327 @@ +/** + ****************************************************************************** + * @file bl602_sf_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CTRL_H__ +#define __BL602_SF_CTRL_H__ + +#include "sf_ctrl_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Serial flash pad select type definition + */ +typedef enum { + SF_CTRL_EMBEDDED_SEL, /*!< Embedded flash select */ + SF_CTRL_EXTERNAL_17TO22_SEL, /*!< External flash select gpio 17-22 */ + SF_CTRL_EXTERNAL_0TO2_20TO22_SEL, /*!< External flash select gpio 0-2 and 20-22 */ +} SF_Ctrl_Pad_Sel; + +/** + * @brief Serial flash controller owner type definition + */ +typedef enum { + SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ + SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ +} SF_Ctrl_Owner_Type; + +/** + * @brief Serial flash controller select clock type definition + */ +typedef enum { + SF_CTRL_SAHB_CLOCK, /*!< Serial flash controller select default sahb clock */ + SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */ +} SF_Ctrl_Sahb_Type; + +/** + * @brief Serial flash controller owner type definition + */ +typedef enum { + HIGH_SPEED_MODE_CLOCK, /*!< Serial flash controller high speed mode clk_ahb>clk_sf */ + REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */ +} SF_Ctrl_Ahb2sif_Type; + +/** + * @brief Read and write type definition + */ +typedef enum { + SF_CTRL_READ, /*!< Serail flash read command flag */ + SF_CTRL_WRITE, /*!< Serail flash write command flag */ +} SF_Ctrl_RW_Type; + +/** + * @brief Serail flash interface IO type definition + */ +typedef enum { + SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ + SF_CTRL_DO_MODE, /*!< Dual Output mode define */ + SF_CTRL_QO_MODE, /*!< Quad Output mode define */ + SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ + SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ +} SF_Ctrl_IO_Type; + +/** + * @brief Serail flash controller interface mode type definition + */ +typedef enum { + SF_CTRL_SPI_MODE, /*!< SPI mode define */ + SF_CTRL_QPI_MODE, /*!< QPI mode define */ +} SF_Ctrl_Mode_Type; + +/** + * @brief Serail flash controller command mode type definition + */ +typedef enum { + SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ + SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ +} SF_Ctrl_Cmd_Mode_Type; + +/** + * @brief Serail flash controller address mode type definition + */ +typedef enum { + SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ + SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ + SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ +} SF_Ctrl_Addr_Mode_Type; + +/** + * @brief Serail flash controller dummy mode type definition + */ +typedef enum { + SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ + SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ + SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ +} SF_Ctrl_Dmy_Mode_Type; + +/** + * @brief Serail flash controller data mode type definition + */ +typedef enum { + SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ + SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ + SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ +} SF_Ctrl_Data_Mode_Type; + +/** + * @brief Serail flash controller AES type definition + */ +typedef enum { + SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ + SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ + SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ + SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ +} SF_Ctrl_AES_Key_Type; + +/** + * @brief Serail flash controller configuration structure type definition + */ +typedef struct +{ + SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ + SF_Ctrl_Sahb_Type sahbClock; /*!< Sflash clock sahb sram select */ + SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */ + uint8_t clkDelay; /*!< Clock count for read due to pad delay */ + uint8_t clkInvert; /*!< Clock invert */ + uint8_t rxClkInvert; /*!< RX clock invert */ + uint8_t doDelay; /*!< Data out delay */ + uint8_t diDelay; /*!< Data in delay */ + uint8_t oeDelay; /*!< Output enable delay */ +} SF_Ctrl_Cfg_Type; + +/** + * @brief Serail flash command configuration structure type definition + */ +typedef struct +{ + uint8_t rwFlag; /*!< Read write flag */ + SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ + SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ + uint8_t addrSize; /*!< Address size */ + uint8_t dummyClks; /*!< Dummy clocks */ + SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ + SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ + uint8_t rsv[1]; /*!< */ + uint32_t nbData; /*!< Transfer number of bytes */ + uint32_t cmdBuf[2]; /*!< Command buffer */ +} SF_Ctrl_Cmd_Cfg_Type; + +/*@} end of group SF_CTRL_Public_Types */ + +/** @defgroup SF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup SF_CTRL_PAD_SEL + * @{ + */ +#define IS_SF_CTRL_PAD_SEL(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \ + ((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \ + ((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL)) + +/** @defgroup SF_CTRL_OWNER_TYPE + * @{ + */ +#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ + ((type) == SF_CTRL_OWNER_IAHB)) + +/** @defgroup SF_CTRL_SAHB_TYPE + * @{ + */ +#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \ + ((type) == SF_CTRL_FLASH_CLOCK)) + +/** @defgroup SF_CTRL_AHB2SIF_TYPE + * @{ + */ +#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \ + ((type) == REMOVE_CLOCK_CONSTRAIN)) + +/** @defgroup SF_CTRL_RW_TYPE + * @{ + */ +#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ + ((type) == SF_CTRL_WRITE)) + +/** @defgroup SF_CTRL_IO_TYPE + * @{ + */ +#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ + ((type) == SF_CTRL_DO_MODE) || \ + ((type) == SF_CTRL_QO_MODE) || \ + ((type) == SF_CTRL_DIO_MODE) || \ + ((type) == SF_CTRL_QIO_MODE)) + +/** @defgroup SF_CTRL_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ + ((type) == SF_CTRL_QPI_MODE)) + +/** @defgroup SF_CTRL_CMD_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ + ((type) == SF_CTRL_CMD_4_LINES)) + +/** @defgroup SF_CTRL_ADDR_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ + ((type) == SF_CTRL_ADDR_2_LINES) || \ + ((type) == SF_CTRL_ADDR_4_LINES)) + +/** @defgroup SF_CTRL_DMY_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ + ((type) == SF_CTRL_DUMMY_2_LINES) || \ + ((type) == SF_CTRL_DUMMY_4_LINES)) + +/** @defgroup SF_CTRL_DATA_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ + ((type) == SF_CTRL_DATA_2_LINES) || \ + ((type) == SF_CTRL_DATA_4_LINES)) + +/** @defgroup SF_CTRL_AES_KEY_TYPE + * @{ + */ +#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ + ((type) == SF_CTRL_AES_256BITS) || \ + ((type) == SF_CTRL_AES_192BITS) || \ + ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) + +/*@} end of group SF_CTRL_Public_Constants */ + +/** @defgroup SF_CTRL_Public_Macros + * @{ + */ +#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF +#define FLASH_CTRL_BUF_SIZE 256 + +/*@} end of group SF_CTRL_Public_Macros */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SF_Ctrl_IRQHandler(void); +#endif +void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); +void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); +void SF_Ctrl_Disable(void); +void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel); +void SF_Ctrl_AES_Enable_BE(void); +void SF_Ctrl_AES_Enable_LE(void); +void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, + uint32_t endAddr, + uint8_t locked); +void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); +void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); +void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); +void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); +void SF_Ctrl_AES_Enable(void); +void SF_Ctrl_AES_Disable(void); +void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset); +uint32_t SF_Ctrl_Get_Flash_Image_Offset(void); +void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType); +void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); +void SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); +void SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); +BL_Sts_Type SF_Ctrl_GetBusyState(void); +uint8_t SF_Ctrl_Is_AES_Enable(void); +uint8_t SF_Ctrl_Get_Clock_Delay(void); +void SF_Ctrl_Set_Clock_Delay(uint8_t delay); + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CTRL_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sflash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sflash.h new file mode 100644 index 0000000000000000000000000000000000000000..ec5bd82d9edf8edc0159b31eba599c6b124eb753 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sflash.h @@ -0,0 +1,199 @@ +/** + ****************************************************************************** + * @file bl602_sflah.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SFLAH_H__ +#define __BL602_SFLAH_H__ + +#include "bl602_common.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH + * @{ + */ + +/** @defgroup SFLAH_Public_Types + * @{ + */ + +/** + * @brief Serial flash configuration structure type definition + */ +typedef struct +{ + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */ + uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +} __attribute__((packed)) SPI_Flash_Cfg_Type; + +/*@} end of group SFLAH_Public_Types */ + +/** @defgroup SFLAH_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_Public_Constants */ + +/** @defgroup SFLAH_Public_Macros + * @{ + */ +#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) +#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) +#define BFLB_SPIFLASH_CMD_INVALID 0xff + +/*@} end of group SFLAH_Public_Macros */ + +/** @defgroup SFLAH_Public_Functions + * @{ + */ +void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg); +BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode); +BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); +BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); +BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum); +BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); +BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); +BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr); +BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); +void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen); +void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data); +void SFlash_GetDeviceId(uint8_t *data); +void SFlash_Powerdown(void); +void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, + uint32_t len); +BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead); +BL_Err_Type SFlash_Cache_Enable_Set(uint8_t wayDisable); +BL_Err_Type SFlash_Cache_Flush(void); +BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, + uint8_t wayDisable); +void SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh); +uint32_t SFlash_Cache_Miss_Count_Get(void); +void SFlash_Cache_Read_Disable(void); +BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, + uint32_t len); +BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, + uint8_t regLen); +BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, + uint8_t regLen); + +/*@} end of group SFLAH_Public_Functions */ + +/*@} end of group SFLAH */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SFLAH_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sflash_ext.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sflash_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..4eaff66a41628ab232631fd0103613fb7e82418b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_sflash_ext.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file bl602_sflah_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SFLAH_EXT_H__ +#define __BL602_SFLAH_EXT_H__ + +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH_EXT + * @{ + */ + +/** @defgroup SFLAH_EXT_Public_Types + * @{ + */ + +/** + * @brief Serial flash security register configuration + */ +typedef struct +{ + uint8_t eraseCmd; /*!< Erase security register command */ + uint8_t programCmd; /*!< Program security register command */ + uint8_t readCmd; /*!< Read security register command */ + uint8_t enterSecOptCmd; /*!< Enter security register option mode command */ + uint8_t exitSecOptCmd; /*!< Exit security register option mode command */ + uint8_t blockNum; /*!< Security register block number */ + uint8_t *data; /*!< Data pointer to be program/read */ + uint32_t addr; /*!< Start address to be program/read */ + uint32_t len; /*!< Data length to be program/read */ +} SFlash_Sec_Reg_Cfg; + +/*@} end of group SFLAH_EXT_Public_Types */ + +/** @defgroup SFLAH_EXT_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Constants */ + +/** @defgroup SFLAH_EXT_Public_Macros + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Macros */ + +/** @defgroup SFLAH_EXT_Public_Functions + * @{ + */ +BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead); +BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos); +BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg); +BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, + SFlash_Sec_Reg_Cfg *pSecRegCfg); +BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg); + +/*@} end of group SFLAH_EXT_Public_Functions */ + +/*@} end of group SFLAH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SFLAH_EXT_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_spi.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..e2ba7003b969fbcf42b94ebca5588022efe9b5cc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_spi.h @@ -0,0 +1,317 @@ +/** + ****************************************************************************** + * @file bl602_spi.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SPI_H__ +#define __BL602_SPI_H__ + +#include "spi_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types + * @{ + */ + +/** + * @brief SPI No. type definition + */ +typedef enum { + SPI_ID_0, /*!< SPI0 port define */ + SPI_ID_MAX, /*!< SPI MAX ID define */ +} SPI_ID_Type; + +/** + * @brief SPI byte inverse type definition + */ +typedef enum { + SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */ + SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */ +} SPI_BYTE_INVERSE_Type; + +/** + * @brief SPI bit inverse type definition + */ +typedef enum { + SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */ + SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */ +} SPI_BIT_INVERSE_Type; + +/** + * @brief SPI clock phase inverse type definition + */ +typedef enum { + SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */ + SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */ +} SPI_CLK_PHASE_INVERSE_Type; + +/** + * @brief SPI clock polarity type definition + */ +typedef enum { + SPI_CLK_POLARITY_LOW, /*!< SPI clock output low at IDLE state */ + SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */ +} SPI_CLK_POLARITY_Type; + +/** + * @brief SPI frame size(also the valid width for each fifo entry) type definition + */ +typedef enum { + SPI_FRAME_SIZE_8, /*!< SPI frame size 8 bit */ + SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */ + SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */ + SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */ +} SPI_FrameSize_Type; + +/** + * @brief SPI work mode select type definition + */ +typedef enum { + SPI_WORK_MODE_SLAVE, /*!< SPI work at slave mode */ + SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */ +} SPI_WORK_MODE_Type; + +/** + * @brief SPI enable or disable timeout judgment definition + */ +typedef enum { + SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */ + SPI_TIMEOUT_ENABLE, /*!< SPI enable timeout judgment */ +} SPI_Timeout_Type; + +/** + * @brief SPI fifo overflow/underflow flag type definition + */ +typedef enum { + SPI_FIFO_TX_OVERFLOW, /*!< SPI tx fifo overflow flag */ + SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */ + SPI_FIFO_RX_OVERFLOW, /*!< SPI rx fifo overflow flag */ + SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */ +} SPI_FifoStatus_Type; + +/** + * @brief SPI interrupt type definition + */ +typedef enum { + SPI_INT_END, /*!< SPI transfer end interrupt,shared by both master and slave mode */ + SPI_INT_TX_FIFO_REQ, /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */ + SPI_INT_RX_FIFO_REQ, /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */ + SPI_INT_SLAVE_TIMEOUT, /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */ + SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */ + SPI_INT_FIFO_ERROR, /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */ + SPI_INT_ALL, /*!< All the interrupt */ +} SPI_INT_Type; + +/** + * @brief SPI configuration type definition + */ +typedef struct +{ + BL_Fun_Type deglitchEnable; /*!< Enable or disable de-glitch function */ + BL_Fun_Type continuousEnable; /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */ + SPI_BYTE_INVERSE_Type byteSequence; /*!< The byte is sent first in SPI transfer */ + SPI_BIT_INVERSE_Type bitSequence; /*!< The bit is sent first in SPI transfer */ + SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */ + SPI_CLK_POLARITY_Type clkPolarity; /*!< SPI clock plarity */ + SPI_FrameSize_Type frameSize; /*!< SPI frame size(also the valid width for each fifo entry) */ +} SPI_CFG_Type; + +/** + * @brief SPI configuration type definition + */ +typedef struct +{ + uint8_t startLen; /*!< Length of start condition */ + uint8_t stopLen; /*!< Length of stop condition */ + uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */ + uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */ + uint8_t intervalLen; /*!< Length of interval between frame */ +} SPI_ClockCfg_Type; + +/** + * @brief SPI DMA configuration type definition + */ +typedef struct +{ + uint8_t txFifoThreshold; /*!< SPI tx FIFO threshold */ + uint8_t rxFifoThreshold; /*!< SPI rx FIFO threshold */ + BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ + BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ +} SPI_FifoCfg_Type; + +/*@} end of group SPI_Public_Types */ + +/** @defgroup SPI_Public_Constants + * @{ + */ + +/** @defgroup SPI_ID_TYPE + * @{ + */ +#define IS_SPI_ID_TYPE(type) (((type) == SPI_ID_0) || \ + ((type) == SPI_ID_MAX)) + +/** @defgroup SPI_BYTE_INVERSE_TYPE + * @{ + */ +#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \ + ((type) == SPI_BYTE_INVERSE_BYTE3_FIRST)) + +/** @defgroup SPI_BIT_INVERSE_TYPE + * @{ + */ +#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \ + ((type) == SPI_BIT_INVERSE_LSB_FIRST)) + +/** @defgroup SPI_CLK_PHASE_INVERSE_TYPE + * @{ + */ +#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \ + ((type) == SPI_CLK_PHASE_INVERSE_1)) + +/** @defgroup SPI_CLK_POLARITY_TYPE + * @{ + */ +#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \ + ((type) == SPI_CLK_POLARITY_HIGH)) + +/** @defgroup SPI_FRAMESIZE_TYPE + * @{ + */ +#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) || \ + ((type) == SPI_FRAME_SIZE_16) || \ + ((type) == SPI_FRAME_SIZE_24) || \ + ((type) == SPI_FRAME_SIZE_32)) + +/** @defgroup SPI_WORK_MODE_TYPE + * @{ + */ +#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \ + ((type) == SPI_WORK_MODE_MASTER)) + +/** @defgroup SPI_TIMEOUT_TYPE + * @{ + */ +#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \ + ((type) == SPI_TIMEOUT_ENABLE)) + +/** @defgroup SPI_FIFOSTATUS_TYPE + * @{ + */ +#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) || \ + ((type) == SPI_FIFO_TX_UNDERFLOW) || \ + ((type) == SPI_FIFO_RX_OVERFLOW) || \ + ((type) == SPI_FIFO_RX_UNDERFLOW)) + +/** @defgroup SPI_INT_TYPE + * @{ + */ +#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) || \ + ((type) == SPI_INT_TX_FIFO_REQ) || \ + ((type) == SPI_INT_RX_FIFO_REQ) || \ + ((type) == SPI_INT_SLAVE_TIMEOUT) || \ + ((type) == SPI_INT_SLAVE_UNDERRUN) || \ + ((type) == SPI_INT_FIFO_ERROR) || \ + ((type) == SPI_INT_ALL)) + +/*@} end of group SPI_Public_Constants */ + +/** @defgroup SPI_Public_Macros + * @{ + */ +#define SPI_RX_FIFO_SIZE 4 +#define SPI_TX_FIFO_SIZE 4 + +/*@} end of group SPI_Public_Macros */ + +/** @defgroup SPI_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SPI_IRQHandler(void); +#endif +BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg); +BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg); +BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg); +BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType); +BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType); +BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value); +BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt); +BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint); +BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType); +BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, uint32_t data); +BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo, uint16_t *sendBuff, uint16_t *recvBuff, uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, + SPI_Timeout_Type timeoutType); +uint32_t SPI_ReceiveData(SPI_ID_Type spiNo); +uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo); +uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo); +BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType); +BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts); +BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo); +BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk); + +/*@} end of group SPI_Public_Functions */ + +/*@} end of group SPI */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SPI_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_timer.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..8b7f2a6bae3ea11013dd6da353850333ebcaea29 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_timer.h @@ -0,0 +1,247 @@ +/** + ****************************************************************************** + * @file bl602_timer.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_TIMER_H__ +#define __BL602_TIMER_H__ + +#include "timer_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Public_Types + * @{ + */ + +/** + * @brief TIMER channel type definition + */ +typedef enum { + TIMER_CH0, /*!< TIMER channel 0 port define */ + TIMER_CH1, /*!< TIMER channel 1 port define */ + TIMER_CH_MAX, /*!< */ +} TIMER_Chan_Type; + +/** + * @brief TIMER clock source type definition + */ +typedef enum { + TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */ + TIMER_CLKSRC_32K, /*!< TIMER clock source :32K CLK */ + TIMER_CLKSRC_1K, /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */ + TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */ +} TIMER_ClkSrc_Type; + +/** + * @brief TIMER match compare ID type definition + */ +typedef enum { + TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */ + TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */ + TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */ +} TIMER_Comp_ID_Type; + +/** + * @brief TIMER preload source type definition + */ +typedef enum { + TIMER_PRELOAD_TRIG_NONE, /*!< TIMER no preload source, just free run */ + TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */ + TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */ + TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */ +} TIMER_PreLoad_Trig_Type; + +/** + * @brief TIMER count register run mode type definition + */ +typedef enum { + TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */ + TIMER_COUNT_FREERUN, /*!< TIMER count register free run */ +} TIMER_CountMode_Type; + +/** + * @brief TIMER interrupt type definition + */ +typedef enum { + TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */ + TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */ + TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */ + TIMER_INT_ALL, /*!< */ +} TIMER_INT_Type; + +/** + * @brief Watchdog timer interrupt type definition + */ +typedef enum { + WDT_INT, /*!< Comparator 0 match cause interrupt */ + WDT_INT_ALL, /*!< */ +} WDT_INT_Type; + +/** + * @brief TIMER configuration structure type definition + */ +typedef struct +{ + TIMER_Chan_Type timerCh; /*!< Timer channel */ + TIMER_ClkSrc_Type clkSrc; /*!< Timer clock source */ + TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */ + TIMER_CountMode_Type countMode; /*!< Timer count mode */ + uint8_t clockDivision; /*!< Timer clock divison value */ + uint32_t matchVal0; /*!< Timer match 0 value 0 */ + uint32_t matchVal1; /*!< Timer match 1 value 0 */ + uint32_t matchVal2; /*!< Timer match 2 value 0 */ + uint32_t preLoadVal; /*!< Timer preload value */ +} TIMER_CFG_Type; + +/*@} end of group TIMER_Public_Types */ + +/** @defgroup TIMER_Public_Constants + * @{ + */ + +/** @defgroup TIMER_CHAN_TYPE + * @{ + */ +#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \ + ((type) == TIMER_CH1) || \ + ((type) == TIMER_CH_MAX)) + +/** @defgroup TIMER_CLKSRC_TYPE + * @{ + */ +#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \ + ((type) == TIMER_CLKSRC_32K) || \ + ((type) == TIMER_CLKSRC_1K) || \ + ((type) == TIMER_CLKSRC_XTAL)) + +/** @defgroup TIMER_COMP_ID_TYPE + * @{ + */ +#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \ + ((type) == TIMER_COMP_ID_1) || \ + ((type) == TIMER_COMP_ID_2)) + +/** @defgroup TIMER_PRELOAD_TRIG_TYPE + * @{ + */ +#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP0) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP1) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP2)) + +/** @defgroup TIMER_COUNTMODE_TYPE + * @{ + */ +#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \ + ((type) == TIMER_COUNT_FREERUN)) + +/** @defgroup TIMER_INT_TYPE + * @{ + */ +#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \ + ((type) == TIMER_INT_COMP_1) || \ + ((type) == TIMER_INT_COMP_2) || \ + ((type) == TIMER_INT_ALL)) + +/** @defgroup WDT_INT_TYPE + * @{ + */ +#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \ + ((type) == WDT_INT_ALL)) + +/*@} end of group TIMER_Public_Constants */ + +/** @defgroup TIMER_Public_Macros + * @{ + */ +#define WDT_ENABLE_ACCESS() \ + { \ + BL_WR_REG(TIMER_BASE, TIMER_WFAR, BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \ + BL_WR_REG(TIMER_BASE, TIMER_WSAR, BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \ + } + +/*@} end of group TIMER_Public_Macros */ + +/** @defgroup TIMER_Public_Functions + * @{ + */ + +/** + * @brief UART Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH0_IRQHandler(void); +void TIMER_CH1_IRQHandler(void); +void TIMER_WDT_IRQHandler(void); +#endif +BL_Err_Type TIMER_Init(TIMER_CFG_Type *timerCfg); +uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val); +uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh); +BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh); +void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val); +void TIMER_SetPreloadSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc); +void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode); +void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +void TIMER_Enable(TIMER_Chan_Type timerCh); +void TIMER_Disable(TIMER_Chan_Type timerCh); +void TIMER_IntMask(TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask); +void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc, uint8_t div); +uint16_t WDT_GetMatchValue(void); +void WDT_SetCompValue(uint16_t val); +uint16_t WDT_GetCounterValue(void); +void WDT_ResetCounterValue(void); +BL_Sts_Type WDT_GetResetStatus(void); +void WDT_ClearResetStatus(void); +void WDT_Enable(void); +void WDT_Disable(void); +void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask); +void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun); +void WDT_Int_Callback_Install(WDT_INT_Type wdtInt, intCallback_Type *cbFun); + +/*@} end of group TIMER_Public_Functions */ + +/*@} end of group TIMER */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_TIMER_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_tzc_sec.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_tzc_sec.h new file mode 100644 index 0000000000000000000000000000000000000000..8f43f12c69bcff063665c5d1239f7032da075539 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_tzc_sec.h @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file bl602_tzc_sec.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_TZC_SEC_H__ +#define __BL602_TZC_SEC_H__ + +#include "tzc_sec_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup TZC_SEC + * @{ + */ + +/** @defgroup TZC_SEC_Public_Types + * @{ + */ + +/*@} end of group TZC_SEC_Public_Types */ + +/** @defgroup TZC_SEC_Public_Constants + * @{ + */ + +/*@} end of group TZC_SEC_Public_Constants */ + +/** @defgroup TZC_SEC_Public_Macros + * @{ + */ + +/*@} end of group TZC_SEC_Public_Macros */ + +/** @defgroup TZC_SEC_Public_Functions + * @{ + */ +void TZC_Sboot_Set(uint8_t Val); +void TZC_Set_Rom0_R0_Protect(uint32_t start, uint32_t end); + +/*@} end of group TZC_SEC_Public_Functions */ + +/*@} end of group TZC_SEC */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_TZC_SEC_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_uart.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..c382f17e648abce12e3f70401a421022de4dc812 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_uart.h @@ -0,0 +1,318 @@ +/** + ****************************************************************************** + * @file bl602_uart.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_UART_H__ +#define __BL602_UART_H__ + +#include "uart_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_Public_Types + * @{ + */ + +/** + * @brief UART port type definition + */ +typedef enum { + UART0_ID, /*!< UART0 port define */ + UART1_ID, /*!< UART1 port define */ + UART_ID_MAX, /*!< UART MAX ID define */ +} UART_ID_Type; + +/** + * @brief UART direction type definition + */ +typedef enum { + UART_TX, /*!< UART TX Direction */ + UART_RX, /*!< UART RX Direction */ + UART_TXRX, /*!< UART TX and RX Direction */ +} UART_Direction_Type; + +/** + * @brief UART parity type definition + */ +typedef enum { + UART_PARITY_NONE, /*!< UART parity none define */ + UART_PARITY_ODD, /*!< UART parity odd define */ + UART_PARITY_EVEN, /*!< UART parity even define */ +} UART_Parity_Type; + +/** + * @brief UART data bits type definiton + */ +typedef enum { + UART_DATABITS_5, /*!< UART data bits length:5 bits */ + UART_DATABITS_6, /*!< UART data bits length:6 bits */ + UART_DATABITS_7, /*!< UART data bits length:7 bits */ + UART_DATABITS_8, /*!< UART data bits length:8 bits */ +} UART_DataBits_Type; + +/** + * @brief UART stop bits type definiton + */ +typedef enum { + UART_STOPBITS_0_5, /*!< UART data stop bits length:0.5 bits */ + UART_STOPBITS_1, /*!< UART data stop bits length:1 bits */ + UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */ + UART_STOPBITS_2, /*!< UART data stop bits length:2 bits */ +} UART_StopBits_Type; + +/** + * @brief UART each data byte is send out LSB-first or MSB-first type definiton + */ +typedef enum { + UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */ + UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */ +} UART_ByteBitInverse_Type; + +/** + * @brief UART auto baudrate detection using codeword 0x55 or start bit definiton + */ +typedef enum { + UART_AUTOBAUD_0X55, /*!< UART auto baudrate detection using codeword 0x55 */ + UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */ +} UART_AutoBaudDetection_Type; + +/** + * @brief UART interrupt type definition + */ +typedef enum { + UART_INT_TX_END, /*!< UART tx transfer end interrupt */ + UART_INT_RX_END, /*!< UART rx transfer end interrupt */ + UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */ + UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */ + UART_INT_RTO, /*!< UART rx time-out interrupt */ + UART_INT_PCE, /*!< UART rx parity check error interrupt */ + UART_INT_TX_FER, /*!< UART tx fifo overflow/underflow error interrupt */ + UART_INT_RX_FER, /*!< UART rx fifo overflow/underflow error interrupt */ + UART_INT_ALL, /*!< All the interrupt */ +} UART_INT_Type; + +/** + * @brief UART overflow or underflow type definition + */ +typedef enum { + UART_TX_OVERFLOW, /*!< UART tx fifo overflow */ + UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */ + UART_RX_OVERFLOW, /*!< UART rx fifo overflow */ + UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */ +} UART_Overflow_Type; + +/** + * @brief UART configuration structure type definition + */ +typedef struct +{ + uint32_t uartClk; /*!< Uart module clock */ + uint32_t baudRate; /*!< Uart baudrate */ + UART_DataBits_Type dataBits; /*!< Uart frame length of data bit */ + UART_StopBits_Type stopBits; /*!< Uart frame length of stop bit */ + UART_Parity_Type parity; /*!< Uart parity check type */ + BL_Fun_Type ctsFlowControl; /*!< Enable or disable tx CTS flow control */ + BL_Fun_Type rxDeglitch; /*!< Enable or disable rx input de-glitch function */ + BL_Fun_Type rtsSoftwareControl; /*!< Enable or disable rx RTS output SW control mode */ + UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */ +} UART_CFG_Type; + +/** + * @brief UART FIFO configuration structure type definition + */ +typedef struct +{ + uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */ + uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */ + BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ + BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ +} UART_FifoCfg_Type; + +/** + * @brief UART infrared configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type txIrEnable; /*!< Enable or disable uart tx ir mode */ + BL_Fun_Type rxIrEnable; /*!< Enable or disable uart rx ir mode */ + BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */ + BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */ + uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */ + uint16_t txIrPulseStop; /*!< Set stop position of uart tx ir pulse */ + uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */ +} UART_IrCfg_Type; + +/*@} end of group UART_Public_Types */ + +/** @defgroup UART_Public_Constants + * @{ + */ + +/** @defgroup UART_ID_TYPE + * @{ + */ +#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \ + ((type) == UART1_ID) || \ + ((type) == UART_ID_MAX)) + +/** @defgroup UART_DIRECTION_TYPE + * @{ + */ +#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \ + ((type) == UART_RX) || \ + ((type) == UART_TXRX)) + +/** @defgroup UART_PARITY_TYPE + * @{ + */ +#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \ + ((type) == UART_PARITY_ODD) || \ + ((type) == UART_PARITY_EVEN)) + +/** @defgroup UART_DATABITS_TYPE + * @{ + */ +#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \ + ((type) == UART_DATABITS_6) || \ + ((type) == UART_DATABITS_7) || \ + ((type) == UART_DATABITS_8)) + +/** @defgroup UART_STOPBITS_TYPE + * @{ + */ +#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) || \ + ((type) == UART_STOPBITS_1_5) || \ + ((type) == UART_STOPBITS_2)) + +/** @defgroup UART_BYTEBITINVERSE_TYPE + * @{ + */ +#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \ + ((type) == UART_MSB_FIRST)) + +/** @defgroup UART_AUTOBAUDDETECTION_TYPE + * @{ + */ +#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \ + ((type) == UART_AUTOBAUD_STARTBIT)) + +/** @defgroup UART_INT_TYPE + * @{ + */ +#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) || \ + ((type) == UART_INT_RX_END) || \ + ((type) == UART_INT_TX_FIFO_REQ) || \ + ((type) == UART_INT_RX_FIFO_REQ) || \ + ((type) == UART_INT_RTO) || \ + ((type) == UART_INT_PCE) || \ + ((type) == UART_INT_TX_FER) || \ + ((type) == UART_INT_RX_FER) || \ + ((type) == UART_INT_ALL)) + +/** @defgroup UART_OVERFLOW_TYPE + * @{ + */ +#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) || \ + ((type) == UART_TX_UNDERFLOW) || \ + ((type) == UART_RX_OVERFLOW) || \ + ((type) == UART_RX_UNDERFLOW)) + +/*@} end of group UART_Public_Constants */ + +/** @defgroup UART_Public_Macros + * @{ + */ +#define UART_RX_FIFO_SIZE 32 +#define UART_TX_FIFO_SIZE 32 +#define UART_DEFAULT_RECV_TIMEOUT 80 + +/*@} end of group UART_Public_Macros */ + +/** @defgroup UART_Public_Functions + * @{ + */ + +/** + * @brief UART Functions + */ +#if 1 //(!defined BFLB_USE_HAL_DRIVER)||(defined BFLB_EFLASH_LOADER) +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +#endif +BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg); +BL_Err_Type UART_DeInit(UART_ID_Type uartId); +BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg); +BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg); +BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct); +BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct); +BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length); +BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length); +BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time); +BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt); +BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet); +BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId); +BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId); +BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun); +BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud); +BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId); +BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId); +BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType); +BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len); +BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len); +uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen); +uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet); +uint8_t UART_GetTxFifoCount(UART_ID_Type uartId); +uint8_t UART_GetRxFifoCount(UART_ID_Type uartId); +BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType); +BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId); +BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId); +BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow); +uint32_t UART_GetBaudrate(UART_ID_Type uartId); + +/*@} end of group UART_Public_Functions */ + +/*@} end of group UART */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_UART_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash.h new file mode 100644 index 0000000000000000000000000000000000000000..c11183b6a735d4b888409b5af2f8a3455a6a25e4 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file bl602_xip_sflash.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_XIP_SFLASH_H__ +#define __BL602_XIP_SFLASH_H__ + +#include "bl602_common.h" +#include "bl602_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_Public_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Types */ + +/** @defgroup XIP_SFLASH_Public_Constants + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Constants */ + +/** @defgroup XIP_SFLASH_Public_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Macros */ + +/** @defgroup XIP_SFLASH_Public_Functions + * @{ + */ +BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset); +BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset); +BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr); +BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, + uint32_t len); +BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data); +BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data); +BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen); +BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len); +int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *dst, int len); +int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *src, int len); +int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, int len); +void XIP_SFlash_Opt_Enter(uint8_t *aesEnable); +void XIP_SFlash_Opt_Exit(uint8_t aesEnable); + +/*@} end of group XIP_SFLASH_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_XIP_SFLASH_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash_ext.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..43eb9f69dd607ff9c2d30ee5ad8c3bc278c3a80e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash_ext.h @@ -0,0 +1,101 @@ +/** + ****************************************************************************** + * @file bl602_xip_sflash_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_XIP_SFLASH_EXT_H__ +#define __BL602_XIP_SFLASH_EXT_H__ + +#include "bl602_common.h" +#include "bl602_sflash.h" +#include "bl602_sflash_ext.h" +#include "bl602_xip_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH_EXT + * @{ + */ + +/** @defgroup XIP_SFLASH_EXT_Public_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Types */ + +/** @defgroup XIP_SFLASH_EXT_Public_Constants + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Constants */ + +/** @defgroup XIP_SFLASH_EXT_Public_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Macros */ + +/** @defgroup XIP_SFLASH_EXT_Public_Functions + * @{ + */ +BL_Err_Type XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset); +BL_Err_Type XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr, + uint32_t endaddr); +BL_Err_Type XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, + uint32_t len); +BL_Err_Type XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, + uint32_t len); +BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data); +BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data); +BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data, + uint8_t idLen); +BL_Err_Type XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, + uint8_t bitPos); +int XIP_SFlash_Read_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len); +int XIP_SFlash_Write_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len); +int XIP_SFlash_Erase_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len); +int XIP_SFlash_RCV_Enable_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos); +BL_Err_Type XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg); +int XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len); +int XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len); +int XIP_SFlash_Erase(uint32_t addr, int len); + +/*@} end of group XIP_SFLASH_EXT_Public_Functions */ + +/*@} end of group XIP_SFLASH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_XIP_SFLASH_EXT_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_acomp.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_acomp.c new file mode 100644 index 0000000000000000000000000000000000000000..75f3d811c4a9b317da13ce0310a18d2e3bdc5b9e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_acomp.c @@ -0,0 +1,202 @@ +/** + ****************************************************************************** + * @file bl602_acomp.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_acomp.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ACOMP + * @{ + */ + +/** @defgroup ACOMP_Private_Macros + * @{ + */ + +/*@} end of group ACOMP_Private_Macros */ + +/** @defgroup ACOMP_Private_Types + * @{ + */ + +/*@} end of group ACOMP_Private_Types */ + +/** @defgroup ACOMP_Private_Variables + * @{ + */ + +/*@} end of group ACOMP_Private_Variables */ + +/** @defgroup ACOMP_Global_Variables + * @{ + */ + +/*@} end of group ACOMP_Global_Variables */ + +/** @defgroup ACOMP_Private_Fun_Declaration + * @{ + */ + +/*@} end of group ACOMP_Private_Fun_Declaration */ + +/** @defgroup ACOMP_Private_Functions + * @{ + */ + +/*@} end of group ACOMP_Private_Functions */ + +/** @defgroup ACOMP_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Analog compare init + * + * @param acompNo: Compare ID + * @param cfg: Compare consideration pointer + * + * @return None + * +*******************************************************************************/ +void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + if (acompNo == AON_ACOMP0_ID) { + /* Disable ACOMP first */ + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); + + /* Set ACOMP config */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, cfg->muxEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, cfg->posChanSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, cfg->negChanSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, cfg->levelFactor); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, cfg->biasProg); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, cfg->hysteresisPosVolt); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, cfg->hysteresisNegVolt); + + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); + + } else { + /* Disable ACOMP first */ + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); + + /* Set ACOMP config */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, cfg->muxEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, cfg->posChanSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, cfg->negChanSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, cfg->levelFactor); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, cfg->biasProg); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, cfg->hysteresisPosVolt); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, cfg->hysteresisNegVolt); + + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); + } +} + +/****************************************************************************/ /** + * @brief Analog compare enable + * + * @param acompNo: Compare ID + * + * @return None + * +*******************************************************************************/ +void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + if (acompNo == AON_ACOMP0_ID) { + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); + } else { + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); + } +} + +/****************************************************************************/ /** + * @brief Analog compare enable + * + * @param acompNo: Compare ID + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL); + + /* Disable ACOMP first */ + if (acompNo == AON_ACOMP0_ID) { + if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) { + return SET; + } else { + return RESET; + } + } else { + if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) { + return SET; + } else { + return RESET; + } + } +} + +/*@} end of group ACOMP_Public_Functions */ + +/*@} end of group ACOMP */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_adc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..2db727f7adc170db942f0b159b00bc24347b9eb8 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_adc.c @@ -0,0 +1,1412 @@ +/** + ****************************************************************************** + * @file bl602_adc.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_adc.h" +#include "bl602_ef_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ +#undef MSG +#define MSG(...) +#define AON_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } +#define ADC_RESTART_DUMMY_WAIT BL602_Delay_US(100) + +/*@} end of group ADC_Private_Macros */ + +/** @defgroup ADC_Private_Types + * @{ + */ + +/*@} end of group ADC_Private_Types */ + +/** @defgroup ADC_Private_Variables + * @{ + */ +static intCallback_Type *adcIntCbfArra[ADC_INT_ALL] = { NULL }; +static ADC_Gain_Coeff_Type adcGainCoeffCal = { + .adcGainCoeffEnable = DISABLE, + .adcgainCoeffVal = 0, + .coe = 1, +}; + +/*@} end of group ADC_Private_Variables */ + +/** @defgroup ADC_Global_Variables + * @{ + */ + +/*@} end of group ADC_Global_Variables */ + +/** @defgroup ADC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group ADC_Private_Fun_Declaration */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/*@} end of group ADC_Private_Functions */ + +/** @defgroup ADC_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Software reset the whole ADC + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Reset(void) +{ + uint32_t regCmd; + + /* reset ADC */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); + AON_CLK_SET_DUMMY_WAIT; + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); +} + +/****************************************************************************/ /** + * @brief ADC glable enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC glable disable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC normal mode init + * + * @param cfg: ADC normal mode configuration + * + * @return None + * +*******************************************************************************/ +void ADC_Init(ADC_CFG_Type *cfg) +{ + uint32_t regCfg1; + uint32_t regCfg2; + uint32_t regCalib; + + CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel)); + CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel)); + CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv)); + CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1)); + CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2)); + CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode)); + CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel)); + CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm)); + CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref)); + CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode)); + CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth)); + + /* config 1 */ + regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); + AON_CLK_SET_DUMMY_WAIT; + + /* config 2 */ + regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel); + + /* chopmode cannot be set by user any more*/ + if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) { + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, 2); + } else { + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, 1); + } + + /* pga_vcmi_en is for mic */ + regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN); + + if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) { + regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN); + } else { + regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN); + } + + /* pga_os_cal is for mic */ + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2); + + /* calibration offset */ + regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE); + regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal); + BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler); +#endif + + ADC_Gain_Trim(); +} + +/****************************************************************************/ /** + * @brief ADC normal mode channel config + * + * @param posCh: ADC pos channel type + * @param negCh: ADC neg channel type + * @param contEn: ENABLE or DISABLE continuous mode + * + * @return None + * +*******************************************************************************/ +void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn) +{ + uint32_t regCmd; + uint32_t regCfg1; + + CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh)); + CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh)); + + /* set channel */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh); + regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); + + /* set continuous mode */ + regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); +} + +/****************************************************************************/ /** + * @brief ADC scan mode channel config + * + * @param posChList[]: ADC pos channel list type + * @param negChList[]: ADC neg channel list type + * @param scanLength: ADC scan length + * @param contEn: ENABLE or DISABLE continuous mode + * + * @return None + * +*******************************************************************************/ +void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn) +{ + uint32_t tmpVal, i; + uint32_t dealLen; + + CHECK_PARAM((scanLength < 13)); + + /* Deal with the first 6 */ + dealLen = 6; + + if (scanLength < dealLen) { + dealLen = scanLength; + } + + /* Set first 6 scan channels */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1); + + for (i = 0; i < dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (posChList[i] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal); + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1); + + for (i = 0; i < dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (negChList[i] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal); + + /* Set the left channels */ + if (scanLength > dealLen) { + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2); + + for (i = 0; i < scanLength - dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (posChList[i + dealLen] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal); + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2); + + for (i = 0; i < scanLength - dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (negChList[i + dealLen] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal); + } + + /* Scan mode */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC normal mode convert start + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Start(void) +{ + uint32_t regCmd; + + /* disable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); + + ADC_RESTART_DUMMY_WAIT; + + /* enable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); +} + +/****************************************************************************/ /** + * @brief ADC normal mode convert stop + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Stop(void) +{ + uint32_t regCmd; + + /* disable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); +} + +/****************************************************************************/ /** + * @brief ADC FIFO configuration + * + * @param fifoCfg: ADC FIFO confifuration pointer + * + * @return None + * +*******************************************************************************/ +void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold)); + + /* + * DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur + * DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt + */ + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold); + + /* Enable DMA */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn); + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO data count + * + * @param None + * + * @return data count in FIFO + * +*******************************************************************************/ +uint8_t ADC_Get_FIFO_Count(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT); +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO full status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_FIFO_Is_Full(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO empty status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_FIFO_Is_Empty(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) { + return RESET; + } else { + return SET; + } +} + +/****************************************************************************/ /** + * @brief ADC read DMA FIFO data + * + * @param None + * + * @return ADC result if return 0 that means this is error data,user should ignore this data. + * +*******************************************************************************/ +uint32_t ADC_Read_FIFO(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA); + + return (tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC parse result + * + * @param orgVal: Original A to D value + * @param len: Original AD vaule count + * @param result: Final Result array pointer + * + * @return None + * +*******************************************************************************/ +void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result) +{ + uint8_t neg = 0; + uint32_t tmpVal1 = 0, tmpVal2 = 0; + ADC_Data_Width_Type dataType; + ADC_SIG_INPUT_Type sigType; + float ref = 2.0; + uint32_t i = 0; + + float coe = 1.0; + + if (adcGainCoeffCal.adcGainCoeffEnable) { + coe = adcGainCoeffCal.coe; + } + + tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL); + sigType = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE); + + if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) { + ref = 3.2; + } + + if (sigType == ADC_INPUT_SINGLE_END) { + for (i = 0; i < len; i++) { + result[i].posChan = orgVal[i] >> 21; + result[i].negChan = -1; + + if (dataType == ADC_DATA_WIDTH_12) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); + result[i].volt = result[i].value / 4096.0 * ref; + } else if (dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); + result[i].volt = result[i].value / 16384.0 * ref; + } else if (dataType == ADC_DATA_WIDTH_16_WITH_64_AVERAGE || dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE) { + result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); + result[i].volt = result[i].value / 65536.0 * ref; + } + } + } else { + for (i = 0; i < len; i++) { + neg = 0; + result[i].posChan = orgVal[i] >> 21; + result[i].negChan = (orgVal[i] >> 16) & 0x1F; + + if (orgVal[i] & 0x8000) { + orgVal[i] = ~orgVal[i]; + orgVal[i] += 1; + neg = 1; + } + + if (dataType == ADC_DATA_WIDTH_12) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); + result[i].volt = result[i].value / 2048.0 * ref; + } else if (dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); + result[i].volt = result[i].value / 8192.0 * ref; + } else if (dataType == ADC_DATA_WIDTH_16_WITH_64_AVERAGE || dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE) { + result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); + result[i].volt = result[i].value / 32768.0 * ref; + } + + if (neg) { + result[i].volt = -result[i].volt; + } + } + } +} + +/****************************************************************************/ /** + * @brief ADC mask or unmask certain or all interrupt + * + * @param intType: interrupt type + * @param intMask: mask or unmask + * + * @return None + * +*******************************************************************************/ +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + } + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + } + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + } + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + + case ADC_INT_ALL: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + } else { + /* Disable this interrupt */ + tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief ADC clear certain or all interrupt + * + * @param intType: interrupt type + * + * @return None + * +*******************************************************************************/ +void ADC_IntClr(ADC_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_ALL: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief ADC get interrupt status + * + * @param intType: interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) +{ + uint32_t tmpVal; + BL_Sts_Type bitStatus = RESET; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET; + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET; + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET; + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET; + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET; + break; + + case ADC_INT_ALL: + break; + + default: + break; + } + + return bitStatus; +} + +/****************************************************************************/ /** + * @brief ADC install interrupt callback + * + * @param intType: ADC interrupt type + * @param cbFun: ADC interrupt callback + * + * @return None + * +*******************************************************************************/ +void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + adcIntCbfArra[intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief ADC DMA interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void GPADC_DMA_IRQHandler(void) +{ + if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) { + ADC_IntClr(ADC_INT_POS_SATURATION); + + if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) { + adcIntCbfArra[ADC_INT_POS_SATURATION](); + } + } + + if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) { + ADC_IntClr(ADC_INT_NEG_SATURATION); + + if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) { + adcIntCbfArra[ADC_INT_NEG_SATURATION](); + } + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) { + ADC_IntClr(ADC_INT_FIFO_UNDERRUN); + + if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_UNDERRUN](); + } + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) { + ADC_IntClr(ADC_INT_FIFO_OVERRUN); + + if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_OVERRUN](); + } + } + + if (ADC_GetIntStatus(ADC_INT_ADC_READY) == SET) { + ADC_IntClr(ADC_INT_ADC_READY); + + if (adcIntCbfArra[ADC_INT_ADC_READY] != NULL) { + adcIntCbfArra[ADC_INT_ADC_READY](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief ADC VBAT enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Vbat_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC VBAT disable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Vbat_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC TSEN Config + * + * @param tsenMod: None + * + * @return None + * +*******************************************************************************/ +void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type)); + + /* config gpadc_reg_cmd */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + /* enable sensor dc test mux*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN); + /*selected sen output current channel*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0); + /* enable chip sensor*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU); + /*dwa_en */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + + /* config 2 */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + /*tsvbe low=0*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + /*dly_sel=2*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2); + /*test_sel=0*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0); + /*test_en=0*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN); + /*ts_en*/ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); + /*select tsen ext or inner*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2); + /*pga vcmi enable*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); + /*0:512uS;1:16mS;2:32mS;3:64mS*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); + + /* config 3 */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + /* set gpadc_dither_en */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); + + /* set 4000F90C[19](gpadc_mic2_diff) = 1 + * debug advise form Ran + * 2020.08.26 + */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief TSEN_Get_V_Error + * + * @param None + * + * @return None + * +*******************************************************************************/ +uint32_t TSEN_Get_V_Error(void) +{ + uint32_t v0 = 0, v1 = 0; + uint32_t v_error = 0; + uint32_t regVal = 0; + ADC_Result_Type result; + uint32_t tmpVal; + uint8_t gainCalEnabled = 0; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_LOW(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v0 = result.value; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_HIGH(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v1 = result.value; + + v_error = v0 - v1; + + return v_error; +} + +/****************************************************************************/ /** + * @brief Trim TSEN + * + * @param tsen_offset: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset) +{ + uint8_t average_index = 0; + uint32_t v_error_sum = 0; + uint32_t tmpVal = 0; + float A1 = 0.0, A2 = 0.0, C = 0.0, delta = 0.0; + Efuse_TSEN_Refcode_Corner_Type trim; + + EF_Ctrl_Read_TSEN_Trim(&trim); + + if (trim.tsenRefcodeCornerEn) { + if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) { + MSG("TSEN ATE Version = %d\r\n", trim.tsenRefcodeCornerVersion); + + *tsen_offset = trim.tsenRefcodeCorner; + + if (trim.tsenRefcodeCornerVersion == 0) { + /* debug advise by ran + * 2020.9.04 + */ + + //set 4000F90C[19](gpadc_mic2_diff) = 0 + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 0); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + + for (average_index = 0; average_index < 50; average_index++) { + v_error_sum += TSEN_Get_V_Error(); + } + + v_error_sum /= 50; + + MSG("A1 = %d\r\n", v_error_sum); + A1 = v_error_sum; + + v_error_sum = 0; + + //set 4000F90C[19](gpadc_mic2_diff) = 1 + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + + for (average_index = 0; average_index < 50; average_index++) { + v_error_sum += TSEN_Get_V_Error(); + } + + v_error_sum /= 50; + + MSG("A2 = %d\r\n", v_error_sum); + A2 = v_error_sum; + + MSG("C = %d\r\n", *tsen_offset); + C = *tsen_offset; + + delta = A2 - (7.753 / 5.62 * A1) + 2.133 / 5.62 * C + 72; + + MSG("delta=A2-7.753/5.62*A1+2.133/5.62*C+72x; delta = %d\r\n", (uint16_t)delta); + + *tsen_offset = delta + C; + } + + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_SET_TSVBE_LOW(void) +{ + uint32_t tmpVal; + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_SET_TSVBE_HIGH(void) +{ + uint32_t tmpVal; + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param tsen_offset: tsen_offset form efuse trim data + * + * @return tempture + * +*******************************************************************************/ +float TSEN_Get_Temp(uint32_t tsen_offset) +{ + uint32_t v0 = 0, v1 = 0; + float temp = 0; + uint32_t regVal = 0; + ADC_Result_Type result; + uint32_t tmpVal; + uint8_t gainCalEnabled = 0; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_LOW(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v0 = result.value; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_HIGH(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v1 = result.value; + + if (v0 > v1) { + temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753; + } else { + temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753; + } + + return temp; +} + +/****************************************************************************/ /** + * @brief ADC MIC Config + * + * @param adc_mic_config: adc_mic_config + * + * @return success or not + * +*******************************************************************************/ +BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config) +{ + uint32_t tmpVal1 = 0, tmpVal2 = 0; + + CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb)); + CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain)); + CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode)); + CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn)); + + tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + + tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn); + + if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) { + /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/ + return ERROR; + } else { + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn); + } + + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief ADC MIC bias control + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_MIC_Bias_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC MIC bias control + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_MIC_Bias_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief Trim ADC Gain + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) +{ + Efuse_ADC_Gain_Coeff_Type trim; + uint32_t tmp; + + EF_Ctrl_Read_ADC_Gain_Trim(&trim); + + if (trim.adcGainCoeffEn) { + if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) { + adcGainCoeffCal.adcGainCoeffEnable = ENABLE; + adcGainCoeffCal.adcgainCoeffVal = trim.adcGainCoeff; + tmp = adcGainCoeffCal.adcgainCoeffVal; + + if (tmp & 0x800) { + tmp = ~tmp; + tmp += 1; + tmp = tmp & 0xfff; + //printf("val==%08x\r\n",(unsigned int)tmp); + adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0)); + //printf("coe==%0f\r\n",adcGainCoeffCal.coe); + } else { + adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0)); + //printf("coe==%0f\r\n",adcGainCoeffCal.coe); + } + + return SUCCESS; + } + } + + return ERROR; +} + +/*@} end of group ADC_Public_Functions */ + +/*@} end of group ADC */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_aon.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_aon.c new file mode 100644 index 0000000000000000000000000000000000000000..3f148bd447e1f074050bd2e85ab25bb333535646 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_aon.c @@ -0,0 +1,551 @@ +/** + ****************************************************************************** + * @file bl602_aon.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_aon.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Private_Macros + * @{ + */ +#define AON_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group AON_Private_Macros */ + +/** @defgroup AON_Private_Types + * @{ + */ + +/*@} end of group AON_Private_Types */ + +/** @defgroup AON_Private_Variables + * @{ + */ + +/*@} end of group AON_Private_Variables */ + +/** @defgroup AON_Global_Variables + * @{ + */ + +/*@} end of group AON_Global_Variables */ + +/** @defgroup AON_Private_Fun_Declaration + * @{ + */ + +/*@} end of group AON_Private_Fun_Declaration */ + +/** @defgroup AON_Private_Functions + * @{ + */ + +/*@} end of group AON_Private_Functions */ + +/** @defgroup AON_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Power on MXX band gap + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void) +{ + uint32_t tmpVal = 0; + + /* Power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off MXX band gap + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void) +{ + uint32_t tmpVal = 0; + + /* Power OFF */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on XTAL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + /* Polling for ready */ + do { + BL602_Delay_US(10); + timeOut++; + tmpVal = BL_RD_REG(AON_BASE, AON_TSEN); + } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120); + + if (timeOut >= 120) { + return TIMEOUT; + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set XTAL cap code + * + * @param capIn: Cap code in + * @param capOut: Cap code out + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut); + BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal); + + BL602_Delay_US(100); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get XTAL cap code + * + * @param None + * + * @return Cap code + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); + + return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON); +} +#endif + +/****************************************************************************/ /** + * @brief Power off XTAL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on bandgap system + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void) +{ + uint32_t tmpVal = 0; + + /* power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); + BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off bandgap system + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void) +{ + uint32_t tmpVal = 0; + + /* power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); + BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on LDO11 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON); + BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off LDO11 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON); + BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on LDO15_RF + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void) +{ + uint32_t tmpVal = 0; + + /* ldo15rf power on */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL602_Delay_US(90); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off LDO15_RF + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void) +{ + uint32_t tmpVal = 0; + + /* ldo15rf power off */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief power on source follow regular + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void) +{ + uint32_t tmpVal = 0; + + /* power on sfreg */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL602_Delay_US(10); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief power off source follow regular + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void) +{ + uint32_t tmpVal = 0; + + /* power off sfreg */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off the power can be shut down in PDS0 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void) +{ + uint32_t tmpVal = 0; + + /* power off sfreg */ + tmpVal = BL_RD_REG(AON_BASE, AON_MISC); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON); + BL_WR_REG(AON_BASE, AON_MISC, tmpVal); + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + /* gating Clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); + tmpVal = tmpVal & (~(1 << 6)); + tmpVal = tmpVal & (~(1 << 7)); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on the power powered down in PDS0 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL602_Delay_US(20); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL602_Delay_US(60); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL602_Delay_US(20); + + /* power on wb */ + tmpVal = BL_RD_REG(AON_BASE, AON_MISC); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON); + BL_WR_REG(AON_BASE, AON_MISC, tmpVal); + + /* ungating Clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); + tmpVal = tmpVal | ((1 << 6)); + tmpVal = tmpVal | ((1 << 7)); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on the power powered down in PDS0 + * + * @param delay: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((delay <= 0x3)); + + /* config ldo11soc_sstart_delay_aon */ + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay); + BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal); + + return SUCCESS; +} + +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_common.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_common.c new file mode 100644 index 0000000000000000000000000000000000000000..cb2cb8c4c367d1196bf0aa65c9c4d8e90ade3652 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_common.c @@ -0,0 +1,343 @@ +#include "l1c_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Periph_Driver + * @{ + */ + +/** @defgroup DRIVER_COMMON DRIVER_COMMON + * @brief Digger driver common functions + * @{ + */ + +/** @defgroup DRIVER_Private_Type + * @{ + */ + +/*@} end of group DRIVER_Private_Type*/ + +/** @defgroup DRIVER_Private_Defines + * @{ + */ + +/*@} end of group DRIVER_Private_Defines */ + +/** @defgroup DRIVER_Private_Variables + * @{ + */ +pFunc __Interrupt_Handlers[IRQn_LAST] = { 0 }; + +/*@} end of group DRIVER_Private_Variables */ + +/** @defgroup DRIVER_Global_Variables + * @{ + */ + +/*@} end of group DRIVER_Global_Variables */ + +/** @defgroup DRIVER_Private_FunctionDeclaration + * @{ + */ + +/*@} end of group DRIVER_Private_FunctionDeclaration */ + +/** @defgroup DRIVER_Private_Functions + * @{ + */ + +/*@} end of group DRIVER_Private_Functions */ + +/** @defgroup DRIVER_Public_Functions + * @{ + */ + +void Trap_Handler(void) +{ + unsigned long cause; + unsigned long epc; + unsigned long tval; + + MSG("Trap_Handler\r\n"); + + cause = read_csr(mcause); + MSG("mcause=%08x\r\n", (uint32_t)cause); + epc = read_csr(mepc); + MSG("mepc:%08x\r\n", (uint32_t)epc); + tval = read_csr(mtval); + MSG("mtval:%08x\r\n", (uint32_t)tval); + + cause = (cause & 0x3ff); + + switch (cause) { + case 1: + MSG("Instruction access fault\r\n"); + break; + + case 2: + MSG("Illegal instruction\r\n"); + break; + + case 3: + MSG("Breakpoint\r\n"); + break; + + case 4: + MSG("Load address misaligned\r\n"); + break; + + case 5: + MSG("Load access fault\r\n"); + break; + + case 6: + MSG("Store/AMO address misaligned\r\n"); + break; + + case 7: + MSG("Store/AMO access fault\r\n"); + break; + + case 8: + MSG("Environment call from U-mode\r\n"); + epc += 4; + write_csr(mepc, epc); + break; + + case 9: + MSG("Environment call from M-mode\r\n"); + epc += 4; + write_csr(mepc, epc); + break; + + default: + MSG("Cause num=%d\r\n", (uint32_t)cause); + epc += 4; + write_csr(mepc, epc); + break; + } + + while (1) + ; +} + +void Interrupt_Handler(void) +{ + pFunc interruptFun; + uint32_t num = 0; + volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL; + + /* Store a few register values that might be useful when determining why this + function was called. */ + __asm volatile("csrr %0, mepc" + : "=r"(ulMEPC)); + __asm volatile("csrr %0, mcause" + : "=r"(ulMCAUSE)); + + if ((ulMCAUSE & 0x80000000) == 0) { + /*Exception*/ + MSG("Exception should not be here\r\n"); + } else { + num = ulMCAUSE & 0x3FF; + + if (num < IRQn_LAST) { + interruptFun = __Interrupt_Handlers[num]; + + if (NULL != interruptFun) { + interruptFun(); + } else { + MSG("Interrupt num:%d IRQHandler not installed\r\n", (unsigned int)num); + + if (num >= IRQ_NUM_BASE) { + MSG("Peripheral Interrupt num:%d \r\n", (unsigned int)num - IRQ_NUM_BASE); + } + + while (1) + ; + } + } else { + MSG("Unexpected interrupt num:%d\r\n", (unsigned int)num); + } + } +} + +void trap_handler(void) +{ +#define MCAUSE_INT_MASK 0x80000000 // [31]=1 interrupt, else exception +#define MCAUSE_CODE_MASK 0x7FFFFFFF // low bits show code + + unsigned long mcause_value = read_csr(mcause); + if (mcause_value & MCAUSE_INT_MASK) { + // Branch to interrupt handler here + Interrupt_Handler(); + } else { + // Branch to exception handle + Trap_Handler(); + } +} + +void FreeRTOS_Interrupt_Handler(void) +{ + Interrupt_Handler(); +} + +void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) +{ + if (irq < IRQn_LAST) { + __Interrupt_Handlers[irq] = interruptFun; + } +} + +/****************************************************************************/ /** + * @brief delay us + * + * @param[in] core: systemcoreclock + * + * @param[in] cnt: delay cnt us + * + * @return none + * + *******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +#ifdef ARCH_ARM +#ifndef __GNUC__ +__WEAK +__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2, #0x01 cmp r2, #0x00 bne loop end bx lr +} +#else +__WEAK +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + __asm__ __volatile__( + "lsr r0,#0x10\n\t" + "mul r0,r1,r0\n\t" + "mov r2,r0\n\t" + "lsr r2,#0x04\n\t" + "lsr r2,#0x03\n\t" + "cmp r2,#0x01\n\t" + "beq end\n\t" + "cmp r2,#0x00\n\t" + "beq end\n" + "loop :" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "sub r2,r2,#0x01\n\t" + "cmp r2,#0x00\n\t" + "bne loop\n" + "end :" + "mov r0,r0\n\t"); +} +#endif +#endif +#ifdef ARCH_RISCV +__WEAK +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + uint32_t codeAddress = 0; + uint32_t divVal = 40; + + codeAddress = (uint32_t)&ASM_Delay_Us; + + /* 1M=100K*10, so multiple is 10 */ + /* loop function take 4 instructions, so instructionNum is 4 */ + /* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */ + /* divVal = multiple*instructionNum*irom2TAccess */ + if (((codeAddress & (0xF << 24)) >> 24) == 0x01) { + /* IROM space */ + if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) { + /* instruction 2T */ + divVal = 80; + } + } + + __asm__ __volatile__( + ".align 4\n\t" + "lw a4,%1\n\t" + "lui a5,0x18\n\t" + "addi a5,a5,1696\n\t" + "divu a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a4,%1\n\t" + "lw a5,%0\n\t" + "mul a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a4,%1\n\t" + "lw a5,%2\n\t" + "divu a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a5,%1\n\t" + "li a4,0x1\n\t" + "beq a5,zero,end\n\t" + "beq a5,a4,end\n\t" + "nop\n\t" + "nop\n\t" + ".align 4\n\t" + "loop :\n" + "addi a4,a5,-1\n\t" + "mv a5,a4\n\t" + "bnez a5,loop\n\t" + "nop\n\t" + "end :\n\t" + "nop\n" + : /* output */ + : "m"(cnt), "m"(core), "m"(divVal) /* input */ + : "t1", "a4", "a5" /* destruct description */ + ); +} +#endif + +/****************************************************************************/ /** + * @brief delay us + * + * @param[in] cnt: delay cnt us + * + * @return none + * + *******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt) +{ + ASM_Delay_Us(SystemCoreClockGet(), cnt); +} + +/****************************************************************************/ /** + * @brief delay ms + * + * @param[in] cnt: delay cnt ms + * + * @return none + * + *******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt) +{ + uint32_t i = 0; + uint32_t count = 0; + + if (cnt >= 1024) { + /* delay (n*1024) ms */ + count = 1024; + + for (i = 0; i < (cnt / 1024); i++) { + BL602_Delay_US(1024 * 1000); + } + } + + if (cnt & 0x3FF) { + /* delay (1-1023)ms */ + count = cnt & 0x3FF; + BL602_Delay_US(count * 1000); + } + + //BL602_Delay_US((count<<10)-(count<<4)-(count<<3)); +} +#endif +/*@} end of group DRIVER_Public_Functions */ + +/*@} end of group DRIVER_COMMON */ + +/*@} end of group BL602_Periph_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_dac.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..7f5c6a0dfca2333020f82a6e433b5055396ba02f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_dac.c @@ -0,0 +1,541 @@ +/** + ****************************************************************************** + * @file bl602_dac.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_dac.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ +#define GPIP_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group DAC_Private_Macros */ + +/** @defgroup DAC_Private_Types + * @{ + */ + +/*@} end of group DAC_Private_Types */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/*@} end of group DAC_Private_Variables */ + +/** @defgroup DAC_Global_Variables + * @{ + */ + +/*@} end of group DAC_Global_Variables */ + +/** @defgroup DAC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group DAC_Private_Fun_Declaration */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/*@} end of group DAC_Private_Functions */ + +/** @defgroup DAC_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief DAC initialization + * + * @param cfg: DAC configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); + + /* Set DAC config */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel); + + if (ENABLE == cfg->resetChanA) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + if (ENABLE == cfg->resetChanB) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + /* Clear reset */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief DAC channel A initialization + * + * @param cfg: DAC channel configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); + + /* Set channel A config */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_OUTMUX, cfg->outMux); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanEn); + + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief DAC channel B initialization + * + * @param cfg: DAC channel configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); + + /* Set channel A config */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_OUTMUX, cfg->outMux); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanEn); + + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief Select DAC channel B source + * + * @param src: DAC channel B source selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src)); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, src); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Select DAC channel A source + * + * @param src: DAC channel A source selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src)); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, src); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Select DAC mode + * + * @param mod: DAC mode selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_Mod_SEL(GPIP_DAC_MOD_Type mod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(mod)); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, mod); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable DAC channel B + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanB_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN2); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable DAC channel B + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanB_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN2); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable DAC channel A + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanA_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable DAC channel A + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanA_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Select DAC DMA TX format + * + * @param fmt: DAC DMA TX format selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt)); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, fmt); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable DAC DMA TX + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable DAC DMA TX + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable DAC DMA TX + * + * @param data: The data to be send + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_DMA_WriteData(uint32_t data) +{ + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_WDATA, data); +} + +/****************************************************************************/ /** + * @brief AON and GPIP DAC config + * + * @param cfg: AON and GPIP DAC configuration + * + * @return config success or not + * +*******************************************************************************/ +BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); + CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->mod)); + CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt)); + + /* AON Set DAC config */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel); + + if (ENABLE == cfg->resetChanA) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + if (ENABLE == cfg->resetChanB) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + /* AON Clear reset */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + + if (cfg->dmaEn == DISABLE && cfg->mod == GPIP_DAC_MOD_512K) { + return ERROR; /*512K mode only used in DMA mode*/ + } + + /* GPIP Set DAC config */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, cfg->mod); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* GPIP Set DMA config */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_TX_EN, cfg->dmaEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, cfg->dmaFmt); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AON and GPIP DAC channel A config + * + * @param cfg: AON and GPIP DAC channel A configuration + * + * @return None + * +*******************************************************************************/ +void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src)); + + /* GPIP select source */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, cfg->src); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* GPIP enable or disable channel */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* AON enable or disable channel */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanCovtEn); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief AON and GPIP DAC channel B config + * + * @param cfg: AON and GPIP DAC channel B configuration + * + * @return None + * +*******************************************************************************/ +void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src)); + + /* GPIP select source */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, cfg->src); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* GPIP enable or disable channel */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN2, cfg->chanEn); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* AON enable or disable channel */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanCovtEn); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief DAC channel A set value + * + * @param val: DAC value + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanA_Value(uint16_t val) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_DATA); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_DATA, val); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_DATA, tmpVal); +} + +/****************************************************************************/ /** + * @brief DAC channel B set value + * + * @param val: DAC value + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanB_Value(uint16_t val) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_DATA); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_DATA, val); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_DATA, tmpVal); +} + +/*@} end of group DAC_Public_Functions */ + +/*@} end of group DAC */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_dma.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..961014f35f7e4c7a11227840819aeaf76d64d0ca --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_dma.c @@ -0,0 +1,751 @@ +/** + ****************************************************************************** + * @file bl602_dma.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602.h" +#include "bl602_dma.h" +#include "string.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ +#define DMA_CHANNEL_OFFSET 0x100 +#define DMA_Get_Channel(ch) (DMA_BASE + DMA_CHANNEL_OFFSET + (ch)*0x100) +static intCallback_Type *dmaIntCbfArra[DMA_CH_MAX][DMA_INT_ALL] = { + { NULL, NULL }, + { NULL, NULL }, + { NULL, NULL }, + { NULL, NULL } +}; +static DMA_LLI_Ctrl_Type PingPongListArra[DMA_CH_MAX][2]; + +/*@} end of group DMA_Private_Macros */ + +/** @defgroup DMA_Private_Types + * @{ + */ + +/*@} end of group DMA_Private_Types */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/*@} end of group DMA_Private_Variables */ + +/** @defgroup DMA_Global_Variables + * @{ + */ + +/*@} end of group DMA_Global_Variables */ + +/** @defgroup DMA_Private_Fun_Declaration + * @{ + */ + +/*@} end of group DMA_Private_Fun_Declaration */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief DMA interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void DMA_ALL_IRQHandler(void) +{ + uint32_t tmpVal; + uint32_t intClr; + uint8_t ch; + /* Get DMA register */ + uint32_t DMAChs = DMA_BASE; + + for (ch = 0; ch < DMA_CH_MAX; ch++) { + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); + + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) { + /* Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); + intClr |= (1 << ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); + BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); + + if (dmaIntCbfArra[ch][DMA_INT_TCOMPLETED] != NULL) { + /* Call the callback function */ + dmaIntCbfArra[ch][DMA_INT_TCOMPLETED](); + } + } + } + + for (ch = 0; ch < DMA_CH_MAX; ch++) { + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); + + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) { + /*Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); + intClr |= (1 << ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); + BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); + + if (dmaIntCbfArra[ch][DMA_INT_ERR] != NULL) { + /* Call the callback function */ + dmaIntCbfArra[ch][DMA_INT_ERR](); + } + } + } +} +#endif + +/*@} end of group DMA_Private_Functions */ + +/** @defgroup DMA_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief DMA enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void DMA_Enable(void) +{ + uint32_t tmpVal; + /* Get DMA register */ + uint32_t DMAChs = DMA_BASE; + + tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal); +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(DMA_ALL_IRQn, DMA_ALL_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief DMA disable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void DMA_Disable(void) +{ + uint32_t tmpVal; + /* Get DMA register */ + uint32_t DMAChs = DMA_BASE; + + tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA channel init + * + * @param chCfg: DMA configuration + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(chCfg->ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch)); + CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth)); + CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth)); + CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSzie)); + CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSzie)); + CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph)); + + /* Config channel config */ + BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr); + BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSzie); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSzie); + /* FIXME: how to deal with SLargerD */ + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_SLARGERD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA channel update source memory address and len + * + * @param ch: DMA channel + * @param memAddr: source memoty address + * @param len: source memory data length + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* config channel config*/ + BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA channel update destination memory address and len + * + * @param ch: DMA channel + * @param memAddr: destination memoty address + * @param len: destination memory data length + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* config channel config*/ + BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); +} + +/****************************************************************************/ /** + * @brief Get DMA channel tranfersize + * + * @param ch: DMA channel + * + * @return tranfersize size + * +*******************************************************************************/ +uint32_t DMA_Channel_TranferSize(uint8_t ch) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE); +} + +/****************************************************************************/ /** + * @brief Get DMA channel busy status + * + * @param ch: DMA channel + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief DMA enable + * + * @param ch: DMA channel number + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Enable(uint8_t ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA disable + * + * @param ch: DMA channel number + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Disable(uint8_t ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA init LLI transfer + * + * @param ch: DMA channel number + * @param lliCfg: LLI configuration + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_Init(uint8_t ch, DMA_LLI_Cfg_Type *lliCfg) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph)); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA channel update LLI + * + * @param ch: DMA channel number + * @param LLI: LLI addr + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_Update(uint8_t ch, uint32_t LLI) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* Config channel config */ + //BL_WR_REG(DMAChs, DMA_LLI, LLI); + BL602_MemCpy4((uint32_t *)DMAChs, (uint32_t *)LLI, 4); +} + +/****************************************************************************/ /** + * @brief DMA LLI PingPong Structure Initial + * + * @param dmaPpStruct: DMA LLI PingPong Config Parameter + * + * @return start success or not + * +*******************************************************************************/ +BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct) +{ + //setup lliList + dmaPpStruct->dmaCtrlRegVal.I = 1; + dmaPpStruct->trans_index = 0; + + if (dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_M2P) { + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[0]; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[1]; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; + } else if (dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_P2M) { + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->chache_buf_addr[0]; + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->chache_buf_addr[1]; + } else { + return ERROR; + /*V1.0 version DMA LLI Ping-Pong structure not support P2P & M2M MODE*/ + } + + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX]; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; + + if (dmaPpStruct->is_single_mode == 1) { + /* + * if is is_single_mode is 1 ping-pong will only run once atfer start singal + * or ping-pong will run forever unless stop singal occour + */ + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = 0; + } else { + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]; + } + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; + + DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg); + + DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief DMA LLI PingPong Structure Start + * + * @param dmaPpStruct: None + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct) +{ + if (dmaPpStruct->is_single_mode == 1) { + DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]); + } + + DMA_Channel_Enable(dmaPpStruct->dmaChan); +} + +/****************************************************************************/ /** + * @brief DMA LLI PingPong Structure Stop + * + * @param dmaPpStruct: None + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct) +{ + DMA_Channel_Disable(dmaPpStruct->dmaChan); +} + +/****************************************************************************/ /** + * @brief DMA LLI PingPong Structure Start + * + * @param dmaPpStruct: dma pp struct pointer + * @param Ping_Transfer_len: ping len + * @param Pong_Transfer_len: pong len + * + * @return Succrss or not + * +*******************************************************************************/ +BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len) +{ + struct DMA_Control_Reg dmaCtrlRegVal_temp; + + if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) { + return ERROR; + } + + dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl; + dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp; + + dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl; + dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp; + + DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg); + DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief DMA LLI Start New Transmit for Ping-Pong Buf + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf) +{ + CPU_Interrupt_Disable(DMA_ALL_IRQn); + + if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) { + DMA_LLI_Update(dmaPpBuf->dmaChan, (uint32_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]); + DMA_Channel_Enable(dmaPpBuf->dmaChan); + dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0; + } + + CPU_Interrupt_Enable(DMA_ALL_IRQn); +} + +/****************************************************************************/ /** + * @brief DMA LLI Remove Completed Ping-Pong Buf List + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return Next Ping-Pong Buf List Header + * +*******************************************************************************/ +DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf) +{ + CPU_Interrupt_Disable(DMA_ALL_IRQn); + + dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL; + CPU_Interrupt_Enable(DMA_ALL_IRQn); + return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex]; +} + +/****************************************************************************/ /** + * @brief DMA LLI Append Buf to List + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * @param dmaLliList: New LLI Buf to Append + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList) +{ + DMA_LLI_Ctrl_Type *pLliList = NULL; + CPU_Interrupt_Disable(DMA_ALL_IRQn); + + pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]; + + if (pLliList == NULL) { + dmaLliList->nextLLI = 0; + dmaLliList->dmaCtrl.I = 1; + dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList; + } else { + /*Append to last */ + while (pLliList->nextLLI != 0) { + pLliList = (DMA_LLI_Ctrl_Type *)pLliList->nextLLI; + } + + pLliList->nextLLI = (uint32_t)dmaLliList; + pLliList->dmaCtrl.I = 0; + dmaLliList->nextLLI = 0; + dmaLliList->dmaCtrl.I = 1; + } + + if (DMA_Channel_Is_Busy(dmaPpBuf->dmaChan) == RESET) { + /* DMA stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable) + or has already stopped before this function is called */ + if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) { + /* DMA has already stopped before this function is called */ + DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf); + } + } + + CPU_Interrupt_Enable(DMA_ALL_IRQn); +} + +/****************************************************************************/ /** + * @brief DMA LLi Destroy Ping-Pong Buf + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf) +{ + /* DMA LLI Disable */ + DMA_Channel_Disable(dmaPpBuf->dmaChan); + + if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) { + dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]); + } + + dmaPpBuf->lliListHeader[0] = NULL; + + if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) { + dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]); + } + + dmaPpBuf->lliListHeader[1] = NULL; + dmaPpBuf->idleIndex = 0; +} + +/****************************************************************************/ /** + * @brief Mask/Unmask the DMA interrupt + * + * @param ch: DMA channel number + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void DMA_IntMask(uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + CHECK_PARAM(IS_DMA_INT_TYPE(intType)); + + switch (intType) { + case DMA_INT_TCOMPLETED: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } + + break; + + case DMA_INT_ERR: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + } + + break; + + case DMA_INT_ALL: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief Install DMA interrupt callback function + * + * @param dmaChan: DMA Channel type + * @param intType: DMA interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan)); + CHECK_PARAM(IS_DMA_INT_TYPE(intType)); + + dmaIntCbfArra[dmaChan][intType] = cbFun; +} + +/*@} end of group DMA_Public_Functions */ + +/*@} end of group DMA */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_ef_ctrl.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_ef_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..def7049c96cdc21835d30113787611b50a905851 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_ef_ctrl.c @@ -0,0 +1,1859 @@ +/** + ****************************************************************************** + * @file bl602_sec_ef_ctrl.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_ef_ctrl.h" +#include "ef_data_0_reg.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_EF_CTRL + * @{ + */ + +/** @defgroup SEC_EF_CTRL_Private_Macros + * @{ + */ +#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) +#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) +#define EF_CTRL_DFT_TIMEOUT_VAL (160 * 1000) +#ifndef BOOTROM +#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() +#else +#define EF_CTRL_LOAD_BEFORE_READ_R0 +#endif +#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, EF_CTRL_EFUSE_R0_SIZE / 4) + +/*@} end of group SEC_EF_CTRL_Private_Macros */ + +/** @defgroup SEC_EF_CTRL_Private_Types + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Types */ + +/** @defgroup SEC_EF_CTRL_Private_Variables + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Variables */ + +/** @defgroup SEC_EF_CTRL_Global_Variables + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Global_Variables */ + +/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ + +/** @defgroup SEC_EF_CTRL_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Switch efuse region 0 control to AHB clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) +{ + uint32_t tmpVal; + uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; + + while (EF_Ctrl_Busy() == SET) { + timeout--; + + if (timeout == 0) { + break; + } + } + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Program efuse region 0 + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void) +{ + uint32_t tmpVal; + + /* Select auto mode and select ef clock */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + /* Program */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (1 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (1 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + /* Add delay for POR to be stable */ + BL602_Delay_US(4); + + /* Trigger */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (1 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (1 << EF_CTRL_EF_IF_0_RW_POS) | + (1 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); +} +#endif + +/*@} end of group SEC_EF_CTRL_Private_Functions */ + +/** @defgroup SEC_EF_CTRL_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Load efuse region 0 + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) +{ + uint32_t tmpVal; + uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; + + EF_CTRL_DATA0_CLEAR; + + /* Trigger read */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (1 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + BL602_Delay_US(10); + + /* Wait for efuse control idle*/ + do { + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); + timeout--; + + if (timeout == 0) { + break; + } + } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || + + (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); + + /* Switch to AHB clock */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Check efuse busy status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); + + if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY)) { + return SET; + } + + return RESET; +} +#endif + +/****************************************************************************/ /** + * @brief Check efuse whether finish loading + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); + + if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) { + return SET; + } else { + return RESET; + } +} +#endif + +/****************************************************************************/ /** + * @brief Efuse write debug password + * + * @param passWdLow: password low 32 bits + * @param passWdHigh: password high 32 bits + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read debug password + * + * @param passWdLow: password low 32 bits pointer to store value + * @param passWdHigh: password high 32 bits pointer to store value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh) +{ + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); + *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); +} + +/****************************************************************************/ /** + * @brief Efuse lock reading for passwd + * + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read LDO11 Vout sel trim + * + * @param Ldo11VoutSelValue: Ldo11VoutSelValue + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_Ldo11VoutSel_Opt(uint8_t *Ldo11VoutSelValue) +{ + uint32_t tmp; + Efuse_Ldo11VoutSelTrim_Info_Type *trim = (Efuse_Ldo11VoutSelTrim_Info_Type *)&tmp; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W3)) >> 7; + + if (trim->en) { + if (trim->parity == EF_Ctrl_Get_Trim_Parity(trim->sel_value, 4)) { + *Ldo11VoutSelValue = trim->sel_value; + return SUCCESS; + } + } + return ERROR; +} + +/****************************************************************************/ /** + * @brief Efuse read LDO11 Vout sel trim + * + * @param TxPower: TxPower + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_TxPower_ATE(int8_t *TxPower) +{ + uint32_t tmp; + Efuse_TxPower_Info_Type *trim = (Efuse_TxPower_Info_Type *)&tmp; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W3)) >> 0; + + //if(trim->en){ + if ((tmp >> 17) & 0x01) { //old en bit will be no longer used, now use bit17 as en bit + if (trim->parity == EF_Ctrl_Get_Trim_Parity(trim->txpower, 5)) { + if (trim->txpower >= 16) { + *TxPower = trim->txpower - 32; + } else { + *TxPower = trim->txpower; + } + + return SUCCESS; + } + } + return ERROR; +} + +/****************************************************************************/ /** + * @brief Efuse lock writing for passwd + * + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read security configuration + * + * @param cfg: security configuration pointer + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read security configuration + * + * @param cfg: security configuration pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + + cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE); + cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS); + cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN); + cfg->ef_no_hd_boot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_NO_HD_BOOT_EN); +} + +/****************************************************************************/ /** + * @brief Efuse write security boot configuration + * + * @param sign[1]: Sign configuration pointer + * @param aes[1]: AES configuration pointer + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]); + + if (aes[0] != EF_CTRL_SF_AES_NONE) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN, 1); + } + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse write security boot configuration + * + * @param sign[1]: Sign configuration pointer + * @param aes[1]: AES configuration pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE); + sign[0] = (EF_Ctrl_Sign_Type)(tmpVal2 & 0x01); + + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN); + + if (tmpVal2) { + aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE); + } else { + aes[0] = EF_CTRL_SF_AES_NONE; + } +} + +/****************************************************************************/ /** + * @brief Get whether do RC32K and RC32M trim + * + * @param None + * + * @return 1 for enable trim RC32M and RC32K, 0 for not + * +*******************************************************************************/ +uint8_t EF_Ctrl_Get_Trim_Enable(void) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + + return BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_TRIM_EN); +} + +/****************************************************************************/ /** + * @brief Analog Trim parity calculate + * + * @param val: Value of efuse trim data + * @param len: Length of bit to calculate + * + * @return Parity bit value + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) +{ + uint8_t cnt = 0; + uint8_t i = 0; + + for (i = 0; i < len; i++) { + if (val & (1 << i)) { + cnt++; + } + } + + return cnt & 0x01; +} +#endif + +/****************************************************************************/ /** + * @brief Efuse write analog trim + * + * @param index: index of analog trim + * @param trim: trim value + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (index == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, trim); + } + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read analog trim + * + * @param index: index of analog trim + * @param trim: trim value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + if (index == 0) { + *trim = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + } +} + +/****************************************************************************/ /** + * @brief Efuse read RC32M trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) +{ + uint32_t tmpVal = 0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + trim->trimRc32mCodeFrExt = (tmpVal >> 10) & 0xff; + trim->trimRc32mCodeFrExtParity = (tmpVal >> 18) & 0x01; + trim->trimRc32mExtCodeEn = (tmpVal >> 19) & 0x01; +} +#endif + +/****************************************************************************/ /** + * @brief Efuse read RC32K trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) +{ + uint32_t tmpVal = 0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + trim->trimRc32kCodeFrExt = (tmpVal >> 20) & 0x3ff; + trim->trimRc32kCodeFrExtParity = (tmpVal >> 30) & 0x01; + trim->trimRc32kExtCodeEn = (tmpVal >> 31) & 0x01; +} +#endif + +/****************************************************************************/ /** + * @brief Efuse read TSEN trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) +{ + uint32_t tmpVal = 0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + trim->tsenRefcodeCornerEn = tmpVal & 0x01; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + trim->tsenRefcodeCorner = tmpVal & 0xfff; + trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); + trim->tsenRefcodeCornerVersion = (tmpVal >> 30) & 0x01; +} + +/****************************************************************************/ /** + * @brief Efuse read ADC Gain trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) +{ + uint32_t tmpVal = 0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + trim->adcGainCoeff = (tmpVal >> 1) & 0xfff; + trim->adcGainCoeffParity = (tmpVal >> 13) & 0x01; + trim->adcGainCoeffEn = (tmpVal >> 14) & 0x01; +} + +/****************************************************************************/ /** + * @brief Efuse write software usage + * + * @param index: index of software usage + * @param usage: usage value + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) +{ + /* switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (index == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage); + } + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read software usage + * + * @param index: index of software usage + * @param usage: usage value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + if (index == 0) { + *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); + } +} + +/****************************************************************************/ /** + * @brief Efuse read software usage + * + * @param index: index of software usage + * @param program: usage value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + + if (index == 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0); + } + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse write MAC address + * + * @param mac[6]: MAC address buffer + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* The low 32 bits */ + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); + /* The high 16 bits */ + tmpVal = machigh[0] + (machigh[1] << 8); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse Ctrl get zero bit count + * + * @param val: Value to count + * + * @return Zero bit count + * +*******************************************************************************/ +static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) +{ + uint32_t cnt = 0; + uint32_t i = 0; + + for (i = 0; i < 8; i++) { + if ((val & (1 << i)) == 0) { + cnt += 1; + } + } + + return cnt; +} + +/****************************************************************************/ /** + * @brief Efuse read MAC address + * + * @param mac[6]: MAC address buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal; + uint32_t i = 0; + uint32_t cnt = 0; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); + BL_WRWD_TO_BYTEP(maclow, tmpVal); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + machigh[0] = tmpVal & 0xff; + machigh[1] = (tmpVal >> 8) & 0xff; + + /* Check parity */ + for (i = 0; i < 6; i++) { + cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + + if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { + /* Change to network order */ + for (i = 0; i < 3; i++) { + tmpVal = mac[i]; + mac[i] = mac[5 - i]; + mac[5 - i] = tmpVal; + } + + return SUCCESS; + } else { + return ERROR; + } +} + +/****************************************************************************/ /** + * @brief Efuse read MAC address + * + * @param mac[7]: MAC address buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); + BL_WRWD_TO_BYTEP(maclow, tmpVal); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + machigh[0] = tmpVal & 0xff; + machigh[1] = (tmpVal >> 8) & 0xff; + machigh[2] = (tmpVal >> 16) & 0xff; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse lock writing for MAC address + * + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_MAC_Address(uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Whether a value bits is all zero + * + * @param val: value to check + * @param start: start bit + * @param len: total length of bits to check + * + * @return 1 for all bits zero 0 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) +{ + uint32_t mask = 0; + + val = (val >> start); + + if (len >= 32) { + mask = 0xffffffff; + } else { + mask = (1 << len) - 1; + } + + if ((val & mask) == 0) { + return 1; + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief Whether MAC address slot is empty + * + * @param slot: MAC address slot + * @param reload: whether reload to check + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload) +{ + uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff; + uint32_t part1Empty = 0, part2Empty = 0; + + if (slot == 0) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); + tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + } else if (slot == 1) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0); + tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); + } else if (slot == 2) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); + tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); + } + + part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32)); + part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22)); + + return (part1Empty && part2Empty); +} + +/****************************************************************************/ /** + * @brief Efuse write optional MAC address + * + * @param slot: MAC address slot + * @param mac[6]: MAC address buffer + * @param program: Whether program + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal; + uint32_t i = 0, cnt; + + if (slot >= 3) { + return ERROR; + } + + /* Change to local order */ + for (i = 0; i < 3; i++) { + tmpVal = mac[i]; + mac[i] = mac[5 - i]; + mac[5 - i] = tmpVal; + } + + if (slot == 2) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + } else { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + } + + /* The low 32 bits */ + if (slot == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); + } else if (slot == 1) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0, BL_RDWD_FRM_BYTEP(maclow)); + } else if (slot == 2) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, BL_RDWD_FRM_BYTEP(maclow)); + } + + /* The high 16 bits */ + tmpVal = machigh[0] + (machigh[1] << 8); + cnt = 0; + + for (i = 0; i < 6; i++) { + cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + + tmpVal |= ((cnt & 0x3f) << 16); + + if (slot == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); + } else if (slot == 1) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, tmpVal); + } else if (slot == 2) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, tmpVal); + } + + if (program) { + if (slot == 2) { + EF_Ctrl_Program_Efuse_0(); + } else { + EF_Ctrl_Program_Efuse_0(); + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse read optional MAC address + * + * @param slot: MAC address slot + * @param mac[6]: MAC address buffer + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal = 0; + uint32_t i = 0; + uint32_t cnt = 0; + + if (slot >= 3) { + return ERROR; + } + + /* Trigger read data from efuse */ + if (reload) { + if (slot == 2) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } else { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + } + + if (slot == 0) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); + } else if (slot == 1) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0); + } else if (slot == 2) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); + } + + BL_WRWD_TO_BYTEP(maclow, tmpVal); + + if (slot == 0) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + } else if (slot == 1) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); + } else if (slot == 2) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); + } + + machigh[0] = tmpVal & 0xff; + machigh[1] = (tmpVal >> 8) & 0xff; + + /* Check parity */ + for (i = 0; i < 6; i++) { + cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + + if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { + /* Change to network order */ + for (i = 0; i < 3; i++) { + tmpVal = mac[i]; + mac[i] = mac[5 - i]; + mac[5 - i] = tmpVal; + } + + return SUCCESS; + } else { + return ERROR; + } +} + +/****************************************************************************/ /** + * @brief Efuse read chip ID + * + * @param chipID[8]: Chip ID buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) +{ + chipID[6] = 0; + chipID[7] = 0; + return EF_Ctrl_Read_MAC_Address(chipID); +} + +/****************************************************************************/ /** + * @brief Efuse read device info + * + * @param deviceInfo: Device info pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo) +{ + uint32_t tmpVal; + uint32_t *p = (uint32_t *)deviceInfo; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + *p = tmpVal; +} + +/****************************************************************************/ /** + * @brief Whether Capcode slot is empty + * + * @param slot: Cap code slot + * @param reload: Whether reload + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_CapCode_Slot_Empty(uint8_t slot, uint8_t reload) +{ + uint32_t tmp = 0xffffffff; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if (slot == 0) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + return (EF_Ctrl_Is_All_Bits_Zero(tmp, 2, 8)); + } else if (slot == 1) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); + return (EF_Ctrl_Is_All_Bits_Zero(tmp, 22, 8)); + } else if (slot == 2) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); + return (EF_Ctrl_Is_All_Bits_Zero(tmp, 22, 8)); + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Efuse write Cap code + * + * @param slot: Cap code slot + * @param code: Cap code value + * @param program: Whether program + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program) +{ + uint32_t tmp; + uint8_t trim; + + if (slot >= 3) { + return ERROR; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + EF_CTRL_LOAD_BEFORE_READ_R0; + + if (slot == 0) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + } else if (slot == 1) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); + } else if (slot == 2) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); + } + + trim = code; + trim |= ((EF_Ctrl_Get_Trim_Parity(code, 6)) << 6); + trim |= (1 << 7); + + if (slot == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp | (trim << 2)); + } else if (slot == 1) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, tmp | (trim << 22)); + } else if (slot == 2) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, tmp | (trim << 22)); + } + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } + + while (SET == EF_Ctrl_Busy()) + ; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse read Cap code + * + * @param slot: Cap code slot + * @param code: Cap code pointer + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload) +{ + uint32_t tmp; + Efuse_Capcode_Info_Type *trim = (Efuse_Capcode_Info_Type *)&tmp; + + if (slot >= 3) { + return ERROR; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if (slot == 0) { + tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0)) >> 2; + } else if (slot == 1) { + tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1)) >> 22; + } else if (slot == 2) { + tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH)) >> 22; + } + + if (trim->en) { + if (trim->parity == EF_Ctrl_Get_Trim_Parity(trim->capCode, 6)) { + *code = trim->capCode; + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Whether power offset slot is empty + * + * @param slot: Power offset code slot + * @param reload: Whether reload + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload) +{ + uint32_t tmp1 = 0xffffffff; + uint32_t part1Empty = 0, part2Empty = 0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if (slot == 0) { + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 15, 17)); + part2Empty = 1; + } else if (slot == 1) { + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); + part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 16)); + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 1)); + } else if (slot == 2) { + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); + part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 16)); + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 1, 1)); + } + + return (part1Empty && part2Empty); +} + +/****************************************************************************/ /** + * @brief Efuse write power offset + * + * @param slot: Power offset slot + * @param pwrOffset[3]: Power offset value array + * @param program: Whether program + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program) +{ + uint64_t tmp = 0; + uint32_t k = 0; + uint64_t Value = 0; + uint8_t parity; + + if (slot >= 3) { + return ERROR; + } + + for (k = 0; k < 3; k++) { + /* Use 5 bits as signed value */ + if (pwrOffset[k] > 15) { + pwrOffset[k] = 15; + } + + if (pwrOffset[k] < -16) { + pwrOffset[k] = -16; + } + + tmp = ((uint64_t)((pwrOffset[k]) & 0x1f)) << (k * 5); + Value += tmp; + } + + parity = EF_Ctrl_Get_Trim_Parity(Value, 15); + + if (slot == 0) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + tmp |= (Value << 16); + tmp |= (1 << 15); + tmp |= (uint32_t)(parity << 31); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp); + } else if (slot == 1) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); + tmp |= (Value << 0); + tmp |= (uint32_t)(parity << 15); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2, tmp); + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + tmp |= (1 << 0); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp); + } else if (slot == 2) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); + tmp |= (Value << 16); + tmp |= (uint32_t)(parity << 31); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2, tmp); + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + tmp |= (1 << 1); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp); + } + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } + + while (SET == EF_Ctrl_Busy()) + ; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse read poweroffset value + * + * @param slot: Power offset slot + * @param pwrOffset[3]: Power offset array + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload) +{ + uint64_t pwrOffsetValue = 0; + + uint32_t tmp = 0, k; + uint8_t en = 0, parity = 0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if (slot == 0) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + en = (tmp >> 15) & 0x01; + pwrOffsetValue = (tmp >> 16) & 0x7fff; + parity = (tmp >> 31) & 0x01; + } else if (slot == 1) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); + pwrOffsetValue = (tmp >> 0) & 0x7fff; + parity = (tmp >> 15) & 0x01; + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + en = (tmp >> 0) & 0x01; + } else if (slot == 2) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); + pwrOffsetValue = (tmp >> 16) & 0x7fff; + parity = (tmp >> 31) & 0x01; + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + en = (tmp >> 1) & 0x01; + } + + if (en) { + if (parity == EF_Ctrl_Get_Trim_Parity(pwrOffsetValue, 15)) { + for (k = 0; k < 3; k++) { + tmp = (pwrOffsetValue >> (k * 5)) & 0x1f; + + if (tmp >= 16) { + pwrOffset[k] = tmp - 32; + } else { + pwrOffset[k] = tmp; + } + } + + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Efuse write AES key + * + * @param index: index of key slot + * @param keyData: key data buffer + * @param len: key data length in words + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) +{ + uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); + + if (index > 5) { + return; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Every key is 4 words len*/ + BL602_MemCpy4(pAESKeyStart0 + index * 4, keyData, len); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read AES key from specified region and index + * + * @param index: index of key slot + * @param keyData: key data buffer + * @param len: key data length in words + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) +{ + uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); + + if (index > 5) { + return; + } + + /* Trigger read data from efuse*/ + EF_CTRL_LOAD_BEFORE_READ_R0; + + /* Every key is 4 words len*/ + BL602_MemCpy4(keyData, pAESKeyStart0 + index * 4, len); +} + +/****************************************************************************/ /** + * @brief Efuse lock writing for aes key + * + * @param index: index of key slot + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) +{ + uint32_t tmpVal; + + if (index > 5) { + return; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + + if (index <= 3) { + tmpVal |= (1 << (index + 19)); + } else { + tmpVal |= (1 << (index + 19)); + tmpVal |= (1 << (index - 4 + 13)); + } + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse lock reading for aes key + * + * @param index: index of key slot + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) +{ + uint32_t tmpVal; + + if (index > 5) { + return; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + tmpVal |= (1 << (index + 26)); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Program data to efuse region 0 + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Add delay for CLK to be stable */ + BL602_Delay_US(4); + + BL602_MemCpy4(pEfuseStart0 + index, data, len); + + EF_Ctrl_Program_Efuse_0(); +} + +/****************************************************************************/ /** + * @brief Read data from efuse region 0 + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + BL602_MemCpy4(data, pEfuseStart0 + index, len); +} + +/****************************************************************************/ /** + * @brief Write data to efuse region 0 without program + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Add delay for CLK to be stable */ + BL602_Delay_US(4); + + BL602_MemCpy4(pEfuseStart0 + index, data, len); +} + +/****************************************************************************/ /** + * @brief Read data from efuse region 0 without reload + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + + BL602_MemCpy4(data, pEfuseStart0 + index, len); +} + +/****************************************************************************/ /** + * @brief Clear efuse data register + * + * @param index: index of efuse in word + * @param len: data length + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + uint32_t i = 0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Clear data */ + for (i = 0; i < len; i++) { + pEfuseStart0[index + i] = 0; + } +} +#endif + +/****************************************************************************/ /** + * @brief efuse ctrl crc enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Crc_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET); + BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN); + BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief efuse ctrl get crc busy status + * + * @param None + * + * @return DISABLE or ENABLE + * +*******************************************************************************/ +BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); + return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY); +} + +/****************************************************************************/ /** + * @brief efuse ctrl set golden value + * + * @param goldenValue: Crc golden value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) +{ + BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); +} + +/****************************************************************************/ /** + * @brief efuse ctrl get crc result + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Crc_Result(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); + return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR); +} + +/*@} end of group SEC_EF_CTRL_Public_Functions */ + +/*@} end of group SEC_EF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_glb.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_glb.c new file mode 100644 index 0000000000000000000000000000000000000000..6464a5960f2ba6192861ff8da069aea84cd7a57e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_glb.c @@ -0,0 +1,2619 @@ +/** + ****************************************************************************** + * @file bl602_glb.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_glb.h" +#include "bl602_hbn.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Private_Macros + * @{ + */ +#define GLB_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } +#define GLB_GPIO_Get_Reg(pin) (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4) +#define GLB_GPIO_INT0_NUM (23) +#define GLB_REG_BCLK_DIS_TRUE (*(volatile uint32_t *)(0x40000FFC) = (0x00000001)) +#define GLB_REG_BCLK_DIS_FALSE (*(volatile uint32_t *)(0x40000FFC) = (0x00000000)) +#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) + +/*@} end of group GLB_Private_Macros */ + +/** @defgroup GLB_Private_Types + * @{ + */ + +/*@} end of group GLB_Private_Types */ + +/** @defgroup GLB_Private_Variables + * @{ + */ +static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL] = { NULL }; +static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL }; +static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + +/*@} end of group GLB_Private_Variables */ + +/** @defgroup GLB_Global_Variables + * @{ + */ + +/*@} end of group GLB_Global_Variables */ + +/** @defgroup GLB_Private_Fun_Declaration + * @{ + */ + +/*@} end of group GLB_Private_Fun_Declaration */ + +/** @defgroup GLB_Private_Functions + * @{ + */ + +/*@} end of group GLB_Private_Functions */ + +/** @defgroup GLB_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief get root clock selection + * + * @param None + * + * @return root clock selection + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) { + case 0: + return GLB_ROOT_CLK_RC32M; + + case 1: + return GLB_ROOT_CLK_XTAL; + + case 2: + return GLB_ROOT_CLK_PLL; + + case 3: + return GLB_ROOT_CLK_PLL; + + default: + return GLB_ROOT_CLK_RC32M; + } +} +#endif + +/****************************************************************************/ /** + * @brief Set System clock divider + * + * @param hclkDiv: HCLK divider + * @param bclkDiv: BCLK divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* recommended: fclk<=160MHz, bclk<=80MHz */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + SystemCoreClockSet(SystemCoreClockGet() / ((uint16_t)hclkDiv + 1)); + GLB_CLK_SET_DUMMY_WAIT; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get Bus clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); +} +#endif + +/****************************************************************************/ /** + * @brief Get CPU clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); +} +#endif + +/****************************************************************************/ /** + * @brief update SystemCoreClock value + * + * @param xtalType: XTAL frequency type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType) +{ + CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType)); + + switch (xtalType) { + case GLB_PLL_XTAL_NONE: + break; + + case GLB_PLL_XTAL_24M: + SystemCoreClockSet(24000000); + break; + + case GLB_PLL_XTAL_32M: + SystemCoreClockSet(32000000); + break; + + case GLB_PLL_XTAL_38P4M: + SystemCoreClockSet(38400000); + break; + + case GLB_PLL_XTAL_40M: + SystemCoreClockSet(40000000); + break; + + case GLB_PLL_XTAL_26M: + SystemCoreClockSet(26000000); + break; + + case GLB_PLL_XTAL_RC32M: + SystemCoreClockSet(32000000); + break; + + default: + break; + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set System clock + * + * @param xtalType: XTAL frequency type + * @param clkFreq: clock frequency selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType)); + CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq)); + + /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + + /* Before config XTAL and PLL ,make sure root clk is from RC32M */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + GLB_Set_System_CLK_Div(0, 0); + SystemCoreClockSet(32 * 1000 * 1000); + + /* Select PKA clock from hclk */ + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_HCLK); + + if (xtalType == GLB_PLL_XTAL_NONE) { + if (clkFreq == GLB_SYS_CLK_RC32M) { + return SUCCESS; + } else { + return ERROR; + } + } + + if (xtalType != GLB_PLL_XTAL_RC32M) { + /* power on xtal first */ + AON_Power_On_XTAL(); + } + + /* always power up PLL and enable all PLL clock output */ + PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType); + BL602_Delay_US(55); + PDS_Enable_PLL_All_Clks(); + + /* reg_pll_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + + /* select pll output clock before select root clock */ + if (clkFreq >= GLB_SYS_CLK_PLL48M) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_PLL48M); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + } + + /* select root clock */ + switch (clkFreq) { + case GLB_SYS_CLK_RC32M: + break; + + case GLB_SYS_CLK_XTAL: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + Update_SystemCoreClockWith_XTAL(xtalType); + break; + + case GLB_SYS_CLK_PLL48M: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(48 * 1000 * 1000); + break; + + case GLB_SYS_CLK_PLL120M: + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(120 * 1000 * 1000); + break; + + case GLB_SYS_CLK_PLL160M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(160 * 1000 * 1000); + break; + + case GLB_SYS_CLK_PLL192M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(192 * 1000 * 1000); + break; + + default: + break; + } + + GLB_CLK_SET_DUMMY_WAIT; + + /* select PKA clock from 120M since we power up PLL */ + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_PLL120M); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief This is demo for user that use RC32M as default bootup clock instead of PLL,when APP is + * started, this function can be called to set PLL to 160M + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void) +{ + SF_Ctrl_Cfg_Type sfCtrlCfg = { + .owner = SF_CTRL_OWNER_IAHB, + .clkDelay = 1, + .clkInvert = 1, + .rxClkInvert = 1, + .doDelay = 0, + .diDelay = 0, + .oeDelay = 0, + }; + /* Use RC32M as PLL ref source to set up PLL to 160M */ + GLB_Set_System_CLK(GLB_PLL_XTAL_RC32M, GLB_SYS_CLK_PLL160M); + /* Flash controller also need changes since system (bus) clock changed */ + SF_Ctrl_Enable(&sfCtrlCfg); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set BLE clock + * + * @param enable: Enable or disable BLE clock + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set wifi core clock divider + * + * @param clkDiv: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((clkDiv <= 0x3)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFI_MAC_CORE_DIV, clkDiv); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set wifi encryption clock + * + * @param clkDiv: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((clkDiv <= 0x3)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFI_MAC_WT_DIV, clkDiv); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DMA clock + * + * @param enable: Enable or disable BLE clock + * @param clk: DMA clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); + + if (enable) { + tmpVal2 |= (1 << clk); + } else { + tmpVal2 &= (~(1 << clk)); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set IR clock divider + * + * @param enable: enable or disable IR clock + * @param clkSel: IR clock type + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel)); + CHECK_PARAM((div <= 0x3F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set sflash clock + * + * @param enable: enable or disable sflash clock + * @param clkSel: sflash clock type + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + GLB_PLL_CLK_Type clk; + + CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel)); + CHECK_PARAM((div <= 0x7)); + + /* disable SFLASH clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Select flash clock, all Flash CLKs are divied by PLL_480M */ + clk = GLB_PLL_CLK_480M; + PDS_Enable_PLL_Clk((PDS_PLL_CLK_Type)clk); + /* clock divider */ + /* Select flash clock, all Flash CLKs are divied by PLL_480M */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div); + + switch (clkSel) { + case GLB_SFLASH_CLK_120M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0); + break; + + case GLB_SFLASH_CLK_XTAL: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1); + break; + + case GLB_SFLASH_CLK_48M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3); + break; + + case GLB_SFLASH_CLK_80M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1); + break; + + case GLB_SFLASH_CLK_BCLK: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2); + break; + + case GLB_SFLASH_CLK_96M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3); + break; + + default: + break; + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* enable or disable flash clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set UART clock + * + * @param enable: Enable or disable UART clock + * @param clkSel: UART clock type + * @param div: UART clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((div <= 0x7)); + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + /* disable UART clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Set div */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Select clock source for uart */ + HBN_Set_UART_CLK_Sel(clkSel); + + /* Set enable or disable */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set I2C clock + * + * @param enable: Enable or disable I2C clock + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set SPI clock + * + * @param enable: Enable or disable SPI clock + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((div <= 0x1F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select PKA clock source + * + * @param clkSel: PKA clock selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software system reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL602_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software CPU reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL602_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software power on reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL602_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Reset slave 1 + * + * @param slave1: slave num + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal &= (~(1 << slave1)); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal |= (1 << slave1); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal &= (~(1 << slave1)); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief clock gate + * + * @param enable: ENABLE or DISABLE + * @param slave1: AHB slaveClk type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1) +{ + uint32_t tmpVal = 0; + + if ((BL_AHB_SLAVE1_GLB == slave1) || (BL_AHB_SLAVE1_TZ2 == slave1) || + (BL_AHB_SLAVE1_CCI == slave1) || (BL_AHB_SLAVE1_L1C == slave1) || + (BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM == slave1)) { + /* not support */ + return ERROR; + } + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + + if (enable) { + /* clear bit means clock gate */ + tmpVal &= (~(1 << slave1)); + } else { + /* set bit means clock pass */ + tmpVal |= (1 << slave1); + } + + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX init + * + * @param BmxCfg: BMX config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler); + Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get BMX error status + * + * @param errType: BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + + if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET; + } +} + +/****************************************************************************/ /** + * @brief Get BMX error address + * + * @param None + * + * @return NP BMX error address + * +*******************************************************************************/ +uint32_t GLB_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR); +} + +/****************************************************************************/ /** + * @brief BMX error interrupt callback install + * + * @param intType: BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType)); + + glbBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void) +{ + BMX_ERR_INT_Type intType; + + for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) { + if (glbBmxErrIntCbfArra[intType] != NULL) { + glbBmxErrIntCbfArra[intType](); + } + } + + while (1) { + MSG("BMX_ERR_IRQHandler\r\n"); + BL602_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief BMX timeout interrupt callback install + * + * @param intType: BMX timeout interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType)); + + glbBmxToIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX Time Out interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_TO_IRQHandler(void) +{ + BMX_TO_INT_Type intType; + + for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) { + if (glbBmxToIntCbfArra[intType] != NULL) { + glbBmxToIntCbfArra[intType](); + } + } + + while (1) { + MSG("BMX_TO_IRQHandler\r\n"); + BL602_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief set sram_ret value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_RET(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_RET, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_ret value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_RET(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_RET); +} + +/****************************************************************************/ /** + * @brief set sram_slp value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_SLP, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_slp value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_SLP(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_SLP); +} + +/****************************************************************************/ /** + * @brief set sram_param value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_parm value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_PARM(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_PARM); +} + +/****************************************************************************/ /** + * @brief select EM type + * + * @param emType: EM type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_EM_TYPE(emType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType); + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap UART gpio pins sig function + * + * @param swapSel: UART swap set gpio pins selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((swapSel <= 0x7)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, swapSel); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap JTAG gpio pins function + * + * @param swapSel: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((swapSel <= 0x3F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap SPI0 MOSI with MISO + * + * @param newState: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select SPI_0 act mode + * + * @param mod: SPI work mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief use internal flash + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief use external flash + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Deswap internal flash IO3 and IO0 pin + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Swap internal flash IO3 and IO0 pin + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set MTimer clock + * + * @param enable: enable or disable MTimer clock + * @param clkSel: clock selection + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel)); + CHECK_PARAM((div <= 0x1FFFF)); + + /* disable MTimer clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set ADC clock + * + * @param enable: enable frequency divider or not + * @param clkSel: ADC clock selection + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel)); + + /* disable ADC clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + } + + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DAC clock + * + * @param enable: enable frequency divider or not + * @param clkSel: ADC clock selection + * @param div: src divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_DAC_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + + if (clkSel == GLB_DAC_CLK_32M) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_CLK_SRC_SEL); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_CLK_SRC_SEL); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } + + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief platform wakeup will becomes one of pds_wakeup source + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Platform_Wakeup_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief platform wakeup will not becomes one of pds_wakeup source + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Platform_Wakeup_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select DIG clock source + * + * @param clkSel: DIG clock selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel) +{ + uint32_t tmpVal; + uint32_t dig512kEn; + uint32_t dig32kEn; + + /* disable DIG512K and DIG32K clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); + dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + /* repristinate DIG512K and DIG32K clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DIG 512K clock + * + * @param enable: enable or disable DIG 512K clock + * @param compensation: enable or disable DIG 512K clock compensation + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + if (compensation) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } + + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DIG 32K clock + * + * @param enable: enable or disable DIG 32K clock + * @param compensation: enable or disable DIG 32K clock compensation + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint8_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + if (compensation) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); + } + + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set BT coex signal + * + * @param enable: ENABLE or DISABLE, if enable, the AP JTAG will be replaced by BT Coex Signal + * @param bandWidth: BT Bandwidth + * @param pti: BT Packet Traffic Information + * @param channel: BT Channel + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, uint8_t pti, uint8_t channel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_BT_BANDWIDTH_TYPE(bandWidth)); + CHECK_PARAM((pti <= 0xF)); + CHECK_PARAM((channel <= 78)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_BW, bandWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_PTI, pti); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_CHANNEL, channel); + BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL); + + if (enable) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 0); + } + + BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select UART signal function + * + * @param sig: UART signal + * @param fun: UART function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun) +{ + uint32_t sig_pos = 0; + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig)); + CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0); + sig_pos = (sig * 4); + /* Clear original val */ + tmpVal &= (~(0xf << sig_pos)); + /* Set new value */ + tmpVal |= (fun << sig_pos); + BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select ir rx gpio (gpio11~gpio13) + * + * @param gpio: IR gpio selected + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio) +{ + uint32_t tmpVal = 0; + + /* Select gpio between gpio11 and gpio13 */ + if (gpio > 10 && gpio < 14) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 10); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + /* Close ir rx */ + if (gpio == 0) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Enable(void) +{ + uint32_t tmpVal = 0; + + /* Enable led driver */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Disable(void) +{ + uint32_t tmpVal = 0; + + /* Disable led driver */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set ir led driver ibias + * + * @param ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias) +{ + uint32_t tmpVal = 0; + + /* Set driver ibias */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0xF); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO initialization + * + * @param cfg: GPIO configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) +{ + uint8_t gpioPin = cfg->gpioPin; + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + + /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */ + /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */ + /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */ + /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */ + + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + if (gpioPin % 2 == 0) { + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + /* Set input or output */ + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + tmpOut |= (1 << pos); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } + + /* Set pull up or down */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + + if (cfg->pullType == GPIO_PULL_UP) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + } else if (cfg->pullType == GPIO_PULL_DOWN) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + } + } else { + /* analog mode */ + + /* clear ie && oe */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + tmpOut &= ~(1 << pos); + + /* clear pu && pd */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + } + + /* set drive && smt && func */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun); + } else { + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + /* Set input or output */ + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + tmpOut |= (1 << pos); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + + /* Set pull up or down */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + + if (cfg->pullType == GPIO_PULL_UP) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + } else if (cfg->pullType == GPIO_PULL_DOWN) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + } + } else { + /* analog mode */ + + /* clear ie && oe */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + tmpOut &= ~(1 << pos); + + /* clear pu && pd */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + } + + /* set drive && smt && func */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + *pOut = tmpOut; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief init GPIO function in pin list + * + * @param gpioFun: GPIO pin function + * @param pinList: GPIO pin list + * @param cnt: GPIO pin count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = (uint8_t)gpioFun, + .gpioMode = GPIO_MODE_AF, + .pullType = GPIO_PULL_UP, + .drive = 1, + .smtCtrl = 1 + }; + + if (gpioFun == GPIO_FUN_ANALOG) { + gpioCfg.gpioMode = GPIO_MODE_ANALOG; + } + + for (uint8_t i = 0; i < cnt; i++) { + gpioCfg.gpioPin = pinList[i]; + GLB_GPIO_Init(&gpioCfg); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set input function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + + if (gpioPin % 2 == 0) { + /* [0] is ie */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } else { + /* [16] is ie */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set input function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + + if (gpioPin % 2 == 0) { + /* [0] is ie */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } else { + /* [16] is ie */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set output function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34); + tmpVal = tmpVal | (1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief GPIO set output function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34); + tmpVal = tmpVal & ~(1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief GPIO set High-Z + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin) +{ + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* select GPIO_FUN_GPIO as FUNC_SEL */ + if (gpioPin % 2 == 0) { + tmpVal = (tmpVal & 0xffff0000); + tmpVal |= 0x0B00; + } else { + tmpVal = (tmpVal & 0x0000ffff); + tmpVal |= (0x0B00 << 16); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + /* Disable output anyway*/ + *pOut = tmpOut; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief GPIO set Pull up + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* Set Pull up */ + if (gpioPin % 2 == 0) { + tmpVal &= (~(1 << 5)); + tmpVal |= (1 << 4); + } else { + tmpVal &= (~(1 << 21)); + tmpVal |= (1 << 20); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set Pull down + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* Set Pull up */ + if (gpioPin % 2 == 0) { + tmpVal &= (~(1 << 4)); + tmpVal |= (1 << 5); + } else { + tmpVal &= (~(1 << 20)); + tmpVal |= (1 << 21); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GPIO function + * + * @param gpioPin: GPIO type + * + * @return GPIO function + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + if (gpioPin % 2 == 0) { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL); + } else { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL); + } +} +#endif + +/****************************************************************************/ /** + * @brief Get GPIO0-GPIO5 real function + * + * @param gpioPin: GPIO type + * + * @return GPIO real function + * +*******************************************************************************/ +GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + CHECK_PARAM((gpioPin <= GLB_GPIO_PIN_5)); + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + if (gpioPin % 2 == 0) { + return (GLB_GPIO_REAL_MODE_Type)BL_GET_REG_BITS_VAL(tmpVal, GLB_REAL_GPIO_0_FUNC_SEL); + } else { + return (GLB_GPIO_REAL_MODE_Type)BL_GET_REG_BITS_VAL(tmpVal, GLB_REAL_GPIO_1_FUNC_SEL); + } +} + +/****************************************************************************/ /** + * @brief Write GPIO + * + * @param gpioPin: GPIO type + * @param val: GPIO value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val) +{ + uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2)); + uint32_t pos = gpioPin % 32; + uint32_t tmpOut; + + tmpOut = *pOut; + + if (val > 0) { + tmpOut |= (1 << pos); + } else { + tmpOut &= (~(1 << pos)); + } + + *pOut = tmpOut; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read GPIO + * + * @param gpioPin: GPIO type + * + * @return GPIO value + * +*******************************************************************************/ +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin) +{ + uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2)); + uint32_t pos = gpioPin % 32; + + if ((*p) & (1 << pos)) { + return 1; + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask + * + * @param gpioPin: GPIO type + * @param intMask: GPIO interrupt MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1); + + if (intMask == MASK) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask + * + * @param gpioPin: GPIO type + * @param intClear: GPIO interrupt clear or unclear + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1); + + if (intClear == SET) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GLB GPIO interrrupt status + * + * @param gpioPin: GPIO type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal = 0; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1); + } + + return (tmpVal & (1 << gpioPin)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief Clear GLB GPIO interrrupt status + * + * @param gpioPin: GPIO type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1); + tmpVal = tmpVal | (1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mode + * + * @param gpioPin: GPIO type + * @param intCtlMod: GPIO interrupt control mode + * @param intTrgMod: GPIO interrupt trigger mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod) +{ + uint32_t tmpVal; + uint32_t tmpGpioPin; + + CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod)); + CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod)); + + if (gpioPin < GLB_GPIO_PIN_10) { + /* GPIO0 ~ GPIO9 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1); + tmpGpioPin = gpioPin; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal); + } else if (gpioPin < GLB_GPIO_PIN_20) { + /* GPIO10 ~ GPIO19 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_10; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal); + } else { + /* GPIO20 ~ GPIO29 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_20; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get GPIO interrupt control mode + * + * @param gpioPin: GPIO pin type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t bitVal; + + if (gpioPin < GLB_GPIO_PIN_10) { + /* GPIO0 - GPIO9 */ + bitVal = gpioPin - 0; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) { + /* GPIO10 - GPIO19 */ + bitVal = gpioPin - 10; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else { + /* GPIO20 - GPIO29 */ + bitVal = gpioPin - 20; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } +} + +/****************************************************************************/ /** + * @brief GPIO INT0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler callback install + * + * @param gpioPin: GPIO pin type + * @param cbFun: callback function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun) +{ + if (gpioPin < 32) { + glbGpioInt0CbfArra[gpioPin] = cbFun; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void GPIO_INT0_IRQHandler(void) +{ + GLB_GPIO_Type gpioPin; + uint32_t timeOut = 0; + + for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_22; gpioPin++) { + if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) { + GLB_GPIO_IntClear(gpioPin, SET); + + /* timeout check */ + timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT; + + do { + timeOut--; + } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut); + + if (!timeOut) { + MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + + /* if timeOut==0, GPIO interrupt status not cleared */ + GLB_GPIO_IntClear(gpioPin, RESET); + + if (glbGpioInt0CbfArra[gpioPin] != NULL) { + /* Call the callback function */ + glbGpioInt0CbfArra[gpioPin](); + } + } + } +} +#endif + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_hbn.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_hbn.c new file mode 100644 index 0000000000000000000000000000000000000000..7aba343fa181852df822571e2015612a73240768 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_hbn.c @@ -0,0 +1,1916 @@ +/** + ****************************************************************************** + * @file bl602_hbn.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_hbn.h" +#include "bl602_glb.h" +#include "bl602_xip_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Private_Macros + * @{ + */ +#define HBN_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group HBN_Private_Macros */ + +/** @defgroup HBN_Private_Types + * @{ + */ + +/*@} end of group HBN_Private_Types */ + +/** @defgroup HBN_Private_Variables + * @{ + */ +static intCallback_Type *hbnInt0CbfArra[3] = { NULL, NULL, NULL }; +static intCallback_Type *hbnInt1CbfArra[4] = { NULL, NULL, NULL, NULL }; + +/*@} end of group HBN_Private_Variables */ + +/** @defgroup HBN_Global_Variables + * @{ + */ + +/*@} end of group HBN_Global_Variables */ + +/** @defgroup HBN_Private_Fun_Declaration + * @{ + */ + +/*@} end of group HBN_Private_Fun_Declaration */ + +/** @defgroup HBN_Private_Functions + * @{ + */ + +/*@} end of group HBN_Private_Functions */ + +/** @defgroup HBN_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Enter HBN + * + * @param cfg: HBN APP Config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) +{ + uint32_t valLow = 0, valHigh = 0; + uint64_t val; + + if (cfg->useXtal32k) { + HBN_32K_Sel(HBN_32K_XTAL); + } else { + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc)); + + if (cfg->gpioWakeupSrc != 0) { + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + HBN_GPIO_INT_Enable(cfg->gpioTrigType); + } else { + HBN_Aon_Pad_IeSmt_Cfg(DISABLE); + } + + /* HBN RTC config and enable */ + HBN_Clear_RTC_Counter(); + + if (cfg->sleepTime != 0) { + HBN_Get_RTC_Timer_Val(&valLow, &valHigh); + val = valLow + ((uint64_t)valHigh << 32); + val += cfg->sleepTime * 32768; + HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39); + HBN_Enable_RTC_Counter(); + } + + HBN_Power_Down_Flash(cfg->flashCfg); + HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */ + + GLB_Set_System_CLK(GLB_PLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + + HBN_Enable(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel); +} + +/****************************************************************************/ /** + * @brief Enter HBN + * + * @param cfg: HBN APP Config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg) +{ + uint32_t valLow = 0, valHigh = 0; + uint64_t val; + + if (cfg->useXtal32k) { + HBN_32K_Sel(HBN_32K_XTAL); + } else { + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc)); + + if (cfg->gpioWakeupSrc != 0) { + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + HBN_GPIO_INT_Enable(cfg->gpioTrigType); + } else { + HBN_Aon_Pad_IeSmt_Cfg(DISABLE); + } + + /* HBN RTC config and enable */ + if (cfg->sleepTime != 0) { + HBN_Clear_RTC_Counter(); + HBN_Get_RTC_Timer_Val(&valLow, &valHigh); + val = valLow + ((uint64_t)valHigh << 32); + val += cfg->sleepTime; + HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39); + HBN_Enable_RTC_Counter(); + } + + HBN_Power_Down_Flash(cfg->flashCfg); + HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */ + + GLB_Set_System_CLK(GLB_PLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + + HBN_Enable_Ext(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel); +} + +/****************************************************************************/ /** + * @brief power down and switch clock + * + * @param flashCfg: None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +{ + SPI_Flash_Cfg_Type bhFlashCfg; + + if (flashCfg == NULL) { + SFlash_Cache_Flush(); + XIP_SFlash_Read_Via_Cache_Need_Lock(BL602_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(SPI_Flash_Cfg_Type)); + SFlash_Cache_Flush(); + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Reset_Continue_Read(&bhFlashCfg); + } else { + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Reset_Continue_Read(flashCfg); + } + + SFlash_Powerdown(); +} +#endif + +/****************************************************************************/ /** + * @brief Enable HBN mode + * + * @param aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to + * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01. + * @param ldoLevel: LDO volatge level + * @param hbnLevel: HBN work level + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel)); + + /* Setting from guide */ + /* RAM Retion */ + BL_WR_REG(HBN_BASE, HBN_SRAM, 0x24); + /* AON GPIO IE */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + ///* Power off 1.8V */ + //tmpVal=BL_RD_REG(AON_BASE,AON_PMIP); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO11_SOC); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_RF); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_IO); + ///* SOC11 enum is not the same as VDD11*/ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_SOC_VOUT_SEL,ldoLevel-1); + //BL_WR_REG(AON_BASE,AON_PMIP,tmpVal); + // + ///* Set RT voltage */ + //tmpVal=BL_RD_REG(AON_BASE,AON); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW3); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW2); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW1); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_BYPASS); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO18_AON); + ///* RT11 enum is not the same as VDD11*/ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_RT_VOUT_SEL,ldoLevel-1); + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_VDD11_SEL,ldoLevel); + //BL_WR_REG(AON_BASE,AON,tmpVal); + + /* Select RC32M */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch (hbnLevel) { + case HBN_LEVEL_0: + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_1: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_2: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_3: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + default: + break; + } + + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Enable HBN mode */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + while (1) { + BL602_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief Enable HBN mode + * + * @param aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to + * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01. + * @param ldoLevel: LDO volatge level + * @param hbnLevel: HBN work level + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel)); + + /* Setting from guide */ + /* RAM Retion */ + BL_WR_REG(HBN_BASE, HBN_SRAM, 0x24); + /* AON GPIO IE */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + /* HBN mode LDO level */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Select RC32M */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch (hbnLevel) { + case HBN_LEVEL_0: + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_1: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_2: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_3: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + default: + break; + } + + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Enable HBN mode */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + while (1) { + BL602_Delay_MS(1000); + } +} + +/****************************************************************************/ /** + * @brief Reset HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Reset HBN mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief reset HBN by software + * + * @param npXtalType: NP clock type + * @param bclkDiv: NP clock div + * @param apXtalType: AP clock type + * @param fclkDiv: AP clock div + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv) +{ + uint32_t tmp[12]; + + tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL); + tmp[1] = BL_RD_REG(HBN_BASE, HBN_TIME_L); + tmp[2] = BL_RD_REG(HBN_BASE, HBN_TIME_H); + tmp[3] = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmp[4] = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmp[5] = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmp[6] = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + tmp[7] = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + tmp[8] = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmp[9] = BL_RD_REG(HBN_BASE, HBN_RSV0); + tmp[10] = BL_RD_REG(HBN_BASE, HBN_RSV1); + tmp[11] = BL_RD_REG(HBN_BASE, HBN_RSV2); + /* DO HBN reset */ + HBN_Reset(); + /* HBN need 3 32k cyclce to recovery */ + BL602_Delay_US(100); + /* Recover HBN value */ + BL_WR_REG(HBN_BASE, HBN_TIME_L, tmp[1]); + BL_WR_REG(HBN_BASE, HBN_TIME_H, tmp[2]); + BL_WR_REG(HBN_BASE, HBN_CTL, tmp[0]); + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp[3]); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmp[4]); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmp[5]); + BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmp[6]); + BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmp[7]); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmp[8]); + BL_WR_REG(HBN_BASE, HBN_RSV0, tmp[9]); + BL_WR_REG(HBN_BASE, HBN_RSV1, tmp[10]); + BL_WR_REG(HBN_BASE, HBN_RSV2, tmp[11]); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Disable HBN mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable HBN PIR + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable HBN PIR + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Config HBN PIR interrupt + * + * @param pirIntCfg: HBN PIR interrupt configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg) +{ + uint32_t tmpVal; + uint32_t bit4 = 0; + uint32_t bit5 = 0; + uint32_t bitVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + + /* low trigger interrupt */ + if (pirIntCfg->lowIntEn == ENABLE) { + bit5 = 0; + } else { + bit5 = 1; + } + + /* high trigger interrupt */ + if (pirIntCfg->highIntEn == ENABLE) { + bit4 = 0; + } else { + bit4 = 1; + } + + bitVal = bit4 | (bit5 << 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select HBN PIR low pass filter + * + * @param lpf: HBN PIR low pass filter selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select HBN PIR high pass filter + * + * @param hpf: HBN PIR high pass filter selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set HBN PIR threshold value + * + * @param threshold: HBN PIR threshold value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold) +{ + uint32_t tmpVal; + + CHECK_PARAM((threshold <= 0x3FFF)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold); + BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN PIR threshold value + * + * @param None + * + * @return HBN PIR threshold value + * +*******************************************************************************/ +uint16_t HBN_Get_PIR_Threshold(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH); +} + +/****************************************************************************/ /** + * @brief Set HBN PIR interval value + * + * @param interval: HBN PIR interval value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval) +{ + uint32_t tmpVal; + + CHECK_PARAM((interval <= 0xFFF)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval); + BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN PIR interval value + * + * @param None + * + * @return HBN PIR interval value + * +*******************************************************************************/ +uint16_t HBN_Get_PIR_Interval(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL); +} + +/****************************************************************************/ /** + * @brief get HBN bor out state + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_BOR_CFG), HBN_R_BOR_OUT) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief set HBN bor config + * + * @param enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset + * @param threshold: bor threshold + * @param mode: bor work mode with por + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold)); + CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG); + + if (enable) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 0); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, threshold); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, mode); + BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11aon voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN set ldo11rt voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN set ldo11soc voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN set ldo11 all voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN select 32K + * + * @param clkType: HBN 32k clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType)); + + HBN_Trim_RC32K(); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Select uart clock source + * + * @param clkSel: uart clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select xclk clock source + * + * @param xClk: xclk clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + + switch (xClk) { + case HBN_XCLK_CLK_RC32M: + tmpVal2 &= (~(1 << 0)); + break; + + case HBN_XCLK_CLK_XTAL: + tmpVal2 |= (1 << 0); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} + +/****************************************************************************/ /** +* @brief get root clock selection +* +* @param None +* +* @return root clock selection +* +*******************************************************************************/ +HBN_ROOT_CLK_Type ATTR_CLOCK_SECTION HBN_Get_Root_CLK_Sel(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + + switch (BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL)) { + case 0: + return HBN_ROOT_CLK_RC32M; + case 1: + return HBN_ROOT_CLK_XTAL; + case 2: + return HBN_ROOT_CLK_PLL; + case 3: + return HBN_ROOT_CLK_PLL; + default: + return HBN_ROOT_CLK_RC32M; + } +} + +/****************************************************************************/ /** + * @brief Select root clk source + * + * @param rootClk: root clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + + switch (rootClk) { + case HBN_ROOT_CLK_RC32M: + tmpVal2 = 0x0; + break; + + case HBN_ROOT_CLK_XTAL: + tmpVal2 = 0x1; + break; + + case HBN_ROOT_CLK_PLL: + tmpVal2 |= (1 << 1); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set HBN_RAM sleep mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_slp(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set HBN_RAM retension mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_Ret(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); + + /* Delay >1s */ + BL602_Delay_US(1100); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + /* Delay >800us */ + BL602_Delay_US(880); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off RC3K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Trim RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void) +{ + Efuse_Ana_RC32K_Trim_Type trim; + int32_t tmpVal = 0; + + EF_Ctrl_Read_RC32K_Trim(&trim); + + if (trim.trimRc32kExtCodeEn) { + if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN); + BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal); + BL602_Delay_US(2); + return SUCCESS; + } + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Get HBN status flag + * + * @param None + * + * @return HBN status flag value + * +*******************************************************************************/ +uint32_t HBN_Get_Status_Flag(void) +{ + return BL_RD_REG(HBN_BASE, HBN_RSV0); +} + +/****************************************************************************/ /** + * @brief Set HBN status flag + * + * @param flag: Status Flag + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag) +{ + BL_WR_REG(HBN_BASE, HBN_RSV0, flag); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN wakeup address + * + * @param None + * + * @return HBN wakeup address + * +*******************************************************************************/ +uint32_t HBN_Get_Wakeup_Addr(void) +{ + return BL_RD_REG(HBN_BASE, HBN_RSV1); +} + +/****************************************************************************/ /** + * @brief Set HBN wakeup address + * + * @param addr: HBN wakeup address + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr) +{ + BL_WR_REG(HBN_BASE, HBN_RSV1, addr); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set RTC timer configuration + * + * @param delay: RTC interrupt delay 32 clocks + * @param compValLow: RTC interrupt commpare value low 32 bits + * @param compValHigh: RTC interrupt commpare value high 32 bits + * @param compMode: RTC interrupt commpare + * mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay)); + + BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow); + BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set interrupt delay option */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay); + /* Set RTC compare mode */ + tmpVal |= (compMode << 1); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get RTC timer count value + * + * @param valLow: RTC count value pointer for low 32 bits + * @param valHigh: RTC count value pointer for high 8 bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh) +{ + uint32_t tmpVal; + + /* Tigger RTC val read */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + + /* Read RTC val */ + *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); + *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_INT(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable GPIO interrupt + * + * @param gpioIntTrigType: HBN GPIO interrupt trigger type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable GPIO interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT); + + if (tmpVal & (1 << irqType)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief HBN get pin wakeup mode value + * + * @param None + * + * @return HBN pin wakeup mode value + * +*******************************************************************************/ +uint8_t HBN_Get_Pin_Wakeup_Mode(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE); +} + +/****************************************************************************/ /** + * @brief HBN clear interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_INT_TYPE(irqType)); + + /* set clear bit */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmpVal |= (1 << irqType); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal); + + /* unset clear bit */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmpVal &= (~(1 << irqType)); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN hardware pullup or pulldown configuration + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + } + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN Config AON pad input and SMT + * + * @param padCfg: AON pad config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, padCfg); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN wakeup pin mask configuration + * + * @param maskVal: mask value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN enable ACOMP0 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); + tmpVal2 = tmpVal2 | (1 << edge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable ACOMP0 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); + tmpVal2 = tmpVal2 & (~(1 << edge)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable ACOMP1 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); + tmpVal2 = tmpVal2 | (1 << edge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable ACOMP1 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); + tmpVal2 = tmpVal2 & (~(1 << edge)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable BOR interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_BOR_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable BOR interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_BOR_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out0_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out0 install interrupt callback + * + * @param intType: HBN out0 interrupt type + * @param cbFun: HBN out0 interrupt callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType)); + + hbnInt0CbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out1 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out1_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out1 install interrupt callback + * + * @param intType: HBN out1 interrupt type + * @param cbFun: HBN out1 interrupt callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType)); + + hbnInt1CbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN GPIO7 debbug pull config + * + * @param pupdEn: Enable or disable GPIO7 pull down and pull up + * @param iesmtEn: Enable or disable GPIO7 IE and SMT + * @param dlyEn: Enable or disable GPIO7 wakeup delay function + * @param dlySec: GPIO7 wakeup delay sec 1 to 7 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec) +{ + uint32_t tmpVal; + + CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7))); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, pupdEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, iesmtEn); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set Embedded Flash Pullup enabe or disable + * + * @param enable: Enable or disable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Embedded_Flash_Pullup(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3); + + enable = (!enable); + tmpVal = ((tmpVal & 0xfffffffe) | (enable & 0x01)); + + BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set Embedded Flash Pullup enabe or disable + * + * @param cfg: Enable or disable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg) +{ + uint32_t tmpVal = 0; + + if (cfg->enableBorInt) { + HBN_Enable_BOR_IRQ(); + } else { + HBN_Disable_BOR_IRQ(); + } + + tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, cfg->borThreshold); + + if (cfg->enablePorInBor) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOR_SEL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOR_SEL); + } + + if (cfg->enableBor) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR); + } + + BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN OUT0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void) +{ + /* GPIO7 GPIO8 and RTC */ + if (SET == HBN_Get_INT_State(HBN_INT_GPIO7)) { + /* gpio7 sync/async mode */ + HBN_Clear_IRQ(HBN_INT_GPIO7); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO7] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO7](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO8)) { + /* gpio8 sync/async mode */ + HBN_Clear_IRQ(HBN_INT_GPIO8); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO8] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO8](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_RTC)) { + HBN_Clear_IRQ(HBN_INT_RTC); + HBN_Clear_RTC_INT(); + + if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_RTC](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief HBN OUT1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT1_IRQHandler(void) +{ + /* PIR */ + if (SET == HBN_Get_INT_State(HBN_INT_PIR)) { + HBN_Clear_IRQ(HBN_INT_PIR); + + if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_PIR](); + } + } + + /* BOR */ + if (SET == HBN_Get_INT_State(HBN_INT_BOR)) { + HBN_Clear_IRQ(HBN_INT_BOR); + + if (hbnInt1CbfArra[HBN_OUT1_INT_BOR] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_BOR](); + } + } + + /* ACOMP0 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) { + HBN_Clear_IRQ(HBN_INT_ACOMP0); + + if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0](); + } + } + + /* ACOMP1 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) { + HBN_Clear_IRQ(HBN_INT_ACOMP1); + + if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1](); + } + } +} +#endif + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_i2c.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..6c8135483a55e491fd73082ece52dff06b3055fe --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_i2c.c @@ -0,0 +1,805 @@ +/** + ****************************************************************************** + * @file bl602_i2c.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_i2c.h" +#include "bl602_glb.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ +#define I2C_FIFO_STATUS_TIMEOUT (160 * 1000 * 2) +#define PUT_UINT32_LE(n, b, i) \ + { \ + (b)[(i)] = (uint8_t)((n)); \ + (b)[(i) + 1] = (uint8_t)((n) >> 8); \ + (b)[(i) + 2] = (uint8_t)((n) >> 16); \ + (b)[(i) + 3] = (uint8_t)((n) >> 24); \ + } + +/*@} end of group I2C_Private_Macros */ + +/** @defgroup I2C_Private_Types + * @{ + */ + +/*@} end of group I2C_Private_Types */ + +/** @defgroup I2C_Private_Variables + * @{ + */ +intCallback_Type *i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL] = { { NULL } }; + +/*@} end of group I2C_Private_Variables */ + +/** @defgroup I2C_Global_Variables + * @{ + */ + +/*@} end of group I2C_Global_Variables */ + +/** @defgroup I2C_Private_Fun_Declaration + * @{ + */ + +/*@} end of group I2C_Private_Fun_Declaration */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief I2C interrupt handler + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static void I2C_IntHandler(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_TXF_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_RXF_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_NAK_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_ARB_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_FER_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT](); + } + } +} +#endif + +/*@} end of group I2C_Private_Functions */ + +/** @defgroup I2C_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief I2C write word data + * + * @param i2cNo: I2C ID type + * @param data: Data word + * + * @return None + * +*******************************************************************************/ +void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data) +{ + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data); +} + +/****************************************************************************/ /** + * @brief I2C read word data + * + * @param i2cNo: I2C ID type + * + * @return word data + * +*******************************************************************************/ +uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo) +{ + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + return BL_RD_REG(I2Cx, I2C_FIFO_RDATA); +} + +/****************************************************************************/ /** + * @brief I2C enable + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +void I2C_Enable(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); + + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2C disable + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +void I2C_Disable(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); + + /* Clear I2C fifo */ + tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR); + BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal); + + /* Clear I2C interrupt status */ + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR); + BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2C set global reset function + * + * @param i2cNo: I2C ID type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo) +{ + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_I2C); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief I2C init function + * + * @param i2cNo: I2C ID type + * @param direct: I2C read or write direct + * @param cfg: I2C transfer config struct + * + * @return None + * +*******************************************************************************/ +void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + /* I2C write config */ + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + + if (direct == I2C_WRITE) { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr); + + if (cfg->subAddrSize > 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize - 1); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); + + /* Set sub address */ + BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(I2C_IRQn, I2C_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief Set de-glitch function cycle count value + * + * @param i2cNo: I2C ID type + * @param cnt: De-glitch function cycle count + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + + if (cnt > 0) { + /* enable de-glitch function */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN); + } else if (cnt == 0) { + /* disable de-glitch function */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN); + } else { + return ERROR; + } + + /* Set count value */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_DEG_CNT, cnt); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set i2c prd + * + * @param i2cNo: I2C ID type + * @param phase: I2C phase value + * + * @return None + * +*******************************************************************************/ +void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + //phase_cycles = (32000000 / phase / 4) - 1; + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal); + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal); + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2C set scl output clock + * + * @param i2cNo: I2C ID type + * @param clk: Clock set + * + * @return None + * +*******************************************************************************/ +void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk) +{ + uint8_t bclkDiv = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + bclkDiv = GLB_Get_BCLK_Div(); + + if (clk >= 100000) { + GLB_Set_I2C_CLK(1, 0); + I2C_SetPrd(i2cNo, (SystemCoreClockGet() / (bclkDiv + 1)) / (clk * 4) - 1); + } else if (clk >= 8000) { + GLB_Set_I2C_CLK(1, 9); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 10) / (clk * 4) - 1); + } else if (clk >= 800) { + GLB_Set_I2C_CLK(1, 99); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 100) / (clk * 4) - 1); + } else { + GLB_Set_I2C_CLK(1, 255); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 256) / (clk * 4) - 1); + } + + /* Disable i2c scl sync to get current i2c clock */ + I2C_SetSclSync(i2cNo, 0); +} + +/****************************************************************************/ /** + * @brief I2C set scl sync + * + * @param i2cNo: I2C ID type + * @param enable: Enable or disable I2C scl sync + * + * @return None + * +*******************************************************************************/ +void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); + } + + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Get i2c busy state + * + * @param i2cNo: I2C ID type + * + * @return RESET or SET + * +*******************************************************************************/ +BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? RESET : SET); +} + +/****************************************************************************/ /** + * @brief I2C master write block data + * + * @param i2cNo: I2C ID type + * @param cfg: I2C transfer config struct + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) +{ + uint8_t i; + uint32_t timeOut = 0; + uint32_t temp = 0; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + I2C_Disable(i2cNo); + I2C_Init(i2cNo, I2C_WRITE, cfg); + I2C_Enable(i2cNo); + + /* Set I2C write data */ + for (i = 0; i < cfg->dataSize; i++) { + temp += (cfg->data[i] << ((i % 4) * 8)); + + if ((i + 1) % 4 == 0) { + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); + temp = 0; + } + } + + if ((cfg->dataSize % 4) != 0) { + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); + } + + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (I2C_IsBusy(i2cNo)) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + I2C_Disable(i2cNo); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief I2C master read block data + * + * @param i2cNo: I2C ID type + * @param cfg: I2C transfer config struct + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) +{ + uint8_t i = 0; + uint32_t timeOut = 0; + uint32_t temp = 0; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + I2C_Disable(i2cNo); + I2C_Init(i2cNo, I2C_READ, cfg); + I2C_Enable(i2cNo); + + /* Read I2C data */ + while (cfg->dataSize - i >= 4) { + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); + PUT_UINT32_LE(temp, cfg->data, i); + i += 4; + } + + if (i < cfg->dataSize) { + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); + + while (i < cfg->dataSize) { + cfg->data[i] = (temp & 0xff); + temp = (temp >> 8); + i++; + } + } + + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (I2C_IsBusy(i2cNo)) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + I2C_Disable(i2cNo); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Mask/Unmask the I2C interrupt + * + * @param i2cNo: I2C ID type + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + CHECK_PARAM(IS_I2C_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + + switch (intType) { + case I2C_TRANS_END_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + } + + break; + + case I2C_TX_FIFO_READY_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + } + + break; + + case I2C_RX_FIFO_READY_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + } + + break; + + case I2C_NACK_RECV_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + } + + break; + + case I2C_ARB_LOST_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + } + + break; + + case I2C_FIFO_ERR_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } + + break; + + case I2C_INT_ALL: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } + + break; + + default: + break; + } + + BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); +} + +/****************************************************************************/ /** + * @brief Install I2C interrupt callback function + * + * @param i2cNo: I2C ID type + * @param intType: Specifies the interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + CHECK_PARAM(IS_I2C_INT_TYPE(intType)); + + i2cIntCbfArra[i2cNo][intType] = cbFun; +} +#endif + +/****************************************************************************/ /** + * @brief I2C IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_IRQHandler(void) +{ + I2C_IntHandler(I2C0_ID); +} +#endif + +/*@} end of group I2C_Public_Functions */ + +/*@} end of group I2C */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_ir.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_ir.c new file mode 100644 index 0000000000000000000000000000000000000000..0378afee9792b6474d96ccb383c2fd579f5eac26 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_ir.c @@ -0,0 +1,1147 @@ +/** + ****************************************************************************** + * @file bl602_ir.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_ir.h" +#include "bl602_glb.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup IR + * @{ + */ + +/** @defgroup IR_Private_Macros + * @{ + */ +#define NEC_HEAD_H_MIN 17000 +#define NEC_HEAD_H_MAX 19000 +#define NEC_HEAD_L_MIN 8400 +#define NEC_HEAD_L_MAX 9600 +#define NEC_BIT0_H_MIN 525 +#define NEC_BIT0_H_MAX 1725 +#define RC5_ONE_PLUSE_MIN 1175 +#define RC5_ONE_PLUSE_MAX 2375 +#define RC5_TWO_PLUSE_MIN 2955 +#define RC5_TWO_PLUSE_MAX 4155 +#define IR_TX_INT_TIMEOUT_COUNT (100 * 160 * 1000) +#define IR_RX_INT_TIMEOUT_COUNT (100 * 160 * 1000) + +/*@} end of group IR_Private_Macros */ + +/** @defgroup IR_Private_Types + * @{ + */ + +/*@} end of group IR_Private_Types */ + +/** @defgroup IR_Private_Variables + * @{ + */ +static intCallback_Type *irIntCbfArra[IR_INT_ALL] = { NULL, NULL }; + +/*@} end of group IR_Private_Variables */ + +/** @defgroup IR_Global_Variables + * @{ + */ + +/*@} end of group IR_Global_Variables */ + +/** @defgroup IR_Private_Fun_Declaration + * @{ + */ + +/*@} end of group IR_Private_Fun_Declaration */ + +/** @defgroup IR_Private_Functions + * @{ + */ + +/*@} end of group IR_Private_Functions */ + +/** @defgroup IR_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief IR RX IRQ handler function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void IRRX_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + + if (BL_IS_REG_BIT_SET(tmpVal, IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_END_MASK)) { + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); + + if (irIntCbfArra[IR_INT_RX] != NULL) { + irIntCbfArra[IR_INT_RX](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief IR TX IRQ handler function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void IRTX_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); + + if (BL_IS_REG_BIT_SET(tmpVal, IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_END_MASK)) { + BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR)); + + if (irIntCbfArra[IR_INT_TX] != NULL) { + irIntCbfArra[IR_INT_TX](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief IR tx initialization function + * + * @param irTxCfg: IR tx configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + /* Set data bit */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, irTxCfg->dataBits - 1); + /* Set tail pulse */ + ENABLE == irTxCfg->tailPulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_HL_INV)); + ENABLE == irTxCfg->tailPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_EN)); + /* Set head pulse */ + ENABLE == irTxCfg->headPulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_HL_INV)); + ENABLE == irTxCfg->headPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_EN)); + /* Enable or disable logic 1 and 0 pulse inverse */ + ENABLE == irTxCfg->logic1PulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV)); + ENABLE == irTxCfg->logic0PulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV)); + /* Enable or disable data pulse */ + ENABLE == irTxCfg->dataPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_DATA_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_DATA_EN)); + /* Enable or disable output modulation */ + ENABLE == irTxCfg->outputModulation ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_MOD_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_MOD_EN)); + /* Enable or disable output inverse */ + ENABLE == irTxCfg->outputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_OUT_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_OUT_INV)); + + /* Write back */ + BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(IRTX_IRQn, IRTX_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR tx pulse width configure function + * + * @param irTxPulseWidthCfg: IR tx pulse width configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE, IRTX_PW); + /* Set logic 0 pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH0_W, irTxPulseWidthCfg->logic0PulseWidth_0 - 1); + /* Set logic 0 pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH1_W, irTxPulseWidthCfg->logic0PulseWidth_1 - 1); + /* Set logic 1 pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH0_W, irTxPulseWidthCfg->logic1PulseWidth_0 - 1); + /* Set logic 1 pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH1_W, irTxPulseWidthCfg->logic1PulseWidth_1 - 1); + /* Set head pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH0_W, irTxPulseWidthCfg->headPulseWidth_0 - 1); + /* Set head pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH1_W, irTxPulseWidthCfg->headPulseWidth_1 - 1); + /* Set tail pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH0_W, irTxPulseWidthCfg->tailPulseWidth_0 - 1); + /* Set tail pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH1_W, irTxPulseWidthCfg->tailPulseWidth_1 - 1); + BL_WR_REG(IR_BASE, IRTX_PW, tmpVal); + + tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH); + /* Set modulation phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH0_W, irTxPulseWidthCfg->moduWidth_0 - 1); + /* Set modulation phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH1_W, irTxPulseWidthCfg->moduWidth_1 - 1); + /* Set pulse width unit */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, irTxPulseWidthCfg->pulseWidthUnit - 1); + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR tx software mode pulse width(multiples of pulse width unit) configure function + * + * @param irTxSWMPulseWidthCfg: IR tx software mode pulse width configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg) +{ + /* Set swm pulse width,multiples of pulse width unit */ + BL_WR_REG(IR_BASE, IRTX_SWM_PW_0, irTxSWMPulseWidthCfg->swmData0); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_1, irTxSWMPulseWidthCfg->swmData1); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_2, irTxSWMPulseWidthCfg->swmData2); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_3, irTxSWMPulseWidthCfg->swmData3); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_4, irTxSWMPulseWidthCfg->swmData4); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_5, irTxSWMPulseWidthCfg->swmData5); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_6, irTxSWMPulseWidthCfg->swmData6); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_7, irTxSWMPulseWidthCfg->swmData7); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR rx initialization function + * + * @param irRxCfg: IR rx configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode)); + + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + + /* Set rx mode */ + switch (irRxCfg->rxMode) { + case IR_RX_NEC: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0); + break; + + case IR_RX_RC5: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1); + break; + + case IR_RX_SWM: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2); + break; + + default: + break; + } + + /* Enable or disable input inverse */ + ENABLE == irRxCfg->inputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)); + /* Enable or disable rx input de-glitch function */ + ENABLE == irRxCfg->rxDeglitch ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)); + /* Set de-glitch function cycle count */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DEG_CNT, irRxCfg->DeglitchCnt); + /* Write back */ + BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG); + /* Set pulse width threshold to trigger end condition */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, irRxCfg->endThreshold - 1); + /* Set pulse width threshold for logic0/1 detection */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DATA_TH, irRxCfg->dataThreshold - 1); + /* Write back */ + BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(IRRX_IRQn, IRRX_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR set default value of all registers function + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_DeInit(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_IRR); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR enable function + * + * @param direct: IR direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_Enable(IR_Direction_Type direct) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); + + if (direct == IR_TX || direct == IR_TXRX) { + /* Enable ir tx unit */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_EN)); + } + + if (direct == IR_RX || direct == IR_TXRX) { + /* Enable ir rx unit */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR disable function + * + * @param direct: IR direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_Disable(IR_Direction_Type direct) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); + + if (direct == IR_TX || direct == IR_TXRX) { + /* Disable ir tx unit */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_EN)); + } + + if (direct == IR_RX || direct == IR_TXRX) { + /* Disable ir rx unit */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR tx software mode enable or disable function + * + * @param txSWM: Enable or disable + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM) +{ + uint32_t tmpVal; + + /* Enable or disable tx swm */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + + if (ENABLE == txSWM) { + BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN)); + } else { + BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR clear rx fifo function + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_RxFIFOClear(void) +{ + uint32_t tmpVal; + + /* Clear rx fifo */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0); + BL_WR_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_RX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send data function + * + * @param irWord: IR tx data word 0 or 1 + * @param data: data to send + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SendData(IR_Word_Type irWord, uint32_t data) +{ + /* Check the parameters */ + CHECK_PARAM(IS_IR_WORD_TYPE(irWord)); + + /* Write word 0 or word 1 */ + if (IR_WORD_0 == irWord) { + BL_WR_REG(IR_BASE, IRTX_DATA_WORD0, data); + } else { + BL_WR_REG(IR_BASE, IRTX_DATA_WORD1, data); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR software mode send pulse width data function + * + * @param data: data to send + * @param length: Length of send buffer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length) +{ + uint8_t i = 0, j = 0; + uint16_t minData = data[0]; + uint32_t tmpVal; + uint32_t pwVal = 0; + uint32_t count = (length + 7) / 8; + + /* Search for min value */ + for (i = 1; i < length; i++) { + if (minData > data[i] && data[i] != 0) { + minData = data[i]; + } + } + + /* Set pulse width unit */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH); + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, minData)); + + /* Set tx SWM pulse width data as multiples of pulse width unit */ + for (i = 0; i < count; i++) { + pwVal = 0; + + if (i < count - 1) { + for (j = 0; j < 8; j++) { + tmpVal = ((2 * data[j + i * 8] + minData) / (2 * minData) - 1) & 0xf; + pwVal |= tmpVal << (4 * j); + } + + *(volatile uint32_t *)(IR_BASE + IRTX_SWM_PW_0_OFFSET + i * 4) = pwVal; + } else { + for (j = 0; j < length % 8; j++) { + tmpVal = ((2 * data[j + i * 8] + minData) / (2 * minData) - 1) & 0xf; + pwVal |= tmpVal << (4 * j); + } + + *(volatile uint32_t *)(IR_BASE + IRTX_SWM_PW_0_OFFSET + i * 4) = pwVal; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send command function + * + * @param word1: IR send data word 1 + * @param word0: IR send data word 0 + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SendCommand(uint32_t word1, uint32_t word0) +{ + uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; + + /* Write data */ + IR_SendData(IR_WORD_1, word1); + IR_SendData(IR_WORD_0, word0); + + /* Mask tx interrupt */ + IR_IntMask(IR_INT_TX, MASK); + + /* Clear tx interrupt */ + IR_ClrIntStatus(IR_INT_TX); + + /* Enable ir tx */ + IR_Enable(IR_TX); + + /* Wait for tx interrupt */ + while (SET != IR_GetIntStatus(IR_INT_TX)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + IR_Disable(IR_TX); + + return TIMEOUT; + } + } + + /* Disable ir tx */ + IR_Disable(IR_TX); + + /* Clear tx interrupt */ + IR_ClrIntStatus(IR_INT_TX); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send command in software mode function + * + * @param data: IR fifo data to send + * @param length: Length of data + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length) +{ + uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; + + /* Write fifo */ + IR_SWMSendData(data, length); + + /* Mask tx interrupt */ + IR_IntMask(IR_INT_TX, MASK); + + /* Clear tx interrupt */ + IR_ClrIntStatus(IR_INT_TX); + + /* Enable ir tx */ + IR_Enable(IR_TX); + + /* Wait for tx interrupt */ + while (SET != IR_GetIntStatus(IR_INT_TX)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + IR_Disable(IR_TX); + + return TIMEOUT; + } + } + + /* Disable ir tx */ + IR_Disable(IR_TX); + + /* Clear tx interrupt */ + IR_ClrIntStatus(IR_INT_TX); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send in NEC protocol + * + * @param address: Address + * @param command: Command + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command) +{ + uint32_t tmpVal = ((~command & 0xff) << 24) + (command << 16) + ((~address & 0xff) << 8) + address; + + IR_SendCommand(0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR interrupt mask or unmask function + * + * @param intType: IR interrupt type + * @param intMask: Mask or unmask + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_INT_TYPE(intType)); + + if (intType == IR_INT_TX || intType == IR_INT_ALL) { + /* Mask or unmask tx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); + BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_END_MASK, intMask)); + } + + if (intType == IR_INT_RX || intType == IR_INT_ALL) { + /* Mask or unmask rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_MASK, intMask)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear ir interrupt function + * + * @param intType: IR interrupt type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_INT_TYPE(intType)); + + if (intType == IR_INT_TX || intType == IR_INT_ALL) { + /* Clear tx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); + BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR)); + } + + if (intType == IR_INT_RX || intType == IR_INT_ALL) { + /* Clear rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR install interrupt callback function + * + * @param intType: IR interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_IR_INT_TYPE(intType)); + + irIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR get interrupt status function + * + * @param intType: IR int type + * + * @return IR tx or rx interrupt status + * +*******************************************************************************/ +BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_INT_TYPE(intType)); + + /* Read tx or rx interrupt status */ + if (IR_INT_TX == intType) { + tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IRTX_END_INT); + } else if (IR_INT_RX == intType) { + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IRRX_END_INT); + } + + if (tmpVal) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief IR get rx fifo underflow or overflow status function + * + * @param fifoSts: IR fifo status type + * + * @return IR rx fifo status + * +*******************************************************************************/ +BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_FIFOSTATUS_TYPE(fifoSts)); + + /* Read rx fifo status */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0); + + if (fifoSts == IR_RX_FIFO_UNDERFLOW) { + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_UNDERFLOW); + } else { + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_OVERFLOW); + } + + if (tmpVal) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief IR receive data function + * + * @param irWord: IR rx data word 0 or 1 + * + * @return Data received + * +*******************************************************************************/ +uint32_t IR_ReceiveData(IR_Word_Type irWord) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_WORD_TYPE(irWord)); + + /* Read word 0 or word 1 */ + if (IR_WORD_0 == irWord) { + tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD0); + } else { + tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD1); + } + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief IR software mode receive pulse width data function + * + * @param data: Data received + * @param length: Max length of receive buffer + * + * @return Length of datas received + * +*******************************************************************************/ +uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length) +{ + uint8_t rxLen = 0; + + while (rxLen < length && IR_GetRxFIFOCount() > 0) { + /* Read data */ + data[rxLen++] = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_RDATA) & 0xffff; + } + + return rxLen; +} + +/****************************************************************************/ /** + * @brief IR receive in NEC protocol + * + * @param address: Address + * @param command: Command + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command) +{ + uint32_t tmpVal = IR_ReceiveData(IR_WORD_0); + + *address = tmpVal & 0xff; + *command = (tmpVal >> 16) & 0xff; + + if ((~(*address) & 0xff) != ((tmpVal >> 8) & 0xff) || (~(*command) & 0xff) != ((tmpVal >> 24) & 0xff)) { + return ERROR; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR get rx data bit count function + * + * @param None + * + * @return IR rx data bit count + * +*******************************************************************************/ +uint8_t IR_GetRxDataBitCount(void) +{ + uint32_t tmpVal; + + /* Read rx data bit count */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_COUNT); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_STS_IRRX_DATA_CNT); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief IR get rx fifo count function + * + * @param None + * + * @return IR rx fifo available count + * +*******************************************************************************/ +uint8_t IR_GetRxFIFOCount(void) +{ + uint32_t tmpVal; + + /* Read rx fifo count */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_CNT); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief IR learning to set rx and tx mode function + * + * @param data: Buffer to save data + * @param length: Length of data + * + * @return Protocol type + * +*******************************************************************************/ +IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length) +{ + uint32_t tmpVal; + uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; + + /* Disable rx,set rx in software mode and enable rx input inverse */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2); + tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV); + BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal); + /* Set pulse width threshold to trigger end condition */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG); + BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, 19999)); + + /* Clear and mask rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_MASK); + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); + + /* Enable rx */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN)); + + /* Wait for rx interrupt */ + while (SET != IR_GetIntStatus(IR_INT_RX)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + IR_Disable(IR_RX); + + return IR_RX_SWM; + } + } + + /* Disable rx */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN)); + + /* Clear rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); + + /*Receive data */ + *length = IR_GetRxFIFOCount(); + *length = IR_SWMReceiveData((uint16_t *)data, *length); + + /* Judge protocol type */ + if (NEC_HEAD_H_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < NEC_HEAD_H_MAX && NEC_HEAD_L_MIN < (data[0] >> 16) && (data[0] >> 16) < NEC_HEAD_L_MAX && NEC_BIT0_H_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < NEC_BIT0_H_MAX) { + /* Set rx in NEC mode */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0)); + /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */ + BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x23270d47); + /* Set tx in NEC mode */ + /* Tx configure */ + BL_WR_REG(IR_BASE, IRTX_CONFIG, 0x1f514); + /* Set logic 0,logic 1,head and tail pulse width */ + BL_WR_REG(IR_BASE, IRTX_PW, 0x7f2000); + /* Set modulation phase width and pulse width unit */ + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110464); + + return IR_RX_NEC; + } else if (RC5_ONE_PLUSE_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < RC5_ONE_PLUSE_MAX && ((RC5_ONE_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_TWO_PLUSE_MAX)) && + ((RC5_ONE_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_TWO_PLUSE_MAX))) { + /* Set rx in RC-5 mode */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1)); + /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */ + BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x13870a6a); + /* Set tx in RC-5 mode */ + /* Tx configure */ + BL_WR_REG(IR_BASE, IRTX_CONFIG, 0xc134); + /* Set logic 0,logic 1,head and tail pulse width */ + BL_WR_REG(IR_BASE, IRTX_PW, 0); + /* Set modulation phase width and pulse width unit */ + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x221106f1); + + return IR_RX_RC5; + } else if ((data[0] >> 16) != 0) { + /* Set tx in software mode */ + /* Tx configure */ + BL_WR_REG(IR_BASE, IRTX_CONFIG, *length << 12 | 0xc); + /* Set modulation phase width */ + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110000); + + return IR_RX_SWM; + } else { + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE); + + if (tmpVal == 0) { + return IR_RX_NEC; + } else if (tmpVal == 1) { + return IR_RX_RC5; + } else { + return IR_RX_SWM; + } + } +} + +/****************************************************************************/ /** + * @brief IR receive data according to mode which is learned function + * + * @param mode: Protocol type + * @param data: Buffer to save data + * + * @return Length of data + * +*******************************************************************************/ +uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data) +{ + uint8_t length = 0; + uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); + + /* Disable ir rx */ + IR_Disable(IR_RX); + + /* Clear and mask rx interrupt */ + IR_ClrIntStatus(IR_INT_RX); + IR_IntMask(IR_INT_RX, MASK); + + /* Enable ir rx */ + IR_Enable(IR_RX); + + /* Wait for rx interrupt */ + while (SET != IR_GetIntStatus(IR_INT_RX)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + IR_Disable(IR_RX); + + return TIMEOUT; + } + } + + /* Disable ir rx */ + IR_Disable(IR_RX); + + /* Clear rx interrupt */ + IR_ClrIntStatus(IR_INT_RX); + + /* Receive data according to mode */ + if (mode == IR_RX_NEC || mode == IR_RX_RC5) { + /* Get data bit count */ + length = IR_GetRxDataBitCount(); + data[0] = IR_ReceiveData(IR_WORD_0); + } else { + /* Get fifo count */ + length = IR_GetRxFIFOCount(); + length = IR_SWMReceiveData((uint16_t *)data, length); + } + + return length; +} + +/****************************************************************************/ /** + * @brief IR send data according to mode which is learned function + * + * @param mode: Protocol type + * @param data: Buffer of data to send + * @param length: Length of data + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); + + /* Set send length */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, length - 1); + BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal); + + if (mode == IR_RX_NEC || mode == IR_RX_RC5) { + IR_SendCommand(0, data[0]); + } else { + IR_SWMSendCommand((uint16_t *)data, length); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR init to control led function + * + * @param clk: Clock source + * @param div: Clock division(1~64) + * @param unit: Pulse width unit(multiples of clock pulse width, 1~4096) + * @param code0H: code 0 high level time(multiples of pulse width unit, 1~16) + * @param code0L: code 0 low level time(multiples of pulse width unit, 1~16) + * @param code1H: code 1 high level time(multiples of pulse width unit, 1~16) + * @param code1L: code 1 low level time(multiples of pulse width unit, 1~16) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L) +{ + IR_TxCfg_Type txCfg = { + 24, /* 24-bit data */ + DISABLE, /* Disable signal of tail pulse inverse */ + DISABLE, /* Disable signal of tail pulse */ + DISABLE, /* Disable signal of head pulse inverse */ + DISABLE, /* Disable signal of head pulse */ + DISABLE, /* Disable signal of logic 1 pulse inverse */ + DISABLE, /* Disable signal of logic 0 pulse inverse */ + ENABLE, /* Enable signal of data pulse */ + DISABLE, /* Disable signal of output modulation */ + ENABLE /* Enable signal of output inverse */ + }; + + IR_TxPulseWidthCfg_Type txPWCfg = { + code0L, /* Pulse width of logic 0 pulse phase 1 */ + code0H, /* Pulse width of logic 0 pulse phase 0 */ + code1L, /* Pulse width of logic 1 pulse phase 1 */ + code1H, /* Pulse width of logic 1 pulse phase 0 */ + 1, /* Pulse width of head pulse phase 1 */ + 1, /* Pulse width of head pulse phase 0 */ + 1, /* Pulse width of tail pulse phase 1 */ + 1, /* Pulse width of tail pulse phase 0 */ + 1, /* Modulation phase 1 width */ + 1, /* Modulation phase 0 width */ + unit /* Pulse width unit */ + }; + + HBN_Set_XCLK_CLK_Sel(clk); + GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, div - 1); + + /* Disable ir before config */ + IR_Disable(IR_TXRX); + + /* IR tx init */ + IR_TxInit(&txCfg); + IR_TxPulseWidthConfig(&txPWCfg); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send 24-bit data to control led function + * + * @param data: Data to send(24-bit) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_LEDSend(uint32_t data) +{ + /* Change MSB_first to LSB_first */ + data = ((data >> 1) & 0x55555555) | ((data << 1) & 0xaaaaaaaa); + data = ((data >> 2) & 0x33333333) | ((data << 2) & 0xcccccccc); + data = ((data >> 4) & 0x0f0f0f0f) | ((data << 4) & 0xf0f0f0f0); + data = ((data >> 16) & 0xff) | (data & 0xff00) | ((data << 16) & 0xff0000); + IR_SendCommand(0, data); + + return SUCCESS; +} + +/*@} end of group IR_Public_Functions */ + +/*@} end of group IR */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_l1c.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_l1c.c new file mode 100644 index 0000000000000000000000000000000000000000..b9e065a584885d2c27484592f89139858b8a31f2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_l1c.c @@ -0,0 +1,428 @@ +/** + ****************************************************************************** + * @file bl602_l1c.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_l1c.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup L1C + * @{ + */ + +/** @defgroup L1C_Private_Macros + * @{ + */ + +/*@} end of group L1C_Private_Macros */ + +/** @defgroup L1C_Private_Types + * @{ + */ + +/*@} end of group L1C_Private_Types */ + +/** @defgroup L1C_Private_Variables + * @{ + */ +static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = { NULL }; +static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL }; + +/*@} end of group L1C_Private_Variables */ + +/** @defgroup L1C_Global_Variables + * @{ + */ + +/*@} end of group L1C_Global_Variables */ + +/** @defgroup L1C_Private_Fun_Declaration + * @{ + */ + +/*@} end of group L1C_Private_Fun_Declaration */ + +/** @defgroup L1C_Private_Functions + * @{ + */ + +/*@} end of group L1C_Private_Functions */ + +/** @defgroup L1C_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief wrap set + * + * @param wrap: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap) +{ + uint32_t tmpVal = 0; + uint8_t cacheEn = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); + + if (cacheEn != 0) { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + } + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + + if (wrap == ENABLE) { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + if (cacheEn != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief cache way disable set + * + * @param disableVal: cache way disable value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal) +{ + uint32_t tmpVal = 0; + uint8_t cacheEn = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); + + if (cacheEn != 0) { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + } + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + if (cacheEn != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set for ROM 2T access if CPU freq >120MHz + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief L1C BMX init + * + * @param l1cBmxCfg: L1C BMX config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler); + Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS); + BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS); + BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get L1C BMX error status + * + * @param errType: L1C BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType)); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + + if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) { + return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET; + } +} + +/****************************************************************************/ /** + * @brief Get L1C BMX error address + * + * @param None + * + * @return NP L1C BMX error address + * +*******************************************************************************/ +uint32_t L1C_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR); +} + +/****************************************************************************/ /** + * @brief L1C BMX error interrupt callback install + * + * @param intType: L1C BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType)); + + l1cBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_ERR_IRQHandler(void) +{ + L1C_BMX_ERR_INT_Type intType; + + for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) { + if (l1cBmxErrIntCbfArra[intType] != NULL) { + l1cBmxErrIntCbfArra[intType](); + } + } + + while (1) { + MSG("L1C_BMX_ERR_IRQHandler\r\n"); + BL602_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief L1C BMX timeout interrupt callback install + * + * @param intType: L1C BMX timeout interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType)); + + l1cBmxToIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX Time Out interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_TO_IRQHandler(void) +{ + L1C_BMX_TO_INT_Type intType; + + for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) { + if (l1cBmxToIntCbfArra[intType] != NULL) { + l1cBmxToIntCbfArra[intType](); + } + } + + while (1) { + MSG("L1C_BMX_TO_IRQHandler\r\n"); + BL602_Delay_MS(1000); + } +} +#endif + +/*@} end of group L1C_Public_Functions */ + +/*@} end of group L1C */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_efuse.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_efuse.c new file mode 100644 index 0000000000000000000000000000000000000000..d91656dc2c0e0704faf755af48af05861b0728fc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_efuse.c @@ -0,0 +1,533 @@ +#include "bl602_glb.h" +#include "bl602_mfg_efuse.h" +#include "bl602_ef_ctrl.h" + +static uint8_t rf_cal_slots = 3; +extern void main(void); +#define RF_CAL_SLOT_CFG_OFFSET (4 * 13) +#ifdef BFLB_MCU_SDK +#include "bflb_platform.h" +#define mfg_print MSG +#else +#define mfg_print printf +#endif + +uint8_t mfg_efuse_get_rf_cal_slots(void) +{ +#if 0 + uint8_t *pslot; + pslot = (uint8_t *)((((uint32_t)main) & 0xfff00000) + RF_CAL_SLOT_CFG_OFFSET); + + if(*pslot != 0) + { + rf_cal_slots = *pslot; + } + +#endif + return rf_cal_slots; +} + +void mfg_efuse_set_rf_cal_slots(uint8_t slots) +{ + rf_cal_slots = slots; +} + +uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload) +{ + uint8_t empty = 0; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 1 && EF_Ctrl_Is_CapCode_Slot_Empty(0, reload)) { + mfg_print("Empty slot:%d\r\n", 0); + empty = 1; + } else if (rf_cal_slots >= 2 && EF_Ctrl_Is_CapCode_Slot_Empty(1, reload)) { + mfg_print("Empty slot:%d\r\n", 1); + empty = 1; + } else if (rf_cal_slots >= 3 && EF_Ctrl_Is_CapCode_Slot_Empty(2, reload)) { + mfg_print("Empty slot:%d\r\n", 2); + empty = 1; + } else { + mfg_print("No empty slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + return empty; +} + +int8_t mfg_efuse_write_xtal_capcode_pre(uint8_t capcode, uint8_t program) +{ + BL_Err_Type ret = SUCCESS; + uint8_t slot = 0xff; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 1 && EF_Ctrl_Is_CapCode_Slot_Empty(0, 1)) { + slot = 0; + } else if (rf_cal_slots >= 2 && EF_Ctrl_Is_CapCode_Slot_Empty(1, 1)) { + slot = 1; + } else if (rf_cal_slots >= 3 && EF_Ctrl_Is_CapCode_Slot_Empty(2, 1)) { + slot = 2; + } else { + mfg_print("No empty slot found\r\n"); + } + + if (slot != 0xff) { + ret = EF_Ctrl_Write_CapCode_Opt(slot, capcode, program); + mfg_print("Write slot:%d\r\n", slot); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} + +void mfg_efuse_write_xtal_capcode(void) +{ + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Program_Direct_R0(0, NULL, 0); + + while (SET == EF_Ctrl_Busy()) + ; + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif +} + +int8_t mfg_efuse_read_xtal_capcode(uint8_t *capcode, uint8_t reload) +{ + uint8_t slot = 0xff; + BL_Err_Type ret = ERROR; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 3 && (!EF_Ctrl_Is_CapCode_Slot_Empty(2, reload))) { + slot = 2; + } else if (rf_cal_slots >= 2 && (!EF_Ctrl_Is_CapCode_Slot_Empty(1, reload))) { + slot = 1; + } else if (rf_cal_slots >= 1 && (!EF_Ctrl_Is_CapCode_Slot_Empty(0, reload))) { + slot = 0; + } + + if (slot != 0xff) { + mfg_print("Read slot:%d\r\n", slot); + ret = EF_Ctrl_Read_CapCode_Opt(slot, capcode, reload); + } else { + mfg_print("No written slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} + +uint8_t mfg_efuse_is_poweroffset_slot_empty(uint8_t reload) +{ + uint8_t empty = 0; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 1 && EF_Ctrl_Is_PowerOffset_Slot_Empty(0, reload)) { + mfg_print("Empty slot:%d\r\n", 0); + empty = 1; + } else if (rf_cal_slots >= 2 && EF_Ctrl_Is_PowerOffset_Slot_Empty(1, reload)) { + mfg_print("Empty slot:%d\r\n", 1); + empty = 1; + } else if (rf_cal_slots >= 3 && EF_Ctrl_Is_PowerOffset_Slot_Empty(2, reload)) { + mfg_print("Empty slot:%d\r\n", 2); + empty = 1; + } else { + mfg_print("No empty slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + return empty; +} + +int8_t mfg_efuse_write_poweroffset_pre(int8_t pwrOffset[14], uint8_t program) +{ + BL_Err_Type ret = SUCCESS; + uint8_t slot = 0xff; + int8_t pwrOffsetTmp[3]; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 1 && EF_Ctrl_Is_PowerOffset_Slot_Empty(0, 1)) { + slot = 0; + } else if (rf_cal_slots >= 2 && EF_Ctrl_Is_PowerOffset_Slot_Empty(1, 1)) { + slot = 1; + } else if (rf_cal_slots >= 3 && EF_Ctrl_Is_PowerOffset_Slot_Empty(2, 1)) { + slot = 2; + } else { + mfg_print("No empty slot found\r\n"); + } + + if (slot != 0xff) { + pwrOffsetTmp[0] = pwrOffset[0]; + pwrOffsetTmp[1] = pwrOffset[6]; + pwrOffsetTmp[2] = pwrOffset[12]; + ret = EF_Ctrl_Write_PowerOffset_Opt(slot, pwrOffsetTmp, program); + mfg_print("Write slot:%d\r\n", slot); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} + +void mfg_efuse_write_poweroffset(void) +{ + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Program_Direct_R0(0, NULL, 0); + + while (SET == EF_Ctrl_Busy()) + ; + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif +} + +int8_t mfg_efuse_read_poweroffset(int8_t pwrOffset[14], uint8_t reload) +{ + uint8_t slot = 0xff; + BL_Err_Type ret = ERROR; + int8_t pwrOffsetTmp[3]; + + int32_t step = 0; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 3 && (!EF_Ctrl_Is_PowerOffset_Slot_Empty(2, reload))) { + slot = 2; + } else if (rf_cal_slots >= 2 && (!EF_Ctrl_Is_PowerOffset_Slot_Empty(1, reload))) { + slot = 1; + } else if (rf_cal_slots >= 1 && (!EF_Ctrl_Is_PowerOffset_Slot_Empty(0, reload))) { + slot = 0; + } + + if (slot != 0xff) { + mfg_print("Read slot:%d\r\n", slot); + ret = EF_Ctrl_Read_PowerOffset_Opt(slot, pwrOffsetTmp, reload); + memset(pwrOffset, 0, 14); + + pwrOffset[0] = pwrOffsetTmp[0]; + + step = (pwrOffsetTmp[1] - pwrOffsetTmp[0]) * 100 / 6; + pwrOffset[1] = (step + 50) / 100 + pwrOffsetTmp[0]; + pwrOffset[2] = (step * 2 + 50) / 100 + pwrOffsetTmp[0]; + pwrOffset[3] = (step * 3 + 50) / 100 + pwrOffsetTmp[0]; + pwrOffset[4] = (step * 4 + 50) / 100 + pwrOffsetTmp[0]; + pwrOffset[5] = (step * 5 + 50) / 100 + pwrOffsetTmp[0]; + + pwrOffset[6] = pwrOffsetTmp[1]; + + step = (pwrOffsetTmp[2] - pwrOffsetTmp[1]) * 100 / 6; + pwrOffset[7] = (step + 50) / 100 + pwrOffsetTmp[1]; + pwrOffset[8] = (step * 2 + 50) / 100 + pwrOffsetTmp[1]; + pwrOffset[9] = (step * 3 + 50) / 100 + pwrOffsetTmp[1]; + pwrOffset[10] = (step * 4 + 50) / 100 + pwrOffsetTmp[1]; + pwrOffset[11] = (step * 5 + 50) / 100 + pwrOffsetTmp[1]; + + pwrOffset[12] = pwrOffsetTmp[2]; + + pwrOffset[13] = (step * 7 + 50) / 100 + pwrOffsetTmp[1]; + } else { + mfg_print("No written slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} + +uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload) +{ + uint8_t empty = 0; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 1 && EF_Ctrl_Is_MAC_Address_Slot_Empty(0, reload)) { + mfg_print("Empty slot:%d\r\n", 0); + empty = 1; + } else if (rf_cal_slots >= 2 && EF_Ctrl_Is_MAC_Address_Slot_Empty(1, reload)) { + mfg_print("Empty slot:%d\r\n", 1); + empty = 1; + } else if (rf_cal_slots >= 3 && EF_Ctrl_Is_MAC_Address_Slot_Empty(2, reload)) { + mfg_print("Empty slot:%d\r\n", 2); + empty = 1; + } else { + mfg_print("No empty slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + return empty; +} + +int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6], uint8_t program) +{ + BL_Err_Type ret = SUCCESS; + uint8_t slot = 0xff; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 1 && EF_Ctrl_Is_MAC_Address_Slot_Empty(0, 1)) { + slot = 0; + } else if (rf_cal_slots >= 2 && EF_Ctrl_Is_MAC_Address_Slot_Empty(1, 1)) { + slot = 1; + } else if (rf_cal_slots >= 3 && EF_Ctrl_Is_MAC_Address_Slot_Empty(2, 1)) { + slot = 2; + } else { + mfg_print("No empty slot found\r\n"); + } + + if (slot != 0xff) { + ret = EF_Ctrl_Write_MAC_Address_Opt(slot, mac, program); + mfg_print("Write slot:%d\r\n", slot); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); + +#endif + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} + +void mfg_efuse_write_macaddr(void) +{ + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Program_Direct_R0(0, NULL, 0); + + while (SET == EF_Ctrl_Busy()) + ; + + //EF_Ctrl_Program_Direct_R1(0,NULL,0); + //while(SET==EF_Ctrl_Busy()); + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif +} + +int8_t mfg_efuse_read_macaddr(uint8_t mac[6], uint8_t reload) +{ + uint8_t slot = 0xff; + BL_Err_Type ret = ERROR; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (rf_cal_slots >= 3 && (!EF_Ctrl_Is_MAC_Address_Slot_Empty(2, reload))) { + slot = 2; + } else if (rf_cal_slots >= 2 && (!EF_Ctrl_Is_MAC_Address_Slot_Empty(1, reload))) { + slot = 1; + } else if (rf_cal_slots >= 1 && (!EF_Ctrl_Is_MAC_Address_Slot_Empty(0, reload))) { + slot = 0; + } + + if (slot != 0xff) { + mfg_print("Read slot:%d\r\n", slot); + ret = EF_Ctrl_Read_MAC_Address_Opt(slot, mac, reload); + } else { + mfg_print("No written slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} + +int8_t mfg_efuse_write_pre(uint32_t addr, uint32_t *data, uint32_t countInword) +{ + BL_Err_Type ret = SUCCESS; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + if (addr > 128) { + return -1; + } + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Write_R0(addr / 4, data, countInword); + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} + +int8_t mfg_efuse_read(uint32_t addr, uint32_t *data, uint32_t countInword, uint8_t reload) +{ + BL_Err_Type ret = SUCCESS; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + if (addr > 128) { + return -1; + } + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if (reload) { + EF_Ctrl_Read_Direct_R0(addr / 4, data, countInword); + } else { + EF_Ctrl_Read_R0(addr / 4, data, countInword); + } + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} + +int8_t mfg_efuse_program(void) +{ + BL_Err_Type ret = SUCCESS; + uint8_t hdiv = 0, bdiv = 0; + HBN_ROOT_CLK_Type rtClk = GLB_Get_Root_CLK_Sel(); + + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Program_Direct_R0(0, NULL, 0); + + while (SET == EF_Ctrl_Busy()) + ; + + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); + + if (ret == SUCCESS) { + return 0; + } else { + return -1; + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_flash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..255184011f1cdd7a56aadbe48fb5e8a41d31ac38 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_flash.c @@ -0,0 +1,244 @@ +#include "bl602_mfg_flash.h" +#include "partition.h" +#include "softcrc.h" + +static rf_para_flash_t rf_para; +static uint32_t rf_para_addr = 0; +static SPI_Flash_Cfg_Type *pFlashCfg; + +#ifdef BFLB_MCU_SDK +#include "bflb_platform.h" +#define mfg_print MSG +#else +#define mfg_print printf +#endif +//#define RF_PARA_MAGIC_FLAG 0x41504652 +#define RF_PARA_MAGIC_FLAG 0x41 +#define RF_PARA_VALID_FLAG 0x5A +#define RF_PARA_PART_NAME "rf_para" + +PtTable_Stuff_Config ptTableStuff[2]; +PtTable_Entry_Config ptEntry = { 0 }; + +/*partiton need this*/ +void main(void) +{ +} + +static BL_Err_Type PtTable_Flash_Read(uint32_t addr, uint8_t *data, uint32_t len) +{ + XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg, addr, data, len); + return SUCCESS; +} + +int8_t mfg_flash_init(SPI_Flash_Cfg_Type *flashCfg) +{ + PtTable_ID_Type activeID; + PtTable_Error_Type ret; + + pFlashCfg = flashCfg; + + if (pFlashCfg != NULL) { + PtTable_Set_Flash_Operation(NULL, NULL, PtTable_Flash_Read); + activeID = PtTable_Get_Active_Partition_Need_Lock(ptTableStuff); + + if (PT_TABLE_ID_INVALID == activeID) { + mfg_print("No valid PT\r\n"); + return -1; + } + + ret = PtTable_Get_Active_Entries_By_Name(&ptTableStuff[activeID], (uint8_t *)RF_PARA_PART_NAME, &ptEntry); + + if (PT_ERROR_SUCCESS == ret) { + rf_para_addr = ptEntry.Address[0]; + mfg_print("RF para flash address=%08x\r\n", (unsigned int)rf_para_addr); + return 0; + } else { + mfg_print("Not found " RF_PARA_PART_NAME "\r\n"); + return -1; + } + } + + return -1; +} + +static int8_t mfg_flash_program(void) +{ + BL_Err_Type ret; + + mfg_print("mfg_flash_write\r\n"); + + ret = XIP_SFlash_Erase_Need_Lock_Ext(pFlashCfg, rf_para_addr, rf_para_addr + 15); + + if (ret != SUCCESS) { + mfg_print("Flash erase error\r\n"); + return -1; + } + + ret = XIP_SFlash_Write_Need_Lock_Ext(pFlashCfg, rf_para_addr, (uint8_t *)&rf_para, sizeof(rf_para)); + + if (ret != SUCCESS) { + mfg_print("Flash write error\r\n"); + return -1; + } + + return 0; +} + +static int8_t mfg_flash_read(void) +{ + BL_Err_Type ret; + + mfg_print("mfg_flash_read\r\n"); + + ret = XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg, rf_para_addr, (uint8_t *)&rf_para, sizeof(rf_para)); + + if (ret != SUCCESS) { + mfg_print("Flash write error\r\n"); + return -1; + } + + return 0; +} + +int8_t mfg_flash_write_xtal_capcode_pre(uint8_t capcode, uint8_t program) +{ + rf_para.magic = RF_PARA_MAGIC_FLAG; + rf_para.capcode_valid = RF_PARA_VALID_FLAG; + rf_para.capcode = capcode; + rf_para.crc32 = BFLB_Soft_CRC32(&rf_para.capcode_valid, sizeof(rf_para) - 8); + + if (program) { + return mfg_flash_program(); + } else { + return 0; + } +} + +void mfg_flash_write_xtal_capcode(void) +{ + mfg_flash_program(); +} + +int8_t mfg_flash_read_xtal_capcode(uint8_t *capcode, uint8_t reload) +{ + if ((reload != 0) && (mfg_flash_read() != 0)) { + return -1; + } + + if (rf_para.magic == RF_PARA_MAGIC_FLAG) { + if (rf_para.crc32 == (BFLB_Soft_CRC32(&rf_para.capcode_valid, sizeof(rf_para) - 8))) { + if (rf_para.capcode_valid == RF_PARA_VALID_FLAG) { + *capcode = rf_para.capcode; + return 0; + } + } + } + + return -1; +} + +int8_t mfg_flash_write_poweroffset_pre(int8_t pwrOffset[14], uint8_t program) +{ + rf_para.magic = RF_PARA_MAGIC_FLAG; + rf_para.poweroffset_valid = RF_PARA_VALID_FLAG; + rf_para.poweroffset[0] = pwrOffset[0]; + rf_para.poweroffset[1] = pwrOffset[6]; + rf_para.poweroffset[2] = pwrOffset[12]; + rf_para.crc32 = BFLB_Soft_CRC32(&rf_para.capcode_valid, sizeof(rf_para) - 8); + + if (program) { + return mfg_flash_program(); + } else { + return 0; + } +} + +void mfg_flash_write_poweroffset(void) +{ + mfg_flash_program(); +} + +int8_t mfg_flash_read_poweroffset(int8_t pwrOffset[14], uint8_t reload) +{ + int8_t pwrOffsetTmp[3]; + int32_t step = 0; + + if ((reload != 0) && (mfg_flash_read() != 0)) { + return -1; + } + + if (rf_para.magic == RF_PARA_MAGIC_FLAG) { + if (rf_para.crc32 == (BFLB_Soft_CRC32(&rf_para.capcode_valid, sizeof(rf_para) - 8))) { + if (rf_para.poweroffset_valid == RF_PARA_VALID_FLAG) { + memset(pwrOffset, 0, 14); + pwrOffsetTmp[0] = rf_para.poweroffset[0]; + pwrOffsetTmp[1] = rf_para.poweroffset[1]; + pwrOffsetTmp[2] = rf_para.poweroffset[2]; + + pwrOffset[0] = pwrOffsetTmp[0]; + + step = (pwrOffsetTmp[1] - pwrOffsetTmp[0]) * 100 / 6; + pwrOffset[1] = (step + 50) / 100 + pwrOffsetTmp[0]; + pwrOffset[2] = (step * 2 + 50) / 100 + pwrOffsetTmp[0]; + pwrOffset[3] = (step * 3 + 50) / 100 + pwrOffsetTmp[0]; + pwrOffset[4] = (step * 4 + 50) / 100 + pwrOffsetTmp[0]; + pwrOffset[5] = (step * 5 + 50) / 100 + pwrOffsetTmp[0]; + + pwrOffset[6] = pwrOffsetTmp[1]; + + step = (pwrOffsetTmp[2] - pwrOffsetTmp[1]) * 100 / 6; + pwrOffset[7] = (step + 50) / 100 + pwrOffsetTmp[1]; + pwrOffset[8] = (step * 2 + 50) / 100 + pwrOffsetTmp[1]; + pwrOffset[9] = (step * 3 + 50) / 100 + pwrOffsetTmp[1]; + pwrOffset[10] = (step * 4 + 50) / 100 + pwrOffsetTmp[1]; + pwrOffset[11] = (step * 5 + 50) / 100 + pwrOffsetTmp[1]; + + pwrOffset[12] = pwrOffsetTmp[2]; + + pwrOffset[13] = (step * 7 + 50) / 100 + pwrOffsetTmp[1]; + return 0; + } + } + } + + return -1; +} + +int8_t mfg_flash_write_macaddr_pre(uint8_t mac[6], uint8_t program) +{ + rf_para.magic = RF_PARA_MAGIC_FLAG; + rf_para.mac_valid = RF_PARA_VALID_FLAG; + memcpy(rf_para.mac, mac, 6); + rf_para.crc32 = BFLB_Soft_CRC32(&rf_para.capcode_valid, sizeof(rf_para) - 8); + + if (program) { + return mfg_flash_program(); + } else { + return 0; + } +} + +void mfg_flash_write_macaddr(void) +{ + mfg_flash_program(); +} + +int8_t mfg_flash_read_macaddr(uint8_t mac[6], uint8_t reload) +{ + if ((reload != 0) && (mfg_flash_read() != 0)) { + mfg_print("mfg_flash_read fail\r\n"); + return -1; + } + + if (rf_para.magic == RF_PARA_MAGIC_FLAG) { + if (rf_para.crc32 == (BFLB_Soft_CRC32(&rf_para.capcode_valid, sizeof(rf_para) - 8))) { + if (rf_para.mac_valid == RF_PARA_VALID_FLAG) { + memcpy(mac, rf_para.mac, 6); + return 0; + } + } + } + + return -1; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_media.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_media.c new file mode 100644 index 0000000000000000000000000000000000000000..338cc23d46e8d133f35708da8c14dd7e544b6336 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_media.c @@ -0,0 +1,220 @@ +#include "bl602_mfg_media.h" + +static uint8_t rf_para_on_flash = 0; + +int8_t mfg_media_init_need_lock(SPI_Flash_Cfg_Type *flashCfg) +{ + if (0 == mfg_flash_init(flashCfg)) { + rf_para_on_flash = 1; + } else { + rf_para_on_flash = 0; + } + + return 0; +} + +int8_t mfg_media_init_with_lock(SPI_Flash_Cfg_Type *flashCfg) +{ + int8_t ret; + + __disable_irq(); + ret = mfg_media_init_need_lock(flashCfg); + __enable_irq(); + + return ret; +} + +uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload) +{ + if (rf_para_on_flash) { + return 1; + } else { + return mfg_efuse_is_xtal_capcode_slot_empty(reload); + } +} + +int8_t mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode, uint8_t program) +{ + if (rf_para_on_flash) { + return mfg_flash_write_xtal_capcode_pre(capcode, program); + } else { + return mfg_efuse_write_xtal_capcode_pre(capcode, program); + } +} + +int8_t mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode, uint8_t program) +{ + int8_t ret; + + __disable_irq(); + ret = mfg_media_write_xtal_capcode_pre_need_lock(capcode, program); + __enable_irq(); + + return ret; +} + +void mfg_media_write_xtal_capcode_need_lock(void) +{ + if (rf_para_on_flash) { + return mfg_flash_write_xtal_capcode(); + } else { + return mfg_efuse_write_xtal_capcode(); + } +} + +void mfg_media_write_xtal_capcode_with_lock(void) +{ + __disable_irq(); + mfg_media_write_xtal_capcode_need_lock(); + __enable_irq(); +} + +int8_t mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode, uint8_t reload) +{ + if (rf_para_on_flash) { + return mfg_flash_read_xtal_capcode(capcode, reload); + } else { + return mfg_efuse_read_xtal_capcode(capcode, reload); + } +} + +int8_t mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode, uint8_t reload) +{ + int8_t ret; + + __disable_irq(); + ret = mfg_media_read_xtal_capcode_need_lock(capcode, reload); + __enable_irq(); + + return ret; +} + +uint8_t mfg_media_is_poweroffset_slot_empty(uint8_t reload) +{ + if (rf_para_on_flash) { + return 1; + } else { + return mfg_efuse_is_poweroffset_slot_empty(reload); + } +} + +int8_t mfg_media_write_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program) +{ + if (rf_para_on_flash) { + return mfg_flash_write_poweroffset_pre(pwrOffset, program); + } else { + return mfg_efuse_write_poweroffset_pre(pwrOffset, program); + } +} + +int8_t mfg_media_write_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program) +{ + int ret; + + __disable_irq(); + ret = mfg_media_write_poweroffset_pre_need_lock(pwrOffset, program); + __enable_irq(); + + return ret; +} + +void mfg_media_write_poweroffset_need_lock(void) +{ + if (rf_para_on_flash) { + return mfg_flash_write_poweroffset(); + } else { + return mfg_efuse_write_poweroffset(); + } +} + +void mfg_media_write_poweroffset_with_lock(void) +{ + __disable_irq(); + mfg_media_write_poweroffset_need_lock(); + __enable_irq(); +} + +int8_t mfg_media_read_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload) +{ + if (rf_para_on_flash) { + return mfg_flash_read_poweroffset(pwrOffset, reload); + } else { + return mfg_efuse_read_poweroffset(pwrOffset, reload); + } +} + +int8_t mfg_media_read_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload) +{ + int ret; + + __disable_irq(); + ret = mfg_media_read_poweroffset_need_lock(pwrOffset, reload); + __enable_irq(); + + return ret; +} + +uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload) +{ + if (rf_para_on_flash) { + return 1; + } else { + return mfg_efuse_is_macaddr_slot_empty(reload); + } +} + +int8_t mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6], uint8_t program) +{ + if (rf_para_on_flash) { + return mfg_flash_write_macaddr_pre(mac, program); + } else { + return mfg_efuse_write_macaddr_pre(mac, program); + } +} + +int8_t mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6], uint8_t program) +{ + int ret; + + __disable_irq(); + ret = mfg_media_write_macaddr_pre_need_lock(mac, program); + __enable_irq(); + + return ret; +} + +void mfg_media_write_macaddr_need_lock(void) +{ + if (rf_para_on_flash) { + return mfg_flash_write_macaddr(); + } else { + return mfg_efuse_write_macaddr(); + } +} + +void mfg_media_write_macaddr_with_lock(void) +{ + __disable_irq(); + mfg_media_write_macaddr_need_lock(); + __enable_irq(); +} + +int8_t mfg_media_read_macaddr_need_lock(uint8_t mac[6], uint8_t reload) +{ + if (rf_para_on_flash) { + return mfg_flash_read_macaddr(mac, reload); + } else { + return mfg_efuse_read_macaddr(mac, reload); + } +} + +int8_t mfg_media_read_macaddr_with_lock(uint8_t mac[6], uint8_t reload) +{ + int ret; + + __disable_irq(); + ret = mfg_media_read_macaddr_need_lock(mac, reload); + __enable_irq(); + + return ret; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_pds.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_pds.c new file mode 100644 index 0000000000000000000000000000000000000000..e406ddc330c2a5a9ec7bdf3f0a1ffe75a3c3e2dc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_pds.c @@ -0,0 +1,831 @@ +/** + ****************************************************************************** + * @file bl602_pds.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602.h" +#include "bl602_pds.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Private_Macros + * @{ + */ + +/*@} end of group PDS_Private_Macros */ + +/** @defgroup PDS_Private_Types + * @{ + */ + +/*@} end of group PDS_Private_Types */ + +/** @defgroup PDS_Private_Variables + * @{ + */ +static intCallback_Type *pdsIntCbfArra[4][1] = { { NULL }, { NULL }, { NULL }, { NULL } }; + +/*@} end of group PDS_Private_Variables */ + +/** @defgroup PDS_Global_Variables + * @{ + */ + +/*@} end of group PDS_Global_Variables */ + +/** @defgroup PDS_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PDS_Private_Fun_Declaration */ + +/** @defgroup PDS_Private_Functions + * @{ + */ + +/*@} end of group PDS_Private_Functions */ + +/** @defgroup PDS_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief PDS software reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void) +{ + uint32_t tmpVal = 0; + + tmpVal = *(uint32_t *)0x40000014; + tmpVal = tmpVal | (1 << 14); + *(uint32_t *)0x40000014 = tmpVal; + + tmpVal = *(uint32_t *)0x40000014; + tmpVal = tmpVal & ~(1 << 14); + *(uint32_t *)0x40000014 = tmpVal; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Enable power down sleep + * + * @param cfg: power down sleep configuration 1 + * @param cfg4: power down sleep configuration 2 + * @param pdsSleepCnt: power down sleep count cycle + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt) +{ + /* PDS sleep time 0 <=> sleep forever */ + /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */ + /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */ + if (!pdsSleepCnt) { + cfg->sleepForever = 1; + } else if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) { + return ERROR; + } else { + BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT); + } + + /* PDS_CTL4 config */ + BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4); + + /* PDS_CTL config */ + if (cfg->pdsStart) { + BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0))); + BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0))); + } else { + BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief power down sleep force configure + * + * @param cfg2: power down sleep force configuration 1 + * @param cfg3: power down sleep force configuration 2 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3) +{ + /* PDS_CTL2 config */ + BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2); + + /* PDS_CTL3 config */ + BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief power down sleep ram configure + * + * @param ramCfg: power down sleep force ram configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg) +{ + uint32_t tmpVal = 0; + + if (NULL == ramCfg) { + return SUCCESS; + } + + tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL); + /* enter bist mode (make ram idle/slp) */ + //tmpVal = tmpVal&~0x1F; + //tmpVal = tmpVal|0x18; + /* enter bist mode (make ram ret) */ + tmpVal = tmpVal | (0x1 << 3); + BL_WR_REG(GLB_BASE, GLB_MBIST_CTL, tmpVal); + + /* PDS_RAM1 config */ + BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL); + /* exit bist mode (make ram idle/slp) */ + //tmpVal = tmpVal&~0x1F; + /* exit bist mode (make ram ret) */ + tmpVal = tmpVal & ~(0x1 << 3); + BL_WR_REG(GLB_BASE, GLB_MBIST_CTL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief power down sleep force configure + * + * @param defaultLvCfg: power down sleep default level configuration + * @param ramCfg: ram configuration + * @param pdsSleepCnt: power down sleep time count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt) +{ + /* RAM config need fix after ECO */ + PDS_RAM_Config(ramCfg); + PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3)); + PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief power down sleep int mask + * + * @param intType: PDS int type + * @param intMask: MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + + if (intMask != UNMASK) { + tmpVal = tmpVal | (1 << (intType + PDS_INT_MASK_BIT_OFFSET)); + } else { + tmpVal = tmpVal & ~(1 << (intType + PDS_INT_MASK_BIT_OFFSET)); + } + + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep int status + * + * @param intType: PDS int type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType) +{ + return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << intType)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief clear power down sleep int status + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_IntClear(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep PLL status + * + * @param None + * + * @return PDS PLL status + * +*******************************************************************************/ +PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void) +{ + return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE); +} + +/****************************************************************************/ /** + * @brief get power down sleep RF status + * + * @param None + * + * @return PDS RF status + * +*******************************************************************************/ +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void) +{ + return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE); +} + +/****************************************************************************/ /** + * @brief get power down sleep status + * + * @param None + * + * @return PDS status + * +*******************************************************************************/ +PDS_STS_Type PDS_Get_PdsStstus(void) +{ + return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE); +} + +/****************************************************************************/ /** + * @brief PDS wakeup IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Install PDS interrupt callback function + * + * @param intType: PDS int type + * @param cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun) +{ + pdsIntCbfArra[intType][0] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Trim RC32M + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void) +{ + Efuse_Ana_RC32M_Trim_Type trim; + int32_t tmpVal = 0; + + EF_Ctrl_Read_RC32M_Trim(&trim); + + if (trim.trimRc32mExtCodeEn) { + if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) { + tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN); + BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal); + BL602_Delay_US(2); + return SUCCESS; + } + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Select RC32M as PLL ref source + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_REFCLK_SEL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Select XTAL as PLL ref source + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_REFCLK_SEL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on PLL + * + * @param xtalType: xtal type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType) +{ + uint32_t tmpVal = 0; + + /* Check parameter*/ + CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType)); + + /**************************/ + /* select PLL XTAL source */ + /**************************/ + + if ((xtalType == PDS_PLL_XTAL_RC32M) || (xtalType == PDS_PLL_XTAL_NONE)) { + PDS_Trim_RC32M(); + PDS_Select_RC32M_As_PLL_Ref(); + } else { + PDS_Select_XTAL_As_PLL_Ref(); + } + + /*******************************************/ + /* PLL power down first, not indispensable */ + /*******************************************/ + /* power off PLL first, this step is not indispensable */ + PDS_Power_Off_PLL(); + + /********************/ + /* PLL param config */ + /********************/ + + /* clkpll_icp_1u */ + /* clkpll_icp_5u */ + /* clkpll_int_frac_sw */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP); + + if (xtalType == PDS_PLL_XTAL_26M) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 0); + } + + BL_WR_REG(PDS_BASE, PDS_CLKPLL_CP, tmpVal); + + /* clkpll_c3 */ + /* clkpll_cz */ + /* clkpll_rz */ + /* clkpll_r4 */ + /* clkpll_r4_short */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ); + + if (xtalType == PDS_PLL_XTAL_26M) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 5); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 0); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 1); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4, 2); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_RZ, tmpVal); + + /* clkpll_refdiv_ratio */ + /* clkpll_postdiv */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 0x14); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 2); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal); + + /* clkpll_sdmin */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); + + switch (xtalType) { + case PDS_PLL_XTAL_NONE: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000); + break; + + case PDS_PLL_XTAL_24M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x500000); + break; + + case PDS_PLL_XTAL_32M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000); + break; + + case PDS_PLL_XTAL_38P4M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x320000); + break; + + case PDS_PLL_XTAL_40M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x300000); + break; + + case PDS_PLL_XTAL_26M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D39D); + break; + + case PDS_PLL_XTAL_RC32M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000); + break; + + default: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000); + break; + } + + BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal); + + /* clkpll_sel_fb_clk */ + /* clkpll_sel_sample_clk can be 0/1, default is 1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_FBDV); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_FB_CLK, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_SAMPLE_CLK, 1); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_FBDV, tmpVal); + + /*************************/ + /* PLL power up sequence */ + /*************************/ + + /* pu_clkpll_sfreg=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + BL602_Delay_US(5); + + /* pu_clkpll=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + /* clkpll_pu_cp=1 */ + /* clkpll_pu_pfd=1 */ + /* clkpll_pu_fbdv=1 */ + /* clkpll_pu_postdiv=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + BL602_Delay_US(5); + + /* clkpll_sdm_reset=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + BL602_Delay_US(1); + /* clkpll_reset_fbdv=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + BL602_Delay_US(2); + /* clkpll_reset_fbdv=0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + BL602_Delay_US(1); + /* clkpll_sdm_reset=0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Fix XTAL26M Setting + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION PDS_Fix_Xtal_Settig(void) +{ + uint32_t tmpVal; + + /* Fix 26M xtal clkpll_sdmin */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); + + if (0x49D39D == BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN)) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D89E); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal); + } + + return SUCCESS; +} + +/** PLL output config **/ +/* +[8] 1'h0 r/w clkpll_en_32m +[7] 1'h0 r/w clkpll_en_48m +[6] 1'h0 r/w clkpll_en_80m +[5] 1'h0 r/w clkpll_en_96m +[4] 1'h0 r/w clkpll_en_120m +[3] 1'h0 r/w clkpll_en_160m +[2] 1'h0 r/w clkpll_en_192m +[1] 1'h0 r/w clkpll_en_240m +[0] 1'h0 r/w clkpll_en_480m +*/ + +/****************************************************************************/ /** + * @brief Enable all PLL clock + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN); + tmpVal |= 0x1FF; + BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Disable all PLL clock + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN); + tmpVal &= (~0x1FF); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Enable PLL clock + * + * @param pllClk: PLL clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + uint32_t tmpVal = 0; + + /* Check parameter*/ + CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk)); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN); + tmpVal |= (1 << pllClk); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Disable PLL clock + * + * @param pllClk: PLL clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + uint32_t tmpVal = 0; + + /* Check parameter*/ + CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk)); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN); + tmpVal &= (~(1 << pllClk)); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off PLL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void) +{ + uint32_t tmpVal = 0; + + /* pu_clkpll_sfreg=0 */ + /* pu_clkpll=0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + /* clkpll_pu_cp=0 */ + /* clkpll_pu_pfd=0 */ + /* clkpll_pu_fbdv=0 */ + /* clkpll_pu_postdiv=0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power down sleep wake up interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void PDS_WAKEUP_IRQHandler(void) +{ + for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) { + if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType][0] != NULL)) { + pdsIntCbfArra[intType][0](); + } + } + + PDS_IntClear(); +} +#endif + +/*@} end of group PDS_Public_Functions */ + +/*@} end of group PDS */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_pwm.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..1c597d5df3665b3a06ae294ec13ac206ad62d7f6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_pwm.c @@ -0,0 +1,610 @@ +/** + ****************************************************************************** + * @file bl602_pwm.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_pwm.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PWM + * @{ + */ + +/** @defgroup PWM_Private_Macros + * @{ + */ +#define PWM_Get_Channel_Reg(ch) (PWM_BASE + PWM_CHANNEL_OFFSET + (ch)*0x20) +#define PWM_INT_TIMEOUT_COUNT (160 * 1000) +#define PWM_STOP_TIMEOUT_COUNT (160 * 1000) + +/*@} end of group PWM_Private_Macros */ + +/** @defgroup PWM_Private_Types + * @{ + */ + +/*@} end of group PWM_Private_Types */ + +/** @defgroup PWM_Private_Variables + * @{ + */ + +/** + * @brief PWM interrupt callback function address array + */ +static intCallback_Type *PWMIntCbfArra[PWM_CH_MAX][PWM_INT_ALL] = { + { NULL } +}; + +/*@} end of group PWM_Private_Variables */ + +/** @defgroup PWM_Global_Variables + * @{ + */ + +/*@} end of group PWM_Global_Variables */ + +/** @defgroup PWM_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph); +#endif + +/*@} end of group PWM_Private_Fun_Declaration */ + +/** @defgroup PWM_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief PWM interrupt handle + * + * @param intPeriph: Select the peripheral, such as PWM0_IRQn + * + * @return SUCCESS + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph) +{ + uint32_t i; + uint32_t tmpVal; + uint32_t timeoutCnt = PWM_INT_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_BASE; + + for (i = 0; i < PWM_CH_MAX; i++) { + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + + if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i)) != 0) { + /* Clear interrupt */ + tmpVal |= (1 << (i + PWM_INT_CLEAR_POS)); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + + /* FIXME: we need set pwm_int_clear to 0 by software and + before this,we must make sure pwm_interrupt_sts is 0*/ + do { + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + timeoutCnt--; + + if (timeoutCnt == 0) { + break; + } + } while (BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i)); + + tmpVal &= (~(1 << (i + PWM_INT_CLEAR_POS))); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + + if (PWMIntCbfArra[i][PWM_INT_PULSE_CNT] != NULL) { + /* Call the callback function */ + PWMIntCbfArra[i][PWM_INT_PULSE_CNT](); + } + } + } + + return SUCCESS; +} +#endif + +/*@} end of group PWM_Private_Functions */ + +/** @defgroup PWM_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief PWM channel init + * + * @param chCfg: PWM configuration + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg) +{ + uint32_t tmpVal; + uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(chCfg->ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(chCfg->ch)); + CHECK_PARAM(IS_PWM_CLK_TYPE(chCfg->clk)); + CHECK_PARAM(IS_PWM_POLARITY_TYPE(chCfg->pol)); + CHECK_PARAM(IS_PWM_STOP_MODE_TYPE(chCfg->stopMode)); + + /* Config pwm clock and polarity */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + + while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, chCfg->clk); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, chCfg->pol); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, chCfg->stopMode); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, chCfg->clkDiv); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, chCfg->threshold1); + BL_WR_REG(PWMx, PWM_THRE2, chCfg->threshold2); + BL_WR_REG(PWMx, PWM_PERIOD, chCfg->period); + + /* Config interrupt pulse count */ + tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT); + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, chCfg->intPulseCnt)); + PWM_IntMask(chCfg->ch, PWM_INT_PULSE_CNT, chCfg->intPulseCnt != 0 ? UNMASK : MASK); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(PWM_IRQn, PWM_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief PWM channel update source memory address and len + * + * @param ch: PWM channel + * @param period: period + * @param threshold1: threshold1 + * @param threshold2: threshold2 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Update(PWM_CH_ID_Type ch, uint16_t period, uint16_t threshold1, uint16_t threshold2) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, threshold1); + BL_WR_REG(PWMx, PWM_THRE2, threshold2); + BL_WR_REG(PWMx, PWM_PERIOD, period); +} + +/****************************************************************************/ /** + * @brief PWM channel update clock divider + * + * @param ch: PWM channel + * @param div: Clock divider + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Div(PWM_CH_ID_Type ch, uint16_t div) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + BL_WR_REG(PWMx, PWM_CLKDIV, div); +} + +/****************************************************************************/ /** + * @brief PWM channel update threshold1 + * + * @param ch: PWM channel + * @param threshold1: threshold1 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch, uint16_t threshold1) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, threshold1); +} + +/****************************************************************************/ /** + * @brief PWM channel update threshold2 + * + * @param ch: PWM channel + * @param threshold2: threshold2 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch, uint16_t threshold2) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE2, threshold2); +} + +/****************************************************************************/ /** + * @brief PWM channel update period + * + * @param ch: PWM channel + * @param period: period + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Period(PWM_CH_ID_Type ch, uint16_t period) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_PERIOD, period); +} + +/****************************************************************************/ /** + * @brief PWM get configuration + * + * @param ch: PWM channel + * @param period: period pointer + * @param threshold1: threshold1 pointer + * @param threshold2: threshold2 pointer + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Get(PWM_CH_ID_Type ch, uint16_t *period, uint16_t *threshold1, uint16_t *threshold2) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* get pwm period and duty */ + tmpVal = BL_RD_REG(PWMx, PWM_THRE1); + *threshold1 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE1); + tmpVal = BL_RD_REG(PWMx, PWM_THRE2); + *threshold2 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE2); + tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); + *period = BL_GET_REG_BITS_VAL(tmpVal, PWM_PERIOD); +} + +/****************************************************************************/ /** + * @brief PWM enable + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Enable(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm clock to enable pwm */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_CLR_REG_BIT(tmpVal, PWM_STOP_EN)); +} + +/****************************************************************************/ /** + * @brief PWM disable + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Disable(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm clock to disable pwm */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + PWM_IntMask(ch, PWM_INT_PULSE_CNT, MASK); +} + +/****************************************************************************/ /** + * @brief PWM channel software mode enable or disable + * + * @param ch: PWM channel number + * @param enable: Enable or disable + * + * @return None + * +*******************************************************************************/ +void PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, PWM_SW_MODE, enable)); +} + +/****************************************************************************/ /** + * @brief PWM channel force output high or low + * + * @param ch: PWM channel number + * @param value: Output value + * + * @return None + * +*******************************************************************************/ +void PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, PWM_SW_FORCE_VAL, value)); +} + +/****************************************************************************/ /** + * @brief PWM channel force output high + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Fource_Output(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_SW_MODE)); +} + +/****************************************************************************/ /** + * @brief Mask/Unmask the PWM interrupt + * + * @param ch: PWM channel number + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void PWM_IntMask(PWM_CH_ID_Type ch, PWM_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + CHECK_PARAM(IS_PWM_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT); + + switch (intType) { + case PWM_INT_PULSE_CNT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } else { + /* MASK(Disable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } + + break; + + case PWM_INT_ALL: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } else { + /* MASK(Disable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief Install PWM interrupt callback function + * + * @param ch: PWM channel number + * @param intType: PWM interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun) +{ + PWMIntCbfArra[ch][intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief PWM smart configure according to frequency and duty cycle function + * + * @param ch: PWM channel number + * @param frequency: PWM frequency + * @param dutyCycle: PWM duty cycle + * + * @return SUCCESS or TIMEOUT + * +*******************************************************************************/ +BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle) +{ + uint32_t tmpVal; + uint16_t clkDiv, period, threshold2; + uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + if (frequency <= 40) { + clkDiv = 625; + period = 64000 / frequency; + threshold2 = 640 * dutyCycle / frequency; + } else if (frequency <= 78) { + clkDiv = 16; + period = 2500000 / frequency; + threshold2 = 25000 * dutyCycle / frequency; + } else if (frequency <= 155) { + clkDiv = 8; + period = 5000000 / frequency; + threshold2 = 50000 * dutyCycle / frequency; + } else if (frequency <= 310) { + clkDiv = 4; + period = 10000000 / frequency; + threshold2 = 100000 * dutyCycle / frequency; + } else if (frequency <= 620) { + clkDiv = 2; + period = 20000000 / frequency; + threshold2 = 200000 * dutyCycle / frequency; + } else { + clkDiv = 1; + period = 40000000 / frequency; + threshold2 = 400000 * dutyCycle / frequency; + } + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + if (BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL) != PWM_CLK_XCLK) { + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) { + timeoutCnt--; + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_XCLK); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, PWM_POL_NORMAL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_GRACEFUL); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, clkDiv); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_PERIOD, period); + BL_WR_REG(PWMx, PWM_THRE1, 0); + BL_WR_REG(PWMx, PWM_THRE2, threshold2); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief PWM interrupt function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void PWM_IRQHandler(void) +{ + PWM_IntHandler(PWM_IRQn); +} +#endif + +/*@} end of group PWM_Public_Functions */ + +/*@} end of group PWM */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_romapi.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_romapi.c new file mode 100644 index 0000000000000000000000000000000000000000..9ec1d7fc0ade8842b4826c01ab155f8bdf3def74 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_romapi.c @@ -0,0 +1,1043 @@ +#include "bl602_romdriver.h" + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void) +{ + return RomDriver_AON_Power_On_MBG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void) +{ + return RomDriver_AON_Power_Off_MBG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void) +{ + return RomDriver_AON_Power_On_XTAL(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut) +{ + return RomDriver_AON_Set_Xtal_CapCode(capIn, capOut); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void) +{ + return RomDriver_AON_Get_Xtal_CapCode(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void) +{ + return RomDriver_AON_Power_Off_XTAL(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void) +{ + return RomDriver_AON_Power_On_BG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void) +{ + return RomDriver_AON_Power_Off_BG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void) +{ + return RomDriver_AON_Power_On_LDO11_SOC(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void) +{ + return RomDriver_AON_Power_Off_LDO11_SOC(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void) +{ + return RomDriver_AON_Power_On_LDO15_RF(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void) +{ + return RomDriver_AON_Power_Off_LDO15_RF(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void) +{ + return RomDriver_AON_Power_On_SFReg(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void) +{ + return RomDriver_AON_Power_Off_SFReg(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void) +{ + return RomDriver_AON_LowPower_Enter_PDS0(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void) +{ + return RomDriver_AON_LowPower_Exit_PDS0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + return RomDriver_ASM_Delay_Us(core, cnt); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt) +{ + return RomDriver_BL602_Delay_US(cnt); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt) +{ + return RomDriver_BL602_Delay_MS(cnt); +} + +__ALWAYS_INLINE +void *ATTR_TCM_SECTION BL602_MemCpy(void *dst, const void *src, uint32_t n) +{ + return RomDriver_BL602_MemCpy(dst, src, n); +} + +__ALWAYS_INLINE +uint32_t *ATTR_TCM_SECTION BL602_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n) +{ + return RomDriver_BL602_MemCpy4(dst, src, n); +} + +__ALWAYS_INLINE +void *ATTR_TCM_SECTION BL602_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) +{ + return RomDriver_BL602_MemCpy_Fast(pdst, psrc, n); +} + +__ALWAYS_INLINE +void *ATTR_TCM_SECTION BL602_MemSet(void *s, uint8_t c, uint32_t n) +{ + return RomDriver_BL602_MemSet(s, c, n); +} + +__ALWAYS_INLINE +uint32_t *ATTR_TCM_SECTION BL602_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n) +{ + return RomDriver_BL602_MemSet4(dst, val, n); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION BL602_MemCmp(const void *s1, const void *s2, uint32_t n) +{ + return RomDriver_BL602_MemCmp(s1, s2, n); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) +{ + return RomDriver_EF_Ctrl_Sw_AHB_Clk_0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void) +{ + return RomDriver_EF_Ctrl_Program_Efuse_0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) +{ + return RomDriver_EF_Ctrl_Load_Efuse_R0(); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) +{ + return RomDriver_EF_Ctrl_Busy(); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void) +{ + return RomDriver_EF_Ctrl_AutoLoad_Done(); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) +{ + return RomDriver_EF_Ctrl_Get_Trim_Parity(val, len); +} + +__ALWAYS_INLINE +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) +{ + return RomDriver_EF_Ctrl_Read_RC32M_Trim(trim); +} + +__ALWAYS_INLINE +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) +{ + return RomDriver_EF_Ctrl_Read_RC32K_Trim(trim); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) +{ + return RomDriver_EF_Ctrl_Clear(index, len); +} + +__ALWAYS_INLINE +GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void) +{ + return RomDriver_GLB_Get_Root_CLK_Sel(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv) +{ + return RomDriver_GLB_Set_System_CLK_Div(hclkDiv, bclkDiv); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void) +{ + return RomDriver_GLB_Get_BCLK_Div(); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void) +{ + return RomDriver_GLB_Get_HCLK_Div(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType) +{ + return RomDriver_Update_SystemCoreClockWith_XTAL(xtalType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) +{ + return RomDriver_GLB_Set_System_CLK(xtalType, clkFreq); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void) +{ + return RomDriver_System_Core_Clock_Update_From_RC32M(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) +{ + return RomDriver_GLB_Set_SF_CLK(enable, clkSel, div); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel) +{ + return RomDriver_GLB_Set_PKA_CLK_Sel(clkSel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) +{ + return RomDriver_GLB_SW_System_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) +{ + return RomDriver_GLB_SW_CPU_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) +{ + return RomDriver_GLB_SW_POR_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void) +{ + return RomDriver_GLB_Select_Internal_Flash(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void) +{ + return RomDriver_GLB_Select_External_Flash(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void) +{ + return RomDriver_GLB_Deswap_Flash_Pin(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void) +{ + return RomDriver_GLB_Swap_Flash_Pin(); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) +{ + return RomDriver_GLB_GPIO_Init(cfg); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_Set_HZ(gpioPin); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_Get_Fun(gpioPin); +} + +#if 0 +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) +{ + return RomDriver_HBN_Mode_Enter(cfg); +} +#endif + +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_HBN_Power_Down_Flash(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + return RomDriver_HBN_Enable(aGPIOIeCfg, ldoLevel, hbnLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void) +{ + return RomDriver_HBN_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + return RomDriver_HBN_Set_Ldo11_Aon_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + return RomDriver_HBN_Set_Ldo11_Rt_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + return RomDriver_HBN_Set_Ldo11_Soc_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType) +{ + return RomDriver_HBN_32K_Sel(clkType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) +{ + return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) +{ + return RomDriver_HBN_Power_On_Xtal_32K(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) +{ + return RomDriver_HBN_Power_Off_Xtal_32K(); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void) +{ + return RomDriver_HBN_Power_On_RC32K(); +} +#endif + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void) +{ + return RomDriver_HBN_Power_Off_RC32K(); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void) +{ + return RomDriver_HBN_Trim_RC32K(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable) +{ + return RomDriver_HBN_Hw_Pu_Pd_Cfg(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal) +{ + return RomDriver_HBN_Pin_WakeUp_Mask(maskVal); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec) +{ + return RomDriver_HBN_GPIO7_Dbg_Pull_Cfg(pupdEn, iesmtEn, dlyEn, dlySec); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Embedded_Flash_Pullup(uint8_t enable) +{ + return RomDriver_HBN_Set_Embedded_Flash_Pullup(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap) +{ + return RomDriver_L1C_Set_Wrap(wrap); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal) +{ + return RomDriver_L1C_Set_Way_Disable(disableVal); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable) +{ + return RomDriver_L1C_IROM_2T_Access_Set(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void) +{ + return RomDriver_PDS_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt) +{ + return RomDriver_PDS_Enable(cfg, cfg4, pdsSleepCnt); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3) +{ + return RomDriver_PDS_Force_Config(cfg2, cfg3); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg) +{ + return RomDriver_PDS_RAM_Config(ramCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt) +{ + return RomDriver_PDS_Default_Level_Config(defaultLvCfg, ramCfg, pdsSleepCnt); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void) +{ + return RomDriver_PDS_Trim_RC32M(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void) +{ + return RomDriver_PDS_Select_RC32M_As_PLL_Ref(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void) +{ + return RomDriver_PDS_Select_XTAL_As_PLL_Ref(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType) +{ + return RomDriver_PDS_Power_On_PLL(xtalType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void) +{ + return RomDriver_PDS_Enable_PLL_All_Clks(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void) +{ + return RomDriver_PDS_Disable_PLL_All_Clks(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + return RomDriver_PDS_Enable_PLL_Clk(pllClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + return RomDriver_PDS_Disable_PLL_Clk(pllClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void) +{ + return RomDriver_PDS_Power_Off_PLL(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SEC_Eng_Turn_On_Sec_Ring(void) +{ + return RomDriver_SEC_Eng_Turn_On_Sec_Ring(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void) +{ + return RomDriver_SEC_Eng_Turn_Off_Sec_Ring(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) +{ + return RomDriver_SFlash_Init(pSfCtrlCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) +{ + return RomDriver_SFlash_SetSPIMode(mode); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Read_Reg(flashCfg, regIndex, regValue, regLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Write_Reg(flashCfg, regIndex, regValue, regLen); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Busy(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Write_Enable(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Qspi_Enable(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Chip_Erase(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) +{ + return RomDriver_SFlash_Sector_Erase(flashCfg, secNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + return RomDriver_SFlash_Blk32_Erase(flashCfg, blkNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + return RomDriver_SFlash_Blk64_Erase(flashCfg, blkNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) +{ + return RomDriver_SFlash_Erase(flashCfg, startaddr, endaddr); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_SFlash_Program(flashCfg, ioMode, addr, data, len); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) +{ + return RomDriver_SFlash_GetUniqueId(data, idLen); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) +{ + return RomDriver_SFlash_GetJedecId(flashCfg, data); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) +{ + return RomDriver_SFlash_GetDeviceId(data); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Powerdown(void) +{ + return RomDriver_SFlash_Powerdown(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Releae_Powerdown(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_SetBurstWrap(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_DisableBurstWrap(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Software_Reset(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Reset_Continue_Read(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) +{ + return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, addr, len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) +{ + return RomDriver_SFlash_IDbus_Read_Enable(flashCfg, ioMode, contRead); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable) +{ + return RomDriver_SFlash_Cache_Enable_Set(wayDisable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Flush(void) +{ + return RomDriver_SFlash_Cache_Flush(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) +{ + return RomDriver_SFlash_Cache_Read_Enable(flashCfg, ioMode, contRead, wayDisable); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) +{ + return RomDriver_SFlash_Cache_Hit_Count_Get(hitCountLow, hitCountHigh); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SFlash_Cache_Miss_Count_Get(void) +{ + return RomDriver_SFlash_Cache_Miss_Count_Get(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) +{ + return RomDriver_SFlash_Cache_Read_Disable(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_SFlash_Read(flashCfg, ioMode, contRead, addr, data, len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg, readRegCmd, regValue, regLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg, writeRegCmd, regValue, regLen); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) +{ + return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg, flashContRead); +} +#endif + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) +{ + return RomDriver_SF_Cfg_Init_Internal_Flash_Gpio(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Restore_GPIO17_Fun(uint8_t fun) +{ + return RomDriver_SF_Cfg_Restore_GPIO17_Fun(fun); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +{ + return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) +{ + return RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) +{ + return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) +{ + return RomDriver_SF_Ctrl_Enable(cfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel) +{ + return RomDriver_SF_Ctrl_Select_Pad(sel); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) +{ + return RomDriver_SF_Ctrl_Set_Owner(owner); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Disable(void) +{ + return RomDriver_SF_Ctrl_Disable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) +{ + return RomDriver_SF_Ctrl_AES_Enable_BE(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) +{ + return RomDriver_SF_Ctrl_AES_Enable_LE(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) +{ + return RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hwKey, startAddr, endAddr, locked); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + return RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + return RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + return RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addrOffset); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + return RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addrOffset); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) +{ + return RomDriver_SF_Ctrl_AES_Enable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) +{ + return RomDriver_SF_Ctrl_AES_Disable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) +{ + return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) +{ + return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) +{ + return RomDriver_SF_Ctrl_Select_Clock(sahbType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) +{ + return RomDriver_SF_Ctrl_SendCmd(cfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + return RomDriver_SF_Ctrl_Icache_Set(cfg, cmdValid); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + return RomDriver_SF_Ctrl_Icache2_Set(cfg, cmdValid); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) +{ + return RomDriver_SF_Ctrl_GetBusyState(); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) +{ + return RomDriver_SF_Ctrl_Is_AES_Enable(); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) +{ + return RomDriver_SF_Ctrl_Get_Clock_Delay(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) +{ + return RomDriver_SF_Ctrl_Set_Clock_Delay(delay); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) +{ + return RomDriver_XIP_SFlash_State_Save(pFlashCfg, offset); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset) +{ + return RomDriver_XIP_SFlash_State_Restore(pFlashCfg, offset); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr) +{ + return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg, startaddr, endaddr); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg, addr, data, len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg, addr, data, len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +{ + return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg, data); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +{ + return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg, data); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen) +{ + return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg, data, idLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *dst, int len) +{ + return RomDriver_XIP_SFlash_Read_With_Lock(pFlashCfg, addr, dst, len); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *src, int len) +{ + return RomDriver_XIP_SFlash_Write_With_Lock(pFlashCfg, addr, src, len); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, int len) +{ + return RomDriver_XIP_SFlash_Erase_With_Lock(pFlashCfg, addr, len); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) +{ + return RomDriver_XIP_SFlash_Opt_Enter(aesEnable); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) +{ + return RomDriver_XIP_SFlash_Opt_Exit(aesEnable); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len) +{ + return RomDriver_BFLB_Soft_CRC32(dataIn, len); +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_romdriver.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_romdriver.c new file mode 100644 index 0000000000000000000000000000000000000000..e14b47724b4ae464cae1b5deec05462ca7fc7988 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_romdriver.c @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file bl602_romdriver.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_romdriver.h" +#include + +/** @addtogroup BL602_Periph_Driver + * @{ + */ + +/** @defgroup ROMDRIVER + * @brief ROMDRIVER common functions + * @{ + */ + +/** @defgroup ROMDRIVER_Private_Type + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Type*/ + +/** @defgroup ROMDRIVER_Private_Defines + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Defines */ + +/** @defgroup ROMDRIVER_Private_Variables + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Variables */ + +/** @defgroup ROMDRIVER_Global_Variables + * @{ + */ + +uint32_t const romDriverTable[] = { + 0x06020002, + 0x00000000, + 0x00000000, + 0x00000000, + + [ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG, + [ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG, + [ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL, + [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode, + [ROM_API_INDEX_AON_Get_Xtal_CapCode] = (uint32_t)AON_Get_Xtal_CapCode, + [ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL, + [ROM_API_INDEX_AON_Power_On_BG] = (uint32_t)AON_Power_On_BG, + [ROM_API_INDEX_AON_Power_Off_BG] = (uint32_t)AON_Power_Off_BG, + [ROM_API_INDEX_AON_Power_On_LDO11_SOC] = (uint32_t)AON_Power_On_LDO11_SOC, + [ROM_API_INDEX_AON_Power_Off_LDO11_SOC] = (uint32_t)AON_Power_Off_LDO11_SOC, + [ROM_API_INDEX_AON_Power_On_LDO15_RF] = (uint32_t)AON_Power_On_LDO15_RF, + [ROM_API_INDEX_AON_Power_Off_LDO15_RF] = (uint32_t)AON_Power_Off_LDO15_RF, + [ROM_API_INDEX_AON_Power_On_SFReg] = (uint32_t)AON_Power_On_SFReg, + [ROM_API_INDEX_AON_Power_Off_SFReg] = (uint32_t)AON_Power_Off_SFReg, + [ROM_API_INDEX_AON_LowPower_Enter_PDS0] = (uint32_t)AON_LowPower_Enter_PDS0, + [ROM_API_INDEX_AON_LowPower_Exit_PDS0] = (uint32_t)AON_LowPower_Exit_PDS0, + + [ROM_API_INDEX_ASM_Delay_Us] = (uint32_t)ASM_Delay_Us, + + [ROM_API_INDEX_BL602_Delay_US] = (uint32_t)BL602_Delay_US, + [ROM_API_INDEX_BL602_Delay_MS] = (uint32_t)BL602_Delay_MS, + [ROM_API_INDEX_BL602_MemCpy] = (uint32_t)BL602_MemCpy, + [ROM_API_INDEX_BL602_MemCpy4] = (uint32_t)BL602_MemCpy4, + [ROM_API_INDEX_BL602_MemCpy_Fast] = (uint32_t)BL602_MemCpy_Fast, + [ROM_API_INDEX_BL602_MemSet] = (uint32_t)BL602_MemSet, + [ROM_API_INDEX_BL602_MemSet4] = (uint32_t)BL602_MemSet4, + [ROM_API_INDEX_BL602_MemCmp] = (uint32_t)BL602_MemCmp, + + [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0, + [ROM_API_INDEX_EF_Ctrl_Program_Efuse_0] = (uint32_t)EF_Ctrl_Program_Efuse_0, + [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0, + [ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy, + [ROM_API_INDEX_EF_Ctrl_AutoLoad_Done] = (uint32_t)EF_Ctrl_AutoLoad_Done, + [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity, + [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim, + [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim, + [ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear, + + [ROM_API_INDEX_GLB_Get_Root_CLK_Sel] = (uint32_t)GLB_Get_Root_CLK_Sel, + [ROM_API_INDEX_GLB_Set_System_CLK_Div] = (uint32_t)GLB_Set_System_CLK_Div, + [ROM_API_INDEX_GLB_Get_BCLK_Div] = (uint32_t)GLB_Get_BCLK_Div, + [ROM_API_INDEX_GLB_Get_HCLK_Div] = (uint32_t)GLB_Get_HCLK_Div, + + [ROM_API_INDEX_Update_SystemCoreClockWith_XTAL] = (uint32_t)Update_SystemCoreClockWith_XTAL, + + [ROM_API_INDEX_GLB_Set_System_CLK] = (uint32_t)GLB_Set_System_CLK, + + [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M, + + [ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK, + [ROM_API_INDEX_GLB_Set_PKA_CLK_Sel] = (uint32_t)GLB_Set_PKA_CLK_Sel, + [ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset, + [ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset, + [ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset, + [ROM_API_INDEX_GLB_Select_Internal_Flash] = (uint32_t)GLB_Select_Internal_Flash, + [ROM_API_INDEX_GLB_Select_External_Flash] = (uint32_t)GLB_Select_External_Flash, + [ROM_API_INDEX_GLB_Deswap_Flash_Pin] = (uint32_t)GLB_Deswap_Flash_Pin, + [ROM_API_INDEX_GLB_Swap_Flash_Pin] = (uint32_t)GLB_Swap_Flash_Pin, + [ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable] = (uint32_t)GLB_GPIO_OUTPUT_Enable, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable] = (uint32_t)GLB_GPIO_OUTPUT_Disable, + [ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ, + [ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun, + + [ROM_API_INDEX_HBN_Mode_Enter] = (uint32_t)HBN_Mode_Enter, + [ROM_API_INDEX_HBN_Power_Down_Flash] = (uint32_t)HBN_Power_Down_Flash, + [ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable, + [ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset, + [ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout] = (uint32_t)HBN_Set_Ldo11_Aon_Vout, + [ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout] = (uint32_t)HBN_Set_Ldo11_Rt_Vout, + [ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout] = (uint32_t)HBN_Set_Ldo11_Soc_Vout, + [ROM_API_INDEX_HBN_32K_Sel] = (uint32_t)HBN_32K_Sel, + [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel] = (uint32_t)HBN_Set_ROOT_CLK_Sel, + [ROM_API_INDEX_HBN_Power_On_Xtal_32K] = (uint32_t)HBN_Power_On_Xtal_32K, + [ROM_API_INDEX_HBN_Power_Off_Xtal_32K] = (uint32_t)HBN_Power_Off_Xtal_32K, + [ROM_API_INDEX_HBN_Power_On_RC32K] = (uint32_t)HBN_Power_On_RC32K, + [ROM_API_INDEX_HBN_Power_Off_RC32K] = (uint32_t)HBN_Power_Off_RC32K, + [ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K, + [ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg] = (uint32_t)HBN_Hw_Pu_Pd_Cfg, + [ROM_API_INDEX_HBN_Pin_WakeUp_Mask] = (uint32_t)HBN_Pin_WakeUp_Mask, + [ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO7_Dbg_Pull_Cfg, + [ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup] = (uint32_t)HBN_Set_Embedded_Flash_Pullup, + + [ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap, + [ROM_API_INDEX_L1C_Set_Way_Disable] = (uint32_t)L1C_Set_Way_Disable, + [ROM_API_INDEX_L1C_IROM_2T_Access_Set] = (uint32_t)L1C_IROM_2T_Access_Set, + + [ROM_API_INDEX_PDS_Reset] = (uint32_t)PDS_Reset, + [ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable, + [ROM_API_INDEX_PDS_Force_Config] = (uint32_t)PDS_Force_Config, + [ROM_API_INDEX_PDS_RAM_Config] = (uint32_t)PDS_RAM_Config, + [ROM_API_INDEX_PDS_Default_Level_Config] = (uint32_t)PDS_Default_Level_Config, + [ROM_API_INDEX_PDS_Trim_RC32M] = (uint32_t)PDS_Trim_RC32M, + [ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref, + [ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref] = (uint32_t)PDS_Select_XTAL_As_PLL_Ref, + [ROM_API_INDEX_PDS_Power_On_PLL] = (uint32_t)PDS_Power_On_PLL, + [ROM_API_INDEX_PDS_Enable_PLL_All_Clks] = (uint32_t)PDS_Enable_PLL_All_Clks, + [ROM_API_INDEX_PDS_Disable_PLL_All_Clks] = (uint32_t)PDS_Disable_PLL_All_Clks, + [ROM_API_INDEX_PDS_Enable_PLL_Clk] = (uint32_t)PDS_Enable_PLL_Clk, + [ROM_API_INDEX_PDS_Disable_PLL_Clk] = (uint32_t)PDS_Disable_PLL_Clk, + [ROM_API_INDEX_PDS_Power_Off_PLL] = (uint32_t)PDS_Power_Off_PLL, + + [ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring] = (uint32_t)SEC_Eng_Turn_On_Sec_Ring, + [ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring] = (uint32_t)SEC_Eng_Turn_Off_Sec_Ring, + + [ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init, + [ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode, + [ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg, + [ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg, + [ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy, + [ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable, + [ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable, + [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable, + [ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase, + [ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase, + [ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase, + [ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase, + [ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase, + [ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program, + [ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId, + [ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId, + [ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId, + [ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown, + [ROM_API_INDEX_SFlash_Releae_Powerdown] = (uint32_t)SFlash_Releae_Powerdown, + [ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap, + [ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap, + [ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset, + [ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read, + [ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg, + [ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Enable_Set] = (uint32_t)SFlash_Cache_Enable_Set, + [ROM_API_INDEX_SFlash_Cache_Flush] = (uint32_t)SFlash_Cache_Flush, + [ROM_API_INDEX_SFlash_Cache_Read_Enable] = (uint32_t)SFlash_Cache_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Hit_Count_Get] = (uint32_t)SFlash_Cache_Hit_Count_Get, + [ROM_API_INDEX_SFlash_Cache_Miss_Count_Get] = (uint32_t)SFlash_Cache_Miss_Count_Get, + [ROM_API_INDEX_SFlash_Cache_Read_Disable] = (uint32_t)SFlash_Cache_Read_Disable, + [ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read, + [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown, + + [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Internal_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun] = (uint32_t)SF_Cfg_Restore_GPIO17_Fun, + [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock, + [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify, + [ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable, + [ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad, + [ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner, + [ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable, + [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Select_Clock] = (uint32_t)SF_Ctrl_Select_Clock, + [ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd, + [ROM_API_INDEX_SF_Ctrl_Icache_Set] = (uint32_t)SF_Ctrl_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_Icache2_Set] = (uint32_t)SF_Ctrl_Icache2_Set, + [ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState, + [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay, + [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay, + + [ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save, + [ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore, + [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Opt_Enter] = (uint32_t)XIP_SFlash_Opt_Enter, + [ROM_API_INDEX_XIP_SFlash_Opt_Exit] = (uint32_t)XIP_SFlash_Opt_Exit, + + [ROM_API_INDEX_BFLB_Soft_CRC32] = (uint32_t)BFLB_Soft_CRC32, + + [ROM_API_INDEX_FUNC_EMPTY_START... ROM_API_INDEX_FUNC_EMPTY_END] = 0xdeedbeef, +}; + +/*@} end of group ROMDRIVER_Global_Variables */ + +/** @defgroup ROMDRIVER_Private_FunctionDeclaration + * @{ + */ + +/*@} end of group ROMDRIVER_Private_FunctionDeclaration */ + +/** @defgroup ROMDRIVER_Private_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Functions */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER_COMMON */ + +/*@} end of group BL602_Periph_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sdu.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sdu.c new file mode 100644 index 0000000000000000000000000000000000000000..aa8180db4e2691045be859fc083f87467e8c873d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sdu.c @@ -0,0 +1,74 @@ +#include "bl602_sdu.h" + +volatile pHidSdio_RegMap_t SdioFuncReg[] = { + (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE), +#if NUM_FUNC == 2 + (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE + BL_SDIO_CCR_FUNC_OFFSET) +#elif NUM_FUNC == 3 + (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE + BL_SDIO_CCR_FUNC_OFFSET), + (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE + (2 * BL_SDIO_CCR_FUNC_OFFSET)) +#endif +}; + +/* if flag_mport = 0, then it supports mport + * flag_mport = 1, then mport disabled + */ +uint8_t flag_mport[NUM_FUNC] = { + 0, +#if NUM_FUNC == 2 + 1 +#elif NUM_FUNC == 3 + 1, 1 +#endif +}; + +void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value) +{ + /* We do not want to generate Download rdy for command port + * only. Currently there is a condition where if we generate + * download ready for command, followed by a download + * ready for data, the download ready for data would be gated + * by the SDIO controller. To avoid this we do not generate + * a download ready for command. Download ready is only generated for data. + */ + /* + if (!flag_mport[port_id] && + (value & SDIO_CCR_CS_DnLdRdy) && (prev_WrBitMap[port_id] == 0x01)) + { + value &= ~SDIO_CCR_CS_DnLdRdy; + if (!value) + { + return; + } + } + */ + SdioFuncReg[port_id]->CardToHostEvent = value; +} + +uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg) +{ + switch (cmd) { + case IOCTL_HID_GET_BLOCK_SIZE: { + if (port_id == FUNC_WIFI) { + uint32_t blockSize = BL_REGS8(SDIO_FN1_BLK_SIZE_0); + + blockSize |= ((BL_REGS8(SDIO_FN1_BLK_SIZE_1) & + SDIO_FN1_BLK_SIZE_1_MASK) + << 8); + + if (blockSize == 0) { + blockSize = 512; + } + + return (blockSize); + } + + break; + } + + default: + break; + } + + return 0; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sec_dbg.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sec_dbg.c new file mode 100644 index 0000000000000000000000000000000000000000..9293c9f3d45e87399d32faf2ff663bf026dc1345 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sec_dbg.c @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file bl602_sec_dbg.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_sec_dbg.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_DBG + * @{ + */ + +/** @defgroup SEC_DBG_Private_Macros + * @{ + */ + +/*@} end of group SEC_DBG_Private_Macros */ + +/** @defgroup SEC_DBG_Private_Types + * @{ + */ + +/*@} end of group SEC_DBG_Private_Types */ + +/** @defgroup SEC_DBG_Private_Variables + * @{ + */ + +/*@} end of group SEC_DBG_Private_Variables */ + +/** @defgroup SEC_DBG_Global_Variables + * @{ + */ + +/*@} end of group SEC_DBG_Global_Variables */ + +/** @defgroup SEC_DBG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_DBG_Private_Fun_Declaration */ + +/** @defgroup SEC_DBG_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Sec Dbg read chip ID + * + * @param id[8]: chip ID buffer + * + * @return None + * +*******************************************************************************/ +void Sec_Dbg_Read_Chip_ID(uint8_t id[8]) +{ + uint32_t idLow, idHigh; + + idLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_LOW); + BL_WRWD_TO_BYTEP(id, idLow); + + idHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_HIGH); + BL_WRWD_TO_BYTEP((id + 4), idHigh); +} + +/****************************************************************************/ /** + * @brief Sec Dbg read MAC address + * + * @param macAddr[6]: MAC address buffer + * + * @return None + * +*******************************************************************************/ +void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]) +{ + uint32_t macLow, macHigh; + + macLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_WIFI_MAC_LOW); + BL_WRWD_TO_BYTEP(macAddr, macLow); + + macHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_WIFI_MAC_HIGH); + macAddr[4] = (macHigh >> 0) & 0xff; + macAddr[5] = (macHigh >> 8) & 0xff; +} + +/****************************************************************************/ /** + * @brief Sec Dbg read debug mode + * + * @param None + * + * @return debug mode status + * +*******************************************************************************/ +uint32_t Sec_Dbg_Read_Dbg_Mode(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_MODE); +} + +/****************************************************************************/ /** + * @brief Sec Dbg read debug enable status + * + * @param None + * + * @return enable status + * +*******************************************************************************/ +uint32_t Sec_Dbg_Read_Dbg_Enable(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_ENA); +} + +/*@} end of group SEC_DBG_Public_Functions */ + +/*@} end of group SEC_DBG */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sec_eng.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sec_eng.c new file mode 100644 index 0000000000000000000000000000000000000000..809af8d8302579107692c53fd0b67af8b589ea46 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sec_eng.c @@ -0,0 +1,3367 @@ +/** + ****************************************************************************** + * @file bl602_sec_eng.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_sec_eng.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_ENG + * @{ + */ + +/** @defgroup SEC_ENG_Private_Macros + * @{ + */ +#define PUT_UINT32_BE(n, b, i) \ + { \ + (b)[(i)] = (uint8_t)((n) >> 24); \ + (b)[(i) + 1] = (uint8_t)((n) >> 16); \ + (b)[(i) + 2] = (uint8_t)((n) >> 8); \ + (b)[(i) + 3] = (uint8_t)((n)); \ + } +#define PUT_UINT64_BE(n, b, i) \ + { \ + (b)[(i)] = (uint8_t)((n) >> 56); \ + (b)[(i) + 1] = (uint8_t)((n) >> 48); \ + (b)[(i) + 2] = (uint8_t)((n) >> 40); \ + (b)[(i) + 3] = (uint8_t)((n) >> 32); \ + (b)[(i) + 4] = (uint8_t)((n) >> 24); \ + (b)[(i) + 5] = (uint8_t)((n) >> 16); \ + (b)[(i) + 6] = (uint8_t)((n) >> 8); \ + (b)[(i) + 7] = (uint8_t)((n)); \ + } +#define SEC_ENG_SHA_BUSY_TIMEOUT_COUNT (100 * 160 * 1000) +#define SEC_ENG_AES_BUSY_TIMEOUT_COUNT (100 * 160 * 1000) +#define SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT (100 * 160 * 1000) +#define SEC_ENG_PKA_INT_TIMEOUT_COUNT (100 * 160 * 1000) +#define SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT (100 * 160 * 1000) + +/*@} end of group SEC_ENG_Private_Macros */ + +/** @defgroup SEC_ENG_Private_Types + * @{ + */ +struct pka0_pld_cfg { + union { + struct + { + uint32_t size : 12; /*[11: 0], r/w, 0x0 */ + uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_pldi_cfg { + union { + struct + { + uint32_t rsvd : 12; /*[11: 0], r/w, 0x0 */ + uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_first_cfg { + union { + struct + { + uint32_t s0_reg_idx : 8; /*[7: 0], r/w, 0x0 */ + uint32_t s0_reg_type : 4; /*[11:8], r/w, 0x0 */ + uint32_t d_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S1_only { + union { + struct + { + uint32_t reserved_0_11 : 12; /*[11: 0], rsvd, 0x0 */ + uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S2_only { + union { + struct + { + uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ + uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /*[31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S1_S2 { + union { + struct + { + uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ + uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ + uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_bit_shift_op_cfg { + union { + struct + { + uint32_t bit_shift : 15; /*[14: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 17; /*[31:15], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +/*@} end of group SEC_ENG_Private_Types */ + +/** @defgroup SEC_ENG_Private_Variables + * @{ + */ +static intCallback_Type *secEngIntCbfArra[SEC_ENG_INT_ALL] = { NULL }; + +/*@} end of group SEC_ENG_Private_Variables */ + +/** @defgroup SEC_ENG_Global_Variables + * @{ + */ + +/*@} end of group SEC_ENG_Global_Variables */ + +/** @defgroup SEC_ENG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_ENG_Private_Fun_Declaration */ + +/** @defgroup SEC_ENG_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief SHA256 initialization function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param shaType: SHA type + * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes + * @param padding[16]: SHA padding buffer for store padding data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t shaTmpBuf[16], uint32_t padding[16]) +{ + uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); + + /* Deal SHA control register to set SHA mode */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MODE, shaType); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + /* Clear context */ + memset(shaCtx, 0, sizeof(SEC_Eng_SHA256_Ctx)); + + /* Init temp buffer and padding buffer */ + shaCtx->shaBuf = shaTmpBuf; + shaCtx->shaPadding = padding; + BL602_MemSet(shaCtx->shaPadding, 0, 64); + BL602_MemSet(shaCtx->shaPadding, 0x80, 1); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_SHA_IRQn, SEC_SHA_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief SHA start function + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Set SHA enable */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_EN); + /* Hash sel 0 for new start */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_HASH_SEL); + + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief SHA256 update input data function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param input: SHA input data pointer, and the address should be word align + * @param len: SHA input data length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) +{ + uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + uint32_t fill; + uint32_t left; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + if (len == 0) { + return SUCCESS; + } + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + /* SHA need set se_sha_sel to 1 to keep the last SHA state */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_HASH_SEL, shaCtx->shaFeed); + + left = shaCtx->total[0] & 0x3F; + fill = 64 - left; + + shaCtx->total[0] += (uint32_t)len; + shaCtx->total[0] &= 0xFFFFFFFF; + + if (shaCtx->total[0] < (uint32_t)len) { + shaCtx->total[1]++; + } + + if (left && len >= fill) { + BL602_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); + /* Set data source address */ + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_MSA, (uint32_t)shaCtx->shaBuf); + + /* Set data length */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MSG_LEN, 1); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + /* Trigger */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_TRIG_1T); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + shaCtx->shaFeed = 1; + input += fill; + len -= fill; + left = 0; + } + + fill = len / 64; + len = len % 64; + + if (fill > 0) { + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + /* SHA need set se_sha_sel to 1 to keep the last sha state */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_HASH_SEL, shaCtx->shaFeed); + + /* Fill data */ + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_MSA, (uint32_t)input); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MSG_LEN, fill); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_TRIG_1T); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + input += (fill * 64); + shaCtx->shaFeed = 1; + } + + if (len > 0) { + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + /* Copy left data into temp buffer */ + BL602_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); + } + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SHA256 finish to get output function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param hash: SHA output data of SHA result + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t shaMode; + uint8_t msgLen[8]; + uint8_t *p = (uint8_t *)hash; + uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3); + low = (shaCtx->total[0] << 3); + + PUT_UINT32_BE(high, msgLen, 0); + PUT_UINT32_BE(low, msgLen, 4); + + last = shaCtx->total[0] & 0x3F; + padn = (last < 56) ? (56 - last) : (120 - last); + + Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); + + /* Wait for shaPadding idle */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + BL602_MemCpy_Fast(shaCtx->shaPadding, msgLen, 8); + Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 8); + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MODE); + /* Copy SHA value */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_0); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_1); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_2); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_3); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_4); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + + if (shaMode == SEC_ENG_SHA224 || shaMode == SEC_ENG_SHA256) { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_5); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_6); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + + if (shaMode == SEC_ENG_SHA256) { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_7); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + } + } + + /* Disable SHA engine*/ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_HASH_SEL); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_EN); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SHA enable link mode and set link config address + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Enable sha and enable link mode */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief SHA disable link mode + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Disable sha and disable link mode */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief SHA256 link mode initialization function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param linkAddr: SHA link configure address + * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes + * @param padding[16]: SHA padding buffer for store padding data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t shaTmpBuf[16], uint32_t padding[16]) +{ + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Clear context */ + memset(shaCtx, 0, sizeof(SEC_Eng_SHA256_Link_Ctx)); + + /* Init temp buffer,padding buffer and link address */ + shaCtx->shaBuf = shaTmpBuf; + shaCtx->shaPadding = padding; + BL602_MemSet(shaCtx->shaPadding, 0, 64); + BL602_MemSet(shaCtx->shaPadding, 0x80, 1); + shaCtx->linkAddr = linkAddr; + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_SHA_IRQn, SEC_SHA_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief SHA256 link mode update input data function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param input: SHA input data pointer, and the address should be word align + * @param len: SHA input data length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t fill; + uint32_t left; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + if (len == 0) { + return SUCCESS; + } + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Set link address */ + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); + + left = shaCtx->total[0] & 0x3F; + fill = 64 - left; + + shaCtx->total[0] += (uint32_t)len; + shaCtx->total[0] &= 0xFFFFFFFF; + + if (shaCtx->total[0] < (uint32_t)len) { + shaCtx->total[1]++; + } + + if (left && len >= fill) { + BL602_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); + /* Set data source address */ + *(uint32_t *)(shaCtx->linkAddr + 4) = (uint32_t)shaCtx->shaBuf; + + /* Set data length */ + *((uint16_t *)shaCtx->linkAddr + 1) = 1; + /* Trigger */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); + + /* Choose accumulating last hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) |= 0x40; + input += fill; + len -= fill; + left = 0; + } + + fill = len / 64; + len = len % 64; + + if (fill > 0) { + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Fill data */ + *(uint32_t *)(shaCtx->linkAddr + 4) = (uint32_t)input; + *((uint16_t *)shaCtx->linkAddr + 1) = fill; + + /* Trigger */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); + + input += (fill * 64); + /* Choose accumulating last hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) |= 0x40; + } + + if (len > 0) { + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Copy left data into temp buffer */ + BL602_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); + } + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SHA256 link mode finish to get output function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param hash: SHA output data of SHA result + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t msgLen[8]; + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t shaMode = (*(uint32_t *)shaCtx->linkAddr) >> 2 & 0x7; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Set link address */ + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); + + high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3); + low = (shaCtx->total[0] << 3); + + PUT_UINT32_BE(high, msgLen, 0); + PUT_UINT32_BE(low, msgLen, 4); + + last = shaCtx->total[0] & 0x3F; + padn = (last < 56) ? (56 - last) : (120 - last); + + Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); + + /* Wait for shaPadding idle */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, msgLen, 8); + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Get result according to SHA mode,result is placed in (link address + offset:8) */ + switch (shaMode) { + case 0: + BL602_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 32); + break; + + case 1: + BL602_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 28); + break; + + case 2: + BL602_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 20); + break; + + case 3: + BL602_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 20); + break; + + default: + break; + } + + /* Choose new hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) &= ~0x40; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AES initialization function + * + * @param aesCtx: AES context pointer + * @param aesNo: AES ID type + * @param aesType: AES type:ECB,CTR,CBC + * @param keyType: AES key type:128,256,192 + * @param enDecType: AES encryption or decryption + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_TYPE(aesType)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_TYPE(keyType)); + CHECK_PARAM(IS_SEC_ENG_AES_ENDEC_TYPE(enDecType)); + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY)); + + /* Set AES mode type*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_BLOCK_MODE, aesType); + + /* Set AES key type */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE, keyType); + + /* Set AES encryption or decryption */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_DEC_EN, enDecType); + + /* Clear dec_key_sel to select new key */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL); + + /* Clear aes iv sel to select new iv */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_IV_SEL); + + /* Clear AES interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_INT_CLR_1T); + + /* Enable AES */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_EN); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + /* Clear AES context */ + memset(aesCtx, 0, sizeof(SEC_Eng_AES_Ctx)); + + /* Enable ID0 Access for HW Key */ + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x03); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AES enable function,set AES bigendian + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_ENDIAN, 0x0f); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief AES enable function,set AES littleendian + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_ENDIAN, 0x00); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief AES enable link mode + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Enable aes link mode */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE)); + + /* Enable ID0 Access for HW Key */ + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x03); +} + +/****************************************************************************/ /** + * @brief AES disable link mode + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Disable aes link mode */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE)); +} + +/****************************************************************************/ /** + * @brief AES work in link mode + * + * @param aesNo: AES ID type + * @param linkAddr: Address of config structure in link mode + * @param in: AES input data buffer to deal with + * @param len: AES input data length + * @param out: AES output data buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Link address should word align */ + if ((linkAddr & 0x03) != 0 || len % 16 != 0) { + return ERROR; + } + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); + + /* Set link address */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_LINK, linkAddr); + + /* Change source buffer address and destination buffer address */ + *(uint32_t *)(linkAddr + 4) = (uint32_t)in; + *(uint32_t *)(linkAddr + 8) = (uint32_t)out; + + /* Set data length */ + *((uint16_t *)linkAddr + 1) = len / 16; + + /* Enable aes */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN)); + + /* Start aes engine and wait finishing */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T)); + __NOP(); + __NOP(); + timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); + + /* Disable aes */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AES set hardware key source:efuse region for CPU0 or region efuse for CPU1 + * + * @param aesNo: AES ID type + * @param src: AES key source type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_SBOOT); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_SBOOT_KEY_SEL, src); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_SBOOT, tmpVal); +} + +/****************************************************************************/ /** + * @brief AES set KEY and IV + * + * @param aesNo: AES ID type + * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW + * @param key: AES KEY pointer + * @param iv: AES IV pointer + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t keyType; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); + + /* Set IV */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + + /* Select hardware key */ + if (keySrc == SEC_ENG_AES_KEY_HW) { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_HW); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_0, *key); + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0, tmpVal); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_1, *key); + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1, tmpVal); + + return; + } + + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_7, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_6, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE); + + if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) { + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS) { + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_1, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_0, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + } + + /* Select software key */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_SW); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief AES set KEY and IV with bigendian + * + * @param aesNo: AES ID type + * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW + * @param key: AES KEY pointer + * @param iv: AES IV pointer + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t keyType; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); + + /* Set IV */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_0, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_1, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_2, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_3, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + + /* Select hardware key */ + if (keySrc == SEC_ENG_AES_KEY_HW) { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_HW); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_0, *key); + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0, tmpVal); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_1, *key); + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1, tmpVal); + + return; + } + + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_0, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_1, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, BL_RDWD_FRM_BYTEP(key)); + key += 4; + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE); + + if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) { + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, BL_RDWD_FRM_BYTEP(key)); + key += 4; + } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS) { + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_6, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_7, BL_RDWD_FRM_BYTEP(key)); + key += 4; + } + + /* Select software key */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_SW); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief AES set counter byte type in CTR mode + * + * @param aesNo: AES ID type + * @param counterType: AES counter type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_COUNTER_TYPE(counterType)); + + /* Set counter type */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_CTR_LEN, counterType)); +} + +/****************************************************************************/ /** + * @brief AES encrypt or decrypt input data + * + * @param aesCtx: AES context pointer + * @param aesNo: AES ID type + * @param in: AES input data buffer to deal with + * @param len: AES input data length + * @param out: AES output data buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, uint8_t *out) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + if (len % 16 != 0) { + return ERROR; + } + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY)); + + /* Clear trigger */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_TRIG_1T); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + /* Set input and output address */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_MSA, (uint32_t)in); + BL_WR_REG(AESx, SEC_ENG_SE_AES_MDA, (uint32_t)out); + + /* Set message length */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MSG_LEN, len / 16); + + if (aesCtx->mode == SEC_ENG_AES_CTR) { + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL); + } + + /* Set IV sel:0 for new, 1 for last */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_IV_SEL, aesCtx->aesFeed); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + /* Trigger AES Engine */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_TRIG_1T); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + /* Wait finished */ + timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY)); + + aesCtx->aesFeed = 1; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AES finish function, clean register + * + * @param aesNo: AES ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY)); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_EN); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_IV_SEL); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief TRNG enable TRNG interrupt + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_Trng_Enable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + /* FIXME:default reseed number is 0x1ff, to verify, use 0xa to speed up */ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_TRNG_RESEED_N,0x1ff); + + /* No interrupt as default */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_EN); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + /* busy will be set to 1 after trigger, the gap is 1T */ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + do { + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_BUSY)); + + /* Clear trng interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_TRNG_IRQn, SEC_TRNG_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief TRNG enable TRNG interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Enable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_MASK); + + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief TRNG disable TRNG interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Disable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_MASK); + + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief TRNG get random data out + * + * @param data[32]: TRNG output data + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]) +{ + uint8_t *p = (uint8_t *)data; + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + /* Trigger */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + /* busy will be set to 1 after trigger, the gap is 1T */ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + do { + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_BUSY)); + + /* copy trng value */ + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_0)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_1)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_2)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_3)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_4)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_5)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_6)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_7)); + p += 4; + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + /* Clear data */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief TRNG get random data out + * + * @param data: TRNG output data buffer + * + * @param len: total length to get in bytes + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len) +{ + uint8_t tmpBuf[32]; + uint32_t readLen = 0; + uint32_t i = 0, cnt = 0; + + while (readLen < len) { + if (Sec_Eng_Trng_Read(tmpBuf) != SUCCESS) { + return -1; + } + + cnt = len - readLen; + + if (cnt > sizeof(tmpBuf)) { + cnt = sizeof(tmpBuf); + } + + for (i = 0; i < cnt; i++) { + data[readLen + i] = tmpBuf[i]; + } + + readLen += cnt; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief TRNG Interrupt Read Trigger + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Read_Trigger(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + Sec_Eng_Trng_Int_Enable(); + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + /* Trigger */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief TRNG get random data out with Interrupt + * + * @param data[32]: TRNG output data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Read(uint8_t data[32]) +{ + uint8_t *p = (uint8_t *)data; + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + /* copy trng value */ + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_0)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_1)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_2)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_3)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_4)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_5)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_6)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_7)); + p += 4; + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + /* Clear data */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable TRNG + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Disable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_EN); + //tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_RESEED_N); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T); + + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief PKA Reset + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Reset(void) +{ + uint8_t val; + + //Disable sec engine + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, 0); + + //Enable sec engine + val = 1 << 3; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, val); +} + +/****************************************************************************/ /** + * @brief PKA Enable big endian + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_BigEndian_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_PKA_IRQn, SEC_PKA_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief PKA Enable little endian + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LittleEndian_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_PKA_IRQn, SEC_PKA_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief PKA clear interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Clear_Int(void) +{ + uint32_t ctrl; + + ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + ctrl = BL_SET_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); + + ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + ctrl = BL_CLR_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); +} + +/****************************************************************************/ /** + * @brief PKA get Register size according to Register type + * + * @param reg_type: PKA Register type + * + * @return Register size + * +*******************************************************************************/ +static uint16_t Sec_Eng_PKA_Get_Reg_Size(SEC_ENG_PKA_REG_SIZE_Type reg_type) +{ + switch (reg_type) { + case SEC_ENG_PKA_REG_SIZE_8: + return 8; + + case SEC_ENG_PKA_REG_SIZE_16: + return 16; + + case SEC_ENG_PKA_REG_SIZE_32: + return 32; + + case SEC_ENG_PKA_REG_SIZE_64: + return 64; + + case SEC_ENG_PKA_REG_SIZE_96: + return 96; + + case SEC_ENG_PKA_REG_SIZE_128: + return 128; + + case SEC_ENG_PKA_REG_SIZE_192: + return 192; + + case SEC_ENG_PKA_REG_SIZE_256: + return 256; + + case SEC_ENG_PKA_REG_SIZE_384: + return 384; + + case SEC_ENG_PKA_REG_SIZE_512: + return 512; + + default: + return 0; + } +} + +/****************************************************************************/ /** + * @brief PKA set pre-load register configuration + * + * @param size: Data size in word to write + * @param regIndex: Register index + * @param regType: Register type + * @param op: PKA operation + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Pld_Cfg(uint16_t size, uint8_t regIndex, SEC_ENG_PKA_REG_SIZE_Type regType, SEC_ENG_PKA_OP_Type op, uint8_t lastOp) +{ + struct pka0_pld_cfg cfg; + + cfg.value.BF.size = size; + cfg.value.BF.d_reg_index = regIndex; + cfg.value.BF.d_reg_type = regType; + cfg.value.BF.op = op; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA write common operation first configuration + * + * @param s0RegIndex: Register index + * @param s0RegType: Register type + * @param dRegIndex: Result Register index + * @param dRegType: Result Register type + * @param op: PKA operation + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_First_Cfg(uint8_t s0RegIndex, uint8_t s0RegType, uint8_t dRegIndex, uint8_t dRegType, + uint8_t op, uint8_t lastOp) +{ + struct pka0_common_op_first_cfg cfg; + + cfg.value.BF.s0_reg_idx = s0RegIndex; + cfg.value.BF.s0_reg_type = s0RegType; + + if (op != SEC_ENG_PKA_OP_LCMP) { + cfg.value.BF.d_reg_idx = dRegIndex; + cfg.value.BF.d_reg_type = dRegType; + } + + cfg.value.BF.op = op; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA write common operation second configuration1 + * + * @param s1RegIndex: Register index + * @param s1RegType: Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(uint8_t s1RegIndex, uint8_t s1RegType) +{ + struct pka0_common_op_snd_cfg_S1_only cfg; + + cfg.value.BF.s1_reg_idx = s1RegIndex; + cfg.value.BF.s1_reg_type = s1RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA write common operation second configuration2 + * + * @param s2RegIndex: Register index + * @param s2RegType: Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(uint8_t s2RegIndex, uint8_t s2RegType) +{ + struct pka0_common_op_snd_cfg_S2_only cfg; + + cfg.value.BF.s2_reg_idx = s2RegIndex; + cfg.value.BF.s2_reg_type = s2RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA write common operation second configuration1 and configuration 2 + * + * @param s1RegIndex: Configuration 1 Register index + * @param s1RegType: Configuration 1 Register type + * @param s2RegIndex: Configuration 2 Register index + * @param s2RegType: Configuration 3 Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(uint8_t s1RegIndex, uint8_t s1RegType, uint8_t s2RegIndex, uint8_t s2RegType) +{ + struct pka0_common_op_snd_cfg_S1_S2 cfg; + + cfg.value.BF.s1_reg_idx = s1RegIndex; + cfg.value.BF.s1_reg_type = s1RegType; + cfg.value.BF.s2_reg_idx = s2RegIndex; + cfg.value.BF.s2_reg_type = s2RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA wait for complete interrupt + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +static BL_Err_Type Sec_Eng_PKA_Wait_ISR(void) +{ + uint32_t pka0_ctrl; + uint32_t timeoutCnt = SEC_ENG_PKA_INT_TIMEOUT_COUNT; + + do { + pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (!BL_GET_REG_BITS_VAL(pka0_ctrl, SEC_ENG_SE_PKA_0_INT)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief PKA read block data from register + * + * @param dest: Pointer to buffer address + * @param src: Pointer to register address + * @param len: Data len in word + * + * @return None + * +*******************************************************************************/ +#ifdef ARCH_ARM +#ifndef __GNUC__ +__ASM void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + PUSH{ R3 - R6, LR } Start0 + CMP R2, +# 4 BLT Finish0 + LDR R3, + [R1] LDR R4, [R1] LDR R5, [R1] LDR R6, [R1] STMIA R0 !, { R3 - R6 } SUBS R2, R2, #4 B Start0 Finish0 POP + { + R3 - R6, PC + } +} +#else +void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + __asm__ __volatile__("push {r3-r6,lr}\n\t" + "Start0 :" + "cmp r2,#4\n\t" + "blt Finish0\n\t" + "ldr r3,[r1]\n\t" + "ldr r4,[r1]\n\t" + "ldr r5,[r1]\n\t" + "ldr r6,[r1]\n\t" + "stmia r0!,{r3-r6}\n\t" + "sub r2,r2,#4\n\t" + "b Start0\n\t" + "Finish0 :" + "pop {r3-r6,pc}\n\t"); +} +#endif +#endif +#ifdef ARCH_RISCV +void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + uint32_t wrLen = len - len % 4; + uint32_t i; + + for (i = 0; i < wrLen; i++) { + dest[i] = *src; + } +} +#endif + +/****************************************************************************/ /** + * @brief PKA Write block data to register + * + * @param dest: Pointer to register address + * @param src: Pointer to buffer address + * @param len: Data len in word + * + * @return None + * +*******************************************************************************/ +#ifdef ARCH_ARM +#ifndef __GNUC__ +__ASM void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + PUSH{ R3 - R6, LR } Start1 + CMP R2, +# 4 BLT Finish1 + LDMIA R1 !, + { R3 - R6 } STR R3, [R0] STR R4, [R0] STR R5, [R0] STR R6, [R0] SUBS R2, R2, #4 B Start1 Finish1 POP + { + R3 - R6, PC + } +} +#else +void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + __asm__ __volatile__("push {r3-r6,lr}\n\t" + "Start1 :" + "cmp r2,#4\n\t" + "blt Finish1\n\t" + "ldmia r1!,{r3-r6}\n\t" + "str r3,[r0]\n\t" + "str r4,[r0]\n\t" + "str r5,[r0]\n\t" + "str r6,[r0]\n\t" + "sub r2,r2,#4\n\t" + "b Start1\n\t" + "Finish1 :" + "pop {r3-r6,pc}\n\t"); +} +#endif +#endif +#ifdef ARCH_RISCV +void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + uint32_t wrLen = len - len % 4; + uint32_t i; + + for (i = 0; i < wrLen; i++) { + *dest = src[i]; + } +} +#endif + +/****************************************************************************/ /** + * @brief PKA get result + * + * @param result: Pointer to store result + * @param retSize: Result length in word + * @param regLen: register length in byte + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Get_Result(uint32_t *result, uint8_t retSize, uint16_t regLen) +{ + uint32_t ret_data = 0x00; + int index = 0x00; + + /* Wait for the result */ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + Sec_Eng_PKA_Read_Block(result, (uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), retSize); + index = retSize - (retSize % 4); + + while (index < retSize) { + ret_data = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW); + result[index] = ret_data; + index++; + } +} + +/****************************************************************************/ /** + * @brief PKA load data to register + * + * @param regType: Register type + * @param regIndex: Register index + * @param data: Data buffer + * @param size: Data length in word + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, uint8_t lastOp) +{ + int index = 0x00; + uint16_t regLen = Sec_Eng_PKA_Get_Reg_Size(regType); + + Sec_Eng_PKA_Write_Pld_Cfg(size, regIndex, regType, SEC_ENG_PKA_OP_CTLIR_PLD, lastOp); + + if (size > regLen / 4) { + size = regLen / 4; + } + + Sec_Eng_PKA_Write_Block((uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), data, size); + index = size - (size % 4); + + while (index < size) { + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data[index]); + index++; + } +} + +/****************************************************************************/ /** + * @brief PKA read data from register + * + * @param regType: Register type + * @param regIdx: Register index + * @param result: Data buffer + * @param retSize: Data length in word + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize) +{ + uint16_t regSize; + uint32_t dummyData = 0; + + regSize = Sec_Eng_PKA_Get_Reg_Size(regType); + + if (retSize > regSize / 4) { + result = NULL; + return; + } + + Sec_Eng_PKA_Write_Pld_Cfg(retSize, regIdx, regType, SEC_ENG_PKA_OP_CFLIR_BUFFER, 1); + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + Sec_Eng_PKA_Get_Result(result, retSize, regSize); +} + +/****************************************************************************/ /** + * @brief PKA clear register + * + * @param dRegType: Register type + * @param dRegIdx: Register index + * @param size: Data length in word + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Pld_Cfg(size, dRegIdx, dRegType, SEC_ENG_PKA_OP_CLIR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA load data to register + * + * @param regType: regType: Register type + * @param regIndex: regIndex: Register index + * @param data: data: Data buffer + * @param lastOp: size: Data length in word + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp) +{ + struct pka0_pldi_cfg cfg; + + cfg.value.BF.rsvd = 0; + cfg.value.BF.d_reg_index = regIndex; + cfg.value.BF.d_reg_type = regType; + cfg.value.BF.op = SEC_ENG_PKA_OP_SLIR; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA negative source data:D = (1 << SIZE{S0})-S0 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_NLIR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA move data:D = S0 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOVDAT, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA resize data:D = S0, D.Size = S0.Size + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_RESIZE, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod add:D = (S0 + S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MADD, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod sub:D = (S0 - S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSUB, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod :D = S0 mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MREM, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod mul:D = (S0 * S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MMUL, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod sqr:D = (S0 ^ 2) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSQR, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod exp:D = (S0 ^ S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MEXP, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod exp:D = (S0 ^ (S2-2) ) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MINV, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA Report COUT to 1 when S0 < S1 + * + * @param cout: Compare result + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx) +{ + uint32_t pka0_ctrl = 0x00; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, 0, 0, SEC_ENG_PKA_OP_LCMP, 1); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + + *cout = (pka0_ctrl & SEC_ENG_PKA_STATUS_LAST_OPC_MASK) >> SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET; +} + +/****************************************************************************/ /** + * @brief PKA add:D = S0 + S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LADD, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA sub:D = S0 - S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSUB, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mul:D = S0 * S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA sqr:D = S0^2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSQR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA div:D = S0 / S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA shift:D = S0 << BIT SHIFT + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL2N, 0); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA shift:D = S0 >> BIT SHIFT + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV2N, 0); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod 2N:D = S0 % ((1 << BIT SHIFT)-1) + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOD2N, lastOp); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA GF to Mont filed 2N:d = (a<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_glb.h" +#include "bl602_sf_cfg.h" +#include "softcrc.h" +#include "bl602_xip_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Private_Macros + * @{ + */ +#define BFLB_FLASH_CFG_MAGIC "FCFG" + +/*@} end of group SF_CFG_Private_Macros */ + +/** @defgroup SF_CFG_Private_Types + * @{ + */ +typedef struct +{ + uint32_t jedecID; + char *name; + const SPI_Flash_Cfg_Type *cfg; +} Flash_Info_t; + +/*@} end of group SF_CFG_Private_Types */ + +/** @defgroup SF_CFG_Private_Variables + * @{ + */ +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 0, + .cReadMode = 0xFF, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3d, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 3, + .qeData = 0, +}; +#if 0 +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80BV = +{ + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3d, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 3, + .qeData = 0, +}; +#endif +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 400, + .timeE32k = 1600, + .timeE64k = 2000, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 3, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Issi = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x9d, + + .deBurstWrapCmd = 0xC0, + .deBurstWrapCmdDmyClk = 0x00, + .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, + .deBurstWrapData = 0x00, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0, + .qeBit = 0x06, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0xC0, + .burstWrapCmdDmyClk = 0x00, + .burstWrapDataMode = SF_CTRL_DATA_1_LINE, + .burstWrapData = 0x06, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 5, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 32 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 8 / 8, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0x12, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32C = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xC2, + + .deBurstWrapCmd = 0xC0, + .deBurstWrapCmdDmyClk = 0x00, + .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, + .deBurstWrapData = 0x10, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0, + .qeBit = 0x06, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA5, + + .burstWrapCmd = 0xC0, + .burstWrapCmdDmyClk = 0x00, + .burstWrapDataMode = SF_CTRL_DATA_1_LINE, + .burstWrapData = 0x02, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x38, + .qppAddrMode = SF_CTRL_ADDR_4_LINES, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 45, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_1635F = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xC2, + + .deBurstWrapCmd = 0xC0, + .deBurstWrapCmdDmyClk = 0x00, + .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, + .deBurstWrapData = 0x10, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0, + .qeBit = 0x06, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA5, + + .burstWrapCmd = 0xC0, + .burstWrapCmdDmyClk = 0x00, + .burstWrapDataMode = SF_CTRL_DATA_1_LINE, + .burstWrapData = 0x02, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x38, + .qppAddrMode = SF_CTRL_ADDR_4_LINES, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 45, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx_Q80B_F16B = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x0B, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = 0x14, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 6000, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x0B, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 6000, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q80L_Q80H_Q16H = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x85, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3d, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 8, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q32H = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x85, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 8, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x68, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FT_VQ80 = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 8, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { + { + .jedecID = 0x1440ef, + //.name="Winb_80DV_08_33", + .cfg = &flashCfg_Winb_80DV, + }, + { + .jedecID = 0x1540ef, + //.name="Winb_16DV_16_33", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1570ef, + //.name="Winb_16jV_16_33_DTR", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1640ef, + //.name="Winb_32FV_32_33", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1460ef, + //.name="Winb_80EW_08_18", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1560ef, + //.name="Winb_16FW_16_18", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1660ef, + //.name="Winb_32FW_32_18", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1860ef, + //.name="Winb_128FW_128_18", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1680ef, + //.name="Winb_32JW_32_18", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x13605e, + //.name="Zbit_04_33", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x14605e, + //.name="Zbit_08_33", + .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x14609d, + //.name="ISSI_08_33", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x15609d, + //.name="ISSI_16_33", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x16609d, + //.name="ISSI_32_33", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x14709d, + //.name="ISSI_08_18", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x15709d, + //.name="ISSI_16_18", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x16709d, + //.name="ISSI_32_18", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x1440C8, + //.name="GD_Q08E_08_33", + .cfg = &flashCfg_Gd_Q80E_Q16E, + }, + { + .jedecID = 0x1540C8, + //.name="GD_Q16E_16_33", + .cfg = &flashCfg_Gd_Q80E_Q16E, + }, + { + .jedecID = 0x1640C8, + //.name="GD_Q32C_32_33", + .cfg = &flashCfg_Gd_Q32C, + }, + { + .jedecID = 0x1460C8, + //.name="GD_LQ08C_08_18", + .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID = 0x1560C8, + //.name="GD_LE16C_16_18", + .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID = 0x1660C8, + //.name="GD_LQ32D_32_18", + .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID = 0x1465C8, + //.name="GD_WQ80E_80_33", + .cfg = &flashCfg_Gd_WQ80E_WQ16E, + }, + { + .jedecID = 0x1565C8, + //.name="GD_WQ16E_16_33", + .cfg = &flashCfg_Gd_WQ80E_WQ16E, + }, + { + .jedecID = 0x1665C8, + //.name="GD_WQ32E_32_33", + .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID = 0x3425C2, + //.name="MX_25V80_08_18", + .cfg = &flashCfg_Mxic, + }, + { + .jedecID = 0x3525C2, + //.name="MX_25U16_35_18", + .cfg = &flashCfg_Mxic_1635F, + }, + { + .jedecID = 0x3625C2, + //.name="MX_25V32_32_18", + .cfg = &flashCfg_Mxic, + }, + { + .jedecID = 0x13400B, + //.name="XT_25F04D_04_33", + .cfg = &flashCfg_Xtx, + }, + { + .jedecID = 0x15400B, + //.name="XT_25F16B_16_33", + .cfg = &flashCfg_Xtx_Q80B_F16B, + }, + { + .jedecID = 0x16400B, + //.name="XT_25F32B_32_33", + .cfg = &flashCfg_Xtx, + }, + { + .jedecID = 0x14600B, + //.name="XT_25Q80B_08_18", + .cfg = &flashCfg_Xtx_Q80B_F16B, + }, + { + .jedecID = 0x16600B, + //.name="XT_25Q32B_32_18", + .cfg = &flashCfg_Xtx, + }, + { + .jedecID = 0x146085, + //.name="Puya_Q80L/H_08_18/33", + .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, + }, + { + .jedecID = 0x156085, + //.name="Puya_Q16H_16_33", + .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, + }, + { + .jedecID = 0x166085, + //.name="Puya_Q32H_32_33", + .cfg = &flashCfg_Puya_Q32H, + }, + { + .jedecID = 0x154068, + //.name="Boya_Q16B_16_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x164068, + //.name="Boya_Q32B_32_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x174068, + //.name="Boya_Q64A_64_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x184068, + //.name="Boya_Q128A_128_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x14605E, + //.name="FT_VQ80", + .cfg = &flashCfg_FT_VQ80, + } +}; + +/*@} end of group SF_CFG_Private_Variables */ + +/** @defgroup SF_CFG_Global_Variables + * @{ + */ + +/*@} end of group SF_CFG_Global_Variables */ + +/** @defgroup SF_CFG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CFG_Private_Fun_Declaration */ + +/** @defgroup SF_CFG_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Init external flash GPIO according to flash GPIO config + * + * @param extFlashPin: Flash GPIO config + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + GLB_GPIO_Cfg_Type cfg; + uint8_t gpiopins[6]; + uint8_t i = 0; + + cfg.gpioMode = GPIO_MODE_AF; + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 1; + cfg.smtCtrl = 1; + cfg.gpioFun = GPIO_FUN_FLASH; + + if (extFlashPin == 0) { + gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; + } else { + gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; + } + + for (i = 0; i < sizeof(gpiopins); i++) { + cfg.gpioPin = gpiopins[i]; + + if (i == 0 || i == 1) { + /*flash clk and cs is output*/ + cfg.gpioMode = GPIO_MODE_OUTPUT; + } else { + /*data are bidir*/ + cfg.gpioMode = GPIO_MODE_AF; + } + + GLB_GPIO_Init(&cfg); + } +} + +/****************************************************************************/ /** + * @brief Init internal flash GPIO according to flash GPIO config + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = GPIO_FUN_SWGPIO, + .gpioMode = GPIO_MODE_INPUT, + .pullType = GPIO_PULL_NONE, + .drive = 0, + .smtCtrl = 1, + }; + + /* Turn on Flash pad, GPIO23 - GPIO28 */ + for (uint32_t pin = 23; pin < 29; pin++) { + gpioCfg.gpioPin = pin; + + if (pin == 24) { + gpioCfg.pullType = GPIO_PULL_DOWN; + } else { + gpioCfg.pullType = GPIO_PULL_NONE; + } + + GLB_GPIO_Init(&gpioCfg); + } +} + +/****************************************************************************/ /** + * @brief Deinit external flash GPIO according to flash GPIO config + * + * @param extFlashPin: Flash GPIO config + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + GLB_GPIO_Cfg_Type cfg; + uint8_t gpiopins[6]; + uint8_t i = 0; + + cfg.gpioMode = GPIO_MODE_INPUT; + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 1; + cfg.smtCtrl = 1; + cfg.gpioFun = GPIO_FUN_SWGPIO; + + if (extFlashPin == 0) { + gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; + + } else { + gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; + } + + for (i = 0; i < sizeof(gpiopins); i++) { + cfg.gpioPin = gpiopins[i]; + GLB_GPIO_Init(&cfg); + } +} + +/****************************************************************************/ /** + * @brief Restore GPIO17 function + * + * @param fun: GPIO17 function + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Cfg_Restore_GPIO17_Fun(uint8_t fun) +{ + GLB_GPIO_Cfg_Type cfg; + + cfg.gpioMode = GPIO_MODE_AF; + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 1; + cfg.smtCtrl = 1; + cfg.gpioPin = GLB_GPIO_PIN_17; + cfg.gpioFun = fun; + GLB_GPIO_Init(&cfg); +} + +/*@} end of group SF_CFG_Private_Functions */ + +/** @defgroup SF_CFG_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Get flash config according to flash ID + * + * @param flashID: Flash ID + * @param pFlashCfg: Flash config pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t i; + uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; + uint32_t crc, *pCrc; + + if (flashID == 0) { + XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL602_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); + + if (BL602_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { + crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); + pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); + + if (*pCrc == crc) { + BL602_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); + return SUCCESS; + } + } + } else { + for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { + if (flashInfos[i].jedecID == flashID) { + BL602_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + return SUCCESS; + } + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Init flash GPIO according to flash Pin config + * + * @param flashPinCfg: Specify flash Pin config + * @param restoreDefault: Wether to restore default setting + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) +{ + if (restoreDefault) { + /* Set Default first */ + SF_Ctrl_Select_Pad(SF_CTRL_EMBEDDED_SEL); + GLB_Select_Internal_Flash(); + GLB_Swap_Flash_Pin(); + //SF_Cfg_Deinit_Ext_Flash_Gpio(0); + SF_Cfg_Deinit_Ext_Flash_Gpio(1); + SF_Cfg_Init_Internal_Flash_Gpio(); + } + + if (flashPinCfg > 0) { + /*01: deswap flash PIN + 10: use ext flash 1(GPIO17-22) + 11: use ext flash 0(GPIO0-2, 20-22) + */ + if (flashPinCfg == BFLB_FLASH_CFG_DESWAP) { + SF_Ctrl_Select_Pad(SF_CTRL_EMBEDDED_SEL); + /*DONOT Swap flash PIN*/ + GLB_Deswap_Flash_Pin(); + } else { + SF_Ctrl_Select_Pad(flashPinCfg - 1); + GLB_Select_External_Flash(); + SF_Cfg_Init_Ext_Flash_Gpio(flashPinCfg - BFLB_FLASH_CFG_EXT0_17_22); + } + } +} + +/****************************************************************************/ /** + * @brief Identify one flash + * + * @param callFromFlash: code run at flash or ram + * @param autoScan: Auto scan all GPIO pin + * @param flashPinCfg: Specify flash GPIO config, not auto scan + * @param restoreDefault: Wether restore default flash GPIO config + * @param pFlashCfg: Flash config pointer + * + * @return Flash ID + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, + uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t jdecId = 0; + uint32_t i = 0; + uint32_t offset; + BL_Err_Type stat; + uint8_t gpio17_fun = 0; + + BL602_MemCpy_Fast(pFlashCfg, &flashCfg_Gd_Q80E_Q16E, sizeof(SPI_Flash_Cfg_Type)); + + if (callFromFlash == 1) { + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); + return 0; + } + } + + if (autoScan) { + flashPinCfg = 0; + + do { + if (flashPinCfg > BFLB_FLASH_CFG_EXT1_0_2_20_22) { + jdecId = 0; + break; + } + + if (flashPinCfg > BFLB_FLASH_CFG_EXT0_17_22) { + /*flashPinCfg=2 has make gpio17 into jtag,but not success*/ + SF_Cfg_Restore_GPIO17_Fun(gpio17_fun); + } + + /* select media gpio */ + if (flashPinCfg == BFLB_FLASH_CFG_EXT0_17_22) { + gpio17_fun = GLB_GPIO_Get_Fun(GLB_GPIO_PIN_17); + } + + SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); + SFlash_Reset_Continue_Read(pFlashCfg); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId = 0; + SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId = jdecId & 0xffffff; + flashPinCfg++; + } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00); + } else { + /* select media gpio */ + SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); + SFlash_Reset_Continue_Read(pFlashCfg); + SFlash_DisableBurstWrap(pFlashCfg); + SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId = jdecId & 0xffffff; + } + + for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { + if (flashInfos[i].jedecID == jdecId) { + BL602_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + break; + } + } + + if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { + if (callFromFlash == 1) { + XIP_SFlash_State_Restore(pFlashCfg, offset); + } + + return jdecId; + } else { + if (callFromFlash == 1) { + XIP_SFlash_State_Restore(pFlashCfg, offset); + } + + return (jdecId | BFLB_FLASH_ID_VALID_FLAG); + } +} +#endif + +/*@} end of group SF_CFG_Public_Functions */ + +/*@} end of group SF_CFG */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sf_cfg_ext.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sf_cfg_ext.c new file mode 100644 index 0000000000000000000000000000000000000000..4fb3a4838bfc3fb67bc0a5bce359edee8250cdc4 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sf_cfg_ext.c @@ -0,0 +1,773 @@ +/** + ****************************************************************************** + * @file bl602_sf_cfg_ext.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_glb.h" +#include "bl602_sf_cfg.h" +#include "bl602_sf_cfg_ext.h" +#include "bl602_xip_sflash.h" +#include "bl602_romdriver.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG_EXT + * @{ + */ + +/** @defgroup SF_CFG_EXT_Private_Macros + * @{ + */ +#define BFLB_FLASH_CFG_MAGIC "FCFG" + +/*@} end of group SF_CFG_EXT_Private_Macros */ + +/** @defgroup SF_CFG_EXT_Private_Types + * @{ + */ +typedef struct { + uint32_t jedecID; + char *name; + const SPI_Flash_Cfg_Type *cfg; +}Flash_Info_t; + +/*@} end of group SF_CFG_EXT_Private_Types */ + +/** @defgroup SF_CFG_EXT_Private_Variables + * @{ + */ +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_25Q08={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xc8, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0xa0, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x01, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=33000, + .pdDelay=20, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x51, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=0, + .cReadMode=0xA0, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=0x11, + .clkDelay=1, + .clkInvert=0x01, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=33000, + .pdDelay=20, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x20, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x31, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x01, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=400, + .timeE32k=1600, + .timeE64k=2000, + .timePagePgm=5, + .timeCe=33000, + .pdDelay=3, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xc2, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x00, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x00, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=0, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=0x11, + .clkDelay=1, + .clkInvert=0x01, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=33000, + .pdDelay=20, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_ZD_25Q16B={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xba, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0xa0, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=0x14, + .clkDelay=1, + .clkInvert=0x01, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=33000, + .pdDelay=20, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={ + { + .jedecID=0x1440A1, + //.name="FM_25Q08", + .cfg=&flashCfg_FM_25Q08, + }, + { + .jedecID=0x134051, + //.name="GD_MD04D_04_33", + .cfg=&flashCfg_Gd_Md_40D, + }, + { + .jedecID=0x144020, + //.name="XM_25QH80_80_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x154020, + //.name="XM_25QH16_16_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x164020, + //.name="XM_25QH32_32_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x174020, + //.name="XM_25QH64_64_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x1320C2, + //.name="MX_KH40_04_33", + .cfg=&flashCfg_MX_KH25, + }, + { + .jedecID=0x1420C2, + //.name="MX_KH80_08_33", + .cfg=&flashCfg_MX_KH25, + }, + { + .jedecID=0x1520C2, + //.name="MX_KH16_16_33", + .cfg=&flashCfg_MX_KH25, + }, + { + .jedecID=0x13325E, + //.name="ZB_D40B_80_33", + .cfg=&flashCfg_MX_KH25, + }, + { + .jedecID=0x14325E, + //.name="ZB_D80B_80_33", + .cfg=&flashCfg_MX_KH25, + }, + { + .jedecID=0x15405E, + //.name="ZB_25Q16B_15_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x16405E, + //.name="ZB_25Q32B_16_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x17405E, + //.name="ZB_25VQ64_64_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x15605E, + //.name="ZB_25VQ16_16_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x15345E, + //.name="ZB_25WQ16_16_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x1560EB, + //.name="TH_25Q16", + .cfg=&flashCfg_FM_25Q08, + }, + { + .jedecID=0x1740C8, + //.name="GD_25Q64E_64_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x176085, + //.name="Puya_P25Q64H_64_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x17400B, + //.name="XT_25F64B", + .cfg=&flashCfg_FM_25Q08, + }, + { + .jedecID=0x1560BA, + //.name="ZD_25Q16B", + .cfg=&flashCfg_ZD_25Q16B, + }, +}; + +/*@} end of group SF_CFG_EXT_Private_Variables */ + +/** @defgroup SF_CFG_EXT_Global_Variables + * @{ + */ + +/*@} end of group SF_CFG_EXT_Global_Variables */ + +/** @defgroup SF_CFG_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */ + +/** @defgroup SF_CFG_EXT_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Get flash config according to flash ID + * + * @param flashID: Flash ID + * @param pFlashCfg: Flash config pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg) +{ + uint32_t i; + uint8_t buf[sizeof(SPI_Flash_Cfg_Type)+8]; + uint32_t crc,*pCrc; + + if(flashID==0){ + XIP_SFlash_Read_Via_Cache_Need_Lock(8+BL602_FLASH_XIP_BASE,buf,sizeof(SPI_Flash_Cfg_Type)+8); + if(BL602_MemCmp(buf,BFLB_FLASH_CFG_MAGIC,4)==0){ + crc=BFLB_Soft_CRC32((uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type)); + pCrc=(uint32_t *)(buf+4+sizeof(SPI_Flash_Cfg_Type)); + if(*pCrc==crc){ + BL602_MemCpy_Fast(pFlashCfg,(uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type)); + return SUCCESS ; + } + } + }else{ + if(SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS){ + return SUCCESS; + } + for(i=0;iioMode&0xf,1,0,32); + } + if((ret&BFLB_FLASH_ID_VALID_FLAG)!=0){ + return ret; + } + + jdecId=(ret&0xffffff); + for(i=0;i
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Private_Macros + * @{ + */ + +/*@} end of group SF_CTRL_Private_Macros */ + +/** @defgroup SF_CTRL_Private_Types + * @{ + */ + +/*@} end of group SF_CTRL_Private_Types */ + +/** @defgroup SF_CTRL_Private_Variables + * @{ + */ +#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) +#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x100) + +/*@} end of group SF_CTRL_Private_Variables */ + +/** @defgroup SF_CTRL_Global_Variables + * @{ + */ + +/*@} end of group SF_CTRL_Global_Variables */ + +/** @defgroup SF_CTRL_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CTRL_Private_Fun_Declaration */ + +/** @defgroup SF_CTRL_Private_Functions + * @{ + */ + +/*@} end of group SF_CTRL_Private_Functions */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Enable serail flash controller + * + * @param cfg: serial flash controller config + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + if (cfg == NULL) { + return; + } + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + if (cfg->clkDelay > 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); + } + + /* Serail out inverted, so sf ctrl send on negative edge */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); + + /* Set do di and oe delay */ + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4, tmpVal); + + /* Enable AHB access sram buffer and enable sf interface */ + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); + + SF_Ctrl_Set_Owner(cfg->owner); +} + +/****************************************************************************/ /** + * @brief Flash pad select + * + * @param sel: pad type + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_PAD_SEL(sel)); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); +} + +/****************************************************************************/ /** + * @brief Set flash controller owner:I/D AHB or system AHB + * + * @param owner: owner type + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + /* Set owner */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner); + + /* Set iahb to flash interface */ + if (owner == SF_CTRL_OWNER_IAHB) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable flash controller + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable flash controller AES with big indian + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable flash controller AES with little indian + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief Serial flash controller set AES region + * + * @param region: region number + * @param enable: enable or not + * @param hwKey: hardware key or software key + * @param startAddr: region start address + * @param endAddr: region end address + * @param locked: lock this region or not + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, + uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); + uint32_t tmpVal; + + tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_CFG); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024); + /* sf_aes_end =1 means 1,11,1111,1111 */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked); + + BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_CFG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Serial flash controller set AES key + * + * @param region: region number + * @param key: key data pointer + * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); + uint32_t tmpVal, i = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); + + if (NULL != key) { + if (keyType == SF_CTRL_AES_128BITS) { + i = 4; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + } else if (keyType == SF_CTRL_AES_256BITS) { + i = 8; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + } else if (keyType == SF_CTRL_AES_192BITS) { + i = 6; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + } + + tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; + + while (i--) { + BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + tmpVal -= 4; + } + } +} + +/****************************************************************************/ /** + * @brief Serial flash controller set AES key with big endian + * + * @param region: region number + * @param key: key data pointer + * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); + uint32_t tmpVal, i = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); + + if (NULL != key) { + if (keyType == SF_CTRL_AES_128BITS) { + i = 4; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + */ + } else if (keyType == SF_CTRL_AES_256BITS) { + i = 8; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); + key+=4; + */ + } else if (keyType == SF_CTRL_AES_192BITS) { + i = 6; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); + */ + } + + tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; + + while (i--) { + BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); + key += 4; + tmpVal += 4; + } + } +} + +/****************************************************************************/ /** + * @brief Serial flash controller set AES iv + * + * @param region: region number + * @param iv: iv data pointer + * @param addrOffset: flash address offset + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); + uint32_t tmpVal, i = 3; + + if (iv != NULL) { + tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET; + + while (i--) { + BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + tmpVal -= 4; + } + + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + */ + BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); + iv += 4; + } +} + +/****************************************************************************/ /** + * @brief Serial flash controller set AES iv with big endian + * + * @param region: region number + * @param iv: iv data pointer + * @param addrOffset: flash address offset + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); + uint32_t tmpVal, i = 3; + + if (iv != NULL) { + tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET; + + while (i--) { + BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + tmpVal += 4; + } + + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + */ + BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); + iv += 4; + } +} + +/****************************************************************************/ /** + * @brief Enable serial flash controller AES + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable serial flash controller AES + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); +} + +/****************************************************************************/ /** + * @brief Set flash image offset + * + * @param addrOffset: Address offset value + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) +{ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); +} + +/****************************************************************************/ /** + * @brief Get flash image offset + * + * @param None + * + * @return :Address offset value + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) +{ + return BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); +} + +/****************************************************************************/ /** + * @brief SF controller send one command + * + * @param sahbType: Serial flash controller clock sahb sram select + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + if (sahbType == SF_CTRL_SAHB_CLOCK) { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL); + } else if (sahbType == SF_CTRL_FLASH_CLOCK) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief SF controller send one command + * + * @param cfg: Serial flash controller command configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) { + return; + } + + /* Clear trigger */ + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_1, cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_2, cfg->cmdBuf[1]); + + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE); + } + + if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { + if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_NIO_MODE); + } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DO_MODE); + } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QO_MODE); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DIO_MODE); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QIO_MODE); + } + + /* Configure cmd */ + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_CMD_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_CMD_BYTE, 0); + + /* Configure address */ + if (cfg->addrSize != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, cfg->addrSize - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, 0); + } + + /* Configure dummy */ + if (cfg->dummyClks != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, cfg->dummyClks - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, 0); + } + + /* Configure data */ + if (cfg->nbData != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, cfg->nbData - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, 0); + } + + /* Set read write flag */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_RW, cfg->rwFlag); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); + + //switch sf_clk_sahb_sram_sel = 1 + SF_Ctrl_Select_Clock(SF_CTRL_FLASH_CLOCK); + /* Trigger */ + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); + return; + } + } + + //switch sf_clk_sahb_sram_sel = 0 + SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); +} + +/****************************************************************************/ /** + * @brief Config SF controller for I/D cache read + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmdValid: command valid or not, for continous read, cache may need no command + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { + return; + } + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0); + + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); + } + + if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { + if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); + } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); + } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); + } + + if (cmdValid) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); + } + + /* Configure address */ + if (cfg->addrSize != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); + } + + /* configure dummy */ + if (cfg->dummyClks != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); + } + + /* Configure data */ + if (cfg->nbData != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); + } + + /* Set read write flag */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief Config SF controller for I/D cache write + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmdValid: command valid or not, cache may need no command + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { + return; + } + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_4, cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_5, cfg->cmdBuf[1]); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3); + + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_SPI_MODE); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_QPI_MODE); + } + + if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { + if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_NIO_MODE); + } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DO_MODE); + } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QO_MODE); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DIO_MODE); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QIO_MODE); + } + + if (cmdValid) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0); + } + + /* Configure address */ + if (cfg->addrSize != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, cfg->addrSize - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, 0); + } + + /* configure dummy */ + if (cfg->dummyClks != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, cfg->dummyClks - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, 0); + } + + /* Configure data */ + if (cfg->nbData != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 0); + } + + /* Set read write flag */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_RW, cfg->rwFlag); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3, tmpVal); +} + +/****************************************************************************/ /** + * @brief Get SF Ctrl busy state + * + * @param None + * + * @return SET for SF ctrl busy or RESET for SF ctrl not busy + * +*******************************************************************************/ +__WEAK +BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0); + + if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_BUSY)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Check is serial flash controller AES enable + * + * @param None + * + * @return Wether AES is enable + * +*******************************************************************************/ +__WEAK +uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + return BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN); +} + +/****************************************************************************/ /** + * @brief Get flash controller clock delay value + * + * @param None + * + * @return Clock delay value + * +*******************************************************************************/ +__WEAK +uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) { + return 0; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; + } +} + +/****************************************************************************/ /** + * @brief Set flash controller clock delay value + * + * @param delay: Clock delay value + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + if (delay > 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief SF Controller interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void SF_Ctrl_IRQHandler(void) +{ + /* TODO: Not implemented */ +} +#endif + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sflash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sflash.c new file mode 100644 index 0000000000000000000000000000000000000000..d07844178310d9e80d34f1b90a0f2b77f19e1903 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sflash.c @@ -0,0 +1,1549 @@ +/** + ****************************************************************************** + * @file bl602_sflash.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" +#include "bl602_l1c.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLASH + * @{ + */ + +/** @defgroup SFLASH_Private_Macros + * @{ + */ + +/*@} end of group SFLASH_Private_Macros */ + +/** @defgroup SFLASH_Private_Types + * @{ + */ + +/*@} end of group SFLASH_Private_Types */ + +/** @defgroup SFLASH_Private_Variables + * @{ + */ +#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) + +/*@} end of group SFLASH_Private_Variables */ + +/** @defgroup SFLASH_Global_Variables + * @{ + */ + +/*@} end of group SFLASH_Global_Variables */ + +/** @defgroup SFLASH_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SFLASH_Private_Fun_Declaration */ + +/** @defgroup SFLASH_Private_Functions + * @{ + */ + +/*@} end of group SFLASH_Private_Functions */ + +/** @defgroup SFLASH_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Init serial flash control interface + * + * @param pSfCtrlCfg: Serial flash controller configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) +{ + SF_Ctrl_Enable(pSfCtrlCfg); +} + +/****************************************************************************/ /** + * @brief Set serial flash control interface SPI or QPI mode + * + * @param mode: Serial flash interface mode + * + * @return BFLB_RET:SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) +{ + BL_Err_Type stat = SUCCESS; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); + + return stat; +} + +/****************************************************************************/ /** + * @brief Read flash register + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param regIndex: register index + * @param regValue: register value pointer to store data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24; + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + BL602_Delay_US(1); + cnt++; + + if (cnt > 1000) { + return ERROR; + } + } + + BL602_MemCpy(regValue, flashCtrlBuf, regLen); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Write flash register + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param regIndex: register index + * @param regValue: register value pointer storing data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + BL602_MemCpy(flashCtrlBuf, regValue, regLen); + + flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24; + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* take 40ms for tw(write status register) as default */ + while (SET == SFlash_Busy(flashCfg)) { + BL602_Delay_US(100); + cnt++; + + if (cnt > 400) { + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Check flash busy status + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SET for busy or RESET for not busy + * +*******************************************************************************/ +__WEAK +BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat = 0; + SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen); + + if ((stat & (1 << flashCfg->busyBit)) == 0) { + return RESET; + } + + return SET; +} + +/****************************************************************************/ /** + * @brief Enable flash write function + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + /* Write enable*/ + flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24; + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + SF_Ctrl_SendCmd(&flashCmd); + + SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen); + + if ((stat & (1 << flashCfg->wrEnableBit)) != 0) { + return SUCCESS; + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Enable flash flash controller QSPI interface + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat = 0, ret; + + if (flashCfg->qeReadRegLen == 0) { + ret = SFlash_Write_Enable(flashCfg); + + if (SUCCESS != ret) { + return ERROR; + } + + SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); + return SUCCESS; + } + + SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); + + if (flashCfg->qeData == 0) { + if ((stat & (1 << flashCfg->qeBit)) != 0) { + return SUCCESS; + } + } else { + if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { + return SUCCESS; + } + } + + if (flashCfg->qeWriteRegLen != 1) { + /* This is read r0,read r1 write r0,r1 case*/ + SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); + SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); + + if (flashCfg->qeData == 0) { + stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)); + } else { + stat = stat & (~(0xff << (8 * flashCfg->qeIndex))); + stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex)); + } + } else { + if (flashCfg->qeData == 0) { + stat |= (1 << (flashCfg->qeBit % 8)); + } else { + stat = flashCfg->qeData; + } + } + + ret = SFlash_Write_Enable(flashCfg); + + if (SUCCESS != ret) { + return ERROR; + } + + SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); + SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); + + if (flashCfg->qeData == 0) { + if ((stat & (1 << flashCfg->qeBit)) != 0) { + return SUCCESS; + } + } else { + if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Enable flash volatile register write enable + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24; + flashCmd.rwFlag = SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); +} + +/****************************************************************************/ /** + * @brief Erase flash whole chip + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24; + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(flashCfg)) { + BL602_Delay_US(500); + cnt++; + + if (cnt > flashCfg->timeCe * 3) { + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Erase flash one sector + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param secNum: flash sector number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) +{ + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(flashCfg)) { + BL602_Delay_US(500); + cnt++; + + if (cnt > flashCfg->timeEsector * 3) { + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Erase flash one 32K block + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param blkNum: flash 32K block number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(flashCfg)) { + BL602_Delay_US(500); + cnt++; + + if (cnt > flashCfg->timeE32k * 3) { + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Erase flash one 64K block + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param blkNum: flash 64K block number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(flashCfg)) { + BL602_Delay_US(500); + cnt++; + + if (cnt > flashCfg->timeE64k * 3) { + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Erase flash one region + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param startaddr: start address to erase + * @param endaddr: end address(include this address) to erase + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) +{ + uint32_t len = 0; + uint32_t eraseLen = 0; + BL_Err_Type ret = SUCCESS; + + while (startaddr <= endaddr) { + len = endaddr - startaddr + 1; + + if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && + (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && + len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { + /* 64K margin address,and length > 64K-sector size, erase one first */ + ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); + eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; + } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && + (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && + len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { + /* 32K margin address,and length > 32K-sector size, erase one first */ + ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); + eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; + } else { + /* Sector erase */ + startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); + ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); + eraseLen = flashCfg->sectorSize * 1024; + } + + startaddr += eraseLen; + + if (ret != SUCCESS) { + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Program flash one region + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: progran mode:SPI mode or QPI mode + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t i = 0, curLen = 0; + uint32_t cnt = 0; + BL_Err_Type stat; + uint8_t cmd; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { + cmd = flashCfg->pageProgramCmd; + } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) { + flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->qpageProgramCmd; + } else { + return ERROR; + } + + /* Prepare command */ + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.addrSize = 3; + + for (i = 0; i < len;) { + /* Write enable is needed for every program */ + stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + /* Get current programmed length within page size */ + curLen = flashCfg->pageSize - addr % flashCfg->pageSize; + + if (curLen > len - i) { + curLen = len - i; + } + + /* Prepare command */ + BL602_MemCpy_Fast(flashCtrlBuf, data, curLen); + flashCmd.cmdBuf[0] = (cmd << 24) | (addr); + flashCmd.nbData = curLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* Adjust address and programmed length */ + addr += curLen; + i += curLen; + data += curLen; + + /* Wait for write done */ + cnt = 0; + + while (SET == SFlash_Busy(flashCfg)) { + BL602_Delay_US(100); + cnt++; + + if (cnt > flashCfg->timePagePgm * 20) { + return ERROR; + } + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get flash unique ID + * + * @param data: data pointer to store read data + * @param idLen: unique ID len + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + dummyClks = 4; + cmd = 0x4B; + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = idLen; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + BL602_MemCpy(data, flashCtrlBuf, idLen); +} + +/****************************************************************************/ /** + * @brief Get flash jedec ID + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param data: data pointer to store read data + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + dummyClks = flashCfg->jedecIdCmdDmyClk; + cmd = flashCfg->jedecIdCmd; + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + BL602_MemCpy(data, flashCtrlBuf, 3); +} + +/****************************************************************************/ /** + * @brief Get flash device ID + * + * @param data: data pointer to store read data + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t addr = 0x00000001; + uint8_t readMode = 0xFF; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + dummyClks = 2; + cmd = 0x94; + flashCmd.cmdBuf[0] = (cmd << 24) | (addr); + flashCmd.cmdBuf[1] = (readMode << 24); + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 4; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = 2; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + BL602_MemCpy(data, flashCtrlBuf, 2); +} + +/****************************************************************************/ /** + * @brief Set flash power down + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Powerdown(void) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t cmd = 0; + uint32_t timeOut = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + cmd = 0xB9; + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } +} + +/****************************************************************************/ /** + * @brief Release flash power down for wake up + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t cmd; + uint32_t timeOut = 0; + + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + cmd = flashCfg->releasePowerDown; + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } +} + +/****************************************************************************/ /** + * @brief Set flash burst wrap config + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t wrapData; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((flashCfg->ioMode >> 4) & 0x01) == 1) { + /* Disable burst wrap ,just return */ + return; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; + flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; + dummyClks = flashCfg->burstWrapCmdDmyClk; + cmd = flashCfg->burstWrapCmd; + wrapData = flashCfg->burstWrapData; + BL602_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = 1; + + SF_Ctrl_SendCmd(&flashCmd); +} + +/****************************************************************************/ /** + * @brief Disable flash burst wrap config + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t wrapData; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; + flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; + dummyClks = flashCfg->deBurstWrapCmdDmyClk; + cmd = flashCfg->deBurstWrapCmd; + wrapData = flashCfg->deBurstWrapData; + BL602_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = 1; + + SF_Ctrl_SendCmd(&flashCmd); +} + +/****************************************************************************/ /** + * @brief Software reset flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) +{ + uint16_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + /* Reset enable */ + flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24; + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + + /* Wait for write done */ + while (SET == SFlash_Busy(flashCfg)) { + BL602_Delay_US(100); + cnt++; + + if (cnt > 20) { + return ERROR; + } + } + + SF_Ctrl_SendCmd(&flashCmd); + + /* Reset */ + flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24; + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + SF_Ctrl_SendCmd(&flashCmd); + + BL602_Delay_US(50); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Reset flash continous read mode + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + /* Reset continous read */ + BL602_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = flashCfg->resetCreadCmdSize; + SF_Ctrl_SendCmd(&flashCmd); +} + +/****************************************************************************/ /** + * @brief Set I/D bus read flash configuration in flash controller + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param addr: address to read/write + * @param len: data length to read/write + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) +{ + uint8_t cmd, dummyClks; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t cmdValid = 1; + uint8_t noReadModeCfg = 0; + uint8_t cReadSupport = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); + + if (SF_CTRL_NIO_MODE == ioMode) { + cmd = flashCfg->fastReadCmd; + dummyClks = flashCfg->frDmyClk; + } else if (SF_CTRL_DO_MODE == ioMode) { + flashCmd.dataMode = SF_CTRL_DATA_2_LINES; + cmd = flashCfg->fastReadDoCmd; + dummyClks = flashCfg->frDoDmyClk; + } else if (SF_CTRL_DIO_MODE == ioMode) { + flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; + flashCmd.dataMode = SF_CTRL_DATA_2_LINES; + cmd = flashCfg->fastReadDioCmd; + dummyClks = flashCfg->frDioDmyClk; + } else if (SF_CTRL_QO_MODE == ioMode) { + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->fastReadQoCmd; + dummyClks = flashCfg->frQoDmyClk; + } else if (SF_CTRL_QIO_MODE == ioMode) { + flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->fastReadQioCmd; + dummyClks = flashCfg->frQioDmyClk; + } else { + return ERROR; + } + + /*prepare command**/ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + flashCmd.cmdBuf[0] = (cmd << 24) | addr; + + if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { + noReadModeCfg = flashCfg->cReadSupport & 0x02; + cReadSupport = flashCfg->cReadSupport & 0x01; + + if (noReadModeCfg == 0) { + /* Read mode must be set*/ + if (cReadSupport == 0) { + /* Not support cont read,but we still need set read mode(winbond 80dv)*/ + flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); + } else { + /* Flash support cont read, setting depend on user parameter */ + if (contRead) { + flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode; + cmdValid = 0; + } else { + flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); + } + } + + flashCmd.addrSize++; + } + } + + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = len; + SF_Ctrl_Icache_Set(&flashCmd, cmdValid); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable I/D bus read from flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) +{ + BL_Err_Type stat; + + stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 4); + + if (SUCCESS != stat) { + return stat; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable cache + * + * @param wayDisable: cache way disable config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable) +{ + uint32_t tmpVal; + uint32_t cnt = 0; + + /* Set cacheable to 0 */ + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + /*Set Tag RAM to zero */ + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_INVALID_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_INVALID_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Polling for invalid done */ + do { + BL602_Delay_US(1); + cnt++; + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100); + + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal |= (wayDisable << L1C_WAY_DIS_POS); + + /* If way disable is 0x0f, cacheable can't be set */ + if (wayDisable != 0x0f) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Flush cache + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Flush(void) +{ + uint32_t tmpVal; + + /* Disable early respone */ + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + SFlash_Cache_Enable_Set((tmpVal >> L1C_WAY_DIS_POS) & 0xf); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable cache read from flash with cache + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param wayDisable: cache way disable config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) +{ + BL_Err_Type stat; + + /* Cache now only support 32 bytes read */ + stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32); + + if (SUCCESS != stat) { + return stat; + } + + return SFlash_Cache_Enable_Set(wayDisable); +} + +/****************************************************************************/ /** + * @brief Get cache hit count + * + * @param hitCountLow: hit count low 32 bits pointer + * @param hitCountHigh: hit count high 32 bits pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) +{ + *hitCountLow = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_LSB); + *hitCountHigh = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_MSB); +} + +/****************************************************************************/ /** + * @brief Get cache miss count + * + * @param None + * + * @return Cache miss count + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION SFlash_Cache_Miss_Count_Get(void) +{ + return BL_RD_REG(L1C_BASE, L1C_MISS_CNT); +} + +/****************************************************************************/ /** + * @brief Disable read from flash with cache + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Read data from flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return None + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t curLen, i; + uint8_t cmd, dummyClks; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t noReadModeCfg = 0; + uint8_t cReadSupport = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + if (SF_CTRL_NIO_MODE == ioMode) { + cmd = flashCfg->fastReadCmd; + dummyClks = flashCfg->frDmyClk; + } else if (SF_CTRL_DO_MODE == ioMode) { + flashCmd.dataMode = SF_CTRL_DATA_2_LINES; + cmd = flashCfg->fastReadDoCmd; + dummyClks = flashCfg->frDoDmyClk; + } else if (SF_CTRL_DIO_MODE == ioMode) { + flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; + flashCmd.dataMode = SF_CTRL_DATA_2_LINES; + cmd = flashCfg->fastReadDioCmd; + dummyClks = flashCfg->frDioDmyClk; + } else if (SF_CTRL_QO_MODE == ioMode) { + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->fastReadQoCmd; + dummyClks = flashCfg->frQoDmyClk; + } else if (SF_CTRL_QIO_MODE == ioMode) { + flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->fastReadQioCmd; + dummyClks = flashCfg->frQioDmyClk; + } else { + return ERROR; + } + + /* Prepare command */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { + noReadModeCfg = flashCfg->cReadSupport & 0x02; + cReadSupport = flashCfg->cReadSupport & 0x01; + + if (noReadModeCfg == 0) { + /* Read mode must be set*/ + if (cReadSupport == 0) { + /* Not support cont read,but we still need set read mode(winbond 80dv)*/ + flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); + } else { + /* Flash support cont read, setting depend on user parameter */ + if (contRead) { + flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); + } else { + flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); + } + } + + flashCmd.addrSize++; + } + } + + flashCmd.dummyClks = dummyClks; + + /* Read data */ + for (i = 0; i < len;) { + /* Prepare command */ + flashCmd.cmdBuf[0] = (cmd << 24) | (addr); + curLen = len - i; + + if (curLen >= FLASH_CTRL_BUF_SIZE) { + curLen = FLASH_CTRL_BUF_SIZE; + flashCmd.nbData = curLen; + } else { + /* Make sf_ctrl word read */ + flashCmd.nbData = ((curLen + 3) >> 2) << 2; + } + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + + BL602_MemCpy_Fast(data, flashCtrlBuf, curLen); + + addr += curLen; + i += curLen; + data += curLen; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read flash register with read command + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param readRegCmd: read command + * @param regValue: register value pointer to store data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = readRegCmd << 24; + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + BL602_Delay_US(1); + cnt++; + + if (cnt > 1000) { + return ERROR; + } + } + + BL602_MemCpy(regValue, flashCtrlBuf, regLen); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Write flash register with write command + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param writeRegCmd: write command + * @param regValue: register value pointer storing data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + BL602_MemCpy(flashCtrlBuf, regValue, regLen); + + flashCmd.cmdBuf[0] = writeRegCmd << 24; + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* take 40ms for tw(write status register) as default */ + while (SET == SFlash_Busy(flashCfg)) { + BL602_Delay_US(100); + cnt++; + + if (cnt > 400) { + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/*@} end of group SFLASH_Public_Functions */ + +/*@} end of group SFLASH */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sflash_ext.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sflash_ext.c new file mode 100644 index 0000000000000000000000000000000000000000..c2ee65144de0eee1b5671e95de9539574503c1de --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_sflash_ext.c @@ -0,0 +1,550 @@ +/** + ****************************************************************************** + * @file bl602_sflash_ext.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_l1c.h" +#include "bl602_sflash_ext.h" +#include "bl602_sf_ctrl.h" +#include "l1c_reg.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLASH_EXT + * @{ + */ + +/** @defgroup SFLASH_EXT_Private_Macros + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Macros */ + +/** @defgroup SFLASH_EXT_Private_Types + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Types */ + +/** @defgroup SFLASH_EXT_Private_Variables + * @{ + */ +#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) + +/*@} end of group SFLASH_EXT_Private_Variables */ + +/** @defgroup SFLASH_EXT_Global_Variables + * @{ + */ + +/*@} end of group SFLASH_EXT_Global_Variables */ + +/** @defgroup SFLASH_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Fun_Declaration */ + +/** @defgroup SFLASH_EXT_Private_Functions + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Functions */ + +/** @defgroup SFLASH_EXT_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Sflash restore from power down + * + * @param pFlashCfg: Flash configuration pointer + * @param flashContRead: Whether enable continuous read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) +{ + BL_Err_Type stat = SUCCESS; + uint32_t jdecId = 0; + uint8_t tmp[8]; + uint8_t ioMode = pFlashCfg->ioMode & 0xf; + + /* Wake flash up from power down */ + SFlash_Releae_Powerdown(pFlashCfg); + BL602_Delay_US(120); + + SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); + + if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) { + SFlash_Qspi_Enable(pFlashCfg); + } + + if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) { + /* unwrap */ + L1C_Set_Wrap(DISABLE); + } else { + /* burst wrap */ + L1C_Set_Wrap(ENABLE); + /* For command that is setting register instead of send command, we need write enable */ + SFlash_Write_Enable(pFlashCfg); + SFlash_SetBurstWrap(pFlashCfg); + } + + if (flashContRead) { + stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); + stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + } else { + stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32); + } + + return stat; +} + +/****************************************************************************/ /** + * @brief Sflash enable RCV mode to recovery for erase while power drop + * + * @param pFlashCfg: Flash configuration pointer + * @param rCmd: Read RCV register cmd + * @param wCmd: Write RCV register cmd + * @param bitPos: RCV register bit pos + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) +{ + BL_Err_Type stat; + uint32_t cnt = 0; + uint32_t tempVal = 0; + + while (SET == SFlash_Busy(pFlashCfg)) { + BL602_Delay_US(500); + cnt++; + + if (cnt > 20000 * 3) { + return ERROR; + } + } + + stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); + + if (SUCCESS != stat) { + stat = ERROR; + } + + if (((tempVal >> bitPos) & 0x01) > 0) { + return SUCCESS; + } + + tempVal |= (uint32_t)(1 << bitPos); + stat = SFlash_Write_Enable(pFlashCfg); + + if (SUCCESS != stat) { + stat = ERROR; + } + + stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1); + + if (SUCCESS != stat) { + return stat; + } + + while (SET == SFlash_Busy(pFlashCfg)) { + BL602_Delay_US(500); + cnt++; + + if (cnt > 20000 * 3) { + return ERROR; + } + } + + stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); + + if (SUCCESS != stat) { + stat = ERROR; + } + + if (((tempVal >> bitPos) & 0x01) <= 0) { + return ERROR; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Erase flash security register one block + * + * @param pFlashCfg: Flash configuration pointer + * @param pSecRegCfg: Security register configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) +{ + uint32_t cnt = 0; + uint8_t cmd = 0; + uint8_t secOptMode = 0; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (pSecRegCfg->enterSecOptCmd != 0x00) { + secOptMode = 1; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + } + + BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + cmd = pSecRegCfg->eraseCmd; + flashCmd.cmdBuf[0] = (cmd << 24) | (pSecRegCfg->blockNum << 12); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(pFlashCfg)) { + BL602_Delay_US(500); + cnt++; + + if (cnt > pFlashCfg->timeEsector * 3) { + return ERROR; + } + } + + if (secOptMode > 0) { + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Program flash security register one block + * + * @param pFlashCfg: Flash configuration pointer + * @param pSecRegCfg: Security register configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t i = 0, curLen = 0; + uint32_t cnt = 0; + BL_Err_Type stat; + uint8_t cmd; + uint8_t secOptMode = 0; + uint8_t *data = pSecRegCfg->data; + uint32_t addr = pSecRegCfg->addr; + uint32_t len = pSecRegCfg->len; + uint32_t currentAddr = 0; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (pSecRegCfg->enterSecOptCmd != 0x00) { + secOptMode = 1; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + /* Prepare command */ + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.addrSize = 3; + cmd = pSecRegCfg->programCmd; + + for (i = 0; i < len;) { + /* Write enable is needed for every program */ + stat = SFlash_Write_Enable(pFlashCfg); + + if (stat != SUCCESS) { + return stat; + } + + /* Get current programmed length within page size */ + curLen = 256 - addr % 256; + + if (curLen > len - i) { + curLen = len - i; + } + + currentAddr = (pSecRegCfg->blockNum << 12) | addr; + + /* Prepare command */ + BL602_MemCpy_Fast(flashCtrlBuf, data, curLen); + flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); + flashCmd.nbData = curLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* Adjust address and programmed length */ + addr += curLen; + i += curLen; + data += curLen; + + /* Wait for write done */ + cnt = 0; + + while (SET == SFlash_Busy(pFlashCfg)) { + BL602_Delay_US(100); + cnt++; + + if (cnt > pFlashCfg->timePagePgm * 20) { + return ERROR; + } + } + } + + if (secOptMode > 0) { + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read data from flash security register one block + * + * @param pSecRegCfg: Security register configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t curLen, i; + uint8_t cmd; + uint8_t secOptMode = 0; + uint8_t *data = pSecRegCfg->data; + uint32_t addr = pSecRegCfg->addr; + uint32_t len = pSecRegCfg->len; + uint32_t currentAddr = 0; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (pSecRegCfg->enterSecOptCmd != 0x00) { + secOptMode = 1; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + /* Prepare command */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + flashCmd.dummyClks = 1; + cmd = pSecRegCfg->readCmd; + + /* Read data */ + for (i = 0; i < len;) { + currentAddr = (pSecRegCfg->blockNum << 12) | addr; + /* Prepare command */ + flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); + curLen = len - i; + + if (curLen >= FLASH_CTRL_BUF_SIZE) { + curLen = FLASH_CTRL_BUF_SIZE; + flashCmd.nbData = curLen; + } else { + /* Make sf_ctrl word read */ + flashCmd.nbData = ((curLen + 3) >> 2) << 2; + } + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + + BL602_MemCpy_Fast(data, flashCtrlBuf, curLen); + + addr += curLen; + i += curLen; + data += curLen; + } + + if (secOptMode > 0) { + if (((uint32_t)&flashCmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/*@} end of group SFLASH_EXT_Public_Functions */ + +/*@} end of group SFLASH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_spi.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..ae1f2a7c3a61d3c6ce480d5d930453b89ac83d39 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_spi.c @@ -0,0 +1,1803 @@ +/** + ****************************************************************************** + * @file bl602_spi.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_spi.h" +#include "bl602_glb.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ +#define SPI_TX_TIMEOUT_COUNT (160 * 1000) +#define SPI_RX_TIMEOUT_COUNT (160 * 1000) + +/*@} end of group SPI_Private_Macros */ + +/** @defgroup SPI_Private_Types + * @{ + */ + +/*@} end of group SPI_Private_Types */ + +/** @defgroup SPI_Private_Variables + * @{ + */ +static const uint32_t spiAddr[SPI_ID_MAX] = { SPI_BASE }; +static intCallback_Type *spiIntCbfArra[SPI_ID_MAX][SPI_INT_ALL] = { + { NULL } +}; + +/*@} end of group SPI_Private_Variables */ + +/** @defgroup SPI_Global_Variables + * @{ + */ + +/*@} end of group SPI_Global_Variables */ + +/** @defgroup SPI_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void SPI_IntHandler(SPI_ID_Type spiNo); +#endif + +/*@} end of group SPI_Private_Fun_Declaration */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief SPI interrupt common handler function + * + * @param spiNo: SPI ID type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static void SPI_IntHandler(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + /* Transfer end interrupt,shared by both master and slave mode */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR)); + + if (spiIntCbfArra[spiNo][SPI_INT_END] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_END](); + } + } + + /* TX fifo ready interrupt(fifo count > fifo threshold) */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) { + if (spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ](); + } + } + + /* RX fifo ready interrupt(fifo count > fifo threshold) */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) { + if (spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ](); + } + } + + /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR)); + + if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT](); + } + } + + /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR)); + + if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN](); + } + } + + /* TX/RX fifo overflow/underflow interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) { + if (spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR](); + } + } +} +#endif + +/*@} end of group SPI_Private_Functions */ + +/** @defgroup SPI_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief SPI initialization function + * + * @param spiNo: SPI ID type + * @param spiCfg: SPI configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod)); + CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence)); + CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence)); + CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv)); + CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity)); + + /* spi config */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_EN, spiCfg->deglitchEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_M_CONT_EN, spiCfg->continuousEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BYTE_INV, spiCfg->byteSequence); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BIT_INV, spiCfg->bitSequence); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_PH, (spiCfg->clkPhaseInv + 1) & 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_POL, spiCfg->clkPolarity); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, spiCfg->frameSize); + BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SPI_IRQn, SPI_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI set default value of all registers function + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo) +{ + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + if (SPI_ID_0 == spiNo) { + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SPI); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Length of data phase1/0,start/stop condition and interval between frame initialization + * function + * + * @param spiNo: SPI ID type + * @param clockCfg: Clock configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Configure length of data phase1/0 and start/stop condition */ + tmpVal = BL_RD_REG(SPIx, SPI_PRD_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, clockCfg->startLen - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, clockCfg->stopLen - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, clockCfg->dataPhase0Len - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, clockCfg->dataPhase1Len - 1); + BL_WR_REG(SPIx, SPI_PRD_0, tmpVal); + + /* Configure length of interval between frame */ + tmpVal = BL_RD_REG(SPIx, SPI_PRD_1); + BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, clockCfg->intervalLen - 1)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set SPI SCK Clcok + * + * @param spiNo: SPI ID type + * @param clk: Clk + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk) +{ + uint32_t glb_div = 1, spi_div = 1; + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + if (clk < 4882) { + clk = 4882; + } + + if (clk > 40000000) { + clk = 40000000; + } + + if (clk > 156250) { + glb_div = 1; + spi_div = 40000000 / clk; + } else { + spi_div = 256; + glb_div = clk >> 8; + } + + /* Configure length of data phase1/0 and start/stop condition */ + tmpVal = BL_RD_REG(SPIx, SPI_PRD_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, spi_div - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, spi_div - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, spi_div - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, spi_div - 1); + BL_WR_REG(SPIx, SPI_PRD_0, tmpVal); + + tmpVal = BL_RD_REG(SPIx, SPI_PRD_1); + BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, spi_div - 1)); + + GLB_Set_SPI_CLK(ENABLE, glb_div - 1); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI configure fifo function + * + * @param spiNo: SPI ID type + * @param fifoCfg: FIFO configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set fifo threshold value */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold - 1); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal); + + /* Enable or disable dma function */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_TX_EN, fifoCfg->txFifoDmaEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_RX_EN, fifoCfg->rxFifoDmaEnable); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable spi transfer + * + * @param spiNo: SPI ID type + * @param modeType: Master or slave mode select + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); + + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + + if (modeType != SPI_WORK_MODE_SLAVE) { + /* master mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); + } else { + /* slave mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); + } + + BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable spi transfer + * + * @param spiNo: SPI ID type + * @param modeType: Master or slave mode select + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); + + /* close master and slave */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); + BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set time-out value to trigger interrupt when spi bus is idle for the given value + * + * @param spiNo: SPI ID type + * @param value: Time value + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set time-out value */ + tmpVal = BL_RD_REG(SPIx, SPI_STO_VALUE); + BL_WR_REG(SPIx, SPI_STO_VALUE, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_STO_VALUE, value - 1)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set de-glitch function cycle count value + * + * @param spiNo: SPI ID type + * @param cnt: De-glitch function cycle count + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set count value */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt); + BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable rx data ignore function and set start/stop point + * + * @param spiNo: SPI ID type + * @param startPoint: Start point + * @param stopPoint: Stop point + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Enable rx ignore function */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Set start and stop point */ + tmpVal = startPoint << SPI_CR_SPI_RXD_IGNR_S_POS | stopPoint; + BL_WR_REG(SPIx, SPI_RXD_IGNR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable rx data ignore function + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Disable rx ignore function */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear tx fifo and tx fifo overflow/underflow status + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Clear tx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear rx fifo and rx fifo overflow/underflow status + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Clear rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear spi interrupt status + * + * @param spiNo: SPI ID type + * @param intType: SPI interrupt type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Clear certain or all interrupt */ + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + if (SPI_INT_ALL == intType) { + tmpVal |= 0x1f << SPI_CR_SPI_END_CLR_POS; + } else { + tmpVal |= 1 << (intType + SPI_CR_SPI_END_CLR_POS); + } + + BL_WR_REG(SPIx, SPI_INT_STS, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI mask or unmask certain or all interrupt + * + * @param spiNo: SPI ID type + * @param intType: SPI interrupt type + * @param intMask: SPI interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + /* Mask or unmask certain or all interrupt */ + if (SPI_INT_ALL == intType) { + if (MASK == intMask) { + tmpVal |= 0x3f << SPI_CR_SPI_END_MASK_POS; + } else { + tmpVal &= ~(0x3f << SPI_CR_SPI_END_MASK_POS); + } + } else { + if (MASK == intMask) { + tmpVal |= 1 << (intType + SPI_CR_SPI_END_MASK_POS); + } else { + tmpVal &= ~(1 << (intType + SPI_CR_SPI_END_MASK_POS)); + } + } + + /* Write back */ + BL_WR_REG(SPIx, SPI_INT_STS, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Install spi interrupt callback function + * + * @param spiNo: SPI ID type + * @param intType: SPI interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_INT_TYPE(intType)); + + spiIntCbfArra[spiNo][intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI write data to tx fifo + * + * @param spiNo: SPI ID type + * @param data: Data to write + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, uint32_t data) +{ + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Write tx fifo */ + BL_WR_REG(SPIx, SPI_FIFO_WDATA, data); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send 8-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t rData; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send 16-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t rData; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send 24-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t rData; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send 32-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t rData; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI receive 8-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t rxLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo with 0 */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (rxLen = 0; rxLen < tmpVal; rxLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive data and send the rest of the data 0 */ + for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive the rest of the data */ + for (; rxLen < length; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI receive 16-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t rxLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo with 0 */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (rxLen = 0; rxLen < tmpVal; rxLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive data and send the rest of the data 0 */ + for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive the rest of the data */ + for (; rxLen < length; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI receive 24-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t rxLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo with 0 */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (rxLen = 0; rxLen < tmpVal; rxLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive data and send the rest of the data 0 */ + for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff; + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive the rest of the data */ + for (; rxLen < length; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI receive 32-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t rxLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo with 0 */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (rxLen = 0; rxLen < tmpVal; rxLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive data and send the rest of the data 0 */ + for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive the rest of the data */ + for (; rxLen < length; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send and receive 8-bit datas at the same time + * + * @param spiNo: SPI ID type + * @param sendBuff: Buffer of datas to send + * @param recvBuff: Buffer of datas received + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[txLen - tmpVal] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[length - tmpVal + txLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send and receive 16-bit datas at the same time + * + * @param spiNo: SPI ID type + * @param sendBuff: Buffer of datas to send + * @param recvBuff: Buffer of datas received + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo, uint16_t *sendBuff, uint16_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[txLen - tmpVal] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[length - tmpVal + txLen] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send and receive 24-bit datas at the same time + * + * @param spiNo: SPI ID type + * @param sendBuff: Buffer of datas to send + * @param recvBuff: Buffer of datas received + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff; + BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send and receive 32-bit datas at the same time + * + * @param spiNo: SPI ID type + * @param sendBuff: Buffer of datas to send + * @param recvBuff: Buffer of datas received + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI read data from rx fifo + * + * @param spiNo: SPI ID type + * + * @return Data readed + * +*******************************************************************************/ +uint32_t SPI_ReceiveData(SPI_ID_Type spiNo) +{ + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + return BL_RD_REG(SPIx, SPI_FIFO_RDATA); +} + +/****************************************************************************/ /** + * @brief Get tx fifo available count value function + * + * @param spiNo: SPI ID type + * + * @return Count value + * +*******************************************************************************/ +uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo) +{ + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Get count value */ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_TX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief Get rx fifo available count value function + * + * @param spiNo: SPI ID type + * + * @return Count value + * +*******************************************************************************/ +uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo) +{ + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Get count value */ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief Get spi interrupt status + * + * @param spiNo: SPI ID type + * @param intType: SPI interrupt type + * + * @return Status of interrupt + * +*******************************************************************************/ +BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_INT_TYPE(intType)); + + /* Get certain or all interrupt status */ + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + if (SPI_INT_ALL == intType) { + if ((tmpVal & 0x3f) != 0) { + return SET; + } else { + return RESET; + } + } else { + if ((tmpVal & (1U << intType)) != 0) { + return SET; + } else { + return RESET; + } + } +} + +/****************************************************************************/ /** + * @brief Get indicator of spi bus busy + * + * @param spiNo: SPI ID type + * + * @return Status of spi bus + * +*******************************************************************************/ +BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Get bus busy status */ + tmpVal = BL_RD_REG(SPIx, SPI_BUS_BUSY); + + if (BL_IS_REG_BIT_SET(tmpVal, SPI_STS_SPI_BUS_BUSY)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Get tx/rx fifo overflow or underflow status + * + * @param spiNo: SPI ID type + * @param fifoSts: Select tx/rx overflow or underflow + * + * @return Status of tx/rx fifo + * +*******************************************************************************/ +BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_FIFOSTATUS_TYPE(fifoSts)); + + /* Get tx/rx fifo overflow or underflow status */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + + if ((tmpVal & (1U << (fifoSts + SPI_TX_FIFO_OVERFLOW_POS))) != 0) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief SPI interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void SPI_IRQHandler(void) +{ + SPI_IntHandler(SPI_ID_0); +} +#endif + +/*@} end of group SPI_Public_Functions */ + +/*@} end of group SPI */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_timer.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..152216475d64b12c902ece08a85241835200a07a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_timer.c @@ -0,0 +1,894 @@ +/** + ****************************************************************************** + * @file bl602_timer.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_timer.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Private_Macros + * @{ + */ +#define TIMER_MAX_MATCH 3 + +/*@} end of group TIMER_Private_Macros */ + +/** @defgroup TIMER_Private_Types + * @{ + */ + +/*@} end of group TIMER_Private_Types */ + +/** @defgroup TIMER_Private_Variables + * @{ + */ +intCallback_Type *timerIntCbfArra[3][TIMER_INT_ALL] = { + { NULL, NULL, NULL }, + { NULL, NULL, NULL }, + { NULL, NULL, NULL } +}; + +/*@} end of group TIMER_Private_Variables */ + +/** @defgroup TIMER_Global_Variables + * @{ + */ + +/*@} end of group TIMER_Global_Variables */ + +/** @defgroup TIMER_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh); +#endif + +/*@} end of group TIMER_Private_Fun_Declaration */ + +/** @defgroup TIMER_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief TIMER interrupt common handler function + * + * @param irqNo: Interrupt ID type + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh) +{ + uint32_t intId; + uint32_t tmpVal; + uint32_t tmpAddr; + + intId = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timerCh); + tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timerCh; + tmpVal = BL_RD_WORD(tmpAddr); + + /* Comparator 0 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_0)) { + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_0)); + + if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_0] != NULL) { + /* Call the callback function */ + timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_0](); + } + } + + /* Comparator 1 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_1)) { + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_1)); + + if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_1] != NULL) { + /* Call the callback function */ + timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_1](); + } + } + + /* Comparator 2 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_2)) { + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_2)); + + if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_2] != NULL) { + /* Call the callback function */ + timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_2](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief Get the specified channel and match comparator value + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * + * @return Match comapre register value + * +*******************************************************************************/ +uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpVal = BL_RD_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo)); + return tmpVal; +} + +/****************************************************************************/ /** + * @brief TIMER set specified channel and comparator compare value + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * @param val: TIMER match comapre register value + * + * @return None + * +*******************************************************************************/ +void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + BL_WR_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo), val); +} + +/****************************************************************************/ /** + * @brief TIMER get the specified channel count value + * + * @param timerCh: TIMER channel type + * + * @return TIMER count register value + * +*******************************************************************************/ +uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + uint32_t tmpAddr; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + /* TO avoid risk of reading, don't read TCVWR directly*/ + /* request for read*/ + tmpAddr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timerCh; + BL_WR_WORD(tmpAddr, 1); + + /* Need wait */ + tmpVal = BL_RD_WORD(tmpAddr); + tmpVal = BL_RD_WORD(tmpAddr); + tmpVal = BL_RD_WORD(tmpAddr); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief TIMER get specified channel and comparator match status + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpVal; + BL_Sts_Type bitStatus = RESET; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpVal = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timerCh); + + switch (cmpNo) { + case TIMER_COMP_ID_0: + bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_0) ? SET : RESET; + break; + + case TIMER_COMP_ID_1: + bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_1) ? SET : RESET; + break; + + case TIMER_COMP_ID_2: + bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_2) ? SET : RESET; + break; + + default: + break; + } + + return bitStatus; +} + +/****************************************************************************/ /** + * @brief TIMER get specified channel preload value + * + * @param timerCh: TIMER channel type + * + * @return Preload register value + * +*******************************************************************************/ +uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + return BL_RD_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timerCh); +} + +/****************************************************************************/ /** + * @brief TIMER set preload register low 32bits value + * + * @param timerCh: TIMER channel type + * @param val: Preload register low 32bits value + * + * @return None + * +*******************************************************************************/ +void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timerCh, val); +} + +/****************************************************************************/ /** + * @brief TIMER set preload trigger source,COMP0,COMP1,COMP2 or None + * + * @param timerCh: TIMER channel type + * @param plSrc: TIMER preload source type + * + * @return None + * +*******************************************************************************/ +void TIMER_SetPreloadTrigSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(plSrc)); + + BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timerCh, plSrc); +} + +/****************************************************************************/ /** + * @brief TIMER set count mode:preload or free run + * + * @param timerCh: TIMER channel type + * @param countMode: TIMER count mode: TIMER_COUNT_PRELOAD or TIMER_COUNT_FREERUN + * + * @return None + * +*******************************************************************************/ +void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode) +{ + uint32_t tmpval; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(countMode)); + + tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET); + tmpval &= (~(1 << (timerCh + 1))); + tmpval |= (countMode << (timerCh + 1)); + + BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval); +} + +/****************************************************************************/ /** + * @brief TIMER clear interrupt status + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER macth comparator ID type + * + * @return None + * +*******************************************************************************/ +void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpAddr; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timerCh; + + tmpVal = BL_RD_WORD(tmpAddr); + tmpVal |= (1 << cmpNo); + + BL_WR_WORD(tmpAddr, tmpVal); +} + +/****************************************************************************/ /** + * @brief TIMER initialization function + * + * @param timerCfg: TIMER configuration structure pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type TIMER_Init(TIMER_CFG_Type *timerCfg) +{ + TIMER_Chan_Type timerCh = timerCfg->timerCh; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(timerCfg->clkSrc)); + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCfg->timerCh)); + CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(timerCfg->plTrigSrc)); + CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(timerCfg->countMode)); + + /* Configure timer clock source */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + + if (timerCh == TIMER_CH0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_1, timerCfg->clkSrc); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_2, timerCfg->clkSrc); + } + + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpVal); + + /* Configure timer clock division */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + + if (timerCh == TIMER_CH0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, timerCfg->clockDivision); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR3, timerCfg->clockDivision); + } + + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); + + /* Configure timer count mode: preload or free run */ + TIMER_SetCountMode(timerCh, timerCfg->countMode); + + /* Configure timer preload trigger src */ + TIMER_SetPreloadTrigSrc(timerCh, timerCfg->plTrigSrc); + + if (timerCfg->countMode == TIMER_COUNT_PRELOAD) { + /* Configure timer preload value */ + TIMER_SetPreloadValue(timerCh, timerCfg->preLoadVal); + + /* Configure match compare values */ + if (timerCfg->matchVal0 > 1 + timerCfg->preLoadVal) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0); + } + + if (timerCfg->matchVal1 > 1 + timerCfg->preLoadVal) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1); + } + + if (timerCfg->matchVal2 > 1 + timerCfg->preLoadVal) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2); + } + } else { + /* Configure match compare values */ + if (timerCfg->matchVal0 > 1) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0); + } + + if (timerCfg->matchVal1 > 1) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1); + } + + if (timerCfg->matchVal2 > 1) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2); + } + } + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER_CH0_IRQHandler); + Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER_CH1_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief TIMER enable one channel function + * + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +void TIMER_Enable(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCER); + tmpVal |= (1 << (timerCh + 1)); + + BL_WR_REG(TIMER_BASE, TIMER_TCER, tmpVal); +} + +/****************************************************************************/ /** + * @brief TIMER disable one channel function + * + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +void TIMER_Disable(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCER); + tmpVal &= (~(1 << (timerCh + 1))); + + BL_WR_REG(TIMER_BASE, TIMER_TCER, tmpVal); +} + +/****************************************************************************/ /** + * @brief TIMER mask or unmask certain or all interrupt + * + * @param timerCh: TIMER channel type + * @param intType: TIMER interrupt type + * @param intMask: TIMER interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt + * + * @return None + * +*******************************************************************************/ +void TIMER_IntMask(TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpAddr; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpAddr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timerCh; + tmpVal = BL_RD_WORD(tmpAddr); + + switch (intType) { + case TIMER_INT_COMP_0: + if (intMask == UNMASK) { + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_0)); + } else { + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_0)); + } + + break; + + case TIMER_INT_COMP_1: + if (intMask == UNMASK) { + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_1)); + } else { + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_1)); + } + + break; + + case TIMER_INT_COMP_2: + if (intMask == UNMASK) { + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_2)); + } else { + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_2)); + } + + break; + + case TIMER_INT_ALL: + if (intMask == UNMASK) { + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_0)); + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_1)); + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_2)); + } else { + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_0)); + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_1)); + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_2)); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief TIMER set watchdog clock source and clock division + * + * @param clkSrc: Watchdog timer clock source type + * @param div: Watchdog timer clock division value + * + * @return None + * +*******************************************************************************/ +void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc, uint8_t div) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(clkSrc)); + + /* Configure watchdog timer clock source */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT, clkSrc); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpVal); + + /* Configure watchdog timer clock divison */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WCDR, div); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); +} + +/****************************************************************************/ /** + * @brief TIMER get watchdog match compare value + * + * @param None + * + * @return Watchdog match comapre register value + * +*******************************************************************************/ +uint16_t WDT_GetMatchValue(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog timer match register value */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMR); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief TIMER set watchdog match compare value + * + * @param val: Watchdog match compare value + * + * @return None + * +*******************************************************************************/ +void WDT_SetCompValue(uint16_t val) +{ + WDT_ENABLE_ACCESS(); + + /* Set watchdog timer match register value */ + BL_WR_REG(TIMER_BASE, TIMER_WMR, val); +} + +/****************************************************************************/ /** + * @brief TIMER get watchdog count register value + * + * @param None + * + * @return Watchdog count register value + * +*******************************************************************************/ +uint16_t WDT_GetCounterValue(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog timer count register value */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WVR); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief TIMER reset watchdog count register value + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_ResetCounterValue(void) +{ + uint32_t tmpVal; + + /* Reset watchdog timer count register value */ + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WCR); + + /* Set watchdog counter reset register bit0 to 1 */ + BL_WR_REG(TIMER_BASE, TIMER_WCR, BL_SET_REG_BIT(tmpVal, TIMER_WCR)); +} + +/****************************************************************************/ /** + * @brief TIMER get watchdog reset status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type WDT_GetResetStatus(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog status register */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WSR); + + return (BL_IS_REG_BIT_SET(tmpVal, TIMER_WTS)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief TIMER clear watchdog reset status + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_ClearResetStatus(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WSR); + + /* Set watchdog status register */ + BL_WR_REG(TIMER_BASE, TIMER_WSR, BL_CLR_REG_BIT(tmpVal, TIMER_WTS)); +} + +/****************************************************************************/ /** + * @brief TIMER enable watchdog function + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_Enable(void) +{ + uint32_t tmpVal; + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(TIMER_WDT_IRQn, TIMER_WDT_IRQHandler); +#endif + + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER); + + BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WE)); +} + +/****************************************************************************/ /** + * @brief Watchdog timer disable function + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_Disable(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER); + + BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WE)); +} + +/****************************************************************************/ /** + * @brief Watchdog timer mask or unmask certain or all interrupt + * + * @param intType: Watchdog interrupt type + * @param intMask: Watchdog interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt + * + * @return None + * +*******************************************************************************/ +void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_WDT_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + WDT_ENABLE_ACCESS(); + + /* Deal with watchdog match/interrupt enable register, + WRIE:watchdog reset/interrupt enable */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER); + + switch (intType) { + case WDT_INT: + if (intMask == UNMASK) { + /* Enable this interrupt */ + /* 0 means generates a watchdog interrupt, + a watchdog timer reset is not generated*/ + BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WRIE)); + } else { + /* Disable this interrupt */ + /* 1 means generates a watchdog timer reset, + a watchdog interrupt is not generated*/ + BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WRIE)); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief TIMER channel 0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH0_IRQHandler(void) +{ + TIMER_IntHandler(TIMER_CH0_IRQn, TIMER_CH0); +} +#endif + +/****************************************************************************/ /** + * @brief TIMER channel 1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH1_IRQHandler(void) +{ + TIMER_IntHandler(TIMER_CH1_IRQn, TIMER_CH1); +} +#endif + +/****************************************************************************/ /** + * @brief TIMER watchdog interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_WDT_IRQHandler(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WICR); + BL_WR_REG(TIMER_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR)); + + if (timerIntCbfArra[TIMER_WDT_IRQn - TIMER_CH0_IRQn][WDT_INT] != NULL) { + /* Call the callback function */ + timerIntCbfArra[TIMER_WDT_IRQn - TIMER_CH0_IRQn][WDT_INT](); + } +} +#endif + +/****************************************************************************/ /** + * @brief TIMER install interrupt callback + * + * @param timerChan: TIMER channel type + * @param intType: TIMER interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan)); + CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); + + timerIntCbfArra[timerChan][intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief Watchdog install interrupt callback + * + * @param wdtInt: Watchdog interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void WDT_Int_Callback_Install(WDT_INT_Type wdtInt, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_WDT_INT_TYPE(wdtInt)); + + timerIntCbfArra[2][wdtInt] = cbFun; +} + +/*@} end of group TIMER_Private_Functions */ + +/*@} end of group TIMER */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_tzc_sec.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_tzc_sec.c new file mode 100644 index 0000000000000000000000000000000000000000..282a0580d83cb083b88f142b2e0dbdc840003967 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_tzc_sec.c @@ -0,0 +1,233 @@ +/** + ****************************************************************************** + * @file bl602_tzc_sec.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_tzc_sec.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup TZC_SEC + * @{ + */ + +/** @defgroup TZC_SEC_Private_Macros + * @{ + */ + +/*@} end of group TZC_SEC_Private_Macros */ + +/** @defgroup TZC_SEC_Private_Types + * @{ + */ + +/*@} end of group TZC_SEC_Private_Types */ + +/** @defgroup TZC_SEC_Private_Variables + * @{ + */ + +/*@} end of group TZC_SEC_Private_Variables */ + +/** @defgroup TZC_SEC_Global_Variables + * @{ + */ + +/*@} end of group TZC_SEC_Global_Variables */ + +/** @defgroup TZC_SEC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group TZC_SEC_Private_Fun_Declaration */ + +/** @defgroup TZC_SEC_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief TZC Security boot set + * + * @param Val: 0 for security boot start, and 0xf for security boot finished + * + * @return None + * +*******************************************************************************/ +void TZC_Sboot_Set(uint8_t Val) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, Val); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief TZC Set ROM0 R0 protect range + * + * @param start: Start address to protect + * @param end: End address to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom0_R0_Protect(uint32_t start, uint32_t end) +{ + uint32_t tmpVal; + + /* Set Range */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R0); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_START, start >> 10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_END, end >> 10); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R0, tmpVal); + + /* Enable */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_ID0_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_ID1_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_LOCK, 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief TZC Set ROM0 R1 protect range + * + * @param start: Start address to protect + * @param end: End address to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom0_R1_Protect(uint32_t start, uint32_t end) +{ + uint32_t tmpVal; + + /* Set Range */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R1); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_START, start >> 10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_END, end >> 10); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R1, tmpVal); + + /* Enable */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_ID0_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_ID1_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_LOCK, 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief TZC Set ROM1 R0 protect range + * + * @param start: Start address to protect + * @param end: End address to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom1_R0_Protect(uint32_t start, uint32_t end) +{ + uint32_t tmpVal; + + /* Set Range */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R0); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_START, start >> 10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_END, end >> 10); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R0, tmpVal); + + /* Enable */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_ID0_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_ID1_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_LOCK, 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief TZC Set ROM1 R1 protect range + * + * @param start: Start address to protect + * @param end: End address to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom1_R1_Protect(uint32_t start, uint32_t end) +{ + uint32_t tmpVal; + + /* Set Range */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R1); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_START, start >> 10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_END, end >> 10); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R1, tmpVal); + + /* Enable */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_ID0_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_ID1_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_LOCK, 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/*@} end of group TZC_SEC_Public_Functions */ + +/*@} end of group TZC_SEC */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_uart.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..422249e3c842932dddcf3accf0402176423c1d50 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_uart.c @@ -0,0 +1,1240 @@ +/** + ****************************************************************************** + * @file bl602_uart.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_uart.h" +#include "bl602_glb.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_Private_Macros + * @{ + */ +#define UART_TX_TIMEOUT_COUNT (160 * 1000) + +/*@} end of group UART_Private_Macros */ + +/** @defgroup UART_Private_Types + * @{ + */ + +/*@} end of group UART_Private_Types */ + +/** @defgroup UART_Private_Variables + * @{ + */ +static const uint32_t uartAddr[2] = { UART0_BASE, UART1_BASE }; +static intCallback_Type *uartIntCbfArra[2][UART_INT_ALL] = { + { NULL }, + { NULL } +}; + +/*@} end of group UART_Private_Variables */ + +/** @defgroup UART_Global_Variables + * @{ + */ + +/*@} end of group UART_Global_Variables */ + +/** @defgroup UART_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void UART_IntHandler(UART_ID_Type uartId); +#endif + +/*@} end of group UART_Private_Fun_Declaration */ + +/** @defgroup UART_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief UART interrupt common handler function + * + * @param uartId: UART ID type + * + * @return None + * +*******************************************************************************/ +#if 1 //#ifndef BFLB_USE_HAL_DRIVER +static void UART_IntHandler(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t maskVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + tmpVal = BL_RD_REG(UARTx, UART_INT_STS); + maskVal = BL_RD_REG(UARTx, UART_INT_MASK); + + /* Length of uart tx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1); + + if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) { + uartIntCbfArra[uartId][UART_INT_TX_END](); + } + } + + /* Length of uart rx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2); + + if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) { + uartIntCbfArra[uartId][UART_INT_RX_END](); + } + } + + /* Tx fifo ready interrupt,auto-cleared when data is pushed */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) { + if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) { + uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ](); + } + } + + /* Rx fifo ready interrupt,auto-cleared when data is popped */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) { + if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) { + uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ](); + } + } + + /* Rx time-out interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10); + + if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) { + uartIntCbfArra[uartId][UART_INT_RTO](); + } + } + + /* Rx parity check error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20); + + if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) { + uartIntCbfArra[uartId][UART_INT_PCE](); + } + } + + /* Tx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { + if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) { + uartIntCbfArra[uartId][UART_INT_TX_FER](); + } + } + + /* Rx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { + if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) { + uartIntCbfArra[uartId][UART_INT_RX_FER](); + } + } +} +#endif + +/*@} end of group UART_Private_Functions */ + +/** @defgroup UART_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief UART initialization function + * + * @param uartId: UART ID type + * @param uartCfg: UART configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg) +{ + uint32_t tmpValTxCfg = 0; + uint32_t tmpValRxCfg = 0; + uint32_t fraction = 0; + uint32_t baudRateDivisor = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity)); + CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits)); + CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits)); + CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse)); + + /* Cal the baud rate divisor */ + fraction = uartCfg->uartClk * 10 / uartCfg->baudRate % 10; + baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate; + + if (fraction >= 5) { + ++baudRateDivisor; + } + + /* Set the baud rate register value */ + BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF)); + + /* Configure parity type */ + tmpValTxCfg = BL_RD_REG(UARTx, UART_UTX_CONFIG); + tmpValRxCfg = BL_RD_REG(UARTx, UART_URX_CONFIG); + + switch (uartCfg->parity) { + case UART_PARITY_NONE: + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); + break; + + case UART_PARITY_ODD: + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL); + break; + + case UART_PARITY_EVEN: + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL); + break; + + default: + break; + } + + /* Configure data bits */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_D, (uartCfg->dataBits + 4)); + tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_BIT_CNT_D, (uartCfg->dataBits + 4)); + + /* Configure tx stop bits */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, uartCfg->stopBits); + + /* Configure tx cts flow control function */ + if (ENABLE == uartCfg->ctsFlowControl) { + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_CTS_EN); + } else { + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_CTS_EN); + } + + /* Configure rx input de-glitch function */ + if (ENABLE == uartCfg->rxDeglitch) { + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_DEG_EN); + } else { + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_DEG_EN); + } + + /* Configure rx rts output SW control mode */ + if (ENABLE == uartCfg->rtsSoftwareControl) { + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_RTS_SW_MODE); + } else { + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_RTS_SW_MODE); + } + + /* Write back */ + BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpValTxCfg); + BL_WR_REG(UARTx, UART_URX_CONFIG, tmpValRxCfg); + + /* Configure LSB-first or MSB-first */ + tmpValTxCfg = BL_RD_REG(UARTx, UART_DATA_CONFIG); + + if (UART_MSB_FIRST == uartCfg->byteBitInverse) { + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV); + } else { + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV); + } + + BL_WR_REG(UARTx, UART_DATA_CONFIG, tmpValTxCfg); + +#if 1 //#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(UART0_IRQn, UART0_IRQHandler); + Interrupt_Handler_Register(UART1_IRQn, UART1_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set default value of all registers function + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_DeInit(UART_ID_Type uartId) +{ + if (UART0_ID == uartId) { + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0); + } else if (UART1_ID == uartId) { + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART configure fifo function + * + * @param uartId: UART ID type + * @param fifoCfg: FIFO configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Deal with uart fifo configure register */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1); + /* Configure dma tx fifo threshold */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold - 1); + /* Configure dma rx fifo threshold */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold - 1); + /* Write back */ + BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal); + + /* Enable or disable uart fifo dma function */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); + + if (ENABLE == fifoCfg->txFifoDmaEnable) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN); + } + + if (ENABLE == fifoCfg->rxFifoDmaEnable) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN); + } + + BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART configure infra function + * + * @param uartId: UART ID type + * @param irCfg: IR configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Configure tx ir mode */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + + if (ENABLE == irCfg->txIrEnable) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_EN); + } + + if (ENABLE == irCfg->txIrInverse) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_INV); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_INV); + } + + BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpVal); + + /* Configure rx ir mode */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + + if (ENABLE == irCfg->rxIrEnable) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_EN); + } + + if (ENABLE == irCfg->rxIrInverse) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_INV); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_INV); + } + + BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal); + + /* Configure tx ir pulse start and stop position */ + BL_WR_REG(UARTx, UART_UTX_IR_POSITION, irCfg->txIrPulseStop << 0x10 | irCfg->txIrPulseStart); + + /* Configure rx ir pulse start position */ + BL_WR_REG(UARTx, UART_URX_IR_POSITION, irCfg->rxIrPulseStart); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable UART + * + * @param uartId: UART ID type + * @param direct: UART direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); + + if (direct == UART_TX || direct == UART_TXRX) { + /* Enable UART tx unit */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_EN)); + } + + if (direct == UART_RX || direct == UART_TXRX) { + /* Enable UART rx unit */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable UART + * + * @param uartId: UART ID type + * @param direct: UART direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); + + if (direct == UART_TX || direct == UART_TXRX) { + /* Disable UART tx unit */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_EN)); + } + + if (direct == UART_RX || direct == UART_TXRX) { + /* Disable UART rx unit */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set length of tx data transfer,tx end interrupt will assert when this length is + * reached + * + * @param uartId: UART ID type + * @param length: Length of data (unit:character/byte) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set length */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_LEN, length - 1)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set length of rx data transfer,rx end interrupt will assert when this length is + * reached + * + * @param uartId: UART ID type + * @param length: Length of data (unit:character/byte) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set length */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_LEN, length - 1)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set rx time-out value for triggering RTO interrupt + * + * @param uartId: UART ID type + * @param time: Time-out value (unit:bit time) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set time-out value */ + tmpVal = BL_RD_REG(UARTx, UART_URX_RTO_TIMER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_RTO_VALUE, time - 1); + BL_WR_REG(UARTx, UART_URX_RTO_TIMER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set de-glitch function cycle count value + * + * @param uartId: UART ID type + * @param deglitchCnt: De-glitch function cycle count + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set count value */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt); + BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set tx and rx baudrate according to auto baudrate detection value + * + * @param uartId: UART ID type + * @param autoBaudDet: Choose detection value using codeword 0x55 or start bit + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) +{ + uint32_t UARTx = uartAddr[uartId]; + uint16_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Get detection value */ + tmpVal = UART_GetAutoBaudCount(uartId, autoBaudDet); + + /* Set tx baudrate */ + BL_WR_REG(UARTx, UART_BIT_PRD, tmpVal << 0x10 | tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set rx rts output software control value + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Rts set 1*/ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART clear rx rts output software control value + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Rts clear 0 */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART configure tx free run mode function + * + * @param uartId: UART ID type + * @param txFreeRun: Enable or disable tx free run mode + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Enable or disable tx free run mode */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + + if (ENABLE == txFreeRun) { + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN)); + } else { + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART configure auto baud rate detection function + * + * @param uartId: UART ID type + * @param autoBaud: Enable or disable auto function + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Enable or disable auto baud rate detection function */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + + if (ENABLE == autoBaud) { + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_ABR_EN)); + } else { + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_ABR_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART tx fifo clear + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Clear tx fifo */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); + BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_TX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART rx fifo clear + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Clear rx fifo */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); + BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_RX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART mask or unmask certain or all interrupt + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * @param intMask: UART interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(UARTx, UART_INT_MASK); + + /* Mask or unmask certain or all interrupt */ + if (UART_INT_ALL == intType) { + if (MASK == intMask) { + tmpVal |= 0xff; + } else { + tmpVal &= 0; + } + } else { + if (MASK == intMask) { + tmpVal |= 1 << intType; + } else { + tmpVal &= ~(1 << intType); + } + } + + /* Write back */ + BL_WR_REG(UARTx, UART_INT_MASK, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART clear certain or all interrupt + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(UARTx, UART_INT_CLEAR); + + /* Clear certain or all interrupt */ + if (UART_INT_ALL == intType) { + tmpVal |= 0xff; + } else { + tmpVal |= 1 << intType; + } + + /* Write back */ + BL_WR_REG(UARTx, UART_INT_CLEAR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Install uart interrupt callback function + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + + uartIntCbfArra[uartId][intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART send data to tx fifo + * + * @param uartId: UART ID type + * @param data: The data to be send + * @param len: The length of the send buffer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len) +{ + uint32_t txLen = 0; + uint32_t UARTx = uartAddr[uartId]; + uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Send data */ + while (txLen < len) { + if (UART_GetTxFifoCount(uartId) > 0) { + BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]); + timeoutCnt = UART_TX_TIMEOUT_COUNT; + } else { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART send data to tx fifo in block mode + * + * @param uartId: UART ID type + * @param data: The data to be send + * @param len: The length of the send buffer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len) +{ + uint32_t txLen = 0; + uint32_t UARTx = uartAddr[uartId]; + uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Send data */ + while (txLen < len) { + if (UART_GetTxFifoCount(uartId) > 0) { + BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]); + timeoutCnt = UART_TX_TIMEOUT_COUNT; + } else { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + while (UART_GetTxBusBusyStatus(uartId) == SET) { + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART receive data from rx fifo + * + * @param uartId: UART ID type + * @param data: The receive data buffer + * @param maxLen: The max length of the buffer + * + * @return The length of the received buffer + * +*******************************************************************************/ +uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen) +{ + uint32_t rxLen = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Receive data */ + while (rxLen < maxLen && UART_GetRxFifoCount(uartId) > 0) { + data[rxLen++] = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET); + } + + return rxLen; +} + +/****************************************************************************/ /** + * @brief UART get auto baud count value + * + * @param uartId: UART ID type + * @param autoBaudDet: Detection using codeword 0x55 or start bit + * + * @return Bit period of auto baudrate detection + * +*******************************************************************************/ +uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_AUTOBAUDDETECTION_TYPE(autoBaudDet)); + + /* Select 0x55 or start bit detection value */ + if (UART_AUTOBAUD_0X55 == autoBaudDet) { + return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) >> 0x10 & 0xffff; + } else { + return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) & 0xffff; + } +} + +/****************************************************************************/ /** + * @brief UART get tx fifo unoccupied count value + * + * @param uartId: UART ID type + * + * @return Tx fifo unoccupied count value + * +*******************************************************************************/ +uint8_t UART_GetTxFifoCount(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief UART get rx fifo occupied count value + * + * @param uartId: UART ID type + * + * @return Rx fifo occupied count value + * +*******************************************************************************/ +uint8_t UART_GetRxFifoCount(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief Get uart interrupt status + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * + * @return Status of interrupt + * +*******************************************************************************/ +BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + + /* Get certain or all interrupt status */ + tmpVal = BL_RD_REG(UARTx, UART_INT_STS); + + if (UART_INT_ALL == intType) { + if ((tmpVal & 0xff) != 0) { + return SET; + } else { + return RESET; + } + } else { + if ((tmpVal & (1U << intType)) != 0) { + return SET; + } else { + return RESET; + } + } +} + +/****************************************************************************/ /** + * @brief Get indicator of uart tx bus busy + * + * @param uartId: UART ID type + * + * @return Status of tx bus + * +*******************************************************************************/ +BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Get tx bus busy status */ + tmpVal = BL_RD_REG(UARTx, UART_STATUS); + + if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_UTX_BUS_BUSY)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Get indicator of uart rx bus busy + * + * @param uartId: UART ID type + * + * @return Status of rx bus + * +*******************************************************************************/ +BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Get rx bus busy status */ + tmpVal = BL_RD_REG(UARTx, UART_STATUS); + + if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_URX_BUS_BUSY)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Get tx/rx fifo overflow or underflow status + * + * @param uartId: UART ID type + * @param overflow: Select tx/rx overflow or underflow + * + * @return Status of tx/rx fifo + * +*******************************************************************************/ +BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_OVERFLOW_TYPE(overflow)); + + /* Get tx/rx fifo overflow or underflow status */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); + + if ((tmpVal & (1U << (overflow + 4))) != 0) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Get current baudrate function + * + * @param uartId: UART ID type + * + * @return Baudrate + * +*******************************************************************************/ +uint32_t UART_GetBaudrate(UART_ID_Type uartId) +{ + uint32_t clock = 0; + uint32_t tmpVal = 0; + uint32_t div1 = 1; + uint32_t div2 = 1; + uint32_t UARTx = uartAddr[uartId]; + + /* Get uart clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + div2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV) + 1; + + if (BL_IS_REG_BIT_SET(tmpVal, GLB_HBN_UART_CLK_SEL)) { + clock = 160000000; + } else { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + div1 = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL); + + if (tmpVal == 0) { + clock = 32000000; + } else if (tmpVal == 1) { + clock = 40000000; + } else { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL); + + switch (tmpVal) { + case 0: + clock = 48000000; + break; + + case 1: + clock = 120000000; + break; + + case 2: + clock = 160000000; + break; + + case 3: + clock = 192000000; + break; + + default: + clock = 160000000; + break; + } + } + + clock /= div1; + } + + clock /= div2; + + /* Get uart bit period */ + tmpVal = BL_RD_REG(UARTx, UART_BIT_PRD); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, UART_CR_UTX_BIT_PRD) + 1; + + return (clock / tmpVal); +} + +/****************************************************************************/ /** + * @brief UART0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#if 1 //#ifndef BFLB_USE_HAL_DRIVER +void UART0_IRQHandler(void) +{ + UART_IntHandler(UART0_ID); +} +#endif + +/****************************************************************************/ /** + * @brief UART1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#if 1 //#ifndef BFLB_USE_HAL_DRIVER +void UART1_IRQHandler(void) +{ + UART_IntHandler(UART1_ID); +} +#endif + +/*@} end of group UART_Public_Functions */ + +/*@} end of group UART */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_xip_sflash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_xip_sflash.c new file mode 100644 index 0000000000000000000000000000000000000000..a4df0c2c24c10f95ed05f1a210166e7ddc9e6772 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_xip_sflash.c @@ -0,0 +1,441 @@ +/** + ****************************************************************************** + * @file bl602_xip_sflash.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_xip_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_Private_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Macros */ + +/** @defgroup XIP_SFLASH_Private_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Types */ + +/** @defgroup XIP_SFLASH_Private_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Variables */ + +/** @defgroup XIP_SFLASH_Global_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_Global_Variables */ + +/** @defgroup XIP_SFLASH_Private_Fun_Declaration + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ + +/** @defgroup XIP_SFLASH_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Save flash controller state + * + * @param pFlashCfg: Flash config pointer + * @param offset: CPU XIP flash offset pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) +{ + /* XIP_SFlash_Delay */ + volatile uint32_t i = 32 * 2; + + while (i--) + ; + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + /* Exit form continous read for accepting command */ + SFlash_Reset_Continue_Read(pFlashCfg); + /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */ + SFlash_Software_Reset(pFlashCfg); + /* For disable command that is setting register instaed of send command, we need write enable */ + SFlash_DisableBurstWrap(pFlashCfg); + /* Enable QE again in case reset command make it reset */ + SFlash_Qspi_Enable(pFlashCfg); + /* Deburst again to make sure */ + SFlash_DisableBurstWrap(pFlashCfg); + + /* Clear offset setting*/ + *offset = SF_Ctrl_Get_Flash_Image_Offset(); + SF_Ctrl_Set_Flash_Image_Offset(0); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Restore flash controller state + * + * @param pFlashCfg: Flash config pointer + * @param offset: CPU XIP flash offset + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset) +{ + uint32_t tmp[1]; + + SF_Ctrl_Set_Flash_Image_Offset(offset); + + SFlash_SetBurstWrap(pFlashCfg); + SFlash_Read(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); + SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); + + return SUCCESS; +} + +/*@} end of group XIP_SFLASH_Private_Functions */ + +/** @defgroup XIP_SFLASH_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Erase flash one region + * + * @param pFlashCfg: Flash config pointer + * @param startaddr: start address to erase + * @param endaddr: end address(include this address) to erase + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); + } else { + stat = SFlash_Erase(pFlashCfg, startaddr, endaddr); + XIP_SFlash_State_Restore(pFlashCfg, offset); + } + + return stat; +} + +/****************************************************************************/ /** + * @brief Program flash one region + * + * @param pFlashCfg: Flash config pointer + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); + } else { + stat = SFlash_Program(pFlashCfg, SF_CTRL_QIO_MODE, addr, data, len); + XIP_SFlash_State_Restore(pFlashCfg, offset); + } + + return stat; +} + +/****************************************************************************/ /** + * @brief Read data from flash + * + * @param pFlashCfg: Flash config pointer + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); + } else { + stat = SFlash_Read(pFlashCfg, SF_CTRL_QIO_MODE, 0, addr, data, len); + XIP_SFlash_State_Restore(pFlashCfg, offset); + } + + return stat; +} + +/****************************************************************************/ /** + * @brief Get Flash Jedec ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Jedec ID Read from flash + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); + } else { + SFlash_GetJedecId(pFlashCfg, data); + XIP_SFlash_State_Restore(pFlashCfg, offset); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get Flash Device ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Device ID Read from flash + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); + } else { + SFlash_GetDeviceId(data); + XIP_SFlash_State_Restore(pFlashCfg, offset); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get Flash Unique ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Device ID Read from flash + * @param idLen: Unique id len + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); + } else { + SFlash_GetUniqueId(data, idLen); + XIP_SFlash_State_Restore(pFlashCfg, offset); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read data from flash via XIP + * + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) +{ + uint32_t offset; + + if (addr >= BL602_FLASH_XIP_BASE && addr < BL602_FLASH_XIP_END) { + offset = SF_Ctrl_Get_Flash_Image_Offset(); + SF_Ctrl_Set_Flash_Image_Offset(0); + /* Flash read */ + BL602_MemCpy_Fast(data, (void *)(addr), len); + SF_Ctrl_Set_Flash_Image_Offset(offset); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read data from flash with lock + * + * @param pFlashCfg: Flash config pointer + * @param addr: flash read start address + * @param dst: data pointer to store data read from flash + * @param len: data length to read + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *dst, int len) +{ + __disable_irq(); + XIP_SFlash_Read_Need_Lock(pFlashCfg, addr, dst, len); + __enable_irq(); + return 0; +} + +/****************************************************************************/ /** + * @brief Program flash one region with lock + * + * @param pFlashCfg: Flash config pointer + * @param addr: Start address to be programed + * @param src: Data pointer to be programed + * @param len: Data length to be programed + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *src, int len) +{ + __disable_irq(); + XIP_SFlash_Write_Need_Lock(pFlashCfg, addr, src, len); + __enable_irq(); + return 0; +} + +/****************************************************************************/ /** + * @brief Erase flash one region with lock + * + * @param pFlashCfg: Flash config pointer + * @param addr: Start address to be erased + * @param len: Data length to be erased + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, int len) +{ + __disable_irq(); + XIP_SFlash_Erase_Need_Lock(pFlashCfg, addr, addr + len - 1); + __enable_irq(); + return 0; +} + +/****************************************************************************/ /** + * @brief XIP SFlash option save + * + * @param aesEnable: AES enable status pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) +{ + *aesEnable = SF_Ctrl_Is_AES_Enable(); + + if (*aesEnable) { + SF_Ctrl_AES_Disable(); + } +} + +/****************************************************************************/ /** + * @brief XIP SFlash option restore + * + * @param aesEnable: AES enable status + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) +{ + if (aesEnable) { + SF_Ctrl_AES_Enable(); + } +} +#endif + +/*@} end of group XIP_SFLASH_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_xip_sflash_ext.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_xip_sflash_ext.c new file mode 100644 index 0000000000000000000000000000000000000000..e0d62f67da427255f3283f809fae10bdfe5dc9fb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_xip_sflash_ext.c @@ -0,0 +1,497 @@ +/** + ****************************************************************************** + * @file bl602_xip_sflash_ext.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_sf_cfg.h" +#include "bl602_sf_cfg_ext.h" +#include "bl602_xip_sflash.h" +#include "bl602_xip_sflash_ext.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH_EXT + * @{ + */ + +/** @defgroup XIP_SFLASH_EXT_Private_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Macros */ + +/** @defgroup XIP_SFLASH_EXT_Private_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Types */ + +/** @defgroup XIP_SFLASH_EXT_Private_Variables + * @{ + */ + +static SPI_Flash_Cfg_Type flashCfg; +static uint8_t aesEnable; + +/*@} end of group XIP_SFLASH_EXT_Private_Variables */ + +/** @defgroup XIP_SFLASH_EXT_Global_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Global_Variables */ + +/** @defgroup XIP_SFLASH_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Fun_Declaration */ + +/** @defgroup XIP_SFLASH_EXT_Private_Functions + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Functions */ + +/** @defgroup XIP_SFLASH_EXT_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Restore flash controller state + * + * @param pFlashCfg: Flash config pointer + * @param offset: CPU XIP flash offset + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset) +{ + uint32_t tmp[1]; + SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + + SF_Ctrl_Set_Flash_Image_Offset(offset); + + if(((pFlashCfg->ioMode>>4)&0x01) == 0) { + if((pFlashCfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) { + SFlash_SetBurstWrap(pFlashCfg); + } + } + SFlash_Read(pFlashCfg,ioMode,1,0x0,(uint8_t *)tmp, sizeof(tmp)); + SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + + return SUCCESS; +} + +/*@} end of group XIP_SFLASH_EXT_Public_Functions */ + +/** @defgroup XIP_SFLASH_EXT_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Erase flash one region + * + * @param pFlashCfg: Flash config pointer + * @param startaddr: start address to erase + * @param endaddr: end address(include this address) to erase + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr,uint32_t endaddr) +{ + BL_Err_Type stat; + uint32_t offset; + SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + }else{ + stat=SFlash_Erase(pFlashCfg,startaddr,endaddr); + XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + } + + return stat; +} + +/****************************************************************************//** + * @brief Program flash one region + * + * @param pFlashCfg: Flash config pointer + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len) +{ + BL_Err_Type stat; + uint32_t offset; + SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + }else{ + stat= SFlash_Program(pFlashCfg,ioMode,addr,data,len); + XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + } + + return stat; +} + +/****************************************************************************//** + * @brief Read data from flash + * + * @param pFlashCfg: Flash config pointer + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len) +{ + BL_Err_Type stat; + uint32_t offset; + SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + }else{ + stat=SFlash_Read(pFlashCfg,ioMode,0,addr, data,len); + XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + } + + return stat; +} + +/****************************************************************************//** + * @brief Get Flash Jedec ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Jedec ID Read from flash + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data) +{ + BL_Err_Type stat; + uint32_t offset; + SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + }else{ + SFlash_GetJedecId(pFlashCfg,data); + XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get Flash Device ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Device ID Read from flash + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data) +{ + BL_Err_Type stat; + uint32_t offset; + SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + }else{ + SFlash_GetDeviceId(data); + XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get Flash Unique ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Device ID Read from flash + * @param idLen: Unique id len + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data,uint8_t idLen) +{ + BL_Err_Type stat; + uint32_t offset; + SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + }else{ + SFlash_GetUniqueId(data,idLen); + XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Sflash enable RCV mode to recovery for erase while power drop need lock + * + * @param pFlashCfg: Flash config pointer + * @param rCmd: Read RCV register cmd + * @param wCmd: Write RCV register cmd + * @param bitPos: RCV register bit pos + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) +{ + BL_Err_Type stat; + uint32_t offset; + SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + }else{ + stat=SFlash_RCV_Enable(pFlashCfg, rCmd, wCmd, bitPos); + XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + } + + return stat; +} + +/****************************************************************************//** + * @brief Read data from flash with lock + * + * @param pFlashCfg: Flash config pointer + * @param addr: flash read start address + * @param dst: data pointer to store data read from flash + * @param len: data length to read + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len) +{ + __disable_irq(); + XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg, addr, dst, len); + __enable_irq(); + return 0; +} + +/****************************************************************************//** + * @brief Program flash one region with lock + * + * @param pFlashCfg: Flash config pointer + * @param addr: Start address to be programed + * @param src: Data pointer to be programed + * @param len: Data length to be programed + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len) +{ + __disable_irq(); + XIP_SFlash_Write_Need_Lock_Ext(pFlashCfg, addr, src, len); + __enable_irq(); + return 0; +} + +/****************************************************************************//** + * @brief Erase flash one region with lock + * + * @param pFlashCfg: Flash config pointer + * @param addr: Start address to be erased + * @param len: Data length to be erased + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len) +{ + __disable_irq(); + XIP_SFlash_Erase_Need_Lock_Ext(pFlashCfg, addr, addr + len - 1); + __enable_irq(); + return 0; +} + +/****************************************************************************//** + * @brief Sflash enable RCV mode to recovery for erase while power drop with lock + * + * @param pFlashCfg: Flash config pointer + * @param rCmd: Read RCV register cmd + * @param wCmd: Write RCV register cmd + * @param bitPos: RCV register bit pos + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) +{ + __disable_irq(); + XIP_SFlash_RCV_Enable_Need_Lock(pFlashCfg, rCmd, wCmd, bitPos); + __enable_irq(); + return 0; +} + +/****************************************************************************//** + * @brief Read data from flash with lock + * + * @param pFlashCfg:Flash config pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t ret; + + if(pFlashCfg==NULL){ + /* Get flash config identify */ + XIP_SFlash_Opt_Enter(&aesEnable); + ret=SF_Cfg_Flash_Identify_Ext(1,1,0,0,&flashCfg); + XIP_SFlash_Opt_Exit(aesEnable); + if((ret&BFLB_FLASH_ID_VALID_FLAG)==0){ + return ERROR; + } + }else{ + memcpy(&flashCfg,pFlashCfg,sizeof(flashCfg)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Read data from flash with lock + * + * @param addr: flash read start address + * @param dst: data pointer to store data read from flash + * @param len: data length to read + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(&aesEnable); + XIP_SFlash_Read_Need_Lock_Ext(&flashCfg, addr, dst, len); + XIP_SFlash_Opt_Exit(aesEnable); + __enable_irq(); + return 0; +} + +/****************************************************************************//** + * @brief Program flash one region with lock + * + * @param addr: Start address to be programed + * @param src: Data pointer to be programed + * @param len: Data length to be programed + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(&aesEnable); + XIP_SFlash_Write_Need_Lock_Ext(&flashCfg, addr, src, len); + XIP_SFlash_Opt_Exit(aesEnable); + __enable_irq(); + return 0; +} + +/****************************************************************************//** + * @brief Erase flash one region with lock + * + * @param addr: Start address to be erased + * @param len: Data length to be erased + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Erase(uint32_t addr, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(&aesEnable); + XIP_SFlash_Erase_Need_Lock_Ext(&flashCfg, addr, addr + len - 1); + XIP_SFlash_Opt_Exit(aesEnable); + __enable_irq(); + return 0; +} +/*@} end of group XIP_SFLASH_EXT_Public_Functions */ + +/*@} end of group XIP_SFLASH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..4a8ede15484364882c4345941c3683ee1ed4e2c2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld @@ -0,0 +1,232 @@ +/**************************************************************************************** +* @file bl702_flash.ld +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2021 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +/* INPUT(-lc) */ +/* link with the standard GCC library */ +/* INPUT(-lgcc) */ +/* configure the entry point */ +ENTRY(_enter) + +StackSize = 0x1000; /* 4KB */ + +MEMORY +{ + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K + itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K + dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 16K + ram_memory (!rx) : ORIGIN = 0x4201C000, LENGTH = 80K + hbn_memory (rx) : ORIGIN = 0x40010000, LENGTH = 0xE00 /* hbn ram 4K used 3.5K*/ +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + /* section information for shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for usb desc */ + . = ALIGN(4); + _usb_desc_start = .; + KEEP(*(usb_desc)) + . = ALIGN(4); + _usb_desc_end = .; + + *(.text) + *(.text.*) + + /*put .rodata**/ + *(EXCLUDE_FILE( *bl702_glb.o \ + *bl702_pds.o \ + *bl702_common.o \ + *bl702_sf_cfg.o \ + *bl702_sf_ctrl.o \ + *bl702_sflash.o \ + *bl702_xip_sflash.o \ + *bl702_ef_ctrl.o) .rodata*) + *(.rodata) + *(.rodata.*) + + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + *(.tcm_code) + *(.tcm_const) + *(.sclock_rlt_code) + *(.sclock_rlt_const) + + *bl702_glb.o*(.rodata*) + *bl702_pds.o*(.rodata*) + *bl702_common.o*(.rodata*) + *bl702_sf_cfg.o*(.rodata*) + *bl702_sf_ctrl.o*(.rodata*) + *bl702_sflash.o*(.rodata*) + *bl702_xip_sflash.o*(.rodata*) + *bl702_ef_ctrl.o*(.rodata*) + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .hbn_ram_region : AT (__hbn_load_addr) + { + . = ALIGN(4); + __hbn_ram_start__ = .; + *(EXCLUDE_FILE(*bl702_hbn_wakeup.o).rodata*) + *bl702_hbn_wakeup.o*(.rodata*) + *(.hbn_ram_code) + *(.hbn_ram_data) + . = ALIGN(4); + __hbn_ram_end__ = .; + } > hbn_memory + + __dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + PROVIDE( __freertos_irq_stack_top = __StackTop); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + + PROVIDE (__heap_min_size = 0x400); + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + + ASSERT((__HeapLimit - __HeapBase ) >= __heap_min_size, "heap size is too short.") + +} + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/bl702_ram.ld b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/bl702_ram.ld new file mode 100644 index 0000000000000000000000000000000000000000..790b64bac015c7a72ab1c4ae1087c55ca5320ca0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/bl702_ram.ld @@ -0,0 +1,194 @@ +/**************************************************************************************** +* @file bl702_ram.ld +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2021 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +/* INPUT(-lc) */ +/* link with the standard GCC library */ +/* INPUT(-lgcc) */ +/* configure the entry point */ +ENTRY(_enter) + +StackSize = 0x0400; /* 1KB */ + +MEMORY +{ + itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 32K + dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 32K + ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 48K + hbn_memory (rx) : ORIGIN = 0x40010000, LENGTH = 4K /* hbn ram 4K*/ +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + + *(.text) + *(.text.*) + + *(.rodata) + *(.rodata.*) + + *(.srodata) + *(.srodata.*) + + *(.tcm_code) + *(.tcm_const) + *(.sclock_rlt_code) + *(.sclock_rlt_const) + + . = ALIGN(4); + __text_code_end__ = .; + } > itcm_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .hbn_ram_region : AT (__hbn_load_addr) + { + . = ALIGN(4); + __hbn_ram_start__ = .; + *(.hbn_ram_code) + *(.hbn_data) + . = ALIGN(4); + __hbn_ram_end__ = .; + } > hbn_memory + + __dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + + PROVIDE (__heap_min_size = 0x400); + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + + ASSERT((__HeapLimit - __HeapBase ) >= __heap_min_size, "heap size is too short.") + +} + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/blsp_boot2_iap_flash.ld b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/blsp_boot2_iap_flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..8fe54f5fffacacca5c60b968c0d8bf49355e8f66 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/blsp_boot2_iap_flash.ld @@ -0,0 +1,202 @@ +/**************************************************************************************** +* @file map.txt +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2018 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +INPUT(-lc) +/* link with the standard GCC library */ +INPUT(-lgcc) +/* configure the entry point */ +ENTRY(_enter) + +StackSize = 0x1000; /* 4KB */ +HeapSize = 0x0; /* 0KB */ +PROVIDE(__boot2_pass_param_addr = 0x4202DC00); + +MEMORY +{ + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 64K + itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K + dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 4K + ram_memory (!rx) : ORIGIN = 0x42019000/*0x42020000*/, LENGTH = 88K +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + /* section information for finsh shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP(*(shellCommand)) + _shell_command_end = .; + + + + *(EXCLUDE_FILE ( *bl702_uart.c.obj* *hal_uart.c.obj* ) .text*) + /* section information for usb desc */ + . = ALIGN(4); + _usb_desc_start = .; + KEEP(*(usb_desc)) + . = ALIGN(4); + _usb_desc_end = .; + + *(.rodata) + *(.rodata.*) + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + *(.tcm_code) + *(.tcm_const) + *(.sclock_rlt_code) + *(.sclock_rlt_const) + *bl602_romapi.o(.text) + *bl602_romapi.o(.text.*) + *bl602_romapi.o(.rodata) + *bl602_romapi.o(.rodata.*) + *bl602_romapi.o(.srodata) + *bl602_romapi.o(.srodata.*) + *bl702_uart.c.obj* (.text*) + *hal_uart.c.obj* (.text*) + . = ALIGN(4); + __tcm_code_end__ = .; + + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /* .heap_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of heap sections, and assign + * values to heap symbols later */ + .heap_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + HeapSize; + . = ALIGN(0x4); + } > dtcm_memory + + __HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize; + __HeapSize = HeapSize; + __HeapLimit = __HeapBase + __HeapSize; + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__HeapBase >= __tcm_data_end__, "region RAM overflowed with stack") + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + +} + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/cpu_flags.cmake b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/cpu_flags.cmake new file mode 100644 index 0000000000000000000000000000000000000000..ed04bf07ef6a69a0920cb9a5fd8211e3491a39f2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/cpu_flags.cmake @@ -0,0 +1,11 @@ +SET(CPU_ARCH "RISCV") +SET(MCPU "riscv-e24") +SET(MARCH "rv32imafc") +SET(MABI "ilp32f") + +list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI}) +list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI}) + +SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_flash.ld) +SET(RAM_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_ram.ld) +SET(BOOT2_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/blsp_boot2_iap_flash.ld) \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/adc_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/adc_config.h new file mode 100644 index 0000000000000000000000000000000000000000..1946d0cbd182a18f8fdb423a8110765de8a57121 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/adc_config.h @@ -0,0 +1,17 @@ +#ifndef _ADC_CONFIG_H +#define _ADC_CONFIG_H + +#define ADC_DATA_WIDIH_12 (0) + +#define ADC_V18_SELECT (2) /*!< ADC 1.8V select */ +#define ADC_V11_SELECT (1) /*!< ADC 1.1V select */ + +#define ADC_PGA_VCM (0) /*!< ADC VCM value */ +#define ADC_PGA_GAIN1 (0) /*!< PGA gain 1 */ +#define ADC_PGA_GAIN2 (0) /*!< PGA gain 2 */ +#define ADC_CHOP_MODE (2) /*!< ADC chop mode select */ +#define ADC_BIAS_SELECT (0) /*!< ADC current form main bandgap or aon bandgap */ +#define ADC_OFFSET_CALIB_EN (0) /*!< Offset calibration enable */ +#define ADC_OFFSER_CALIB_VAL (0) /*!< Offset calibration value */ + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/dac_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/dac_config.h new file mode 100644 index 0000000000000000000000000000000000000000..33143af6ea500592561539545bb2af6a53f060a7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/dac_config.h @@ -0,0 +1,7 @@ +#ifndef _ADC_CONFIG_H +#define _ADC_CONFIG_H + +#define DAC_REF_SEL (0) +#define DAC_EXT_REF_GPIO (7) + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2c_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2c_config.h new file mode 100644 index 0000000000000000000000000000000000000000..323904097bf88d052e2296e930eed10d3c02d961 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2c_config.h @@ -0,0 +1,4 @@ +#ifndef _I2C_CONFIG_H +#define _I2C_CONFIG_H + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2s_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2s_config.h new file mode 100644 index 0000000000000000000000000000000000000000..e77913a70c182f82f0930883ffb1fca6794faff6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2s_config.h @@ -0,0 +1,11 @@ +#ifndef _I2S_CONFIG_H +#define _I2S_CONFIG_H + +#define I2S_ADUIO_PLL_DEFAULT AUDIO_PLL_12288000_HZ +#define I2S_DATA_ENDIAN I2S_DATA_ENDIAN_MSB +#define I2S_MONO_CHANNEL I2S_RX_MONO_MODE_LEFT_CHANNEL +#define I2S_LR_EXCHANGE DISABLE /*The position of L/R channel data within each entry is exchanged if enabled*/ +#define I2S_FS_INVERT DISABLE +#define I2S_BCLK_INVERT DISABLE + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/power_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/power_config.h new file mode 100644 index 0000000000000000000000000000000000000000..9330b74d6bb5178a3b0a3a5ff689d6b00cad83c9 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/power_config.h @@ -0,0 +1,17 @@ +#ifndef _POWER_CONFIG_H +#define _POWER_CONFIG_H + +#define DEAULT_LP_XTAL_TYPE GLB_DLL_XTAL_32M +#define DEFAULT_LP_LDO_LEVEL PDS_LDO_LEVEL_1P10V +#define DEFAULT_LP_PDS_AON_GPIO_WAKE_UP_SRC PDS_AON_WAKEUP_GPIO_10 +#define DEFAULT_LP_PDS_AON_GPIO_TRIG_TYPE PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE + +#define DEFAULT_LP_PDS_FLASH_POWER_DOWN 1 +#define DEFAULT_LP_PDS_HOLD_GPIO 0 +#define DEFAULT_LP_PDS_TURN_OFF_FLASH_PAD 1 +#define DEFAULT_LP_PDS_TURN_OFF_XTAL_32M 1 +#define DEFAULT_LP_PDS_TURN_OFF_DLL 1 +#define DEFAULT_LP_PDS_TURN_OFF_RF 1 +#define DEFAULT_LP_PDS_USE_XTAL_32K 0 + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/pwm_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/pwm_config.h new file mode 100644 index 0000000000000000000000000000000000000000..cfe936de0e06ab25f1ba3604e81cdcc7adcc1e64 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/pwm_config.h @@ -0,0 +1,6 @@ +#ifndef _PWM_CONFIG_H +#define _PWM_CONFIG_H + +#define PWM_STOP_MODE_SEL (PWM_STOP_GRACEFUL) + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/spi_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/spi_config.h new file mode 100644 index 0000000000000000000000000000000000000000..5794716e48c6ad1b29f86aeecb7a5d5d76ebc376 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/spi_config.h @@ -0,0 +1,8 @@ +#ifndef _SPI_CONFIG_H +#define _SPI_CONFIG_H + +#define SPI_DEGLITCH_ENABLE (0) +#define SPI_CONTINUE_TRANSFER_ENABLE (1) +#define SPI_SWAP_ENABLE (1) + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/timer_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/timer_config.h new file mode 100644 index 0000000000000000000000000000000000000000..1cc78c5f90dbb3085ccaae7bd2a3b944a3e141cf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/timer_config.h @@ -0,0 +1,6 @@ +#ifndef _TIMER_CONFIG_H +#define _TIMER_CONFIG_H + +#define TIMER_CLK_SRC (0) + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/uart_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/uart_config.h new file mode 100644 index 0000000000000000000000000000000000000000..ca55aa1fe2206a76ad6c9ca606fff537f3cc0289 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/uart_config.h @@ -0,0 +1,17 @@ +#ifndef _UART_CONFIG_H +#define _UART_CONFIG_H + +#define UART_CLOCK_SOURCE_96M_ENABLE (1) +#define UART_CTS_FLOWCONTROL_ENABLE (0) +#define UART_RTS_FLOWCONTROL_ENABLE (0) +#define UART_RX_DEGLITCH_ENABLE (0) +#define UART_MSB_FIRST_ENABLE (0) +#define UART_TX_SWCONTROL_ENABLE (0) +#define UART_TX_LINMODE_ENABLE (0) +#define UART_RX_LINMODE_ENABLE (0) +#define UART_TX_BREAKBIT_CNT (0) + +#define UART_FIFO_MAX_LEN 128 +#define UART_DEFAULT_RTO_TIMEOUT 100 + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/usb_config.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/usb_config.h new file mode 100644 index 0000000000000000000000000000000000000000..0cd9e8604ea38be6f75d5a842990024ace96b88f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/usb_config.h @@ -0,0 +1,10 @@ +#ifndef _USB_CONFIG_H +#define _USB_CONFIG_H + +//#define USE_EXTERNAL_TRANSCEIVER +#define USE_INTERNAL_TRANSCEIVER +#define ENABLE_LPM_INT +//#define ENABLE_SOF3MS_INT +//#define ENABLE_ERROR_INT + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_acomp.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_acomp.h new file mode 100644 index 0000000000000000000000000000000000000000..345878268a292fd5c259ecc0fd78d0d7ce6c2351 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_acomp.h @@ -0,0 +1,48 @@ +#ifndef __HAL_ACOMP_H__ +#define __HAL_ACOMP_H__ + +#include "drv_device.h" +#include "bl702_config.h" + +enum acomp_channel_type { + ACOMP_CHANNEL_ADC_CHANNEL0, /*!< Analog compare channel,ADC input channel 0 */ + ACOMP_CHANNEL_ADC_CHANNEL1, /*!< Analog compare channel,ADC input channel 1 */ + ACOMP_CHANNEL_ADC_CHANNEL2, /*!< Analog compare channel,ADC input channel 2 */ + ACOMP_CHANNEL_ADC_CHANNEL3, /*!< Analog compare channel,ADC input channel 3 */ + ACOMP_CHANNEL_ADC_CHANNEL4, /*!< Analog compare channel,ADC input channel 4 */ + ACOMP_CHANNEL_ADC_CHANNEL5, /*!< Analog compare channel,ADC input channel 5 */ + ACOMP_CHANNEL_ADC_CHANNEL6, /*!< Analog compare channel,ADC input channel 6 */ + ACOMP_CHANNEL_ADC_CHANNEL7, /*!< Analog compare channel,ADC input channel 7 */ + ACOMP_CHANNEL_DAC_CHANNELA, /*!< Analog compare channel,DAC output channel A */ + ACOMP_CHANNEL_DAC_CHANNELB, /*!< Analog compare channel,DAC output channel B */ + ACOMP_CHANNEL_VREF_1P2V, /*!< Analog compare channel,1.2V ref voltage */ + ACOMP_CHANNEL_0P375VBAT, /*!< Analog compare channel,6/16Vbat */ + ACOMP_CHANNEL_0P25VBAT, /*!< Analog compare channel,4/16Vbat */ + ACOMP_CHANNEL_0P1875VBAT, /*!< Analog compare channel,3/16Vbat */ + ACOMP_CHANNEL_0P3125VBAT, /*!< Analog compare channel,5/16Vbat */ + ACOMP_CHANNEL_VSS, /*!< Analog compare channel,vss */ +}; + +enum acomp_hysteresis_vol_type { + ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */ + ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */ + ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */ + ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */ + ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */ + ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */ + ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */ + ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */ +}; + +typedef struct acomp_device { + struct device parent; + uint8_t id; + enum acomp_channel_type pos_ch; + enum acomp_channel_type neg_ch; + enum acomp_hysteresis_vol_type pos_hysteresis_vol; + enum acomp_hysteresis_vol_type neg_hysteresis_vol; +} acomp_device_t; + +void acomp_init(acomp_device_t *device); +int acomp_get_result(acomp_device_t *device); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_adc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..67ea9c83d46cf93b90e9f865fd6ea5489e873d21 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_adc.h @@ -0,0 +1,175 @@ +/** + * @file hal_adc.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_ADC__H__ +#define __HAL_ADC__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define DEVICE_CTRL_ADC_CHANNEL_START 0x10 +#define DEVICE_CTRL_ADC_CHANNEL_STOP 0x11 +#define DEVICE_CTRL_ADC_CHANNEL_CONFIG 0x12 +#define DEVICE_CTRL_ADC_VBAT_ON 0x13 +#define DEVICE_CTRL_ADC_VBAT_OFF 0x14 +#define DEVICE_CTRL_ADC_TSEN_ON 0x15 +#define DEVICE_CTRL_ADC_TSEN_OFF 0x16 + +enum adc_index_type { +#ifdef BSP_USING_ADC0 + ADC0_INDEX, +#endif + ADC_MAX_INDEX +}; + +enum adc_event_type { + ADC_EVEN_INT_POS_SATURATION, + ADC_EVEN_INT_NEG_SATURATION, + ADC_EVENT_UNDERRUN, + ADC_EVENT_OVERRUN, + ADC_EVENT_REVERSED, + ADC_EVENT_FIFO_READY, + ADC_EVEN_MAX, +}; + +enum adc_it_type { + ADC_EVENT_FIFO_READY_IT = 1 << 0, + ADC_EVENT_OVERRUN_IT = 1 << 1, + ADC_EVENT_UNDERRUN_IT = 1 << 2, + ADC_EVEN_INT_POS_SATURATION_IT = 1 << 3, + ADC_EVEN_INT_NEG_SATURATION_IT = 1 << 4, +}; + +#define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL) +#define adc_channel_stop(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL) +#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list) + +typedef enum { + ADC_CHANNEL0, /* ADC channel 0 */ + ADC_CHANNEL1, /* ADC channel 1 */ + ADC_CHANNEL2, /* ADC channel 2 */ + ADC_CHANNEL3, /* ADC channel 3 */ + ADC_CHANNEL4, /* ADC channel 4 */ + ADC_CHANNEL5, /* ADC channel 5 */ + ADC_CHANNEL6, /* ADC channel 6 */ + ADC_CHANNEL7, /* ADC channel 7 */ + ADC_CHANNEL8, /* ADC channel 8 */ + ADC_CHANNEL9, /* ADC channel 9 */ + ADC_CHANNEL10, /* ADC channel 10 */ + ADC_CHANNEL11, /* ADC channel 11 */ + ADC_CHANNEL_DAC_OUTA, /* DACA, ADC channel 12 */ + ADC_CHANNEL_DAC_OUTB, /* DACB, ADC channel 13 */ + ADC_CHANNEL_TSEN_P, /* TSenp, ADC channel 14 */ + ADC_CHANNEL_TSEN_N, /* TSenn, ADC channel 15 */ + ADC_CHANNEL_VREF, /* Vref, ADC channel 16 */ + ADC_CHANNEL_DCTEST, /* DCTest, ADC channel 17 */ + ADC_CHANNEL_VABT_HALF, /* VBAT/2, ADC channel 18 */ + ADC_CHANNEL_SENP3, /* SenVP3, ADC channel 19 */ + ADC_CHANNEL_SENP2, /* SenVP2, ADC channel 20 */ + ADC_CHANNEL_SENP1, /* SenVP1, ADC channel 21 */ + ADC_CHANNEL_SENP0, /* SenVP0, ADC channel 22 */ + ADC_CHANNEL_GND, /* GND, ADC channel 23 */ +} adc_channel_t; + +typedef enum { + ADC_CLOCK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ + ADC_CLOCK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ + ADC_CLOCK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ + ADC_CLOCK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ + ADC_CLOCK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ + ADC_CLOCK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ + ADC_CLOCK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ + ADC_CLOCK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ +} adc_clk_div_t; + +typedef enum { + ADC_VREF_3V2 = 0, /* ADC select 3.2V as reference voltage */ + ADC_VREF_2V = 1, /* ADC select 2V as reference voltage */ +} adc_vref_t; + +/** + * @brief ADC data width type definition + */ +typedef enum { + ADC_DATA_WIDTH_12B, /*!< ADC 12 bits */ + ADC_DATA_WIDTH_14B_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ + ADC_DATA_WIDTH_16B_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */ + ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ + ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ +} adc_data_width_t; + +/** + * @brief ADC FIFO threshold type definition + */ +typedef enum { + ADC_FIFO_THRESHOLD_1BYTE, /*!< ADC FIFO threshold is 1 */ + ADC_FIFO_THRESHOLD_4BYTE, /*!< ADC FIFO threshold is 4 */ + ADC_FIFO_THRESHOLD_8BYTE, /*!< ADC FIFO threshold is 8 */ + ADC_FIFO_THRESHOLD_16BYTE, /*!< ADC FIFO threshold is 16 */ +} adc_fifo_threshold_t; + +/** + * @brief ADC PGA gain type definition + */ +typedef enum { + ADC_GAIN_NONE, /*!< No PGA gain */ + ADC_GAIN_1, /*!< PGA gain 1 */ + ADC_GAIN_2, /*!< PGA gain 2 */ + ADC_GAIN_4, /*!< PGA gain 4 */ + ADC_GAIN_8, /*!< PGA gain 8 */ + ADC_GAIN_16, /*!< PGA gain 16 */ + ADC_GAIN_32, /*!< PGA gain 32 */ +} adc_pga_gain_t; + +typedef struct +{ + uint8_t *pos_channel; + uint8_t *neg_channel; + uint8_t num; +} adc_channel_cfg_t; + +typedef struct +{ + int8_t posChan; /*!< Positive channel */ + int8_t negChan; /*!< Negative channel */ + uint16_t value; /*!< ADC value */ + float volt; /*!< ADC voltage result */ +} adc_channel_val_t; + +typedef struct adc_device { + struct device parent; + adc_clk_div_t clk_div; /* CLK is not more than 2Mhz */ + adc_vref_t vref; /* ADC voltage reference*/ + bool continuous_conv_mode; /** conversion mode: shot conversion mode or continuous conversion mode. */ + bool differential_mode; /** Channel type: single-ended or differential. */ + adc_data_width_t data_width; + adc_fifo_threshold_t fifo_threshold; + adc_pga_gain_t gain; +} adc_device_t; + +#define ADC_DEV(dev) ((adc_device_t *)dev) + +int adc_register(enum adc_index_type index, const char *name); +int adc_trim_tsen(uint16_t *tsen_offset); +float adc_get_tsen(uint16_t tsen_offset); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_boot2.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_boot2.h new file mode 100644 index 0000000000000000000000000000000000000000..b9c9e667553ce9403bd7eb005559756e956be86f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_boot2.h @@ -0,0 +1,113 @@ +/** + * ***************************************************************************** + * @file hal_boot2_custom.h + * @version 0.1 + * @date 2021-07-17 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __HAL_BOOT2_H__ +#define __HAL_BOOT2_H__ + +#include "drv_device.h" +#include "bl702_sflash.h" +#include "bl702_glb.h" + +#define HAL_EFUSE_CPU_MAX 2 +#define HAL_EFUSE_PK_HASH_SIZE 256 / 8 + +#define BL_TCM_BASE BL702_TCM_BASE +#define BL_SYS_CLK_PLL GLB_SYS_CLK_DLL144M +#define BL_SFLASH_CLK GLB_SFLASH_CLK_72M +#define HAL_PLL_CFG_MAGICCODE "PCFG" + +#define BL_FLASH_XIP_BASE BL702_FLASH_XIP_BASE +#define HAL_BOOT2_SUPPORT_DECOMPRESS 0 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_USB_IAP 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 0 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 1 /* 1 support decompress, 0 not support */ + + + +typedef struct +{ + uint8_t encrypted[HAL_EFUSE_CPU_MAX]; + uint8_t sign[HAL_EFUSE_CPU_MAX]; + uint8_t hbn_check_sign; + uint8_t rsvd[3]; + uint8_t chip_id[8]; + uint8_t pk_hash_cpu0[HAL_EFUSE_PK_HASH_SIZE]; + uint8_t pk_hash_cpu1[HAL_EFUSE_PK_HASH_SIZE]; +} boot2_efuse_hw_config; + +typedef struct +{ + uint8_t xtal_type; + uint8_t pll_clk; + uint8_t hclk_div; + uint8_t bclk_div; + + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t rsvd[2]; +} hal_sys_clk_config; + +typedef struct +{ + uint32_t magicCode; /*'PCFG'*/ + hal_sys_clk_config cfg; + uint32_t crc32; +} hal_pll_config; + +typedef struct +{ + uint32_t magicCode; /*'FCFG'*/ + SPI_Flash_Cfg_Type cfg; + uint32_t crc32; +} hal_flash_config; + +uint32_t hal_boot2_custom(void); +void hal_boot2_reset_sec_eng(void); +void hal_boot2_sw_system_reset(void); +void hal_boot2_set_psmode_status(uint32_t flag); +uint32_t hal_boot2_get_psmode_status(void); +uint32_t hal_boot2_get_user_fw(void); +void hal_boot2_clr_user_fw(void); +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg); +int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg); +void hal_boot2_sboot_finish(void); +void hal_boot2_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_init(void); +#if HAL_BOOT2_SUPPORT_USB_IAP +void hal_boot2_debug_usb_port_init(void); +#endif + +void hal_boot2_debug_uart_gpio_deinit(void); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_cam.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_cam.h new file mode 100644 index 0000000000000000000000000000000000000000..225dbb19b7290d2b9f3020c976ecd508ee5d1f0d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_cam.h @@ -0,0 +1,93 @@ +/** + * @file hal_cam.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __HAL_CAM_H__ +#define __HAL_CAM_H__ + +#include "drv_device.h" +#include "bl702_cam.h" +#include "bl702_config.h" + +#define DEVICE_OFLAG_INT 0x01 +#define DEVICE_OFLAG_POLL 0x02 + +enum camera_event_type { + CAM_EVENT_NORMAL_0, /*!< Interleave mode: normal write interrupt, planar mode:even byte normal write interrupt */ + CAM_EVENT_NORMAL_1, /*!< Interleave mode: no use, planar mode:odd byte normal write interrupt */ + CAM_EVENT_MEMORY_OVERWRITE_0, /*!< Interleave mode: memory overwrite interrupt, planar mode:even byte memory overwrite interrupt */ + CAM_EVENT_MEMORY_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte memory overwrite interrupt */ + CAM_EVENT_FRAME_OVERWRITE_0, /*!< Interleave mode: frame overwrite interrupt, planar mode:even byte frame overwrite interrupt */ + CAM_EVENT_FRAME_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte frame overwrite interrupt */ + CAM_EVENT_FIFO_OVERWRITE_0, /*!< Interleave mode: fifo overwrite interrupt, planar mode:even byte fifo overwrite interrupt */ + CAM_EVENT_FIFO_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte fifo overwrite interrupt */ + CAM_EVENT_VSYNC_CNT_ERROR, /*!< Vsync valid line count non-match interrupt */ + CAM_EVENT_HSYNC_CNT_ERROR, /*!< Hsync valid pixel count non-match interrupt */ + CAM_EVENT_ALL, /*!< All of interrupt */ +}; + +typedef enum { + CAM_AUTO_MODE, + CAM_MANUAL_MODE, +} cam_software_mode_t; + +typedef enum { + CAM_FRAME_PLANAR_MODE, + CAM_FRAME_INTERLEAVE_MODE, +} cam_frame_mode_t; + +typedef enum { + CAM_YUV_FORMAT_YUV422, + CAM_YUV_FORMAT_YUV420_EVEN, + CAM_YUV_FORMAT_YUV420_ODD, + CAM_YUV_FORMAT_YUV400_EVEN, + CAM_YUV_FORMAT_YUV400_ODD, +} cam_yuv_format_t; + +typedef struct cam_device { + struct device parent; + cam_software_mode_t software_mode; + cam_frame_mode_t frame_mode; + cam_yuv_format_t yuv_format; + uint32_t cam_write_ram_addr; + uint32_t cam_write_ram_size; + uint32_t cam_frame_size; + + // planar mode need use: + uint32_t cam_write_ram_addr1; + uint32_t cam_write_ram_size1; + uint32_t cam_frame_size1; +} cam_device_t; + +void cam_init(cam_device_t *cam_cfg, uint16_t oflag); +void cam_start(void); +void cam_stop(void); +uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len); +uint8_t cam_get_one_frame_planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, uint8_t **picUV, uint32_t *lenUV); +void cam_drop_one_frame_interleave(void); +void cam_drop_one_frame_planar(void); +void cam_hsync_crop(uint16_t start, uint16_t end); +void cam_vsync_crop(uint16_t start, uint16_t end); +void cam_hw_mode_wrap(uint8_t enbale); +void CAM_Int_Callback_set(CAM_INT_Type intType, intCallback_Type *cbFun); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_clock.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_clock.h new file mode 100644 index 0000000000000000000000000000000000000000..47f06d32997ef88bd775249910ac08ef902617e5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_clock.h @@ -0,0 +1,87 @@ +/** + * @file hal_clock.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_CLOCK__H__ +#define __HAL_CLOCK__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +/*XTAL_TYPE*/ +#define XTAL_NONE 0 +#define EXTERNAL_XTAL_32M 1 +#define INTERNAL_RC_32M 2 + +/*CLOCK_32K_XTAL*/ +#define EXTERNAL_XTAL_32K 0 +#define INTERNAL_RC_32K 1 + +/*BSP_ROOT_CLOCK_SOURCE*/ +#if XTAL_TYPE != EXTERNAL_XTAL_32M +#define ROOT_CLOCK_SOURCE_XCLK 0 +#else +#define ROOT_CLOCK_SOURCE_XCLK 1 +#endif +#define ROOT_CLOCK_SOURCE_PLL_57P6M 2 +#define ROOT_CLOCK_SOURCE_PLL_96M 3 +#define ROOT_CLOCK_SOURCE_PLL_144M 4 +/*BSP_XXX_CLOCK_SOURCE*/ +#define ROOT_CLOCK_SOURCE_32K_CLK 5 +#define ROOT_CLOCK_SOURCE_FCLK 6 +#define ROOT_CLOCK_SOURCE_BCLK 7 +#define ROOT_CLOCK_SOURCE_1K_CLK 8 + +/*BSP_AUDIO_PLL_CLOCK_SOURCE*/ +#define ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ 9 +#define ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ 10 +#define ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ 11 +#define ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ 12 +#define ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ 13 + +enum system_clock_type { + SYSTEM_CLOCK_ROOT_CLOCK = 0, /* clock source before fclk_div*/ + SYSTEM_CLOCK_FCLK, /* clock source after fclk_div*/ + SYSTEM_CLOCK_BCLK, /* clock source after bclk_div*/ + SYSTEM_CLOCK_XCLK, /* xtal clock*/ + SYSTEM_CLOCK_32K_CLK, + SYSTEM_CLOCK_AUPLL, +}; +enum peripheral_clock_type { + PERIPHERAL_CLOCK_UART = 0, + PERIPHERAL_CLOCK_SPI, + PERIPHERAL_CLOCK_I2C, + PERIPHERAL_CLOCK_ADC, + PERIPHERAL_CLOCK_DAC, + PERIPHERAL_CLOCK_I2S, + PERIPHERAL_CLOCK_PWM, + PERIPHERAL_CLOCK_CAM, + PERIPHERAL_CLOCK_TIMER0, + PERIPHERAL_CLOCK_TIMER1, +}; + +void system_clock_init(void); +void system_mtimer_clock_init(void); +void system_mtimer_clock_reinit(void); +void peripheral_clock_init(void); +uint32_t system_clock_get(enum system_clock_type type); +uint32_t peripheral_clock_get(enum peripheral_clock_type type); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dac.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..54defe3f5d58bc998e04e9d582c8a9bfc89bb134 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dac.h @@ -0,0 +1,68 @@ +/** + * @file hal_dac.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_DAC__H__ +#define __HAL_DAC__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +enum dac_index_type { +#ifdef BSP_USING_DAC0 + DAC0_INDEX, +#endif + DAC_MAX_INDEX +}; + +typedef struct +{ + uint8_t dac0; + uint8_t dac1; + uint8_t pin_num; +} dac_pin_t; + +typedef enum { + DAC_CHANNEL_0, + DAC_CHANNEL_1, + DAC_CHANNEL_ALL, +} dac_channel_t; + +typedef enum { + DAC_CLK_500KHZ, + DAC_CLK_44P1KHZ, + DAC_CLK_16KHZ, + DAC_CLK_8KHZ, +} dac_clk_t; + +typedef struct dac_device { + struct device parent; + dac_clk_t clk; + dac_pin_t pin; + + void *tx_dma; +} dac_device_t; + +#define DAC_DEV(dev) ((adc_device_t *)dev) + +int dac_register(enum dac_index_type index, const char *name); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..71ad7f6ab4cc698110c56af2d4d68ce65ba7859b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h @@ -0,0 +1,199 @@ +/** + * @file hal_dma.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_DMA__H__ +#define __HAL_DMA__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define DMA_CHANNEL_GET_STATUS 0x10 +#define DMA_CHANNEL_START 0x11 +#define DMA_CHANNEL_STOP 0x12 +#define DMA_CHANNEL_UPDATE 0x13 + +enum dma_index_type { +#ifdef BSP_USING_DMA0_CH0 + DMA0_CH0_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH1 + DMA0_CH1_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH2 + DMA0_CH2_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH3 + DMA0_CH3_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH4 + DMA0_CH4_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH5 + DMA0_CH5_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH6 + DMA0_CH6_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH7 + DMA0_CH7_INDEX, +#endif + DMA_MAX_INDEX +}; + +#define dma_channel_start(dev) device_control(dev, DMA_CHANNEL_START, NULL) +#define dma_channel_stop(dev) device_control(dev, DMA_CHANNEL_STOP, NULL) +#define dma_channel_update(dev, list) device_control(dev, DMA_CHANNEL_UPDATE, list) +#define dma_channel_check_busy(dev) device_control(dev, DMA_CHANNEL_GET_STATUS, NULL) + +#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88) +#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C) +#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88) +#define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C) +#define DMA_ADDR_I2C_TDR (0x4000A300 + 0x88) +#define DMA_ADDR_I2C_RDR (0x4000A300 + 0x8C) +#define DMA_ADDR_SPI_TDR (0x4000A200 + 0x88) +#define DMA_ADDR_SPI_RDR (0x4000A200 + 0x8C) +#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88) +#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C) +#define DMA_ADDR_ADC0_DR (0x40002000 + 0x04) +#define DMA_ADDR_ADC1_DR (0x40002000 + 0x04) +#define DMA_ADDR_DAC_TDR (0x40002048) + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE 1 /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0 /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE 1 /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0 /*!< Memory increment mode disable */ + +#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */ +#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */ +#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX */ +#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX */ +#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX */ +#define DMA_REQUEST_I2C0_RX 0x00000006 /*!< DMA request peripheral:I2C RX */ +#define DMA_REQUEST_I2C0_TX 0x00000007 /*!< DMA request peripheral:I2C TX */ +#define DMA_REQUEST_SPI0_RX 0x0000000A /*!< DMA request peripheral:SPI RX */ +#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI TX */ +#define DMA_REQUEST_I2S_RX 0x00000014 /*!< DMA request peripheral:I2S RX */ +#define DMA_REQUEST_I2S_TX 0x00000015 /*!< DMA request peripheral:I2S TX */ +#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:ADC0 */ +#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:DAC0 */ +#define DMA_REQUEST_USB_EP0 0x00000018 /*!< DMA request peripheral:USB EP0*/ +#define DMA_REQUEST_USB_EP1 0x00000019 /*!< DMA request peripheral:USB EP1*/ +#define DMA_REQUEST_USB_EP2 0x0000001A /*!< DMA request peripheral:USB EP2*/ +#define DMA_REQUEST_USB_EP3 0x0000001B /*!< DMA request peripheral:USB EP3*/ +#define DMA_REQUEST_USB_EP4 0x0000001C /*!< DMA request peripheral:USB EP4*/ +#define DMA_REQUEST_USB_EP5 0x0000001D /*!< DMA request peripheral:USB EP5*/ +#define DMA_REQUEST_USB_EP6 0x0000001E /*!< DMA request peripheral:USB EP6*/ +#define DMA_REQUEST_USB_EP7 0x0000001F /*!< DMA request peripheral:USB EP7 */ + +#define DMA_BURST_1BYTE 0 +#define DMA_BURST_4BYTE 1 +#define DMA_BURST_8BYTE 2 +#define DMA_BURST_16BYTE 3 + +#define DMA_TRANSFER_WIDTH_8BIT 0 +#define DMA_TRANSFER_WIDTH_16BIT 1 +#define DMA_TRANSFER_WIDTH_32BIT 2 + +#define DMA_LLI_ONCE_MODE 0 +#define DMA_LLI_CYCLE_MODE 1 + +/** + * @brief DMA transfer direction type definition + */ +typedef enum { + DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer tyep:memory to memory */ + DMA_MEMORY_TO_PERIPH, /*!< DMA transfer tyep:memory to peripheral */ + DMA_PERIPH_TO_MEMORY, /*!< DMA transfer tyep:peripheral to memory */ + DMA_PERIPH_TO_PERIPH, /*!< DMA transfer tyep:peripheral to peripheral */ +} dma_transfer_dir_type; + +typedef union { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } bits; + uint32_t WORD; +} dma_control_data_t; + +typedef struct +{ + uint32_t src_addr; + uint32_t dst_addr; + uint32_t nextlli; + dma_control_data_t cfg; +} dma_lli_ctrl_t; + +typedef struct +{ + uint8_t direction; + uint32_t src_req; + uint32_t dst_req; +} dma_ctrl_param_t; + +typedef struct dma_device { + struct device parent; + uint8_t id; + uint8_t ch; + uint8_t direction; + uint8_t transfer_mode; + uint32_t src_req; + uint32_t dst_req; + uint8_t src_burst_size; + uint8_t dst_burst_size; + uint8_t src_width; + uint8_t dst_width; + dma_lli_ctrl_t *lli_cfg; +} dma_device_t; + +#define DMA_DEV(dev) ((dma_device_t *)dev) + +int dma_register(enum dma_index_type index, const char *name); +int dma_allocate_register(const char *name); +int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_emac.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_emac.h new file mode 100644 index 0000000000000000000000000000000000000000..1163e99c655b4b9d80101afa886811b46f5b2259 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_emac.h @@ -0,0 +1,88 @@ +/** + * @file hal_emac.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __HAL_EMAC_H__ +#define __HAL_EMAC_H__ + +#include "drv_device.h" +#include "bl702_emac.h" +#include "bl702_config.h" + +typedef struct emac_device { + struct device parent; + uint8_t mac_addr[6]; /*!< mac address */ +} emac_device_t; + +/** + * @brief EMAC PHY configuration type definition + */ +typedef struct +{ + uint8_t auto_negotiation; /*!< Speed and mode auto negotiation */ + uint8_t full_duplex; /*!< Duplex mode */ +#define PHY_STATE_DOWN (0) /* PHY is not usable */ +#define PHY_STATE_READY (1) /* PHY is OK, wait for controller */ +#define PHY_STATE_UP (2) /* Network is ready for TX/RX */ +#define PHY_STATE_RUNNING (3) /* working */ +#define PHY_STATE_NOLINK (4) /* no cable connected */ +#define PHY_STATE_STOPPED (5) /* PHY has been stopped */ +#define PHY_STATE_TESTING (6) /* in test mode */ + uint8_t phy_state; /*!< down,ready,up,running,nolink,halted */ + uint16_t speed; /*!< Speed mode */ + uint16_t phy_address; /*!< PHY address */ + uint32_t phy_id; /*!< PHY OUI */ +} emac_phy_cfg_t; + +#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \ + EMAC_BD_FIELD_MSK(TX_IRQ) | \ + EMAC_BD_FIELD_MSK(TX_PAD) | \ + EMAC_BD_FIELD_MSK(TX_CRC)) + +#define EMAC_RX_COMMON_FLAGS (ETH_MAX_PACKET_SIZE << 16) | \ + EMAC_BD_FIELD_MSK(RX_IRQ) ) + +typedef enum _BD_TYPE_ { + EMAC_BD_TYPE_INVLAID, + EMAC_BD_TYPE_TX, + EMAC_BD_TYPE_RX, + EMAC_BD_TYPE_NONE, + EMAC_BD_TYPE_MAX = 0x7FFFFFFF +} EMAC_BD_TYPE_e; + +int emac_init(emac_device_t *emac_cfg); +int emac_bd_init(uint8_t *ethTxBuff, uint8_t txBufCount, uint8_t *ethRxBuff, uint8_t rxBufCount); +int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in); +int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out); +__WEAK void emac_rx_done_callback_app(void); +__WEAK void emac_rx_error_callback_app(void); +__WEAK void emac_rx_busy_callback_app(void); +__WEAK void emac_tx_error_callback_app(void); +__WEAK void emac_tx_done_callback_app(void); +int emac_phy_set_address(uint16_t phyAddress); +int emac_phy_config_full_duplex(uint8_t fullDuplex); +int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue); +int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue); +int emac_stop(void); +int emac_start(void); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_flash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..f67a9c124dc987aec77ec14820ed8c99de5f312b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_flash.h @@ -0,0 +1,41 @@ +/** + * @file hal_flash.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_FLASH__H__ +#define __HAL_FLASH__H__ + +#include "drv_device.h" + + +#define FLASH_NOT_DETECT 0x10 +#define BL_FLASH_XIP_BASE BL702_FLASH_XIP_BASE + +BL_Err_Type flash_init(void); +BL_Err_Type flash_read_jedec_id(uint8_t *data); +BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type flash_read(uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len); +BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset); +BL_Err_Type flash_get_cfg(uint8_t **cfg_addr,uint32_t *len); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..d849219420b1e3a40aaa8501b976a30ad35a15a1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h @@ -0,0 +1,86 @@ +/** + * @file hal_gpio.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_GPIO__H__ +#define __HAL_GPIO__H__ + +#include "drv_device.h" + +enum gpio_pin_type { + GPIO_PIN_0 = 0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, + GPIO_PIN_8, + GPIO_PIN_9, + GPIO_PIN_10, + GPIO_PIN_11, + GPIO_PIN_12, + GPIO_PIN_13, + GPIO_PIN_14, + GPIO_PIN_15, + GPIO_PIN_16, + GPIO_PIN_17, + GPIO_PIN_18, + GPIO_PIN_19, + GPIO_PIN_20, + GPIO_PIN_21, + GPIO_PIN_22, + GPIO_PIN_23, + GPIO_PIN_24, + GPIO_PIN_25, + GPIO_PIN_26, + GPIO_PIN_27, + GPIO_PIN_28, + GPIO_PIN_29, + GPIO_PIN_30, + GPIO_PIN_31, + GPIO_PIN_MAX, +}; + +#define GPIO_OUTPUT_MODE 0 +#define GPIO_OUTPUT_PP_MODE 1 +#define GPIO_OUTPUT_PD_MODE 2 +#define GPIO_INPUT_MODE 3 +#define GPIO_INPUT_PP_MODE 4 +#define GPIO_INPUT_PD_MODE 5 +#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6 +#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7 +#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8 +#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9 +#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10 +#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11 +#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 12 +#define GPIO_SYNC_LOW_LEVEL_INT_MODE 13 +#define GPIO_HZ_MODE 14 + +void gpio_set_mode(uint32_t pin, uint32_t mode); +void gpio_write(uint32_t pin, uint32_t value); +void gpio_toggle(uint32_t pin); +int gpio_read(uint32_t pin); +void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)); +void gpio_irq_enable(uint32_t pin, uint8_t enabled); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2c.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..9dd6ae1a36ce155cc85cac9ac848d041e3d32a5d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2c.h @@ -0,0 +1,67 @@ +/** + * @file hal_i2c.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_I2C__H__ +#define __HAL_I2C__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +enum i2c_index_type { +#ifdef BSP_USING_I2C0 + I2C0_INDEX, +#endif + I2C_MAX_INDEX +}; + +#define I2C_WR 0x0000 +#define I2C_RD 0x0001 +#define I2C_RW_MASK 0x0001 + +#define SUB_ADDR_0BYTE 0x0010 +#define SUB_ADDR_1BYTE 0x0020 +#define SUB_ADDR_2BYTE 0x0040 + +#define I2C_HW_MODE 0 +#define I2C_SW_MODE 1 + +typedef struct i2c_msg { + uint8_t slaveaddr; + uint32_t subaddr; + uint16_t flags; + uint16_t len; + uint8_t *buf; +} i2c_msg_t; + +typedef struct i2c_device { + struct device parent; + uint8_t id; + uint8_t mode; + uint32_t phase; +} i2c_device_t; + +#define I2C_DEV(dev) ((i2c_device_t *)dev) + +int i2c_register(enum i2c_index_type index, const char *name); +int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2s.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2s.h new file mode 100644 index 0000000000000000000000000000000000000000..ea0415bb7e07096eaf16e75fe40a655c6d1bcb38 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2s.h @@ -0,0 +1,114 @@ +/** + * @file hal_i2s.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_I2S__H__ +#define __HAL_I2S__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define I2S_GET_TX_FIFO_CMD 0x10 +#define I2S_GET_RX_FIFO_CMD 0x11 + +enum i2s_index_type { +#ifdef BSP_USING_I2S0 + I2S0_INDEX, +#endif + I2S_MAX_INDEX +}; + +#define I2S_DEFAULT_RTO_TIMEOUT 15 + +/*! + * @brief I2S mode type settings + * + * This enumeration defines the I2S mode type + */ +typedef enum { + I2S_MODE_STD, /*!< I2S STD Mode */ + I2S_MODE_LEFT, /*!< Left-Justified Mode */ + I2S_MODE_RIGHT, /*!< Right-Justified Mode */ + I2S_MODE_DSP_A, /*!< DSP/PCM Mode A*/ + I2S_MODE_DSP_B, /*!< DSP/PCM Mode B*/ +} interface_mode_t; + +/*! + * @brief I2S frame size settings + * + * This enumeration defines the frame size type + */ +typedef enum { + I2S_FRAME_LEN_8 = 1, /*!< I2S frame size 8 bits */ + I2S_FRAME_LEN_16 = 2, /*!< I2S frame size 16 bits */ + I2S_FRAME_LEN_24 = 3, /*!< I2S frame size 24 bits */ + I2S_FRAME_LEN_32 = 4, /*!< I2S frame size 32 bits */ +} i2s_frame_size_t; + +/*! + * @brief I2S data size settings + * + * This enumeration defines the data size type + */ +typedef enum { + I2S_DATA_LEN_8 = 1, /*!< I2S data size 8 bits */ + I2S_DATA_LEN_16 = 2, /*!< I2S data size 16 bits */ + I2S_DATA_LEN_24 = 3, /*!< I2S data size 24 bits */ + I2S_DATA_LEN_32 = 4, /*!< I2S data size 32 bits */ +} i2s_data_size_t; + +/*! + * @brief I2S frame channel settings + * + * This enumeration defines the frame channel mode type + */ +typedef enum { + I2S_FS_CHANNELS_NUM_MONO = 1, /*!< I2S frame is for 1 channels */ + I2S_FS_CHANNELS_NUM_2 = 2, /*!< I2S frame is for 2 channels */ + I2S_FS_CHANNELS_NUM_3 = 3, /*!< I2S frame is for 3 channels, DSP mode only, frame_size must equal data_size*/ + I2S_FS_CHANNELS_NUM_4 = 4, /*!< I2S frame is for 4 channels, DSP mode only, frame_size must equal data_size*/ +} i2s_channel_num_t; + +typedef enum { + I2S_MODE_MASTER = 0, /*!< I2S as master */ + I2S_MODE_SLAVE, /*!< I2S as slave */ +} i2s_mode_t; + +typedef struct i2s_device { + struct device parent; + uint8_t id; + + i2s_mode_t iis_mode; + interface_mode_t interface_mode; + uint32_t sampl_freq_hz; /*!< I2S sample data frequency in Hz */ + i2s_channel_num_t channel_num; + i2s_frame_size_t frame_size; + i2s_data_size_t data_size; + uint8_t fifo_threshold; /*!< I2S receive and transmit threshold*/ + void *tx_dma; + void *rx_dma; +} i2s_device_t; + +#define I2S_DEV(dev) ((i2s_device_t *)dev) + +int i2s_register(enum i2s_index_type index, const char *name); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_keyscan.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_keyscan.h new file mode 100644 index 0000000000000000000000000000000000000000..e65c3774fa187e493b1874fcaf5339bc7e6deea1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_keyscan.h @@ -0,0 +1,89 @@ +/** + * @file hal_keyscan.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_KEYSCAN__H__ +#define __HAL_KEYSCAN__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define DEVICE_CTRL_KEYSCAN_GET_KEYCODE 0x10 + +enum keyscan_index_type { +#ifdef BSP_USING_KEYSCAN + KEYSCAN_INDEX, +#endif + KEYSCAN_MAX_INDEX +}; + +enum col_num_type { + COL_NUM_1 = 1, + COL_NUM_2, + COL_NUM_3, + COL_NUM_4, + COL_NUM_5, + COL_NUM_6, + COL_NUM_7, + COL_NUM_8, + COL_NUM_9, + COL_NUM_10, + COL_NUM_11, + COL_NUM_12, + COL_NUM_13, + COL_NUM_14, + COL_NUM_15, + COL_NUM_16, + COL_NUM_17, + COL_NUM_18, + COL_NUM_19, + COL_NUM_20 +}; + +enum row_num_type { + ROW_NUM_1 = 1, + ROW_NUM_2, + ROW_NUM_3, + ROW_NUM_4, + ROW_NUM_5, + ROW_NUM_6, + ROW_NUM_7, + ROW_NUM_8, +}; + +enum keyscan_event_type { + KEYSCAN_EVENT_TRIG, + KEYSCAN_EVENT_UNKNOWN +}; + +typedef struct keyscan_device { + struct device parent; + enum col_num_type col_num; + enum row_num_type row_num; + uint8_t deglitch_count; + +} keyscan_device_t; + +#define KEYSCAN_DEV(dev) ((keyscan_device_t *)dev) + +int keyscan_register(enum keyscan_index_type index, const char *name); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h new file mode 100644 index 0000000000000000000000000000000000000000..7cccd41eccbe46f2b4ef5093b21e75b677076e9f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h @@ -0,0 +1,69 @@ +/** + * @file hal_mjpeg.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_MJPEG__H__ +#define __HAL_MJPEG__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define MJPEG_PACKET_ADD_NONE 0 +#define MJPEG_PACKET_ADD_DEFAULT 1 << 0 +#define MJPEG_PACKET_ADD_FRAME_HEAD 1 << 1 +#define MJPEG_PACKET_ADD_FRAME_TAIL 1 << 2 +#define MJPEG_PACKET_ADD_END_TAIL 1 << 3 + +/** + * @brief MJPEG YUV format definition + */ +typedef enum { + MJPEG_YUV_FORMAT_YUV420, /*!< MJPEG YUV420 planar mode */ + MJPEG_YUV_FORMAT_YUV400, /*!< MJPEG YUV400 grey scale mode */ + MJPEG_YUV_FORMAT_YUV422_PLANAR, /*!< MJPEG YUV422 planar mode */ + MJPEG_YUV_FORMAT_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */ +} mjpeg_yuv_format_t; + +typedef struct mjpeg_device { + struct device parent; + uint8_t quality; + mjpeg_yuv_format_t yuv_format; + uint32_t write_buffer_addr; /*!< MJPEG buffer addr */ + uint32_t write_buffer_size; /*!< MJPEG buffer size */ + uint32_t read_buffer_addr; + uint32_t read_buffer_size; + uint16_t resolution_x; /*!< CAM RESOLUTION X */ + uint16_t resolution_y; /*!< CAM RESOLUTION Y */ + + uint8_t packet_cut_mode; + uint16_t frame_head_length; + uint16_t packet_head_length; + uint16_t packet_body_length; + uint16_t packet_tail_length; +} mjpeg_device_t; + +void mjpeg_init(mjpeg_device_t *mjpeg_cfg); +void mjpeg_start(void); +void mjpeg_stop(void); +uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q); +void mjpeg_drop_one_frame(void); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h new file mode 100644 index 0000000000000000000000000000000000000000..bd73f93fba4833487ce826ecf171df44bb88fe81 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h @@ -0,0 +1,33 @@ +/** + * @file hal_mtimer.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_MTIMER__H__ +#define __HAL_MTIMER__H__ + +#include "stdint.h" + +void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)); +uint64_t mtimer_get_time_ms(); +uint64_t mtimer_get_time_us(); +void mtimer_delay_ms(uint32_t time); +void mtimer_delay_us(uint32_t time); +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm.h new file mode 100644 index 0000000000000000000000000000000000000000..a625cd7943f1d3f6f155ed545b05b16a877da5b5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm.h @@ -0,0 +1,66 @@ +/** + * @file hal_pm.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_PM__H__ +#define __HAL_PM__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +enum pm_pds_sleep_level { + PM_PDS_LEVEL_0, + PM_PDS_LEVEL_1, + PM_PDS_LEVEL_2, + PM_PDS_LEVEL_3, + PM_PDS_LEVEL_4, /*do not recommend to use*/ + PM_PDS_LEVEL_5, /*do not recommend to use*/ + PM_PDS_LEVEL_6, /*do not recommend to use*/ + PM_PDS_LEVEL_7, /*do not recommend to use*/ + PM_PDS_LEVEL_31, +}; + +enum pm_hbn_sleep_level { + PM_HBN_LEVEL_0, + PM_HBN_LEVEL_1, + PM_HBN_LEVEL_2, +}; + +enum pm_event_type { + PM_HBN_GPIO9_WAKEUP_EVENT, + PM_HBN_GPIO10_WAKEUP_EVENT, + PM_HBN_GPIO11_WAKEUP_EVENT, + PM_HBN_GPIO12_WAKEUP_EVENT, + PM_HBN_RTC_WAKEUP_EVENT, + PM_HBN_ACOMP0_WAKEUP_EVENT, + PM_HBN_ACOMP1_WAKEUP_EVENT, +}; + +void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint8_t sleep_time); +void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time); +void pm_hbn_set_wakeup_callback(void (*wakeup_callback)(void)); +void pm_hbn_enter_again(bool reset); +void pm_hbn_out0_irq_register(void); +void pm_hbn_out1_irq_register(void); +void pm_irq_callback(enum pm_event_type event); +uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_power.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_power.h new file mode 100644 index 0000000000000000000000000000000000000000..31e192adbe3663f1fd66158f2e625d1162698d96 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_power.h @@ -0,0 +1,57 @@ +/** + * @file hal_power.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_POWER__H__ +#define __HAL_POWER__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +typedef enum { + CLOCK_AHB_UART0_GATE = 0x10, + CLOCK_AHB_UART1_GATE = 0x11, + CLOCK_AHB_SPI_GATE = 0x12, + CLOCK_AHB_I2C_GATE = 0x13, + CLOCK_AHB_PWM_GATE = 0x14, + CLOCK_AHB_TMR_GATE = 0x15, + CLOCK_AHB_IRR_GATE = 0x16, + CLOCK_AHB_CKS_GATE = 0x17, + CLOCK_AHB_QDEC_GATE = 0x18, + CLOCK_AHB_KYS_GATE = 0x19, + CLOCK_AHB_I2S_GATE = 0x1A, + CLOCK_AHB_USB_GATE = 0x1C, + CLOCK_AHB_CAM_GATE = 0x1D, + CLOCK_AHB_MJPEG_GATE = 0x1E, + CLOCK_AHB_ALL = 0x1F, +} Clock_Gate_Type; + +int lp_set_clock_gate(uint8_t enable, Clock_Gate_Type clockType); +void lp_set_all_gpio_hz(void); +void lp_power_off_dll(void); + +int hbn_set_wakeup_addr(uint32_t addr); +int hbn_set_status_flag(uint32_t flag); +int lp_enter_wfi(void); +int lp_enter_pds(uint32_t sleep_time, void (*preCbFun)(void), void (*postCbFun)(void)); +int lp_enter_hbn(uint32_t sleepTime, uint8_t hbn_level); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pwm.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..545b65eca8e7f45067f06b9b42c3f6d25480f89a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pwm.h @@ -0,0 +1,83 @@ +/** + * @file hal_pwm.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_PWM__H__ +#define __HAL_PWM__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define DEVICE_CTRL_PWM_FREQUENCE_CONFIG 0x10 +#define DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG 0x11 +#define DEVICE_CTRL_PWM_IT_PULSE_COUNT_CONFIG 0x12 + +enum pwm_index_type { +#ifdef BSP_USING_PWM_CH0 + PWM_CH0_INDEX, +#endif +#ifdef BSP_USING_PWM_CH1 + PWM_CH1_INDEX, +#endif +#ifdef BSP_USING_PWM_CH2 + PWM_CH2_INDEX, +#endif +#ifdef BSP_USING_PWM_CH3 + PWM_CH3_INDEX, +#endif +#ifdef BSP_USING_PWM_CH4 + PWM_CH4_INDEX, +#endif + PWM_MAX_INDEX +}; + +#define pwm_channel_start(dev) device_control(dev, DEVICE_CTRL_RESUME, NULL) +#define pwm_channel_stop(dev) device_control(dev, DEVICE_CTRL_SUSPEND, NULL) +#define pwm_channel_freq_update(dev, count) device_control(dev, DEIVCE_CTRL_PWM_FREQUENCE_CONFIG, (void *)count) +#define pwm_channel_dutycycle_update(dev, cfg) device_control(dev, DEIVCE_CTRL_PWM_DUTYCYCLE_CONFIG, cfg) +#define pwm_it_pulse_count_update(dev, count) device_control(dev, DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG, (void *)count) + +enum pwm_event_type { + PWM_EVENT_COMPLETE, +}; + +typedef struct +{ + uint16_t threshold_low; + uint16_t threshold_high; +} pwm_dutycycle_config_t; + +typedef struct pwm_device { + struct device parent; + uint8_t ch; + uint8_t polarity_invert_mode; + uint16_t period; + uint16_t threshold_low; + uint16_t threshold_high; + uint16_t it_pulse_count; + +} pwm_device_t; + +#define PWM_DEV(dev) ((pwm_device_t *)dev) + +int pwm_register(enum pwm_index_type index, const char *name); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_qdec.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_qdec.h new file mode 100644 index 0000000000000000000000000000000000000000..8f2f256b60caf67b7b7e2fd4098e5ece82d3babe --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_qdec.h @@ -0,0 +1,76 @@ +/** + * @file hal_qdec.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __HAL_QDEC__H__ +#define __HAL_QDEC__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define DEVICE_CTRL_GET_SAMPLE_VAL (0x10) +#define DEVICE_CTRL_GET_SAMPLE_DIR (0x11) +#define DEVICE_CTRL_GET_ERROR_CNT (0x12) + +enum qdec_index_type { +#ifdef BSP_USING_QDEC0 + QDEC0_INDEX, +#endif +#ifdef BSP_USING_QDEC1 + QDEC1_INDEX, +#endif +#ifdef BSP_USING_QDEC2 + QDEC2_INDEX, +#endif + QDEC_MAX_INDEX, +}; + +enum qdec_event_type { + QDEC_REPORT_EVENT = 1 << 0, /*!< report interrupt */ + QDEC_SAMPLE_EVENT = 1 << 1, /*!< sample interrupt */ + QDEC_ERROR_EVENT = 1 << 2, /*!< error interrupt */ + QDEC_OVERFLOW_EVENT = 1 << 3, /*!< ACC1 and ACC2 overflow interrupt */ + QDEC_ALL_EVENT = 1 << 4, /*!< interrupt max num */ +}; + +typedef struct qdec_device { + struct device parent; + uint8_t id; + + uint8_t acc_mode; + uint8_t sample_mode; + uint8_t sample_period; + uint8_t report_mode; + uint32_t report_period; + uint8_t led_en; + uint8_t led_swap; + uint16_t led_period; + uint8_t deglitch_en; + uint8_t deglitch_strength; + +} qdec_device_t; + +#define QDEC_DEV(dev) ((qdec_device_t *)dev) + +int qdec_register(enum qdec_index_type index, const char *name); + +#endif // __HAL_QDEC_H__ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_rtc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..4f00f38eba694c3cec82c5ed110fbaf764f72d29 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_rtc.h @@ -0,0 +1,33 @@ +/** + * @file hal_rtc.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_RTC__H__ +#define __HAL_RTC__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +void rtc_init(uint64_t sleep_time); +void rtc_set_timestamp(uint64_t time_stamp); +uint64_t rtc_get_timestamp(void); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..0a66f6e301e2622795df7bd97e770af2c5d63264 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h @@ -0,0 +1,57 @@ +/** + * @file hal_sec_aes.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_AES__H__ +#define __HAL_SEC_AES__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +typedef enum { + SEC_ASE_CBC, + SEC_ASE_CTR, + SEC_ASE_ECB +} sec_aes_type; + +typedef enum { + SEC_ASE_KEY_128, + SEC_ASE_KEY_256, + SEC_ASE_KEY_192 +} sec_aes_key_type; + +typedef struct sec_aes_handle_t { + sec_aes_type aes_type; + sec_aes_key_type key_type; +} sec_aes_handle_t; + +typedef enum { + SEC_AES_DIR_ENCRYPT, + SEC_AES_DIR_DECRYPT +} sec_aes_dir_type; + +int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type); +int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir); +int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out); +int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out); +int sec_aes_deinit(sec_aes_handle_t *handle); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h new file mode 100644 index 0000000000000000000000000000000000000000..82bf591e441084f57fafe0ba5c14f0e0eec37056 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h @@ -0,0 +1,58 @@ +/** + * @file hal_sec_dsa.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_DSA__H__ +#define __HAL_SEC_DSA__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +typedef struct sec_dsa_crt_cfg_tag { + uint32_t *dP; + uint32_t *dQ; + uint32_t *qInv; + uint32_t *p; + uint32_t *invR_p; + uint32_t *primeN_p; + uint32_t *q; + uint32_t *invR_q; + uint32_t *primeN_q; +} sec_dsa_crt_cfg_t; + +typedef struct +{ + uint32_t size; + uint32_t crtSize; + uint32_t *n; + uint32_t *e; + uint32_t *d; + sec_dsa_crt_cfg_t crtCfg; +} sec_dsa_handle_t; + +int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size); +int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r); +int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r); +int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r); +int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s); +int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h new file mode 100644 index 0000000000000000000000000000000000000000..d8e1f987cc5290b5516c2cd847a43db5b80e541e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h @@ -0,0 +1,62 @@ +/** + * @file hal_sec_ecdsa.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_ECDSA__H__ +#define __HAL_SEC_ECDSA__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +typedef enum { + ECP_SECP256R1 = 0, +} sec_ecp_type; + +typedef struct +{ + sec_ecp_type ecpId; + uint32_t *privateKey; + uint32_t *publicKeyx; + uint32_t *publicKeyy; +} sec_ecdsa_handle_t; + +typedef struct +{ + sec_ecp_type ecpId; +} sec_ecdh_handle_t; + +int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id); +int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle); +int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s); +int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s); +int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key); +int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); + +int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id); +int sec_ecdh_deinit(sec_ecdh_handle_t *handle); +int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); +int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); +int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size); +int sec_eng_trng_enable(void); +void sec_eng_trng_disable(void); +int sec_eng_trng_read(uint8_t data[32]); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h new file mode 100644 index 0000000000000000000000000000000000000000..6617720972e6ee512daadcd3219790697bf945cf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h @@ -0,0 +1,53 @@ +/** + * @file hal_sec_hash.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_HASH__H__ +#define __HAL_SEC_HASH__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +enum sec_hash_index_type { + SEC_HASH0_INDEX, + SEC_HASH_MAX_INDEX +}; + +enum sec_hash_type { + SEC_HASH_SHA1, + SEC_HASH_SHA224, + SEC_HASH_SHA256, + SEC_HASH_SHA384, + SEC_HASH_SHA512, + SEC_HASH_UNKNOWN +}; + +typedef struct sec_hash_device { + struct device parent; + uint32_t shaBuf[64 / 4]; /*!< Data not processed but in this temp buffer */ + uint32_t shaPadding[64 / 4]; /*!< Padding data */ + uint8_t type; /*!< Sha has feed data */ +} sec_hash_device_t; + +int sec_hash_register(enum sec_hash_index_type index, const char *name); +int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_spi.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..5a858e3555c97d6bf56d7f1b8a5cc984c04c2eb5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_spi.h @@ -0,0 +1,105 @@ +/** + * @file hal_spi.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SPI__H__ +#define __HAL_SPI__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define DEVICE_CTRL_SPI_CONFIG_CLOCK 0x10 + +enum spi_index_type { +#ifdef BSP_USING_SPI0 + SPI0_INDEX, +#endif + SPI_MAX_INDEX +}; + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_LSB_BYTE0_DIRECTION_FIRST 0 +#define SPI_LSB_BYTE3_DIRECTION_FIRST 1 +#define SPI_MSB_BYTE0_DIRECTION_FIRST 2 +#define SPI_MSB_BYTE3_DIRECTION_FIRST 3 + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_8BIT 0 +#define SPI_DATASIZE_16BIT 1 +#define SPI_DATASIZE_24BIT 2 +#define SPI_DATASIZE_32BIT 3 + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW 0 +#define SPI_POLARITY_HIGH 1 + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE 0 +#define SPI_PHASE_2EDGE 1 + +/** @defgroup + * @{ + */ +#define SPI_SLVAE_MODE 0 +#define SPI_MASTER_MODE 1 + +#define SPI_TRANSFER_TYPE_8BIT 0 +#define SPI_TRANSFER_TYPE_16BIT 1 +#define SPI_TRANSFER_TPYE_24BIT 2 +#define SPI_TRANSFER_TYPE_32BIT 3 + +enum spi_event_type { + SPI_EVENT_TX_FIFO, + SPI_EVENT_RX_FIFO, + SPI_EVENT_UNKNOWN +}; + +typedef struct spi_device { + struct device parent; + uint8_t id; + uint32_t clk; + uint8_t mode; + uint8_t direction; + uint8_t clk_polaraity; + uint8_t clk_phase; + uint8_t datasize; + uint8_t fifo_threshold; + void *tx_dma; + void *rx_dma; +} spi_device_t; + +#define SPI_DEV(dev) ((spi_device_t *)dev) + +int spi_register(enum spi_index_type index, const char *name); + +int spi_transmit(struct device *dev, void *buffer, uint32_t size, uint8_t type); +int spi_receive(struct device *dev, void *buffer, uint32_t size, uint8_t type); +int spi_transmit_receive(struct device *dev, const void *send_buf, void *recv_buf, uint32_t length, uint8_t type); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_timer.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..bf64a8fbd383936c896379643d6cce45c103beb8 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_timer.h @@ -0,0 +1,90 @@ +/** + * @file hal_timer.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_TIMER__H__ +#define __HAL_TIMER__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +enum timer_index_type { +#ifdef BSP_USING_TIMER0 + TIMER0_INDEX, +#endif +#ifdef BSP_USING_TIMER1 + TIMER1_INDEX, +#endif + TIMER_MAX_INDEX +}; + +enum timer_preload_trigger_type { + TIMER_PRELOAD_TRIGGER_NONE, + TIMER_PRELOAD_TRIGGER_COMP0, + TIMER_PRELOAD_TRIGGER_COMP1, + TIMER_PRELOAD_TRIGGER_COMP2, +}; + +enum timer_cnt_mode_type { + TIMER_CNT_PRELOAD, + TIMER_CNT_FREERUN, +}; + +enum timer_compare_id_type { + TIMER_COMPARE_ID_0, + TIMER_COMPARE_ID_1, + TIMER_COMPARE_ID_2, +}; + +enum timer_it_type { + TIMER_COMP0_IT = 1 << 0, + TIMER_COMP1_IT = 1 << 1, + TIMER_COMP2_IT = 1 << 2, +}; + +enum timer_event_type { + TIMER_EVENT_COMP0, + TIMER_EVENT_COMP1, + TIMER_EVENT_COMP2, + TIMER_EVENT_UNKNOWN +}; + +typedef struct timer_timeout_cfg { + enum timer_compare_id_type timeout_id; + uint32_t timeout_val; +} timer_timeout_cfg_t; + +typedef struct timer_device { + struct device parent; + uint8_t id; + enum timer_cnt_mode_type cnt_mode; + enum timer_preload_trigger_type trigger; + uint32_t reload; + uint32_t timeout1; + uint32_t timeout2; + uint32_t timeout3; +} timer_device_t; + +#define TIMER_DEV(dev) ((timer_device_t *)dev) + +int timer_register(enum timer_index_type index, const char *name); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_uart.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..cf4350dc68d013b53b83e318f707ae71e7d39db3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_uart.h @@ -0,0 +1,124 @@ +/** + * @file hal_uart.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_UART__H__ +#define __HAL_UART__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define UART_FIFO_LEN 128 + +#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10 +#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11 + +enum uart_index_type { +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif + UART_MAX_INDEX +}; + +/*! + * @brief UART data length settings + * + * This enumeration defines the UART data lengths. + */ +typedef enum { + UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */ + UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */ + UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */ + UART_DATA_LEN_8 = 3 /*!< Data length is 8 bits */ +} uart_databits_t; + +/*! + * @brief UART stop bit settings + * + * This enumeration defines the UART stop bits. + */ +typedef enum { + UART_STOP_ZERO_D_FIVE = 0, /*!< 0.5 stop bit */ + UART_STOP_ONE = 1, /*!< 1 stop bit */ + UART_STOP_ONE_D_FIVE = 2, /*!< 1.5 stop bit */ + UART_STOP_TWO = 3 /*!< 2 stop bits */ +} uart_stopbits_t; + +/*! + * @brief UART parity type settings + * + * This enumeration defines the UART parity types. + */ +typedef enum { + UART_PAR_NONE = 0, /*!< No parity */ + UART_PAR_ODD = 1, /*!< Parity bit is odd */ + UART_PAR_EVEN = 2, /*!< Parity bit is even */ +} uart_parity_t; + +enum uart_event_type { + UART_EVENT_TX_END, + UART_EVENT_TX_FIFO, + UART_EVENT_RX_END, + UART_EVENT_RX_FIFO, + UART_EVENT_RTO, + UART_EVENT_UNKNOWN +}; + +enum uart_it_type { + UART_TX_END_IT = 1 << 0, + UART_RX_END_IT = 1 << 1, + UART_TX_FIFO_IT = 1 << 2, + UART_RX_FIFO_IT = 1 << 3, + UART_RTO_IT = 1 << 4, + UART_PCE_IT = 1 << 5, + UART_TX_FER_IT = 1 << 6, + UART_RX_FER_IT = 1 << 7, + UART_ALL_IT = 1 << 8 +}; + +typedef struct +{ + uint32_t baudrate; + uart_databits_t databits; + uart_stopbits_t stopbits; + uart_parity_t parity; +} uart_param_cfg_t; + +typedef struct uart_device { + struct device parent; + uint8_t id; + uint32_t baudrate; + uart_databits_t databits; + uart_stopbits_t stopbits; + uart_parity_t parity; + uint8_t fifo_threshold; + void *tx_dma; + void *rx_dma; +} uart_device_t; + +#define UART_DEV(dev) ((uart_device_t *)dev) + +int uart_register(enum uart_index_type index, const char *name); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_usb.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_usb.h new file mode 100644 index 0000000000000000000000000000000000000000..43815f5c3f629d49d2f789145d5ba5ffb1f2f63f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_usb.h @@ -0,0 +1,219 @@ +/** + * @file hal_usb.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_USB__H__ +#define __HAL_USB__H__ + +#include "drv_device.h" +#include "ring_buffer.h" +#include "bl702_config.h" + +#define DEVICE_CTRL_USB_DC_SET_ACK 0X10 +#define DEVICE_CTRL_USB_DC_ENUM_ON 0X11 +#define DEVICE_CTRL_USB_DC_ENUM_OFF 0X12 +#define DEVICE_CTRL_USB_DC_GET_EP_TX_FIFO_CNT 0x13 +#define DEVICE_CTRL_USB_DC_GET_EP_RX_FIFO_CNT 0x14 +#define DEVICE_CTRL_USB_DC_SET_TX_DMA 0x15 +#define DEVICE_CTRL_USB_DC_SET_RX_DMA 0x16 + +enum usb_index_type { +#ifdef BSP_USING_USB + USB_INDEX, +#endif + USB_MAX_INDEX +}; + +/** + * USB endpoint Transfer Type mask. + */ +#define USBD_EP_TYPE_CTRL 0 +#define USBD_EP_TYPE_ISOC 1 +#define USBD_EP_TYPE_BULK 2 +#define USBD_EP_TYPE_INTR 3 +#define USBD_EP_TYPE_MASK 3 + +/** + * USB endpoint direction and number. + */ +#define USB_EP_DIR_MASK 0x80U +#define USB_EP_DIR_IN 0x80U +#define USB_EP_DIR_OUT 0x00U + +#define USB_EP_OUT_MSK 0x7FU +#define USB_EP_IN_MSK 0x80U + +/** Get endpoint index (number) from endpoint address */ +#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) +/** Get direction from endpoint address */ +#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) +/** Get endpoint address from endpoint index and direction */ +#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) +/** True if the endpoint is an IN endpoint */ +#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) +/** True if the endpoint is an OUT endpoint */ +#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) + +#define USB_SET_EP_OUT(ep) (ep & USB_EP_OUT_MSK) +#define USB_SET_EP_IN(ep) (ep | USB_EP_IN_MSK) + +#define USB_OUT_EP_NUM 8 +#define USB_IN_EP_NUM 8 + +#define USB_CTRL_EP_MPS 64 /**< maximum packet size (MPS) for EP 0 */ +#define USB_FS_MAX_PACKET_SIZE 64 /**< full speed MPS for bulk EP */ + +/* Default USB control EP, always 0 and 0x80 */ +#define USB_CONTROL_OUT_EP0 0 +#define USB_CONTROL_IN_EP0 0x80 + +#define USB_DC_EP_TYPE_CTRL 0x5 /*0*/ +#define USB_DC_EP_TYPE_ISOC 0x2 /*1*/ +#define USB_DC_EP_TYPE_BULK 0x4 /*2*/ +#define USB_DC_EP_TYPE_INTR 0x0 /*3*/ + +#define USB_DC_EP1_IN_DR (0x4000D800 + 0x118) +#define USB_DC_EP1_OUT_DR (0x4000D800 + 0x11c) +#define USB_DC_EP2_IN_DR (0x4000D800 + 0x128) +#define USB_DC_EP2_OUT_DR (0x4000D800 + 0x12c) +#define USB_DC_EP3_IN_DR (0x4000D800 + 0x138) +#define USB_DC_EP3_OUT_DR (0x4000D800 + 0x13c) +#define USB_DC_EP4_IN_DR (0x4000D800 + 0x148) +#define USB_DC_EP4_OUT_DR (0x4000D800 + 0x14c) +#define USB_DC_EP5_IN_DR (0x4000D800 + 0x158) +#define USB_DC_EP5_OUT_DR (0x4000D800 + 0x15c) +#define USB_DC_EP6_IN_DR (0x4000D800 + 0x168) +#define USB_DC_EP6_OUT_DR (0x4000D800 + 0x16c) +#define USB_DC_EP7_IN_DR (0x4000D800 + 0x178) +#define USB_DC_EP7_OUT_DR (0x4000D800 + 0x17c) + +enum usb_dc_event_type { + /** USB error reported by the controller */ + USB_DC_EVENT_ERROR, + /** USB reset */ + USB_DC_EVENT_RESET, + /** Start of Frame received */ + USB_DC_EVENT_SOF, + /** USB connection established, hardware enumeration is completed */ + USB_DC_EVENT_CONNECTED, + /** USB configuration done */ + USB_DC_EVENT_CONFIGURED, + /** USB connection suspended by the HOST */ + USB_DC_EVENT_SUSPEND, + /** USB connection lost */ + USB_DC_EVENT_DISCONNECTED, + /** USB connection resumed by the HOST */ + USB_DC_EVENT_RESUME, + + /** setup packet received */ + USB_DC_EVENT_SETUP_NOTIFY, + /** ep0 in packet received */ + USB_DC_EVENT_EP0_IN_NOTIFY, + /** ep0 out packet received */ + USB_DC_EVENT_EP0_OUT_NOTIFY, + /** ep in packet except ep0 received */ + USB_DC_EVENT_EP_IN_NOTIFY, + /** ep out packet except ep0 received */ + USB_DC_EVENT_EP_OUT_NOTIFY, + /** Initial USB connection status */ + USB_DC_EVENT_UNKNOWN +}; + +enum usb_dc_ep_it_type { + USB_SOF_IT = 1 << 0, + USB_EP1_DATA_IN_IT = 1 << 10, + USB_EP1_DATA_OUT_IT = 1 << 11, + USB_EP2_DATA_IN_IT = 1 << 12, + USB_EP2_DATA_OUT_IT = 1 << 13, + USB_EP3_DATA_IN_IT = 1 << 14, + USB_EP3_DATA_OUT_IT = 1 << 15, + USB_EP4_DATA_IN_IT = 1 << 16, + USB_EP4_DATA_OUT_IT = 1 << 17, + USB_EP5_DATA_IN_IT = 1 << 18, + USB_EP5_DATA_OUT_IT = 1 << 19, + USB_EP6_DATA_IN_IT = 1 << 20, + USB_EP6_DATA_OUT_IT = 1 << 21, + USB_EP7_DATA_IN_IT = 1 << 22, + USB_EP7_DATA_OUT_IT = 1 << 23, +}; + +enum usb_error_type { + USB_DC_OK = 0, + USB_DC_EP_DIR_ERR = 1, + USB_DC_EP_EN_ERR = 2, + USB_DC_EP_TIMEOUT_ERR = 3, + USB_DC_ADDR_ERR = 4, + USB_DC_RB_SIZE_SMALL_ERR = 5, + USB_DC_ZLP_ERR = 6, +}; +/** + * @brief USB Endpoint Configuration. + * + * Structure containing the USB endpoint configuration. + */ +struct usb_dc_ep_cfg { + /** The number associated with the EP in the device + * configuration structure + * IN EP = 0x80 | \ + * OUT EP = 0x00 | \ + */ + uint8_t ep_addr; + /** Endpoint max packet size */ + uint16_t ep_mps; + /** Endpoint Transfer Type. + * May be Bulk, Interrupt, Control or Isochronous + */ + uint8_t ep_type; +}; + +/* + * USB endpoint structure. + */ +typedef struct +{ + uint8_t ep_ena; + uint32_t is_stalled; + struct usb_dc_ep_cfg ep_cfg; +} usb_dc_ep_state_t; + +typedef struct usb_dc_device { + struct device parent; + uint8_t id; + usb_dc_ep_state_t in_ep[8]; /*!< IN endpoint parameters */ + usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters */ + void *tx_dma; + void *rx_dma; +} usb_dc_device_t; + +int usb_dc_register(enum usb_index_type index, const char *name); + +int usb_dc_set_dev_address(const uint8_t addr); +int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg); +int usb_dc_ep_close(const uint8_t ep); +int usb_dc_ep_set_stall(const uint8_t ep); +int usb_dc_ep_clear_stall(const uint8_t ep); +int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled); +int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes); +int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes); +int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep); +int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep); + +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_wdt.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..5299fefd05d882804ee47ee922856640ece8fdbf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_wdt.h @@ -0,0 +1,57 @@ +/** + * @file hal_wdt.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_WDT__H__ +#define __HAL_WDT__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define DEVICE_CTRL_GET_WDT_COUNTER (0x10) +#define DEVICE_CTRL_RST_WDT_COUNTER (0x11) +#define DEVICE_CTRL_GET_RST_STATUS (0x12) +#define DEVICE_CTRL_CLR_RST_STATUS (0x13) + +enum wdt_index_type { +#ifdef BSP_USING_WDT + WDT_INDEX, +#endif + WDT_MAX_INDEX +}; + +enum wdt_event_type { + WDT_EVENT, + WDT_EVENT_UNKNOWN +}; + +typedef struct wdt_device { + struct device parent; + uint8_t id; + uint32_t wdt_timeout; +} wdt_device_t; + +#define WDT_DEV(dev) ((wdt_device_t *)dev) + +int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); +int wdt_register(enum wdt_index_type index, const char *name); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_acomp.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_acomp.c new file mode 100644 index 0000000000000000000000000000000000000000..bd80a16e8546bf56d1affbccc1fc55ac4270469d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_acomp.c @@ -0,0 +1,89 @@ +#include "hal_acomp.h" +#include "bl702_acomp.h" +#include "bl702_hbn.h" + +void acomp_init(acomp_device_t *device) +{ + uint32_t tmpVal; + + if (device->id == AON_ACOMP0_ID) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal &= ~(1 << 20); + tmpVal &= ~(1 << 21); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + /* Disable ACOMP first */ + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); + + /* Set ACOMP config */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, device->pos_ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, device->neg_ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, AON_ACOMP_LEVEL_FACTOR_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, AON_ACOMP_BIAS_POWER_MODE1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, device->pos_hysteresis_vol); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, device->neg_hysteresis_vol); + /*enable acomp*/ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal |= (1 << 20); + tmpVal |= (1 << 21); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + HBN_Clear_IRQ(HBN_INT_ACOMP0); + } else { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal &= ~(1 << 22); + tmpVal &= ~(1 << 23); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + /* Disable ACOMP first */ + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); + + /* Set ACOMP config */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, device->pos_ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, device->neg_ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, AON_ACOMP_LEVEL_FACTOR_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, AON_ACOMP_BIAS_POWER_MODE1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, device->pos_hysteresis_vol); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, device->neg_hysteresis_vol); + /*enable acomp*/ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal |= (1 << 22); + tmpVal |= (1 << 23); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + HBN_Clear_IRQ(HBN_INT_ACOMP1); + } +} + +int acomp_get_result(acomp_device_t *device) +{ + uint32_t tmpVal; + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL); + + /* Disable ACOMP first */ + if (device->id == AON_ACOMP0_ID) { + if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) { + return SET; + } else { + return RESET; + } + } else { + if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) { + return SET; + } else { + return RESET; + } + } +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_adc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..02bd6c6b19a94ac1f5e642ef1cfe34dfa656abe3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_adc.c @@ -0,0 +1,380 @@ +/** + * @file hal_adc.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_adc.h" +#include "hal_gpio.h" +#include "hal_clock.h" +#include "bl702_glb.h" +#include "bl702_dma.h" +#include "bl702_adc.h" +#include "adc_config.h" + +#ifdef BSP_USING_ADC0 +static void ADC_IRQ(void); +#endif + +static adc_device_t adcx_device[ADC_MAX_INDEX] = { +#ifdef BSP_USING_ADC0 + ADC0_CONFIG, +#endif +}; + +/** + * @brief Check whether Channel Corresponding IO is configed success by Board System + * + * @param pos_list pos channel list + * @param neg_list negative channel list + * @param channelNum channel number + */ +uint8_t adc_check_channel_status(uint8_t *pos_list, uint8_t *neg_list, uint16_t channelNum) +{ + uint16_t i = 0; + + uint8_t channel_io_reference_table[] = { + GPIO_PIN_8, /* CH0 IO */ + GPIO_PIN_15, /* CH1 IO */ + GPIO_PIN_17, /* CH2 IO */ + GPIO_PIN_11, /* CH3 IO */ + GPIO_PIN_12, /* CH4 IO */ + GPIO_PIN_14, /* CH5 IO */ + GPIO_PIN_7, /* CH6 IO */ + GPIO_PIN_9, /* CH7 IO */ + GPIO_PIN_18, /* CH8 IO */ + GPIO_PIN_19, /* CH9 IO */ + GPIO_PIN_20, /* CH10 IO */ + GPIO_PIN_21, /* CH11 IO */ + + }; + + for (i = 0; i < channelNum; i++) { + if (pos_list[i] > ADC_CHANNEL11) { + continue; + } + + if (GLB_GPIO_Get_Fun(channel_io_reference_table[pos_list[i]]) != GPIO_FUN_ANALOG) { + return ERROR; + } + } + + return SUCCESS; +} +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int adc_open(struct device *dev, uint16_t oflag) +{ + adc_device_t *adc_device = (adc_device_t *)dev; + ADC_CFG_Type adc_cfg = { 0 }; + ADC_FIFO_Cfg_Type adc_fifo_cfg = { 0 }; + + adc_cfg.clkDiv = adc_device->clk_div; + + adc_cfg.vref = adc_device->vref; + adc_cfg.resWidth = adc_device->data_width; + adc_cfg.inputMode = adc_device->differential_mode; + + adc_cfg.v18Sel = ADC_V18_SELECT; + adc_cfg.v11Sel = ADC_V11_SELECT; + adc_cfg.gain1 = ADC_PGA_GAIN1; + adc_cfg.gain2 = ADC_PGA_GAIN2; + adc_cfg.chopMode = ADC_CHOP_MODE; + adc_cfg.biasSel = ADC_BIAS_SELECT; + adc_cfg.vcm = ADC_PGA_VCM; + adc_cfg.offsetCalibEn = ADC_OFFSET_CALIB_EN; + adc_cfg.offsetCalibVal = ADC_OFFSER_CALIB_VAL; + + adc_fifo_cfg.dmaEn = DISABLE; + + if (oflag & DEVICE_OFLAG_STREAM_TX) { + } + + if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) { + } + + if (oflag & DEVICE_OFLAG_DMA_TX) { + } + + if (oflag & DEVICE_OFLAG_DMA_RX) { + adc_fifo_cfg.dmaEn = ENABLE; + } + + adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold; + +#ifdef BSP_USING_ADC0 + Interrupt_Handler_Register(GPADC_DMA_IRQn, ADC_IRQ); +#endif + + ADC_Disable(); + ADC_Enable(); + + ADC_Reset(); + + ADC_Init(&adc_cfg); + + ADC_FIFO_Cfg(&adc_fifo_cfg); + + ADC_IntMask(ADC_INT_ALL, MASK); + + CPU_Interrupt_Enable(GPADC_DMA_IRQn); + + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int adc_close(struct device *dev) +{ + ADC_Disable(); + return 0; +} + +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int adc_control(struct device *dev, int cmd, void *args) +{ + adc_device_t *adc_device = (adc_device_t *)dev; + adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args; + uint8_t rlt = 0; + uint32_t mask = 0; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: + mask = (uint32_t)args; + + if (mask & ADC_EVENT_FIFO_READY_IT) { + ADC_IntMask(ADC_EVENT_FIFO_READY, UNMASK); + } + if (mask & ADC_EVENT_OVERRUN_IT) { + ADC_IntMask(ADC_EVENT_OVERRUN, UNMASK); + } + if (mask & ADC_EVENT_UNDERRUN_IT) { + ADC_IntMask(ADC_EVENT_UNDERRUN, UNMASK); + } + if (mask & ADC_EVEN_INT_POS_SATURATION_IT) { + ADC_IntMask(ADC_EVEN_INT_POS_SATURATION, UNMASK); + } + if (mask & ADC_EVEN_INT_NEG_SATURATION_IT) { + ADC_IntMask(ADC_EVEN_INT_NEG_SATURATION, UNMASK); + } + + break; + + case DEVICE_CTRL_CLR_INT /* constant-expression */: + mask = (uint32_t)args; + + if (mask & ADC_EVENT_FIFO_READY_IT) { + ADC_IntMask(ADC_EVENT_FIFO_READY, MASK); + } + if (mask & ADC_EVENT_OVERRUN_IT) { + ADC_IntMask(ADC_EVENT_OVERRUN, MASK); + } + if (mask & ADC_EVENT_UNDERRUN_IT) { + ADC_IntMask(ADC_EVENT_UNDERRUN, MASK); + } + if (mask & ADC_EVEN_INT_POS_SATURATION_IT) { + ADC_IntMask(ADC_EVEN_INT_POS_SATURATION, MASK); + } + if (mask & ADC_EVEN_INT_NEG_SATURATION_IT) { + ADC_IntMask(ADC_EVEN_INT_NEG_SATURATION, MASK); + } + + break; + + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_CONFIG /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_ADC_CHANNEL_CONFIG /* constant-expression */: + if (adc_channel_cfg->num == 1) { + ADC_Channel_Config(*adc_channel_cfg->pos_channel, *adc_channel_cfg->neg_channel, adc_device->continuous_conv_mode); + rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, 1); + } else { + ADC_Scan_Channel_Config(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num, adc_device->continuous_conv_mode); + rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num); + } + + break; + + case DEVICE_CTRL_ADC_CHANNEL_START /* constant-expression */: + /* code */ + ADC_Start(); + break; + + case DEVICE_CTRL_ADC_CHANNEL_STOP /* constant-expression */: + /* code */ + ADC_Stop(); + break; + + case DEVICE_CTRL_ADC_VBAT_ON: + ADC_Vbat_Enable(); + break; + + case DEVICE_CTRL_ADC_VBAT_OFF: + ADC_Vbat_Disable(); + break; + + case DEVICE_CTRL_ADC_TSEN_ON: + ADC_Tsen_Init(ADC_TSEN_MOD_INTERNAL_DIODE); + break; + + case DEVICE_CTRL_ADC_TSEN_OFF: + + break; + + default: + break; + } + + return rlt; +} +// int adc_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +// { + +// return 0; +// } +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + if (dev->oflag & DEVICE_OFLAG_STREAM_RX || dev->oflag & DEVICE_OFLAG_INT_RX) { + while (ADC_Get_FIFO_Count() == 0) + ; + + do { + uint32_t regVal = ADC_Read_FIFO(); + + if (regVal) { + ADC_Result_Type *result = (ADC_Result_Type *)buffer; + ADC_Parse_Result(®Val, size, result); + } + } while (ADC_Get_FIFO_Count() != 0); + } + + return 0; +} + +int adc_trim_tsen(uint16_t *tsen_offset) +{ + return ADC_Trim_TSEN(tsen_offset); +} + +float adc_get_tsen(uint16_t tsen_offset) +{ + return TSEN_Get_Temp(tsen_offset); +} + +/** + * @brief + * + * @param index + * @param name + * @param flag + * @param adc_user_cfg + * @return int + */ +int adc_register(enum adc_index_type index, const char *name) +{ + struct device *dev; + + if (ADC_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(adcx_device[index].parent); + + dev->open = adc_open; + dev->close = adc_close; + dev->control = adc_control; + dev->write = NULL; + dev->read = adc_read; + + dev->type = DEVICE_CLASS_ADC; + dev->handle = NULL; + + return device_register(dev, name); +} + +/** + * @brief + * + * @param handle + */ +void adc_isr(adc_device_t *handle) +{ + if (!handle->parent.callback) + return; + + if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) { + handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_POS_SATURATION); + ADC_IntClr(ADC_INT_POS_SATURATION); + } + + if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) { + handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_NEG_SATURATION); + ADC_IntClr(ADC_INT_NEG_SATURATION); + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) { + handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN); + ADC_IntClr(ADC_INT_FIFO_UNDERRUN); + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) { + handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN); + ADC_IntClr(ADC_INT_FIFO_OVERRUN); + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) { + handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_FIFO_READY); + ADC_IntClr(ADC_INT_FIFO_READY); + } +} +#ifdef BSP_USING_ADC0 +void ADC_IRQ(void) +{ + adc_isr(&adcx_device[ADC0_INDEX]); +} +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_boot2.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_boot2.c new file mode 100644 index 0000000000000000000000000000000000000000..ca4aefa0f71b6bdd95fd5b234e988cdbe5585c5e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_boot2.c @@ -0,0 +1,209 @@ +#include "hal_boot2.h" +#include "hal_flash.h" +#include "bl702_ef_ctrl.h" +#include "bl702_hbn.h" +#include "bl702_glb.h" +#include "bl702_xip_sflash.h" +#include "tzc_sec_reg.h" +#include "hal_gpio.h" + +/** + * @brief boot2 custom + * + * @param None + * @return uint32 + */ +uint32_t hal_boot2_custom(void) +{ + return 0; +} + + + +/** + * @brief get efuse Boot2 config + * + * @param g_efuse_cfg + * @param + * @param + * @return None + */ +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg) +{ + uint32_t tmp; + uint32_t rootClk; + uint8_t hdiv = 0, bdiv = 0; + + /* save bclk fclk div and root clock sel */ + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + rootClk = BL_RD_REG(HBN_BASE, HBN_GLB); + + /* change root clock to rc32m for efuse operation */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + + /* Get sign and aes type*/ + EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)g_efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)g_efuse_cfg->encrypted); + /* Get hash:aes key slot 0 and slot1*/ + EF_Ctrl_Read_AES_Key(0, (uint32_t *)g_efuse_cfg->pk_hash_cpu0, 8); + EF_Ctrl_Read_Chip_ID(g_efuse_cfg->chip_id); + /* Get HBN check sign config */ + EF_Ctrl_Read_Sw_Usage(0, &tmp); + g_efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01; + + /* restore bclk fclk div and root clock sel */ + GLB_Set_System_CLK_Div(hdiv, bdiv); + BL_WR_REG(HBN_BASE, HBN_GLB,rootClk); + __NOP();__NOP();__NOP();__NOP(); +} +/** + * @brief reset sec eng clock + * + * @return + */ +void hal_boot2_reset_sec_eng(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC); +} + +/** + * @brief system soft reset + * + * @return + */ +void hal_boot2_sw_system_reset(void) +{ + GLB_SW_System_Reset(); +} + + +/** + * @brief + * + * @param flag + * @param + * @param + * @return + */ +void hal_boot2_set_psmode_status(uint32_t flag) +{ + HBN_Set_Status_Flag(flag); +} + +/** + * @brief + * + * @param + * @param + * @param + * @return flag + */ +uint32_t hal_boot2_get_psmode_status(void) +{ + return HBN_Get_Status_Flag(); +} + +/** + * @brief + * + * @param + * @param + * @param + * @return user define flag + */ +uint32_t hal_boot2_get_user_fw(void) +{ + return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); +} + +/** + * @brief clr user define flag + * + * @param + * @param + * @param + * @return + */ +void hal_boot2_clr_user_fw(void) +{ + uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET); + *p = 0; +} + +/** + * @brief hal_boot2_sboot_finish + * + * @return + */ +void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) +{ + uint32_t tmp_val; + + tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val); +} + +/** + * @brief hal_boot2_pll_init + * + * @return + */ +void hal_boot2_uart_gpio_init(void) +{ + GLB_GPIO_Type gpios[]={GPIO_PIN_14,GPIO_PIN_15}; + + GLB_GPIO_Func_Init(GPIO_FUN_UART,gpios,2); + + GLB_UART_Fun_Sel((GPIO_PIN_14 % 8), GLB_UART_SIG_FUN_UART0_TXD);// GPIO_FUN_UART1_TX + GLB_UART_Fun_Sel((GPIO_PIN_15 % 8), GLB_UART_SIG_FUN_UART0_RXD); +} + +/** + * @brief hal_boot2_pll_init + * + * @return + */ +void hal_boot2_debug_uart_gpio_init(void) +{ + GLB_GPIO_Type gpios[]={GPIO_PIN_17}; + + GLB_GPIO_Func_Init(GPIO_FUN_UART,gpios,1); + + GLB_UART_Fun_Sel((GPIO_PIN_17 % 8), GLB_UART_SIG_FUN_UART1_TXD); +} + + +/** + * @brief hal_boot2_debug_usb_port_init + * + * @return + */ +#if HAL_BOOT2_SUPPORT_USB_IAP +void hal_boot2_debug_usb_port_init(void) +{ + + + /* must do this , or usb can not be recognized */ + __disable_irq(); + __enable_irq(); + + GLB_GPIO_Type gpios[]={GPIO_PIN_7,GPIO_PIN_8}; + GLB_GPIO_Func_Init(GPIO_FUN_ANALOG,gpios,2); +} +#endif + +/** + * @brief hal_boot2_debug_uart_gpio_deinit + * + * @return + */ +void hal_boot2_debug_uart_gpio_deinit(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0); + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1); + GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); +} + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_cam.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_cam.c new file mode 100644 index 0000000000000000000000000000000000000000..59c013160a40aa237e9bd574f3abdf466f613d48 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_cam.c @@ -0,0 +1,249 @@ +/** + * @file hal_cam.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "bl702_cam.h" +#include "bl702_glb.h" +#include "hal_cam.h" + +#ifdef BSP_USING_CAM +static intCallback_Type *camIntCbfArra[CAM_INT_ALL] = { NULL }; + +void CAMERA_IRQ(void); +#endif +/** + * @brief + * + * @param cam_cfg + */ +void cam_init(cam_device_t *cam_cfg, uint16_t oflag) +{ + CAM_CFG_Type camera_cfg = { + .swMode = cam_cfg->software_mode, + .swIntCnt = 0, + .frameMode = cam_cfg->frame_mode, + .yuvMode = cam_cfg->yuv_format, + .waitCount = 0x40, + .linePol = CAM_LINE_ACTIVE_POLARITY_HIGH, + .framePol = CAM_FRAME_ACTIVE_POLARITY_HIGH, + .burstType = CAM_BURST_TYPE_INCR16, + .camSensorMode = CAM_SENSOR_MODE_V_AND_H, + .memStart0 = cam_cfg->cam_write_ram_addr, + .memSize0 = cam_cfg->cam_write_ram_size, + .frameSize0 = cam_cfg->cam_frame_size, + /* planar mode*/ + .memStart1 = cam_cfg->cam_write_ram_addr1, + .memSize1 = cam_cfg->cam_write_ram_size1, + .frameSize1 = cam_cfg->cam_frame_size1, + }; + CAM_Init(&camera_cfg); + + if (oflag == DEVICE_OFLAG_INT) { +#ifdef BSP_USING_CAM + Interrupt_Handler_Register(CAM_IRQn, CAMERA_IRQ); +#endif + } +} + +/** + * @brief + * + */ +void cam_start(void) +{ + CAM_Enable(); +} + +/** + * @brief + * + */ +void cam_stop(void) +{ + CAM_Disable(); +} + +/** + * @brief + * + * @param pic + * @param len + */ +uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len) +{ + CAM_Interleave_Frame_Info info; + arch_memset(&info, 0, sizeof(info)); + + CAM_Interleave_Get_Frame_Info(&info); + + if (info.validFrames == 0) { + return ERROR; + } + + *pic = (uint8_t *)(info.curFrameAddr); + *len = info.curFrameBytes; + + return SUCCESS; +} + +uint8_t cam_get_one_frame_planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, uint8_t **picUV, uint32_t *lenUV) +{ + CAM_Planar_Frame_Info info; + arch_memset(&info, 0, sizeof(info)); + + CAM_Planar_Get_Frame_Info(&info); + + if (yuv == CAM_YUV400_EVEN || yuv == CAM_YUV400_ODD) { + if (info.validFrames0 == 0 && info.validFrames1 == 0) { + return ERROR; + } + } else { + if (info.validFrames0 == 0 || info.validFrames1 == 0) { + return ERROR; + } + } + + *picYY = (uint8_t *)(info.curFrameAddr0); + *lenYY = info.curFrameBytes0; + *picUV = (uint8_t *)(info.curFrameAddr1); + *lenUV = info.curFrameBytes1; + + return SUCCESS; +} + +void cam_drop_one_frame_interleave(void) +{ + CAM_Interleave_Pop_Frame(); +} + +void cam_drop_one_frame_planar(void) +{ + CAM_Planar_Pop_Frame(); +} + +void cam_hsync_crop(uint16_t start, uint16_t end) +{ + CAM_Hsync_Crop(start, end); +} + +void cam_vsync_crop(uint16_t start, uint16_t end) +{ + CAM_Vsync_Crop(start, end); +} + +void cam_hw_mode_wrap(uint8_t enable) +{ + CAM_HW_Mode_Wrap(enable); +} + +void cam_isr(cam_device_t *handle) +{ +} + +#ifdef BSP_USING_CAM + +void CAM_Int_Callback_set(CAM_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_CAM_INT_TYPE(intType)); + + camIntCbfArra[intType] = cbFun; +} + +void CAMERA_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR); + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_0)) { + CAM_IntClr(CAM_INT_NORMAL_0); + if (camIntCbfArra[CAM_INT_NORMAL_0] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_NORMAL_0](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_1)) { + CAM_IntClr(CAM_INT_NORMAL_1); + if (camIntCbfArra[CAM_INT_NORMAL_1] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_NORMAL_1](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_0)) { + CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_0); + if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_1)) { + CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_1); + if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_0)) { + CAM_IntClr(CAM_INT_FRAME_OVERWRITE_0); + if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_1)) { + CAM_IntClr(CAM_INT_FRAME_OVERWRITE_1); + if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_0)) { + CAM_IntClr(CAM_INT_FIFO_OVERWRITE_0); + if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_1)) { + CAM_IntClr(CAM_INT_FIFO_OVERWRITE_1); + if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) { + CAM_IntClr(CAM_INT_HSYNC_CNT_ERROR); + if (camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR](); + } + } + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) { + CAM_IntClr(CAM_INT_VSYNC_CNT_ERROR); + if (camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR](); + } + } +} + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..4c14cb0778aa09d9047f1300462d502cea567b3c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c @@ -0,0 +1,636 @@ +/** + * @file hal_clock.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "bl702_glb.h" +#include "bl702_pwm.h" +#include "bl702_timer.h" +#include "hal_clock.h" +#include "hal_mtimer.h" + +static uint32_t mtimer_get_clk_src_div(void) +{ + return ((SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1)) / 1000 / 1000 - 1); +} + +static void peripheral_clock_gate_all() +{ + uint32_t tmpVal; + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + tmpVal &= (~(1 << BL_AHB_SLAVE1_DMA)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_EMAC)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_UART0)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_UART1)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_SPI)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_I2C)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_PWM)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_TMR)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_IRR)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_QDEC)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_KYS)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_I2S)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_USB)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_CAM)); + tmpVal &= (~(1 << BL_AHB_SLAVE1_MJPEG)); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); +} + +void system_clock_init(void) +{ + /*select root clock*/ + GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE); +#if BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_57P6M + /* fix 57.6M */ + SystemCoreClockSet(57.6 * 1000 * 1000); +#endif + /*set fclk/hclk and bclk clock*/ + GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV); + /* Set MTimer the same frequency as SystemCoreClock */ + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); +#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE + PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE - ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ); +#endif +#if 1 + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); +#else + HBN_32K_Sel(HBN_32K_XTAL); + HBN_Power_On_Xtal_32K(); +#endif + if ((XTAL_TYPE == INTERNAL_RC_32M) || (XTAL_TYPE == XTAL_NONE)) { + HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M); + } else { + HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL); + } +} + +void system_mtimer_clock_init(void) +{ + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); +} + +void system_mtimer_clock_reinit(void) +{ + /* reinit clock to 10M */ + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7); +} + +void peripheral_clock_init(void) +{ + peripheral_clock_gate_all(); +#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) +#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M +#if defined(BSP_USING_UART0) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_UART0); +#endif +#if defined(BSP_USING_UART1) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_UART1); +#endif + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, BSP_UART_CLOCK_DIV); +#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK +#if defined(BSP_USING_UART0) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_UART0); +#endif +#if defined(BSP_USING_UART1) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_UART1); +#endif + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_FCLK, BSP_UART_CLOCK_DIV); +#else +#error "please select correct uart clock source" +#endif +#endif + +#if defined(BSP_USING_I2C0) +#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_I2C); + GLB_Set_I2C_CLK(ENABLE, BSP_I2C_CLOCK_DIV); +#else +#error "please select correct i2c clock source" +#endif +#endif + +#if defined(BSP_USING_SPI0) +#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_SPI); + GLB_Set_SPI_CLK(ENABLE, BSP_SPI_CLOCK_DIV); +#else +#error "please select correct spi clock source" +#endif +#endif + +#if defined(BSP_USING_TIMER0) +#if BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure timer clock source */ + uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_FCLK); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp); + + /* Configure timer clock division */ + tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure timer clock source */ + uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_XTAL); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp); + + /* Configure timer clock division */ + tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure timer clock source */ + uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_32K); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp); + + /* Configure timer clock division */ + tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure timer clock source */ + uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_1K); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp); + + /* Configure timer clock division */ + tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp); +#else +#error "please select correct timer0 clock source" +#endif +#endif + +#if defined(BSP_USING_TIMER1) +#if BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure timer clock source */ + uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_FCLK); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1); + + /* Configure timer clock division */ + tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1); +#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure timer clock source */ + uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_XTAL); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1); + + /* Configure timer clock division */ + tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1); +#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure timer clock source */ + uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_32K); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1); + + /* Configure timer clock division */ + tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1); +#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure timer clock source */ + uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_1K); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1); + + /* Configure timer clock division */ + tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1); +#else +#error "please select correct timer1 clock source" +#endif +#endif + +#if defined(BSP_USING_WDT) +#if BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure watchdog timer clock source */ + uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_FCLK); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt); + + /* Configure watchdog timer clock division */ + tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt); +#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure watchdog timer clock source */ + uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_XTAL); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt); + + /* Configure watchdog timer clock division */ + tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt); +#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure watchdog timer clock source */ + uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_32K); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt); + + /* Configure watchdog timer clock division */ + tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt); +#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR); + /* Configure watchdog timer clock source */ + uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_1K); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt); + + /* Configure watchdog timer clock division */ + tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt); +#else +#error "please select correct watchdog timer clock source" +#endif +#endif + +#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5) + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_PWM); + uint32_t timeoutCnt = 160 * 1000; + uint32_t tmpVal; + uint32_t PWMx; +#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK + + for (int i = 0; i < 5; i++) { + PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20; + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + + while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return; + } + } + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_32K); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV); + } +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + + for (int i = 0; i < 5; i++) { + PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20; + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + + while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return; + } + } + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_BCLK); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV); + } +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + + for (int i = 0; i < 5; i++) { + PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20; + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + + while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return; + } + } + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_XCLK); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV); + } +#else +#error "please select correct pwm clock source" +#endif +#endif + +#if defined(BSP_USING_IR) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_IRR); + GLB_Set_IR_CLK(ENABLE, 0, BSP_IR_CLOCK_DIV); +#endif + +#if defined(BSP_USING_I2S0) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_I2S); + GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE); +#endif + +#if defined(BSP_USING_ADC0) +#if BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV); +#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV); +#else +#error "please select correct adc clock source" +#endif +#endif + +#if defined(BSP_USING_DAC0) +#if BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ + GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV); +#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, BSP_DAC_CLOCK_DIV); +#else +#error "please select correct dac clock source" +#endif +#endif + +#if defined(BSP_USING_CAM) +#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_CAM); + GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV); + GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM); +#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_CAM); + GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_XCLK, BSP_CAM_CLOCK_DIV); + GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM); +#else +#error "please select correct camera clock source" +#endif +#endif + +#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2) || defined(BSP_USING_KEYSCAN) +#if BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK +#ifdef BSP_USING_KEYSCAN + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_KYS); +#endif +#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_QDEC); +#endif + GLB_Set_QDEC_CLK(GLB_QDEC_CLK_F32K, BSP_QDEC_KEYSCAN_CLOCK_DIV); +#elif BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK +#if defined(BSP_USING_KEYSCAN) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_KYS); +#endif +#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_QDEC); +#endif + GLB_Set_QDEC_CLK(GLB_QDEC_CLK_XCLK, BSP_QDEC_KEYSCAN_CLOCK_DIV); +#else +#error "please select correct qdec or keyscan clock source" +#endif +#endif + +#if defined(BSP_USING_USB) + GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_USB); + GLB_Set_USB_CLK(1); +#endif +} +uint32_t system_clock_get(enum system_clock_type type) +{ + switch (type) { + case SYSTEM_CLOCK_ROOT_CLOCK: + if (GLB_Get_Root_CLK_Sel() == 0) { + return 32 * 1000 * 1000; + } else if (GLB_Get_Root_CLK_Sel() == 1) + return 32 * 1000 * 1000; + else { + uint32_t tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL); + if (tmpVal == 0) { + return 57.6 * 1000 * 1000; + } else if (tmpVal == 1) { + return 96 * 1000 * 1000; + } else if (tmpVal == 2) { + return 144 * 1000 * 1000; + } else { + return 0; + } + } + case SYSTEM_CLOCK_FCLK: + return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1); + + case SYSTEM_CLOCK_BCLK: + return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1) / (GLB_Get_BCLK_Div() + 1); + + case SYSTEM_CLOCK_XCLK: + return 32000000; + case SYSTEM_CLOCK_32K_CLK: + return 32000; + case SYSTEM_CLOCK_AUPLL: + if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ) { + return 12288000; + } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ) { + return 11289600; + } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ) { + return 5644800; + } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ) { + return 24576000; + } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ) { + return 24000000; + } + default: + break; + } + + return 0; +} +uint32_t peripheral_clock_get(enum peripheral_clock_type type) +{ + uint32_t tmpVal; + uint32_t div; + + switch (type) { +#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) + case PERIPHERAL_CLOCK_UART: +#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV); + return 96000000 / (div + 1); +#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1); +#else + break; +#endif + +#endif +#if defined(BSP_USING_SPI0) + case PERIPHERAL_CLOCK_SPI: +#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1); +#else + break; +#endif +#endif +#if defined(BSP_USING_I2C0) + case PERIPHERAL_CLOCK_I2C: +#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1); + +#else + break; +#endif +#endif +#if defined(BSP_USING_I2S0) + case PERIPHERAL_CLOCK_I2S: + return system_clock_get(SYSTEM_CLOCK_AUPLL); +#endif +#if defined(BSP_USING_ADC0) + case PERIPHERAL_CLOCK_ADC: +#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_XCLK) / div; +#elif BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_AUPLL) / div; +#else + break; +#endif +#endif +#if defined(BSP_USING_DAC0) + case PERIPHERAL_CLOCK_DAC: +#if BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV); + return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1); +#elif BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV); + return system_clock_get(SYSTEM_CLOCK_AUPLL) / div; +#else + break; +#endif +#endif +#if defined(BSP_USING_TIMER0) + case PERIPHERAL_CLOCK_TIMER0: +#if BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR2); + return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR2); + return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR2); + return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR2); + return 1000 / (div + 1); +#else + break; +#endif +#endif +#if defined(BSP_USING_TIMER1) + case PERIPHERAL_CLOCK_TIMER1: +#if BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3); + return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3); + return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3); + return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1); +#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3); + return 1000 / (div + 1); +#else + break; +#endif +#endif +#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5) + case PERIPHERAL_CLOCK_PWM: +#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK + div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV); + return system_clock_get(SYSTEM_CLOCK_32K_CLK) / div; +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV); + return system_clock_get(SYSTEM_CLOCK_BCLK) / div; +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV); + return system_clock_get(SYSTEM_CLOCK_XCLK) / div; +#else + break; +#endif +#endif +#if defined(BSP_USING_CAM) + case PERIPHERAL_CLOCK_CAM: +#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV); + return (96000000 / (div + 1)); +#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV); + return (system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1)); +#else + break; +#endif +#endif + default: + + break; + } + + (void)(tmpVal); + (void)(div); + return 0; +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dac.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..695329a547d9eed7dbc7f1e646568108e9200720 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dac.c @@ -0,0 +1,246 @@ +/** + * @file hal_dac.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_dac.h" +#include "hal_dma.h" +#include "bl702_gpio.h" +#include "bl702_dac.h" +#include "bl702_dma.h" +#include "bl702_config.h" +#include "bl702_glb.h" +#include "dac_config.h" + +static dac_device_t dacx_device[] = { +#ifdef BSP_USING_DAC0 + DAC_CONFIG, +#endif +}; + +int dac_open(struct device *dev, uint16_t oflag) +{ + GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = { 0 }; + GLB_GPIP_DAC_Cfg_Type dacCfg = { 0 }; + dac_device_t *dac_device = (dac_device_t *)dev; + uint8_t dac_ext_ref_pin = 0; + + if (dac_device->pin.pin_num == 2) { + GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, (GLB_GPIO_Type *)&dac_device->pin.dac0, 2); + } else if (dac_device->pin.pin_num == 1) { + GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, (GLB_GPIO_Type *)&dac_device->pin.dac0, 1); + } else { + return ERROR; + } + + switch (dac_device->clk) { + case DAC_CLK_500KHZ: + PDS_Set_Audio_PLL_Freq(AUDIO_PLL_24000000_HZ); + /* 24.0000MHZ / 3 / 16 = 500KHZ*/ + GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, 3); + dacCfg.div = DAC_CLK_DIV_16; + break; + + case DAC_CLK_8KHZ: + /* set audio pll as 12.288MHZ*/ + PDS_Set_Audio_PLL_Freq(AUDIO_PLL_12288000_HZ); + /* 12.2880MHZ / 24 / 64 = 8KHZ*/ + GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, 24); + dacCfg.div = DAC_CLK_DIV_64; + break; + + case DAC_CLK_16KHZ: + /* set audio pll as 12.288MHZ*/ + PDS_Set_Audio_PLL_Freq(AUDIO_PLL_12288000_HZ); + /* 12.2880MHZ / 24 / 32 = 16KHZ*/ + GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, 24); + dacCfg.div = DAC_CLK_DIV_32; + break; + + case DAC_CLK_44P1KHZ: + /* set audio pll as 11.2896MHZ*/ + PDS_Set_Audio_PLL_Freq(AUDIO_PLL_11289600_HZ); + /* 11.2896MHZ / 16 / 16 = 44.1KHZ*/ + GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, 16); + dacCfg.div = DAC_CLK_DIV_16; + break; + + default: + break; + } + + if (DAC_REF_SEL == GLB_DAC_REF_SEL_EXTERNAL) { + dac_ext_ref_pin = DAC_EXT_REF_GPIO; + dacCfg.refSel = GLB_DAC_REF_SEL_EXTERNAL; + GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, (GLB_GPIO_Type *)&dac_ext_ref_pin, 1); + } else { + dacCfg.refSel = GLB_DAC_REF_SEL_INTERNAL; + } + + if (oflag & DEVICE_OFLAG_STREAM_TX) { + dacCfg.dmaEn = DISABLE; + dacCfg.resetChanA = ENABLE; + dacCfg.resetChanB = ENABLE; + dacCfg.dmaFmt = GPIP_DAC_DMA_FORMAT_0; + + chCfg.chanCovtEn = ENABLE; + chCfg.outputEn = ENABLE; + chCfg.chanEn = ENABLE; + chCfg.src = GPIP_DAC_ChanA_SRC_REG; + + GLB_GPIP_DAC_Init(&dacCfg); + GLB_GPIP_DAC_Set_ChanA_Config(&chCfg); + GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg); + + } else if (oflag & DEVICE_OFLAG_DMA_TX) { + dacCfg.dmaEn = ENABLE; + dacCfg.resetChanA = ENABLE; + dacCfg.resetChanB = ENABLE; + + if (dac_device->pin.pin_num == 2) { + dacCfg.dmaFmt = GPIP_DAC_DMA_FORMAT_1; + } else { + dacCfg.dmaFmt = GPIP_DAC_DMA_FORMAT_0; + } + + chCfg.chanCovtEn = ENABLE; + chCfg.outputEn = ENABLE; + chCfg.chanEn = ENABLE; + chCfg.src = GPIP_DAC_ChanA_SRC_DMA; + + GLB_GPIP_DAC_Init(&dacCfg); + GLB_GPIP_DAC_Set_ChanA_Config(&chCfg); + GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg); + + GPIP_Set_DAC_DMA_TX_FORMAT_SEL(dacCfg.dmaFmt); + GPIP_Set_DAC_DMA_TX_Enable(); + + } else { + } + + return 0; +} +int dac_close(struct device *dev) +{ + return 0; +} +int dac_control(struct device *dev, int cmd, void *args) +{ + dac_device_t *dac_device = (dac_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: + + break; + + case DEVICE_CTRL_CLR_INT /* constant-expression */: + + break; + + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_CONFIG /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_RESUME /* constant-expression */: + + break; + + case DEVICE_CTRL_SUSPEND /* constant-expression */: + + break; + + case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */: + dac_device->tx_dma = (struct device *)args; + break; + + default: + break; + } + + return 0; +} +int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + dac_channel_t channel = (dac_channel_t)pos; + dac_device_t *dac_device = (dac_device_t *)dev; + uint32_t i = 0; + + if (dev->oflag & DEVICE_OFLAG_DMA_TX) { + struct device *dma_ch = (struct device *)dac_device->tx_dma; + + if (!dma_ch) { + return -1; + } + + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_DAC_TDR, size); + dma_channel_start(dma_ch); + } + + if (dev->oflag & DEVICE_OFLAG_STREAM_TX) { + if (channel == DAC_CHANNEL_0) { + for (i = 0; i < size; i++) { + GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); + } + } else if (channel == DAC_CHANNEL_1) { + for (i = 0; i < size; i++) { + GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); + } + } else { + for (i = 0; i < size; i++) { + GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); + GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); + } + } + } + + return 0; +} +int dac_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + return 0; +} + +int dac_register(enum dac_index_type index, const char *name) +{ + struct device *dev; + + if (DAC_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(dacx_device[index].parent); + + dev->open = dac_open; + dev->close = dac_close; + dev->control = dac_control; + dev->write = dac_write; + dev->read = NULL; + + dev->type = DEVICE_CLASS_DAC; + dev->handle = NULL; + + device_register(dev, name); + + return 0; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..22a9713cff159807bb44b197adcf5fbc020b47a2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c @@ -0,0 +1,477 @@ +/** + * @file hal_dma.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_dma.h" +#include "bl702_dma.h" + +static dma_control_data_t dma_ctrl_cfg; + +static void DMA0_IRQ(void); + +static dma_device_t dmax_device[DMA_MAX_INDEX] = { +#ifdef BSP_USING_DMA0_CH0 + DMA0_CH0_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH1 + DMA0_CH1_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH2 + DMA0_CH2_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH3 + DMA0_CH3_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH4 + DMA0_CH4_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH5 + DMA0_CH5_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH6 + DMA0_CH6_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH7 + DMA0_CH7_CONFIG, +#endif +}; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int dma_open(struct device *dev, uint16_t oflag) +{ + dma_device_t *dma_device = (dma_device_t *)dev; + + DMA_LLI_Cfg_Type lliCfg = { 0 }; + + /* Disable all interrupt */ + DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK); + /* Enable uart interrupt*/ + CPU_Interrupt_Disable(DMA_ALL_IRQn); + + DMA_Disable(); + + DMA_Channel_Disable(dma_device->ch); + + lliCfg.dir = dma_device->direction; + lliCfg.srcPeriph = dma_device->src_req; + lliCfg.dstPeriph = dma_device->dst_req; + + DMA_LLI_Init(dma_device->ch, &lliCfg); + + dma_ctrl_cfg.bits.fix_cnt = 0; + dma_ctrl_cfg.bits.dst_min_mode = 0; + dma_ctrl_cfg.bits.dst_add_mode = 0; + + DMA_Enable(); + + Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ); + /* Enable uart interrupt*/ + CPU_Interrupt_Enable(DMA_ALL_IRQn); + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int dma_control(struct device *dev, int cmd, void *args) +{ + dma_device_t *dma_device = (dma_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: + /* Dma interrupt configuration */ + DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK); + DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK); + + break; + + case DEVICE_CTRL_CLR_INT /* constant-expression */: + /* Dma interrupt configuration */ + DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK); + DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK); + + break; + + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_CONFIG /* constant-expression */: { + dma_ctrl_param_t *cfg = (dma_ctrl_param_t *)args; + DMA_LLI_Cfg_Type lliCfg = { 0 }; + + lliCfg.dir = cfg->direction; + lliCfg.srcPeriph = cfg->src_req; + lliCfg.dstPeriph = cfg->dst_req; + + DMA_LLI_Init(dma_device->ch, &lliCfg); + + break; + } + + case DMA_CHANNEL_UPDATE: + DMA_LLI_Update(dma_device->ch, (uint32_t)args); + break; + + case DMA_CHANNEL_GET_STATUS /* constant-expression */: + return DMA_Channel_Is_Busy(dma_device->ch); + + case DMA_CHANNEL_START /* constant-expression */: + DMA_Channel_Enable(dma_device->ch); + break; + + case DMA_CHANNEL_STOP /* constant-expression */: + DMA_Channel_Disable(dma_device->ch); + break; + + default: + break; + } + + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int dma_close(struct device *dev) +{ + DMA_Disable(); + return 0; +} + +int dma_register(enum dma_index_type index, const char *name) +{ + struct device *dev; + + if (DMA_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(dmax_device[index].parent); + + dev->open = dma_open; + dev->close = dma_close; + dev->control = dma_control; + // dev->write = dma_write; + // dev->read = dma_read; + + dev->type = DEVICE_CLASS_DMA; + dev->handle = NULL; + + return device_register(dev, name); +} + +static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index) +{ + struct device *dev; + dlist_t *node; + uint8_t dma_index = 0; + uint32_t dma_handle[DMA_MAX_INDEX]; + + for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) { + dma_handle[dma_index] = 0xff; + } + + /* get registered dma handle list*/ + dlist_for_each(node, device_get_list_header()) + { + dev = dlist_entry(node, struct device, list); + + if (dev->type == DEVICE_CLASS_DMA) { + dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET; + } + } + + for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) { + if (dma_handle[dma_index] == 0xff) { + *allocate_index = dma_index; + return SUCCESS; + } + } + + return ERROR; +} + +int dma_allocate_register(const char *name) +{ + struct device *dev; + uint8_t index; + + if (DMA_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + if (dma_scan_unregister_device(&index) == ERROR) { + return -DEVICE_ENOSPACE; + } + + dev = &(dmax_device[index].parent); + + dev->open = dma_open; + dev->close = dma_close; + dev->control = dma_control; + // dev->write = dma_write; + // dev->read = dma_read; + + dev->status = DEVICE_UNREGISTER; + dev->type = DEVICE_CLASS_DMA; + dev->handle = NULL; + + return device_register(dev, name); +} + +/** + * @brief + * + * @param dev + * @param src_addr + * @param dst_addr + * @param transfer_size + * @return int + */ +int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size) +{ + uint32_t malloc_count; + uint32_t remain_len; + uint32_t actual_transfer_len = 0; + uint32_t actual_transfer_offset = 0; + + dma_device_t *dma_device = (dma_device_t *)dev; + + DMA_Channel_Disable(dma_device->ch); + + if (dma_device->direction == DMA_MEMORY_TO_MEMORY) { + dma_ctrl_cfg.bits.SI = 1; + dma_ctrl_cfg.bits.DI = 1; + } else if (dma_device->direction == DMA_MEMORY_TO_PERIPH) { + dma_ctrl_cfg.bits.SI = 1; + dma_ctrl_cfg.bits.DI = 0; + } else if (dma_device->direction == DMA_PERIPH_TO_MEMORY) { + dma_ctrl_cfg.bits.SI = 0; + dma_ctrl_cfg.bits.DI = 1; + } else if (dma_device->direction == DMA_PERIPH_TO_PERIPH) { + dma_ctrl_cfg.bits.SI = 0; + dma_ctrl_cfg.bits.DI = 0; + } + + if (dma_device->direction == DMA_MEMORY_TO_MEMORY) { + switch (dma_device->src_width) { + case DMA_TRANSFER_WIDTH_8BIT: + dma_device->src_burst_size = DMA_BURST_16BYTE; + case DMA_TRANSFER_WIDTH_16BIT: + dma_device->src_burst_size = DMA_BURST_8BYTE; + case DMA_TRANSFER_WIDTH_32BIT: + dma_device->src_burst_size = DMA_BURST_4BYTE; + } + } else { + dma_ctrl_cfg.bits.SBSize = dma_device->src_burst_size; + dma_ctrl_cfg.bits.DBSize = dma_device->dst_burst_size; + } + + dma_ctrl_cfg.bits.SWidth = dma_device->src_width; + dma_ctrl_cfg.bits.DWidth = dma_device->dst_width; + + if (dma_device->src_width == DMA_TRANSFER_WIDTH_8BIT) { + actual_transfer_offset = 4095; + actual_transfer_len = transfer_size; + } else if (dma_device->src_width == DMA_TRANSFER_WIDTH_16BIT) { + if (transfer_size % 2) { + return -1; + } + + actual_transfer_offset = (4095 * 2); + actual_transfer_len = transfer_size / 2; + } else if (dma_device->src_width == DMA_TRANSFER_WIDTH_32BIT) { + if (transfer_size % 4) { + return -1; + } + + actual_transfer_offset = (4095 * 4); + actual_transfer_len = transfer_size / 4; + } + + malloc_count = actual_transfer_len / 4095; + remain_len = actual_transfer_len % 4095; + + if (remain_len) { + malloc_count++; + } + + if (dma_device->lli_cfg) { + free(dma_device->lli_cfg); + dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count); + } else { + dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count); + } + + if (dma_device->lli_cfg) { + /*transfer_size will be 4095 or 4095*2 or 4095*4 in different transfer width*/ + if ((!remain_len) && (malloc_count == 1)) { + dma_device->lli_cfg[0].src_addr = src_addr; + dma_device->lli_cfg[0].dst_addr = dst_addr; + dma_device->lli_cfg[0].nextlli = 0; + dma_ctrl_cfg.bits.TransferSize = remain_len; + dma_ctrl_cfg.bits.I = 1; + memcpy(&dma_device->lli_cfg[0].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + /*transfer_size will be 4095*n or 4095*2*n or 4095*4*n,(n>1) in different transfer width*/ + else if ((!remain_len) && (malloc_count > 1)) { + for (uint32_t i = 0; i < malloc_count; i++) { + dma_device->lli_cfg[i].src_addr = src_addr; + dma_device->lli_cfg[i].dst_addr = dst_addr; + dma_device->lli_cfg[i].nextlli = 0; + + dma_ctrl_cfg.bits.TransferSize = 4095; + dma_ctrl_cfg.bits.I = 0; + + if (dma_ctrl_cfg.bits.SI) { + src_addr += actual_transfer_offset; + } + + if (dma_ctrl_cfg.bits.DI) { + dst_addr += actual_transfer_offset; + } + + if (i == malloc_count - 1) { + dma_ctrl_cfg.bits.I = 1; + + if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) { + dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0]; + } + } + + if (i) { + dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i]; + } + + memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + } else { + for (uint32_t i = 0; i < malloc_count; i++) { + dma_device->lli_cfg[i].src_addr = src_addr; + dma_device->lli_cfg[i].dst_addr = dst_addr; + dma_device->lli_cfg[i].nextlli = 0; + + dma_ctrl_cfg.bits.TransferSize = 4095; + dma_ctrl_cfg.bits.I = 0; + + if (dma_ctrl_cfg.bits.SI) { + src_addr += actual_transfer_offset; + } + + if (dma_ctrl_cfg.bits.DI) { + dst_addr += actual_transfer_offset; + } + + if (i == malloc_count - 1) { + dma_ctrl_cfg.bits.TransferSize = remain_len; + dma_ctrl_cfg.bits.I = 1; + + if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) { + dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0]; + } + } + + if (i) { + dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i]; + } + + memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + } + + DMA_LLI_Update(dma_device->ch, (uint32_t)dma_device->lli_cfg); + } else { + return -2; + } + + return 0; +} +/** + * @brief + * + * @param handle + */ +void dma_isr(dma_device_t *handle) +{ + uint32_t tmpVal; + uint32_t intClr; + + /* Get DMA register */ + if (handle->id == 0) { + uint32_t DMAChs = DMA_BASE; + + for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); + + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle[i].ch)) != 0) { + /* Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); + intClr |= (1 << handle[i].ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); + BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); + + if (handle[i].parent.callback) { + handle[i].parent.callback(&handle[i].parent, NULL, 0, DMA_INT_TCOMPLETED); + } + } + } + + for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); + + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle[i].ch)) != 0) { + /*Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); + intClr |= (1 << handle[i].ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); + BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); + + if (handle[i].parent.callback) { + handle[i].parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR); + } + } + } + } else { + } +} +/** + * @brief + * + */ +void DMA0_IRQ(void) +{ + dma_isr(&dmax_device[0]); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_emac.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_emac.c new file mode 100644 index 0000000000000000000000000000000000000000..394b6f3e44f3af9591f48637edf20c00b572f880 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_emac.c @@ -0,0 +1,526 @@ +/** + * @file hal_emac.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "bl702_emac.h" +#include "bl702_glb.h" +#include "hal_emac.h" + +#define EMAC_USE_INSIDE_CLOCK (0) +#define TAG "EMAC_BD: " + +static EMAC_Handle_Type ethHandle; +static EMAC_Handle_Type *thiz = NULL; + +/** + * @brief + * + */ +static void emac_gpio_init(void) +{ + uint8_t emacPins[] = { GLB_GPIO_PIN_0, GLB_GPIO_PIN_1, GLB_GPIO_PIN_2, + GLB_GPIO_PIN_7, GLB_GPIO_PIN_8, + GLB_GPIO_PIN_18, GLB_GPIO_PIN_19, GLB_GPIO_PIN_20, GLB_GPIO_PIN_21, GLB_GPIO_PIN_22 }; + + GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_EMAC); + + GLB_GPIO_Func_Init(GPIO_FUN_ETHER_MAC, (GLB_GPIO_Type *)emacPins, sizeof(emacPins)); +} + +/** + * @brief + * + * @param bdt + * @return int + */ +static uint32_t emac_bd_get_cur_active(EMAC_BD_TYPE_e bdt) +{ + uint32_t bd = 0; + + bd = BL_RD_REG(EMAC_BASE, EMAC_TX_BD_NUM); + + if (bdt == EMAC_BD_TYPE_TX) { + bd &= EMAC_TXBDPTR_MSK; + bd >>= EMAC_TXBDPTR_POS; + } + + if (bdt == EMAC_BD_TYPE_RX) { + bd &= EMAC_RXBDPTR_MSK; + bd >>= EMAC_RXBDPTR_POS; + } + + return bd; +} + +/** + * @brief + * + * @param index + * @return int + */ +static int emac_bd_rx_enqueue(uint32_t index) +{ + BL_Err_Type err = SUCCESS; + + thiz->rxIndexEMAC = index; + + return err; +} + +/** + * @brief + * + * @param index + * @return int + */ +static void emac_bd_rx_on_err(uint32_t index) +{ + /* handle error */ + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_OR)) { + MSG("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_RE)) { + MSG("MAC RX RE Error at %s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_DN)) { + MSG("MAC RX DN Error at %s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_TL)) { + MSG("MAC RX TL Error at %s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_CRC)) { + MSG("MAC RX CRC Error at %s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_LC)) { + MSG("MAC RX LC Error at %s:%d\r\n", __func__, __LINE__); + } + + thiz->bd[index].C_S_L &= ~0xff; + /* RX BD is ready for RX */ + thiz->bd[index].C_S_L |= EMAC_BD_FIELD_MSK(RX_E); +} + +/** + * @brief this func will be called in ISR + * + * @param index + * @return int + */ +static int emac_bd_tx_dequeue(uint32_t index) +{ + BL_Err_Type err = SUCCESS; + EMAC_BD_Desc_Type *DMADesc; + + thiz->txIndexEMAC = index; + DMADesc = &thiz->bd[thiz->txIndexEMAC]; + /* release this tx BD to SW (HW will do this) */ + DMADesc->C_S_L &= EMAC_BD_FIELD_UMSK(TX_RD); + + return err; +} + +/** + * @brief + * + * @param index + * @return int + */ +static void emac_bd_tx_on_err(uint32_t index) +{ + /* handle error */ + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_UR)) { + MSG("%s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RTRY)) { + MSG("%s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RL)) { + MSG("%s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_LC)) { + MSG("%s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_DF)) { + MSG("%s:%d\r\n", __func__, __LINE__); + } + + if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_CS)) { + MSG("%s:%d\r\n", __func__, __LINE__); + } + + thiz->bd[index].C_S_L &= ~0xff; +} + +/** + * @brief + * + */ +__WEAK void emac_tx_done_callback_app(void) +{ +} + +/** + * @brief + * + */ +static void emac_tx_done_callback(void) +{ + uint32_t index = 0; + index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); + + emac_bd_tx_dequeue(index); + + emac_tx_done_callback_app(); +} + +/** + * @brief + * + */ +__WEAK void emac_tx_error_callback_app(void) +{ +} + +/** + * @brief + * + */ +static void emac_tx_error_callback(void) +{ + uint32_t index = 0; + + index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); + + emac_bd_tx_on_err(index); +} + +/** + * @brief + * + */ +__WEAK void emac_rx_done_callback_app(void) +{ +} + +/** + * @brief + * + */ +static void emac_rx_done_callback(void) +{ + uint32_t index = 0; + + index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); + + emac_bd_rx_enqueue(index); + + emac_rx_done_callback_app(); +} + +/** + * @brief + * + */ +__WEAK void emac_rx_error_callback_app(void) +{ +} + +/** + * @brief + * + */ +static void emac_rx_error_callback(void) +{ + uint32_t index; + + index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); + + emac_bd_rx_on_err(index); + + emac_rx_error_callback_app(); +} + +/** + * @brief + * + */ +__WEAK void emac_rx_busy_callback_app(void) +{ +} + +/** + * @brief + * + */ +static void emac_rx_busy_callback(void) +{ + MSG("EMAC Rx busy at %s:%d\r\n", __func__, __LINE__); + emac_rx_busy_callback_app(); +} + +/** + * @brief + * + * @param emac_cfg + * @return int + */ +int emac_init(emac_device_t *emac_cfg) +{ + EMAC_CFG_Type emacCfg = { + .recvSmallFrame = ENABLE, /*!< Receive small frmae or not */ + .recvHugeFrame = DISABLE, /*!< Receive huge frmae(>64K bytes) or not */ + .padEnable = ENABLE, /*!< Enable padding for frame which is less than MINFL or not */ + .crcEnable = ENABLE, /*!< Enable hardware CRC or not */ + .noPreamble = DISABLE, /*!< Enable preamble or not */ + .recvBroadCast = ENABLE, /*!< Receive broadcast frame or not */ + .interFrameGapCheck = ENABLE, /*!< Check inter frame gap or not */ + .miiNoPreamble = ENABLE, /*!< Enable MII interface preamble or not */ + .miiClkDiv = 49, /*!< MII interface clock divider from bus clock */ + .maxTxRetry = 16, /*!< Maximum tx retry count */ + .interFrameGapValue = 24, /*!< Inter frame gap vaule in clock cycles(default 24)*/ + .minFrameLen = 64, /*!< Minimum frame length */ + .maxFrameLen = 1500, /*!< Maximum frame length */ + .collisionValid = 16, /*!< Collision valid value */ + .macAddr[0] = 0x18, /*!< MAC Address */ + .macAddr[1] = 0xB0, + .macAddr[2] = 0x09, + .macAddr[3] = 0x00, + .macAddr[4] = 0x12, + .macAddr[5] = 0x34, + }; + BL_Err_Type err = SUCCESS; + + /* init emac giio */ + emac_gpio_init(); + + memcpy(emacCfg.macAddr, emac_cfg->mac_addr, 6); +#if EMAC_USE_INSIDE_CLOCK + //enable audio clock */ + PDS_Enable_PLL_Clk(PDS_PLL_CLK_48M); + PDS_Set_Audio_PLL_Freq(AUDIO_PLL_50000000_HZ); + + GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_INSIDE_50M); +#else + GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_OUTSIDE_50M); +#endif + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC); + //GLB_Invert_ETH_RX_CLK(0); + //GLB_Invert_ETH_TX_CLK(0); + EMAC_Init(&emacCfg); + + EMAC_Int_Callback_Install(EMAC_INT_TX_DONE_IDX, emac_tx_done_callback); + EMAC_Int_Callback_Install(EMAC_INT_TX_ERROR_IDX, emac_tx_error_callback); + + EMAC_Int_Callback_Install(EMAC_INT_RX_DONE_IDX, emac_rx_done_callback); + EMAC_Int_Callback_Install(EMAC_INT_RX_ERROR_IDX, emac_rx_error_callback); + + EMAC_Int_Callback_Install(EMAC_INT_RX_BUSY_IDX, emac_rx_busy_callback); + + CPU_Interrupt_Enable(EMAC_IRQn); + + EMAC_ClrIntStatus(EMAC_INT_ALL); + EMAC_IntMask(EMAC_INT_ALL, UNMASK); + + //EMAC_Enable(); + + return err; +} + +/** + * @brief + * + * @param eth_tx_buff + * @param tx_buf_count + * @param eth_rx_buff + * @param rx_buf_count + * @return int + */ +int emac_bd_init(uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count) +{ + BL_Err_Type err = SUCCESS; + thiz = ðHandle; + + /* init the BDs in emac with buffer address */ + err = EMAC_DMADescListInit(thiz, (uint8_t *)eth_tx_buff, tx_buf_count, + (uint8_t *)eth_rx_buff, rx_buf_count); + return err; +} + +/** + * @brief + * + * @param flags + * @param len + * @param data_in + * @return int + */ +int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in) +{ + BL_Err_Type err = SUCCESS; + EMAC_BD_Desc_Type *DMADesc; + + DMADesc = &thiz->bd[thiz->txIndexCPU]; + + if ((uint32_t)(-1) == flags) { + flags = EMAC_TX_COMMON_FLAGS; + } + + if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(TX_RD)) { + /* no free BD, lost sync with DMA TX? */ + err = NORESC; + //MSG_ERR(TAG"%s:%d\n", __func__, __LINE__); + } else { + //DMADesc->TXBuffer = (uint32_t)data_in; + ARCH_MemCpy_Fast((void *)DMADesc->Buffer, data_in, len); + + DMADesc->C_S_L = flags | (len << BD_TX_LEN_POS); + + /* move to next TX BD */ + if ((++thiz->txIndexCPU) > thiz->txBuffLimit) { + /* the last BD */ + DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(TX_WR); + /* wrap back */ + thiz->txIndexCPU = 0; + } + } + + return err; +} + +/** + * @brief + * + * @param flags + * @param len + * @param data_out + * @return int + */ +int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out) +{ + BL_Err_Type err = SUCCESS; + EMAC_BD_Desc_Type *DMADesc; + + DMADesc = &thiz->bd[thiz->rxIndexCPU]; + + if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(RX_E)) { + /* current RX BD is empty */ + err = NORESC; + *len = 0; + } else { + *len = (thiz->bd[thiz->rxIndexCPU].C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS; + + if (data_out) { + ARCH_MemCpy_Fast(data_out, (const void *)DMADesc->Buffer, *len); + } + + /* RX BD can be used for another receive */ + DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_E); + + /* move to next RX BD */ + if ((++thiz->rxIndexCPU) > thiz->rxBuffLimit) { + /* the last BD */ + DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_WR); + /* wrap back */ + thiz->rxIndexCPU = thiz->txBuffLimit + 1; + } + } + + return err; +} + +/** + * @brief + * + * @param phyAddress + * @return int + */ +int emac_phy_set_address(uint16_t phyAddress) +{ + EMAC_Phy_SetAddress(phyAddress); + + return 0; +} + +/** + * @brief + * + * @param fullDuplex + * @return int + */ +int emac_phy_config_full_duplex(uint8_t fullDuplex) +{ + EMAC_Phy_Set_Full_Duplex(fullDuplex); + + return 0; +} + +/** + * @brief + * + * @param phyReg + * @param regValue + * @return int + */ +int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue) +{ + if (EMAC_Phy_Read(phyReg, regValue) != SUCCESS) { + return -1; + } + + return 0; +} + +/** + * @brief + * + * @param phyReg + * @param regValue + * @return int + */ +int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue) +{ + if (EMAC_Phy_Write(phyReg, regValue) != SUCCESS) { + return -1; + } + + return 0; +} + +int emac_stop() +{ + return 0; +} + +int emac_start() +{ + EMAC_Enable(); + return 0; +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_flash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..de6610edc420e9404072afc151dfdff973779ead --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_flash.c @@ -0,0 +1,285 @@ +/** + * @file hal_flash.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl702_glb.h" +#include "bl702_xip_sflash.h" +#include "bl702_xip_sflash_ext.h" +#include "bl702_sf_cfg.h" +#include "bl702_sf_cfg_ext.h" +#include "hal_flash.h" + +static SPI_Flash_Cfg_Type g_flash_cfg; + +/** + * @brief flash_get_cfg + * + * @return BL_Err_Type + */ +BL_Err_Type flash_get_cfg(uint8_t **cfg_addr,uint32_t *len) +{ + *cfg_addr = (uint8_t *)&g_flash_cfg; + *len = sizeof(SPI_Flash_Cfg_Type); + + return SUCCESS; +} + +/** + * @brief flash_set_qspi_enable + * + * @return BL_Err_Type + */ +static BL_Err_Type ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) +{ + if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { + SFlash_Qspi_Enable(p_flash_cfg); + } + + return SUCCESS; +} + +/** + * @brief flash_set_l1c_wrap + * + * @return BL_Err_Type + */ +static BL_Err_Type ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) +{ + if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) { + L1C_Set_Wrap(DISABLE); + } else { + L1C_Set_Wrap(ENABLE); + if((p_flash_cfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (p_flash_cfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) { + SFlash_SetBurstWrap(p_flash_cfg); + } + } + + return SUCCESS; +} + +/** + * @brief flash_config_init + * + * @return BL_Err_Type + */ +static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) +{ + BL_Err_Type ret = ERROR; + uint32_t jid = 0; + uint32_t offset = 0; + + __disable_irq(); + XIP_SFlash_Opt_Enter(); + XIP_SFlash_State_Save(p_flash_cfg, &offset); + SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid); + arch_memcpy(jedec_id, (uint8_t *)&jid, 3); + jid &= 0xFFFFFF; + ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg); + if (ret == SUCCESS) { + p_flash_cfg->mid = (jid&0xff); + } + + /* Set flash controler from p_flash_cfg */ + flash_set_qspi_enable(p_flash_cfg); + flash_set_l1c_wrap(p_flash_cfg); + XIP_SFlash_State_Restore(p_flash_cfg, p_flash_cfg->ioMode & 0x0f, offset); + XIP_SFlash_Opt_Exit(); + __enable_irq(); + + return ret; +} + +/** + * @brief multi flash adapter + * + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_init(void) +{ + BL_Err_Type ret = ERROR; + uint8_t clkDelay = 1; + uint8_t clkInvert = 1; + uint32_t jedec_id = 0; + + __disable_irq(); + L1C_Cache_Flush_Ext(); + SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg); + L1C_Cache_Flush_Ext(); + __enable_irq(); + if (g_flash_cfg.mid != 0xff) { + return SUCCESS; + } + clkDelay = g_flash_cfg.clkDelay; + clkInvert = g_flash_cfg.clkInvert; + g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f; + + ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); + MSG("flash ID = %08x\r\n", jedec_id); + bflb_platform_dump((uint8_t *)&g_flash_cfg, sizeof(g_flash_cfg)); + if (ret != SUCCESS) { + MSG("flash config init fail!\r\n"); + } + g_flash_cfg.clkDelay = clkDelay; + g_flash_cfg.clkInvert = clkInvert; + + return ret; +} + +/** + * @brief read jedec id + * + * @param data + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data) +{ + uint32_t jid = 0; + + __disable_irq(); + XIP_SFlash_Opt_Enter(); + XIP_SFlash_GetJedecId_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, (uint8_t *)&jid); + XIP_SFlash_Opt_Exit(); + __enable_irq(); + jid &= 0xFFFFFF; + arch_memcpy(data, (void *)&jid, 4); + + return SUCCESS; +} + +/** + * @brief read flash data via xip + * + * @param addr + * @param data + * @param len + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len) +{ + __disable_irq(); + L1C_Cache_Flush_Ext(); + XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len); + L1C_Cache_Flush_Ext(); + __enable_irq(); + + return SUCCESS; +} + +/** + * @brief flash read data + * + * @param addr + * @param data + * @param len + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t len) +{ + BL_Err_Type ret = ERROR; + + XIP_SFlash_Opt_Enter(); + ret = XIP_SFlash_Read_With_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len); + XIP_SFlash_Opt_Exit(); + + return ret; +} + +/** + * @brief flash write data + * + * @param addr + * @param data + * @param len + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t len) +{ + BL_Err_Type ret = ERROR; + + XIP_SFlash_Opt_Enter(); + ret = XIP_SFlash_Write_With_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len); + XIP_SFlash_Opt_Exit(); + + return ret; +} + +/** + * @brief flash erase + * + * @param startaddr + * @param endaddr + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len) +{ + BL_Err_Type ret = ERROR; + + XIP_SFlash_Opt_Enter(); + ret = XIP_SFlash_Erase_With_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, startaddr, len); + XIP_SFlash_Opt_Exit(); + + return ret; +} + +/** + * @brief set flash cache + * + * @param cont_read + * @param cache_enable + * @param cache_way_disable + * @param flash_offset + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) +{ + uint32_t tmp[1]; + BL_Err_Type stat; + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + + XIP_SFlash_Opt_Enter(); + /* To make it simple, exit cont read anyway */ + SFlash_Reset_Continue_Read(&g_flash_cfg); + + if (g_flash_cfg.cReadSupport == 0) { + cont_read = 0; + } + + if (cont_read == 1) { + stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); + + if (SUCCESS != stat) { + XIP_SFlash_Opt_Exit(); + return ERROR; + } + } + + /* Set default value */ + L1C_Cache_Enable_Set(0xf); + + if (cache_enable) { + SF_Ctrl_Set_Flash_Image_Offset(flash_offset); + SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable); + } + XIP_SFlash_Opt_Exit(); + + return SUCCESS; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..53cb4dd3fcba29184fa9a064fadafa615af941a2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c @@ -0,0 +1,234 @@ +/** + * @file hal_gpio.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl702_glb.h" +#include "bl702_gpio.h" +#include "hal_gpio.h" + +static void GPIO_IRQ(void); + +struct gpio_int_cfg_private { + slist_t list; + uint32_t pin; + void (*cbfun)(uint32_t pin); +}; + +static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head); + +/** + * @brief + * + * @param pin + * @param mode + */ +void gpio_set_mode(uint32_t pin, uint32_t mode) +{ + GLB_GPIO_Cfg_Type gpio_cfg; + + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioPin = pin; + gpio_cfg.drive = 0; + gpio_cfg.smtCtrl = 1; + + switch (mode) { + case GPIO_OUTPUT_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_NONE; + break; + + case GPIO_OUTPUT_PP_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_UP; + break; + + case GPIO_OUTPUT_PD_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_DOWN; + break; + + case GPIO_INPUT_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_NONE; + break; + + case GPIO_INPUT_PP_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_UP; + break; + + case GPIO_INPUT_PD_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_DOWN; + break; + case GPIO_HZ_MODE: + GLB_GPIO_Set_HZ(pin); + default: + CPU_Interrupt_Disable(GPIO_INT0_IRQn); + GLB_GPIO_IntMask(pin, MASK); + + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + + if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE); + } + + else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE); + } + + else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL); + } + + else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL); + } + + else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_PULSE); + } + + else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_PULSE); + } + + else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_LEVEL); + } + + else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL); + } + + else { + return; + } + + break; + } + + GLB_GPIO_Init(&gpio_cfg); +} +/** + * @brief + * + * @param pin + * @param value + */ +void gpio_write(uint32_t pin, uint32_t value) +{ + uint32_t tmp = BL_RD_REG(GLB_BASE, GLB_GPIO_OUTPUT); + + if (value) + tmp |= (1 << pin); + else + tmp &= ~(1 << pin); + + BL_WR_REG(GLB_BASE, GLB_GPIO_OUTPUT, tmp); +} +/** + * @brief + * + * @param pin + */ +void gpio_toggle(uint32_t pin) +{ + uint32_t tmp = BL_RD_REG(GLB_BASE, GLB_GPIO_OUTPUT); + tmp ^= (1 << pin); + BL_WR_REG(GLB_BASE, GLB_GPIO_OUTPUT, tmp); +} +/** + * @brief + * + * @param pin + * @return int + */ +int gpio_read(uint32_t pin) +{ + return ((BL_RD_REG(GLB_BASE, GLB_GPIO_INPUT) & (1 << pin)) ? 1 : 0); +} +/** + * @brief + * + * @param pin + * @param cbFun + */ +void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)) +{ + struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private)); + int_cfg->cbfun = cbfun; + int_cfg->pin = pin; + slist_add_tail(&gpio_int_head, &int_cfg->list); + CPU_Interrupt_Disable(GPIO_INT0_IRQn); + Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_IRQ); + CPU_Interrupt_Enable(GPIO_INT0_IRQn); +} +/** + * @brief + * + * @param pin + * @param enabled + */ +void gpio_irq_enable(uint32_t pin, uint8_t enabled) +{ + if (enabled) { + GLB_GPIO_IntMask(pin, UNMASK); + } else { + GLB_GPIO_IntMask(pin, MASK); + } +} + +static void GPIO_IRQ(void) +{ + slist_t *i; + uint32_t timeOut = 0; +#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) + slist_for_each(i, &gpio_int_head) + { + struct gpio_int_cfg_private *int_cfg = slist_entry(i, struct gpio_int_cfg_private, list); + + if (SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) { + int_cfg->cbfun(int_cfg->pin); + GLB_GPIO_IntClear(int_cfg->pin, SET); + /* timeout check */ + timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT; + + do { + timeOut--; + } while ((SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) && timeOut); + + if (!timeOut) { + MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + + GLB_GPIO_IntClear(int_cfg->pin, RESET); + } + } +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2c.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..f998fdc98e2ebf24e0b56200d3743eed89b67f5f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2c.c @@ -0,0 +1,174 @@ +/** + * @file hal_i2c.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_i2c.h" +#include "hal_gpio.h" +#include "bl702_i2c.h" +#include "bl702_i2c_gpio_sim.h" +#include "bl702_glb.h" + +static i2c_device_t i2cx_device[I2C_MAX_INDEX] = { +#ifdef BSP_USING_I2C0 + I2C0_CONFIG, +#endif +#ifdef BSP_USING_I2C1 + I2C1_CONFIG, +#endif +}; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int i2c_open(struct device *dev, uint16_t oflag) +{ + i2c_device_t *i2c_device = (i2c_device_t *)dev; + + if (i2c_device->mode == I2C_HW_MODE) { + I2C_SetPrd(i2c_device->id, i2c_device->phase); + } + + return 0; +} + +// int i2c_close(struct device *dev) +// { + +// return 0; +// } + +// int i2c_control(struct device *dev, int cmd, void *args) +// { +// //i2c_device_t *i2c_device = (i2c_device_t *)dev; + +// switch (cmd) +// { +// case DEVICE_CTRL_SET_INT /* constant-expression */: + +// break; +// case DEVICE_CTRL_CLR_INT /* constant-expression */: +// /* code */ +// /* Enable UART interrupt*/ + +// break; +// case DEVICE_CTRL_GET_INT /* constant-expression */: +// /* code */ +// break; +// case DEVICE_CTRL_CONFIG /* constant-expression */: +// /* code */ +// break; +// case 4 /* constant-expression */: +// /* code */ +// break; +// case 5 /* constant-expression */: +// /* code */ +// break; +// default: +// break; +// } + +// return 0; +// } +// int i2c_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +// { + +// return 0; +// } +// int i2c_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +// { + +// return 0; +// } +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int i2c_register(enum i2c_index_type index, const char *name) +{ + struct device *dev; + + if (I2C_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(i2cx_device[index].parent); + + dev->open = i2c_open; + dev->close = NULL; + dev->control = NULL; + dev->write = NULL; + dev->read = NULL; + + dev->type = DEVICE_CLASS_I2C; + dev->handle = NULL; + + return device_register(dev, name); +} +/** + * @brief + * + * @param dev + * @param msgs + * @param num + * @return uint32_t + */ +int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num) +{ + i2c_msg_t *msg; + I2C_Transfer_Cfg i2cCfg = { 0 }; + + i2c_device_t *i2c_device = (i2c_device_t *)dev; + + if (i2c_device->mode == I2C_HW_MODE) { + for (uint32_t i = 0; i < num; i++) { + msg = &msgs[i]; + i2cCfg.slaveAddr = msg->slaveaddr; + i2cCfg.stopEveryByte = DISABLE; + i2cCfg.subAddr = msg->subaddr; + i2cCfg.dataSize = msg->len; + i2cCfg.data = msg->buf; + + if (msg->flags & SUB_ADDR_0BYTE) { + i2cCfg.subAddrSize = 0; + } else if (msg->flags & SUB_ADDR_1BYTE) { + i2cCfg.subAddrSize = 1; + } else if (msg->flags & SUB_ADDR_2BYTE) { + i2cCfg.subAddrSize = 2; + } + + if ((msg->flags & I2C_RW_MASK) == I2C_WR) { + return I2C_MasterSendBlocking(i2c_device->id, &i2cCfg); + } else if ((msg->flags & I2C_RW_MASK) == I2C_RD) { + return I2C_MasterReceiveBlocking(i2c_device->id, &i2cCfg); + } + } + } else { + } + + return 0; +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2s.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..d404e54d549a77017a51501ffcc3908e17057a90 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2s.c @@ -0,0 +1,390 @@ +/** + * @file hal_i2s.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_i2s.h" +#include "hal_dma.h" +#include "bl702_i2s.h" +#include "bl702_glb.h" +#include "i2s_config.h" + +static i2s_device_t i2sx_device[I2S_MAX_INDEX] = { +#ifdef BSP_USING_I2S0 + I2S0_CONFIG, +#endif +}; + +int i2s_open(struct device *dev, uint16_t oflag) +{ + i2s_device_t *i2s_device = (i2s_device_t *)dev; + I2S_CFG_Type i2sCfg = { 0 }; + I2S_FifoCfg_Type fifoCfg = { 0 }; + + GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK); + GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE); + + /*Finding the right frequency*/ + if (12288000 % (i2s_device->sampl_freq_hz) == 0) { + i2sCfg.audioFreqHz = 12288000; + PDS_Set_Audio_PLL_Freq(AUDIO_PLL_12288000_HZ); + } else if (11289600 % (i2s_device->sampl_freq_hz) == 0) { + i2sCfg.audioFreqHz = 11289600; + PDS_Set_Audio_PLL_Freq(AUDIO_PLL_11289600_HZ); + } else if (5644800 % (i2s_device->sampl_freq_hz) == 0) { + i2sCfg.audioFreqHz = 5644800; + PDS_Set_Audio_PLL_Freq(AUDIO_PLL_5644800_HZ); + } else { + switch (I2S_ADUIO_PLL_DEFAULT) { + case AUDIO_PLL_12288000_HZ: + i2sCfg.audioFreqHz = 12288000; + break; + + case AUDIO_PLL_11289600_HZ: + i2sCfg.audioFreqHz = 11289600; + break; + + case AUDIO_PLL_5644800_HZ: + i2sCfg.audioFreqHz = 5644800; + break; + + default: + return ERROR; + break; + } + + PDS_Set_Audio_PLL_Freq(I2S_ADUIO_PLL_DEFAULT); + } + + i2sCfg.sampleFreqHz = i2s_device->sampl_freq_hz; + + /*!< default I2S msb first */ + i2sCfg.endianType = I2S_DATA_ENDIAN; + + /* Config the I2S type */ + switch (i2s_device->interface_mode) { + case I2S_MODE_STD: + i2sCfg.modeType = I2S_MODE_I2S_LEFT; + i2sCfg.fsMode = I2S_FS_MODE_EVEN; + i2sCfg.dataOffset = 1; + break; + + case I2S_MODE_LEFT: + i2sCfg.modeType = I2S_MODE_I2S_LEFT; + i2sCfg.fsMode = I2S_FS_MODE_EVEN; + i2sCfg.dataOffset = 0; + break; + + case I2S_MODE_RIGHT: + i2sCfg.modeType = I2S_MODE_I2S_RIGHT; + i2sCfg.fsMode = I2S_FS_MODE_EVEN; + i2sCfg.dataOffset = 0; + break; + + case I2S_MODE_DSP_A: + i2sCfg.modeType = I2S_MODE_I2S_DSP; + i2sCfg.fsMode = I2S_FS_MODE_1T; + i2sCfg.dataOffset = 1; + break; + + case I2S_MODE_DSP_B: + i2sCfg.modeType = I2S_MODE_I2S_DSP; + i2sCfg.fsMode = I2S_FS_MODE_1T; + i2sCfg.dataOffset = 0; + break; + + default: + return ERROR; + break; + } + + /* Config the frame/data Size */ + switch (i2s_device->frame_size) { + case I2S_FRAME_LEN_8: + i2sCfg.frameSize = I2S_SIZE_FRAME_8; + break; + + case I2S_FRAME_LEN_16: + i2sCfg.frameSize = I2S_SIZE_FRAME_16; + break; + + case I2S_FRAME_LEN_24: + i2sCfg.frameSize = I2S_SIZE_FRAME_24; + break; + + case I2S_FRAME_LEN_32: + i2sCfg.frameSize = I2S_SIZE_FRAME_32; + break; + + default: + return ERROR; + break; + } + + switch (i2s_device->data_size) { + case I2S_DATA_LEN_8: + i2sCfg.dataSize = I2S_SIZE_DATA_8; + break; + + case I2S_DATA_LEN_16: + i2sCfg.dataSize = I2S_SIZE_DATA_16; + break; + + case I2S_DATA_LEN_24: + i2sCfg.dataSize = I2S_SIZE_DATA_24; + break; + + case I2S_DATA_LEN_32: + i2sCfg.dataSize = I2S_SIZE_DATA_32; + break; + + default: + return ERROR; + break; + } + + fifoCfg.lRMerge = DISABLE; + fifoCfg.frameDataExchange = DISABLE; + + /* Config the Channel number */ + switch (i2s_device->channel_num) { + case I2S_FS_CHANNELS_NUM_MONO: + i2sCfg.monoMode = ENABLE; + i2sCfg.fsChannel = I2S_FS_CHANNELS_2; + i2sCfg.monoModeChannel = I2S_MONO_CHANNEL; + break; + + case I2S_FS_CHANNELS_NUM_2: + i2sCfg.monoMode = DISABLE; + i2sCfg.fsChannel = I2S_FS_CHANNELS_2; + + if (i2s_device->data_size == I2S_DATA_LEN_8 || i2s_device->data_size == I2S_DATA_LEN_16) { + fifoCfg.lRMerge = ENABLE; + fifoCfg.frameDataExchange = I2S_LR_EXCHANGE; + } + + break; + + case I2S_FS_CHANNELS_NUM_3: + if ((i2s_device->interface_mode != I2S_MODE_DSP_A) && (i2s_device->interface_mode != I2S_MODE_DSP_B)) { + return ERROR; + } + + i2sCfg.monoMode = DISABLE; + i2sCfg.fsChannel = I2S_FS_CHANNELS_3; + break; + + case I2S_FS_CHANNELS_NUM_4: + if ((i2s_device->interface_mode != I2S_MODE_DSP_A) && (i2s_device->interface_mode != I2S_MODE_DSP_B)) { + return ERROR; + } + + i2sCfg.monoMode = DISABLE; + i2sCfg.fsChannel = I2S_FS_CHANNELS_4; + + default: + return ERROR; + break; + } + + /* Config the bclk/fs invert */ + i2sCfg.bclkInvert = I2S_BCLK_INVERT; + i2sCfg.fsInvert = I2S_FS_INVERT; + + if (oflag & DEVICE_OFLAG_INT_TX) { + } + + if (oflag & DEVICE_OFLAG_INT_RX) { + } + + fifoCfg.txfifoDmaEnable = (oflag & DEVICE_OFLAG_DMA_TX) ? ENABLE : DISABLE; + fifoCfg.rxfifoDmaEnable = (oflag & DEVICE_OFLAG_DMA_RX) ? ENABLE : DISABLE; + fifoCfg.txFifoLevel = i2s_device->fifo_threshold; + fifoCfg.rxFifoLevel = i2s_device->fifo_threshold; + + /* I2S Init */ + I2S_Disable(); + I2S_Init(&i2sCfg); + I2S_FifoConfig(&fifoCfg); + + if (i2s_device->iis_mode == I2S_MODE_MASTER) + I2S_Enable(I2S_ROLE_MASTER); + else if (i2s_device->iis_mode == I2S_MODE_SLAVE) + I2S_Enable(I2S_ROLE_SLAVE); + return SUCCESS; +} + +int i2s_close(struct device *dev) +{ + //i2s_device_t* uart_device = (i2s_device_t*)dev; + I2S_Disable(); + return SUCCESS; +} + +int i2s_control(struct device *dev, int cmd, void *args) +{ + i2s_device_t *i2s_device = (i2s_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT: + for (uint16_t i = 0, j = 1; i < 8; i++, j <<= 1) { + if ((uint32_t)args & j) { + /* code */ + } + } + + break; + + case DEVICE_CTRL_CLR_INT: + for (uint16_t i = 0, j = 1; i < 8; i++, j <<= 1) { + if ((uint32_t)args & j) { + /* code */ + } + } + + break; + + case DEVICE_CTRL_GET_INT: + /* code */ + break; + + case DEVICE_CTRL_RESUME: + /* code */ + break; + + case DEVICE_CTRL_SUSPEND: + /* code */ + break; + + case DEVICE_CTRL_CONFIG: + /* code */ + break; + + case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */: + i2s_device->tx_dma = (struct device *)args; + break; + + case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */: + i2s_device->rx_dma = (struct device *)args; + break; + + case DEVICE_CTRL_GET_CONFIG: + switch ((uint32_t)args) { + case I2S_GET_TX_FIFO_CMD: + return I2S_GetTxFIFO_AvlCnt(); + + case I2S_GET_RX_FIFO_CMD: + return I2S_GetRxFIFO_AvlCnt(); + + default: + break; + } + + break; + + default: + return ERROR; + break; + } + + return SUCCESS; +} + +int i2s_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + i2s_device_t *i2s_device = (i2s_device_t *)dev; + + if (dev->oflag & DEVICE_OFLAG_DMA_TX) { + struct device *dma_ch = (struct device *)i2s_device->tx_dma; + + if (!dma_ch) { + return -1; + } + + if (i2s_device->id == 0) { + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_I2S_TDR, size); + dma_channel_start(dma_ch); + } else if (i2s_device->id == 1) { + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_I2S_TDR, size); + dma_channel_start(dma_ch); + } + + return 0; + } else { + return 0; + } +} + +int i2s_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + i2s_device_t *i2s_device = (i2s_device_t *)dev; + + if (dev->oflag & DEVICE_OFLAG_DMA_RX) { + struct device *dma_ch = (struct device *)i2s_device->rx_dma; + + if (!dma_ch) { + return -1; + } + + if (i2s_device->id == 0) { + dma_reload(dma_ch, (uint32_t)DMA_ADDR_I2S_RDR, (uint32_t)buffer, size); + dma_channel_start(dma_ch); + } else if (i2s_device->id == 1) { + dma_reload(dma_ch, (uint32_t)DMA_ADDR_I2S_RDR, (uint32_t)buffer, size); + dma_channel_start(dma_ch); + } + + return 0; + } else { + return 0; + } +} + +int i2s_register(enum i2s_index_type index, const char *name) +{ + struct device *dev; + + if (I2S_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(i2sx_device[index].parent); + + dev->open = i2s_open; + dev->close = i2s_close; + dev->control = i2s_control; + dev->write = i2s_write; + dev->read = i2s_read; + + dev->type = DEVICE_CLASS_I2S; + dev->handle = NULL; + + return device_register(dev, name); +} + +void i2s_isr(i2s_device_t *handle) +{ + return; +} + +void I2S_IRQ(void) +{ + i2s_isr(&i2sx_device[0]); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_keyscan.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_keyscan.c new file mode 100644 index 0000000000000000000000000000000000000000..7353f7cbf032110c935e22964e19cc392533acef --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_keyscan.c @@ -0,0 +1,159 @@ +/** + * @file hal_keyscan.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_keyscan.h" +#include "kys_reg.h" +#include "bl702_glb.h" + +#ifdef BSP_USING_KEYSCAN +static void KeyScan_IRQ(void); +#endif + +static keyscan_device_t keyscan_device[KEYSCAN_MAX_INDEX] = { +#ifdef BSP_USING_KEYSCAN + KEYSCAN_CONFIG +#endif +}; + +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int keyscan_open(struct device *dev, uint16_t oflag) +{ + uint32_t tmpVal; + keyscan_device_t *keyscan_device = (keyscan_device_t *)dev; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + /* Set col and row */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_COL_NUM, keyscan_device->col_num - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM, keyscan_device->row_num - 1); + + /* Set idle duration between column scans */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_RC_EXT, 0); + + /* ghost key event detection not support*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_GHOST_EN, 0); + + if (keyscan_device->deglitch_count) { + /* Enable or disable deglitch function */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_EN, 1); + + /* Set deglitch count */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_CNT, keyscan_device->deglitch_count); + } else { + /* Enable or disable deglitch function */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_EN, 0); + + /* Set deglitch count */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_CNT, 0); + } + + /* Write back */ + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, tmpVal); + + return 0; +} + +int keyscan_control(struct device *dev, int cmd, void *args) +{ + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: +#ifdef BSP_USING_KEYSCAN + Interrupt_Handler_Register(KYS_IRQn, KeyScan_IRQ); +#endif + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 1); + CPU_Interrupt_Enable(KYS_IRQn); + break; + case DEVICE_CTRL_CLR_INT /* constant-expression */: + Interrupt_Handler_Register(KYS_IRQn, NULL); + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 0); + CPU_Interrupt_Disable(KYS_IRQn); + break; + case DEVICE_CTRL_GET_INT: + return (BL_RD_REG(KYS_BASE, KYS_KS_INT_STS) & 0xf); + case DEVICE_CTRL_RESUME: { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_SET_REG_BIT(tmpVal, KYS_KS_EN)); + } break; + case DEVICE_CTRL_SUSPEND: { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_CLR_REG_BIT(tmpVal, KYS_KS_EN)); + } break; + case DEVICE_CTRL_KEYSCAN_GET_KEYCODE: { + uint32_t *key_code = (uint32_t *)args; + *key_code = BL_RD_REG(KYS_BASE, KYS_KEYCODE_VALUE); + BL_WR_REG(KYS_BASE, KYS_KEYCODE_CLR, 0xf); + } break; + default: + break; + } + + return 0; +} +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int keyscan_register(enum keyscan_index_type index, const char *name) +{ + struct device *dev; + + if (KEYSCAN_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(keyscan_device[index].parent); + + dev->open = keyscan_open; + dev->close = NULL; + dev->control = keyscan_control; + dev->write = NULL; + dev->read = NULL; + + dev->type = DEVICE_CLASS_KEYSCAN; + dev->handle = NULL; + + return device_register(dev, name); +} + +#if defined(BSP_USING_KEYSCAN) +static void KeyScan_IRQ(void) +{ + if (keyscan_device[KEYSCAN_INDEX].parent.callback) { + keyscan_device[KEYSCAN_INDEX].parent.callback(&keyscan_device[KEYSCAN_INDEX].parent, (void *)(BL_RD_REG(KYS_BASE, KYS_KEYCODE_VALUE)), 0, KEYSCAN_EVENT_TRIG); + } + + BL_WR_REG(KYS_BASE, KYS_KEYCODE_CLR, 0xf); +} +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c new file mode 100644 index 0000000000000000000000000000000000000000..2ffa157a7d95e20b6c1f49c77c01b7d8092cbe19 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c @@ -0,0 +1,121 @@ +/** + * @file hal_mjpeg.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl702_mjpeg.h" +#include "bl702_glb.h" +#include "hal_mjpeg.h" + +void mjpeg_init(mjpeg_device_t *mjpeg_cfg) +{ + MJPEG_CFG_Type mjpegCfg = { + .burst = MJPEG_BURST_INCR16, + .quality = mjpeg_cfg->quality, + .yuv = mjpeg_cfg->yuv_format, + .waitCount = 0x400, + .bufferMjpeg = mjpeg_cfg->write_buffer_addr, + .sizeMjpeg = mjpeg_cfg->write_buffer_size, + .bufferCamYY = mjpeg_cfg->read_buffer_addr, + .sizeCamYY = mjpeg_cfg->read_buffer_size, + .bufferCamUV = 0, + .sizeCamUV = 0, + .resolutionX = mjpeg_cfg->resolution_x, + .resolutionY = mjpeg_cfg->resolution_y, + .bitOrderEnable = ENABLE, + .evenOrderEnable = ENABLE, + .swapModeEnable = DISABLE, + .overStopEnable = ENABLE, + .reflectDmy = DISABLE, + .verticalDmy = DISABLE, + .horizationalDmy = DISABLE, + }; + + static MJPEG_Packet_Type packetCfg = { + .packetEnable = DISABLE, + .endToTail = DISABLE, + .frameHead = 0, + .frameTail = DISABLE, + .packetHead = 0, + .packetBody = 0, + .packetTail = 0, + }; + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG); + + MJPEG_Init(&mjpegCfg); + + if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_DEFAULT) { + packetCfg.packetEnable = ENABLE; + packetCfg.packetHead = mjpeg_cfg->packet_head_length; + packetCfg.packetBody = mjpeg_cfg->packet_body_length; + packetCfg.packetTail = mjpeg_cfg->packet_tail_length; + } + + if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_FRAME_HEAD) { + packetCfg.frameHead = mjpeg_cfg->frame_head_length; + } + + if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_FRAME_TAIL) { + packetCfg.frameTail = ENABLE; + } + + if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_END_TAIL) { + packetCfg.endToTail = ENABLE; + } + + MJPEG_Packet_Config(&packetCfg); + + if (mjpeg_cfg->yuv_format == MJPEG_YUV_FORMAT_YUV422_INTERLEAVE) { + MJPEG_Set_YUYV_Order_Interleave(1, 0, 3, 2); + } +} + +void mjpeg_start(void) +{ + MJPEG_Enable(); +} + +void mjpeg_stop(void) +{ + MJPEG_Disable(); +} + +uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q) +{ + MJPEG_Frame_Info info; + arch_memset(&info, 0, sizeof(info)); + + MJPEG_Get_Frame_Info(&info); + + if (info.validFrames == 0) { + return ERROR; + } + + *pic = (uint8_t *)(info.curFrameAddr); + *len = info.curFrameBytes; + *q = info.curFrameQ; + + return SUCCESS; +} + +void mjpeg_drop_one_frame(void) +{ + MJPEG_Pop_Frame(); +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mtimer.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mtimer.c new file mode 100644 index 0000000000000000000000000000000000000000..a243e20fdb9016edc0800c4f4428af3e051df32e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mtimer.c @@ -0,0 +1,142 @@ +/** + * @file hal_mtimer.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_mtimer.h" +#include "bl702_glb.h" + +static void (*systick_callback)(void); +static uint64_t next_compare_tick = 0; +static uint64_t current_set_ticks = 0; + +static void Systick_Handler(void) +{ + *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick; + systick_callback(); + next_compare_tick += current_set_ticks; +} + +/** + * @brief + * + * @param time + * @param interruptFun + */ +void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)) +{ + CPU_Interrupt_Disable(MTIME_IRQn); + + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t *const pulTimeHigh = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); + volatile uint32_t *const pulTimeLow = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME); + volatile uint32_t ulHartId = 0; + + current_set_ticks = ticks; + systick_callback = interruptfun; + + __asm volatile("csrr %0, mhartid" + : "=r"(ulHartId)); + + do { + ulCurrentTimeHigh = *pulTimeHigh; + ulCurrentTimeLow = *pulTimeLow; + } while (ulCurrentTimeHigh != *pulTimeHigh); + + next_compare_tick = (uint64_t)ulCurrentTimeHigh; + next_compare_tick <<= 32ULL; + next_compare_tick |= (uint64_t)ulCurrentTimeLow; + next_compare_tick += (uint64_t)current_set_ticks; + + *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick; + + /* Prepare the time to use after the next tick interrupt. */ + next_compare_tick += (uint64_t)current_set_ticks; + + Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler); + CPU_Interrupt_Enable(MTIME_IRQn); +} + +/** + * @brief + * + * @return uint64_t + */ +uint64_t mtimer_get_time_ms() +{ + return mtimer_get_time_us() / 1000; +} +/** + * @brief + * + * @return uint64_t + */ +uint64_t mtimer_get_time_us() +{ + uint32_t tmpValLow, tmpValHigh, tmpValHigh1; + + do { + tmpValLow = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME); + tmpValHigh = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); + tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); + } while (tmpValHigh != tmpValHigh1); + + return (((uint64_t)tmpValHigh << 32) + tmpValLow); +} +/** + * @brief + * + * @param time + */ +void mtimer_delay_ms(uint32_t time) +{ + uint64_t cnt = 0; + uint32_t clock = SystemCoreClockGet(); + uint64_t startTime = mtimer_get_time_ms(); + + while (mtimer_get_time_ms() - startTime < time) { + cnt++; + + /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/ + if (cnt > (time * (clock >> (10 + 5))) * 2) { + break; + } + } +} +/** + * @brief + * + * @param time + */ +void mtimer_delay_us(uint32_t time) +{ + uint64_t cnt = 0; + uint32_t clock = SystemCoreClockGet(); + uint64_t startTime = mtimer_get_time_us(); + + while (mtimer_get_time_us() - startTime < time) { + cnt++; + + /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/ + if (cnt > (time * (clock >> (10 + 5))) * 2) { + break; + } + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm.c new file mode 100644 index 0000000000000000000000000000000000000000..8d8ecac8110948fad0a548bd25b1a4774d2d282c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm.c @@ -0,0 +1,1208 @@ +/** + * @file hal_pm.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl702_sflash.h" +#include "bl702_glb.h" +#include "hal_pm.h" +#include "hal_clock.h" +#include "hal_rtc.h" +#include "hal_flash.h" + +#define PM_PDS_FLASH_POWER_OFF 1 +#define PM_PDS_EXTERNAL_XTAL_32M_POWER_OFF 1 +#define PM_PDS_DLL_POWER_OFF 1 +#define PM_PDS_PLL_POWER_OFF 1 +#define PM_PDS_RF_POWER_OFF 1 +#define PM_PDS_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V +#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_0P90V + +void HBN_OUT0_IRQ(void); +void HBN_OUT1_IRQ(void); + +/** @defgroup Hal_Power_Global_Variables + * + * @brief PDS level config + * @{ + */ +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel0 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel4 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel5 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel6 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel31 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 0, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 1, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 1, + .MiscRst = 1, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; + +/****************************************************************************/ /** + * @brief PDS update flash_ctrl setting + * + * @param fastClock: fast clock + * + * @return None + * +*******************************************************************************/ +static ATTR_TCM_SECTION void PDS_Update_Flash_Ctrl_Setting(uint8_t fastClock) +{ + if (fastClock) { + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_72M, 0); + } else { + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0); + } + + SF_Ctrl_Set_Clock_Delay(fastClock); +} +/** + * @brief power management in pds(power down sleep) mode + * + * cpu's behavior after wakeup depend on psd level,see flow table if cpu off , cpu will reset after wakeup + * + * PD_CORE PD_CORE_MISC_DIG PD_CORE_MISC_ANA PD_CORE_CPU PD_BZ PD_USB + * PDS0 ON ON ON ON ON ON + * PDS1 ON ON ON ON ON OFF + * PDS2 ON ON ON ON OFF ON + * PDS3 ON ON ON ON OFF OFF + * PDS4 ON ON ON OFF ON ON + * PDS5 ON ON ON OFF ON OFF + * PDS6 ON ON ON OFF OFF ON + * PDS7 ON ON ON OFF OFF OFF + * PDS31 ON OFF OFF OFF OFF OFF + */ +ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint8_t sleep_time) +{ + PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL; + uint32_t tmpVal; + SPI_Flash_Cfg_Type *flash_cfg; + uint32_t flash_cfg_len; + + /* To make it simple and safe*/ + __disable_irq(); + + flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len); + HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT); + + PDS_WAKEUP_IRQHandler_Install(); + HBN_Clear_IRQ(HBN_INT_GPIO9); + HBN_Clear_IRQ(HBN_INT_GPIO10); + HBN_Clear_IRQ(HBN_INT_GPIO11); + HBN_Clear_IRQ(HBN_INT_GPIO12); + HBN_Clear_IRQ(HBN_INT_GPIO13); + HBN_Clear_IRQ(HBN_INT_ACOMP0); + HBN_Clear_IRQ(HBN_INT_ACOMP1); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal &= ~(1 << 8); //unmask pds wakeup + + if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK) || !(BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1) == 0xffffffff)) + tmpVal |= (1 << 19); //enable gpio wakeup for pds + if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT)) + tmpVal |= (1 << 17); //enable hbn out0 wakeup for pds + + if (sleep_time) + tmpVal |= (1 << 16); //unmask pds sleep time wakeup + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + PDS_Set_Vddcore_GPIO_IntClear(); + PDS_IntClear(); + + /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */ + CPU_Interrupt_Enable(PDS_WAKEUP_IRQn); + + switch (pds_level) { + case PM_PDS_LEVEL_0: + pPdsCfg = &pdsCfgLevel0; + break; + case PM_PDS_LEVEL_1: + pPdsCfg = &pdsCfgLevel1; + break; + case PM_PDS_LEVEL_2: + pPdsCfg = &pdsCfgLevel2; + break; + case PM_PDS_LEVEL_3: + pPdsCfg = &pdsCfgLevel3; + break; + case PM_PDS_LEVEL_4: + pPdsCfg = &pdsCfgLevel4; + break; + case PM_PDS_LEVEL_5: + pPdsCfg = &pdsCfgLevel5; + break; + case PM_PDS_LEVEL_6: + pPdsCfg = &pdsCfgLevel6; + break; + case PM_PDS_LEVEL_7: + pPdsCfg = &pdsCfgLevel7; + break; + case PM_PDS_LEVEL_31: + pPdsCfg = &pdsCfgLevel31; + break; + } + +#if PM_PDS_FLASH_POWER_OFF + HBN_Power_Down_Flash(flash_cfg); + /* turn_off_ext_flash_pin, GPIO23 - GPIO28 */ + for (uint32_t pin = 23; pin <= 28; pin++) { + GLB_GPIO_Set_HZ(pin); + } + /* SF io select from efuse value */ + uint32_t flash_select = BL_RD_WORD(0x40007074); + if (((flash_select >> 26) & 7) == 0) { + HBN_Set_Pad_23_28_Pullup(); + } + pPdsCfg->pdsCtl.puFlash = 1; +#endif + +#if PM_PDS_EXTERNAL_XTAL_32M_POWER_OFF + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + AON_Power_Off_XTAL(); +#endif +#if PM_PDS_DLL_POWER_OFF + GLB_Power_Off_DLL(); +#endif +#if PM_PDS_PLL_POWER_OFF + GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + PDS_Update_Flash_Ctrl_Setting(0); + PDS_Power_Off_PLL(); +#endif + + /* pds0-pds7 : ldo11rt_iload_sel=3 */ + /* pds31 : ldo11rt_iload_sel=1 */ + if ((pds_level >= 0) && (pds_level <= 7)) { + HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_25_250UA); + } else if (pds_level == 31) { + HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA); + } else { + /* pdsLevel error */ + } + + pPdsCfg->pdsCtl.gpioIePuPd = 0; + pPdsCfg->pdsCtl.pdsLdoVol = PM_PDS_LDO_LEVEL_DEFAULT; + pPdsCfg->pdsCtl.pdsLdoVselEn = 1; + +#if PM_PDS_RF_POWER_OFF == 0 + pPdsCfg->pdsCtl.pdsCtlRfSel = 0; +#endif + /* config ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */ + AON_Set_LDO11_SOC_Sstart_Delay(0x2); + + PDS_Default_Level_Config(pPdsCfg, sleep_time * 32768); + __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */ + +#if PM_PDS_PLL_POWER_OFF + GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE); + PDS_Update_Flash_Ctrl_Setting(1); +#endif + +#if PM_PDS_FLASH_POWER_OFF + HBN_Set_Pad_23_28_Pullnone(); + /* Init flash gpio */ + SF_Cfg_Init_Flash_Gpio(0, 1); + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Restore_From_Powerdown(flash_cfg, 0); +#endif + + __enable_irq(); +} +/** + * @brief + * + * power management in hbn(hibernation) mode + * cpu will reset after wakeup + * + * HBN_LEVEL PD_AON PD_AON_HNBRTC PD_AON_HBNCORE PD_CORE PD_CORE_MISC_DIG PD_CORE_MISC_ANA PD_CORE_CPU PD_BZ PD_USB + * HBN0 ON ON ON OFF OFF OFF OFF OFF OFF + * HBN1 ON ON OFF OFF OFF OFF OFF OFF OFF + * HBN2 ON OFF OFF OFF OFF OFF OFF OFF OFF + * @param hbn_level + */ +ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time) +{ + uint32_t tmpVal; + + /* To make it simple and safe*/ + __disable_irq(); + + CPU_Interrupt_Pending_Clear(HBN_OUT0_IRQn); + CPU_Interrupt_Pending_Clear(HBN_OUT1_IRQn); + + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); + + if (sleep_time && (hbn_level < PM_HBN_LEVEL_2)) + rtc_init(sleep_time); //sleep time,unit is second + + if (hbn_level >= PM_HBN_LEVEL_2) + HBN_Power_Off_RC32K(); + else + HBN_Power_On_RC32K(); + + HBN_Power_Down_Flash(NULL); + /* SF io select from efuse value */ + uint32_t flash_select = BL_RD_WORD(0x40007074); + if (((flash_select >> 26) & 7) == 0) { + HBN_Set_Pad_23_28_Pullup(); + } + + /* Select RC32M */ + GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + /* power off xtal */ + AON_Power_Off_XTAL(); + + /* HBN mode LDO level */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, PM_HBN_LDO_LEVEL_DEFAULT); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, PM_HBN_LDO_LEVEL_DEFAULT); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch (hbn_level) { + case PM_HBN_LEVEL_0: + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case PM_HBN_LEVEL_1: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case PM_HBN_LEVEL_2: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + default: + break; + } + + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Enable HBN mode */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + while (1) { + BL702_Delay_MS(1000); + } +} + +void pm_hbn_set_wakeup_callback(void (*wakeup_callback)(void)) +{ + BL_WR_REG(HBN_BASE, HBN_RSV1, (uint32_t)wakeup_callback); +} + +ATTR_HBN_RAM_SECTION void pm_hbn_enter_again(bool reset) +{ + uint32_t tmpVal; + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); + + if (!reset) + /* Enable HBN mode */ + BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); +} +void pm_hbn_out0_irq_register(void) +{ + Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT0_IRQ); + CPU_Interrupt_Enable(HBN_OUT0_IRQn); +} + +void pm_hbn_out1_irq_register(void) +{ + Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQ); + CPU_Interrupt_Enable(HBN_OUT1_IRQn); +} + +void HBN_OUT0_IRQ(void) +{ + if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) { + HBN_Clear_IRQ(HBN_INT_GPIO9); + pm_irq_callback(PM_HBN_GPIO9_WAKEUP_EVENT); + } + if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) { + HBN_Clear_IRQ(HBN_INT_GPIO10); + pm_irq_callback(PM_HBN_GPIO10_WAKEUP_EVENT); + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) { + HBN_Clear_IRQ(HBN_INT_GPIO11); + pm_irq_callback(PM_HBN_GPIO11_WAKEUP_EVENT); + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) { + HBN_Clear_IRQ(HBN_INT_GPIO12); + pm_irq_callback(PM_HBN_GPIO12_WAKEUP_EVENT); + } + + if (SET == HBN_Get_INT_State(HBN_INT_RTC)) { + HBN_Clear_IRQ(HBN_INT_RTC); + HBN_Clear_RTC_INT(); + pm_irq_callback(PM_HBN_RTC_WAKEUP_EVENT); + } +} + +void HBN_OUT1_IRQ(void) +{ + /* PIR */ + if (SET == HBN_Get_INT_State(HBN_INT_PIR)) { + HBN_Clear_IRQ(HBN_INT_PIR); + } + + /* BOR */ + if (SET == HBN_Get_INT_State(HBN_INT_BOR)) { + HBN_Clear_IRQ(HBN_INT_BOR); + } + + /* ACOMP0 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) { + HBN_Clear_IRQ(HBN_INT_ACOMP0); + pm_irq_callback(PM_HBN_ACOMP0_WAKEUP_EVENT); + } + + /* ACOMP1 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) { + HBN_Clear_IRQ(HBN_INT_ACOMP1); + pm_irq_callback(PM_HBN_ACOMP1_WAKEUP_EVENT); + } +} + +__WEAK void pm_irq_callback(enum pm_event_type event) +{ +} +/** + * @brief hal_pds_enter_with_time_compensation + * + * @param pdsLevel pds level support 0~3,31 + * @param pdsSleepCycles if user set sleep time, pdsSleepCycles cannot be less than 32768, pdsSleepCycles is a multiple of 32768 preferably. + * @return uint32_t actual sleep time(ms) + * + * @note If necessary,please application layer call vTaskStepTick, + */ +uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles) +{ + uint32_t rtcLowBeforeSleep = 0, rtcHighBeforeSleep = 0; + uint32_t rtcLowAfterSleep = 0, rtcHighAfterSleep = 0; + uint32_t actualSleepDuration_32768cycles = 0; + uint32_t actualSleepDuration_ms = 0; + + HBN_Get_RTC_Timer_Val(&rtcLowBeforeSleep, &rtcHighBeforeSleep); + + pm_pds_mode_enter(pdsLevel, pdsSleepCycles / 32768); + + HBN_Get_RTC_Timer_Val(&rtcLowAfterSleep, &rtcHighAfterSleep); + + CHECK_PARAM((rtcHighAfterSleep - rtcHighBeforeSleep) <= 1); // make sure sleep less than 1 hour (2^32 us > 1 hour) + + actualSleepDuration_32768cycles = (rtcLowAfterSleep - rtcLowBeforeSleep); + + actualSleepDuration_ms = (actualSleepDuration_32768cycles >> 5) - (actualSleepDuration_32768cycles >> 11) - (actualSleepDuration_32768cycles >> 12); + + // vTaskStepTick(actualSleepDuration_ms); + + return actualSleepDuration_ms; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_power.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_power.c new file mode 100644 index 0000000000000000000000000000000000000000..3561f3470d079d5d8ab73f5d403bb68caabafdc6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_power.c @@ -0,0 +1,1499 @@ +/** + * @file hal_power.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "misc.h" +#include "bl702_sflash.h" +#include "bl702_sec_eng.h" +#include "bl702_ef_ctrl.h" +#include "bl702_glb.h" +#include "bl702_pds.h" +#include "bl702_hbn.h" +#include "bl702_clock.h" +#include "power_config.h" +#include "hal_power.h" + +#define ALWAYS_DISABLE_AON_PAD_9 (0) + +/** + * @brief gating peripheral clock for power saving + * + * @param enable + * @param clockType + * @return int + */ +int lp_set_clock_gate(uint8_t enable, Clock_Gate_Type clockType) +{ + if (clockType == CLOCK_AHB_ALL) { + for (uint8_t i = CLOCK_AHB_UART0_GATE; i < CLOCK_AHB_ALL; i++) { + GLB_AHB_Slave1_Clock_Gate(enable, i); + } + + return 0; + } + + return GLB_AHB_Slave1_Clock_Gate(enable, clockType); +} + +/** + * @brief Set the gpio hz object + * + * set all gpio to high z for power saving + * + */ +void lp_set_all_gpio_hz(void) +{ + GLB_GPIO_Cfg_Type gpio_cfg = { + .gpioPin = GLB_GPIO_PIN_14, + .gpioFun = GPIO_FUN_GPIO, + .gpioMode = GPIO_MODE_OUTPUT, + .pullType = GPIO_PULL_UP, + .drive = 0, + .smtCtrl = 1 + }; + + for (GLB_GPIO_Type pin = GLB_GPIO_PIN_0; pin < GLB_GPIO_PIN_MAX; pin++) { + GLB_GPIO_Init(&gpio_cfg); + GLB_GPIO_Set_HZ(gpio_cfg.gpioPin); + } +} + +void lp_power_off_dll(void) +{ + GLB_Power_Off_DLL(); +} + +/** + * @brief enter cpu into mode + * + * wfi mode will suspend CPU for power saving, if any interrupt happned CPU + * will continue to run. + * + * @return int + */ +int lp_enter_wfi(void) +{ + HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P10V); + + __WFI(); + + return 0; +} +/** @defgroup Hal_Power_Global_Variables + * + * @brief PDS level config + * @{ + */ +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel0 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel4 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel5 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel6 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel31 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 0, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 1, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 1, + .MiscRst = 1, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; +static void (*glb_preCbFun)(void); +static void (*glb_postCbFun)(void); +/*@} end of group Hal_Power_Global_Variables */ + +/****************************************************************************/ /** + * @brief PDS update flash_ctrl setting + * + * @param fastClock: fast clock + * + * @return None + * +*******************************************************************************/ +static ATTR_TCM_SECTION void PDS_Update_Flash_Ctrl_Setting(uint8_t fastClock) +{ + if (fastClock) { + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_96M, 0); + } else { + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0); + } + + SF_Ctrl_Set_Clock_Delay(fastClock); +} + +/****************************************************************************/ /** + * @brief PDS power on flash pad gpio + * + * @param flashPinCfg: flash pin config + * + * @return None + * +*******************************************************************************/ +static ATTR_TCM_SECTION void PDS_Power_On_Flash_Pad(uint8_t flashPinCfg) +{ + switch (flashPinCfg) { + case 0: + HBN_Set_Pad_23_28_Pullnone(); + break; + + case 1: + break; + + case 2: + break; + + case 3: + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_23, PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_24, PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_25, PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_26, PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_27, PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_28, PDS_PAD_CFG_PULL_NONE); + break; + + default: + break; + } + + /* Init flash gpio */ + SF_Cfg_Init_Flash_Gpio(flashPinCfg, 1); +} + +/****************************************************************************/ /** + * @brief PDS power on flash + * + * @param cfg: PDS app config + * + * @return None + * +*******************************************************************************/ +static ATTR_TCM_SECTION void PDS_Power_On_Flash(PDS_APP_CFG_Type *cfg) +{ + /* Init flash gpio */ + //SF_Cfg_Init_Flash_Gpio(0,1); + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + + /* Restore flash */ + SFlash_Restore_From_Powerdown(cfg->flashCfg, cfg->flashContRead); +} + +/****************************************************************************/ /** + * @brief power down sleep mode test function + * + * @param cfg: PDS app config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION PDS_Mode_Enter(PDS_APP_CFG_Type *cfg) +{ + PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL; + + if (cfg->useXtal32k) { + HBN_32K_Sel(HBN_32K_XTAL); + } else { + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* turn_off_sec_ring */ + SEC_Eng_Turn_Off_Sec_Ring(); /* E_ITEM_04 */ + + /* disable sec_eng to reduce current which enabled by bflb_platform_init(0) */ + Sec_Eng_Trng_Disable(); + + /* pre callback */ + if (cfg->preCbFun) { + cfg->preCbFun(); + } + + /* always disable HBN pin pull up/down for reduce PDS0/1/2/3/7 current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + /* mask/unmask HBN pin wakeup, 0x4000F014[4:3] */ + HBN_Pin_WakeUp_Mask(~(cfg->pdsAonGpioWakeupSrc)); + HBN_Aon_Pad_IeSmt_Cfg(cfg->pdsAonGpioWakeupSrc); + + if (cfg->pdsAonGpioWakeupSrc != 0) { + HBN_GPIO_INT_Enable(cfg->pdsAonGpioTrigType); + } + +#if ALWAYS_DISABLE_AON_PAD_9 + uint32_t tmpVal = 0, tmpVal2 = 0; + + /* always disable and mask aon_pad_GPIO9, mask/unmask and ie_enable/ie_disable */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK); + tmpVal2 |= (1 << 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, tmpVal2); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT); + tmpVal2 &= ~(1 << 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); +#endif + + /* To make it simple and safe*/ + __disable_irq(); + + if (cfg->powerDownFlash) { + HBN_Power_Down_Flash(cfg->flashCfg); + GLB_Select_External_Flash(); + } + + HBN_Set_Ldo11_All_Vout(cfg->ldoLevel); + + if (cfg->turnOffXtal32m) { + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + AON_Power_Off_XTAL(); + } + + if (cfg->turnOffDll) { + GLB_Power_Off_DLL(); + } + + /* power off PLL to reduce current */ + if (cfg->turnoffPLL) { + GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + PDS_Update_Flash_Ctrl_Setting(0); + PDS_Power_Off_PLL(); + } + + /* pds0-pds7 : ldo11rt_iload_sel=3 */ + /* pds31 : ldo11rt_iload_sel=1 */ + if ((cfg->pdsLevel >= 0) && (cfg->pdsLevel <= 7)) { + HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_25_250UA); + } else if (cfg->pdsLevel == 31) { + HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA); + } else { + /* pdsLevel error */ + } + + switch (cfg->pdsLevel) { + case 0: + pPdsCfg = &pdsCfgLevel0; + break; + + case 1: + pPdsCfg = &pdsCfgLevel1; + break; + + case 2: + pPdsCfg = &pdsCfgLevel2; + break; + + case 3: + pPdsCfg = &pdsCfgLevel3; + break; + + case 4: + pPdsCfg = &pdsCfgLevel4; + break; + + case 5: + pPdsCfg = &pdsCfgLevel5; + break; + + case 6: + pPdsCfg = &pdsCfgLevel6; + break; + + case 7: + pPdsCfg = &pdsCfgLevel7; + break; + + case 31: + pPdsCfg = &pdsCfgLevel31; + break; + + default: + + /* pdsLevel error */ + while (1) { + BL702_Delay_MS(500); + } + + break; + } + + if (cfg->turnOffFlashPad) { + switch (cfg->flashPinCfg) { + case 0: + + /* turn_off_ext_flash_pin, GPIO23 - GPIO28 */ + for (uint32_t pin = 23; pin <= 28; pin++) { + GLB_GPIO_Set_HZ(pin); + } + + HBN_Set_Pad_23_28_Pullup(); + break; + + case 1: + + /* turn_off_internal_flash_pin, GPIO23 - GPIO28 */ + for (uint32_t pin = 23; pin <= 28; pin++) { + GLB_GPIO_Set_HZ(pin); + } + + break; + + case 2: + + /* turn_off_internal_flash_pin, GPIO23 - GPIO28 */ + for (uint32_t pin = 23; pin <= 28; pin++) { + GLB_GPIO_Set_HZ(pin); + } + + break; + + case 3: + + /* turn_off_ext_flash_pin, GPIO17 - GPIO22 */ + for (uint32_t pin = 17; pin <= 22; pin++) { + GLB_GPIO_Set_HZ(pin); + } + + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_23, PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_24, PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_25, PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_26, PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_27, PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_28, PDS_PAD_CFG_PULL_UP); + break; + + default: + break; + } + + pPdsCfg->pdsCtl.puFlash = 1; /* power switch setting, set 1 for internal flash, has no effect on ext flash */ + } + + if (cfg->pdsHoldGpio) { + pPdsCfg->pdsCtl.gpioIePuPd = 1; + } else { + pPdsCfg->pdsCtl.gpioIePuPd = 0; + } + + pPdsCfg->pdsCtl.pdsLdoVol = cfg->ldoLevel; + pPdsCfg->pdsCtl.pdsLdoVselEn = 1; + + if (!(cfg->turnOffRF)) { + pPdsCfg->pdsCtl.pdsCtlRfSel = 0; + } + + /* config ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */ + AON_Set_LDO11_SOC_Sstart_Delay(0x2); + + PDS_Default_Level_Config(pPdsCfg, cfg->sleepTime); + __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */ + + /* Wake up from PDS */ + /* post callback, mainly for GPIO or peripherals on/off */ + if (cfg->postCbFun) { + cfg->postCbFun(); + } + + if (cfg->turnoffPLL) { + GLB_Set_System_CLK(cfg->xtalType, GLB_SYS_CLK_DLL144M); + PDS_Update_Flash_Ctrl_Setting(1); + } + + if (cfg->turnOffFlashPad) { + PDS_Power_On_Flash_Pad(cfg->flashPinCfg); + } + + if (cfg->powerDownFlash) { + PDS_Power_On_Flash(cfg); /* call GLB_Select_Internal_Flash() in this API */ + } + + /* always turn_on_sec_ring, may cost more current */ + SEC_Eng_Turn_On_Sec_Ring(); /* E_ITEM_04 */ + + /* always enable sec_eng, may cost more current */ + Sec_Eng_Trng_Enable(); + + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + + __enable_irq(); +} + +/** + * @brief callback function before entry into pds + * + */ +static void ATTR_TCM_SECTION PDS_Pre_CallBack(void) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = GPIO_FUN_GPIO, + .gpioMode = GPIO_MODE_INPUT, + .pullType = GPIO_PULL_NONE, + .drive = 0, + .smtCtrl = 0, + }; + + /* turn off gpio except for CCI, GPIO0 - GPIO22 */ + for (GLB_GPIO_Type pin = GLB_GPIO_PIN_0; pin < GLB_GPIO_PIN_MAX; pin++) { + GLB_CCI_Use_IO_0_1_2_7(DISABLE); + GLB_CCI_Use_Jtag_Pin(DISABLE); + + /* flash pin GPIO17~GPIO22 */ + if ((pin >= GLB_GPIO_PIN_17) && (pin <= GLB_GPIO_PIN_22)) { + continue; + } + + /* flash pin GPIO23~GPIO28 */ + if ((pin >= GLB_GPIO_PIN_23) && (pin <= GLB_GPIO_PIN_28)) { + continue; + } + + /* DBG_TX pin */ + if (pin == GLB_GPIO_PIN_14) { + continue; + } + + gpioCfg.gpioPin = pin; + GLB_GPIO_Init(&gpioCfg); + GLB_GPIO_Set_HZ(gpioCfg.gpioPin); + } + + if (glb_preCbFun != NULL) { + glb_preCbFun(); + } +} + +/** + * @brief callback function after wake up form pds if cpu do not reset + * + */ +static void ATTR_TCM_SECTION PDS_Post_CallBack(void) +{ + HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_1P00V); + + if (glb_postCbFun != NULL) { + glb_postCbFun(); + } +} + +int hbn_set_wakeup_addr(uint32_t addr) +{ + return HBN_Set_Wakeup_Addr(addr); +} + +int hbn_set_status_flag(uint32_t flag) +{ + return HBN_Set_Status_Flag(flag); +} + +/** + * @brief enter cpu into pds mode + * + * pds(power down sleep) mode will set CPU into sleep mode. + * cpu's behavior after wakeup depend on psd level + * + * see flow table if cpu off , cpu will reset after wakeup + * + * PD_CORE PD_CORE_MISC_DIG PD_CORE_MISC_ANA PD_CORE_CPU PD_BZ PD_USB + * PDS0 ON ON ON ON ON ON + * PDS1 ON ON ON ON ON OFF + * PDS2 ON ON ON ON OFF ON + * PDS3 ON ON ON ON OFF OFF + * PDS4 ON ON ON OFF ON ON + * PDS5 ON ON ON OFF ON OFF + * PDS6 ON ON ON OFF OFF ON + * PDS7 ON ON ON OFF OFF OFF + * PDS31 ON OFF OFF OFF OFF OFF + * + * + * now default pds level is pds31 + * @return int + */ +int lp_enter_pds(uint32_t sleep_time, void (*preCbFun)(void), void (*postCbFun)(void)) +{ + PDS_APP_CFG_Type pdsCfg = { + .pdsLevel = 31, /*!< PDS level */ + .turnOffXtal32m = DEFAULT_LP_PDS_TURN_OFF_XTAL_32M, /*!< Wheather turn off XTAL32M */ + .turnOffDll = DEFAULT_LP_PDS_TURN_OFF_DLL, /*!< Wheather turn off DLL */ + .turnOffRF = DEFAULT_LP_PDS_TURN_OFF_RF, /*!< Wheather turn off RF */ + .useXtal32k = DEFAULT_LP_PDS_USE_XTAL_32K, /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */ + .pdsAonGpioWakeupSrc = DEFAULT_LP_PDS_AON_GPIO_WAKE_UP_SRC, /*!< PDS level 0-7,31 mode aon GPIO Wakeup source(HBN wakeup pin) */ + .pdsAonGpioTrigType = DEFAULT_LP_PDS_AON_GPIO_TRIG_TYPE, /*!< PDS level 0-7,31 mode aon GPIO Triger type(HBN wakeup pin) */ + .powerDownFlash = DEFAULT_LP_PDS_FLASH_POWER_DOWN, /*!< Whether power down flash */ + .pdsHoldGpio = DEFAULT_LP_PDS_HOLD_GPIO, /*!< Whether pds hold gpio level */ + .turnOffFlashPad = DEFAULT_LP_PDS_TURN_OFF_FLASH_PAD, /*!< Whether turn off ext flash pad(GPIO17-GPIO22, GPIO23-GPIO28) */ + .flashPinCfg = 0, + .turnoffPLL = 1, + /*!< Whether trun off PLL */ /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */ + .xtalType = DEAULT_LP_XTAL_TYPE, /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ + .flashContRead = 0, /*!< Whether enable flash continue read */ + .sleepTime = 10 * 32768, /*!< PDS sleep time */ + .flashCfg = &flashCfg_Gd_Q80E_Q16E, /*!< Flash config pointer, used when power down flash */ + .ldoLevel = DEFAULT_LP_LDO_LEVEL, /*!< LDO level */ + .preCbFun = PDS_Pre_CallBack, /*!< Pre callback function */ + .postCbFun = PDS_Post_CallBack, /*!< Post callback function */ + }; + + BL702_Delay_MS(2000); + + glb_preCbFun = preCbFun; + glb_postCbFun = postCbFun; + + pdsCfg.sleepTime = sleep_time; + + HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_1P00V); + + PDS_WAKEUP_IRQHandler_Install(); + + /* clear aon pads int status */ + HBN_Hw_Pu_Pd_Cfg(0); + HBN_Aon_Pad_IeSmt_Cfg(0); + HBN_Pin_WakeUp_Mask(0x1F); + HBN_Clear_IRQ(HBN_INT_GPIO9); + HBN_Clear_IRQ(HBN_INT_GPIO10); + HBN_Clear_IRQ(HBN_INT_GPIO11); + HBN_Clear_IRQ(HBN_INT_GPIO12); + HBN_Clear_IRQ(HBN_INT_GPIO13); + + /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */ + CPU_Interrupt_Enable(PDS_WAKEUP_IRQn); + + /* clear and mask PDS int */ + PDS_IntMask(PDS_INT_WAKEUP, UNMASK); + PDS_IntMask(PDS_INT_RF_DONE, MASK); + PDS_IntMask(PDS_INT_PLL_DONE, MASK); + PDS_IntClear(); + + BL702_Delay_MS(100); + + PDS_Mode_Enter(&pdsCfg); + + while (1) { + //MSG("pds wakeup and running.\r\n"); + BL702_Delay_MS(1000); + } + + return 0; +} + +/** + * @brief enter cpu into hbn mode + * + * @param sleepTime sleep time + * @return int + * + * @note now default hbn level is hbn1 + */ +int lp_enter_hbn(uint32_t sleepTime, uint8_t hbn_level) +{ + HBN_APP_CFG_Type cfg = { + .useXtal32k = 0, /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */ + .sleepTime = sleepTime, /*!< HBN sleep time */ + .gpioWakeupSrc = DEFAULT_LP_PDS_AON_GPIO_WAKE_UP_SRC, /*!< GPIO Wakeup source */ + .gpioTrigType = DEFAULT_LP_PDS_AON_GPIO_TRIG_TYPE, /*!< GPIO Triger type */ + .flashCfg = NULL, /*!< Flash config pointer, used when power down flash */ + .flashPinCfg = 0, /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */ + .hbnLevel = hbn_level, /*!< HBN level */ + .ldoLevel = HBN_LDO_LEVEL_0P90V, /*!< LDO level */ + }; + + HBN_Out0_IRQHandler_Install(); + HBN_Out1_IRQHandler_Install(); + + //HBN_Check_RAM(0); + + /* disable aon_pad(gpio7) will cause uart0_rx irq_req, __disable_irq() for all irq_req */ + __disable_irq(); + + HBN_Mode_Enter(&cfg); + + while (1) { + BL702_Delay_MS(1000); + } + + return 0; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pwm.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..7623ac3028849e019b2d7be2a1ca239e5e9278a4 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pwm.c @@ -0,0 +1,203 @@ +/** + * @file hal_pwm.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_pwm.h" +#include "hal_gpio.h" +#include "hal_clock.h" +#include "bl702_pwm.h" +#include "bl702_gpio.h" +#include "bl702_glb.h" +#include "pwm_config.h" + +static pwm_device_t pwmx_device[PWM_MAX_INDEX] = { +#ifdef BSP_USING_PWM_CH0 + PWM_CH0_CONFIG, +#endif +#ifdef BSP_USING_PWM_CH1 + PWM_CH1_CONFIG, +#endif +#ifdef BSP_USING_PWM_CH2 + PWM_CH2_CONFIG, +#endif +#ifdef BSP_USING_PWM_CH3 + PWM_CH3_CONFIG, +#endif +#ifdef BSP_USING_PWM_CH4 + PWM_CH4_CONFIG, +#endif +}; +static void PWM_IRQ(void); + +int pwm_open(struct device *dev, uint16_t oflag) +{ + pwm_device_t *pwm_device = (pwm_device_t *)dev; + + uint32_t tmpVal; + uint32_t PWMx; + PWM_Channel_Disable(pwm_device->ch); + PWM_IntMask(pwm_device->ch, PWM_INT_ALL, MASK); + + uint32_t pwm_clk = peripheral_clock_get(PERIPHERAL_CLOCK_PWM); + if (pwm_device->period > pwm_clk) + return -1; + + PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20; + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, pwm_device->polarity_invert_mode); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_MODE_SEL); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + + BL_WR_REG(PWMx, PWM_THRE1, pwm_device->threshold_low); + BL_WR_REG(PWMx, PWM_THRE2, pwm_device->threshold_high); + BL_WR_REG(PWMx, PWM_PERIOD, pwm_device->period); + + if (oflag & DEVICE_OFLAG_INT_TX) { + tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT); + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, pwm_device->it_pulse_count)); + Interrupt_Handler_Register(PWM_IRQn, PWM_IRQ); + PWM_IntMask(pwm_device->ch, PWM_INT_PULSE_CNT, UNMASK); + CPU_Interrupt_Enable(PWM_IRQn); + } + + return 0; +} +int pwm_close(struct device *dev) +{ + pwm_device_t *pwm_device = (pwm_device_t *)dev; + PWM_Channel_Disable(pwm_device->ch); + return 0; +} + +int pwm_control(struct device *dev, int cmd, void *args) +{ + pwm_device_t *pwm_device = (pwm_device_t *)dev; + pwm_dutycycle_config_t *pwm_detycycle_config = (pwm_dutycycle_config_t *)args; + + switch (cmd) { + case DEVICE_CTRL_CONFIG /* constant-expression */: + break; + case DEVICE_CTRL_RESUME /* constant-expression */: + PWM_Channel_Enable(pwm_device->ch); + break; + + case DEVICE_CTRL_SUSPEND /* constant-expression */: + PWM_Channel_Disable(pwm_device->ch); + break; + case DEVICE_CTRL_PWM_FREQUENCE_CONFIG: + + if ((uint32_t)args > peripheral_clock_get(PERIPHERAL_CLOCK_PWM)) + return -1; + pwm_device->period = (uint32_t)args; + BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_PERIOD, (uint32_t)args); + break; + case DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG: + BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE1, pwm_detycycle_config->threshold_low); + BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE2, pwm_detycycle_config->threshold_high); + break; + case DEVICE_CTRL_PWM_IT_PULSE_COUNT_CONFIG: { + /* Config interrupt pulse count */ + uint32_t pwm_ch_addr = PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20; + uint32_t tmpVal = BL_RD_REG(pwm_ch_addr, PWM_INTERRUPT); + BL_WR_REG(pwm_ch_addr, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, (uint32_t)args)); + + if ((uint32_t)args) { + PWM_IntMask(pwm_device->ch, PWM_INT_PULSE_CNT, UNMASK); + CPU_Interrupt_Enable(PWM_IRQn); + } else { + PWM_IntMask(pwm_device->ch, PWM_INT_PULSE_CNT, MASK); + CPU_Interrupt_Disable(PWM_IRQn); + } + + break; + } + + default: + break; + } + + return 0; +} + +int pwm_register(enum pwm_index_type index, const char *name) +{ + struct device *dev; + + if (PWM_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(pwmx_device[index].parent); + + dev->open = pwm_open; + dev->close = pwm_close; + dev->control = pwm_control; + dev->write = NULL; + dev->read = NULL; + + dev->type = DEVICE_CLASS_PWM; + dev->handle = NULL; + + return device_register(dev, name); +} + +static void pwm_isr(pwm_device_t *handle) +{ + uint32_t i; + uint32_t tmpVal; + uint32_t timeoutCnt = 160 * 1000; + /* Get channel register */ + uint32_t PWMx = PWM_BASE; + + for (i = 0; i < PWM_MAX_INDEX; i++) { + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + + if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << handle[i].ch)) != 0) { + /* Clear interrupt */ + tmpVal |= (1 << (handle[i].ch + PWM_INT_CLEAR_POS)); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + + /* FIXME: we need set pwm_int_clear to 0 by software and + before this,we must make sure pwm_interrupt_sts is 0*/ + do { + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + timeoutCnt--; + + if (timeoutCnt == 0) { + break; + } + } while (BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << handle[i].ch)); + + tmpVal &= (~(1 << (handle[i].ch + PWM_INT_CLEAR_POS))); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + + if (handle[i].parent.callback) { + handle[i].parent.callback(&handle[i].parent, NULL, 0, PWM_EVENT_COMPLETE); + } + } + } +} + +static void PWM_IRQ(void) +{ + pwm_isr(&pwmx_device[0]); +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_qdec.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_qdec.c new file mode 100644 index 0000000000000000000000000000000000000000..eff9fabdfc47c0ae2f73c95e89404b10e2fc8fdc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_qdec.c @@ -0,0 +1,290 @@ +/** + * @file hal_qdec.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "hal_qdec.h" +#include "qdec_reg.h" +#include "bl702_qdec.h" +#include "bl702_gpio.h" +#include "bl702_glb.h" + +static qdec_device_t qdecx_device[QDEC_MAX_INDEX] = { +#ifdef BSP_USING_QDEC0 + QDEC0_CONFIG, +#endif +#ifdef BSP_USING_QDEC1 + QDEC1_CONFIG, +#endif +#ifdef BSP_USING_QDEC2 + QDEC2_CONFIG, +#endif +}; +#ifdef BSP_USING_QDEC0 +static void QDEC0_IRQ(void); +#endif +#ifdef BSP_USING_QDEC1 +static void QDEC1_IRQ(void); +#endif +#ifdef BSP_USING_QDEC2 +static void QDEC2_IRQ(void); +#endif + +int qdec_open(struct device *dev, uint16_t oflag) +{ + qdec_device_t *qdec_device = (qdec_device_t *)dev; + QDEC_CFG_Type qdec_cfg = { 0 }; + + QDEC_DeInit(qdec_device->id); + + qdec_cfg.sampleCfg.sampleMod = qdec_device->sample_mode; + qdec_cfg.sampleCfg.samplePeriod = qdec_device->sample_period; + qdec_cfg.reportCfg.reportMod = qdec_device->report_mode; + qdec_cfg.reportCfg.reportPeriod = qdec_device->report_period; + qdec_cfg.ledCfg.ledEn = qdec_device->led_en; + qdec_cfg.ledCfg.ledSwap = qdec_device->led_swap; + qdec_cfg.ledCfg.ledPeriod = qdec_device->led_period; + qdec_cfg.deglitchCfg.deglitchEn = qdec_device->deglitch_en; + qdec_cfg.deglitchCfg.deglitchStrength = qdec_device->deglitch_strength; + qdec_cfg.accMod = qdec_device->acc_mode; + + QDEC_Init(qdec_device->id, &qdec_cfg); + + if (oflag & DEVICE_OFLAG_INT_RX) { +#ifdef BSP_USING_QDEC0 + if (qdec_device->id == QDEC0_ID) { + Interrupt_Handler_Register(QDEC0_IRQn, QDEC0_IRQ); + } +#endif +#ifdef BSP_USING_QDEC1 + if (qdec_device->id == QDEC1_ID) { + Interrupt_Handler_Register(QDEC1_IRQn, QDEC1_IRQ); + QDEC_SetIntMask(qdec_device->id, QDEC_INT_REPORT, MASK); + QDEC_SetIntMask(qdec_device->id, QDEC_INT_SAMPLE, MASK); + QDEC_SetIntMask(qdec_device->id, QDEC_INT_ERROR, MASK); + QDEC_SetIntMask(qdec_device->id, QDEC_INT_OVERFLOW, MASK); + // CPU_Interrupt_Enable(QDEC1_IRQn); + } +#endif +#ifdef BSP_USING_QDEC2 + if (qdec_device->id == QDEC2_ID) { + Interrupt_Handler_Register(QDEC2_IRQn, QDEC2_IRQ); + QDEC_SetIntMask(qdec_device->id, QDEC_INT_REPORT, MASK); + QDEC_SetIntMask(qdec_device->id, QDEC_INT_SAMPLE, MASK); + QDEC_SetIntMask(qdec_device->id, QDEC_INT_ERROR, MASK); + QDEC_SetIntMask(qdec_device->id, QDEC_INT_OVERFLOW, MASK); + // CPU_Interrupt_Enable(QDEC2_IRQn); + } +#endif + } + + return 0; +} + +int qdec_close(struct device *dev) +{ + qdec_device_t *qdec_device = (qdec_device_t *)dev; + + QDEC_Disable(qdec_device->id); + return 0; +} + +int qdec_control(struct device *dev, int cmd, void *args) +{ + qdec_device_t *qdec_device = (qdec_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT: { + uint32_t offset = __builtin_ctz((uint32_t)args); + while (offset < 5) { + if ((uint32_t)args & (1 << offset)) { + QDEC_SetIntMask(qdec_device->id, offset, UNMASK); + } + offset++; + } + if (qdec_device->id == QDEC0_ID) { + CPU_Interrupt_Enable(QDEC0_IRQn); + } else if (qdec_device->id == QDEC1_ID) { + CPU_Interrupt_Enable(QDEC1_IRQn); + } else if (qdec_device->id == QDEC2_ID) { + CPU_Interrupt_Enable(QDEC2_IRQn); + } + break; + } + + case DEVICE_CTRL_CLR_INT: { + uint32_t offset = __builtin_ctz((uint32_t)args); + while (offset < 5) { + if ((uint32_t)args & (1 << offset)) { + QDEC_SetIntMask(qdec_device->id, offset, MASK); + } + offset++; + } + if (qdec_device->id == QDEC0_ID) { + CPU_Interrupt_Disable(QDEC0_IRQn); + } else if (qdec_device->id == QDEC1_ID) { + CPU_Interrupt_Disable(QDEC1_IRQn); + } else if (qdec_device->id == QDEC2_ID) { + CPU_Interrupt_Disable(QDEC2_IRQn); + } + break; + } + + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_CONFIG /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_RESUME /* constant-expression */: { + /* Enable timer */ + QDEC_Enable(qdec_device->id); + break; + } + + case DEVICE_CTRL_SUSPEND /* constant-expression */: { + QDEC_Disable(qdec_device->id); + break; + } + + case DEVICE_CTRL_GET_SAMPLE_VAL: { + return QDEC_Get_Sample_Val(qdec_device->id); + } + + case DEVICE_CTRL_GET_SAMPLE_DIR: { + return QDEC_Get_Sample_Direction(qdec_device->id); + } + + case DEVICE_CTRL_GET_ERROR_CNT: { + return QDEC_Get_Err_Cnt(qdec_device->id); + } + default: + break; + } + + return 0; +} + +int qdec_register(enum qdec_index_type index, const char *name) +{ + struct device *dev; + + if (QDEC_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(qdecx_device[index].parent); + + dev->open = qdec_open; + dev->close = qdec_close; + dev->control = qdec_control; + dev->write = NULL; + dev->read = NULL; //qdec_read; + + dev->type = DEVICE_CLASS_QDEC; + dev->handle = NULL; + + return device_register(dev, name); +} + +void qdec_isr(qdec_device_t *handle) +{ + uint32_t tmp_sts = 0; + uint32_t tmp_val = 0; + uint32_t tmp_clr = 0; + uint32_t tmp_clr_val = 0; + + if (handle->id == QDEC0_ID) { + tmp_sts = BL_RD_WORD(QDEC0_BASE + QDEC0_INT_STS_OFFSET); + tmp_clr = QDEC0_BASE + QDEC0_INT_CLR_OFFSET; + tmp_clr_val = BL_RD_WORD(tmp_clr); + tmp_val = BL_RD_REG(QDEC0_BASE, QDEC0_INT_EN); + } else if (handle->id == QDEC1_ID) { + tmp_sts = BL_RD_WORD(QDEC0_BASE + QDEC1_INT_STS_OFFSET); + tmp_clr = QDEC0_BASE + QDEC1_INT_CLR_OFFSET; + tmp_clr_val = BL_RD_WORD(tmp_clr); + tmp_val = BL_RD_REG(QDEC1_BASE, QDEC0_INT_EN); + } else if (handle->id == QDEC2_ID) { + tmp_sts = BL_RD_WORD(QDEC0_BASE + QDEC2_INT_STS_OFFSET); + tmp_clr = QDEC0_BASE + QDEC2_INT_CLR_OFFSET; + tmp_clr_val = BL_RD_WORD(tmp_clr); + tmp_val = BL_RD_REG(QDEC2_BASE, QDEC0_INT_EN); + } + + if (!handle->parent.callback) { + return; + } + + /* qdec report intterupt */ + if (!(BL_GET_REG_BITS_VAL(tmp_val, QDEC_RPT_RDY_EN) ? UNMASK : MASK)) { + if (BL_IS_REG_BIT_SET(tmp_sts, QDEC_RPT_RDY_STS)) { + BL_WR_WORD(tmp_clr, BL_SET_REG_BIT(tmp_clr_val, QDEC_RPT_RDY_CLR)); + handle->parent.callback(&handle->parent, NULL, 0, QDEC_REPORT_EVENT); + } + } + + /* qdec sample intterupt */ + if (!(BL_GET_REG_BITS_VAL(tmp_val, QDEC_SPL_RDY_EN) ? UNMASK : MASK)) { + if (BL_IS_REG_BIT_SET(tmp_sts, QDEC_SPL_RDY_STS)) { + BL_WR_WORD(tmp_clr, BL_SET_REG_BIT(tmp_clr_val, QDEC_SPL_RDY_CLR)); + handle->parent.callback(&handle->parent, NULL, 0, QDEC_SAMPLE_EVENT); + } + } + + /* qdec error intterupt */ + if (!(BL_GET_REG_BITS_VAL(tmp_val, QDEC_DBL_RDY_EN) ? UNMASK : MASK)) { + if (BL_IS_REG_BIT_SET(tmp_sts, QDEC_DBL_RDY_STS)) { + BL_WR_WORD(tmp_clr, BL_SET_REG_BIT(tmp_clr_val, QDEC_DBL_RDY_CLR)); + handle->parent.callback(&handle->parent, NULL, 0, QDEC_ERROR_EVENT); + } + } + + /* qdec overflow intterupt */ + if (!(BL_GET_REG_BITS_VAL(tmp_val, QDEC_OVERFLOW_EN) ? UNMASK : MASK)) { + if (BL_IS_REG_BIT_SET(tmp_sts, QDEC_OVERFLOW_STS)) { + BL_WR_WORD(tmp_clr, BL_SET_REG_BIT(tmp_clr_val, QDEC_OVERFLOW_CLR)); + handle->parent.callback(&handle->parent, NULL, 0, QDEC_OVERFLOW_EVENT); + } + } +} + +#ifdef BSP_USING_QDEC0 +static void QDEC0_IRQ(void) +{ + qdec_isr(&qdecx_device[QDEC0_INDEX]); +} +#endif + +#ifdef BSP_USING_QDEC1 +static void QDEC1_IRQ(void) +{ + qdec_isr(&qdecx_device[QDEC1_INDEX]); +} +#endif + +#ifdef BSP_USING_QDEC2 +static void QDEC2_IRQ(void) +{ + qdec_isr(&qdecx_device[QDEC2_INDEX]); +} +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_rtc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..9819b95aa7c1ff9c8e58968378672efed2cdeb14 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_rtc.c @@ -0,0 +1,101 @@ +/** + * @file hal_rtc.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl702_hbn.h" +#include "hal_rtc.h" + +static uint64_t current_timestamp = 0; +/** + * @brief rtc init withc sleep time + * + * @param sleep_time + */ +void rtc_init(uint64_t sleep_time) +{ + uint32_t tmpVal; + uint32_t comp_l, comp_h; + + /* Clear & Disable RTC counter */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff0); + + /* Get current RTC timer */ + /* Tigger RTC val read */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + + /* Read RTC val */ + comp_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); + comp_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); + + /* calculate RTC Comp time */ + comp_l += (uint32_t)((sleep_time * 32768) & 0xFFFFFFFF); + comp_h += (uint32_t)(((sleep_time * 32768) >> 32) & 0xFFFFFFFF); + + /* Set RTC Comp time */ + BL_WR_REG(HBN_BASE, HBN_TIME_L, comp_l); + BL_WR_REG(HBN_BASE, HBN_TIME_H, comp_h & 0xff); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set interrupt delay option */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, HBN_RTC_INT_DELAY_0T); + /* Set RTC compare mode */ + tmpVal |= (HBN_RTC_COMP_BIT0_39 << 1); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Enable RTC Counter */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01); +} + +void rtc_set_timestamp(uint64_t time_stamp) +{ + current_timestamp = time_stamp; +} +/** +* @bref Get rtc value +* +*/ +uint64_t rtc_get_timestamp(void) +{ + uint32_t tmpVal; + uint64_t time_l; + uint64_t time_h; + + /* Tigger RTC val read */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + + /* Read RTC val */ + time_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); + time_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); + + return (((time_h << 32 | time_l) >> 15) + current_timestamp); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c new file mode 100644 index 0000000000000000000000000000000000000000..691c7acb9d2315b8fc49c3ff37a0d9a00d217892 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c @@ -0,0 +1,119 @@ +/** + * @file hal_sec_aes.c + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_sec_aes.h" +#include "bl702_sec_eng.h" + +static SEC_Eng_AES_Ctx aesCtx; + +int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type) +{ + handle->aes_type = aes_tye; + handle->key_type = key_type; + + return 0; +} + +static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle) +{ + SEC_ENG_AES_Key_Type type = 0; + + switch (handle->key_type) { + case SEC_ASE_KEY_128: + type = SEC_ENG_AES_KEY_128BITS; + break; + + case SEC_ASE_KEY_256: + type = SEC_ENG_AES_KEY_256BITS; + break; + + case SEC_ASE_KEY_192: + type = SEC_ENG_AES_KEY_192BITS; + break; + + default: + return SEC_ENG_AES_KEY_128BITS; + } + + return type; +} + +int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir) +{ + SEC_ENG_AES_Key_Type type = sec_aes_get_key_type(handle); + + switch (handle->aes_type) { + case SEC_ASE_CBC: + Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); + Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CBC, type, + SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION); + break; + + case SEC_ASE_CTR: + Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); + Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CTR, type, + SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION); + break; + + case SEC_ASE_ECB: + break; + + default: + return -1; + } + + /* if key len is 0, means key is from efuse and *key value is key_sel value */ + if (key_len == 0) { + Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_HW, key, nonce); + } else { + Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_SW, key, nonce); + } + + return 0; +} + +int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out) +{ + if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) { + return -1; + } + + return 0; +} + +int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out) +{ + if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) { + return -1; + } + + return 0; +} + +int sec_aes_deinit(sec_aes_handle_t *handle) +{ + Sec_Eng_AES_Finish(SEC_ENG_AES_ID0); + + memset(handle, 0, sizeof(sec_aes_handle_t)); + + return 0; +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c new file mode 100644 index 0000000000000000000000000000000000000000..3929b90d6b28b6ce3ecc72ef75fec1568297c494 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c @@ -0,0 +1,389 @@ +/** + * @file hal_sec_dsa.c + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_sec_dsa.h" +#include "bl702_sec_eng.h" + +//#define DSA_DBG 1 +//#define DSA_DBG_DETAIL 1 +void bflb_platform_dump(uint8_t *data, uint32_t len); + +#if (defined(DSA_DBG) || defined(DSA_DBG_DETAIL)) +uint32_t pka_tmp[64] = { 0 }; +#endif + +/* +n=p*q; +F(n)=(p-1)*(q-1) +e*d%F(n)=1[e is public key and d is private key] +dP=d%(p-1) +dQ=d%(q-1) +m1=c^(dP)%p +m2=c^(dQ)%q +h=qInv*(m1-m2)%p +m=m2+h*q +m=c^d +*/ +static SEC_ENG_PKA_REG_SIZE_Type sec_dsa_get_reg_size(uint32_t size) +{ + switch (size) { + case 64: + return SEC_ENG_PKA_REG_SIZE_8; + + case 128: + return SEC_ENG_PKA_REG_SIZE_16; + + case 256: + return SEC_ENG_PKA_REG_SIZE_32; + + case 512: + return SEC_ENG_PKA_REG_SIZE_64; + + case 768: + return SEC_ENG_PKA_REG_SIZE_96; + + case 1024: + return SEC_ENG_PKA_REG_SIZE_128; + + case 1536: + return SEC_ENG_PKA_REG_SIZE_192; + + case 2048: + return SEC_ENG_PKA_REG_SIZE_256; + + case 3072: + return SEC_ENG_PKA_REG_SIZE_384; + + case 4096: + return SEC_ENG_PKA_REG_SIZE_512; + + default: + return SEC_ENG_PKA_REG_SIZE_32; + } + + return SEC_ENG_PKA_REG_SIZE_32; +} + +/* c code: +number = 1 +base = a +while b: + if b & 1: + number = number * base % c + b >>= 1 + base = base * base % c +return number +*/ +int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r) +{ + uint32_t i, j, k; + uint32_t tmp; + uint32_t isOne = 0; + uint8_t *p = (uint8_t *)b; + SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); + SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); + uint32_t dataSize = (size >> 3) >> 2; +#if 1 + uint8_t oneBuf[128] ALIGN4 = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; +#endif + /* 0:c + * 4:a + * 5:number + * 6&7:temp + */ + + /* base = a */ + Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0); + + /* number = 1 */ + Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)oneBuf, sizeof(oneBuf) / 4, 0); + //Sec_Eng_PKA_Write_Immediate(nregType,5,0x01,1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize); + MSG("number:\r\n"); + bflb_platform_dump(pka_tmp, dataSize * 4); +#endif + + Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0); + + Sec_Eng_PKA_CREG(nregType, 6, dataSize, 1); + Sec_Eng_PKA_CREG(nregType, 7, dataSize, 1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); + MSG("base:\r\n"); + bflb_platform_dump(pka_tmp, dataSize * 4); +#endif + /* Remove zeros bytes*/ + k = 0; + + while (p[k] == 0 && k < (size >> 3)) { + k++; + } + + i = (size >> 3) - 1; + + for (; i >= k; i--) { + tmp = p[i]; + j = 0; + + for (j = 0; j < 8; j++) { + isOne = tmp & (1 << j); + + if (isOne) { + /* number = number * base % c */ + Sec_Eng_PKA_LMUL(lregType, 3, nregType, 5, nregType, 4, 0); + Sec_Eng_PKA_MREM(nregType, 5, lregType, 3, nregType, 0, 1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize); + MSG("number:\r\n"); + bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); +#endif + } + + /* base = base * base % c */ + Sec_Eng_PKA_LSQR(lregType, 3, nregType, 4, 0); + Sec_Eng_PKA_MREM(nregType, 4, lregType, 3, nregType, 0, 1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); + MSG("base:\r\n"); + bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); +#endif + } + } + + Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)r, dataSize); +#ifdef DSA_DBG + MSG("r:\r\n"); + bflb_platform_dump(r, dataSize * 4); +#endif + return 0; +} + +/*r=a^b%c*/ +int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r) +{ + SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); + SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); + uint32_t dataSize = (size >> 3) >> 2; + + /* 0:c + * 1:NPrime_c + * 2:invR_c + * 4:a(mont domain) + * 5:b + * 6:a^b%c(mont domain) + * 7:a^b%c(gf domain) + * 10&11:2^size for GF2Mont*/ + Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0); + Sec_Eng_PKA_Write_Data(nregType, 1, (uint32_t *)primeN_c, dataSize, 1); + Sec_Eng_PKA_Write_Data(nregType, 2, (uint32_t *)invR_c, dataSize, 1); + + /* change a into mont domain*/ + Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0); + Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); + Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); + Sec_Eng_PKA_GF2Mont(nregType, 4, nregType, 4, size, lregType, 5, nregType, 0); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); + MSG("GF2Mont Result of a:\r\n"); + bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); +#endif + + Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)b, dataSize, 0); + /* a^b%c*/ + Sec_Eng_PKA_MEXP(nregType, 6, nregType, 4, nregType, 5, nregType, 0, 1); + + /* change result into gf domain*/ + Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); + Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); + /*index 2 is invertR*/ + Sec_Eng_PKA_Mont2GF(nregType, 7, nregType, 6, nregType, 2, lregType, 5, nregType, 0); + Sec_Eng_PKA_Read_Data(nregType, 7, (uint32_t *)r, dataSize); +#ifdef DSA_DBG + MSG("r:\r\n"); + bflb_platform_dump(r, dataSize /*dataSize*4*/); +#endif + return 0; +} + +/** + * dP=d%(p-1) + * dQ=d%(q-1) + * qInv=qp^(1-1):qInv*q%p=1 + * invR_p*r%p=1(r is 1024/2048/256) + * invR_q*r%q=1(r is 1024/2048/256) + */ +int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r) +{ + /* + * m1 = pow(c, dP, p) + * m2 = pow(c, dQ, q) + * h = (qInv * (m1 - m2)) % p + * m = m2 + h * q + * */ + SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); + SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); + uint32_t dataSize = (size >> 3) >> 2; +#if 0 + uint8_t m1[64] = {0x11, 0xdd, 0x19, 0x7e, 0x69, 0x1a, 0x40, 0x0a, 0x28, 0xfc, 0x3b, 0x31, 0x47, 0xa2, 0x6c, 0x14, + 0x4e, 0xf6, 0xb0, 0xe6, 0xcd, 0x89, 0x0b, 0x4f, 0x02, 0xe4, 0x86, 0xe2, 0xe5, 0xbe, 0xe1, 0xaf, + 0x91, 0xd1, 0x7b, 0x59, 0x8d, 0xdc, 0xb3, 0x57, 0x18, 0xcb, 0x80, 0x05, 0x1c, 0xb5, 0xa4, 0x07, + 0xde, 0x31, 0x94, 0xa4, 0x2f, 0x45, 0xc7, 0x95, 0x75, 0x0f, 0x91, 0xf0, 0x37, 0x91, 0x85, 0xa5 + }; + uint8_t m2[64] = {0x63, 0x89, 0xa3, 0xbb, 0x64, 0x63, 0x87, 0x4f, 0x38, 0xbd, 0x9e, 0x0e, 0x93, 0x29, 0x58, 0xee, + 0xf8, 0xe2, 0x20, 0x2d, 0xe5, 0x38, 0x0a, 0x7f, 0x18, 0x38, 0x2f, 0xa3, 0xf5, 0x48, 0xf8, 0xfd, + 0xe5, 0x78, 0x4a, 0x10, 0x62, 0x01, 0x09, 0x29, 0xe3, 0xe3, 0x9f, 0xad, 0x9b, 0xbe, 0x20, 0xd2, + 0x68, 0x90, 0x57, 0x97, 0xfc, 0x78, 0xd5, 0xdb, 0x07, 0x5b, 0xfe, 0x21, 0x0a, 0x2d, 0x7f, 0xc1 + }; +#else + uint32_t m1[32]; + uint32_t m2[32]; +#endif + /* + * 4:m1 + * 5:m2 + * 6:qInv + * 7:p + * 8:q + * 9:h + * 10&11:qInv*(m1-m2) + */ + sec_dsa_mexp_mont(size, c, crtCfg->dP, crtCfg->p, crtCfg->invR_p, crtCfg->primeN_p, m1); + sec_dsa_mexp_mont(size, c, crtCfg->dQ, crtCfg->q, crtCfg->invR_q, crtCfg->primeN_q, m2); + + Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)m1, dataSize, 0); + Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)m2, dataSize, 0); + Sec_Eng_PKA_Write_Data(nregType, 6, (uint32_t *)crtCfg->qInv, dataSize, 0); + Sec_Eng_PKA_Write_Data(nregType, 7, (uint32_t *)crtCfg->p, dataSize, 0); + Sec_Eng_PKA_Write_Data(nregType, 8, (uint32_t *)crtCfg->q, dataSize, 0); + + /*(m1 - m2)%p*/ + Sec_Eng_PKA_MSUB(nregType, 4, nregType, 4, nregType, 5, nregType, 7, 1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); + MSG("m1 - m2:\r\n"); + bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); +#endif + /* (qInv * (m1 - m2)) % p*/ + Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); + Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); + Sec_Eng_PKA_LMUL(lregType, 5, nregType, 6, nregType, 4, 1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2); + MSG("qInv * (m1 - m2):\r\n"); + bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/); +#endif + Sec_Eng_PKA_MREM(nregType, 9, lregType, 5, nregType, 7, 1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType, 9, (uint32_t *)pka_tmp, dataSize); + MSG("h:\r\n"); + bflb_platform_dump(pka_tmp, dataSize * 4); +#endif + + /* h*q */ + Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); + Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); + Sec_Eng_PKA_LMUL(lregType, 5, nregType, 9, nregType, 8, 1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2); + MSG("h*q:\r\n"); + bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/); +#endif + /* m2 + h*q*/ + Sec_Eng_PKA_LADD(lregType, 5, lregType, 5, nregType, 5, 1); + + Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)r, dataSize * 2); +#ifdef DSA_DBG + MSG("r:\r\n"); + bflb_platform_dump(r, dataSize * 4 * 2); +#endif + return 0; +} + +int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size) +{ + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + memset(handle, 0, sizeof(sec_dsa_handle_t)); + handle->size = size; + handle->crtSize = (size >> 1); + + return 0; +} + +int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s) +{ + uint32_t dsa_tmp[64] = { 0 }; + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + memcpy(dsa_tmp + ((handle->crtSize >> 3) >> 2) - hashLenInWord, hash, hashLenInWord * 4); + + if (0 == sec_dsa_decrypt_crt(handle->crtSize, dsa_tmp, &handle->crtCfg, handle->d, s)) { + return 0; + } else { + return -1; + } +} + +/** + */ +int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s) +{ + uint32_t dsa_tmp[64]; + uint8_t i = 0; + uint8_t resultOffset = 0; + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + if (0 == sec_dsa_mexp_binary(handle->size, s, handle->e, handle->n, dsa_tmp)) { + resultOffset = (handle->size >> 5) - hashLenInWord; + + for (i = 0; i < hashLenInWord; i++) { + if (dsa_tmp[resultOffset + i] != hash[i]) { + return -1; + } + } + + return 0; + } else { + return -1; + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c new file mode 100644 index 0000000000000000000000000000000000000000..196c122983e155985a165b49332c608ba33520d3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c @@ -0,0 +1,1248 @@ +#include "hal_sec_ecdsa.h" +#include "bl702_sec_eng.h" + +#define ECP_SECP256R1_REG_TYPE SEC_ENG_PKA_REG_SIZE_32 +#define ECP_SECP256R1_N_REG_INDEX 0 +#define ECP_SECP256R1_NPRIME_N_REG_INDEX 1 +#define ECP_SECP256R1_INVR_N_REG_INDEX 2 +#define ECP_SECP256R1_NPRIME_P_REG_INDEX 3 +#define ECP_SECP256R1_INVR_P_REG_INDEX 4 +#define ECP_SECP256R1_SIZE 32 +/* Used in verify */ +#define ECP_SECP256R1_S_REG_INDEX 5 +#define ECP_SECP256R1_BAR_S_REG_INDEX 6 +#define ECP_SECP256R1_HASH_REG_INDEX 6 //use ECP_SECP256R1_BAR_S_REG_INDEX since it's temp +#define ECP_SECP256R1_U1_REG_INDEX 7 +#define ECP_SECP256R1_LT_REG_TYPE SEC_ENG_PKA_REG_SIZE_64 +#define ECP_SECP256R1_LT_REG_INDEX 7 +#define ECP_SECP256R1_SLT_REG_TYPE SEC_ENG_PKA_REG_SIZE_128 +#define ECP_SECP256R1_SLT_REG_INDEX 3 + +//#define ECDSA_DBG 1 +//#define ECDSA_DBG_DETAIL 1 +void bflb_platform_dump(uint8_t *data, uint32_t len); + +#if (defined(ECDSA_DBG) || defined(ECDSA_DBG_DETAIL)) +uint32_t pka_tmp[32] = { 0 }; +#endif + +const uint8_t secp256r1P[32] ALIGN4 = { + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +}; +const uint8_t secp256r1B[32] ALIGN4 = { + 0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86, 0xbc, + 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2, 0x60, 0x4b +}; +const uint8_t secp256r1Gx[32] ALIGN4 = { + 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2, + 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96 +}; +const uint8_t secp256r1Gy[32] ALIGN4 = { + 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, + 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5 +}; +const uint8_t secp256r1N[32] ALIGN4 = { + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51 +}; +const uint8_t secp256r1PrimeN_N[32] ALIGN4 = { + 0x60, 0xd0, 0x66, 0x33, 0xa9, 0xd6, 0x28, 0x1c, 0x50, 0xfe, 0x77, 0xec, 0xc5, 0x88, 0xc6, 0xf6, + 0x48, 0xc9, 0x44, 0x08, 0x7d, 0x74, 0xd2, 0xe4, 0xcc, 0xd1, 0xc8, 0xaa, 0xee, 0x00, 0xbc, 0x4f +}; +const uint8_t secp256r1InvR_N[32] ALIGN4 = { + 0x60, 0xd0, 0x66, 0x33, 0x49, 0x05, 0xc1, 0xe9, 0x07, 0xf8, 0xb6, 0x04, 0x1e, 0x60, 0x77, 0x25, + 0xba, 0xde, 0xf3, 0xe2, 0x43, 0x56, 0x6f, 0xaf, 0xce, 0x1b, 0xc8, 0xf7, 0x9c, 0x19, 0x7c, 0x79 +}; +const uint8_t secp256r1PrimeN_P[32] ALIGN4 = { + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; +const uint8_t secp256r1InvR_P[32] ALIGN4 = { + 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x02, + 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 +}; +const uint8_t secp256r1_1[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; +const uint8_t secp256r1_BAR2[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 +}; +const uint8_t secp256r1_BAR3[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x02, 0xff, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 +}; +const uint8_t secp256r1_BAR4[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04 +}; +const uint8_t secp256r1_BAR8[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08 +}; +const uint8_t secp256r1_1P1[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 +}; +const uint8_t secp256r1_1M1[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +const uint8_t secp256r1_Zerox[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +const uint8_t secp256r1_Zeroy[32] ALIGN4 = { + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; +const uint8_t secp256r1_Gx[32] ALIGN4 = { + 0x18, 0x90, 0x5f, 0x76, 0xa5, 0x37, 0x55, 0xc6, 0x79, 0xfb, 0x73, 0x2b, 0x77, 0x62, 0x25, 0x10, + 0x75, 0xba, 0x95, 0xfc, 0x5f, 0xed, 0xb6, 0x01, 0x79, 0xe7, 0x30, 0xd4, 0x18, 0xa9, 0x14, 0x3c +}; +const uint8_t secp256r1_Gy[32] ALIGN4 = { + 0x85, 0x71, 0xff, 0x18, 0x25, 0x88, 0x5d, 0x85, 0xd2, 0xe8, 0x86, 0x88, 0xdd, 0x21, 0xf3, 0x25, + 0x8b, 0x4a, 0xb8, 0xe4, 0xba, 0x19, 0xe4, 0x5c, 0xdd, 0xf2, 0x53, 0x57, 0xce, 0x95, 0x56, 0x0a +}; + +static int sec_ecc_basic_parameter_init(uint8_t id) +{ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_NPRIME_N_REG_INDEX, (uint32_t *)secp256r1PrimeN_N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, (uint32_t *)secp256r1InvR_N, ECP_SECP256R1_SIZE / 4, 0); + + return 0; +} + +static int sec_ecc_point_mul_init(uint8_t id) +{ + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 1, (uint32_t *)secp256r1PrimeN_P, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 9, (uint32_t *)secp256r1_BAR2, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 10, (uint32_t *)secp256r1_BAR3, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 11, (uint32_t *)secp256r1_BAR4, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 12, (uint32_t *)secp256r1_BAR8, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 19, (uint32_t *)secp256r1_1P1, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 20, (uint32_t *)secp256r1_1M1, ECP_SECP256R1_SIZE / 4, 0); + + return 0; +} + +static void sec_ecdsa_point_add_inf_check(uint8_t *pka_p1_eq_inf, uint8_t *pka_p2_eq_inf) +{ + uint8_t res[4]; + + /* index 2:BAR_Zero_x + * index 3:BAR_Zero_y + * index 4:BAR_Zero_z + * index 5:BAR_G_x + * index 6:BAR_G_y + * index 7:BAR_G_z + * index 8:1 + * index 9:2 + * index 10:3 + * index 11:4 + * index 12:8 + * index 19:1P1 + * index 20:1m1*/ + + //cout = 1 if X1 = 0 + Sec_Eng_PKA_LCMP(res, 3, 2, 3, 8); //s0 < s1 => cout = 1 + //cout = 1 if Y1 < Bar_1p1 + Sec_Eng_PKA_LCMP(res + 1, 3, 3, 3, 19); + //cout=1 if Y1 > Bar_1m1 + Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 3); + //cout =1 if Z1 = 0 + Sec_Eng_PKA_LCMP(res + 3, 3, 4, 3, 8); + *pka_p1_eq_inf = res[0] & res[1] & res[2] & res[3]; + + //cout = 1 if X2 = 0 + Sec_Eng_PKA_LCMP(res, 3, 5, 3, 8); + // cout = 1 if Y2 < Bar_1p1 + Sec_Eng_PKA_LCMP(res + 1, 3, 6, 3, 19); + //cout = 1 if Y2 > Bar_1m1 + Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 6); + //cout = 1 if Z2 = 0 + Sec_Eng_PKA_LCMP(res + 3, 3, 7, 3, 8); + *pka_p2_eq_inf = res[0] & res[1] & res[2] & res[3]; +} + +static void sec_ecdsa_copy_x2_to_x1(uint8_t id) +{ + //X2->X1 + Sec_Eng_PKA_Move_Data(3, 2, 3, 5, 0); + //Y2->Y1 + Sec_Eng_PKA_Move_Data(3, 3, 3, 6, 0); + //Z2->Z1 + Sec_Eng_PKA_Move_Data(3, 4, 3, 7, 1); //Caution!!! wait movdat ready to execute next command +} + +static void sec_ecdsa_point_add(uint8_t id) +{ + /* index 2:BAR_Zero_x + * index 3:BAR_Zero_y + * index 4:BAR_Zero_z + * index 5:BAR_G_x + * index 6:BAR_G_y + * index 7:BAR_G_z + * index 8:1 + * index 9:2 + * index 10:3 + * index 11:4 + * index 12:8 + * index 19:1P1 + * index 20:1m1*/ + + //U1 = Y2*Z1 + //PKA_MMUL(0,3,13,3, 6,3, 4,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx + Sec_Eng_PKA_MMUL(3, 13, 3, 6, 3, 4, 3, 0, 0); + + //U2 = Y1*Z2 + //PKA_MMUL(0,3,14,3, 3,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 14, 3, 3, 3, 7, 3, 0, 0); + + //V1 = X2*Z1 + //PKA_MMUL(0,3,15,3, 5,3, 4,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 4, 3, 0, 0); + + //V2 = X1*Z2 + //PKA_MMUL(0,3,16,3, 2,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 16, 3, 2, 3, 7, 3, 0, 0); + + //U = U1-U2 + //PKA_MSUB(0,3,13,3,13,3,14,3,0); + Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0); + + //V = V1-V2 + //PKA_MSUB(0,3,15,3,15,3,16,3,0); + Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 16, 3, 0, 0); + + //W = Z1*Z2 + //PKA_MMUL(0,3, 2,3, 4,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 2, 3, 4, 3, 7, 3, 0, 0); + + //V^2 + //PKA_MMUL(0,3, 3,3,15,3,15,3,0); + Sec_Eng_PKA_MMUL(3, 3, 3, 15, 3, 15, 3, 0, 0); + + //V^3 + //PKA_MMUL(0,3, 4,3, 3,3,15,3,0); + Sec_Eng_PKA_MMUL(3, 4, 3, 3, 3, 15, 3, 0, 0); + + //U^2 + //PKA_MMUL(0,3,17,3,13,3,13,3,0); + Sec_Eng_PKA_MMUL(3, 17, 3, 13, 3, 13, 3, 0, 0); + + //U^2*W + //PKA_MMUL(0,3,17,3,17,3, 2,3,0); + Sec_Eng_PKA_MMUL(3, 17, 3, 17, 3, 2, 3, 0, 0); + + //U^2*W-V^3 + //PKA_MSUB(0,3,17,3,17,3, 4,3,0); + Sec_Eng_PKA_MSUB(3, 17, 3, 17, 3, 4, 3, 0, 0); + + //2*V^2 + //PKA_MMUL(0,3,18,3, 9,3, 3,3,0); + Sec_Eng_PKA_MMUL(3, 18, 3, 9, 3, 3, 3, 0, 0); + + //2*V^2*V2 + //PKA_MMUL(0,3,18,3,18,3,16,3,0); + Sec_Eng_PKA_MMUL(3, 18, 3, 18, 3, 16, 3, 0, 0); + + //A = U^2*W-V^3-2*V^2*V2 + //PKA_MSUB(0,3,18,3,17,3,18,3,0); + Sec_Eng_PKA_MSUB(3, 18, 3, 17, 3, 18, 3, 0, 0); + + //V^2*V2 + //PKA_MMUL(0,3, 3,3, 3,3,16,3,0); + Sec_Eng_PKA_MMUL(3, 3, 3, 3, 3, 16, 3, 0, 0); + + //V^3*U2 + //PKA_MMUL(0,3,14,3, 4,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 14, 3, 4, 3, 14, 3, 0, 0); + + //Z3 = V^3*W + //PKA_MMUL(0,3, 4,3, 4,3, 2,3,0); + Sec_Eng_PKA_MMUL(3, 4, 3, 4, 3, 2, 3, 0, 0); + + //X3 = V*A + //PKA_MMUL(0,3, 2,3,15,3,18,3,0); + Sec_Eng_PKA_MMUL(3, 2, 3, 15, 3, 18, 3, 0, 0); + + //V^2*V2-A + //PKA_MSUB(0,3, 3,3, 3,3,18,3,0); + Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 18, 3, 0, 0); + + //U*(V^2*V2-A) + //PKA_MMUL(0,3, 3,3,13,3, 3,3,0); + Sec_Eng_PKA_MMUL(3, 3, 3, 13, 3, 3, 3, 0, 0); + + //Y3 = U*(V^2*V2-A)-V^3*U2 + //PKA_MSUB(1,3, 3,3, 3,3,14,3,0); + Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 14, 3, 0, 1); +} + +static void sec_ecdsa_point_double(uint8_t id) +{ + /* index 2:BAR_Zero_x + * index 3:BAR_Zero_y + * index 4:BAR_Zero_z + * index 5:BAR_G_x + * index 6:BAR_G_y + * index 7:BAR_G_z + * index 8:1 + * index 9:2 + * index 10:3 + * index 11:4 + * index 12:8 + * index 19:1P1 + * index 20:1m1*/ + + //X1^2 + //PKA_MMUL(0,3,13,3, 5,3, 5,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx + Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0); + + //Z1^2 + //PKA_MMUL(0,3,14,3, 7,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 14, 3, 7, 3, 7, 3, 0, 0); + + //X1^2-Z1^2 + //PKA_MSUB(0,3,13,3,13,3,14,3,0); + Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0); + + //W = 3*(X1^2-Z1^2) + //PKA_MMUL(0,3,13,3,10,3,13,3,0); + Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0); + + //S = Y1*Z1 + //PKA_MMUL(0,3,14,3, 6,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 14, 3, 6, 3, 7, 3, 0, 0); + + //X1*Y1 + //PKA_MMUL(0,3,15,3, 5,3, 6,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 6, 3, 0, 0); + + //W^2 + //PKA_MMUL(0,3, 7,3,13,3,13,3,0); + Sec_Eng_PKA_MMUL(3, 7, 3, 13, 3, 13, 3, 0, 0); + + //B = X1*Y1*S + //PKA_MMUL(0,3,15,3,15,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 14, 3, 0, 0); + + //8*B + //PKA_MMUL(0,3, 5,3,12,3,15,3,0); + Sec_Eng_PKA_MMUL(3, 5, 3, 12, 3, 15, 3, 0, 0); + + //H = W^2-8*B + //PKA_MSUB(0,3, 7,3, 7,3, 5,3,0); + Sec_Eng_PKA_MSUB(3, 7, 3, 7, 3, 5, 3, 0, 0); + + //2*H + //PKA_MMUL(0,3, 5,3, 9,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 5, 3, 9, 3, 7, 3, 0, 0); + + //X2 = 2*H*S + //PKA_MMUL(0,3, 5,3, 5,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 5, 3, 5, 3, 14, 3, 0, 0); + + //4*B + //PKA_MMUL(0,3,15,3,11,3,15,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 11, 3, 15, 3, 0, 0); + + //S^2 + //PKA_MMUL(0,3,16,3,14,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 16, 3, 14, 3, 14, 3, 0, 0); + + //4*B-H + //PKA_MSUB(0,3,15,3,15,3, 7,3,0); + Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 7, 3, 0, 0); + + //Y1^2 + //PKA_MMUL(0,3, 6,3, 6,3, 6,3,0); + Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 6, 3, 0, 0); + + //W*(4*B-H) + //PKA_MMUL(0,3,15,3,15,3,13,3,0); + Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 13, 3, 0, 0); + + //8*Y1^2 + //PKA_MMUL(0,3, 6,3,12,3, 6,3,0); + Sec_Eng_PKA_MMUL(3, 6, 3, 12, 3, 6, 3, 0, 0); + + //8*Y1^2*S^2 + //PKA_MMUL(0,3, 6,3, 6,3,16,3,0); + Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 16, 3, 0, 0); + + //Y2 = W*(4*B-H)-8*Y1^2*S^2 + //PKA_MSUB(0,3, 6,3,15,3, 6,3,0); + Sec_Eng_PKA_MSUB(3, 6, 3, 15, 3, 6, 3, 0, 0); + + //S^3 + //PKA_MMUL(0,3, 7,3,14,3,16,3,0); + Sec_Eng_PKA_MMUL(3, 7, 3, 14, 3, 16, 3, 0, 0); + + //Z2 = 8*S^3 + //PKA_MMUL(1,3, 7,3,12,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 7, 3, 12, 3, 7, 3, 0, 1); +} +#ifdef ECDSA_DBG_DETAIL +static void sec_ecdsa_dump_temp_result() +{ + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("2=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("3=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("4=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("5=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("6=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 7, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("7=\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +} +#endif +static int sec_ecdsa_verify_point_mul(uint8_t id, const uint32_t *m) +{ + uint32_t i, j, k; + uint32_t tmp; + uint32_t isOne = 0; + uint8_t *p = (uint8_t *)m; + uint8_t pka_p1_eq_inf, pka_p2_eq_inf; + + /* Remove zeros bytes*/ + k = 0; + + while (p[k] == 0 && k < 31) { + k++; + } + + i = 31; + + for (; i >= k; i--) { + tmp = p[i]; + j = 0; + + for (j = 0; j < 8; j++) { + isOne = tmp & (1 << j); + + if (isOne) { + sec_ecdsa_point_add_inf_check(&pka_p1_eq_inf, &pka_p2_eq_inf); + + if (pka_p1_eq_inf == 1 && pka_p2_eq_inf == 0) { + //sum = X2 + sec_ecdsa_copy_x2_to_x1(id); +#ifdef ECDSA_DBG_DETAIL + MSG("sum = X2\r\n"); + sec_ecdsa_dump_temp_result(); +#endif + } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 1) { + //sum = X1 + MSG("sum = X1\r\n"); + } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 0) { + //sum = X1 + X2 + sec_ecdsa_point_add(id); +#ifdef ECDSA_DBG_DETAIL + MSG("sum = X1+X2\r\n"); + sec_ecdsa_dump_temp_result(); +#endif + } else { + MSG("Error! infinite point + infinite point\r\n"); + return -1; + } + } + + sec_ecdsa_point_double(id); +#ifdef ECDSA_DBG_DETAIL + sec_ecdsa_dump_temp_result(); +#endif + } + + if (i == 0) { + break; + } + } + + return 0; +} + +/*cal d*G if pkX(pky)==NULL + * cal d(bG) if pkX(pky)!=NULL */ +static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) +{ +#ifdef ECDSA_DBG + uint32_t pk_z[8]; +#endif + + /* Pointer check */ + if (private_key == NULL) { + return -1; + } + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + sec_ecc_basic_parameter_init(id); + + //Clear D[7] + //PKA_CREG(1,4, 7,0); + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); + + sec_ecc_point_mul_init(id); + + //X1 + //PKA_CTREG(3, 2,8,bar_Zero_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); + //Y1 + //PKA_CTREG(3, 3,8,bar_Zero_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); + //Z1 + //PKA_CTREG(3, 4,8,bar_Zero_z); + //PKA_MOVDAT(1,3, 4,3, 2); + Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); + + if (pkX == NULL) { + //X2 + //PKA_CTREG(3, 5,8,bar_G_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0); + //Y2 + //PKA_CTREG(3, 6,8,bar_G_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0); + } else { + /* chaneg peer's public key to mont domain*/ + //PUB_x + //PKA_CTREG(3, 5,8,PUB_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pkX, ECP_SECP256R1_SIZE / 4, 0); + //bar_pub_x + //PKA_GF2MONT(3, 5,3, 5); + /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("PK.x in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + //PUB_y + //PKA_CTREG(3, 6,8,PUB_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pkY, ECP_SECP256R1_SIZE / 4, 0); + //bar_pub_y + //PKA_GF2MONT(3, 6,3, 6); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("PK.y in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + } + + //Z2 + //PKA_CTREG(3, 7,8,bar_G_z); + //PKA_MOVDAT(1,3, 7,3, 3); + Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); + /* Clear temp register since it's used in point-mul*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); + + sec_ecdsa_verify_point_mul(id, private_key); + //get bar_u1_x + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_x\r\n"); + bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_y\r\n"); + bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); +#endif +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pk_z, ECP_SECP256R1_SIZE / 4); + MSG("bar_u1_z\r\n"); + bflb_platform_dump(pk_z, ECP_SECP256R1_SIZE); +#endif + + //get R.x + //R.z ^ -1 + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); + //inv_r + //PKA_CTREG(3, 6,8,inv_r); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); + //R.z ^ -1 + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + //PKA_MONT2GF(3, 5,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (Montgomery to GF) + //PKA_MONT2GF(3, 6,3, 2,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (GF to Affine domain) + //PKA_MONT2GF(3, 2,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.x=\r\n"); + bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 2, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.x%n=\r\n"); + bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); +#endif + + /*after %n,re write p*/ + Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0); + //get R.y + //R.z ^ -1 + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); + //inv_r + //PKA_CTREG(3, 6,8,inv_r); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); + //R.z ^ -1 + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + //PKA_MONT2GF(3, 5,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + //R.x (Montgomery to GF) + //PKA_MONT2GF(3, 6,3, 2,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (GF to Affine domain) + //PKA_MONT2GF(3, 2,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.y=\r\n"); + bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 3, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.y%n=\r\n"); + bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); +#endif + return 0; +} + +static int32_t sec_ecc_is_zero(uint8_t *a, uint32_t len) +{ + uint32_t i = 0; + + for (i = 0; i < len; i++) { + if (a[i] != 0) { + return 0; + } + } + + return 1; +} + +static int32_t sec_ecc_cmp(uint8_t *a, uint8_t *b, uint32_t len) +{ + uint32_t i = 0, j = 0; + + for (i = 0; i < len; i++) { + if (a[i] != 0) { + break; + } + } + + for (j = 0; j < len; j++) { + if (b[j] != 0) { + break; + } + } + + if (i == len && j == len) { + return (0); + } + + if (i > j) { + return (-1); + } + + if (j > i) { + return (1); + } + + for (; i < len; i++) { + if (a[i] > b[i]) { + return (1); + } + + if (a[i] < b[i]) { + return (-1); + } + } + + return 0; +} + +int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id) +{ + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + handle->ecpId = id; + + return 0; +} + +int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle) +{ + Sec_Eng_PKA_Reset(); + + return 0; +} + +int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *r, const uint32_t *s) +{ + uint32_t bar_u1_x[8]; + uint32_t bar_u1_y[8]; + uint32_t bar_u1_z[8]; + uint32_t bar_u2_x[8]; + uint32_t bar_u2_y[8]; + uint32_t bar_u2_z[8]; + uint32_t pka_u1[8] = { 0 }; + uint32_t pka_u2[8] = { 0 }; + uint32_t i = 0; + + /* Pointer check */ + if (hash == NULL || handle->publicKeyx == NULL || handle->publicKeyy == NULL || r == NULL || s == NULL) { + return -1; + } + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + /*Step 0: make sure r and s are in range 1..n-1*/ + + /* r and s should not be 0*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0); + //cout = 1 if r = 0 + Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1 + + if (i == 1) { + return -1; + } + + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); + //cout = 1 if r = 0 + Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1 + + if (i == 1) { + return -1; + } + + sec_ecc_basic_parameter_init(handle->ecpId); + + /* r and s should not be 0*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); + //cout = 1 if r < N + Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); + + if (i != 1) { + return -1; + } + + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); + //cout = 1 if r < N + Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); + + if (i != 1) { + return -1; + } + + /* u1 = e / s mod n, u2 = r / s mod n + * R = u1 G + u2 Q*/ + + /* Step1: Get S^-1*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); + /* Change s to Mont domain */ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("GF2Mont Result of s:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + /* Get S^-1 in Mont domain */ + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("s^-1 in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + /* Change S^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store s^-1*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("S^-1:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + /* Step2: Get u1*/ + //u1=hash(e)*s^-1; + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u1, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("u1:\r\n"); + bflb_platform_dump(pka_u1, ECP_SECP256R1_SIZE); +#endif + + /* Step3: Get u2*/ + //u2=r*s^-1; + // use hash and u1 temp register + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u2, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("u2:\r\n"); + bflb_platform_dump(pka_u2, ECP_SECP256R1_SIZE); +#endif + + /* Step4: Get u1*G*/ + + //Clear D[7] + //PKA_CREG(1,4, 7,0); + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); + + sec_ecc_point_mul_init(handle->ecpId); + + //X1 + //PKA_CTREG(3, 2,8,bar_Zero_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); + //Y1 + //PKA_CTREG(3, 3,8,bar_Zero_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); + //Z1 + //PKA_CTREG(3, 4,8,bar_Zero_z); + //PKA_MOVDAT(1,3, 4,3, 2); + Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); + + //X2 + //PKA_CTREG(3, 5,8,bar_G_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0); + //Y2 + //PKA_CTREG(3, 6,8,bar_G_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0); + //Z2 + //PKA_CTREG(3, 7,8,bar_G_z); + //PKA_MOVDAT(1,3, 7,3, 3); + Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); + + sec_ecdsa_verify_point_mul(handle->ecpId, pka_u1); + //get bar_u1_x + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_x\r\n"); + bflb_platform_dump(bar_u1_x, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_y\r\n"); + bflb_platform_dump(bar_u1_y, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u1_z\r\n"); + bflb_platform_dump(bar_u1_z, ECP_SECP256R1_SIZE); +#endif + + /* Step4: Get u2*Q*/ + //X1 + //PKA_CTREG(3, 2,8,bar_Zero_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); + //Y1 + //PKA_CTREG(3, 3,8,bar_Zero_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); + //Z1 + //PKA_CTREG(3, 4,8,bar_Zero_z); + //PKA_MOVDAT(1,3, 4,3, 2); + Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); + + //PUB_x + //PKA_CTREG(3, 5,8,PUB_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)handle->publicKeyx, ECP_SECP256R1_SIZE / 4, 0); + //bar_pub_x + //PKA_GF2MONT(3, 5,3, 5); + /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("PK.x in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + //PUB_y + //PKA_CTREG(3, 6,8,PUB_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)handle->publicKeyy, ECP_SECP256R1_SIZE / 4, 0); + //bar_pub_y + //PKA_GF2MONT(3, 6,3, 6); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("PK.y in Mont:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + //bar_pub_z + //PKA_CTREG(3, 7,8,PUB_z); + //PKA_MOVDAT(1,3, 7,3, 3); + Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); + + /* Clear temp register since it's used in point-mul*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); + + sec_ecdsa_verify_point_mul(handle->ecpId, pka_u2); + //get bar_u1_x + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u2_x\r\n"); + bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u2_y, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u2_y\r\n"); + bflb_platform_dump(bar_u2_y, ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u2_z, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("bar_u2_z\r\n"); + bflb_platform_dump(bar_u2_z, ECP_SECP256R1_SIZE); +#endif + + /* Step5: Get u1*G+u2*Q*/ + //move bar_u2_x + //PKA_MOVDAT(0,3, 5,3, 2); + Sec_Eng_PKA_Move_Data(3, 5, 3, 2, 0); + //move bar_u2_y + //PKA_MOVDAT(0,3, 6,3, 3); + Sec_Eng_PKA_Move_Data(3, 6, 3, 3, 0); + //move bar_u2_z + //PKA_MOVDAT(1,3, 7,3, 4); + Sec_Eng_PKA_Move_Data(3, 7, 3, 4, 1); + + //bar_u1_x + //PKA_CTREG(3, 2,8,bar_u1_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4, 0); + //bar_u1_y + //PKA_CTREG(3, 3,8,bar_u1_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4, 0); + //bar_u1_z + //PKA_CTREG(3, 4,8,bar_u1_z); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4, 0); + + //R = u1 * G + u2 * PUB + //PKA_POINT_ADDITION(); + sec_ecdsa_point_add(handle->ecpId); + + /* Step6 Get R.x(R=u1G+u2P)*/ + //R.z ^ -1 + //PKA_MINV(0,3, 5,3, 4,3, 0); + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); + //inv_r + //PKA_CTREG(3, 6,8,inv_r); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); + //R.z ^ -1 + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + //PKA_MONT2GF(3, 5,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (Montgomery to GF) + //PKA_MONT2GF(3, 6,3, 2,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + + //R.x (GF to Affine domain) + //PKA_MONT2GF(3, 2,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("R.x=\r\n"); + bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE); +#endif + + /* Step7 check R.x=r*/ + /* Check Result */ + for (i = 0; i < 8; i++) { + if (bar_u2_x[i] != r[i]) { + return -1; + } + } + +#ifdef ECDSA_DBG + MSG("Verify success\r\n"); +#endif + return 0; +} + +int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s) +{ + uint32_t k[8]; + uint32_t Rx[8]; + uint32_t Ry[8]; + uint32_t KInvert[8]; + uint32_t maxTry1 = 100; + + /* Pointer check */ + if (handle->privateKey == NULL || hash == NULL || r == NULL || s == NULL) { + return -1; + } + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + while (maxTry1--) { + /* step 1 ,get random k*/ + if (random_k == NULL) { + if (sec_ecc_get_random_value(k, (uint32_t *)secp256r1N, 32) < 0) { + return -1; + } + } else { + memcpy(k, random_k, 32); + } + +#ifdef ECDSA_DBG + MSG("Random k:\r\n"); + bflb_platform_dump(k, ECP_SECP256R1_SIZE); +#endif + + /*step 2, calc R=kG*/ + if (sec_ecdsa_get_public_key(handle, k, Rx, Ry) < 0) { + return -1; + } + + if (sec_ecc_is_zero((uint8_t *)Rx, 32)) { + continue; + } + + memcpy(r, Rx, 32); +#ifdef ECDSA_DBG + MSG("r:\r\n"); + bflb_platform_dump(r, ECP_SECP256R1_SIZE); +#endif + sec_ecc_basic_parameter_init(handle->ecpId); + /* step 3,get k^-1*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)k, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + /* Change k to Mont domain */ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); + MSG("GF2Mont Result of k:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); +#endif + + /* Get k^-1 in Mont domain */ + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 5, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4); + MSG("k^-1 in Mont:\r\n"); + bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE); +#endif + + /* Change k^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store k^-1*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, + ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("k^-1:\r\n"); + bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE); +#endif + + /* Step 4,r*d ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)handle->privateKey, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 4, + ECP_SECP256R1_REG_TYPE, 5, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); + MSG("r*d:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); +#endif + + /* Step 5,e+r*d ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LADD(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, 5, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); + MSG("e+r*d:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); +#endif + + /* Step 6,(e+r*d)*k^-1 ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, 5, 1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); + MSG("(e+r*d)*k^-1:\r\n"); + bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); +#endif + /*N write only this time,add following operation will not change this register*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)s, ECP_SECP256R1_SIZE / 4); +#ifdef ECDSA_DBG + MSG("s:\r\n"); + bflb_platform_dump(s, ECP_SECP256R1_SIZE); +#endif + + /* Check s zero*/ + if (sec_ecc_is_zero((uint8_t *)s, 32)) { + continue; + } + + return 0; + } + + return -1; +} + +int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key) +{ + if (sec_ecc_get_random_value(private_key, (uint32_t *)secp256r1N, 32) < 0) { + return -1; + } + + return 0; +} + +int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy); +} + +int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size) +{ + uint32_t maxTry = 100; + int32_t ret = 0; + + while (maxTry--) { + ret = Sec_Eng_Trng_Get_Random((uint8_t *)randomData, size); + + if (ret < 0) { + return -1; + } + + if (maxRef != NULL) { + if (sec_ecc_cmp((uint8_t *)maxRef, (uint8_t *)randomData, size) > 0) { + return 0; + } + } else { + return 0; + } + } + + return -1; +} + +int sec_eng_trng_enable(void) +{ + return Sec_Eng_Trng_Enable(); +} + +void sec_eng_trng_disable(void) +{ + Sec_Eng_Trng_Disable(); +} + +int sec_eng_trng_read(uint8_t data[32]) +{ + return Sec_Eng_Trng_Read(data); +} + +int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id) +{ + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + handle->ecpId = id; + + return 0; +} + +int sec_ecdh_deinit(sec_ecdh_handle_t *handle) +{ + Sec_Eng_PKA_Reset(); + + return 0; +} + +int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId, pkX, pkY, private_key, pRx, pRy); +} + +int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c new file mode 100644 index 0000000000000000000000000000000000000000..cb04e632ff3e4149353a3c453beaf278ce60d655 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c @@ -0,0 +1,252 @@ +/** + * @file hal_sec_hash.c + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_sec_hash.h" +#include "bl702_sec_eng.h" + +void SEC_SHA_IRQHandler(void); + +static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] = { + 0 +}; +static SEC_Eng_SHA256_Ctx shaCtx; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int sec_hash_open(struct device *dev, uint16_t oflag) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret = 0; + + switch (sec_hash_device->type) { + case SEC_HASH_SHA1: + ret = -1; + break; + + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, sec_hash_device->shaBuf, sec_hash_device->shaPadding); + Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); + break; + + case SEC_HASH_SHA256: + Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, sec_hash_device->shaBuf, sec_hash_device->shaPadding); + Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); + break; + + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret = -1; + break; + + default: + ret = -1; + break; + } + + return ret; +} +/** + * @brief + * + * @param dev + * @return int + */ +int sec_hash_close(struct device *dev) +{ + //sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + //memset(sec_hash_device, 0, sizeof(sec_hash_device_t)); //will cause crash + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int sec_hash_control(struct device *dev, int cmd, void *args) +{ + return 0; +} + +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret = 0; + + switch (sec_hash_device->type) { + case SEC_HASH_SHA1: + ret = -1; + break; + + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); + break; + + case SEC_HASH_SHA256: + Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); + break; + + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret = -1; + break; + + default: + ret = -1; + break; + } + + return ret; +} + +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret = 0; + + switch (sec_hash_device->type) { + case SEC_HASH_SHA1: + ret = -1; + break; + + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); + ret = 28; + break; + + case SEC_HASH_SHA256: + Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); + ret = 32; + break; + + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret = -1; + break; + + default: + ret = -1; + break; + } + + return ret; +} + +/** + * @brief + * + * @param index + * @param type + * @param name + * @param flag + * @return int + */ +static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type, const char *name) +{ + struct device *dev; + + if (SEC_HASH_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(sec_hashx_device[index].parent); + sec_hashx_device[index].type = type; + + dev->open = sec_hash_open; + dev->close = sec_hash_close; + dev->control = sec_hash_control; + dev->write = sec_hash_write; + dev->read = sec_hash_read; + + dev->type = DEVICE_CLASS_SEC_HASH; + dev->handle = NULL; + + return device_register(dev, name); +} + +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name) +{ + return sec_hash_sha_register(index, SEC_HASH_SHA256, name); +} + +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name) +{ + return sec_hash_sha_register(index, SEC_HASH_SHA224, name); +} + +/** + * @brief + * + * @param handle + */ +void sec_hash_isr(sec_hash_device_t *handle) +{ +} + +/** + * @brief + * + */ +void SEC_SHA_IRQ(void) +{ + sec_hash_isr(&sec_hashx_device[0]); +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_spi.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..d3a3b18a5324f9286763606f3ec351011d56113d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_spi.c @@ -0,0 +1,519 @@ +/** + * @file hal_spi.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_spi.h" +#include "hal_dma.h" +#include "hal_gpio.h" +#include "bl702_glb.h" +#include "bl702_spi.h" +#include "spi_config.h" + +#ifdef BSP_USING_SPI0 +static void SPI0_IRQ(void); +#endif + +static spi_device_t spix_device[SPI_MAX_INDEX] = { +#ifdef BSP_USING_SPI0 + SPI0_CONFIG, +#endif +}; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int spi_open(struct device *dev, uint16_t oflag) +{ + spi_device_t *spi_device = (spi_device_t *)dev; + SPI_CFG_Type spiCfg = { 0 }; + SPI_FifoCfg_Type fifoCfg = { 0 }; +#if SPI_SWAP_ENABLE + GLB_Swap_SPI_0_MOSI_With_MISO(ENABLE); +#endif + + SPI_IntMask(spi_device->id, SPI_INT_ALL, MASK); + /* Enable uart interrupt*/ + CPU_Interrupt_Disable(SPI_IRQn); + + SPI_Disable(spi_device->id, spi_device->mode); + + GLB_Set_SPI_0_ACT_MOD_Sel(spi_device->mode); + GLB_Set_SPI_CLK(ENABLE, 0); + /* Set SPI clock */ + SPI_ClockCfg_Type clockCfg = { + 2, /* Length of start condition */ + 2, /* Length of stop condition */ + 2, /* Length of data phase 0,affecting clock */ + 2, /* Length of data phase 1,affecting clock */ + 2 /* Length of interval between frame */ + }; + + if (spi_device->clk > 72 * 1000000) { + return -1; + } + + uint8_t length = 72 * 1000000 / spi_device->clk; + + if (!(length % 2)) { + clockCfg.dataPhase0Len = length / 2; + clockCfg.dataPhase1Len = length / 2; + } else { + clockCfg.dataPhase0Len = length / 2; + clockCfg.dataPhase1Len = length / 2 + 1; + } + + SPI_ClockConfig(spi_device->id, &clockCfg); + + spiCfg.deglitchEnable = SPI_DEGLITCH_ENABLE; + spiCfg.continuousEnable = SPI_CONTINUE_TRANSFER_ENABLE; + + if (spi_device->direction == SPI_LSB_BYTE0_DIRECTION_FIRST) { + spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST; + spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST; + } else if (spi_device->direction == SPI_LSB_BYTE3_DIRECTION_FIRST) { + spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST; + spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE3_FIRST; + } else if (spi_device->direction == SPI_MSB_BYTE0_DIRECTION_FIRST) { + spiCfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST; + spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST; + } else if (spi_device->direction == SPI_MSB_BYTE3_DIRECTION_FIRST) { + spiCfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST; + spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE3_FIRST; + } + + spiCfg.clkPolarity = spi_device->clk_polaraity; + spiCfg.clkPhaseInv = spi_device->clk_phase; + spiCfg.frameSize = spi_device->datasize; + + /* SPI config */ + SPI_Init(spi_device->id, &spiCfg); + + fifoCfg.txFifoThreshold = spi_device->fifo_threshold; + fifoCfg.txFifoDmaEnable = DISABLE; + fifoCfg.rxFifoThreshold = spi_device->fifo_threshold; + fifoCfg.rxFifoDmaEnable = DISABLE; + + if (oflag & DEVICE_OFLAG_INT_TX || oflag & DEVICE_OFLAG_INT_RX) { +#ifdef BSP_USING_SPI0 + Interrupt_Handler_Register(SPI_IRQn, SPI0_IRQ); +#endif + } + + if (oflag & DEVICE_OFLAG_DMA_TX) { + fifoCfg.txFifoDmaEnable = ENABLE; + } + + if (oflag & DEVICE_OFLAG_DMA_RX) { + fifoCfg.rxFifoDmaEnable = ENABLE; + } + + SPI_FifoConfig(spi_device->id, &fifoCfg); + /* Enable spi master mode */ + SPI_Enable(spi_device->id, spi_device->mode); + + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int spi_close(struct device *dev) +{ + spi_device_t *spi_device = (spi_device_t *)dev; + + SPI_Disable(spi_device->id, spi_device->mode); + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int spi_control(struct device *dev, int cmd, void *args) +{ + spi_device_t *spi_device = (spi_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: + + break; + + case DEVICE_CTRL_CLR_INT /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_RESUME: + /* code */ + SPI_Enable(spi_device->id, spi_device->mode); + break; + + case DEVICE_CTRL_SUSPEND: + SPI_Disable(spi_device->id, spi_device->mode); + break; + + case DEVICE_CTRL_CONFIG /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */: + spi_device->tx_dma = (struct device *)args; + break; + + case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */: + spi_device->rx_dma = (struct device *)args; + break; + + case DEVICE_CTRL_SPI_CONFIG_CLOCK /* constant-expression */: + SPI_SetClock(spi_device->id, (uint32_t)args); + break; + + case DEVICE_CTRL_TX_DMA_SUSPEND: { + uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0); + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_TX_EN); + BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal); + dev->oflag &= ~DEVICE_OFLAG_DMA_TX; + break; + } + + case DEVICE_CTRL_RX_DMA_SUSPEND: { + uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0); + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_RX_EN); + BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal); + dev->oflag &= ~DEVICE_OFLAG_DMA_RX; + break; + } + + case DEVICE_CTRL_TX_DMA_RESUME: { + uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_TX_EN); + BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal); + dev->oflag |= DEVICE_OFLAG_DMA_TX; + break; + } + + case DEVICE_CTRL_RX_DMA_RESUME: { + uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_RX_EN); + BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal); + dev->oflag |= DEVICE_OFLAG_DMA_RX; + break; + } + + default: + break; + } + + return 0; +} +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int spi_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + spi_device_t *spi_device = (spi_device_t *)dev; + + if (dev->oflag & DEVICE_OFLAG_DMA_TX) { + struct device *dma_ch = (struct device *)spi_device->tx_dma; + + if (!dma_ch) { + return -1; + } + + if (spi_device->id == 0) { + /* Set valid width for each fifo entry */ + uint32_t tmpVal; + uint32_t SPIx = SPI_BASE; + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + switch (DMA_DEV(dma_ch)->dst_width) { + case DMA_TRANSFER_WIDTH_8BIT: + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0)); + break; + case DMA_TRANSFER_WIDTH_16BIT: + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1)); + break; + + case DMA_TRANSFER_WIDTH_32BIT: + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3)); + break; + default: + break; + } + + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_SPI_TDR, size); + dma_channel_start(dma_ch); + } + + return 0; + } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { + return -1; + } else { + if (spi_device->datasize == SPI_DATASIZE_8BIT) { + return SPI_Send_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (spi_device->datasize == SPI_DATASIZE_16BIT) { + return SPI_Send_16bits(spi_device->id, (uint16_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (spi_device->datasize == SPI_DATASIZE_24BIT) { + return SPI_Send_24bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else { + return SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } + } +} +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int spi_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + spi_device_t *spi_device = (spi_device_t *)dev; + + if (dev->oflag & DEVICE_OFLAG_DMA_RX) { + struct device *dma_ch = (struct device *)spi_device->rx_dma; + + if (!dma_ch) { + return -1; + } + + if (spi_device->id == 0) { + /* Set valid width for each fifo entry */ + uint32_t tmpVal; + uint32_t SPIx = SPI_BASE; + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + switch (DMA_DEV(dma_ch)->src_width) { + case DMA_TRANSFER_WIDTH_8BIT: + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0)); + break; + case DMA_TRANSFER_WIDTH_16BIT: + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1)); + break; + + case DMA_TRANSFER_WIDTH_32BIT: + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3)); + break; + default: + break; + dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI_RDR, (uint32_t)buffer, size); + dma_channel_start(dma_ch); + } + dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI_RDR, (uint32_t)buffer, size); + dma_channel_start(dma_ch); + } + + return 0; + } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { + return -1; + } else { + if (spi_device->datasize == SPI_DATASIZE_8BIT) { + return SPI_Recv_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (spi_device->datasize == SPI_DATASIZE_16BIT) { + return SPI_Recv_16bits(spi_device->id, (uint16_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (spi_device->datasize == SPI_DATASIZE_24BIT) { + return SPI_Recv_24bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else { + return SPI_Recv_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } + } +} +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int spi_register(enum spi_index_type index, const char *name) +{ + struct device *dev; + + if (SPI_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(spix_device[index].parent); + + dev->open = spi_open; + dev->close = spi_close; + dev->control = spi_control; + dev->write = spi_write; + dev->read = spi_read; + + dev->type = DEVICE_CLASS_SPI; + dev->handle = NULL; + + return device_register(dev, name); +} + +/** + * @brief + * + * @param dev + * @param buffer + * @param size + * @param type + * @return int + */ +int spi_transmit(struct device *dev, void *buffer, uint32_t size, uint8_t type) +{ + spi_device_t *spi_device = (spi_device_t *)dev; + + if (type == 0) { + return SPI_Send_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (type == 1) { + return SPI_Send_16bits(spi_device->id, (uint16_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (type == 2) { + return SPI_Send_24bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (type == 3) { + return SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } + + return -1; +} +/** + * @brief + * + * @param dev + * @param buffer + * @param size + * @param type + * @return int + */ +int spi_receive(struct device *dev, void *buffer, uint32_t size, uint8_t type) +{ + spi_device_t *spi_device = (spi_device_t *)dev; + + if (type == 0) { + return SPI_Recv_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (type == 1) { + return SPI_Recv_16bits(spi_device->id, (uint16_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (type == 2) { + return SPI_Recv_24bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } else if (type == 3) { + return SPI_Recv_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE); + } + + return -1; +} + +/** + * @brief + * + * @param dev + * @param send_buf + * @param recv_buf + * @param length + * @param type + * @return int + */ +int spi_transmit_receive(struct device *dev, const void *send_buf, void *recv_buf, uint32_t length, uint8_t type) +{ + spi_device_t *spi_device = (spi_device_t *)dev; + + if (type == 0) { + return SPI_SendRecv_8bits(spi_device->id, (uint8_t *)send_buf, (uint8_t *)recv_buf, length, SPI_TIMEOUT_DISABLE); + } else if (type == 1) { + return SPI_SendRecv_16bits(spi_device->id, (uint16_t *)send_buf, (uint16_t *)recv_buf, length, SPI_TIMEOUT_DISABLE); + } else if (type == 2) { + return SPI_SendRecv_24bits(spi_device->id, (uint32_t *)send_buf, (uint32_t *)recv_buf, length, SPI_TIMEOUT_DISABLE); + } else if (type == 3) { + return SPI_SendRecv_32bits(spi_device->id, (uint32_t *)send_buf, (uint32_t *)recv_buf, length, SPI_TIMEOUT_DISABLE); + } + + return -1; +} +/** + * @brief + * + * @param handle + */ +void spi_isr(spi_device_t *handle) +{ + uint32_t tmpVal; + uint32_t SPIx = SPI_BASE + handle->id * 0x100; + + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + if (!handle->parent.callback) { + return; + } + + /* Transfer end interrupt,shared by both master and slave mode */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR)); + handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_END); + } + + /* TX fifo ready interrupt(fifo count > fifo threshold) */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_TX_FIFO_REQ); + } + + /* RX fifo ready interrupt(fifo count > fifo threshold) */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_RX_FIFO_REQ); + } + + /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR)); + handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_SLAVE_TIMEOUT); + } + + /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR)); + handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_SLAVE_UNDERRUN); + } + + /* TX/RX fifo overflow/underflow interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_FIFO_ERROR); + } +} + +#ifdef BSP_USING_SPI0 +void SPI0_IRQ() +{ + spi_isr(&spix_device[SPI0_INDEX]); +} +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_timer.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..57db1d850aa2e5539d2cddf4516c050a8b87ee86 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_timer.c @@ -0,0 +1,389 @@ +/** + * @file hal_timer.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_timer.h" +#include "timer_config.h" +#include "bl702_glb.h" +#include "bl702_timer.h" +#include "hal_clock.h" + +#ifdef BSP_USING_TIMER0 +void TIMER0_IRQ(void); +#endif +#ifdef BSP_USING_TIMER1 +void TIMER1_IRQ(void); +#endif + +static timer_device_t timerx_device[TIMER_MAX_INDEX] = { +#ifdef BSP_USING_TIMER0 + TIMER0_CONFIG, +#endif +#ifdef BSP_USING_TIMER1 + TIMER1_CONFIG, +#endif +}; + +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int timer_open(struct device *dev, uint16_t oflag) +{ + timer_device_t *timer_device = (timer_device_t *)dev; + + uint32_t tmpval; + uint32_t compare_count1 = 0; + uint32_t compare_count2 = 0; + uint32_t compare_count3 = 0; + uint32_t reload_val = 0; + uint32_t clkval = 0; + uint32_t unit = 0; + + /* Disable all interrupt */ + TIMER_IntMask(timer_device->id, TIMER_INT_ALL, MASK); + /* Disable timer before config */ + TIMER_Disable(timer_device->id); + + /* Configure timer count mode: preload or free run */ + tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET); + tmpval &= (~(1 << (timer_device->id + 1))); + tmpval |= (timer_device->cnt_mode << (timer_device->id + 1)); + + BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval); + + /* Configure timer preload trigger source */ + BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_device->id, timer_device->trigger); + + if (timer_device->cnt_mode == TIMER_CNT_PRELOAD) { + BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_device->id, timer_device->reload); + reload_val = timer_device->reload; + } + + if (timer_device->id == TIMER_CH0) { + clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0); + } else { + clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1); + } + + if (clkval % 1000000 == 0) { + unit = 1000000; //1us + } else if (clkval % 100000 == 0) { + unit = 100000; //10us + } else if (clkval % 10000 == 0) { + unit = 10000; //100us + } else if (clkval % 1000 == 0) { + unit = 1000; //1ms + } else if (clkval % 100 == 0) { + unit = 100; //10ms + } else if (clkval % 10 == 0) { + unit = 10; //100ms + } else if (clkval % 1 == 0) { + unit = 1; //s + } else { + } + + compare_count1 = timer_device->timeout1 / (1000000 / unit) * (clkval / unit) + reload_val; + compare_count2 = timer_device->timeout2 / (1000000 / unit) * (clkval / unit) + reload_val; + compare_count3 = timer_device->timeout3 / (1000000 / unit) * (clkval / unit) + reload_val; + + /* Configure match compare values */ + if ((compare_count1 < 1) || (compare_count2 < 1) || (compare_count3 < 1)) { + return -1; + } + + TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_0, compare_count1 - 2); + TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_1, compare_count2 - 2); + TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_2, compare_count3 - 2); + + /* Clear interrupt status*/ + TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_0); + TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_1); + TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_2); + + if (oflag & DEVICE_OFLAG_STREAM_TX) { + /* Enable timer match interrupt */ + /* Note: if not enable match interrupt, TIMER_GetMatchStatus will not work + and status bit will not set */ + TIMER_IntMask(timer_device->id, TIMER_INT_COMP_0, UNMASK); + TIMER_IntMask(timer_device->id, TIMER_INT_COMP_1, UNMASK); + TIMER_IntMask(timer_device->id, TIMER_INT_COMP_2, UNMASK); + } + + if (oflag & DEVICE_OFLAG_INT_TX) { +#ifdef BSP_USING_TIMER0 + if (timer_device->id == TIMER_CH0) { + Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER0_IRQ); + } +#endif +#ifdef BSP_USING_TIMER1 + if (timer_device->id == TIMER_CH1) { + Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER1_IRQ); + } +#endif + } + /* Enable timer */ + TIMER_Enable(timer_device->id); + return 0; +} + +/** + * @brief + * + * @param dev + * @return int + */ +int timer_close(struct device *dev) +{ + timer_device_t *timer_device = (timer_device_t *)(dev); + TIMER_Disable(timer_device->id); + return 0; +} + +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int timer_control(struct device *dev, int cmd, void *args) +{ + timer_device_t *timer_device = (timer_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: { + uint32_t offset = __builtin_ctz((uint32_t)args); + + while (offset < 3) { + if ((uint32_t)args & (1 << offset)) { + TIMER_IntMask(timer_device->id, offset, UNMASK); + } + offset++; + } + + if (timer_device->id == TIMER_CH0) { + CPU_Interrupt_Pending_Clear(TIMER_CH0_IRQn); + CPU_Interrupt_Enable(TIMER_CH0_IRQn); + } else if (timer_device->id == TIMER_CH1) { + CPU_Interrupt_Pending_Clear(TIMER_CH1_IRQn); + CPU_Interrupt_Enable(TIMER_CH1_IRQn); + } + + break; + } + + case DEVICE_CTRL_CLR_INT /* constant-expression */: { + uint32_t offset = __builtin_ctz((uint32_t)args); + + while (offset < 3) { + if ((uint32_t)args & (1 << offset)) { + TIMER_IntMask(timer_device->id, offset, MASK); + } + offset++; + } + if (timer_device->id == TIMER_CH0) { + CPU_Interrupt_Disable(TIMER_CH0_IRQn); + } else if (timer_device->id == TIMER_CH1) { + CPU_Interrupt_Disable(TIMER_CH1_IRQn); + } + break; + } + + case DEVICE_CTRL_GET_INT /* constant-expression */: { + uint32_t offset = __builtin_ctz((uint32_t)args); + uint32_t intstatus = TIMER_GetMatchStatus(timer_device->id, offset); + /* Clear interrupt status*/ + TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_0); + TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_1); + TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_2); + return intstatus; + } + case DEVICE_CTRL_CONFIG /* constant-expression */: + /* code */ + break; + + case DEVICE_CTRL_RESUME /* constant-expression */: { + /* Enable timer */ + TIMER_Enable(timer_device->id); + break; + } + + case DEVICE_CTRL_SUSPEND /* constant-expression */: { + TIMER_Disable(timer_device->id); + break; + } + case DEVICE_CTRL_GET_CONFIG: + return TIMER_GetCounterValue(timer_device->id); + default: + break; + } + + return 0; +} + +int timer_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + timer_device_t *timer_device = (timer_device_t *)dev; + timer_timeout_cfg_t *timeout_cfg = (timer_timeout_cfg_t *)buffer; + uint32_t compare_count = 0; + uint32_t reload_val = 0; + uint32_t clkval = 0; + uint32_t unit = 0; + + if (size % sizeof(timer_timeout_cfg_t)) { + return -1; + } + /* Disable timer before config */ + TIMER_Disable(timer_device->id); + + if (timer_device->cnt_mode == TIMER_CNT_PRELOAD) { + reload_val = timer_device->reload; + } + + if (timer_device->id == TIMER_CH0) { + clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0); + } else { + clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1); + } + + if (clkval % 1000000 == 0) { + unit = 1000000; //1us + } else if (clkval % 100000 == 0) { + unit = 100000; //10us + } else if (clkval % 10000 == 0) { + unit = 10000; //100us + } else if (clkval % 1000 == 0) { + unit = 1000; //1ms + } else if (clkval % 100 == 0) { + unit = 100; //10ms + } else if (clkval % 10 == 0) { + unit = 10; //100ms + } else if (clkval % 1 == 0) { + unit = 1; //s + } else { + } + + for (uint32_t i = 0; i < size / sizeof(timer_timeout_cfg_t); i++) { + compare_count = timeout_cfg->timeout_val / (1000000 / unit) * (clkval / unit) + reload_val; + + if (compare_count < 1) { + return -1; + } + TIMER_SetCompValue(timer_device->id, timeout_cfg->timeout_id, compare_count - 2); + } + TIMER_Enable(timer_device->id); + return 0; +} +int timer_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + return 0; +} + +/** + * @brief + * + * @param index + * @param name + * @return int + */ +int timer_register(enum timer_index_type index, const char *name) +{ + struct device *dev; + + if (TIMER_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(timerx_device[index].parent); + + dev->open = timer_open; + dev->close = timer_close; + dev->control = timer_control; + dev->write = timer_write; + // dev->read = NULL; + + dev->type = DEVICE_CLASS_TIMER; + dev->handle = NULL; + + return device_register(dev, name); +} + +void timer_isr(timer_device_t *handle) +{ + uint32_t intId = 0; + uint32_t tmpVal = 0; + uint32_t tmpAddr = 0; + + if (!handle->parent.callback) { + return; + } + + intId = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * handle->id); + tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * handle->id; + tmpVal = BL_RD_WORD(tmpAddr); + + /* Comparator 0 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_0)) { + handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP0); + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_0)); + } + + /* Comparator 1 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_1)) { + handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP1); + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_1)); + } + + /* Comparator 2 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_2)) { + handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP2); + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_2)); + } +} + +#ifdef BSP_USING_TIMER0 +/** + * @brief + * + */ +void TIMER0_IRQ(void) +{ + timer_isr(&timerx_device[TIMER0_INDEX]); +} + +#endif + +#ifdef BSP_USING_TIMER1 +/** + * @brief + * + */ +void TIMER1_IRQ(void) +{ + timer_isr(&timerx_device[TIMER1_INDEX]); +} + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_uart.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..692f3001da30e26142603e7034509cede40a2827 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_uart.c @@ -0,0 +1,438 @@ +/** + * @file hal_uart.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_uart.h" +#include "hal_dma.h" +#include "hal_gpio.h" +#include "hal_clock.h" +#include "bl702_uart.h" +#include "bl702_glb.h" +#include "uart_config.h" + +#ifdef BSP_USING_UART0 +static void UART0_IRQ(void); +#endif +#ifdef BSP_USING_UART1 +static void UART1_IRQ(void); +#endif + +static uart_device_t uartx_device[UART_MAX_INDEX] = { +#ifdef BSP_USING_UART0 + UART0_CONFIG, +#endif +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +}; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int uart_open(struct device *dev, uint16_t oflag) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + UART_FifoCfg_Type fifoCfg = { 0 }; + UART_CFG_Type uart_cfg = { 0 }; + + /* disable all interrupt */ + UART_IntMask(uart_device->id, UART_INT_ALL, MASK); + /* disable uart before config */ + UART_Disable(uart_device->id, UART_TXRX); + + uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART); + uart_cfg.baudRate = uart_device->baudrate; + uart_cfg.dataBits = uart_device->databits; + uart_cfg.stopBits = uart_device->stopbits; + uart_cfg.parity = uart_device->parity; + uart_cfg.uartClk = uart_clk; + uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; + uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; + uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; + uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE; + uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE; + uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE; + uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT; + uart_cfg.rxDeglitch = ENABLE; + + /* uart init with default configuration */ + UART_Init(uart_device->id, &uart_cfg); + + /* Enable tx free run mode */ + UART_TxFreeRun(uart_device->id, ENABLE); + /*set de-glitch function cycle count value*/ + UART_SetDeglitchCount(uart_device->id, 2); + + /* Set rx time-out value */ + UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT); + + fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold; + fifoCfg.txFifoDmaEnable = DISABLE; + fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold; + fifoCfg.rxFifoDmaEnable = DISABLE; + + if (oflag & DEVICE_OFLAG_STREAM_TX) { + } + if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) { +#ifdef BSP_USING_UART0 + if (uart_device->id == UART0_ID) + Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ); +#endif +#ifdef BSP_USING_UART1 + if (uart_device->id == UART1_ID) + Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ); +#endif + } + if (oflag & DEVICE_OFLAG_DMA_TX) { + fifoCfg.txFifoDmaEnable = ENABLE; + } + if (oflag & DEVICE_OFLAG_DMA_RX) { + fifoCfg.rxFifoDmaEnable = ENABLE; + } + + UART_FifoConfig(uart_device->id, &fifoCfg); + /* enable uart */ + UART_Enable(uart_device->id, UART_TXRX); + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int uart_close(struct device *dev) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + + UART_Disable(uart_device->id, UART_TXRX); + if (uart_device->id == 0) { + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0); + } else if (uart_device->id == 1) { + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1); + } + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int uart_control(struct device *dev, int cmd, void *args) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: { + uint32_t offset = __builtin_ctz((uint32_t)args); + while ((0 <= offset) && (offset < 9)) { + if ((uint32_t)args & (1 << offset)) { + UART_IntMask(uart_device->id, offset, UNMASK); + } + offset++; + } + if (uart_device->id == UART0_ID) + CPU_Interrupt_Enable(UART0_IRQn); + else if (uart_device->id == UART1_ID) + CPU_Interrupt_Enable(UART1_IRQn); + + break; + } + case DEVICE_CTRL_CLR_INT /* constant-expression */: { + uint32_t offset = __builtin_ctz((uint32_t)args); + while ((0 <= offset) && (offset < 9)) { + if ((uint32_t)args & (1 << offset)) { + UART_IntMask(uart_device->id, offset, MASK); + } + offset++; + } + if (uart_device->id == UART0_ID) + CPU_Interrupt_Disable(UART0_IRQn); + else if (uart_device->id == UART1_ID) + CPU_Interrupt_Disable(UART1_IRQn); + + break; + } + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + case DEVICE_CTRL_RESUME /* constant-expression */: + UART_Enable(uart_device->id, UART_TXRX); + break; + case DEVICE_CTRL_SUSPEND /* constant-expression */: + UART_Disable(uart_device->id, UART_TXRX); + break; + case DEVICE_CTRL_CONFIG /* constant-expression */: { + uart_param_cfg_t *cfg = (uart_param_cfg_t *)args; + UART_CFG_Type uart_cfg; + + uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART); + + uart_cfg.uartClk = uart_clk; + uart_cfg.baudRate = cfg->baudrate; + uart_cfg.stopBits = cfg->stopbits; + uart_cfg.parity = cfg->parity; + uart_cfg.dataBits = cfg->databits; + uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; + uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; + uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; + uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE; + uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE; + uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE; + uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT; + uart_cfg.rxDeglitch = ENABLE; + UART_Init(uart_device->id, &uart_cfg); + /*set de-glitch function cycle count value*/ + UART_SetDeglitchCount(uart_device->id, 2); + break; + } + case DEVICE_CTRL_GET_CONFIG /* constant-expression */: + break; + case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */: + uart_device->tx_dma = (struct device *)args; + break; + case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */: + uart_device->rx_dma = (struct device *)args; + break; + case DEVICE_CTRL_TX_DMA_SUSPEND: { + uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0); + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN); + BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal); + dev->oflag &= ~DEVICE_OFLAG_DMA_TX; + break; + } + case DEVICE_CTRL_RX_DMA_SUSPEND: { + uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0); + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN); + BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal); + dev->oflag &= ~DEVICE_OFLAG_DMA_RX; + break; + } + case DEVICE_CTRL_TX_DMA_RESUME: { + uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN); + BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal); + dev->oflag |= DEVICE_OFLAG_DMA_TX; + break; + } + case DEVICE_CTRL_RX_DMA_RESUME: { + uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN); + BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal); + dev->oflag |= DEVICE_OFLAG_DMA_RX; + break; + } + case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */: + return UART_GetTxFifoCount(uart_device->id); + case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */: + return UART_GetRxFifoCount(uart_device->id); + default: + break; + } + + return 0; +} +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + if (dev->oflag & DEVICE_OFLAG_DMA_TX) { + struct device *dma_ch = (struct device *)uart_device->tx_dma; + if (!dma_ch) + return -1; + + if (uart_device->id == 0) { + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size); + dma_channel_start(dma_ch); + } else if (uart_device->id == 1) { + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size); + dma_channel_start(dma_ch); + } + return 0; + } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { + return -2; + } else + return UART_SendData(uart_device->id, (uint8_t *)buffer, size); +} +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + if (dev->oflag & DEVICE_OFLAG_DMA_RX) { + struct device *dma_ch = (struct device *)uart_device->rx_dma; + if (!dma_ch) + return -1; + + if (uart_device->id == 0) { + dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART0_RDR, (uint32_t)buffer, size); + dma_channel_start(dma_ch); + } else if (uart_device->id == 1) { + dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART1_RDR, (uint32_t)buffer, size); + dma_channel_start(dma_ch); + } + return 0; + } else if (dev->oflag & DEVICE_OFLAG_INT_RX) { + return -2; + } else { + return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size); + } +} +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int uart_register(enum uart_index_type index, const char *name) +{ + struct device *dev; + + if (UART_MAX_INDEX == 0) + return -DEVICE_EINVAL; + + dev = &(uartx_device[index].parent); + + dev->open = uart_open; + dev->close = uart_close; + dev->control = uart_control; + dev->write = uart_write; + dev->read = uart_read; + + dev->type = DEVICE_CLASS_UART; + dev->handle = NULL; + + return device_register(dev, name); +} +/** + * @brief + * + * @param handle + */ +void uart_isr(uart_device_t *handle) +{ + uint32_t tmpVal = 0; + uint32_t maskVal = 0; + uint32_t UARTx = (UART0_BASE + handle->id * 0x100); + + tmpVal = BL_RD_REG(UARTx, UART_INT_STS); + maskVal = BL_RD_REG(UARTx, UART_INT_MASK); + + if (!handle->parent.callback) + return; + + /* Length of uart tx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1); + handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END); + } + + /* Length of uart rx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2); + handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_END); + } + + /* Tx fifo ready interrupt,auto-cleared when data is pushed */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO); + } + + /* Rx fifo ready interrupt,auto-cleared when data is popped */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) { + uint8_t buffer[UART_FIFO_MAX_LEN]; + uint8_t len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold); + if (len) { + handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO); + } + } + + /* Rx time-out interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { + uint8_t buffer[UART_FIFO_MAX_LEN]; + uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN); + if (len) { + handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO); + } + + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10); + } + + /* Rx parity check error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20); + handle->parent.callback(&handle->parent, NULL, 0, UART_PCE_IT); + } + + /* Tx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, UART_TX_FER_IT); + } + + /* Rx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { + handle->parent.callback(&handle->parent, NULL, 0, UART_RX_FER_IT); + } +} + +#ifdef BSP_USING_UART0 +/** + * @brief + * + */ +void UART0_IRQ(void) +{ + uart_isr(&uartx_device[UART0_INDEX]); +} +#endif +#ifdef BSP_USING_UART1 +/** + * @brief + * + */ +void UART1_IRQ(void) +{ + uart_isr(&uartx_device[UART1_INDEX]); +} +#endif \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c new file mode 100644 index 0000000000000000000000000000000000000000..6610811b8ccb5e958e83162e3ceb38b18e7c1f14 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c @@ -0,0 +1,1078 @@ +/** + * @file hal_usb.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_usb.h" +#include "hal_dma.h" +#include "hal_mtimer.h" +#include "bl702_usb.h" +#include "bl702_glb.h" +#include "bl702_gpio.h" +#include "usb_config.h" + +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define USB_DC_LOG_WRN(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__) +#define USB_DC_LOG_DBG(a, ...) +#define USB_DC_LOG_ERR(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__) +#define USB_DC_LOG(a, ...) + +static usb_dc_device_t usb_fs_device; +static void USB_FS_IRQ(void); + +static dma_lli_ctrl_t usb_lli_list = { + .src_addr = 0, + .dst_addr = 0, + .nextlli = 0, + .cfg.bits.fix_cnt = 0, + .cfg.bits.dst_min_mode = 0, + .cfg.bits.dst_add_mode = 0, + .cfg.bits.SI = 0, + .cfg.bits.DI = 0, + .cfg.bits.SWidth = DMA_TRANSFER_WIDTH_8BIT, + .cfg.bits.DWidth = DMA_TRANSFER_WIDTH_8BIT, + .cfg.bits.SBSize = 0, + .cfg.bits.DBSize = 0, + .cfg.bits.I = 0, + .cfg.bits.TransferSize = 0 +}; + +static void usb_set_power_up(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USB); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); +} + +static void usb_set_power_off(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USB); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); +} + +static uint8_t usb_ep_is_enabled(uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + /* Check if ep enabled */ + if ((USB_EP_DIR_IS_OUT(ep)) && + usb_fs_device.out_ep[ep_idx].ep_ena) { + return 1; + } else if ((USB_EP_DIR_IS_IN(ep)) && + usb_fs_device.in_ep[ep_idx].ep_ena) { + return 1; + } + + return 0; +} + +static void usb_xcvr_config(BL_Fun_Type NewState) +{ + uint32_t tmpVal = 0; + + if (NewState != DISABLE) { +#if defined(USE_EXTERNAL_TRANSCEIVER) + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 0); //use external tranceiver + BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal); +#elif defined(USE_INTERNAL_TRANSCEIVER) +#if 1 + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SUS, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SPD, 1); //0 for 1.1 ls,1 for 1.1 fs + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_DATA_CONVERT, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_OEB_SEL, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_PMOS, 3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_NMOS, 3); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_RISE, 2); //1 for 1.1 ls + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_FALL, 2); //1 for 1.1 ls + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_RISE, 2); //1 for 1.1 ls + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_FALL, 2); //1 for 1.1 ls + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_RES_PULLUP_TUNE, 5); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_P, 2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_M, 2); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal); + + ///* force BD=1, not use */ + //tmpVal=BL_RD_REG(GLB_BASE,GLB_USB_XCVR); + //tmpVal=BL_SET_REG_BIT(tmpVal,GLB_PU_USB_LDO); + //BL_WR_REG(GLB_BASE,GLB_USB_XCVR,tmpVal); + + /* BD_voltage_thresdhold=2.8V */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 7); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal); + +#else + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SUS, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SPD, 0); //0 for 1.1 ls,1 for 1.1 fs + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_DATA_CONVERT, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_OEB_SEL, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_PMOS, 3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_NMOS, 3); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_RISE, 1); //4 for 1.1 fs + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_FALL, 1); //3 for 1.1 fs + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_RISE, 1); //4 for 1.1 fs + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_FALL, 1); //3 for 1.1 fs + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_RES_PULLUP_TUNE, 5); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_P, 2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_M, 2); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal); +#endif + + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 1); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); +#endif + } else { +#ifdef USE_INTERNAL_TRANSCEIVER + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 0); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); + + ///* force BD=1, not use */ + //tmpVal=BL_RD_REG(GLB_BASE,GLB_USB_XCVR); + //tmpVal=BL_SET_REG_BIT(tmpVal,GLB_PU_USB_LDO); + //BL_WR_REG(GLB_BASE,GLB_USB_XCVR,tmpVal); + + /* BD_voltage_thresdhold=2.8V */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 7); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal); + +#else + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1); //use internal tranceiver + BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); +#endif + } +} + +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int usb_open(struct device *dev, uint16_t oflag) +{ + USB_Config_Type usbCfg = { 0 }; + + usb_set_power_off(); + mtimer_delay_ms(10); + usb_set_power_up(); + + usb_xcvr_config(DISABLE); + usb_xcvr_config(ENABLE); + + CPU_Interrupt_Disable(USB_IRQn); + + usbCfg.DeviceAddress = 0; + usbCfg.EnumInEn = ENABLE; + usbCfg.EnumOutEn = ENABLE; + usbCfg.RomBaseDescriptorUsed = 0; + usbCfg.SoftwareCtrl = 1; + usbCfg.EnumMaxPacketSize = USB_CTRL_EP_MPS; + + /* Init Device */ + USB_Set_Config(DISABLE, &usbCfg); + + usb_fs_device.out_ep[0].ep_ena = 1U; + usb_fs_device.in_ep[0].ep_ena = 1U; + usb_fs_device.out_ep[0].ep_cfg.ep_mps = USB_CTRL_EP_MPS; + usb_fs_device.out_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; + usb_fs_device.in_ep[0].ep_cfg.ep_mps = USB_CTRL_EP_MPS; + usb_fs_device.in_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; + + /* USB interrupt enable config */ + USB_IntEn(USB_INT_ALL, DISABLE); //all + USB_IntEn(USB_INT_RESET, ENABLE); //1 + USB_IntEn(USB_INT_EP0_SETUP_DONE, ENABLE); //5 + USB_IntEn(USB_INT_EP0_IN_DONE, ENABLE); //7 + USB_IntEn(USB_INT_EP0_OUT_DONE, ENABLE); //9 + USB_IntEn(USB_INT_RESET_END, ENABLE); //27 + + /* USB interrupt mask config */ + USB_IntMask(USB_INT_ALL, MASK); //all + USB_IntMask(USB_INT_RESET, UNMASK); //1 + USB_IntMask(USB_INT_EP0_SETUP_DONE, UNMASK); //5 + USB_IntMask(USB_INT_EP0_IN_DONE, UNMASK); //7 + USB_IntMask(USB_INT_EP0_OUT_DONE, UNMASK); //9 + USB_IntMask(USB_INT_RESET_END, UNMASK); //27 + +#ifdef ENABLE_LPM_INT + USB_IntEn(USB_INT_LPM_PACKET, ENABLE); + USB_IntEn(USB_INT_LPM_WAKEUP, ENABLE); + USB_IntMask(USB_INT_LPM_PACKET, UNMASK); + USB_IntMask(USB_INT_LPM_WAKEUP, UNMASK); + + USB_LPM_Enable(); + USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_ACK); + +#endif + +#ifdef ENABLE_SOF3MS_INT + /* disable sof3ms until reset_end */ + USB_IntEn(USB_INT_LOST_SOF_3_TIMES, DISABLE); + USB_IntMask(USB_INT_LOST_SOF_3_TIMES, MASK); + + /* recommended enable sof3ms after reset_end */ + USB_IntEn(USB_INT_LOST_SOF_3_TIMES, ENABLE); + USB_IntMask(USB_INT_LOST_SOF_3_TIMES, UNMASK); +#endif + +#ifdef ENABLE_ERROR_INT + USB_IntEn(USB_INT_ERROR, ENABLE); + USB_IntMask(USB_INT_ERROR, UNMASK); +#endif + /*Clear pending interrupts*/ + USB_Clr_IntStatus(USB_INT_ALL); + + Interrupt_Handler_Register(USB_IRQn, USB_FS_IRQ); + CPU_Interrupt_Enable(USB_IRQn); + USB_Enable(); + + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int usb_close(struct device *dev) +{ + /* disable all interrupts and force USB reset */ + CPU_Interrupt_Disable(USB_IRQn); + USB_IntMask(USB_INT_LPM_WAKEUP, MASK); + USB_IntMask(USB_INT_LPM_PACKET, MASK); + + USB_Disable(); + + /* clear interrupt status register */ + USB_Clr_IntStatus(USB_INT_ALL); + + usb_set_power_off(); + + usb_xcvr_config(DISABLE); + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int usb_control(struct device *dev, int cmd, void *args) +{ + struct usb_dc_device *usb_device = (struct usb_dc_device *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT /* constant-expression */: { + uint32_t offset = __builtin_ctz((uint32_t)args); + + while (offset < 24) { + if ((uint32_t)args & (1 << offset)) { + USB_IntEn(offset, ENABLE); + USB_IntMask(offset, UNMASK); //11 + //USB_DC_LOG("offset:%d\r\n",offset); + } + + offset++; + } + break; + } + case DEVICE_CTRL_CLR_INT /* constant-expression */: + break; + + case DEVICE_CTRL_USB_DC_SET_ACK /* constant-expression */: + USB_Set_EPx_Status(USB_EP_GET_IDX(((uint32_t)args) & 0x7f), USB_EP_STATUS_ACK); + return 0; + case DEVICE_CTRL_USB_DC_ENUM_ON: { + uint32_t tmpVal; + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 1); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); + return 0; + } + case DEVICE_CTRL_USB_DC_ENUM_OFF: { + uint32_t tmpVal; + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); + return 0; + } + case DEVICE_CTRL_USB_DC_GET_EP_TX_FIFO_CNT: + return USB_Get_EPx_TX_FIFO_CNT(((uint32_t)args) & 0x7f); + + case DEVICE_CTRL_USB_DC_GET_EP_RX_FIFO_CNT: + return USB_Get_EPx_RX_FIFO_CNT(((uint32_t)args) & 0x7f); + case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */: + usb_device->tx_dma = (struct device *)args; + break; + + case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */: + usb_device->rx_dma = (struct device *)args; + break; + + case DEVICE_CTRL_USB_DC_SET_TX_DMA /* constant-expression */: + USB_Set_EPx_TX_DMA_Interface_Config(((uint32_t)args) & 0x7f, ENABLE); + break; + + case DEVICE_CTRL_USB_DC_SET_RX_DMA /* constant-expression */: + USB_Set_EPx_RX_DMA_Interface_Config(((uint32_t)args) & 0x7f, ENABLE); + break; + + default: + break; + } + + return 0; +} + +int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + struct usb_dc_device *usb_device = (struct usb_dc_device *)dev; + uint8_t ep_idx = USB_EP_GET_IDX(pos); + + if (usb_device->in_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC) { + uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x10; + + dma_channel_stop(usb_device->tx_dma); + usb_lli_list.src_addr = (uint32_t)buffer; + usb_lli_list.dst_addr = usb_ep_addr; + usb_lli_list.cfg.bits.TransferSize = size; + usb_lli_list.cfg.bits.DI = 0; + usb_lli_list.cfg.bits.SI = 1; + usb_lli_list.cfg.bits.SBSize = DMA_BURST_16BYTE; + usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE; + device_control(usb_device->tx_dma, DMA_CHANNEL_UPDATE, (void *)((uint32_t)&usb_lli_list)); + dma_channel_start(usb_device->tx_dma); + } else { + } + + return -1; +} + +int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + struct usb_dc_device *usb_device = (struct usb_dc_device *)dev; + uint8_t ep_idx = USB_EP_GET_IDX(pos); + + if (usb_device->out_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC) { + uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x1c; + + dma_channel_stop(usb_device->tx_dma); + usb_lli_list.src_addr = usb_ep_addr; + usb_lli_list.dst_addr = (uint32_t)buffer; + usb_lli_list.cfg.bits.TransferSize = size; + usb_lli_list.cfg.bits.DI = 1; + usb_lli_list.cfg.bits.SI = 0; + usb_lli_list.cfg.bits.SBSize = DMA_BURST_1BYTE; + usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE; + device_control(usb_device->rx_dma, DMA_CHANNEL_UPDATE, (void *)((uint32_t)&usb_lli_list)); + dma_channel_start(usb_device->rx_dma); + } else { + } + + return -1; +} + +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int usb_dc_register(enum usb_index_type index, const char *name) +{ + struct device *dev; + + if (USB_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(usb_fs_device.parent); + + dev->open = usb_open; + dev->close = usb_close; + dev->control = usb_control; + dev->write = usb_write; + dev->read = usb_read; + + dev->type = DEVICE_CLASS_USB; + dev->handle = NULL; + + return device_register(dev, name); +} + +/** + * @brief Set USB device address + * + * @param[in] addr Device address + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_set_dev_address(const uint8_t addr) +{ + USB_Set_Device_Addr(addr); + return 0; +} + +/** + * @brief configure and enable endpoint + * This function sets endpoint configuration according to one specified in USB + * endpoint descriptor and then enables it for data transfers. + * + * @param dev + * @param ep_cfg ep_cfg Endpoint + * @return int + */ +int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg) +{ + uint8_t ep; + EP_Config_Type epCfg; + + if (!ep_cfg) { + return -1; + } + + ep = ep_cfg->ep_addr; + + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + USB_DC_LOG_DBG("%s ep %x, mps %d, type %d\r\n", __func__, ep, ep_cfg->ep_mps, ep_cfg->ep_type); + + if (USB_EP_DIR_IS_OUT(ep)) { + epCfg.dir = EP_OUT; + epCfg.EPMaxPacketSize = ep_cfg->ep_mps; + usb_fs_device.out_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; + usb_fs_device.out_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; + } else { + epCfg.dir = EP_IN; + epCfg.EPMaxPacketSize = ep_cfg->ep_mps; + usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; + usb_fs_device.in_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; + } + + if (ep_idx) { + switch (ep_cfg->ep_type) { + case USBD_EP_TYPE_CTRL: + epCfg.type = USB_DC_EP_TYPE_CTRL; + break; + + case USBD_EP_TYPE_ISOC: + epCfg.type = USB_DC_EP_TYPE_ISOC; + break; + + case USBD_EP_TYPE_BULK: + epCfg.type = USB_DC_EP_TYPE_BULK; + break; + + case USBD_EP_TYPE_INTR: + epCfg.type = USB_DC_EP_TYPE_INTR; + break; + + default: + return -1; + } + + USB_Set_EPx_Config(ep_idx, &epCfg); + + if (USB_EP_DIR_IS_OUT(ep)) { + /* Clear NAK and enable ep */ + USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK); + usb_fs_device.out_ep[ep_idx].ep_ena = 1U; + } else { + //USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK); + USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_NACK); + usb_fs_device.in_ep[ep_idx].ep_ena = 1U; + } + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + usb_fs_device.out_ep[ep_idx].ep_ena = 1U; + } else { + usb_fs_device.in_ep[ep_idx].ep_ena = 1U; + } + } + + return 0; +} + +int usb_dc_ep_close(const uint8_t ep) +{ + return 0; +} + +/** + * @brief Set stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_set_stall(const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_Set_EPx_Status(ep_idx, USB_EP_STATUS_STALL); + usb_fs_device.out_ep[ep_idx].is_stalled = 1U; + } else { + USB_Set_EPx_Status(ep_idx, USB_EP_STATUS_STALL); + usb_fs_device.in_ep[ep_idx].is_stalled = 1U; + } + return 0; +} +/** + * @brief Clear stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_clear_stall(const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_Set_EPx_Status(ep_idx, USB_EP_STATUS_NSTALL); + usb_fs_device.out_ep[ep_idx].is_stalled = 0; + } else { + USB_Set_EPx_Status(ep_idx, USB_EP_STATUS_NSTALL); + usb_fs_device.in_ep[ep_idx].is_stalled = 0; + } + return 0; +} + +/** + * @brief Check if the selected endpoint is stalled + * + * @param dev usb device + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[out] stalled Endpoint stall status + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!stalled) { + return -1; + } + + *stalled = 0U; + + if (USB_EP_DIR_IS_OUT(ep)) { + if (USB_Get_EPx_Status(ep_idx) & USB_EP_STATUS_STALL && usb_fs_device.out_ep[ep_idx].is_stalled) { + *stalled = 1U; + } + } else { + if (USB_Get_EPx_Status(ep_idx) & USB_EP_STATUS_STALL && usb_fs_device.in_ep[ep_idx].is_stalled) { + *stalled = 1U; + } + } + + return 0; +} + +/** + * @brief Write data to the specified endpoint + * + * This function is called to write data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is transmitted + * out. + * + * @param dev + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of the data requested to write. This may + * be zero for a zero length status packet. + * @param[out] ret_bytes Bytes scheduled for transmission. This value + * may be NULL if the application expects all + * bytes to be written + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) +{ + uint8_t ep_idx; + uint32_t timeout = 0x00FFFFFF; + uint32_t ep_tx_fifo_addr; + + ep_idx = USB_EP_GET_IDX(ep); + + /* Check if IN ep */ + if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { + return -USB_DC_EP_DIR_ERR; + } + + /* Check if ep enabled */ + if (!usb_ep_is_enabled(ep)) { + return -USB_DC_EP_EN_ERR; + } + /* Check if ep free */ + while (!USB_Is_EPx_RDY_Free(ep_idx)) { + timeout--; + + if (!timeout) { + USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep); + return -USB_DC_EP_TIMEOUT_ERR; + } + } + + if (!data_len) { + /* Zero length packet */ + /* Clear NAK and enable ep */ + USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK); + return USB_DC_OK; + } + + if (!data && data_len) { + USB_DC_LOG_ERR("data is null\r\n"); + return -USB_DC_ADDR_ERR; + } + + if (data_len > usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps) { + /* Check if transfer len is too big */ + data_len = usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps; + } + + /* Wait for FIFO space available */ + do { + uint32_t avail_space = USB_Get_EPx_TX_FIFO_CNT(ep_idx); + + if (avail_space >= usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps) { + break; + } + + //USB_DC_LOG_ERR("EP%d have remain data\r\n", ep_idx); + } while (1); + + /* + * Write data to FIFO, make sure that we are protected against + * other USB register accesses. According to "DesignWare Cores + * USB 1.1/2.0 Device Subsystem-AHB/VCI Databook": "During FIFO + * access, the application must not access the UDC/Subsystem + * registers or vendor registers (for ULPI mode). After starting + * to access a FIFO, the application must complete the transaction + * before accessing the register." + */ + ep_tx_fifo_addr = USB_BASE + USB_EP0_TX_FIFO_WDATA_OFFSET + ep_idx * 0x10; + + if ((data_len == 1) && (ep_idx == 0)) { + USB_Set_EPx_Xfer_Size(EP_ID0, 1); + } else if (ep_idx == 0) { + USB_Set_EPx_Xfer_Size(EP_ID0, 64); + } + + memcopy_to_fifo((void *)ep_tx_fifo_addr, (uint8_t *)data, data_len); + /* Clear NAK and enable ep */ + USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK); + + USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len); + + if (ret_bytes) { + *ret_bytes = data_len; + } + + return USB_DC_OK; +} + +/** + * @brief Read data from the specified endpoint + * + * This is similar to usb_dc_ep_read, the difference being that, it doesn't + * clear the endpoint NAKs so that the consumer is not bogged down by further + * upcalls till he is done with the processing of the data. The caller should + * reactivate ep by invoking usb_dc_ep_read_continue() do so. + * + * @param dev + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data buffer to write to + * @param[in] max_data_len Max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t read_count; + uint32_t ep_rx_fifo_addr; + uint32_t timeout = 0x00FFFFFF; + + /* Check if OUT ep */ + if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { + USB_DC_LOG_ERR("Wrong endpoint direction\r\n"); + return -USB_DC_EP_DIR_ERR; + } + + /* Check if ep enabled */ + if (!usb_ep_is_enabled(ep)) { + USB_DC_LOG_ERR("Not enabled endpoint\r\n"); + return -USB_DC_EP_EN_ERR; + } + /* Check if ep free */ + while (!USB_Is_EPx_RDY_Free(ep_idx) && (usb_fs_device.out_ep[ep_idx].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) { + timeout--; + + if (!timeout) { + USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep); + return -USB_DC_EP_TIMEOUT_ERR; + } + } + + /* Allow to read 0 bytes */ + if (!data_len) { + /* Clear NAK and enable ep */ + USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK); + return USB_DC_OK; + } + + if (!data && data_len) { + USB_DC_LOG_ERR("data is null\r\n"); + return -USB_DC_ADDR_ERR; + } + + read_count = USB_Get_EPx_RX_FIFO_CNT(ep_idx); + read_count = MIN(read_count, data_len); + + /* Data in the FIFOs is always stored per 8-bit word*/ + ep_rx_fifo_addr = (USB_BASE + USB_EP0_RX_FIFO_RDATA_OFFSET + ep_idx * 0x10); + fifocopy_to_mem((void *)ep_rx_fifo_addr, data, read_count); + USB_DC_LOG_DBG("Read EP%d, req %d, read %d bytes\r\n", ep, data_len, read_count); + + if (read_bytes) { + *read_bytes = read_count; + } + + return USB_DC_OK; +} +/** + * @brief + * + * @param dev + * @param rb + * @param ep + * @return int + */ +int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep) +{ + uint8_t ep_idx; + uint8_t recv_len; + static bool overflow_flag = false; + + /* Check if OUT ep */ + if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { + USB_DC_LOG_ERR("Wrong endpoint direction\r\n"); + return -USB_DC_EP_DIR_ERR; + } + + /* Check if ep enabled */ + if (!usb_ep_is_enabled(ep)) { + return -USB_DC_EP_EN_ERR; + } + + ep_idx = USB_EP_GET_IDX(ep); + + recv_len = USB_Get_EPx_RX_FIFO_CNT(ep_idx); + + /*if rx fifo count equal 0,it means last is send nack and ringbuffer is smaller than 64, + * so,if ringbuffer is larger than 64,set ack to recv next data. + */ + if (overflow_flag && (Ring_Buffer_Get_Empty_Length(rb) > 64) && (!recv_len)) { + overflow_flag = false; + USB_Set_EPx_Rdy(ep_idx); + return 0; + } else { + uint32_t addr = USB_BASE + 0x11C + (ep_idx - 1) * 0x10; + Ring_Buffer_Write_Callback(rb, recv_len, fifocopy_to_mem, (void *)addr); + + if (Ring_Buffer_Get_Empty_Length(rb) < 64) { + overflow_flag = true; + return -USB_DC_RB_SIZE_SMALL_ERR; + } + + USB_Set_EPx_Rdy(ep_idx); + return 0; + } +} +/** + * @brief + * + * @param dev + * @param rb + * @param ep + * @return int + */ +int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep) +{ + uint8_t ep_idx; + static bool zlp_flag = false; + static uint32_t send_total_len = 0; + + ep_idx = USB_EP_GET_IDX(ep); + + /* Check if IN ep */ + if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { + return -USB_DC_EP_DIR_ERR; + } + + /* Check if ep enabled */ + if (!usb_ep_is_enabled(ep)) { + return -USB_DC_EP_EN_ERR; + } + + uint32_t addr = USB_BASE + 0x118 + (ep_idx - 1) * 0x10; + + if (zlp_flag == false) { + if ((USB_Get_EPx_TX_FIFO_CNT(ep_idx) == USB_FS_MAX_PACKET_SIZE) && Ring_Buffer_Get_Length(rb)) { + uint32_t actual_len = Ring_Buffer_Read_Callback(rb, USB_FS_MAX_PACKET_SIZE, memcopy_to_fifo, (void *)addr); + send_total_len += actual_len; + + if (!Ring_Buffer_Get_Length(rb) && (!(send_total_len % 64))) { + zlp_flag = true; + } + + USB_Set_EPx_Rdy(ep_idx); + return 0; + } else { + return -USB_DC_RB_SIZE_SMALL_ERR; + } + } else { + zlp_flag = false; + send_total_len = 0; + USB_Set_EPx_Rdy(ep_idx); + return -USB_DC_ZLP_ERR; + } +} + +/** + * @brief This function handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ + +/** + * @brief + * + * @param device + */ +void usb_dc_isr(usb_dc_device_t *device) +{ + USB_EP_ID epnum = EP_ID0; + + /* EP1_DONE -> EP2_DONE -> ...... -> EP7_DONE*/ + for (USB_INT_Type epint = USB_INT_EP1_DONE; epint <= USB_INT_EP7_DONE; epint += 2) { + if (USB_Get_IntStatus(epint)) { + epnum = (epint - USB_INT_EP0_OUT_CMD) >> 1; + if (!USB_Is_EPx_RDY_Free(epnum) && (device->out_ep[epnum].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) { + USB_DC_LOG_ERR("ep%d out busy\r\n", epnum); + return; + } + device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_OUT(epnum)), 0, USB_DC_EVENT_EP_OUT_NOTIFY); + USB_Clr_IntStatus(epint); + return; + } + } + + /* EP1_CMD -> EP2_CMD -> ...... -> EP7_CMD*/ + for (USB_INT_Type epint = USB_INT_EP1_CMD; epint <= USB_INT_EP7_CMD; epint += 2) { + if (USB_Get_IntStatus(epint)) { + epnum = (epint - USB_INT_EP0_OUT_CMD) >> 1; + if (!USB_Is_EPx_RDY_Free(epnum)) { + USB_DC_LOG_DBG("ep%d in busy\r\n", epnum); + return; + } + device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_IN(epnum)), 0, USB_DC_EVENT_EP_IN_NOTIFY); + USB_Clr_IntStatus(epint); + return; + } + } + + /* reset */ + if (USB_Get_IntStatus(USB_INT_SOF)) { + USB_DC_LOG("sof\r\n"); + device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SOF); + USB_Clr_IntStatus(USB_INT_SOF); + return; + } + + /* reset */ + if (USB_Get_IntStatus(USB_INT_RESET)) { + USB_DC_LOG("reset\r\n"); + device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_RESET); + USB_Clr_IntStatus(USB_INT_RESET); + return; + } + + /* vbus toggle */ + if (USB_Get_IntStatus(USB_INT_VBUS_TGL)) { + USB_DC_LOG("vbus toggle\r\n"); + /*************************************/ + /*************************************/ + USB_Clr_IntStatus(USB_INT_VBUS_TGL); + return; + } + + /* EP0 setup done */ + if (USB_Get_IntStatus(USB_INT_EP0_SETUP_DONE)) { + USB_DC_LOG("S\r\n"); + if (!USB_Is_EPx_RDY_Free(0)) { + USB_DC_LOG_DBG("ep0 setup busy\r\n"); + return; + } + device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SETUP_NOTIFY); + USB_Clr_IntStatus(USB_INT_EP0_SETUP_DONE); + return; + } + + /* EP0 in done */ + if (USB_Get_IntStatus(USB_INT_EP0_IN_DONE)) { + USB_DC_LOG("I\r\n"); + if (!USB_Is_EPx_RDY_Free(0)) { + USB_DC_LOG_DBG("ep0 in busy\r\n"); + return; + } + device->parent.callback(&device->parent, (void *)0x80, 0, USB_DC_EVENT_EP0_IN_NOTIFY); + USB_Clr_IntStatus(USB_INT_EP0_IN_DONE); + return; + } + + /* EP0 out done */ + if (USB_Get_IntStatus(USB_INT_EP0_OUT_DONE)) { + USB_DC_LOG("O\r\n"); + if (!USB_Is_EPx_RDY_Free(0)) { + USB_DC_LOG_DBG("ep0 out busy\r\n"); + return; + } + device->parent.callback(&device->parent, (void *)0x00, 0, USB_DC_EVENT_EP0_OUT_NOTIFY); + /*************************************/ + USB_Clr_IntStatus(USB_INT_EP0_OUT_DONE); + return; + } + + /* reset end */ + if (USB_Get_IntStatus(USB_INT_RESET_END)) { + USB_DC_LOG("re\r\n"); + /*************************************/ + USB_Set_EPx_Rdy(EP_ID0); + /*************************************/ + USB_Clr_IntStatus(USB_INT_RESET_END); + return; + } + + /* LPM wakeup */ + /* usb wakeup interrupt, need update by reg_excel_files */ + if (USB_Get_IntStatus(USB_INT_LPM_WAKEUP)) { + /*************************************/ + /*set wInterrupt_Mask global variable*/ + //HAL_PCD_ResumeCallback(hpcd); + /*************************************/ + USB_Clr_IntStatus(USB_INT_LPM_WAKEUP); + return; + } + + /* LPM packet */ + /* usb suspend interrupt, need update by reg_excel_files */ + if (USB_Get_IntStatus(USB_INT_LPM_PACKET)) { + /*************************************/ + /* Force low-power mode in the macrocell */ + if (USB_Get_IntStatus(USB_INT_LPM_WAKEUP) == 0) { + //HAL_PCD_SuspendCallback(hpcd); + } + + /*************************************/ + USB_Clr_IntStatus(USB_INT_LPM_PACKET); + return; + } + + /* lost 3 SOF */ + if (USB_Get_IntStatus(USB_INT_LOST_SOF_3_TIMES)) { + USB_DC_LOG_ERR("Lost 3 SOFs\r\n"); + /*************************************/ + /*************************************/ + USB_Clr_IntStatus(USB_INT_LOST_SOF_3_TIMES); + return; + } + + /* error */ + if (USB_Get_IntStatus(USB_INT_ERROR)) { + USB_DC_LOG("USB bus error 0x%08x; EP2 fifo status 0x%08x\r\n", *(volatile uint32_t *)(0x4000D81C), *(volatile uint32_t *)(0x4000D920)); + /*************************************/ + /*************************************/ + device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_ERROR); + USB_Clr_IntStatus(USB_INT_ERROR); + return; + } +} +/** + * @brief + * + */ +void USB_FS_IRQ(void) +{ + usb_dc_isr(&usb_fs_device); +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_wdt.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..6d7783cfef9991f26aa9c2ab72a090335dd42e38 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_wdt.c @@ -0,0 +1,180 @@ +/** + * @file hal_wdt.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_wdt.h" +#include "bl702_timer.h" + +#ifdef BSP_USING_WDT +void WDT_IRQ(void); +#endif + +static wdt_device_t wdtx_device[WDT_MAX_INDEX] = { +#ifdef BSP_USING_WDT + WDT_CONFIG, +#endif +}; + +int wdt_open(struct device *dev, uint16_t oflag) +{ + // uint32_t tmpval; + + /* watchdog timer disable*/ + // tmpval = BL_RD_REG(TIMER_BASE, TIMER_WMER); + // BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpval, TIMER_WE)); + // // MSG("wdt timeout %d \r\n", wdt_device->wdt_timeout); + // /* Set watchdog timer match register value */ + // BL_WR_REG(TIMER_BASE, TIMER_WMR, (uint16_t)wdt_device->wdt_timeout); + + if (oflag & DEVICE_OFLAG_INT_TX) { +#ifdef BSP_USING_WDT + wdt_device_t *wdt_device = (wdt_device_t *)dev; + // WDT_IntMask(WDT_INT, UNMASK); + if (wdt_device->id == 0) { + Interrupt_Handler_Register(TIMER_WDT_IRQn, WDT_IRQ); + } +#endif + } else { + WDT_IntMask(WDT_INT, MASK); + } + + // /* enable watchdog timer */ + WDT_Enable(); + return 0; +} + +int wdt_close(struct device *dev) +{ + // wdt_device_t *wdt_device = (wdt_device_t *)(dev); + WDT_Disable(); + return 0; +} + +int wdt_control(struct device *dev, int cmd, void *args) +{ + // wdt_device_t *wdt_device = (wdt_device_t *)dev; + + switch (cmd) { + case DEVICE_CTRL_SET_INT: { + WDT_IntMask(WDT_INT, UNMASK); + CPU_Interrupt_Pending_Clear(TIMER_WDT_IRQn); + CPU_Interrupt_Enable(TIMER_WDT_IRQn); + break; + } + case DEVICE_CTRL_CLR_INT: { + WDT_IntMask(WDT_INT, MASK); + CPU_Interrupt_Disable(TIMER_WDT_IRQn); + break; + } + case DEVICE_CTRL_CONFIG: { + break; + } + case DEVICE_CTRL_RESUME: { + WDT_Enable(); + break; + } + case DEVICE_CTRL_SUSPEND: { + WDT_Disable(); + break; + } + case DEVICE_CTRL_GET_WDT_COUNTER: { + return WDT_GetCounterValue(); + break; + } + case DEVICE_CTRL_RST_WDT_COUNTER: { + WDT_ResetCounterValue(); + break; + } + case DEVICE_CTRL_GET_RST_STATUS: { + return WDT_GetResetStatus(); + break; + } + case DEVICE_CTRL_CLR_RST_STATUS: { + WDT_ClearResetStatus(); + break; + } + default: + break; + } + + return 0; +} + +int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + // wdt_device_t *wdt_device = (wdt_device_t *)dev; + uint16_t wdt_timeout = (uint16_t)(uint32_t)buffer; + + WDT_Disable(); + MSG("wdt timeout %d \r\n", wdt_timeout); + WDT_SetCompValue(wdt_timeout); + WDT_Enable(); + + return 0; +} + +int wdt_register(enum wdt_index_type index, const char *name) +{ + struct device *dev; + + if (WDT_MAX_INDEX == 0) { + return -DEVICE_EINVAL; + } + + dev = &(wdtx_device[index].parent); + + dev->open = wdt_open; + dev->close = wdt_close; + dev->control = wdt_control; + dev->write = wdt_write; + // dev->read = NULL; + + dev->status = DEVICE_UNREGISTER; + dev->type = DEVICE_CLASS_TIMER; + dev->handle = NULL; + + return device_register(dev, name); +} + +void wdt_isr(wdt_device_t *handle) +{ + uint32_t tmpval; + + if (!handle->parent.callback) { + return; + } + + tmpval = BL_RD_REG(TIMER_BASE, TIMER_WICR); + BL_WR_REG(TIMER_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpval, TIMER_WICLR)); + + handle->parent.callback(&handle->parent, NULL, 0, WDT_EVENT); +} + +#ifdef BSP_USING_WDT +/** + * @brief + * + */ +void WDT_IRQ(void) +{ + wdt_isr(&wdtx_device[WDT_INDEX]); +} +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/aon_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/aon_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..bb581832775c96364c6449f5d210b7390fe5bbbd --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/aon_reg.h @@ -0,0 +1,1579 @@ +/** + ****************************************************************************** + * @file aon_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __AON_REG_H__ +#define __AON_REG_H__ + +#include "bl702.h" + +/* 0x800 : aon */ +#define AON_OFFSET (0x800) +#define AON_RESV AON_RESV +#define AON_RESV_POS (0U) +#define AON_RESV_LEN (8U) +#define AON_RESV_MSK (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS) +#define AON_RESV_UMSK (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)) +#define AON_PU_AON_DC_TBUF AON_PU_AON_DC_TBUF +#define AON_PU_AON_DC_TBUF_POS (12U) +#define AON_PU_AON_DC_TBUF_LEN (1U) +#define AON_PU_AON_DC_TBUF_MSK (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS) +#define AON_PU_AON_DC_TBUF_UMSK (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)) +#define AON_LDO11_RT_PULLDOWN AON_LDO11_RT_PULLDOWN +#define AON_LDO11_RT_PULLDOWN_POS (20U) +#define AON_LDO11_RT_PULLDOWN_LEN (1U) +#define AON_LDO11_RT_PULLDOWN_MSK (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS) +#define AON_LDO11_RT_PULLDOWN_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)) +#define AON_LDO11_RT_PULLDOWN_SEL AON_LDO11_RT_PULLDOWN_SEL +#define AON_LDO11_RT_PULLDOWN_SEL_POS (21U) +#define AON_LDO11_RT_PULLDOWN_SEL_LEN (1U) +#define AON_LDO11_RT_PULLDOWN_SEL_MSK (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS) +#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)) +#define AON_SW_PU_LDO11_RT AON_SW_PU_LDO11_RT +#define AON_SW_PU_LDO11_RT_POS (22U) +#define AON_SW_PU_LDO11_RT_LEN (1U) +#define AON_SW_PU_LDO11_RT_MSK (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS) +#define AON_SW_PU_LDO11_RT_UMSK (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)) + +/* 0x804 : aon_common */ +#define AON_COMMON_OFFSET (0x804) +#define AON_TMUX_AON AON_TMUX_AON +#define AON_TMUX_AON_POS (0U) +#define AON_TMUX_AON_LEN (3U) +#define AON_TMUX_AON_MSK (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS) +#define AON_TMUX_AON_UMSK (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)) +#define AON_TEN_AON AON_TEN_AON +#define AON_TEN_AON_POS (4U) +#define AON_TEN_AON_LEN (1U) +#define AON_TEN_AON_MSK (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS) +#define AON_TEN_AON_UMSK (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)) +#define AON_DTEN_XTAL32K AON_DTEN_XTAL32K +#define AON_DTEN_XTAL32K_POS (5U) +#define AON_DTEN_XTAL32K_LEN (1U) +#define AON_DTEN_XTAL32K_MSK (((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS) +#define AON_DTEN_XTAL32K_UMSK (~(((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS)) +#define AON_TEN_XTAL32K AON_TEN_XTAL32K +#define AON_TEN_XTAL32K_POS (6U) +#define AON_TEN_XTAL32K_LEN (1U) +#define AON_TEN_XTAL32K_MSK (((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS) +#define AON_TEN_XTAL32K_UMSK (~(((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS)) +#define AON_TEN_VDDCORE_AON AON_TEN_VDDCORE_AON +#define AON_TEN_VDDCORE_AON_POS (8U) +#define AON_TEN_VDDCORE_AON_LEN (1U) +#define AON_TEN_VDDCORE_AON_MSK (((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS) +#define AON_TEN_VDDCORE_AON_UMSK (~(((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS)) +#define AON_TEN_LDO11SOC_AON AON_TEN_LDO11SOC_AON +#define AON_TEN_LDO11SOC_AON_POS (9U) +#define AON_TEN_LDO11SOC_AON_LEN (1U) +#define AON_TEN_LDO11SOC_AON_MSK (((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS) +#define AON_TEN_LDO11SOC_AON_UMSK (~(((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS)) +#define AON_TEN_DCDC18_0_AON AON_TEN_DCDC18_0_AON +#define AON_TEN_DCDC18_0_AON_POS (10U) +#define AON_TEN_DCDC18_0_AON_LEN (1U) +#define AON_TEN_DCDC18_0_AON_MSK (((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS) +#define AON_TEN_DCDC18_0_AON_UMSK (~(((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS)) +#define AON_TEN_DCDC18_1_AON AON_TEN_DCDC18_1_AON +#define AON_TEN_DCDC18_1_AON_POS (11U) +#define AON_TEN_DCDC18_1_AON_LEN (1U) +#define AON_TEN_DCDC18_1_AON_MSK (((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS) +#define AON_TEN_DCDC18_1_AON_UMSK (~(((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS)) +#define AON_TEN_BG_SYS_AON AON_TEN_BG_SYS_AON +#define AON_TEN_BG_SYS_AON_POS (12U) +#define AON_TEN_BG_SYS_AON_LEN (1U) +#define AON_TEN_BG_SYS_AON_MSK (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS) +#define AON_TEN_BG_SYS_AON_UMSK (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)) +#define AON_TEN_LDO15RF_AON AON_TEN_LDO15RF_AON +#define AON_TEN_LDO15RF_AON_POS (16U) +#define AON_TEN_LDO15RF_AON_LEN (1U) +#define AON_TEN_LDO15RF_AON_MSK (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS) +#define AON_TEN_LDO15RF_AON_UMSK (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)) +#define AON_TEN_XTAL_AON AON_TEN_XTAL_AON +#define AON_TEN_XTAL_AON_POS (17U) +#define AON_TEN_XTAL_AON_LEN (1U) +#define AON_TEN_XTAL_AON_MSK (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS) +#define AON_TEN_XTAL_AON_UMSK (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)) +#define AON_DTEN_XTAL_AON AON_DTEN_XTAL_AON +#define AON_DTEN_XTAL_AON_POS (18U) +#define AON_DTEN_XTAL_AON_LEN (1U) +#define AON_DTEN_XTAL_AON_MSK (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS) +#define AON_DTEN_XTAL_AON_UMSK (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)) +#define AON_TEN_MBG_AON AON_TEN_MBG_AON +#define AON_TEN_MBG_AON_POS (19U) +#define AON_TEN_MBG_AON_LEN (1U) +#define AON_TEN_MBG_AON_MSK (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS) +#define AON_TEN_MBG_AON_UMSK (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)) +#define AON_TEN_CIP_MISC_AON AON_TEN_CIP_MISC_AON +#define AON_TEN_CIP_MISC_AON_POS (20U) +#define AON_TEN_CIP_MISC_AON_LEN (1U) +#define AON_TEN_CIP_MISC_AON_MSK (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS) +#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)) + +/* 0x808 : aon_misc */ +#define AON_MISC_OFFSET (0x808) +#define AON_SW_SOC_EN_AON AON_SW_SOC_EN_AON +#define AON_SW_SOC_EN_AON_POS (0U) +#define AON_SW_SOC_EN_AON_LEN (1U) +#define AON_SW_SOC_EN_AON_MSK (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS) +#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)) +#define AON_SW_BZ_EN_AON AON_SW_BZ_EN_AON +#define AON_SW_BZ_EN_AON_POS (1U) +#define AON_SW_BZ_EN_AON_LEN (1U) +#define AON_SW_BZ_EN_AON_MSK (((1U << AON_SW_BZ_EN_AON_LEN) - 1) << AON_SW_BZ_EN_AON_POS) +#define AON_SW_BZ_EN_AON_UMSK (~(((1U << AON_SW_BZ_EN_AON_LEN) - 1) << AON_SW_BZ_EN_AON_POS)) + +/* 0x810 : bg_sys_top */ +#define AON_BG_SYS_TOP_OFFSET (0x810) +#define AON_PMIP_RESV AON_PMIP_RESV +#define AON_PMIP_RESV_POS (0U) +#define AON_PMIP_RESV_LEN (8U) +#define AON_PMIP_RESV_MSK (((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS) +#define AON_PMIP_RESV_UMSK (~(((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS)) +#define AON_PU_BG_SYS_AON AON_PU_BG_SYS_AON +#define AON_PU_BG_SYS_AON_POS (8U) +#define AON_PU_BG_SYS_AON_LEN (1U) +#define AON_PU_BG_SYS_AON_MSK (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS) +#define AON_PU_BG_SYS_AON_UMSK (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)) +#define AON_BG_SYS_START_CTRL_AON AON_BG_SYS_START_CTRL_AON +#define AON_BG_SYS_START_CTRL_AON_POS (12U) +#define AON_BG_SYS_START_CTRL_AON_LEN (1U) +#define AON_BG_SYS_START_CTRL_AON_MSK (((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS) +#define AON_BG_SYS_START_CTRL_AON_UMSK (~(((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS)) + +/* 0x814 : dcdc18_top_0 */ +#define AON_DCDC18_TOP_0_OFFSET (0x814) +#define AON_DCDC18_VOUT_SEL_AON AON_DCDC18_VOUT_SEL_AON +#define AON_DCDC18_VOUT_SEL_AON_POS (1U) +#define AON_DCDC18_VOUT_SEL_AON_LEN (5U) +#define AON_DCDC18_VOUT_SEL_AON_MSK (((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS) +#define AON_DCDC18_VOUT_SEL_AON_UMSK (~(((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS)) +#define AON_DCDC18_VPFM_AON AON_DCDC18_VPFM_AON +#define AON_DCDC18_VPFM_AON_POS (8U) +#define AON_DCDC18_VPFM_AON_LEN (4U) +#define AON_DCDC18_VPFM_AON_MSK (((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS) +#define AON_DCDC18_VPFM_AON_UMSK (~(((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS)) +#define AON_DCDC18_OSC_2M_MODE_AON AON_DCDC18_OSC_2M_MODE_AON +#define AON_DCDC18_OSC_2M_MODE_AON_POS (12U) +#define AON_DCDC18_OSC_2M_MODE_AON_LEN (1U) +#define AON_DCDC18_OSC_2M_MODE_AON_MSK (((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS) +#define AON_DCDC18_OSC_2M_MODE_AON_UMSK (~(((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS)) +#define AON_DCDC18_OSC_FREQ_TRIM_AON AON_DCDC18_OSC_FREQ_TRIM_AON +#define AON_DCDC18_OSC_FREQ_TRIM_AON_POS (16U) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_LEN (4U) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_MSK (((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_UMSK (~(((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS)) +#define AON_DCDC18_SLOPE_CURR_SEL_AON AON_DCDC18_SLOPE_CURR_SEL_AON +#define AON_DCDC18_SLOPE_CURR_SEL_AON_POS (20U) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_LEN (5U) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_MSK (((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS)) +#define AON_DCDC18_STOP_OSC_AON AON_DCDC18_STOP_OSC_AON +#define AON_DCDC18_STOP_OSC_AON_POS (25U) +#define AON_DCDC18_STOP_OSC_AON_LEN (1U) +#define AON_DCDC18_STOP_OSC_AON_MSK (((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS) +#define AON_DCDC18_STOP_OSC_AON_UMSK (~(((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS)) +#define AON_DCDC18_SLOW_OSC_AON AON_DCDC18_SLOW_OSC_AON +#define AON_DCDC18_SLOW_OSC_AON_POS (26U) +#define AON_DCDC18_SLOW_OSC_AON_LEN (1U) +#define AON_DCDC18_SLOW_OSC_AON_MSK (((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS) +#define AON_DCDC18_SLOW_OSC_AON_UMSK (~(((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS)) +#define AON_DCDC18_OSC_INHIBIT_T2_AON AON_DCDC18_OSC_INHIBIT_T2_AON +#define AON_DCDC18_OSC_INHIBIT_T2_AON_POS (27U) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_LEN (1U) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_MSK (((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS)) +#define AON_DCDC18_SSTART_TIME_AON AON_DCDC18_SSTART_TIME_AON +#define AON_DCDC18_SSTART_TIME_AON_POS (28U) +#define AON_DCDC18_SSTART_TIME_AON_LEN (2U) +#define AON_DCDC18_SSTART_TIME_AON_MSK (((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS) +#define AON_DCDC18_SSTART_TIME_AON_UMSK (~(((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS)) +#define AON_DCDC18_RDY_AON AON_DCDC18_RDY_AON +#define AON_DCDC18_RDY_AON_POS (31U) +#define AON_DCDC18_RDY_AON_LEN (1U) +#define AON_DCDC18_RDY_AON_MSK (((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS) +#define AON_DCDC18_RDY_AON_UMSK (~(((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS)) + +/* 0x818 : dcdc18_top_1 */ +#define AON_DCDC18_TOP_1_OFFSET (0x818) +#define AON_DCDC18_FORCE_CS_ZVS_AON AON_DCDC18_FORCE_CS_ZVS_AON +#define AON_DCDC18_FORCE_CS_ZVS_AON_POS (0U) +#define AON_DCDC18_FORCE_CS_ZVS_AON_LEN (1U) +#define AON_DCDC18_FORCE_CS_ZVS_AON_MSK (((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS) +#define AON_DCDC18_FORCE_CS_ZVS_AON_UMSK (~(((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS)) +#define AON_DCDC18_CS_DELAY_AON AON_DCDC18_CS_DELAY_AON +#define AON_DCDC18_CS_DELAY_AON_POS (1U) +#define AON_DCDC18_CS_DELAY_AON_LEN (3U) +#define AON_DCDC18_CS_DELAY_AON_MSK (((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS) +#define AON_DCDC18_CS_DELAY_AON_UMSK (~(((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS)) +#define AON_DCDC18_ZVS_TD_OPT_AON AON_DCDC18_ZVS_TD_OPT_AON +#define AON_DCDC18_ZVS_TD_OPT_AON_POS (4U) +#define AON_DCDC18_ZVS_TD_OPT_AON_LEN (3U) +#define AON_DCDC18_ZVS_TD_OPT_AON_MSK (((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS) +#define AON_DCDC18_ZVS_TD_OPT_AON_UMSK (~(((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS)) +#define AON_DCDC18_NONOVERLAP_TD_AON AON_DCDC18_NONOVERLAP_TD_AON +#define AON_DCDC18_NONOVERLAP_TD_AON_POS (8U) +#define AON_DCDC18_NONOVERLAP_TD_AON_LEN (5U) +#define AON_DCDC18_NONOVERLAP_TD_AON_MSK (((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS) +#define AON_DCDC18_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS)) +#define AON_DCDC18_RC_SEL_AON AON_DCDC18_RC_SEL_AON +#define AON_DCDC18_RC_SEL_AON_POS (16U) +#define AON_DCDC18_RC_SEL_AON_LEN (4U) +#define AON_DCDC18_RC_SEL_AON_MSK (((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS) +#define AON_DCDC18_RC_SEL_AON_UMSK (~(((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS)) +#define AON_DCDC18_CHF_SEL_AON AON_DCDC18_CHF_SEL_AON +#define AON_DCDC18_CHF_SEL_AON_POS (20U) +#define AON_DCDC18_CHF_SEL_AON_LEN (4U) +#define AON_DCDC18_CHF_SEL_AON_MSK (((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS) +#define AON_DCDC18_CHF_SEL_AON_UMSK (~(((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS)) +#define AON_DCDC18_CFB_SEL_AON AON_DCDC18_CFB_SEL_AON +#define AON_DCDC18_CFB_SEL_AON_POS (24U) +#define AON_DCDC18_CFB_SEL_AON_LEN (4U) +#define AON_DCDC18_CFB_SEL_AON_MSK (((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS) +#define AON_DCDC18_CFB_SEL_AON_UMSK (~(((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS)) +#define AON_DCDC18_EN_ANTIRING_AON AON_DCDC18_EN_ANTIRING_AON +#define AON_DCDC18_EN_ANTIRING_AON_POS (28U) +#define AON_DCDC18_EN_ANTIRING_AON_LEN (1U) +#define AON_DCDC18_EN_ANTIRING_AON_MSK (((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS) +#define AON_DCDC18_EN_ANTIRING_AON_UMSK (~(((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS)) +#define AON_DCDC18_PULLDOWN_AON AON_DCDC18_PULLDOWN_AON +#define AON_DCDC18_PULLDOWN_AON_POS (29U) +#define AON_DCDC18_PULLDOWN_AON_LEN (1U) +#define AON_DCDC18_PULLDOWN_AON_MSK (((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS) +#define AON_DCDC18_PULLDOWN_AON_UMSK (~(((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS)) + +/* 0x81C : ldo11soc_and_dctest */ +#define AON_LDO11SOC_AND_DCTEST_OFFSET (0x81C) +#define AON_PU_LDO11SOC_AON AON_PU_LDO11SOC_AON +#define AON_PU_LDO11SOC_AON_POS (0U) +#define AON_PU_LDO11SOC_AON_LEN (1U) +#define AON_PU_LDO11SOC_AON_MSK (((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS) +#define AON_PU_LDO11SOC_AON_UMSK (~(((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS)) +#define AON_LDO11SOC_SSTART_SEL_AON AON_LDO11SOC_SSTART_SEL_AON +#define AON_LDO11SOC_SSTART_SEL_AON_POS (4U) +#define AON_LDO11SOC_SSTART_SEL_AON_LEN (1U) +#define AON_LDO11SOC_SSTART_SEL_AON_MSK (((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS) +#define AON_LDO11SOC_SSTART_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS)) +#define AON_LDO11SOC_SSTART_DELAY_AON AON_LDO11SOC_SSTART_DELAY_AON +#define AON_LDO11SOC_SSTART_DELAY_AON_POS (8U) +#define AON_LDO11SOC_SSTART_DELAY_AON_LEN (2U) +#define AON_LDO11SOC_SSTART_DELAY_AON_MSK (((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS) +#define AON_LDO11SOC_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS)) +#define AON_LDO11SOC_PULLDOWN_AON AON_LDO11SOC_PULLDOWN_AON +#define AON_LDO11SOC_PULLDOWN_AON_POS (10U) +#define AON_LDO11SOC_PULLDOWN_AON_LEN (1U) +#define AON_LDO11SOC_PULLDOWN_AON_MSK (((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS) +#define AON_LDO11SOC_PULLDOWN_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS)) +#define AON_LDO11SOC_PULLDOWN_SEL_AON AON_LDO11SOC_PULLDOWN_SEL_AON +#define AON_LDO11SOC_PULLDOWN_SEL_AON_POS (11U) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_LEN (1U) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_MSK (((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS)) +#define AON_LDO11SOC_VTH_SEL_AON AON_LDO11SOC_VTH_SEL_AON +#define AON_LDO11SOC_VTH_SEL_AON_POS (12U) +#define AON_LDO11SOC_VTH_SEL_AON_LEN (2U) +#define AON_LDO11SOC_VTH_SEL_AON_MSK (((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS) +#define AON_LDO11SOC_VTH_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS)) +#define AON_LDO11SOC_CC_AON AON_LDO11SOC_CC_AON +#define AON_LDO11SOC_CC_AON_POS (24U) +#define AON_LDO11SOC_CC_AON_LEN (2U) +#define AON_LDO11SOC_CC_AON_MSK (((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS) +#define AON_LDO11SOC_CC_AON_UMSK (~(((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS)) +#define AON_LDO11SOC_RDY_AON AON_LDO11SOC_RDY_AON +#define AON_LDO11SOC_RDY_AON_POS (28U) +#define AON_LDO11SOC_RDY_AON_LEN (1U) +#define AON_LDO11SOC_RDY_AON_MSK (((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS) +#define AON_LDO11SOC_RDY_AON_UMSK (~(((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS)) +#define AON_LDO11SOC_POWER_GOOD_AON AON_LDO11SOC_POWER_GOOD_AON +#define AON_LDO11SOC_POWER_GOOD_AON_POS (29U) +#define AON_LDO11SOC_POWER_GOOD_AON_LEN (1U) +#define AON_LDO11SOC_POWER_GOOD_AON_MSK (((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS) +#define AON_LDO11SOC_POWER_GOOD_AON_UMSK (~(((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS)) +#define AON_PU_VDDCORE_MISC_AON AON_PU_VDDCORE_MISC_AON +#define AON_PU_VDDCORE_MISC_AON_POS (30U) +#define AON_PU_VDDCORE_MISC_AON_LEN (1U) +#define AON_PU_VDDCORE_MISC_AON_MSK (((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS) +#define AON_PU_VDDCORE_MISC_AON_UMSK (~(((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS)) +#define AON_PMIP_DC_TP_OUT_EN_AON AON_PMIP_DC_TP_OUT_EN_AON +#define AON_PMIP_DC_TP_OUT_EN_AON_POS (31U) +#define AON_PMIP_DC_TP_OUT_EN_AON_LEN (1U) +#define AON_PMIP_DC_TP_OUT_EN_AON_MSK (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS) +#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)) + +/* 0x820 : psw_irrcv */ +#define AON_PSW_IRRCV_OFFSET (0x820) +#define AON_PU_IR_PSW_AON AON_PU_IR_PSW_AON +#define AON_PU_IR_PSW_AON_POS (0U) +#define AON_PU_IR_PSW_AON_LEN (1U) +#define AON_PU_IR_PSW_AON_MSK (((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS) +#define AON_PU_IR_PSW_AON_UMSK (~(((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS)) + +/* 0x880 : rf_top_aon */ +#define AON_RF_TOP_AON_OFFSET (0x880) +#define AON_PU_MBG_AON AON_PU_MBG_AON +#define AON_PU_MBG_AON_POS (0U) +#define AON_PU_MBG_AON_LEN (1U) +#define AON_PU_MBG_AON_MSK (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS) +#define AON_PU_MBG_AON_UMSK (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)) +#define AON_PU_LDO15RF_AON AON_PU_LDO15RF_AON +#define AON_PU_LDO15RF_AON_POS (1U) +#define AON_PU_LDO15RF_AON_LEN (1U) +#define AON_PU_LDO15RF_AON_MSK (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS) +#define AON_PU_LDO15RF_AON_UMSK (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)) +#define AON_PU_SFREG_AON AON_PU_SFREG_AON +#define AON_PU_SFREG_AON_POS (2U) +#define AON_PU_SFREG_AON_LEN (1U) +#define AON_PU_SFREG_AON_MSK (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS) +#define AON_PU_SFREG_AON_UMSK (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)) +#define AON_PU_XTAL_BUF_AON AON_PU_XTAL_BUF_AON +#define AON_PU_XTAL_BUF_AON_POS (4U) +#define AON_PU_XTAL_BUF_AON_LEN (1U) +#define AON_PU_XTAL_BUF_AON_MSK (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS) +#define AON_PU_XTAL_BUF_AON_UMSK (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)) +#define AON_PU_XTAL_AON AON_PU_XTAL_AON +#define AON_PU_XTAL_AON_POS (5U) +#define AON_PU_XTAL_AON_LEN (1U) +#define AON_PU_XTAL_AON_MSK (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS) +#define AON_PU_XTAL_AON_UMSK (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)) +#define AON_LDO15RF_SSTART_SEL_AON AON_LDO15RF_SSTART_SEL_AON +#define AON_LDO15RF_SSTART_SEL_AON_POS (8U) +#define AON_LDO15RF_SSTART_SEL_AON_LEN (1U) +#define AON_LDO15RF_SSTART_SEL_AON_MSK (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS) +#define AON_LDO15RF_SSTART_SEL_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)) +#define AON_LDO15RF_SSTART_DELAY_AON AON_LDO15RF_SSTART_DELAY_AON +#define AON_LDO15RF_SSTART_DELAY_AON_POS (9U) +#define AON_LDO15RF_SSTART_DELAY_AON_LEN (2U) +#define AON_LDO15RF_SSTART_DELAY_AON_MSK (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS) +#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)) +#define AON_LDO15RF_PULLDOWN_AON AON_LDO15RF_PULLDOWN_AON +#define AON_LDO15RF_PULLDOWN_AON_POS (12U) +#define AON_LDO15RF_PULLDOWN_AON_LEN (1U) +#define AON_LDO15RF_PULLDOWN_AON_MSK (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS) +#define AON_LDO15RF_PULLDOWN_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)) +#define AON_LDO15RF_PULLDOWN_SEL_AON AON_LDO15RF_PULLDOWN_SEL_AON +#define AON_LDO15RF_PULLDOWN_SEL_AON_POS (13U) +#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN (1U) +#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS) +#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)) +#define AON_LDO15RF_VOUT_SEL_AON AON_LDO15RF_VOUT_SEL_AON +#define AON_LDO15RF_VOUT_SEL_AON_POS (16U) +#define AON_LDO15RF_VOUT_SEL_AON_LEN (3U) +#define AON_LDO15RF_VOUT_SEL_AON_MSK (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS) +#define AON_LDO15RF_VOUT_SEL_AON_UMSK (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)) +#define AON_LDO15RF_CC_AON AON_LDO15RF_CC_AON +#define AON_LDO15RF_CC_AON_POS (24U) +#define AON_LDO15RF_CC_AON_LEN (2U) +#define AON_LDO15RF_CC_AON_MSK (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS) +#define AON_LDO15RF_CC_AON_UMSK (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)) +#define AON_LDO15RF_BYPASS_AON AON_LDO15RF_BYPASS_AON +#define AON_LDO15RF_BYPASS_AON_POS (28U) +#define AON_LDO15RF_BYPASS_AON_LEN (1U) +#define AON_LDO15RF_BYPASS_AON_MSK (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS) +#define AON_LDO15RF_BYPASS_AON_UMSK (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)) + +/* 0x884 : xtal_cfg */ +#define AON_XTAL_CFG_OFFSET (0x884) +#define AON_XTAL_BK_AON AON_XTAL_BK_AON +#define AON_XTAL_BK_AON_POS (0U) +#define AON_XTAL_BK_AON_LEN (2U) +#define AON_XTAL_BK_AON_MSK (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS) +#define AON_XTAL_BK_AON_UMSK (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)) +#define AON_XTAL_CAPCODE_EXTRA_AON AON_XTAL_CAPCODE_EXTRA_AON +#define AON_XTAL_CAPCODE_EXTRA_AON_POS (2U) +#define AON_XTAL_CAPCODE_EXTRA_AON_LEN (1U) +#define AON_XTAL_CAPCODE_EXTRA_AON_MSK (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS) +#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)) +#define AON_XTAL_EXT_SEL_AON AON_XTAL_EXT_SEL_AON +#define AON_XTAL_EXT_SEL_AON_POS (3U) +#define AON_XTAL_EXT_SEL_AON_LEN (1U) +#define AON_XTAL_EXT_SEL_AON_MSK (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS) +#define AON_XTAL_EXT_SEL_AON_UMSK (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)) +#define AON_XTAL_BUF_EN_AON AON_XTAL_BUF_EN_AON +#define AON_XTAL_BUF_EN_AON_POS (4U) +#define AON_XTAL_BUF_EN_AON_LEN (4U) +#define AON_XTAL_BUF_EN_AON_MSK (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS) +#define AON_XTAL_BUF_EN_AON_UMSK (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)) +#define AON_XTAL_BUF_HP_AON AON_XTAL_BUF_HP_AON +#define AON_XTAL_BUF_HP_AON_POS (8U) +#define AON_XTAL_BUF_HP_AON_LEN (4U) +#define AON_XTAL_BUF_HP_AON_MSK (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS) +#define AON_XTAL_BUF_HP_AON_UMSK (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)) +#define AON_XTAL_FAST_STARTUP_AON AON_XTAL_FAST_STARTUP_AON +#define AON_XTAL_FAST_STARTUP_AON_POS (12U) +#define AON_XTAL_FAST_STARTUP_AON_LEN (1U) +#define AON_XTAL_FAST_STARTUP_AON_MSK (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS) +#define AON_XTAL_FAST_STARTUP_AON_UMSK (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)) +#define AON_XTAL_SLEEP_AON AON_XTAL_SLEEP_AON +#define AON_XTAL_SLEEP_AON_POS (13U) +#define AON_XTAL_SLEEP_AON_LEN (1U) +#define AON_XTAL_SLEEP_AON_MSK (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS) +#define AON_XTAL_SLEEP_AON_UMSK (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)) +#define AON_XTAL_AMP_CTRL_AON AON_XTAL_AMP_CTRL_AON +#define AON_XTAL_AMP_CTRL_AON_POS (14U) +#define AON_XTAL_AMP_CTRL_AON_LEN (2U) +#define AON_XTAL_AMP_CTRL_AON_MSK (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS) +#define AON_XTAL_AMP_CTRL_AON_UMSK (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)) +#define AON_XTAL_CAPCODE_OUT_AON AON_XTAL_CAPCODE_OUT_AON +#define AON_XTAL_CAPCODE_OUT_AON_POS (16U) +#define AON_XTAL_CAPCODE_OUT_AON_LEN (6U) +#define AON_XTAL_CAPCODE_OUT_AON_MSK (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS) +#define AON_XTAL_CAPCODE_OUT_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)) +#define AON_XTAL_CAPCODE_IN_AON AON_XTAL_CAPCODE_IN_AON +#define AON_XTAL_CAPCODE_IN_AON_POS (22U) +#define AON_XTAL_CAPCODE_IN_AON_LEN (6U) +#define AON_XTAL_CAPCODE_IN_AON_MSK (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS) +#define AON_XTAL_CAPCODE_IN_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)) +#define AON_XTAL_GM_BOOST_AON AON_XTAL_GM_BOOST_AON +#define AON_XTAL_GM_BOOST_AON_POS (28U) +#define AON_XTAL_GM_BOOST_AON_LEN (2U) +#define AON_XTAL_GM_BOOST_AON_MSK (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS) +#define AON_XTAL_GM_BOOST_AON_UMSK (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)) +#define AON_XTAL_RDY_SEL_AON AON_XTAL_RDY_SEL_AON +#define AON_XTAL_RDY_SEL_AON_POS (30U) +#define AON_XTAL_RDY_SEL_AON_LEN (2U) +#define AON_XTAL_RDY_SEL_AON_MSK (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS) +#define AON_XTAL_RDY_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)) + +/* 0x888 : tsen */ +#define AON_TSEN_OFFSET (0x888) +#define AON_TSEN_REFCODE_CORNER AON_TSEN_REFCODE_CORNER +#define AON_TSEN_REFCODE_CORNER_POS (0U) +#define AON_TSEN_REFCODE_CORNER_LEN (12U) +#define AON_TSEN_REFCODE_CORNER_MSK (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS) +#define AON_TSEN_REFCODE_CORNER_UMSK (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)) +#define AON_TSEN_REFCODE_RFCAL AON_TSEN_REFCODE_RFCAL +#define AON_TSEN_REFCODE_RFCAL_POS (16U) +#define AON_TSEN_REFCODE_RFCAL_LEN (12U) +#define AON_TSEN_REFCODE_RFCAL_MSK (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS) +#define AON_TSEN_REFCODE_RFCAL_UMSK (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)) +#define AON_XTAL_RDY AON_XTAL_RDY +#define AON_XTAL_RDY_POS (28U) +#define AON_XTAL_RDY_LEN (1U) +#define AON_XTAL_RDY_MSK (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS) +#define AON_XTAL_RDY_UMSK (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)) +#define AON_XTAL_INN_CFG_EN_AON AON_XTAL_INN_CFG_EN_AON +#define AON_XTAL_INN_CFG_EN_AON_POS (29U) +#define AON_XTAL_INN_CFG_EN_AON_LEN (1U) +#define AON_XTAL_INN_CFG_EN_AON_MSK (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS) +#define AON_XTAL_INN_CFG_EN_AON_UMSK (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)) +#define AON_XTAL_RDY_INT_SEL_AON AON_XTAL_RDY_INT_SEL_AON +#define AON_XTAL_RDY_INT_SEL_AON_POS (30U) +#define AON_XTAL_RDY_INT_SEL_AON_LEN (2U) +#define AON_XTAL_RDY_INT_SEL_AON_MSK (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS) +#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)) + +/* 0x900 : acomp0_ctrl */ +#define AON_ACOMP0_CTRL_OFFSET (0x900) +#define AON_ACOMP0_EN AON_ACOMP0_EN +#define AON_ACOMP0_EN_POS (0U) +#define AON_ACOMP0_EN_LEN (1U) +#define AON_ACOMP0_EN_MSK (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS) +#define AON_ACOMP0_EN_UMSK (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)) +#define AON_ACOMP0_HYST_SELN AON_ACOMP0_HYST_SELN +#define AON_ACOMP0_HYST_SELN_POS (4U) +#define AON_ACOMP0_HYST_SELN_LEN (3U) +#define AON_ACOMP0_HYST_SELN_MSK (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS) +#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)) +#define AON_ACOMP0_HYST_SELP AON_ACOMP0_HYST_SELP +#define AON_ACOMP0_HYST_SELP_POS (7U) +#define AON_ACOMP0_HYST_SELP_LEN (3U) +#define AON_ACOMP0_HYST_SELP_MSK (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS) +#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)) +#define AON_ACOMP0_BIAS_PROG AON_ACOMP0_BIAS_PROG +#define AON_ACOMP0_BIAS_PROG_POS (10U) +#define AON_ACOMP0_BIAS_PROG_LEN (2U) +#define AON_ACOMP0_BIAS_PROG_MSK (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS) +#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)) +#define AON_ACOMP0_LEVEL_SEL AON_ACOMP0_LEVEL_SEL +#define AON_ACOMP0_LEVEL_SEL_POS (12U) +#define AON_ACOMP0_LEVEL_SEL_LEN (6U) +#define AON_ACOMP0_LEVEL_SEL_MSK (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS) +#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)) +#define AON_ACOMP0_NEG_SEL AON_ACOMP0_NEG_SEL +#define AON_ACOMP0_NEG_SEL_POS (18U) +#define AON_ACOMP0_NEG_SEL_LEN (4U) +#define AON_ACOMP0_NEG_SEL_MSK (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS) +#define AON_ACOMP0_NEG_SEL_UMSK (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)) +#define AON_ACOMP0_POS_SEL AON_ACOMP0_POS_SEL +#define AON_ACOMP0_POS_SEL_POS (22U) +#define AON_ACOMP0_POS_SEL_LEN (4U) +#define AON_ACOMP0_POS_SEL_MSK (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS) +#define AON_ACOMP0_POS_SEL_UMSK (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)) +#define AON_ACOMP0_MUXEN AON_ACOMP0_MUXEN +#define AON_ACOMP0_MUXEN_POS (26U) +#define AON_ACOMP0_MUXEN_LEN (1U) +#define AON_ACOMP0_MUXEN_MSK (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS) +#define AON_ACOMP0_MUXEN_UMSK (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)) + +/* 0x904 : acomp1_ctrl */ +#define AON_ACOMP1_CTRL_OFFSET (0x904) +#define AON_ACOMP1_EN AON_ACOMP1_EN +#define AON_ACOMP1_EN_POS (0U) +#define AON_ACOMP1_EN_LEN (1U) +#define AON_ACOMP1_EN_MSK (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS) +#define AON_ACOMP1_EN_UMSK (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)) +#define AON_ACOMP1_HYST_SELN AON_ACOMP1_HYST_SELN +#define AON_ACOMP1_HYST_SELN_POS (4U) +#define AON_ACOMP1_HYST_SELN_LEN (3U) +#define AON_ACOMP1_HYST_SELN_MSK (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS) +#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)) +#define AON_ACOMP1_HYST_SELP AON_ACOMP1_HYST_SELP +#define AON_ACOMP1_HYST_SELP_POS (7U) +#define AON_ACOMP1_HYST_SELP_LEN (3U) +#define AON_ACOMP1_HYST_SELP_MSK (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS) +#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)) +#define AON_ACOMP1_BIAS_PROG AON_ACOMP1_BIAS_PROG +#define AON_ACOMP1_BIAS_PROG_POS (10U) +#define AON_ACOMP1_BIAS_PROG_LEN (2U) +#define AON_ACOMP1_BIAS_PROG_MSK (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS) +#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)) +#define AON_ACOMP1_LEVEL_SEL AON_ACOMP1_LEVEL_SEL +#define AON_ACOMP1_LEVEL_SEL_POS (12U) +#define AON_ACOMP1_LEVEL_SEL_LEN (6U) +#define AON_ACOMP1_LEVEL_SEL_MSK (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS) +#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)) +#define AON_ACOMP1_NEG_SEL AON_ACOMP1_NEG_SEL +#define AON_ACOMP1_NEG_SEL_POS (18U) +#define AON_ACOMP1_NEG_SEL_LEN (4U) +#define AON_ACOMP1_NEG_SEL_MSK (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS) +#define AON_ACOMP1_NEG_SEL_UMSK (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)) +#define AON_ACOMP1_POS_SEL AON_ACOMP1_POS_SEL +#define AON_ACOMP1_POS_SEL_POS (22U) +#define AON_ACOMP1_POS_SEL_LEN (4U) +#define AON_ACOMP1_POS_SEL_MSK (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS) +#define AON_ACOMP1_POS_SEL_UMSK (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)) +#define AON_ACOMP1_MUXEN AON_ACOMP1_MUXEN +#define AON_ACOMP1_MUXEN_POS (26U) +#define AON_ACOMP1_MUXEN_LEN (1U) +#define AON_ACOMP1_MUXEN_MSK (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS) +#define AON_ACOMP1_MUXEN_UMSK (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)) + +/* 0x908 : acomp_ctrl */ +#define AON_ACOMP_CTRL_OFFSET (0x908) +#define AON_ACOMP1_RSTN_ANA AON_ACOMP1_RSTN_ANA +#define AON_ACOMP1_RSTN_ANA_POS (0U) +#define AON_ACOMP1_RSTN_ANA_LEN (1U) +#define AON_ACOMP1_RSTN_ANA_MSK (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS) +#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)) +#define AON_ACOMP0_RSTN_ANA AON_ACOMP0_RSTN_ANA +#define AON_ACOMP0_RSTN_ANA_POS (1U) +#define AON_ACOMP0_RSTN_ANA_LEN (1U) +#define AON_ACOMP0_RSTN_ANA_MSK (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS) +#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)) +#define AON_ACOMP1_TEST_EN AON_ACOMP1_TEST_EN +#define AON_ACOMP1_TEST_EN_POS (8U) +#define AON_ACOMP1_TEST_EN_LEN (1U) +#define AON_ACOMP1_TEST_EN_MSK (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS) +#define AON_ACOMP1_TEST_EN_UMSK (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)) +#define AON_ACOMP0_TEST_EN AON_ACOMP0_TEST_EN +#define AON_ACOMP0_TEST_EN_POS (9U) +#define AON_ACOMP0_TEST_EN_LEN (1U) +#define AON_ACOMP0_TEST_EN_MSK (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS) +#define AON_ACOMP0_TEST_EN_UMSK (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)) +#define AON_ACOMP1_TEST_SEL AON_ACOMP1_TEST_SEL +#define AON_ACOMP1_TEST_SEL_POS (10U) +#define AON_ACOMP1_TEST_SEL_LEN (2U) +#define AON_ACOMP1_TEST_SEL_MSK (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS) +#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)) +#define AON_ACOMP0_TEST_SEL AON_ACOMP0_TEST_SEL +#define AON_ACOMP0_TEST_SEL_POS (12U) +#define AON_ACOMP0_TEST_SEL_LEN (2U) +#define AON_ACOMP0_TEST_SEL_MSK (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS) +#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)) +#define AON_ACOMP1_OUT_RAW AON_ACOMP1_OUT_RAW +#define AON_ACOMP1_OUT_RAW_POS (17U) +#define AON_ACOMP1_OUT_RAW_LEN (1U) +#define AON_ACOMP1_OUT_RAW_MSK (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS) +#define AON_ACOMP1_OUT_RAW_UMSK (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)) +#define AON_ACOMP0_OUT_RAW AON_ACOMP0_OUT_RAW +#define AON_ACOMP0_OUT_RAW_POS (19U) +#define AON_ACOMP0_OUT_RAW_LEN (1U) +#define AON_ACOMP0_OUT_RAW_MSK (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS) +#define AON_ACOMP0_OUT_RAW_UMSK (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)) +#define AON_ACOMP_RESERVED AON_ACOMP_RESERVED +#define AON_ACOMP_RESERVED_POS (24U) +#define AON_ACOMP_RESERVED_LEN (8U) +#define AON_ACOMP_RESERVED_MSK (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS) +#define AON_ACOMP_RESERVED_UMSK (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)) + +/* 0x90C : gpadc_reg_cmd */ +#define AON_GPADC_REG_CMD_OFFSET (0x90C) +#define AON_GPADC_GLOBAL_EN AON_GPADC_GLOBAL_EN +#define AON_GPADC_GLOBAL_EN_POS (0U) +#define AON_GPADC_GLOBAL_EN_LEN (1U) +#define AON_GPADC_GLOBAL_EN_MSK (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS) +#define AON_GPADC_GLOBAL_EN_UMSK (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)) +#define AON_GPADC_CONV_START AON_GPADC_CONV_START +#define AON_GPADC_CONV_START_POS (1U) +#define AON_GPADC_CONV_START_LEN (1U) +#define AON_GPADC_CONV_START_MSK (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS) +#define AON_GPADC_CONV_START_UMSK (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)) +#define AON_GPADC_SOFT_RST AON_GPADC_SOFT_RST +#define AON_GPADC_SOFT_RST_POS (2U) +#define AON_GPADC_SOFT_RST_LEN (1U) +#define AON_GPADC_SOFT_RST_MSK (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS) +#define AON_GPADC_SOFT_RST_UMSK (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)) +#define AON_GPADC_NEG_SEL AON_GPADC_NEG_SEL +#define AON_GPADC_NEG_SEL_POS (3U) +#define AON_GPADC_NEG_SEL_LEN (5U) +#define AON_GPADC_NEG_SEL_MSK (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS) +#define AON_GPADC_NEG_SEL_UMSK (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)) +#define AON_GPADC_POS_SEL AON_GPADC_POS_SEL +#define AON_GPADC_POS_SEL_POS (8U) +#define AON_GPADC_POS_SEL_LEN (5U) +#define AON_GPADC_POS_SEL_MSK (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS) +#define AON_GPADC_POS_SEL_UMSK (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)) +#define AON_GPADC_NEG_GND AON_GPADC_NEG_GND +#define AON_GPADC_NEG_GND_POS (13U) +#define AON_GPADC_NEG_GND_LEN (1U) +#define AON_GPADC_NEG_GND_MSK (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS) +#define AON_GPADC_NEG_GND_UMSK (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)) +#define AON_GPADC_MICBIAS_EN AON_GPADC_MICBIAS_EN +#define AON_GPADC_MICBIAS_EN_POS (14U) +#define AON_GPADC_MICBIAS_EN_LEN (1U) +#define AON_GPADC_MICBIAS_EN_MSK (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS) +#define AON_GPADC_MICBIAS_EN_UMSK (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)) +#define AON_GPADC_MICPGA_EN AON_GPADC_MICPGA_EN +#define AON_GPADC_MICPGA_EN_POS (15U) +#define AON_GPADC_MICPGA_EN_LEN (1U) +#define AON_GPADC_MICPGA_EN_MSK (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS) +#define AON_GPADC_MICPGA_EN_UMSK (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)) +#define AON_GPADC_BYP_MICBOOST AON_GPADC_BYP_MICBOOST +#define AON_GPADC_BYP_MICBOOST_POS (16U) +#define AON_GPADC_BYP_MICBOOST_LEN (1U) +#define AON_GPADC_BYP_MICBOOST_MSK (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS) +#define AON_GPADC_BYP_MICBOOST_UMSK (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)) +#define AON_GPADC_DWA_EN AON_GPADC_DWA_EN +#define AON_GPADC_DWA_EN_POS (18U) +#define AON_GPADC_DWA_EN_LEN (1U) +#define AON_GPADC_DWA_EN_MSK (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS) +#define AON_GPADC_DWA_EN_UMSK (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)) +#define AON_GPADC_MIC2_DIFF AON_GPADC_MIC2_DIFF +#define AON_GPADC_MIC2_DIFF_POS (19U) +#define AON_GPADC_MIC2_DIFF_LEN (1U) +#define AON_GPADC_MIC2_DIFF_MSK (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS) +#define AON_GPADC_MIC2_DIFF_UMSK (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)) +#define AON_GPADC_MIC1_DIFF AON_GPADC_MIC1_DIFF +#define AON_GPADC_MIC1_DIFF_POS (20U) +#define AON_GPADC_MIC1_DIFF_LEN (1U) +#define AON_GPADC_MIC1_DIFF_MSK (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS) +#define AON_GPADC_MIC1_DIFF_UMSK (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)) +#define AON_GPADC_MIC_PGA2_GAIN AON_GPADC_MIC_PGA2_GAIN +#define AON_GPADC_MIC_PGA2_GAIN_POS (21U) +#define AON_GPADC_MIC_PGA2_GAIN_LEN (2U) +#define AON_GPADC_MIC_PGA2_GAIN_MSK (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS) +#define AON_GPADC_MIC_PGA2_GAIN_UMSK (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)) +#define AON_GPADC_MICBOOST_32DB_EN AON_GPADC_MICBOOST_32DB_EN +#define AON_GPADC_MICBOOST_32DB_EN_POS (23U) +#define AON_GPADC_MICBOOST_32DB_EN_LEN (1U) +#define AON_GPADC_MICBOOST_32DB_EN_MSK (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS) +#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)) +#define AON_GPADC_CHIP_SEN_PU AON_GPADC_CHIP_SEN_PU +#define AON_GPADC_CHIP_SEN_PU_POS (27U) +#define AON_GPADC_CHIP_SEN_PU_LEN (1U) +#define AON_GPADC_CHIP_SEN_PU_MSK (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS) +#define AON_GPADC_CHIP_SEN_PU_UMSK (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)) +#define AON_GPADC_SEN_SEL AON_GPADC_SEN_SEL +#define AON_GPADC_SEN_SEL_POS (28U) +#define AON_GPADC_SEN_SEL_LEN (2U) +#define AON_GPADC_SEN_SEL_MSK (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS) +#define AON_GPADC_SEN_SEL_UMSK (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)) +#define AON_GPADC_SEN_TEST_EN AON_GPADC_SEN_TEST_EN +#define AON_GPADC_SEN_TEST_EN_POS (30U) +#define AON_GPADC_SEN_TEST_EN_LEN (1U) +#define AON_GPADC_SEN_TEST_EN_MSK (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS) +#define AON_GPADC_SEN_TEST_EN_UMSK (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)) + +/* 0x910 : gpadc_reg_config1 */ +#define AON_GPADC_REG_CONFIG1_OFFSET (0x910) +#define AON_GPADC_CAL_OS_EN AON_GPADC_CAL_OS_EN +#define AON_GPADC_CAL_OS_EN_POS (0U) +#define AON_GPADC_CAL_OS_EN_LEN (1U) +#define AON_GPADC_CAL_OS_EN_MSK (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS) +#define AON_GPADC_CAL_OS_EN_UMSK (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)) +#define AON_GPADC_CONT_CONV_EN AON_GPADC_CONT_CONV_EN +#define AON_GPADC_CONT_CONV_EN_POS (1U) +#define AON_GPADC_CONT_CONV_EN_LEN (1U) +#define AON_GPADC_CONT_CONV_EN_MSK (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS) +#define AON_GPADC_CONT_CONV_EN_UMSK (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)) +#define AON_GPADC_RES_SEL AON_GPADC_RES_SEL +#define AON_GPADC_RES_SEL_POS (2U) +#define AON_GPADC_RES_SEL_LEN (3U) +#define AON_GPADC_RES_SEL_MSK (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS) +#define AON_GPADC_RES_SEL_UMSK (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)) +#define AON_GPADC_VCM_SEL_EN AON_GPADC_VCM_SEL_EN +#define AON_GPADC_VCM_SEL_EN_POS (8U) +#define AON_GPADC_VCM_SEL_EN_LEN (1U) +#define AON_GPADC_VCM_SEL_EN_MSK (((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS) +#define AON_GPADC_VCM_SEL_EN_UMSK (~(((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS)) +#define AON_GPADC_VCM_HYST_SEL AON_GPADC_VCM_HYST_SEL +#define AON_GPADC_VCM_HYST_SEL_POS (9U) +#define AON_GPADC_VCM_HYST_SEL_LEN (1U) +#define AON_GPADC_VCM_HYST_SEL_MSK (((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS) +#define AON_GPADC_VCM_HYST_SEL_UMSK (~(((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS)) +#define AON_GPADC_LOWV_DET_EN AON_GPADC_LOWV_DET_EN +#define AON_GPADC_LOWV_DET_EN_POS (10U) +#define AON_GPADC_LOWV_DET_EN_LEN (1U) +#define AON_GPADC_LOWV_DET_EN_MSK (((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS) +#define AON_GPADC_LOWV_DET_EN_UMSK (~(((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS)) +#define AON_GPADC_CLK_ANA_INV AON_GPADC_CLK_ANA_INV +#define AON_GPADC_CLK_ANA_INV_POS (17U) +#define AON_GPADC_CLK_ANA_INV_LEN (1U) +#define AON_GPADC_CLK_ANA_INV_MSK (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS) +#define AON_GPADC_CLK_ANA_INV_UMSK (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)) +#define AON_GPADC_CLK_DIV_RATIO AON_GPADC_CLK_DIV_RATIO +#define AON_GPADC_CLK_DIV_RATIO_POS (18U) +#define AON_GPADC_CLK_DIV_RATIO_LEN (3U) +#define AON_GPADC_CLK_DIV_RATIO_MSK (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS) +#define AON_GPADC_CLK_DIV_RATIO_UMSK (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)) +#define AON_GPADC_SCAN_LENGTH AON_GPADC_SCAN_LENGTH +#define AON_GPADC_SCAN_LENGTH_POS (21U) +#define AON_GPADC_SCAN_LENGTH_LEN (4U) +#define AON_GPADC_SCAN_LENGTH_MSK (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS) +#define AON_GPADC_SCAN_LENGTH_UMSK (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)) +#define AON_GPADC_SCAN_EN AON_GPADC_SCAN_EN +#define AON_GPADC_SCAN_EN_POS (25U) +#define AON_GPADC_SCAN_EN_LEN (1U) +#define AON_GPADC_SCAN_EN_MSK (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS) +#define AON_GPADC_SCAN_EN_UMSK (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)) +#define AON_GPADC_DITHER_EN AON_GPADC_DITHER_EN +#define AON_GPADC_DITHER_EN_POS (26U) +#define AON_GPADC_DITHER_EN_LEN (1U) +#define AON_GPADC_DITHER_EN_MSK (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS) +#define AON_GPADC_DITHER_EN_UMSK (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)) +#define AON_GPADC_V11_SEL AON_GPADC_V11_SEL +#define AON_GPADC_V11_SEL_POS (27U) +#define AON_GPADC_V11_SEL_LEN (2U) +#define AON_GPADC_V11_SEL_MSK (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS) +#define AON_GPADC_V11_SEL_UMSK (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)) +#define AON_GPADC_V18_SEL AON_GPADC_V18_SEL +#define AON_GPADC_V18_SEL_POS (29U) +#define AON_GPADC_V18_SEL_LEN (2U) +#define AON_GPADC_V18_SEL_MSK (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS) +#define AON_GPADC_V18_SEL_UMSK (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)) + +/* 0x914 : gpadc_reg_config2 */ +#define AON_GPADC_REG_CONFIG2_OFFSET (0x914) +#define AON_GPADC_DIFF_MODE AON_GPADC_DIFF_MODE +#define AON_GPADC_DIFF_MODE_POS (2U) +#define AON_GPADC_DIFF_MODE_LEN (1U) +#define AON_GPADC_DIFF_MODE_MSK (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS) +#define AON_GPADC_DIFF_MODE_UMSK (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)) +#define AON_GPADC_VREF_SEL AON_GPADC_VREF_SEL +#define AON_GPADC_VREF_SEL_POS (3U) +#define AON_GPADC_VREF_SEL_LEN (1U) +#define AON_GPADC_VREF_SEL_MSK (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS) +#define AON_GPADC_VREF_SEL_UMSK (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)) +#define AON_GPADC_VBAT_EN AON_GPADC_VBAT_EN +#define AON_GPADC_VBAT_EN_POS (4U) +#define AON_GPADC_VBAT_EN_LEN (1U) +#define AON_GPADC_VBAT_EN_MSK (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS) +#define AON_GPADC_VBAT_EN_UMSK (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)) +#define AON_GPADC_TSEXT_SEL AON_GPADC_TSEXT_SEL +#define AON_GPADC_TSEXT_SEL_POS (5U) +#define AON_GPADC_TSEXT_SEL_LEN (1U) +#define AON_GPADC_TSEXT_SEL_MSK (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS) +#define AON_GPADC_TSEXT_SEL_UMSK (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)) +#define AON_GPADC_TS_EN AON_GPADC_TS_EN +#define AON_GPADC_TS_EN_POS (6U) +#define AON_GPADC_TS_EN_LEN (1U) +#define AON_GPADC_TS_EN_MSK (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS) +#define AON_GPADC_TS_EN_UMSK (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)) +#define AON_GPADC_PGA_VCM AON_GPADC_PGA_VCM +#define AON_GPADC_PGA_VCM_POS (7U) +#define AON_GPADC_PGA_VCM_LEN (2U) +#define AON_GPADC_PGA_VCM_MSK (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS) +#define AON_GPADC_PGA_VCM_UMSK (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)) +#define AON_GPADC_PGA_OS_CAL AON_GPADC_PGA_OS_CAL +#define AON_GPADC_PGA_OS_CAL_POS (9U) +#define AON_GPADC_PGA_OS_CAL_LEN (4U) +#define AON_GPADC_PGA_OS_CAL_MSK (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS) +#define AON_GPADC_PGA_OS_CAL_UMSK (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)) +#define AON_GPADC_PGA_EN AON_GPADC_PGA_EN +#define AON_GPADC_PGA_EN_POS (13U) +#define AON_GPADC_PGA_EN_LEN (1U) +#define AON_GPADC_PGA_EN_MSK (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS) +#define AON_GPADC_PGA_EN_UMSK (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)) +#define AON_GPADC_PGA_VCMI_EN AON_GPADC_PGA_VCMI_EN +#define AON_GPADC_PGA_VCMI_EN_POS (14U) +#define AON_GPADC_PGA_VCMI_EN_LEN (1U) +#define AON_GPADC_PGA_VCMI_EN_MSK (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS) +#define AON_GPADC_PGA_VCMI_EN_UMSK (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)) +#define AON_GPADC_CHOP_MODE AON_GPADC_CHOP_MODE +#define AON_GPADC_CHOP_MODE_POS (15U) +#define AON_GPADC_CHOP_MODE_LEN (2U) +#define AON_GPADC_CHOP_MODE_MSK (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS) +#define AON_GPADC_CHOP_MODE_UMSK (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)) +#define AON_GPADC_BIAS_SEL AON_GPADC_BIAS_SEL +#define AON_GPADC_BIAS_SEL_POS (17U) +#define AON_GPADC_BIAS_SEL_LEN (1U) +#define AON_GPADC_BIAS_SEL_MSK (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS) +#define AON_GPADC_BIAS_SEL_UMSK (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)) +#define AON_GPADC_TEST_EN AON_GPADC_TEST_EN +#define AON_GPADC_TEST_EN_POS (18U) +#define AON_GPADC_TEST_EN_LEN (1U) +#define AON_GPADC_TEST_EN_MSK (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS) +#define AON_GPADC_TEST_EN_UMSK (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)) +#define AON_GPADC_TEST_SEL AON_GPADC_TEST_SEL +#define AON_GPADC_TEST_SEL_POS (19U) +#define AON_GPADC_TEST_SEL_LEN (3U) +#define AON_GPADC_TEST_SEL_MSK (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS) +#define AON_GPADC_TEST_SEL_UMSK (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)) +#define AON_GPADC_PGA2_GAIN AON_GPADC_PGA2_GAIN +#define AON_GPADC_PGA2_GAIN_POS (22U) +#define AON_GPADC_PGA2_GAIN_LEN (3U) +#define AON_GPADC_PGA2_GAIN_MSK (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS) +#define AON_GPADC_PGA2_GAIN_UMSK (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)) +#define AON_GPADC_PGA1_GAIN AON_GPADC_PGA1_GAIN +#define AON_GPADC_PGA1_GAIN_POS (25U) +#define AON_GPADC_PGA1_GAIN_LEN (3U) +#define AON_GPADC_PGA1_GAIN_MSK (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS) +#define AON_GPADC_PGA1_GAIN_UMSK (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)) +#define AON_GPADC_DLY_SEL AON_GPADC_DLY_SEL +#define AON_GPADC_DLY_SEL_POS (28U) +#define AON_GPADC_DLY_SEL_LEN (3U) +#define AON_GPADC_DLY_SEL_MSK (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS) +#define AON_GPADC_DLY_SEL_UMSK (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)) +#define AON_GPADC_TSVBE_LOW AON_GPADC_TSVBE_LOW +#define AON_GPADC_TSVBE_LOW_POS (31U) +#define AON_GPADC_TSVBE_LOW_LEN (1U) +#define AON_GPADC_TSVBE_LOW_MSK (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS) +#define AON_GPADC_TSVBE_LOW_UMSK (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)) + +/* 0x918 : adc converation sequence 1 */ +#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918) +#define AON_GPADC_SCAN_POS_0 AON_GPADC_SCAN_POS_0 +#define AON_GPADC_SCAN_POS_0_POS (0U) +#define AON_GPADC_SCAN_POS_0_LEN (5U) +#define AON_GPADC_SCAN_POS_0_MSK (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS) +#define AON_GPADC_SCAN_POS_0_UMSK (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)) +#define AON_GPADC_SCAN_POS_1 AON_GPADC_SCAN_POS_1 +#define AON_GPADC_SCAN_POS_1_POS (5U) +#define AON_GPADC_SCAN_POS_1_LEN (5U) +#define AON_GPADC_SCAN_POS_1_MSK (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS) +#define AON_GPADC_SCAN_POS_1_UMSK (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)) +#define AON_GPADC_SCAN_POS_2 AON_GPADC_SCAN_POS_2 +#define AON_GPADC_SCAN_POS_2_POS (10U) +#define AON_GPADC_SCAN_POS_2_LEN (5U) +#define AON_GPADC_SCAN_POS_2_MSK (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS) +#define AON_GPADC_SCAN_POS_2_UMSK (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)) +#define AON_GPADC_SCAN_POS_3 AON_GPADC_SCAN_POS_3 +#define AON_GPADC_SCAN_POS_3_POS (15U) +#define AON_GPADC_SCAN_POS_3_LEN (5U) +#define AON_GPADC_SCAN_POS_3_MSK (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS) +#define AON_GPADC_SCAN_POS_3_UMSK (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)) +#define AON_GPADC_SCAN_POS_4 AON_GPADC_SCAN_POS_4 +#define AON_GPADC_SCAN_POS_4_POS (20U) +#define AON_GPADC_SCAN_POS_4_LEN (5U) +#define AON_GPADC_SCAN_POS_4_MSK (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS) +#define AON_GPADC_SCAN_POS_4_UMSK (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)) +#define AON_GPADC_SCAN_POS_5 AON_GPADC_SCAN_POS_5 +#define AON_GPADC_SCAN_POS_5_POS (25U) +#define AON_GPADC_SCAN_POS_5_LEN (5U) +#define AON_GPADC_SCAN_POS_5_MSK (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS) +#define AON_GPADC_SCAN_POS_5_UMSK (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)) + +/* 0x91C : adc converation sequence 2 */ +#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C) +#define AON_GPADC_SCAN_POS_6 AON_GPADC_SCAN_POS_6 +#define AON_GPADC_SCAN_POS_6_POS (0U) +#define AON_GPADC_SCAN_POS_6_LEN (5U) +#define AON_GPADC_SCAN_POS_6_MSK (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS) +#define AON_GPADC_SCAN_POS_6_UMSK (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)) +#define AON_GPADC_SCAN_POS_7 AON_GPADC_SCAN_POS_7 +#define AON_GPADC_SCAN_POS_7_POS (5U) +#define AON_GPADC_SCAN_POS_7_LEN (5U) +#define AON_GPADC_SCAN_POS_7_MSK (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS) +#define AON_GPADC_SCAN_POS_7_UMSK (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)) +#define AON_GPADC_SCAN_POS_8 AON_GPADC_SCAN_POS_8 +#define AON_GPADC_SCAN_POS_8_POS (10U) +#define AON_GPADC_SCAN_POS_8_LEN (5U) +#define AON_GPADC_SCAN_POS_8_MSK (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS) +#define AON_GPADC_SCAN_POS_8_UMSK (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)) +#define AON_GPADC_SCAN_POS_9 AON_GPADC_SCAN_POS_9 +#define AON_GPADC_SCAN_POS_9_POS (15U) +#define AON_GPADC_SCAN_POS_9_LEN (5U) +#define AON_GPADC_SCAN_POS_9_MSK (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS) +#define AON_GPADC_SCAN_POS_9_UMSK (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)) +#define AON_GPADC_SCAN_POS_10 AON_GPADC_SCAN_POS_10 +#define AON_GPADC_SCAN_POS_10_POS (20U) +#define AON_GPADC_SCAN_POS_10_LEN (5U) +#define AON_GPADC_SCAN_POS_10_MSK (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS) +#define AON_GPADC_SCAN_POS_10_UMSK (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)) +#define AON_GPADC_SCAN_POS_11 AON_GPADC_SCAN_POS_11 +#define AON_GPADC_SCAN_POS_11_POS (25U) +#define AON_GPADC_SCAN_POS_11_LEN (5U) +#define AON_GPADC_SCAN_POS_11_MSK (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS) +#define AON_GPADC_SCAN_POS_11_UMSK (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)) + +/* 0x920 : adc converation sequence 3 */ +#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920) +#define AON_GPADC_SCAN_NEG_0 AON_GPADC_SCAN_NEG_0 +#define AON_GPADC_SCAN_NEG_0_POS (0U) +#define AON_GPADC_SCAN_NEG_0_LEN (5U) +#define AON_GPADC_SCAN_NEG_0_MSK (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS) +#define AON_GPADC_SCAN_NEG_0_UMSK (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)) +#define AON_GPADC_SCAN_NEG_1 AON_GPADC_SCAN_NEG_1 +#define AON_GPADC_SCAN_NEG_1_POS (5U) +#define AON_GPADC_SCAN_NEG_1_LEN (5U) +#define AON_GPADC_SCAN_NEG_1_MSK (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS) +#define AON_GPADC_SCAN_NEG_1_UMSK (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)) +#define AON_GPADC_SCAN_NEG_2 AON_GPADC_SCAN_NEG_2 +#define AON_GPADC_SCAN_NEG_2_POS (10U) +#define AON_GPADC_SCAN_NEG_2_LEN (5U) +#define AON_GPADC_SCAN_NEG_2_MSK (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS) +#define AON_GPADC_SCAN_NEG_2_UMSK (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)) +#define AON_GPADC_SCAN_NEG_3 AON_GPADC_SCAN_NEG_3 +#define AON_GPADC_SCAN_NEG_3_POS (15U) +#define AON_GPADC_SCAN_NEG_3_LEN (5U) +#define AON_GPADC_SCAN_NEG_3_MSK (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS) +#define AON_GPADC_SCAN_NEG_3_UMSK (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)) +#define AON_GPADC_SCAN_NEG_4 AON_GPADC_SCAN_NEG_4 +#define AON_GPADC_SCAN_NEG_4_POS (20U) +#define AON_GPADC_SCAN_NEG_4_LEN (5U) +#define AON_GPADC_SCAN_NEG_4_MSK (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS) +#define AON_GPADC_SCAN_NEG_4_UMSK (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)) +#define AON_GPADC_SCAN_NEG_5 AON_GPADC_SCAN_NEG_5 +#define AON_GPADC_SCAN_NEG_5_POS (25U) +#define AON_GPADC_SCAN_NEG_5_LEN (5U) +#define AON_GPADC_SCAN_NEG_5_MSK (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS) +#define AON_GPADC_SCAN_NEG_5_UMSK (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)) + +/* 0x924 : adc converation sequence 4 */ +#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924) +#define AON_GPADC_SCAN_NEG_6 AON_GPADC_SCAN_NEG_6 +#define AON_GPADC_SCAN_NEG_6_POS (0U) +#define AON_GPADC_SCAN_NEG_6_LEN (5U) +#define AON_GPADC_SCAN_NEG_6_MSK (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS) +#define AON_GPADC_SCAN_NEG_6_UMSK (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)) +#define AON_GPADC_SCAN_NEG_7 AON_GPADC_SCAN_NEG_7 +#define AON_GPADC_SCAN_NEG_7_POS (5U) +#define AON_GPADC_SCAN_NEG_7_LEN (5U) +#define AON_GPADC_SCAN_NEG_7_MSK (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS) +#define AON_GPADC_SCAN_NEG_7_UMSK (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)) +#define AON_GPADC_SCAN_NEG_8 AON_GPADC_SCAN_NEG_8 +#define AON_GPADC_SCAN_NEG_8_POS (10U) +#define AON_GPADC_SCAN_NEG_8_LEN (5U) +#define AON_GPADC_SCAN_NEG_8_MSK (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS) +#define AON_GPADC_SCAN_NEG_8_UMSK (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)) +#define AON_GPADC_SCAN_NEG_9 AON_GPADC_SCAN_NEG_9 +#define AON_GPADC_SCAN_NEG_9_POS (15U) +#define AON_GPADC_SCAN_NEG_9_LEN (5U) +#define AON_GPADC_SCAN_NEG_9_MSK (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS) +#define AON_GPADC_SCAN_NEG_9_UMSK (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)) +#define AON_GPADC_SCAN_NEG_10 AON_GPADC_SCAN_NEG_10 +#define AON_GPADC_SCAN_NEG_10_POS (20U) +#define AON_GPADC_SCAN_NEG_10_LEN (5U) +#define AON_GPADC_SCAN_NEG_10_MSK (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS) +#define AON_GPADC_SCAN_NEG_10_UMSK (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)) +#define AON_GPADC_SCAN_NEG_11 AON_GPADC_SCAN_NEG_11 +#define AON_GPADC_SCAN_NEG_11_POS (25U) +#define AON_GPADC_SCAN_NEG_11_LEN (5U) +#define AON_GPADC_SCAN_NEG_11_MSK (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS) +#define AON_GPADC_SCAN_NEG_11_UMSK (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)) + +/* 0x928 : gpadc_reg_status */ +#define AON_GPADC_REG_STATUS_OFFSET (0x928) +#define AON_GPADC_DATA_RDY AON_GPADC_DATA_RDY +#define AON_GPADC_DATA_RDY_POS (0U) +#define AON_GPADC_DATA_RDY_LEN (1U) +#define AON_GPADC_DATA_RDY_MSK (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS) +#define AON_GPADC_DATA_RDY_UMSK (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)) +#define AON_GPADC_RESERVED AON_GPADC_RESERVED +#define AON_GPADC_RESERVED_POS (16U) +#define AON_GPADC_RESERVED_LEN (16U) +#define AON_GPADC_RESERVED_MSK (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS) +#define AON_GPADC_RESERVED_UMSK (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)) + +/* 0x92C : gpadc_reg_isr */ +#define AON_GPADC_REG_ISR_OFFSET (0x92C) +#define AON_GPADC_NEG_SATUR AON_GPADC_NEG_SATUR +#define AON_GPADC_NEG_SATUR_POS (0U) +#define AON_GPADC_NEG_SATUR_LEN (1U) +#define AON_GPADC_NEG_SATUR_MSK (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS) +#define AON_GPADC_NEG_SATUR_UMSK (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)) +#define AON_GPADC_POS_SATUR AON_GPADC_POS_SATUR +#define AON_GPADC_POS_SATUR_POS (1U) +#define AON_GPADC_POS_SATUR_LEN (1U) +#define AON_GPADC_POS_SATUR_MSK (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS) +#define AON_GPADC_POS_SATUR_UMSK (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)) +#define AON_GPADC_NEG_SATUR_CLR AON_GPADC_NEG_SATUR_CLR +#define AON_GPADC_NEG_SATUR_CLR_POS (4U) +#define AON_GPADC_NEG_SATUR_CLR_LEN (1U) +#define AON_GPADC_NEG_SATUR_CLR_MSK (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS) +#define AON_GPADC_NEG_SATUR_CLR_UMSK (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)) +#define AON_GPADC_POS_SATUR_CLR AON_GPADC_POS_SATUR_CLR +#define AON_GPADC_POS_SATUR_CLR_POS (5U) +#define AON_GPADC_POS_SATUR_CLR_LEN (1U) +#define AON_GPADC_POS_SATUR_CLR_MSK (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS) +#define AON_GPADC_POS_SATUR_CLR_UMSK (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)) +#define AON_GPADC_NEG_SATUR_MASK AON_GPADC_NEG_SATUR_MASK +#define AON_GPADC_NEG_SATUR_MASK_POS (8U) +#define AON_GPADC_NEG_SATUR_MASK_LEN (1U) +#define AON_GPADC_NEG_SATUR_MASK_MSK (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS) +#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)) +#define AON_GPADC_POS_SATUR_MASK AON_GPADC_POS_SATUR_MASK +#define AON_GPADC_POS_SATUR_MASK_POS (9U) +#define AON_GPADC_POS_SATUR_MASK_LEN (1U) +#define AON_GPADC_POS_SATUR_MASK_MSK (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS) +#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)) + +/* 0x930 : gpadc_reg_result */ +#define AON_GPADC_REG_RESULT_OFFSET (0x930) +#define AON_GPADC_DATA_OUT AON_GPADC_DATA_OUT +#define AON_GPADC_DATA_OUT_POS (0U) +#define AON_GPADC_DATA_OUT_LEN (26U) +#define AON_GPADC_DATA_OUT_MSK (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS) +#define AON_GPADC_DATA_OUT_UMSK (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)) + +/* 0x934 : gpadc_reg_raw_result */ +#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934) +#define AON_GPADC_RAW_DATA AON_GPADC_RAW_DATA +#define AON_GPADC_RAW_DATA_POS (0U) +#define AON_GPADC_RAW_DATA_LEN (12U) +#define AON_GPADC_RAW_DATA_MSK (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS) +#define AON_GPADC_RAW_DATA_UMSK (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)) + +/* 0x938 : gpadc_reg_define */ +#define AON_GPADC_REG_DEFINE_OFFSET (0x938) +#define AON_GPADC_OS_CAL_DATA AON_GPADC_OS_CAL_DATA +#define AON_GPADC_OS_CAL_DATA_POS (0U) +#define AON_GPADC_OS_CAL_DATA_LEN (16U) +#define AON_GPADC_OS_CAL_DATA_MSK (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS) +#define AON_GPADC_OS_CAL_DATA_UMSK (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)) + +/* 0x93C : hbncore_resv0 */ +#define AON_HBNCORE_RESV0_OFFSET (0x93C) +#define AON_HBNCORE_RESV0_DATA AON_HBNCORE_RESV0_DATA +#define AON_HBNCORE_RESV0_DATA_POS (0U) +#define AON_HBNCORE_RESV0_DATA_LEN (32U) +#define AON_HBNCORE_RESV0_DATA_MSK (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS) +#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)) + +/* 0x940 : hbncore_resv1 */ +#define AON_HBNCORE_RESV1_OFFSET (0x940) +#define AON_HBNCORE_RESV1_DATA AON_HBNCORE_RESV1_DATA +#define AON_HBNCORE_RESV1_DATA_POS (0U) +#define AON_HBNCORE_RESV1_DATA_LEN (32U) +#define AON_HBNCORE_RESV1_DATA_MSK (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS) +#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)) + +struct aon_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[2048]; + + /* 0x800 : aon */ + union { + struct + { + uint32_t aon_resv : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t pu_aon_dc_tbuf : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_19 : 7; /* [19:13], rsvd, 0x0 */ + uint32_t ldo11_rt_pulldown : 1; /* [ 20], r/w, 0x0 */ + uint32_t ldo11_rt_pulldown_sel : 1; /* [ 21], r/w, 0x0 */ + uint32_t sw_pu_ldo11_rt : 1; /* [ 22], r/w, 0x1 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon; + + /* 0x804 : aon_common */ + union { + struct + { + uint32_t tmux_aon : 3; /* [ 2: 0], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t ten_aon : 1; /* [ 4], r/w, 0x0 */ + uint32_t dten_xtal32k : 1; /* [ 5], r/w, 0x0 */ + uint32_t ten_xtal32k : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t ten_vddcore_aon : 1; /* [ 8], r/w, 0x0 */ + uint32_t ten_ldo11soc_aon : 1; /* [ 9], r/w, 0x0 */ + uint32_t ten_dcdc18_0_aon : 1; /* [ 10], r/w, 0x0 */ + uint32_t ten_dcdc18_1_aon : 1; /* [ 11], r/w, 0x0 */ + uint32_t ten_bg_sys_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t ten_ldo15rf_aon : 1; /* [ 16], r/w, 0x0 */ + uint32_t ten_xtal_aon : 1; /* [ 17], r/w, 0x0 */ + uint32_t dten_xtal_aon : 1; /* [ 18], r/w, 0x0 */ + uint32_t ten_mbg_aon : 1; /* [ 19], r/w, 0x0 */ + uint32_t ten_cip_misc_aon : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon_common; + + /* 0x808 : aon_misc */ + union { + struct + { + uint32_t sw_soc_en_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t sw_bz_en_aon : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon_misc; + + /* 0x80c reserved */ + uint8_t RESERVED0x80c[4]; + + /* 0x810 : bg_sys_top */ + union { + struct + { + uint32_t pmip_resv : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t pu_bg_sys_aon : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t bg_sys_start_ctrl_aon : 1; /* [ 12], r/w, 0x1 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } bg_sys_top; + + /* 0x814 : dcdc18_top_0 */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t dcdc18_vout_sel_aon : 5; /* [ 5: 1], r/w, 0x1b */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t dcdc18_vpfm_aon : 4; /* [11: 8], r/w, 0x7 */ + uint32_t dcdc18_osc_2m_mode_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t dcdc18_osc_freq_trim_aon : 4; /* [19:16], r/w, 0x8 */ + uint32_t dcdc18_slope_curr_sel_aon : 5; /* [24:20], r/w, 0x5 */ + uint32_t dcdc18_stop_osc_aon : 1; /* [ 25], r/w, 0x1 */ + uint32_t dcdc18_slow_osc_aon : 1; /* [ 26], r/w, 0x0 */ + uint32_t dcdc18_osc_inhibit_t2_aon : 1; /* [ 27], r/w, 0x1 */ + uint32_t dcdc18_sstart_time_aon : 2; /* [29:28], r/w, 0x0 */ + uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ + uint32_t dcdc18_rdy_aon : 1; /* [ 31], r, 0x1 */ + } BF; + uint32_t WORD; + } dcdc18_top_0; + + /* 0x818 : dcdc18_top_1 */ + union { + struct + { + uint32_t dcdc18_force_cs_zvs_aon : 1; /* [ 0], r/w, 0x0 */ + uint32_t dcdc18_cs_delay_aon : 3; /* [ 3: 1], r/w, 0x4 */ + uint32_t dcdc18_zvs_td_opt_aon : 3; /* [ 6: 4], r/w, 0x4 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t dcdc18_nonoverlap_td_aon : 5; /* [12: 8], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t dcdc18_rc_sel_aon : 4; /* [19:16], r/w, 0x8 */ + uint32_t dcdc18_chf_sel_aon : 4; /* [23:20], r/w, 0x1 */ + uint32_t dcdc18_cfb_sel_aon : 4; /* [27:24], r/w, 0x8 */ + uint32_t dcdc18_en_antiring_aon : 1; /* [ 28], r/w, 0x1 */ + uint32_t dcdc18_pulldown_aon : 1; /* [ 29], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } dcdc18_top_1; + + /* 0x81C : ldo11soc_and_dctest */ + union { + struct + { + uint32_t pu_ldo11soc_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t ldo11soc_sstart_sel_aon : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t ldo11soc_sstart_delay_aon : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t ldo11soc_pulldown_aon : 1; /* [ 10], r/w, 0x0 */ + uint32_t ldo11soc_pulldown_sel_aon : 1; /* [ 11], r/w, 0x1 */ + uint32_t ldo11soc_vth_sel_aon : 2; /* [13:12], r/w, 0x1 */ + uint32_t reserved_14_23 : 10; /* [23:14], rsvd, 0x0 */ + uint32_t ldo11soc_cc_aon : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t ldo11soc_rdy_aon : 1; /* [ 28], r, 0x1 */ + uint32_t ldo11soc_power_good_aon : 1; /* [ 29], r, 0x1 */ + uint32_t pu_vddcore_misc_aon : 1; /* [ 30], r/w, 0x1 */ + uint32_t pmip_dc_tp_out_en_aon : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ldo11soc_and_dctest; + + /* 0x820 : psw_irrcv */ + union { + struct + { + uint32_t pu_ir_psw_aon : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } psw_irrcv; + + /* 0x824 reserved */ + uint8_t RESERVED0x824[92]; + + /* 0x880 : rf_top_aon */ + union { + struct + { + uint32_t pu_mbg_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t pu_ldo15rf_aon : 1; /* [ 1], r/w, 0x1 */ + uint32_t pu_sfreg_aon : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t pu_xtal_buf_aon : 1; /* [ 4], r/w, 0x1 */ + uint32_t pu_xtal_aon : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t ldo15rf_sstart_sel_aon : 1; /* [ 8], r/w, 0x1 */ + uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t ldo15rf_pulldown_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t ldo15rf_pulldown_sel_aon : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t ldo15rf_vout_sel_aon : 3; /* [18:16], r/w, 0x2 */ + uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ + uint32_t ldo15rf_cc_aon : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t ldo15rf_bypass_aon : 1; /* [ 28], r/w, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rf_top_aon; + + /* 0x884 : xtal_cfg */ + union { + struct + { + uint32_t xtal_bk_aon : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t xtal_capcode_extra_aon : 1; /* [ 2], r/w, 0x0 */ + uint32_t xtal_ext_sel_aon : 1; /* [ 3], r/w, 0x0 */ + uint32_t xtal_buf_en_aon : 4; /* [ 7: 4], r/w, 0xf */ + uint32_t xtal_buf_hp_aon : 4; /* [11: 8], r/w, 0x0 */ + uint32_t xtal_fast_startup_aon : 1; /* [ 12], r/w, 0x1 */ + uint32_t xtal_sleep_aon : 1; /* [ 13], r/w, 0x1 */ + uint32_t xtal_amp_ctrl_aon : 2; /* [15:14], r/w, 0x3 */ + uint32_t xtal_capcode_out_aon : 6; /* [21:16], r/w, 0x10 */ + uint32_t xtal_capcode_in_aon : 6; /* [27:22], r/w, 0x10 */ + uint32_t xtal_gm_boost_aon : 2; /* [29:28], r/w, 0x3 */ + uint32_t xtal_rdy_sel_aon : 2; /* [31:30], r/w, 0x2 */ + } BF; + uint32_t WORD; + } xtal_cfg; + + /* 0x888 : tsen */ + union { + struct + { + uint32_t tsen_refcode_corner : 12; /* [11: 0], r/w, 0x8ff */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t tsen_refcode_rfcal : 12; /* [27:16], r/w, 0x8ff */ + uint32_t xtal_rdy : 1; /* [ 28], r, 0x1 */ + uint32_t xtal_inn_cfg_en_aon : 1; /* [ 29], r/w, 0x1 */ + uint32_t xtal_rdy_int_sel_aon : 2; /* [31:30], r/w, 0x1 */ + } BF; + uint32_t WORD; + } tsen; + + /* 0x88c reserved */ + uint8_t RESERVED0x88c[116]; + + /* 0x900 : acomp0_ctrl */ + union { + struct + { + uint32_t acomp0_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t acomp0_hyst_seln : 3; /* [ 6: 4], r/w, 0x0 */ + uint32_t acomp0_hyst_selp : 3; /* [ 9: 7], r/w, 0x0 */ + uint32_t acomp0_bias_prog : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp0_level_sel : 6; /* [17:12], r/w, 0x0 */ + uint32_t acomp0_neg_sel : 4; /* [21:18], r/w, 0x0 */ + uint32_t acomp0_pos_sel : 4; /* [25:22], r/w, 0x0 */ + uint32_t acomp0_muxen : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } acomp0_ctrl; + + /* 0x904 : acomp1_ctrl */ + union { + struct + { + uint32_t acomp1_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t acomp1_hyst_seln : 3; /* [ 6: 4], r/w, 0x0 */ + uint32_t acomp1_hyst_selp : 3; /* [ 9: 7], r/w, 0x0 */ + uint32_t acomp1_bias_prog : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp1_level_sel : 6; /* [17:12], r/w, 0x0 */ + uint32_t acomp1_neg_sel : 4; /* [21:18], r/w, 0x0 */ + uint32_t acomp1_pos_sel : 4; /* [25:22], r/w, 0x0 */ + uint32_t acomp1_muxen : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } acomp1_ctrl; + + /* 0x908 : acomp_ctrl */ + union { + struct + { + uint32_t acomp1_rstn_ana : 1; /* [ 0], r/w, 0x1 */ + uint32_t acomp0_rstn_ana : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t acomp1_test_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t acomp0_test_en : 1; /* [ 9], r/w, 0x0 */ + uint32_t acomp1_test_sel : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp0_test_sel : 2; /* [13:12], r/w, 0x0 */ + uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */ + uint32_t acomp1_out_raw : 1; /* [ 17], r, 0x0 */ + uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t acomp0_out_raw : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t acomp_reserved : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } acomp_ctrl; + + /* 0x90C : gpadc_reg_cmd */ + union { + struct + { + uint32_t gpadc_global_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpadc_conv_start : 1; /* [ 1], r/w, 0x0 */ + uint32_t gpadc_soft_rst : 1; /* [ 2], r/w, 0x0 */ + uint32_t gpadc_neg_sel : 5; /* [ 7: 3], r/w, 0xf */ + uint32_t gpadc_pos_sel : 5; /* [12: 8], r/w, 0xf */ + uint32_t gpadc_neg_gnd : 1; /* [ 13], r/w, 0x0 */ + uint32_t gpadc_micbias_en : 1; /* [ 14], r/w, 0x0 */ + uint32_t gpadc_micpga_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t gpadc_byp_micboost : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t gpadc_dwa_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t gpadc_mic2_diff : 1; /* [ 19], r/w, 0x0 */ + uint32_t gpadc_mic1_diff : 1; /* [ 20], r/w, 0x0 */ + uint32_t gpadc_mic_pga2_gain : 2; /* [22:21], r/w, 0x0 */ + uint32_t gpadc_micboost_32db_en : 1; /* [ 23], r/w, 0x0 */ + uint32_t reserved_24_26 : 3; /* [26:24], rsvd, 0x0 */ + uint32_t gpadc_chip_sen_pu : 1; /* [ 27], r/w, 0x0 */ + uint32_t gpadc_sen_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t gpadc_sen_test_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_cmd; + + /* 0x910 : gpadc_reg_config1 */ + union { + struct + { + uint32_t gpadc_cal_os_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpadc_cont_conv_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t gpadc_res_sel : 3; /* [ 4: 2], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t gpadc_vcm_sel_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpadc_vcm_hyst_sel : 1; /* [ 9], r/w, 0x0 */ + uint32_t gpadc_lowv_det_en : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_16 : 6; /* [16:11], rsvd, 0x0 */ + uint32_t gpadc_clk_ana_inv : 1; /* [ 17], r/w, 0x0 */ + uint32_t gpadc_clk_div_ratio : 3; /* [20:18], r/w, 0x3 */ + uint32_t gpadc_scan_length : 4; /* [24:21], r/w, 0x0 */ + uint32_t gpadc_scan_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t gpadc_dither_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t gpadc_v11_sel : 2; /* [28:27], r/w, 0x0 */ + uint32_t gpadc_v18_sel : 2; /* [30:29], r/w, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_config1; + + /* 0x914 : gpadc_reg_config2 */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t gpadc_diff_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t gpadc_vref_sel : 1; /* [ 3], r/w, 0x0 */ + uint32_t gpadc_vbat_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t gpadc_tsext_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t gpadc_ts_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t gpadc_pga_vcm : 2; /* [ 8: 7], r/w, 0x2 */ + uint32_t gpadc_pga_os_cal : 4; /* [12: 9], r/w, 0x8 */ + uint32_t gpadc_pga_en : 1; /* [ 13], r/w, 0x0 */ + uint32_t gpadc_pga_vcmi_en : 1; /* [ 14], r/w, 0x0 */ + uint32_t gpadc_chop_mode : 2; /* [16:15], r/w, 0x3 */ + uint32_t gpadc_bias_sel : 1; /* [ 17], r/w, 0x0 */ + uint32_t gpadc_test_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t gpadc_test_sel : 3; /* [21:19], r/w, 0x0 */ + uint32_t gpadc_pga2_gain : 3; /* [24:22], r/w, 0x0 */ + uint32_t gpadc_pga1_gain : 3; /* [27:25], r/w, 0x0 */ + uint32_t gpadc_dly_sel : 3; /* [30:28], r/w, 0x0 */ + uint32_t gpadc_tsvbe_low : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_config2; + + /* 0x918 : adc converation sequence 1 */ + union { + struct + { + uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_pos_2 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_pos_3 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_pos_4 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_pos_5 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_pos1; + + /* 0x91C : adc converation sequence 2 */ + union { + struct + { + uint32_t gpadc_scan_pos_6 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_pos_7 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_pos_8 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_pos_9 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_pos_10 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_pos_11 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_pos2; + + /* 0x920 : adc converation sequence 3 */ + union { + struct + { + uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_neg_2 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_neg_3 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_neg_4 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_neg_5 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_neg1; + + /* 0x924 : adc converation sequence 4 */ + union { + struct + { + uint32_t gpadc_scan_neg_6 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_neg_7 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_neg_8 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_neg_9 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_neg_10 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_neg_11 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_neg2; + + /* 0x928 : gpadc_reg_status */ + union { + struct + { + uint32_t gpadc_data_rdy : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ + uint32_t gpadc_reserved : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_status; + + /* 0x92C : gpadc_reg_isr */ + union { + struct + { + uint32_t gpadc_neg_satur : 1; /* [ 0], r, 0x0 */ + uint32_t gpadc_pos_satur : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t gpadc_neg_satur_clr : 1; /* [ 4], r/w, 0x0 */ + uint32_t gpadc_pos_satur_clr : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t gpadc_neg_satur_mask : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpadc_pos_satur_mask : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_isr; + + /* 0x930 : gpadc_reg_result */ + union { + struct + { + uint32_t gpadc_data_out : 26; /* [25: 0], r, 0x1ef0000 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_result; + + /* 0x934 : gpadc_reg_raw_result */ + union { + struct + { + uint32_t gpadc_raw_data : 12; /* [11: 0], r, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_raw_result; + + /* 0x938 : gpadc_reg_define */ + union { + struct + { + uint32_t gpadc_os_cal_data : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_define; + + /* 0x93C : hbncore_resv0 */ + union { + struct + { + uint32_t hbncore_resv0_data : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } hbncore_resv0; + + /* 0x940 : hbncore_resv1 */ + union { + struct + { + uint32_t hbncore_resv1_data : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } hbncore_resv1; +}; + +typedef volatile struct aon_reg aon_reg_t; + +#endif /* __AON_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/bl702.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/bl702.h new file mode 100644 index 0000000000000000000000000000000000000000..77bf7736c8ce52c64420d41679a8838d4859a398 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/bl702.h @@ -0,0 +1,324 @@ +#ifndef __BL702_H__ +#define __BL702_H__ + +/* This file had been modified, add USB_IRQn=43 for temp test, the irq value 43 should be checked after all. */ + +/** @addtogroup Configuration_section_for_RISCV + * @{ + */ + +/** + * @brief Configuration of the Processor and Core Peripherals + */ + +/* fix 57.6M */ +#define SystemCoreClockSet(val) \ + if (val == 57 * 6000 * 1000) { \ + BL_WR_WORD(0x4000F108, 57.6 * 1000 * 1000); \ + } else { \ + BL_WR_WORD(0x4000F108, val); \ + } +#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108) + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +#ifdef ARCH_ARM +#define IRQ_NUM_BASE 0 +#endif + +#ifdef ARCH_RISCV +#define IRQ_NUM_BASE 16 +#endif +/** + * @brief BL702 Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum { +#ifdef ARCH_ARM + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +#endif +#ifdef ARCH_RISCV + MSOFT_IRQn = 3, /*!< 3 RISCV machine software Interrupt */ + MTIME_IRQn = 7, /*!< 7 RISCV machine time Interrupt */ + MEXT_IRQn = 11, /*!< 11 RISCV external Interrupt */ + CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending Interrupt */ +#endif + /****** BL702 specific Interrupt Numbers **********************************************************************/ + BMX_ERR_IRQn = IRQ_NUM_BASE + 0, /*!< BMX Error Interrupt */ + BMX_TO_IRQn = IRQ_NUM_BASE + 1, /*!< BMX Timeout Interrupt */ + L1C_BMX_ERR_IRQn = IRQ_NUM_BASE + 2, /*!< L1C BMX Error Interrupt */ + L1C_BMX_TO_IRQn = IRQ_NUM_BASE + 3, /*!< L1C BMX Timeout Interrupt */ + SEC_BMX_ERR_IRQn = IRQ_NUM_BASE + 4, /*!< SEC BMX Error Interrupt */ + RF_TOP_INT0_IRQn = IRQ_NUM_BASE + 5, /*!< RF_TOP_INT0 Interrupt */ + RF_TOP_INT1_IRQn = IRQ_NUM_BASE + 6, /*!< RF_TOP_INT1 Interrupt */ + RESERVED0 = IRQ_NUM_BASE + 7, /*!< RESERVED Interrupt */ + DMA_BMX_ERR_IRQn = IRQ_NUM_BASE + 8, /*!< DMA BMX Error Interrupt */ + SEC_GMAC_IRQn = IRQ_NUM_BASE + 9, /*!< SEC_ENG_GMAC_INT Interrupt */ + SEC_CDET_IRQn = IRQ_NUM_BASE + 10, /*!< SEC_ENG_CDET_INT Interrupt */ + SEC_PKA_IRQn = IRQ_NUM_BASE + 11, /*!< SEC_ENG_PKA_INT Interrupt */ + SEC_TRNG_IRQn = IRQ_NUM_BASE + 12, /*!< SEC_ENG_TRNG_INT Interrupt */ + SEC_AES_IRQn = IRQ_NUM_BASE + 13, /*!< SEC_ENG_AES_INT Interrupt */ + SEC_SHA_IRQn = IRQ_NUM_BASE + 14, /*!< SEC_ENG_SHA_INT Interrupt */ + DMA_ALL_IRQn = IRQ_NUM_BASE + 15, /*!< DMA ALL Interrupt */ + MJPEG_IRQn = IRQ_NUM_BASE + 16, /*!< MJPEG Interrupt */ + CAM_IRQn = IRQ_NUM_BASE + 17, /*!< CAM Interrupt */ + I2S_IRQn = IRQ_NUM_BASE + 18, /*!< I2S Interrupt */ + IRTX_IRQn = IRQ_NUM_BASE + 19, /*!< IR TX Interrupt */ + IRRX_IRQn = IRQ_NUM_BASE + 20, /*!< IR RX Interrupt */ + USB_IRQn = IRQ_NUM_BASE + 21, /*!< USB Interrupt */ + EMAC_IRQn = IRQ_NUM_BASE + 22, /*!< EMAC Interrupt */ + SF_CTRL_IRQn = IRQ_NUM_BASE + 23, /*!< SF_CTRL Interrupt */ + RESERVED1 = IRQ_NUM_BASE + 24, /*!< RESERVED Interrupt */ + GPADC_DMA_IRQn = IRQ_NUM_BASE + 25, /*!< GPADC_DMA Interrupt */ + EFUSE_IRQn = IRQ_NUM_BASE + 26, /*!< Efuse Interrupt */ + SPI_IRQn = IRQ_NUM_BASE + 27, /*!< SPI Interrupt */ + RESERVED2 = IRQ_NUM_BASE + 28, /*!< RESERVED Interrupt */ + UART0_IRQn = IRQ_NUM_BASE + 29, /*!< UART Interrupt */ + UART1_IRQn = IRQ_NUM_BASE + 30, /*!< UART1 Interrupt */ + RESERVED3 = IRQ_NUM_BASE + 31, /*!< RESERVED Interrupt */ + I2C_IRQn = IRQ_NUM_BASE + 32, /*!< I2C Interrupt */ + RESERVED4 = IRQ_NUM_BASE + 33, /*!< RESERVED Interrupt */ + PWM_IRQn = IRQ_NUM_BASE + 34, /*!< PWM Interrupt */ + RESERVED5 = IRQ_NUM_BASE + 35, /*!< RESERVED Interrupt */ + TIMER_CH0_IRQn = IRQ_NUM_BASE + 36, /*!< Timer Channel 0 Interrupt */ + TIMER_CH1_IRQn = IRQ_NUM_BASE + 37, /*!< Timer Channel 1 Interrupt */ + TIMER_WDT_IRQn = IRQ_NUM_BASE + 38, /*!< Timer Watch Dog Interrupt */ + KYS_IRQn = IRQ_NUM_BASE + 39, /*!< KYS Interrupt */ + QDEC0_IRQn = IRQ_NUM_BASE + 40, /*!< QDEC0 Interrupt */ + QDEC1_IRQn = IRQ_NUM_BASE + 41, /*!< QDEC1 Interrupt */ + QDEC2_IRQn = IRQ_NUM_BASE + 42, /*!< QDEC2 Interrupt */ + RESERVED6 = IRQ_NUM_BASE + 43, /*!< RESERVED Interrupt */ + GPIO_INT0_IRQn = IRQ_NUM_BASE + 44, /*!< GPIO_INT0 Interrupt */ + TOUCH_IRQn = IRQ_NUM_BASE + 45, /*!< TOUCH Interrupt */ + RESERVED7 = IRQ_NUM_BASE + 46, /*!< RESERVED Interrupt */ + M154_REQ_ENH_ACK_IRQn = IRQ_NUM_BASE + 47, /*!< M154_REQ Interrupt */ + M154_IRQn = IRQ_NUM_BASE + 48, /*!< M154 Interrupt */ + M154_AES_IRQn = IRQ_NUM_BASE + 49, /*!< M154_AES Interrupt */ + PDS_WAKEUP_IRQn = IRQ_NUM_BASE + 50, /*!< PDS Wakeup Interrupt */ + HBN_OUT0_IRQn = IRQ_NUM_BASE + 51, /*!< Hibernate out 0 Interrupt */ + HBN_OUT1_IRQn = IRQ_NUM_BASE + 52, /*!< Hibernate out 1 Interrupt */ + BOR_IRQn = IRQ_NUM_BASE + 53, /*!< BOR Interrupt */ + WIFI_IRQn = IRQ_NUM_BASE + 54, /*!< WIFI To CPU Interrupt */ + BZ_PHY_IRQn = IRQ_NUM_BASE + 55, /*!< BZ_PHY Interrupt */ + BLE_IRQn = IRQ_NUM_BASE + 56, /*!< BLE Interrupt */ + MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE + 57, /*!< mac_int_tx_rx_timer Interrupt */ + MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE + 58, /*!< mac_int_tx_rx_misc Interrupt */ + MAC_RX_TRG_IRQn = IRQ_NUM_BASE + 59, /*!< mac_int_rx_trigger Interrupt */ + MAC_TX_TRG_IRQn = IRQ_NUM_BASE + 60, /*!< mac_int_tx_trigger Interrupt */ + MAC_GEN_IRQn = IRQ_NUM_BASE + 61, /*!< mac_int_gen Interrupt */ + MAC_PORT_TRG_IRQn = IRQ_NUM_BASE + 62, /*!< mac_int_port_trigger Interrupt */ + WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE + 63, /*!< wifi IPC public Interrupt */ + IRQn_LAST, +} IRQn_Type; + +/** + * @brief BL702 Memory Map Definitions + */ +#define BL702_FLASH_XIP_BASE 0x23000000 +#define BL702_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) +#define BL702_FLASH_XIP_REMAP0_BASE 0x33000000 +#define BL702_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024) +#define BL702_FLASH_XIP_REMAP1_BASE 0x43000000 +#define BL702_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024) +#define BL702_FLASH_XIP_REMAP2_BASE 0x53000000 +#define BL702_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024) + +#define BL702_PSRAM_XIP_BASE 0x24000000 +#define BL702_PSRAM_XIP_END (0x24000000 + 16 * 1024 * 1024) +#define BL702_PSRAM_XIP_REMAP0_BASE 0x34000000 +#define BL702_PSRAM_XIP_REMAP0_END (0x34000000 + 16 * 1024 * 1024) +#define BL702_PSRAM_XIP_REMAP1_BASE 0x44000000 +#define BL702_PSRAM_XIP_REMAP1_END (0x44000000 + 16 * 1024 * 1024) +#define BL702_PSRAM_XIP_REMAP2_BASE 0x54000000 +#define BL702_PSRAM_XIP_REMAP2_END (0x54000000 + 16 * 1024 * 1024) + +#define BL702_WRAM_BASE 0x42020000 +#define BL702_WRAM_END (0x42020000 + 56 * 1024) +#define BL702_WRAM_REMAP0_BASE 0x22020000 +#define BL702_WRAM_REMAP0_END (0x22020000 + 56 * 1024) +#define BL702_WRAM_REMAP1_BASE 0x32020000 +#define BL702_WRAM_REMAP1_END (0x32020000 + 56 * 1024) +#define BL702_WRAM_REMAP2_BASE 0x52020000 +#define BL702_WRAM_REMAP2_END (0x52020000 + 56 * 1024) + +#define BL702_TCM_BASE 0x22010000 +#define BL702_TCM_END (0x22010000 + (16 + 48) * 1024) +#define BL702_TCM_REMAP0_BASE 0x32010000 +#define BL702_TCM_REMAP0_END (0x32010000 + (16 + 48) * 1024) +#define BL702_TCM_REMAP1_BASE 0x42010000 +#define BL702_TCM_REMAP1_END (0x42010000 + (16 + 48) * 1024) +#define BL702_TCM_REMAP2_BASE 0x52010000 +#define BL702_TCM_REMAP2_END (0x52010000 + (16 + 48) * 1024) +/*@} end of group Memory_Map_Section */ + +/* BL702 peripherals base address */ +#define GLB_BASE ((uint32_t)0x40000000) +#define RF_BASE ((uint32_t)0x40001000) +#define BZ_PHY_BASE ((uint32_t)0x40001000) +#define BZ_PHY_AGC_BASE ((uint32_t)0x40001000) +#define GPIP_BASE ((uint32_t)0x40002000) /*!< AUX module base address */ +#define SEC_DBG_BASE ((uint32_t)0x40003000) /*!< Security Debug module base address */ +#define SEC_ENG_BASE ((uint32_t)0x40004000) /*!< Security Engine module base address */ +#define TZC_SEC_BASE ((uint32_t)0x40005000) /*!< Trustzone control security base address */ +#define TZC_NSEC_BASE ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */ +#define EF_DATA_BASE ((uint32_t)0x40007000) +#define EF_CTRL_BASE ((uint32_t)0x40007000) +#define CCI_BASE ((uint32_t)0x40008000) +#define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ +#define UART0_BASE ((uint32_t)0x4000A000) +#define UART1_BASE ((uint32_t)0x4000A100) +#define SPI_BASE ((uint32_t)0x4000A200) +#define I2C_BASE ((uint32_t)0x4000A300) +#define PWM_BASE ((uint32_t)0x4000A400) +#define TIMER_BASE ((uint32_t)0x4000A500) +#define IR_BASE ((uint32_t)0x4000A600) +#define CKS_BASE ((uint32_t)0x4000A700) +#define QDEC0_BASE ((uint32_t)0x4000A800) +#define QDEC1_BASE ((uint32_t)0x4000A840) +#define QDEC2_BASE ((uint32_t)0x4000A880) +#define KYS_BASE ((uint32_t)0x4000A900) +#define I2S_BASE ((uint32_t)0x4000AA00) +#define CAM_BASE ((uint32_t)0x4000AD00) +#define MJPEG_BASE ((uint32_t)0x4000AE00) +#define SF_CTRL_BASE ((uint32_t)0x4000B000) +#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700) +#define DMA_BASE ((uint32_t)0x4000C000) +#define EMAC_BASE ((uint32_t)0x4000D000) +#define USB_BASE ((uint32_t)0x4000D800) +#define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ +#define HBN_BASE ((uint32_t)0x4000F000) /*!< Hibernate module base address */ +#define AON_BASE ((uint32_t)0x4000F000) /*!< Always on module base address */ +#define MAC154_BASE ((uint32_t)0x4C000000) /*!< MAC154 module base address */ + +#define HBN_RAM_BASE ((uint32_t)0x40010000) + +typedef enum { + BL_AHB_SLAVE1_GLB = 0x00, + BL_AHB_SLAVE1_MIX = 0x01, + BL_AHB_SLAVE1_GPIP = 0x02, + BL_AHB_SLAVE1_SEC_DBG = 0x03, + BL_AHB_SLAVE1_SEC = 0x04, + BL_AHB_SLAVE1_TZ1 = 0x05, + BL_AHB_SLAVE1_TZ2 = 0x06, + BL_AHB_SLAVE1_EFUSE = 0x07, + BL_AHB_SLAVE1_CCI = 0x08, + BL_AHB_SLAVE1_L1C = 0x09, + BL_AHB_SLAVE1_S1A_ALL = 0x0A, + BL_AHB_SLAVE1_SFC = 0x0B, + BL_AHB_SLAVE1_DMA = 0x0C, + BL_AHB_SLAVE1_EMAC = 0x0D, + BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E, + BL_AHB_SLAVE1_RSVD0F = 0x0F, + BL_AHB_SLAVE1_UART0 = 0x10, + BL_AHB_SLAVE1_UART1 = 0x11, + BL_AHB_SLAVE1_SPI = 0x12, + BL_AHB_SLAVE1_I2C = 0x13, + BL_AHB_SLAVE1_PWM = 0x14, + BL_AHB_SLAVE1_TMR = 0x15, + BL_AHB_SLAVE1_IRR = 0x16, + BL_AHB_SLAVE1_CKS = 0x17, + BL_AHB_SLAVE1_QDEC = 0x18, + BL_AHB_SLAVE1_KYS = 0x19, + BL_AHB_SLAVE1_I2S = 0x1A, + BL_AHB_SLAVE1_RSVD1B = 0x1B, + BL_AHB_SLAVE1_USB = 0x1C, + BL_AHB_SLAVE1_CAM = 0x1D, + BL_AHB_SLAVE1_MJPEG = 0x1E, + BL_AHB_SLAVE1_MAX = 0x1F, +} BL_AHB_Slave1_Type; + +typedef enum { + BL_AHB_SEC_ENG_AES0 = 0, + BL_AHB_SEC_ENG_AES1, + BL_AHB_SEC_ENG_SHA0, + BL_AHB_SEC_ENG_SHA1, +} BL_AHB_Sec_Eng_Type; + +typedef enum { + BL_AHB_DMA0_CH0 = 0, + BL_AHB_DMA0_CH1, + BL_AHB_DMA0_CH2, + BL_AHB_DMA0_CH3, + BL_AHB_DMA0_CH4, + BL_AHB_DMA0_CH5, + BL_AHB_DMA0_CH6, + BL_AHB_DMA0_CH7, +} BL_AHB_DMA0_CHNL_Type; + +typedef enum { + BL_AHB_SLAVE2_WIFI_CFG = 0, + BL_AHB_SLAVE2_MAX, +} BL_AHB_Slave2_Type; + +typedef enum { + BL_AHB_SLAVE3_BLE = 0, + BL_AHB_SLAVE3_MAX, +} BL_AHB_Slave3_Type; + +typedef enum { + BL_CORE_MASTER_IBUS_CPU = 0, + BL_CORE_MASTER_DBUS_CPU, + BL_CORE_MASTER_BUS_S2F, + BL_CORE_MASTER_MAX, +} BL_Core_Master_Type; + +typedef enum { + BL_CORE_SLAVE0_DTCM_CPU = 0, + BL_CORE_SLAVE0_MAX, +} BL_Core_Slave0_Type; + +typedef enum { + BL_CORE_SLAVE1_XIP_CPU = 0, + BL_CORE_SLAVE1_ITCM_CPU, + BL_CORE_SLAVE1_ROM, + BL_CORE_SLAVE1_MAX, +} BL_Core_Slave1_Type; + +typedef enum { + BL_CORE_SLAVE2_F2S = 0, + BL_CORE_SLAVE2_MAX, +} BL_Core_Slave2_Type; + +/** + * @} + */ +#include +#include +/* ARM CPU include files */ +#ifdef ARCH_ARM +#ifdef CPU_AP_CM4 +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#endif +#ifdef CPU_NP_CM0 +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#endif +#endif +/* RISCV CPU include files */ +#ifdef ARCH_RISCV +#ifdef __GNUC__ +#include "cmsis_compatible_gcc.h" +#include "clic.h" +#include "riscv_encoding.h" +#endif +#endif + +/** + * @} + */ + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/bl70x_reg.svc b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/bl70x_reg.svc new file mode 100644 index 0000000000000000000000000000000000000000..1c6009c16455a231d35e9aff2bd22b3cf321ab25 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/bl70x_reg.svc @@ -0,0 +1,4968 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cam_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cam_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..92613df8095946149bf4cb3ef6b0da3c3cd3d9fb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cam_reg.h @@ -0,0 +1,1203 @@ +/** + ****************************************************************************** + * @file cam_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __CAM_REG_H__ +#define __CAM_REG_H__ + +#include "bl702.h" + +/* 0x0 : dvp2axi_configue */ +#define CAM_DVP2AXI_CONFIGUE_OFFSET (0x0) +#define CAM_REG_DVP_ENABLE CAM_REG_DVP_ENABLE +#define CAM_REG_DVP_ENABLE_POS (0U) +#define CAM_REG_DVP_ENABLE_LEN (1U) +#define CAM_REG_DVP_ENABLE_MSK (((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS) +#define CAM_REG_DVP_ENABLE_UMSK (~(((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS)) +#define CAM_REG_SW_MODE CAM_REG_SW_MODE +#define CAM_REG_SW_MODE_POS (1U) +#define CAM_REG_SW_MODE_LEN (1U) +#define CAM_REG_SW_MODE_MSK (((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS) +#define CAM_REG_SW_MODE_UMSK (~(((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS)) +#define CAM_REG_FRAM_VLD_POL CAM_REG_FRAM_VLD_POL +#define CAM_REG_FRAM_VLD_POL_POS (2U) +#define CAM_REG_FRAM_VLD_POL_LEN (1U) +#define CAM_REG_FRAM_VLD_POL_MSK (((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS) +#define CAM_REG_FRAM_VLD_POL_UMSK (~(((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS)) +#define CAM_REG_LINE_VLD_POL CAM_REG_LINE_VLD_POL +#define CAM_REG_LINE_VLD_POL_POS (3U) +#define CAM_REG_LINE_VLD_POL_LEN (1U) +#define CAM_REG_LINE_VLD_POL_MSK (((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS) +#define CAM_REG_LINE_VLD_POL_UMSK (~(((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS)) +#define CAM_REG_HBURST CAM_REG_HBURST +#define CAM_REG_HBURST_POS (4U) +#define CAM_REG_HBURST_LEN (2U) +#define CAM_REG_HBURST_MSK (((1U << CAM_REG_HBURST_LEN) - 1) << CAM_REG_HBURST_POS) +#define CAM_REG_HBURST_UMSK (~(((1U << CAM_REG_HBURST_LEN) - 1) << CAM_REG_HBURST_POS)) +#define CAM_REG_DVP_MODE CAM_REG_DVP_MODE +#define CAM_REG_DVP_MODE_POS (8U) +#define CAM_REG_DVP_MODE_LEN (3U) +#define CAM_REG_DVP_MODE_MSK (((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS) +#define CAM_REG_DVP_MODE_UMSK (~(((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS)) +#define CAM_REG_HW_MODE_FWRAP CAM_REG_HW_MODE_FWRAP +#define CAM_REG_HW_MODE_FWRAP_POS (11U) +#define CAM_REG_HW_MODE_FWRAP_LEN (1U) +#define CAM_REG_HW_MODE_FWRAP_MSK (((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS) +#define CAM_REG_HW_MODE_FWRAP_UMSK (~(((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS)) +#define CAM_REG_DROP_EN CAM_REG_DROP_EN +#define CAM_REG_DROP_EN_POS (12U) +#define CAM_REG_DROP_EN_LEN (1U) +#define CAM_REG_DROP_EN_MSK (((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS) +#define CAM_REG_DROP_EN_UMSK (~(((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS)) +#define CAM_REG_DROP_EVEN CAM_REG_DROP_EVEN +#define CAM_REG_DROP_EVEN_POS (13U) +#define CAM_REG_DROP_EVEN_LEN (1U) +#define CAM_REG_DROP_EVEN_MSK (((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS) +#define CAM_REG_DROP_EVEN_UMSK (~(((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS)) +#define CAM_REG_SUBSAMPLE_EN CAM_REG_SUBSAMPLE_EN +#define CAM_REG_SUBSAMPLE_EN_POS (14U) +#define CAM_REG_SUBSAMPLE_EN_LEN (1U) +#define CAM_REG_SUBSAMPLE_EN_MSK (((1U << CAM_REG_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_SUBSAMPLE_EN_POS) +#define CAM_REG_SUBSAMPLE_EN_UMSK (~(((1U << CAM_REG_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_SUBSAMPLE_EN_POS)) +#define CAM_REG_SUBSAMPLE_EVEN CAM_REG_SUBSAMPLE_EVEN +#define CAM_REG_SUBSAMPLE_EVEN_POS (15U) +#define CAM_REG_SUBSAMPLE_EVEN_LEN (1U) +#define CAM_REG_SUBSAMPLE_EVEN_MSK (((1U << CAM_REG_SUBSAMPLE_EVEN_LEN) - 1) << CAM_REG_SUBSAMPLE_EVEN_POS) +#define CAM_REG_SUBSAMPLE_EVEN_UMSK (~(((1U << CAM_REG_SUBSAMPLE_EVEN_LEN) - 1) << CAM_REG_SUBSAMPLE_EVEN_POS)) +#define CAM_REG_INTERLV_MODE CAM_REG_INTERLV_MODE +#define CAM_REG_INTERLV_MODE_POS (16U) +#define CAM_REG_INTERLV_MODE_LEN (1U) +#define CAM_REG_INTERLV_MODE_MSK (((1U << CAM_REG_INTERLV_MODE_LEN) - 1) << CAM_REG_INTERLV_MODE_POS) +#define CAM_REG_INTERLV_MODE_UMSK (~(((1U << CAM_REG_INTERLV_MODE_LEN) - 1) << CAM_REG_INTERLV_MODE_POS)) +#define CAM_REG_DVP_PIX_CLK_CG CAM_REG_DVP_PIX_CLK_CG +#define CAM_REG_DVP_PIX_CLK_CG_POS (20U) +#define CAM_REG_DVP_PIX_CLK_CG_LEN (1U) +#define CAM_REG_DVP_PIX_CLK_CG_MSK (((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS) +#define CAM_REG_DVP_PIX_CLK_CG_UMSK (~(((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS)) +#define CAM_REG_DVP_WAIT_CYCLE CAM_REG_DVP_WAIT_CYCLE +#define CAM_REG_DVP_WAIT_CYCLE_POS (24U) +#define CAM_REG_DVP_WAIT_CYCLE_LEN (8U) +#define CAM_REG_DVP_WAIT_CYCLE_MSK (((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS) +#define CAM_REG_DVP_WAIT_CYCLE_UMSK (~(((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS)) + +/* 0x4 : dvp2ahb_addr_start_0 */ +#define CAM_DVP2AHB_ADDR_START_0_OFFSET (0x4) +#define CAM_REG_ADDR_START_0 CAM_REG_ADDR_START_0 +#define CAM_REG_ADDR_START_0_POS (0U) +#define CAM_REG_ADDR_START_0_LEN (32U) +#define CAM_REG_ADDR_START_0_MSK (((1U << CAM_REG_ADDR_START_0_LEN) - 1) << CAM_REG_ADDR_START_0_POS) +#define CAM_REG_ADDR_START_0_UMSK (~(((1U << CAM_REG_ADDR_START_0_LEN) - 1) << CAM_REG_ADDR_START_0_POS)) + +/* 0x8 : dvp2ahb_mem_bcnt_0 */ +#define CAM_DVP2AHB_MEM_BCNT_0_OFFSET (0x8) +#define CAM_REG_MEM_BURST_CNT_0 CAM_REG_MEM_BURST_CNT_0 +#define CAM_REG_MEM_BURST_CNT_0_POS (0U) +#define CAM_REG_MEM_BURST_CNT_0_LEN (32U) +#define CAM_REG_MEM_BURST_CNT_0_MSK (((1U << CAM_REG_MEM_BURST_CNT_0_LEN) - 1) << CAM_REG_MEM_BURST_CNT_0_POS) +#define CAM_REG_MEM_BURST_CNT_0_UMSK (~(((1U << CAM_REG_MEM_BURST_CNT_0_LEN) - 1) << CAM_REG_MEM_BURST_CNT_0_POS)) + +/* 0xC : dvp2ahb_frame_bcnt_0 */ +#define CAM_DVP2AHB_FRAME_BCNT_0_OFFSET (0xC) +#define CAM_REG_FRAME_BURST_CNT_0 CAM_REG_FRAME_BURST_CNT_0 +#define CAM_REG_FRAME_BURST_CNT_0_POS (0U) +#define CAM_REG_FRAME_BURST_CNT_0_LEN (32U) +#define CAM_REG_FRAME_BURST_CNT_0_MSK (((1U << CAM_REG_FRAME_BURST_CNT_0_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_0_POS) +#define CAM_REG_FRAME_BURST_CNT_0_UMSK (~(((1U << CAM_REG_FRAME_BURST_CNT_0_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_0_POS)) + +/* 0x10 : dvp2ahb_addr_start_1 */ +#define CAM_DVP2AHB_ADDR_START_1_OFFSET (0x10) +#define CAM_REG_ADDR_START_1 CAM_REG_ADDR_START_1 +#define CAM_REG_ADDR_START_1_POS (0U) +#define CAM_REG_ADDR_START_1_LEN (32U) +#define CAM_REG_ADDR_START_1_MSK (((1U << CAM_REG_ADDR_START_1_LEN) - 1) << CAM_REG_ADDR_START_1_POS) +#define CAM_REG_ADDR_START_1_UMSK (~(((1U << CAM_REG_ADDR_START_1_LEN) - 1) << CAM_REG_ADDR_START_1_POS)) + +/* 0x14 : dvp2ahb_mem_bcnt_1 */ +#define CAM_DVP2AHB_MEM_BCNT_1_OFFSET (0x14) +#define CAM_REG_MEM_BURST_CNT_1 CAM_REG_MEM_BURST_CNT_1 +#define CAM_REG_MEM_BURST_CNT_1_POS (0U) +#define CAM_REG_MEM_BURST_CNT_1_LEN (32U) +#define CAM_REG_MEM_BURST_CNT_1_MSK (((1U << CAM_REG_MEM_BURST_CNT_1_LEN) - 1) << CAM_REG_MEM_BURST_CNT_1_POS) +#define CAM_REG_MEM_BURST_CNT_1_UMSK (~(((1U << CAM_REG_MEM_BURST_CNT_1_LEN) - 1) << CAM_REG_MEM_BURST_CNT_1_POS)) + +/* 0x18 : dvp2ahb_frame_bcnt_1 */ +#define CAM_DVP2AHB_FRAME_BCNT_1_OFFSET (0x18) +#define CAM_REG_FRAME_BURST_CNT_1 CAM_REG_FRAME_BURST_CNT_1 +#define CAM_REG_FRAME_BURST_CNT_1_POS (0U) +#define CAM_REG_FRAME_BURST_CNT_1_LEN (32U) +#define CAM_REG_FRAME_BURST_CNT_1_MSK (((1U << CAM_REG_FRAME_BURST_CNT_1_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_1_POS) +#define CAM_REG_FRAME_BURST_CNT_1_UMSK (~(((1U << CAM_REG_FRAME_BURST_CNT_1_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_1_POS)) + +/* 0x1C : dvp_status_and_error */ +#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0x1C) +#define CAM_STS_NORMAL_INT_0 CAM_STS_NORMAL_INT_0 +#define CAM_STS_NORMAL_INT_0_POS (0U) +#define CAM_STS_NORMAL_INT_0_LEN (1U) +#define CAM_STS_NORMAL_INT_0_MSK (((1U << CAM_STS_NORMAL_INT_0_LEN) - 1) << CAM_STS_NORMAL_INT_0_POS) +#define CAM_STS_NORMAL_INT_0_UMSK (~(((1U << CAM_STS_NORMAL_INT_0_LEN) - 1) << CAM_STS_NORMAL_INT_0_POS)) +#define CAM_STS_NORMAL_INT_1 CAM_STS_NORMAL_INT_1 +#define CAM_STS_NORMAL_INT_1_POS (1U) +#define CAM_STS_NORMAL_INT_1_LEN (1U) +#define CAM_STS_NORMAL_INT_1_MSK (((1U << CAM_STS_NORMAL_INT_1_LEN) - 1) << CAM_STS_NORMAL_INT_1_POS) +#define CAM_STS_NORMAL_INT_1_UMSK (~(((1U << CAM_STS_NORMAL_INT_1_LEN) - 1) << CAM_STS_NORMAL_INT_1_POS)) +#define CAM_STS_MEM_INT_0 CAM_STS_MEM_INT_0 +#define CAM_STS_MEM_INT_0_POS (2U) +#define CAM_STS_MEM_INT_0_LEN (1U) +#define CAM_STS_MEM_INT_0_MSK (((1U << CAM_STS_MEM_INT_0_LEN) - 1) << CAM_STS_MEM_INT_0_POS) +#define CAM_STS_MEM_INT_0_UMSK (~(((1U << CAM_STS_MEM_INT_0_LEN) - 1) << CAM_STS_MEM_INT_0_POS)) +#define CAM_STS_MEM_INT_1 CAM_STS_MEM_INT_1 +#define CAM_STS_MEM_INT_1_POS (3U) +#define CAM_STS_MEM_INT_1_LEN (1U) +#define CAM_STS_MEM_INT_1_MSK (((1U << CAM_STS_MEM_INT_1_LEN) - 1) << CAM_STS_MEM_INT_1_POS) +#define CAM_STS_MEM_INT_1_UMSK (~(((1U << CAM_STS_MEM_INT_1_LEN) - 1) << CAM_STS_MEM_INT_1_POS)) +#define CAM_STS_FRAME_INT_0 CAM_STS_FRAME_INT_0 +#define CAM_STS_FRAME_INT_0_POS (4U) +#define CAM_STS_FRAME_INT_0_LEN (1U) +#define CAM_STS_FRAME_INT_0_MSK (((1U << CAM_STS_FRAME_INT_0_LEN) - 1) << CAM_STS_FRAME_INT_0_POS) +#define CAM_STS_FRAME_INT_0_UMSK (~(((1U << CAM_STS_FRAME_INT_0_LEN) - 1) << CAM_STS_FRAME_INT_0_POS)) +#define CAM_STS_FRAME_INT_1 CAM_STS_FRAME_INT_1 +#define CAM_STS_FRAME_INT_1_POS (5U) +#define CAM_STS_FRAME_INT_1_LEN (1U) +#define CAM_STS_FRAME_INT_1_MSK (((1U << CAM_STS_FRAME_INT_1_LEN) - 1) << CAM_STS_FRAME_INT_1_POS) +#define CAM_STS_FRAME_INT_1_UMSK (~(((1U << CAM_STS_FRAME_INT_1_LEN) - 1) << CAM_STS_FRAME_INT_1_POS)) +#define CAM_STS_FIFO_INT_0 CAM_STS_FIFO_INT_0 +#define CAM_STS_FIFO_INT_0_POS (6U) +#define CAM_STS_FIFO_INT_0_LEN (1U) +#define CAM_STS_FIFO_INT_0_MSK (((1U << CAM_STS_FIFO_INT_0_LEN) - 1) << CAM_STS_FIFO_INT_0_POS) +#define CAM_STS_FIFO_INT_0_UMSK (~(((1U << CAM_STS_FIFO_INT_0_LEN) - 1) << CAM_STS_FIFO_INT_0_POS)) +#define CAM_STS_FIFO_INT_1 CAM_STS_FIFO_INT_1 +#define CAM_STS_FIFO_INT_1_POS (7U) +#define CAM_STS_FIFO_INT_1_LEN (1U) +#define CAM_STS_FIFO_INT_1_MSK (((1U << CAM_STS_FIFO_INT_1_LEN) - 1) << CAM_STS_FIFO_INT_1_POS) +#define CAM_STS_FIFO_INT_1_UMSK (~(((1U << CAM_STS_FIFO_INT_1_LEN) - 1) << CAM_STS_FIFO_INT_1_POS)) +#define CAM_STS_HCNT_INT CAM_STS_HCNT_INT +#define CAM_STS_HCNT_INT_POS (8U) +#define CAM_STS_HCNT_INT_LEN (1U) +#define CAM_STS_HCNT_INT_MSK (((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS) +#define CAM_STS_HCNT_INT_UMSK (~(((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS)) +#define CAM_STS_VCNT_INT CAM_STS_VCNT_INT +#define CAM_STS_VCNT_INT_POS (9U) +#define CAM_STS_VCNT_INT_LEN (1U) +#define CAM_STS_VCNT_INT_MSK (((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS) +#define CAM_STS_VCNT_INT_UMSK (~(((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS)) +#define CAM_AHB_IDLE_0 CAM_AHB_IDLE_0 +#define CAM_AHB_IDLE_0_POS (16U) +#define CAM_AHB_IDLE_0_LEN (1U) +#define CAM_AHB_IDLE_0_MSK (((1U << CAM_AHB_IDLE_0_LEN) - 1) << CAM_AHB_IDLE_0_POS) +#define CAM_AHB_IDLE_0_UMSK (~(((1U << CAM_AHB_IDLE_0_LEN) - 1) << CAM_AHB_IDLE_0_POS)) +#define CAM_AHB_IDLE_1 CAM_AHB_IDLE_1 +#define CAM_AHB_IDLE_1_POS (17U) +#define CAM_AHB_IDLE_1_LEN (1U) +#define CAM_AHB_IDLE_1_MSK (((1U << CAM_AHB_IDLE_1_LEN) - 1) << CAM_AHB_IDLE_1_POS) +#define CAM_AHB_IDLE_1_UMSK (~(((1U << CAM_AHB_IDLE_1_LEN) - 1) << CAM_AHB_IDLE_1_POS)) +#define CAM_ST_DVP_IDLE CAM_ST_DVP_IDLE +#define CAM_ST_DVP_IDLE_POS (19U) +#define CAM_ST_DVP_IDLE_LEN (1U) +#define CAM_ST_DVP_IDLE_MSK (((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS) +#define CAM_ST_DVP_IDLE_UMSK (~(((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS)) +#define CAM_FRAME_VALID_CNT_0 CAM_FRAME_VALID_CNT_0 +#define CAM_FRAME_VALID_CNT_0_POS (20U) +#define CAM_FRAME_VALID_CNT_0_LEN (4U) +#define CAM_FRAME_VALID_CNT_0_MSK (((1U << CAM_FRAME_VALID_CNT_0_LEN) - 1) << CAM_FRAME_VALID_CNT_0_POS) +#define CAM_FRAME_VALID_CNT_0_UMSK (~(((1U << CAM_FRAME_VALID_CNT_0_LEN) - 1) << CAM_FRAME_VALID_CNT_0_POS)) +#define CAM_FRAME_VALID_CNT_1 CAM_FRAME_VALID_CNT_1 +#define CAM_FRAME_VALID_CNT_1_POS (24U) +#define CAM_FRAME_VALID_CNT_1_LEN (4U) +#define CAM_FRAME_VALID_CNT_1_MSK (((1U << CAM_FRAME_VALID_CNT_1_LEN) - 1) << CAM_FRAME_VALID_CNT_1_POS) +#define CAM_FRAME_VALID_CNT_1_UMSK (~(((1U << CAM_FRAME_VALID_CNT_1_LEN) - 1) << CAM_FRAME_VALID_CNT_1_POS)) +#define CAM_ST_BUS_IDLE CAM_ST_BUS_IDLE +#define CAM_ST_BUS_IDLE_POS (28U) +#define CAM_ST_BUS_IDLE_LEN (1U) +#define CAM_ST_BUS_IDLE_MSK (((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS) +#define CAM_ST_BUS_IDLE_UMSK (~(((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS)) +#define CAM_ST_BUS_FUNC CAM_ST_BUS_FUNC +#define CAM_ST_BUS_FUNC_POS (29U) +#define CAM_ST_BUS_FUNC_LEN (1U) +#define CAM_ST_BUS_FUNC_MSK (((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS) +#define CAM_ST_BUS_FUNC_UMSK (~(((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS)) +#define CAM_ST_BUS_WAIT CAM_ST_BUS_WAIT +#define CAM_ST_BUS_WAIT_POS (30U) +#define CAM_ST_BUS_WAIT_LEN (1U) +#define CAM_ST_BUS_WAIT_MSK (((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS) +#define CAM_ST_BUS_WAIT_UMSK (~(((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS)) +#define CAM_ST_BUS_FLSH CAM_ST_BUS_FLSH +#define CAM_ST_BUS_FLSH_POS (31U) +#define CAM_ST_BUS_FLSH_LEN (1U) +#define CAM_ST_BUS_FLSH_MSK (((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS) +#define CAM_ST_BUS_FLSH_UMSK (~(((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS)) + +/* 0x20 : dvp_frame_fifo_pop */ +#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x20) +#define CAM_RFIFO_POP_0 CAM_RFIFO_POP_0 +#define CAM_RFIFO_POP_0_POS (0U) +#define CAM_RFIFO_POP_0_LEN (1U) +#define CAM_RFIFO_POP_0_MSK (((1U << CAM_RFIFO_POP_0_LEN) - 1) << CAM_RFIFO_POP_0_POS) +#define CAM_RFIFO_POP_0_UMSK (~(((1U << CAM_RFIFO_POP_0_LEN) - 1) << CAM_RFIFO_POP_0_POS)) +#define CAM_RFIFO_POP_1 CAM_RFIFO_POP_1 +#define CAM_RFIFO_POP_1_POS (1U) +#define CAM_RFIFO_POP_1_LEN (1U) +#define CAM_RFIFO_POP_1_MSK (((1U << CAM_RFIFO_POP_1_LEN) - 1) << CAM_RFIFO_POP_1_POS) +#define CAM_RFIFO_POP_1_UMSK (~(((1U << CAM_RFIFO_POP_1_LEN) - 1) << CAM_RFIFO_POP_1_POS)) +#define CAM_REG_INT_NORMAL_CLR_0 CAM_REG_INT_NORMAL_CLR_0 +#define CAM_REG_INT_NORMAL_CLR_0_POS (4U) +#define CAM_REG_INT_NORMAL_CLR_0_LEN (1U) +#define CAM_REG_INT_NORMAL_CLR_0_MSK (((1U << CAM_REG_INT_NORMAL_CLR_0_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_0_POS) +#define CAM_REG_INT_NORMAL_CLR_0_UMSK (~(((1U << CAM_REG_INT_NORMAL_CLR_0_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_0_POS)) +#define CAM_REG_INT_MEM_CLR_0 CAM_REG_INT_MEM_CLR_0 +#define CAM_REG_INT_MEM_CLR_0_POS (5U) +#define CAM_REG_INT_MEM_CLR_0_LEN (1U) +#define CAM_REG_INT_MEM_CLR_0_MSK (((1U << CAM_REG_INT_MEM_CLR_0_LEN) - 1) << CAM_REG_INT_MEM_CLR_0_POS) +#define CAM_REG_INT_MEM_CLR_0_UMSK (~(((1U << CAM_REG_INT_MEM_CLR_0_LEN) - 1) << CAM_REG_INT_MEM_CLR_0_POS)) +#define CAM_REG_INT_FRAME_CLR_0 CAM_REG_INT_FRAME_CLR_0 +#define CAM_REG_INT_FRAME_CLR_0_POS (6U) +#define CAM_REG_INT_FRAME_CLR_0_LEN (1U) +#define CAM_REG_INT_FRAME_CLR_0_MSK (((1U << CAM_REG_INT_FRAME_CLR_0_LEN) - 1) << CAM_REG_INT_FRAME_CLR_0_POS) +#define CAM_REG_INT_FRAME_CLR_0_UMSK (~(((1U << CAM_REG_INT_FRAME_CLR_0_LEN) - 1) << CAM_REG_INT_FRAME_CLR_0_POS)) +#define CAM_REG_INT_FIFO_CLR_0 CAM_REG_INT_FIFO_CLR_0 +#define CAM_REG_INT_FIFO_CLR_0_POS (7U) +#define CAM_REG_INT_FIFO_CLR_0_LEN (1U) +#define CAM_REG_INT_FIFO_CLR_0_MSK (((1U << CAM_REG_INT_FIFO_CLR_0_LEN) - 1) << CAM_REG_INT_FIFO_CLR_0_POS) +#define CAM_REG_INT_FIFO_CLR_0_UMSK (~(((1U << CAM_REG_INT_FIFO_CLR_0_LEN) - 1) << CAM_REG_INT_FIFO_CLR_0_POS)) +#define CAM_REG_INT_HCNT_CLR_0 CAM_REG_INT_HCNT_CLR_0 +#define CAM_REG_INT_HCNT_CLR_0_POS (8U) +#define CAM_REG_INT_HCNT_CLR_0_LEN (1U) +#define CAM_REG_INT_HCNT_CLR_0_MSK (((1U << CAM_REG_INT_HCNT_CLR_0_LEN) - 1) << CAM_REG_INT_HCNT_CLR_0_POS) +#define CAM_REG_INT_HCNT_CLR_0_UMSK (~(((1U << CAM_REG_INT_HCNT_CLR_0_LEN) - 1) << CAM_REG_INT_HCNT_CLR_0_POS)) +#define CAM_REG_INT_VCNT_CLR_0 CAM_REG_INT_VCNT_CLR_0 +#define CAM_REG_INT_VCNT_CLR_0_POS (9U) +#define CAM_REG_INT_VCNT_CLR_0_LEN (1U) +#define CAM_REG_INT_VCNT_CLR_0_MSK (((1U << CAM_REG_INT_VCNT_CLR_0_LEN) - 1) << CAM_REG_INT_VCNT_CLR_0_POS) +#define CAM_REG_INT_VCNT_CLR_0_UMSK (~(((1U << CAM_REG_INT_VCNT_CLR_0_LEN) - 1) << CAM_REG_INT_VCNT_CLR_0_POS)) +#define CAM_REG_INT_NORMAL_CLR_1 CAM_REG_INT_NORMAL_CLR_1 +#define CAM_REG_INT_NORMAL_CLR_1_POS (16U) +#define CAM_REG_INT_NORMAL_CLR_1_LEN (1U) +#define CAM_REG_INT_NORMAL_CLR_1_MSK (((1U << CAM_REG_INT_NORMAL_CLR_1_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_1_POS) +#define CAM_REG_INT_NORMAL_CLR_1_UMSK (~(((1U << CAM_REG_INT_NORMAL_CLR_1_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_1_POS)) +#define CAM_REG_INT_MEM_CLR_1 CAM_REG_INT_MEM_CLR_1 +#define CAM_REG_INT_MEM_CLR_1_POS (17U) +#define CAM_REG_INT_MEM_CLR_1_LEN (1U) +#define CAM_REG_INT_MEM_CLR_1_MSK (((1U << CAM_REG_INT_MEM_CLR_1_LEN) - 1) << CAM_REG_INT_MEM_CLR_1_POS) +#define CAM_REG_INT_MEM_CLR_1_UMSK (~(((1U << CAM_REG_INT_MEM_CLR_1_LEN) - 1) << CAM_REG_INT_MEM_CLR_1_POS)) +#define CAM_REG_INT_FRAME_CLR_1 CAM_REG_INT_FRAME_CLR_1 +#define CAM_REG_INT_FRAME_CLR_1_POS (18U) +#define CAM_REG_INT_FRAME_CLR_1_LEN (1U) +#define CAM_REG_INT_FRAME_CLR_1_MSK (((1U << CAM_REG_INT_FRAME_CLR_1_LEN) - 1) << CAM_REG_INT_FRAME_CLR_1_POS) +#define CAM_REG_INT_FRAME_CLR_1_UMSK (~(((1U << CAM_REG_INT_FRAME_CLR_1_LEN) - 1) << CAM_REG_INT_FRAME_CLR_1_POS)) +#define CAM_REG_INT_FIFO_CLR_1 CAM_REG_INT_FIFO_CLR_1 +#define CAM_REG_INT_FIFO_CLR_1_POS (19U) +#define CAM_REG_INT_FIFO_CLR_1_LEN (1U) +#define CAM_REG_INT_FIFO_CLR_1_MSK (((1U << CAM_REG_INT_FIFO_CLR_1_LEN) - 1) << CAM_REG_INT_FIFO_CLR_1_POS) +#define CAM_REG_INT_FIFO_CLR_1_UMSK (~(((1U << CAM_REG_INT_FIFO_CLR_1_LEN) - 1) << CAM_REG_INT_FIFO_CLR_1_POS)) + +/* 0x24 : snsr_control */ +#define CAM_SNSR_CONTROL_OFFSET (0x24) +#define CAM_REG_CAM_RST CAM_REG_CAM_RST +#define CAM_REG_CAM_RST_POS (0U) +#define CAM_REG_CAM_RST_LEN (1U) +#define CAM_REG_CAM_RST_MSK (((1U << CAM_REG_CAM_RST_LEN) - 1) << CAM_REG_CAM_RST_POS) +#define CAM_REG_CAM_RST_UMSK (~(((1U << CAM_REG_CAM_RST_LEN) - 1) << CAM_REG_CAM_RST_POS)) +#define CAM_REG_CAM_PWDN CAM_REG_CAM_PWDN +#define CAM_REG_CAM_PWDN_POS (1U) +#define CAM_REG_CAM_PWDN_LEN (1U) +#define CAM_REG_CAM_PWDN_MSK (((1U << CAM_REG_CAM_PWDN_LEN) - 1) << CAM_REG_CAM_PWDN_POS) +#define CAM_REG_CAM_PWDN_UMSK (~(((1U << CAM_REG_CAM_PWDN_LEN) - 1) << CAM_REG_CAM_PWDN_POS)) + +/* 0x28 : int_control */ +#define CAM_INT_CONTROL_OFFSET (0x28) +#define CAM_REG_INT_NORMAL_0_EN CAM_REG_INT_NORMAL_0_EN +#define CAM_REG_INT_NORMAL_0_EN_POS (0U) +#define CAM_REG_INT_NORMAL_0_EN_LEN (1U) +#define CAM_REG_INT_NORMAL_0_EN_MSK (((1U << CAM_REG_INT_NORMAL_0_EN_LEN) - 1) << CAM_REG_INT_NORMAL_0_EN_POS) +#define CAM_REG_INT_NORMAL_0_EN_UMSK (~(((1U << CAM_REG_INT_NORMAL_0_EN_LEN) - 1) << CAM_REG_INT_NORMAL_0_EN_POS)) +#define CAM_REG_INT_NORMAL_1_EN CAM_REG_INT_NORMAL_1_EN +#define CAM_REG_INT_NORMAL_1_EN_POS (1U) +#define CAM_REG_INT_NORMAL_1_EN_LEN (1U) +#define CAM_REG_INT_NORMAL_1_EN_MSK (((1U << CAM_REG_INT_NORMAL_1_EN_LEN) - 1) << CAM_REG_INT_NORMAL_1_EN_POS) +#define CAM_REG_INT_NORMAL_1_EN_UMSK (~(((1U << CAM_REG_INT_NORMAL_1_EN_LEN) - 1) << CAM_REG_INT_NORMAL_1_EN_POS)) +#define CAM_REG_INT_MEM_EN CAM_REG_INT_MEM_EN +#define CAM_REG_INT_MEM_EN_POS (2U) +#define CAM_REG_INT_MEM_EN_LEN (1U) +#define CAM_REG_INT_MEM_EN_MSK (((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS) +#define CAM_REG_INT_MEM_EN_UMSK (~(((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS)) +#define CAM_REG_INT_FRAME_EN CAM_REG_INT_FRAME_EN +#define CAM_REG_INT_FRAME_EN_POS (3U) +#define CAM_REG_INT_FRAME_EN_LEN (1U) +#define CAM_REG_INT_FRAME_EN_MSK (((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS) +#define CAM_REG_INT_FRAME_EN_UMSK (~(((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS)) +#define CAM_REG_INT_FIFO_EN CAM_REG_INT_FIFO_EN +#define CAM_REG_INT_FIFO_EN_POS (4U) +#define CAM_REG_INT_FIFO_EN_LEN (1U) +#define CAM_REG_INT_FIFO_EN_MSK (((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS) +#define CAM_REG_INT_FIFO_EN_UMSK (~(((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS)) +#define CAM_REG_INT_HCNT_EN CAM_REG_INT_HCNT_EN +#define CAM_REG_INT_HCNT_EN_POS (5U) +#define CAM_REG_INT_HCNT_EN_LEN (1U) +#define CAM_REG_INT_HCNT_EN_MSK (((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS) +#define CAM_REG_INT_HCNT_EN_UMSK (~(((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS)) +#define CAM_REG_INT_VCNT_EN CAM_REG_INT_VCNT_EN +#define CAM_REG_INT_VCNT_EN_POS (6U) +#define CAM_REG_INT_VCNT_EN_LEN (1U) +#define CAM_REG_INT_VCNT_EN_MSK (((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS) +#define CAM_REG_INT_VCNT_EN_UMSK (~(((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS)) +#define CAM_REG_FRAME_CNT_TRGR_INT CAM_REG_FRAME_CNT_TRGR_INT +#define CAM_REG_FRAME_CNT_TRGR_INT_POS (28U) +#define CAM_REG_FRAME_CNT_TRGR_INT_LEN (4U) +#define CAM_REG_FRAME_CNT_TRGR_INT_MSK (((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS) +#define CAM_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS)) + +/* 0x30 : hsync_control */ +#define CAM_HSYNC_CONTROL_OFFSET (0x30) +#define CAM_REG_HSYNC_ACT_END CAM_REG_HSYNC_ACT_END +#define CAM_REG_HSYNC_ACT_END_POS (0U) +#define CAM_REG_HSYNC_ACT_END_LEN (16U) +#define CAM_REG_HSYNC_ACT_END_MSK (((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS) +#define CAM_REG_HSYNC_ACT_END_UMSK (~(((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS)) +#define CAM_REG_HSYNC_ACT_START CAM_REG_HSYNC_ACT_START +#define CAM_REG_HSYNC_ACT_START_POS (16U) +#define CAM_REG_HSYNC_ACT_START_LEN (16U) +#define CAM_REG_HSYNC_ACT_START_MSK (((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS) +#define CAM_REG_HSYNC_ACT_START_UMSK (~(((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS)) + +/* 0x34 : vsync_control */ +#define CAM_VSYNC_CONTROL_OFFSET (0x34) +#define CAM_REG_VSYNC_ACT_END CAM_REG_VSYNC_ACT_END +#define CAM_REG_VSYNC_ACT_END_POS (0U) +#define CAM_REG_VSYNC_ACT_END_LEN (16U) +#define CAM_REG_VSYNC_ACT_END_MSK (((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS) +#define CAM_REG_VSYNC_ACT_END_UMSK (~(((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS)) +#define CAM_REG_VSYNC_ACT_START CAM_REG_VSYNC_ACT_START +#define CAM_REG_VSYNC_ACT_START_POS (16U) +#define CAM_REG_VSYNC_ACT_START_LEN (16U) +#define CAM_REG_VSYNC_ACT_START_MSK (((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS) +#define CAM_REG_VSYNC_ACT_START_UMSK (~(((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS)) + +/* 0x38 : frame_size_control */ +#define CAM_FRAME_SIZE_CONTROL_OFFSET (0x38) +#define CAM_REG_TOTAL_HCNT CAM_REG_TOTAL_HCNT +#define CAM_REG_TOTAL_HCNT_POS (0U) +#define CAM_REG_TOTAL_HCNT_LEN (16U) +#define CAM_REG_TOTAL_HCNT_MSK (((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS) +#define CAM_REG_TOTAL_HCNT_UMSK (~(((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS)) +#define CAM_REG_TOTAL_VCNT CAM_REG_TOTAL_VCNT +#define CAM_REG_TOTAL_VCNT_POS (16U) +#define CAM_REG_TOTAL_VCNT_LEN (16U) +#define CAM_REG_TOTAL_VCNT_MSK (((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS) +#define CAM_REG_TOTAL_VCNT_UMSK (~(((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS)) + +/* 0x40 : frame_start_addr0_0 */ +#define CAM_FRAME_START_ADDR0_0_OFFSET (0x40) +#define CAM_FRAME_START_ADDR_0_0 CAM_FRAME_START_ADDR_0_0 +#define CAM_FRAME_START_ADDR_0_0_POS (0U) +#define CAM_FRAME_START_ADDR_0_0_LEN (32U) +#define CAM_FRAME_START_ADDR_0_0_MSK (((1U << CAM_FRAME_START_ADDR_0_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_0_POS) +#define CAM_FRAME_START_ADDR_0_0_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_0_POS)) + +/* 0x44 : frame_byte_cnt0_0 */ +#define CAM_FRAME_BYTE_CNT0_0_OFFSET (0x44) +#define CAM_FRAME_BYTE_CNT_0_0 CAM_FRAME_BYTE_CNT_0_0 +#define CAM_FRAME_BYTE_CNT_0_0_POS (0U) +#define CAM_FRAME_BYTE_CNT_0_0_LEN (32U) +#define CAM_FRAME_BYTE_CNT_0_0_MSK (((1U << CAM_FRAME_BYTE_CNT_0_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_0_POS) +#define CAM_FRAME_BYTE_CNT_0_0_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_0_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_0_POS)) + +/* 0x48 : frame_start_addr0_1 */ +#define CAM_FRAME_START_ADDR0_1_OFFSET (0x48) +#define CAM_FRAME_START_ADDR_0_1 CAM_FRAME_START_ADDR_0_1 +#define CAM_FRAME_START_ADDR_0_1_POS (0U) +#define CAM_FRAME_START_ADDR_0_1_LEN (32U) +#define CAM_FRAME_START_ADDR_0_1_MSK (((1U << CAM_FRAME_START_ADDR_0_1_LEN) - 1) << CAM_FRAME_START_ADDR_0_1_POS) +#define CAM_FRAME_START_ADDR_0_1_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_1_LEN) - 1) << CAM_FRAME_START_ADDR_0_1_POS)) + +/* 0x4C : frame_byte_cnt0_1 */ +#define CAM_FRAME_BYTE_CNT0_1_OFFSET (0x4C) +#define CAM_FRAME_BYTE_CNT_0_1 CAM_FRAME_BYTE_CNT_0_1 +#define CAM_FRAME_BYTE_CNT_0_1_POS (0U) +#define CAM_FRAME_BYTE_CNT_0_1_LEN (32U) +#define CAM_FRAME_BYTE_CNT_0_1_MSK (((1U << CAM_FRAME_BYTE_CNT_0_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_1_POS) +#define CAM_FRAME_BYTE_CNT_0_1_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_0_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_1_POS)) + +/* 0x50 : frame_start_addr0_2 */ +#define CAM_FRAME_START_ADDR0_2_OFFSET (0x50) +#define CAM_FRAME_START_ADDR_0_2 CAM_FRAME_START_ADDR_0_2 +#define CAM_FRAME_START_ADDR_0_2_POS (0U) +#define CAM_FRAME_START_ADDR_0_2_LEN (32U) +#define CAM_FRAME_START_ADDR_0_2_MSK (((1U << CAM_FRAME_START_ADDR_0_2_LEN) - 1) << CAM_FRAME_START_ADDR_0_2_POS) +#define CAM_FRAME_START_ADDR_0_2_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_2_LEN) - 1) << CAM_FRAME_START_ADDR_0_2_POS)) + +/* 0x54 : frame_byte_cnt0_2 */ +#define CAM_FRAME_BYTE_CNT0_2_OFFSET (0x54) +#define CAM_FRAME_BYTE_CNT_0_2 CAM_FRAME_BYTE_CNT_0_2 +#define CAM_FRAME_BYTE_CNT_0_2_POS (0U) +#define CAM_FRAME_BYTE_CNT_0_2_LEN (32U) +#define CAM_FRAME_BYTE_CNT_0_2_MSK (((1U << CAM_FRAME_BYTE_CNT_0_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_2_POS) +#define CAM_FRAME_BYTE_CNT_0_2_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_0_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_2_POS)) + +/* 0x58 : frame_start_addr0_3 */ +#define CAM_FRAME_START_ADDR0_3_OFFSET (0x58) +#define CAM_FRAME_START_ADDR_0_3 CAM_FRAME_START_ADDR_0_3 +#define CAM_FRAME_START_ADDR_0_3_POS (0U) +#define CAM_FRAME_START_ADDR_0_3_LEN (32U) +#define CAM_FRAME_START_ADDR_0_3_MSK (((1U << CAM_FRAME_START_ADDR_0_3_LEN) - 1) << CAM_FRAME_START_ADDR_0_3_POS) +#define CAM_FRAME_START_ADDR_0_3_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_3_LEN) - 1) << CAM_FRAME_START_ADDR_0_3_POS)) + +/* 0x5C : frame_byte_cnt0_3 */ +#define CAM_FRAME_BYTE_CNT0_3_OFFSET (0x5C) +#define CAM_FRAME_BYTE_CNT_0_3 CAM_FRAME_BYTE_CNT_0_3 +#define CAM_FRAME_BYTE_CNT_0_3_POS (0U) +#define CAM_FRAME_BYTE_CNT_0_3_LEN (32U) +#define CAM_FRAME_BYTE_CNT_0_3_MSK (((1U << CAM_FRAME_BYTE_CNT_0_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_3_POS) +#define CAM_FRAME_BYTE_CNT_0_3_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_0_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_3_POS)) + +/* 0x60 : frame_start_addr0_4 */ +#define CAM_FRAME_START_ADDR0_4_OFFSET (0x60) +#define CAM_FRAME_START_ADDR_0_4 CAM_FRAME_START_ADDR_0_4 +#define CAM_FRAME_START_ADDR_0_4_POS (0U) +#define CAM_FRAME_START_ADDR_0_4_LEN (32U) +#define CAM_FRAME_START_ADDR_0_4_MSK (((1U << CAM_FRAME_START_ADDR_0_4_LEN) - 1) << CAM_FRAME_START_ADDR_0_4_POS) +#define CAM_FRAME_START_ADDR_0_4_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_4_LEN) - 1) << CAM_FRAME_START_ADDR_0_4_POS)) + +/* 0x64 : frame_byte_cnt0_4 */ +#define CAM_FRAME_BYTE_CNT0_4_OFFSET (0x64) +#define CAM_FRAME_BYTE_CNT_0_4 CAM_FRAME_BYTE_CNT_0_4 +#define CAM_FRAME_BYTE_CNT_0_4_POS (0U) +#define CAM_FRAME_BYTE_CNT_0_4_LEN (32U) +#define CAM_FRAME_BYTE_CNT_0_4_MSK (((1U << CAM_FRAME_BYTE_CNT_0_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_4_POS) +#define CAM_FRAME_BYTE_CNT_0_4_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_0_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_4_POS)) + +/* 0x68 : frame_start_addr0_5 */ +#define CAM_FRAME_START_ADDR0_5_OFFSET (0x68) +#define CAM_FRAME_START_ADDR_0_5 CAM_FRAME_START_ADDR_0_5 +#define CAM_FRAME_START_ADDR_0_5_POS (0U) +#define CAM_FRAME_START_ADDR_0_5_LEN (32U) +#define CAM_FRAME_START_ADDR_0_5_MSK (((1U << CAM_FRAME_START_ADDR_0_5_LEN) - 1) << CAM_FRAME_START_ADDR_0_5_POS) +#define CAM_FRAME_START_ADDR_0_5_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_5_LEN) - 1) << CAM_FRAME_START_ADDR_0_5_POS)) + +/* 0x6C : frame_byte_cnt0_5 */ +#define CAM_FRAME_BYTE_CNT0_5_OFFSET (0x6C) +#define CAM_FRAME_BYTE_CNT_0_5 CAM_FRAME_BYTE_CNT_0_5 +#define CAM_FRAME_BYTE_CNT_0_5_POS (0U) +#define CAM_FRAME_BYTE_CNT_0_5_LEN (32U) +#define CAM_FRAME_BYTE_CNT_0_5_MSK (((1U << CAM_FRAME_BYTE_CNT_0_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_5_POS) +#define CAM_FRAME_BYTE_CNT_0_5_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_0_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_5_POS)) + +/* 0x70 : frame_start_addr0_6 */ +#define CAM_FRAME_START_ADDR0_6_OFFSET (0x70) +#define CAM_FRAME_START_ADDR_0_6 CAM_FRAME_START_ADDR_0_6 +#define CAM_FRAME_START_ADDR_0_6_POS (0U) +#define CAM_FRAME_START_ADDR_0_6_LEN (32U) +#define CAM_FRAME_START_ADDR_0_6_MSK (((1U << CAM_FRAME_START_ADDR_0_6_LEN) - 1) << CAM_FRAME_START_ADDR_0_6_POS) +#define CAM_FRAME_START_ADDR_0_6_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_6_LEN) - 1) << CAM_FRAME_START_ADDR_0_6_POS)) + +/* 0x74 : frame_byte_cnt0_6 */ +#define CAM_FRAME_BYTE_CNT0_6_OFFSET (0x74) +#define CAM_FRAME_BYTE_CNT_0_6 CAM_FRAME_BYTE_CNT_0_6 +#define CAM_FRAME_BYTE_CNT_0_6_POS (0U) +#define CAM_FRAME_BYTE_CNT_0_6_LEN (32U) +#define CAM_FRAME_BYTE_CNT_0_6_MSK (((1U << CAM_FRAME_BYTE_CNT_0_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_6_POS) +#define CAM_FRAME_BYTE_CNT_0_6_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_0_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_6_POS)) + +/* 0x78 : frame_start_addr0_7 */ +#define CAM_FRAME_START_ADDR0_7_OFFSET (0x78) +#define CAM_FRAME_START_ADDR_0_7 CAM_FRAME_START_ADDR_0_7 +#define CAM_FRAME_START_ADDR_0_7_POS (0U) +#define CAM_FRAME_START_ADDR_0_7_LEN (32U) +#define CAM_FRAME_START_ADDR_0_7_MSK (((1U << CAM_FRAME_START_ADDR_0_7_LEN) - 1) << CAM_FRAME_START_ADDR_0_7_POS) +#define CAM_FRAME_START_ADDR_0_7_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_7_LEN) - 1) << CAM_FRAME_START_ADDR_0_7_POS)) + +/* 0x7C : frame_byte_cnt0_7 */ +#define CAM_FRAME_BYTE_CNT0_7_OFFSET (0x7C) +#define CAM_FRAME_BYTE_CNT_0_7 CAM_FRAME_BYTE_CNT_0_7 +#define CAM_FRAME_BYTE_CNT_0_7_POS (0U) +#define CAM_FRAME_BYTE_CNT_0_7_LEN (32U) +#define CAM_FRAME_BYTE_CNT_0_7_MSK (((1U << CAM_FRAME_BYTE_CNT_0_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_7_POS) +#define CAM_FRAME_BYTE_CNT_0_7_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_0_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_7_POS)) + +/* 0x80 : frame_start_addr1_0 */ +#define CAM_FRAME_START_ADDR1_0_OFFSET (0x80) +#define CAM_FRAME_START_ADDR_1_0 CAM_FRAME_START_ADDR_1_0 +#define CAM_FRAME_START_ADDR_1_0_POS (0U) +#define CAM_FRAME_START_ADDR_1_0_LEN (32U) +#define CAM_FRAME_START_ADDR_1_0_MSK (((1U << CAM_FRAME_START_ADDR_1_0_LEN) - 1) << CAM_FRAME_START_ADDR_1_0_POS) +#define CAM_FRAME_START_ADDR_1_0_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_0_LEN) - 1) << CAM_FRAME_START_ADDR_1_0_POS)) + +/* 0x84 : frame_byte_cnt1_0 */ +#define CAM_FRAME_BYTE_CNT1_0_OFFSET (0x84) +#define CAM_FRAME_BYTE_CNT_1_0 CAM_FRAME_BYTE_CNT_1_0 +#define CAM_FRAME_BYTE_CNT_1_0_POS (0U) +#define CAM_FRAME_BYTE_CNT_1_0_LEN (32U) +#define CAM_FRAME_BYTE_CNT_1_0_MSK (((1U << CAM_FRAME_BYTE_CNT_1_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_0_POS) +#define CAM_FRAME_BYTE_CNT_1_0_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_1_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_0_POS)) + +/* 0x88 : frame_start_addr1_1 */ +#define CAM_FRAME_START_ADDR1_1_OFFSET (0x88) +#define CAM_FRAME_START_ADDR_1_1 CAM_FRAME_START_ADDR_1_1 +#define CAM_FRAME_START_ADDR_1_1_POS (0U) +#define CAM_FRAME_START_ADDR_1_1_LEN (32U) +#define CAM_FRAME_START_ADDR_1_1_MSK (((1U << CAM_FRAME_START_ADDR_1_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_1_POS) +#define CAM_FRAME_START_ADDR_1_1_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_1_POS)) + +/* 0x8C : frame_byte_cnt1_1 */ +#define CAM_FRAME_BYTE_CNT1_1_OFFSET (0x8C) +#define CAM_FRAME_BYTE_CNT_1_1 CAM_FRAME_BYTE_CNT_1_1 +#define CAM_FRAME_BYTE_CNT_1_1_POS (0U) +#define CAM_FRAME_BYTE_CNT_1_1_LEN (32U) +#define CAM_FRAME_BYTE_CNT_1_1_MSK (((1U << CAM_FRAME_BYTE_CNT_1_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_1_POS) +#define CAM_FRAME_BYTE_CNT_1_1_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_1_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_1_POS)) + +/* 0x90 : frame_start_addr1_2 */ +#define CAM_FRAME_START_ADDR1_2_OFFSET (0x90) +#define CAM_FRAME_START_ADDR_1_2 CAM_FRAME_START_ADDR_1_2 +#define CAM_FRAME_START_ADDR_1_2_POS (0U) +#define CAM_FRAME_START_ADDR_1_2_LEN (32U) +#define CAM_FRAME_START_ADDR_1_2_MSK (((1U << CAM_FRAME_START_ADDR_1_2_LEN) - 1) << CAM_FRAME_START_ADDR_1_2_POS) +#define CAM_FRAME_START_ADDR_1_2_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_2_LEN) - 1) << CAM_FRAME_START_ADDR_1_2_POS)) + +/* 0x94 : frame_byte_cnt1_2 */ +#define CAM_FRAME_BYTE_CNT1_2_OFFSET (0x94) +#define CAM_FRAME_BYTE_CNT_1_2 CAM_FRAME_BYTE_CNT_1_2 +#define CAM_FRAME_BYTE_CNT_1_2_POS (0U) +#define CAM_FRAME_BYTE_CNT_1_2_LEN (32U) +#define CAM_FRAME_BYTE_CNT_1_2_MSK (((1U << CAM_FRAME_BYTE_CNT_1_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_2_POS) +#define CAM_FRAME_BYTE_CNT_1_2_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_1_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_2_POS)) + +/* 0x98 : frame_start_addr1_3 */ +#define CAM_FRAME_START_ADDR1_3_OFFSET (0x98) +#define CAM_FRAME_START_ADDR_1_3 CAM_FRAME_START_ADDR_1_3 +#define CAM_FRAME_START_ADDR_1_3_POS (0U) +#define CAM_FRAME_START_ADDR_1_3_LEN (32U) +#define CAM_FRAME_START_ADDR_1_3_MSK (((1U << CAM_FRAME_START_ADDR_1_3_LEN) - 1) << CAM_FRAME_START_ADDR_1_3_POS) +#define CAM_FRAME_START_ADDR_1_3_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_3_LEN) - 1) << CAM_FRAME_START_ADDR_1_3_POS)) + +/* 0x9C : frame_byte_cnt1_3 */ +#define CAM_FRAME_BYTE_CNT1_3_OFFSET (0x9C) +#define CAM_FRAME_BYTE_CNT_1_3 CAM_FRAME_BYTE_CNT_1_3 +#define CAM_FRAME_BYTE_CNT_1_3_POS (0U) +#define CAM_FRAME_BYTE_CNT_1_3_LEN (32U) +#define CAM_FRAME_BYTE_CNT_1_3_MSK (((1U << CAM_FRAME_BYTE_CNT_1_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_3_POS) +#define CAM_FRAME_BYTE_CNT_1_3_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_1_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_3_POS)) + +/* 0xA0 : frame_start_addr1_4 */ +#define CAM_FRAME_START_ADDR1_4_OFFSET (0xA0) +#define CAM_FRAME_START_ADDR_1_4 CAM_FRAME_START_ADDR_1_4 +#define CAM_FRAME_START_ADDR_1_4_POS (0U) +#define CAM_FRAME_START_ADDR_1_4_LEN (32U) +#define CAM_FRAME_START_ADDR_1_4_MSK (((1U << CAM_FRAME_START_ADDR_1_4_LEN) - 1) << CAM_FRAME_START_ADDR_1_4_POS) +#define CAM_FRAME_START_ADDR_1_4_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_4_LEN) - 1) << CAM_FRAME_START_ADDR_1_4_POS)) + +/* 0xA4 : frame_byte_cnt1_4 */ +#define CAM_FRAME_BYTE_CNT1_4_OFFSET (0xA4) +#define CAM_FRAME_BYTE_CNT_1_4 CAM_FRAME_BYTE_CNT_1_4 +#define CAM_FRAME_BYTE_CNT_1_4_POS (0U) +#define CAM_FRAME_BYTE_CNT_1_4_LEN (32U) +#define CAM_FRAME_BYTE_CNT_1_4_MSK (((1U << CAM_FRAME_BYTE_CNT_1_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_4_POS) +#define CAM_FRAME_BYTE_CNT_1_4_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_1_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_4_POS)) + +/* 0xA8 : frame_start_addr1_5 */ +#define CAM_FRAME_START_ADDR1_5_OFFSET (0xA8) +#define CAM_FRAME_START_ADDR_1_5 CAM_FRAME_START_ADDR_1_5 +#define CAM_FRAME_START_ADDR_1_5_POS (0U) +#define CAM_FRAME_START_ADDR_1_5_LEN (32U) +#define CAM_FRAME_START_ADDR_1_5_MSK (((1U << CAM_FRAME_START_ADDR_1_5_LEN) - 1) << CAM_FRAME_START_ADDR_1_5_POS) +#define CAM_FRAME_START_ADDR_1_5_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_5_LEN) - 1) << CAM_FRAME_START_ADDR_1_5_POS)) + +/* 0xAC : frame_byte_cnt1_5 */ +#define CAM_FRAME_BYTE_CNT1_5_OFFSET (0xAC) +#define CAM_FRAME_BYTE_CNT_1_5 CAM_FRAME_BYTE_CNT_1_5 +#define CAM_FRAME_BYTE_CNT_1_5_POS (0U) +#define CAM_FRAME_BYTE_CNT_1_5_LEN (32U) +#define CAM_FRAME_BYTE_CNT_1_5_MSK (((1U << CAM_FRAME_BYTE_CNT_1_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_5_POS) +#define CAM_FRAME_BYTE_CNT_1_5_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_1_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_5_POS)) + +/* 0xB0 : frame_start_addr1_6 */ +#define CAM_FRAME_START_ADDR1_6_OFFSET (0xB0) +#define CAM_FRAME_START_ADDR_1_6 CAM_FRAME_START_ADDR_1_6 +#define CAM_FRAME_START_ADDR_1_6_POS (0U) +#define CAM_FRAME_START_ADDR_1_6_LEN (32U) +#define CAM_FRAME_START_ADDR_1_6_MSK (((1U << CAM_FRAME_START_ADDR_1_6_LEN) - 1) << CAM_FRAME_START_ADDR_1_6_POS) +#define CAM_FRAME_START_ADDR_1_6_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_6_LEN) - 1) << CAM_FRAME_START_ADDR_1_6_POS)) + +/* 0xB4 : frame_byte_cnt1_6 */ +#define CAM_FRAME_BYTE_CNT1_6_OFFSET (0xB4) +#define CAM_FRAME_BYTE_CNT_1_6 CAM_FRAME_BYTE_CNT_1_6 +#define CAM_FRAME_BYTE_CNT_1_6_POS (0U) +#define CAM_FRAME_BYTE_CNT_1_6_LEN (32U) +#define CAM_FRAME_BYTE_CNT_1_6_MSK (((1U << CAM_FRAME_BYTE_CNT_1_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_6_POS) +#define CAM_FRAME_BYTE_CNT_1_6_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_1_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_6_POS)) + +/* 0xB8 : frame_start_addr1_7 */ +#define CAM_FRAME_START_ADDR1_7_OFFSET (0xB8) +#define CAM_FRAME_START_ADDR_1_7 CAM_FRAME_START_ADDR_1_7 +#define CAM_FRAME_START_ADDR_1_7_POS (0U) +#define CAM_FRAME_START_ADDR_1_7_LEN (32U) +#define CAM_FRAME_START_ADDR_1_7_MSK (((1U << CAM_FRAME_START_ADDR_1_7_LEN) - 1) << CAM_FRAME_START_ADDR_1_7_POS) +#define CAM_FRAME_START_ADDR_1_7_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_7_LEN) - 1) << CAM_FRAME_START_ADDR_1_7_POS)) + +/* 0xBC : frame_byte_cnt1_7 */ +#define CAM_FRAME_BYTE_CNT1_7_OFFSET (0xBC) +#define CAM_FRAME_BYTE_CNT_1_7 CAM_FRAME_BYTE_CNT_1_7 +#define CAM_FRAME_BYTE_CNT_1_7_POS (0U) +#define CAM_FRAME_BYTE_CNT_1_7_LEN (32U) +#define CAM_FRAME_BYTE_CNT_1_7_MSK (((1U << CAM_FRAME_BYTE_CNT_1_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_7_POS) +#define CAM_FRAME_BYTE_CNT_1_7_UMSK (~(((1U << CAM_FRAME_BYTE_CNT_1_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_7_POS)) + +/* 0xFF0 : dvp_debug */ +#define CAM_DVP_DEBUG_OFFSET (0xFF0) +#define CAM_REG_DVP_DBG_EN CAM_REG_DVP_DBG_EN +#define CAM_REG_DVP_DBG_EN_POS (0U) +#define CAM_REG_DVP_DBG_EN_LEN (1U) +#define CAM_REG_DVP_DBG_EN_MSK (((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS) +#define CAM_REG_DVP_DBG_EN_UMSK (~(((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS)) +#define CAM_REG_DVP_DBG_SEL CAM_REG_DVP_DBG_SEL +#define CAM_REG_DVP_DBG_SEL_POS (1U) +#define CAM_REG_DVP_DBG_SEL_LEN (3U) +#define CAM_REG_DVP_DBG_SEL_MSK (((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS) +#define CAM_REG_DVP_DBG_SEL_UMSK (~(((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS)) + +/* 0xFFC : dvp_dummy_reg */ +#define CAM_DVP_DUMMY_REG_OFFSET (0xFFC) + +struct cam_reg { + /* 0x0 : dvp2axi_configue */ + union { + struct + { + uint32_t reg_dvp_enable : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_sw_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_fram_vld_pol : 1; /* [ 2], r/w, 0x1 */ + uint32_t reg_line_vld_pol : 1; /* [ 3], r/w, 0x1 */ + uint32_t reg_hburst : 2; /* [ 5: 4], r/w, 0x3 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_dvp_mode : 3; /* [10: 8], r/w, 0x0 */ + uint32_t reg_hw_mode_fwrap : 1; /* [ 11], r/w, 0x1 */ + uint32_t reg_drop_en : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_drop_even : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_subsample_en : 1; /* [ 14], r/w, 0x0 */ + uint32_t reg_subsample_even : 1; /* [ 15], r/w, 0x0 */ + uint32_t reg_interlv_mode : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ + uint32_t reg_dvp_pix_clk_cg : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ + uint32_t reg_dvp_wait_cycle : 8; /* [31:24], r/w, 0x40 */ + } BF; + uint32_t WORD; + } dvp2axi_configue; + + /* 0x4 : dvp2ahb_addr_start_0 */ + union { + struct + { + uint32_t reg_addr_start_0 : 32; /* [31: 0], r/w, 0x80000000L */ + } BF; + uint32_t WORD; + } dvp2ahb_addr_start_0; + + /* 0x8 : dvp2ahb_mem_bcnt_0 */ + union { + struct + { + uint32_t reg_mem_burst_cnt_0 : 32; /* [31: 0], r/w, 0xc000 */ + } BF; + uint32_t WORD; + } dvp2ahb_mem_bcnt_0; + + /* 0xC : dvp2ahb_frame_bcnt_0 */ + union { + struct + { + uint32_t reg_frame_burst_cnt_0 : 32; /* [31: 0], r/w, 0xc000 */ + } BF; + uint32_t WORD; + } dvp2ahb_frame_bcnt_0; + + /* 0x10 : dvp2ahb_addr_start_1 */ + union { + struct + { + uint32_t reg_addr_start_1 : 32; /* [31: 0], r/w, 0x80000000L */ + } BF; + uint32_t WORD; + } dvp2ahb_addr_start_1; + + /* 0x14 : dvp2ahb_mem_bcnt_1 */ + union { + struct + { + uint32_t reg_mem_burst_cnt_1 : 32; /* [31: 0], r/w, 0xc000 */ + } BF; + uint32_t WORD; + } dvp2ahb_mem_bcnt_1; + + /* 0x18 : dvp2ahb_frame_bcnt_1 */ + union { + struct + { + uint32_t reg_frame_burst_cnt_1 : 32; /* [31: 0], r/w, 0xc000 */ + } BF; + uint32_t WORD; + } dvp2ahb_frame_bcnt_1; + + /* 0x1C : dvp_status_and_error */ + union { + struct + { + uint32_t sts_normal_int_0 : 1; /* [ 0], r, 0x0 */ + uint32_t sts_normal_int_1 : 1; /* [ 1], r, 0x0 */ + uint32_t sts_mem_int_0 : 1; /* [ 2], r, 0x0 */ + uint32_t sts_mem_int_1 : 1; /* [ 3], r, 0x0 */ + uint32_t sts_frame_int_0 : 1; /* [ 4], r, 0x0 */ + uint32_t sts_frame_int_1 : 1; /* [ 5], r, 0x0 */ + uint32_t sts_fifo_int_0 : 1; /* [ 6], r, 0x0 */ + uint32_t sts_fifo_int_1 : 1; /* [ 7], r, 0x0 */ + uint32_t sts_hcnt_int : 1; /* [ 8], r, 0x0 */ + uint32_t sts_vcnt_int : 1; /* [ 9], r, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t ahb_idle_0 : 1; /* [ 16], r, 0x1 */ + uint32_t ahb_idle_1 : 1; /* [ 17], r, 0x1 */ + uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t st_dvp_idle : 1; /* [ 19], r, 0x1 */ + uint32_t frame_valid_cnt_0 : 4; /* [23:20], r, 0x0 */ + uint32_t frame_valid_cnt_1 : 4; /* [27:24], r, 0x0 */ + uint32_t st_bus_idle : 1; /* [ 28], r, 0x1 */ + uint32_t st_bus_func : 1; /* [ 29], r, 0x0 */ + uint32_t st_bus_wait : 1; /* [ 30], r, 0x0 */ + uint32_t st_bus_flsh : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } dvp_status_and_error; + + /* 0x20 : dvp_frame_fifo_pop */ + union { + struct + { + uint32_t rfifo_pop_0 : 1; /* [ 0], w1p, 0x0 */ + uint32_t rfifo_pop_1 : 1; /* [ 1], w1p, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t reg_int_normal_clr_0 : 1; /* [ 4], w1p, 0x0 */ + uint32_t reg_int_mem_clr_0 : 1; /* [ 5], w1p, 0x0 */ + uint32_t reg_int_frame_clr_0 : 1; /* [ 6], w1p, 0x0 */ + uint32_t reg_int_fifo_clr_0 : 1; /* [ 7], w1p, 0x0 */ + uint32_t reg_int_hcnt_clr_0 : 1; /* [ 8], w1p, 0x0 */ + uint32_t reg_int_vcnt_clr_0 : 1; /* [ 9], w1p, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t reg_int_normal_clr_1 : 1; /* [ 16], w1p, 0x0 */ + uint32_t reg_int_mem_clr_1 : 1; /* [ 17], w1p, 0x0 */ + uint32_t reg_int_frame_clr_1 : 1; /* [ 18], w1p, 0x0 */ + uint32_t reg_int_fifo_clr_1 : 1; /* [ 19], w1p, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } dvp_frame_fifo_pop; + + /* 0x24 : snsr_control */ + union { + struct + { + uint32_t reg_cam_rst : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_cam_pwdn : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } snsr_control; + + /* 0x28 : int_control */ + union { + struct + { + uint32_t reg_int_normal_0_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_int_normal_1_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_int_mem_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t reg_int_frame_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_int_fifo_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t reg_int_hcnt_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t reg_int_vcnt_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7_27 : 21; /* [27: 7], rsvd, 0x0 */ + uint32_t reg_frame_cnt_trgr_int : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } int_control; + + /* 0x2c reserved */ + uint8_t RESERVED0x2c[4]; + + /* 0x30 : hsync_control */ + union { + struct + { + uint32_t reg_hsync_act_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t reg_hsync_act_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } hsync_control; + + /* 0x34 : vsync_control */ + union { + struct + { + uint32_t reg_vsync_act_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t reg_vsync_act_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } vsync_control; + + /* 0x38 : frame_size_control */ + union { + struct + { + uint32_t reg_total_hcnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reg_total_vcnt : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } frame_size_control; + + /* 0x3c reserved */ + uint8_t RESERVED0x3c[4]; + + /* 0x40 : frame_start_addr0_0 */ + union { + struct + { + uint32_t frame_start_addr_0_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr0_0; + + /* 0x44 : frame_byte_cnt0_0 */ + union { + struct + { + uint32_t frame_byte_cnt_0_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt0_0; + + /* 0x48 : frame_start_addr0_1 */ + union { + struct + { + uint32_t frame_start_addr_0_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr0_1; + + /* 0x4C : frame_byte_cnt0_1 */ + union { + struct + { + uint32_t frame_byte_cnt_0_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt0_1; + + /* 0x50 : frame_start_addr0_2 */ + union { + struct + { + uint32_t frame_start_addr_0_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr0_2; + + /* 0x54 : frame_byte_cnt0_2 */ + union { + struct + { + uint32_t frame_byte_cnt_0_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt0_2; + + /* 0x58 : frame_start_addr0_3 */ + union { + struct + { + uint32_t frame_start_addr_0_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr0_3; + + /* 0x5C : frame_byte_cnt0_3 */ + union { + struct + { + uint32_t frame_byte_cnt_0_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt0_3; + + /* 0x60 : frame_start_addr0_4 */ + union { + struct + { + uint32_t frame_start_addr_0_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr0_4; + + /* 0x64 : frame_byte_cnt0_4 */ + union { + struct + { + uint32_t frame_byte_cnt_0_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt0_4; + + /* 0x68 : frame_start_addr0_5 */ + union { + struct + { + uint32_t frame_start_addr_0_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr0_5; + + /* 0x6C : frame_byte_cnt0_5 */ + union { + struct + { + uint32_t frame_byte_cnt_0_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt0_5; + + /* 0x70 : frame_start_addr0_6 */ + union { + struct + { + uint32_t frame_start_addr_0_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr0_6; + + /* 0x74 : frame_byte_cnt0_6 */ + union { + struct + { + uint32_t frame_byte_cnt_0_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt0_6; + + /* 0x78 : frame_start_addr0_7 */ + union { + struct + { + uint32_t frame_start_addr_0_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr0_7; + + /* 0x7C : frame_byte_cnt0_7 */ + union { + struct + { + uint32_t frame_byte_cnt_0_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt0_7; + + /* 0x80 : frame_start_addr1_0 */ + union { + struct + { + uint32_t frame_start_addr_1_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr1_0; + + /* 0x84 : frame_byte_cnt1_0 */ + union { + struct + { + uint32_t frame_byte_cnt_1_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt1_0; + + /* 0x88 : frame_start_addr1_1 */ + union { + struct + { + uint32_t frame_start_addr_1_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr1_1; + + /* 0x8C : frame_byte_cnt1_1 */ + union { + struct + { + uint32_t frame_byte_cnt_1_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt1_1; + + /* 0x90 : frame_start_addr1_2 */ + union { + struct + { + uint32_t frame_start_addr_1_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr1_2; + + /* 0x94 : frame_byte_cnt1_2 */ + union { + struct + { + uint32_t frame_byte_cnt_1_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt1_2; + + /* 0x98 : frame_start_addr1_3 */ + union { + struct + { + uint32_t frame_start_addr_1_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr1_3; + + /* 0x9C : frame_byte_cnt1_3 */ + union { + struct + { + uint32_t frame_byte_cnt_1_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt1_3; + + /* 0xA0 : frame_start_addr1_4 */ + union { + struct + { + uint32_t frame_start_addr_1_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr1_4; + + /* 0xA4 : frame_byte_cnt1_4 */ + union { + struct + { + uint32_t frame_byte_cnt_1_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt1_4; + + /* 0xA8 : frame_start_addr1_5 */ + union { + struct + { + uint32_t frame_start_addr_1_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr1_5; + + /* 0xAC : frame_byte_cnt1_5 */ + union { + struct + { + uint32_t frame_byte_cnt_1_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt1_5; + + /* 0xB0 : frame_start_addr1_6 */ + union { + struct + { + uint32_t frame_start_addr_1_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr1_6; + + /* 0xB4 : frame_byte_cnt1_6 */ + union { + struct + { + uint32_t frame_byte_cnt_1_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt1_6; + + /* 0xB8 : frame_start_addr1_7 */ + union { + struct + { + uint32_t frame_start_addr_1_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_start_addr1_7; + + /* 0xBC : frame_byte_cnt1_7 */ + union { + struct + { + uint32_t frame_byte_cnt_1_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } frame_byte_cnt1_7; + + /* 0xc0 reserved */ + uint8_t RESERVED0xc0[3888]; + + /* 0xFF0 : dvp_debug */ + union { + struct + { + uint32_t reg_dvp_dbg_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_dvp_dbg_sel : 3; /* [ 3: 1], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } dvp_debug; + + /* 0xff4 reserved */ + uint8_t RESERVED0xff4[8]; + + /* 0xFFC : dvp_dummy_reg */ + union { + struct + { + uint32_t RESERVED_31_0 : 32; /* [31: 0], rsvd, 0xf0f0f0f0L */ + } BF; + uint32_t WORD; + } dvp_dummy_reg; +}; + +typedef volatile struct cam_reg cam_reg_t; + +#endif /* __CAM_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cci_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cci_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..e1fe75259ab3ca46f4e294a4e1cf1883a8c5d418 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cci_reg.h @@ -0,0 +1,192 @@ +/** + ****************************************************************************** + * @file cci_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __CCI_REG_H__ +#define __CCI_REG_H__ + +#include "bl702.h" + +/* 0x0 : cci_cfg */ +#define CCI_CFG_OFFSET (0x0) +#define CCI_EN CCI_EN +#define CCI_EN_POS (0U) +#define CCI_EN_LEN (1U) +#define CCI_EN_MSK (((1U << CCI_EN_LEN) - 1) << CCI_EN_POS) +#define CCI_EN_UMSK (~(((1U << CCI_EN_LEN) - 1) << CCI_EN_POS)) +#define CCI_SLV_SEL_CCI2 CCI_SLV_SEL_CCI2 +#define CCI_SLV_SEL_CCI2_POS (1U) +#define CCI_SLV_SEL_CCI2_LEN (1U) +#define CCI_SLV_SEL_CCI2_MSK (((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS) +#define CCI_SLV_SEL_CCI2_UMSK (~(((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS)) +#define CCI_MAS_SEL_CCI2 CCI_MAS_SEL_CCI2 +#define CCI_MAS_SEL_CCI2_POS (2U) +#define CCI_MAS_SEL_CCI2_LEN (1U) +#define CCI_MAS_SEL_CCI2_MSK (((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS) +#define CCI_MAS_SEL_CCI2_UMSK (~(((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS)) +#define CCI_MAS_HW_MODE CCI_MAS_HW_MODE +#define CCI_MAS_HW_MODE_POS (3U) +#define CCI_MAS_HW_MODE_LEN (1U) +#define CCI_MAS_HW_MODE_MSK (((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS) +#define CCI_MAS_HW_MODE_UMSK (~(((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS)) +#define CCI_REG_M_CCI_SCLK_EN CCI_REG_M_CCI_SCLK_EN +#define CCI_REG_M_CCI_SCLK_EN_POS (4U) +#define CCI_REG_M_CCI_SCLK_EN_LEN (1U) +#define CCI_REG_M_CCI_SCLK_EN_MSK (((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS) +#define CCI_REG_M_CCI_SCLK_EN_UMSK (~(((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS)) +#define CCI_REG_DIV_M_CCI_SCLK CCI_REG_DIV_M_CCI_SCLK +#define CCI_REG_DIV_M_CCI_SCLK_POS (5U) +#define CCI_REG_DIV_M_CCI_SCLK_LEN (2U) +#define CCI_REG_DIV_M_CCI_SCLK_MSK (((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS) +#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS)) +#define CCI_CFG_CCI1_PRE_READ CCI_CFG_CCI1_PRE_READ +#define CCI_CFG_CCI1_PRE_READ_POS (7U) +#define CCI_CFG_CCI1_PRE_READ_LEN (1U) +#define CCI_CFG_CCI1_PRE_READ_MSK (((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS) +#define CCI_CFG_CCI1_PRE_READ_UMSK (~(((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS)) +#define CCI_REG_SCCI_CLK_INV CCI_REG_SCCI_CLK_INV +#define CCI_REG_SCCI_CLK_INV_POS (8U) +#define CCI_REG_SCCI_CLK_INV_LEN (1U) +#define CCI_REG_SCCI_CLK_INV_MSK (((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS) +#define CCI_REG_SCCI_CLK_INV_UMSK (~(((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS)) +#define CCI_REG_MCCI_CLK_INV CCI_REG_MCCI_CLK_INV +#define CCI_REG_MCCI_CLK_INV_POS (9U) +#define CCI_REG_MCCI_CLK_INV_LEN (1U) +#define CCI_REG_MCCI_CLK_INV_MSK (((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS) +#define CCI_REG_MCCI_CLK_INV_UMSK (~(((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS)) + +/* 0x4 : cci_addr */ +#define CCI_ADDR_OFFSET (0x4) +#define CCI_APB_CCI_ADDR CCI_APB_CCI_ADDR +#define CCI_APB_CCI_ADDR_POS (0U) +#define CCI_APB_CCI_ADDR_LEN (32U) +#define CCI_APB_CCI_ADDR_MSK (((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS) +#define CCI_APB_CCI_ADDR_UMSK (~(((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS)) + +/* 0x8 : cci_wdata */ +#define CCI_WDATA_OFFSET (0x8) +#define CCI_APB_CCI_WDATA CCI_APB_CCI_WDATA +#define CCI_APB_CCI_WDATA_POS (0U) +#define CCI_APB_CCI_WDATA_LEN (32U) +#define CCI_APB_CCI_WDATA_MSK (((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS) +#define CCI_APB_CCI_WDATA_UMSK (~(((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS)) + +/* 0xC : cci_rdata */ +#define CCI_RDATA_OFFSET (0xC) +#define CCI_APB_CCI_RDATA CCI_APB_CCI_RDATA +#define CCI_APB_CCI_RDATA_POS (0U) +#define CCI_APB_CCI_RDATA_LEN (32U) +#define CCI_APB_CCI_RDATA_MSK (((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS) +#define CCI_APB_CCI_RDATA_UMSK (~(((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS)) + +/* 0x10 : cci_ctl */ +#define CCI_CTL_OFFSET (0x10) +#define CCI_WRITE_FLAG CCI_WRITE_FLAG +#define CCI_WRITE_FLAG_POS (0U) +#define CCI_WRITE_FLAG_LEN (1U) +#define CCI_WRITE_FLAG_MSK (((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS) +#define CCI_WRITE_FLAG_UMSK (~(((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS)) +#define CCI_READ_FLAG CCI_READ_FLAG +#define CCI_READ_FLAG_POS (1U) +#define CCI_READ_FLAG_LEN (1U) +#define CCI_READ_FLAG_MSK (((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS) +#define CCI_READ_FLAG_UMSK (~(((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS)) +#define CCI_AHB_STATE CCI_AHB_STATE +#define CCI_AHB_STATE_POS (2U) +#define CCI_AHB_STATE_LEN (2U) +#define CCI_AHB_STATE_MSK (((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS) +#define CCI_AHB_STATE_UMSK (~(((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS)) + +struct cci_reg { + /* 0x0 : cci_cfg */ + union { + struct + { + uint32_t cci_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t cci_slv_sel_cci2 : 1; /* [ 1], r/w, 0x0 */ + uint32_t cci_mas_sel_cci2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t cci_mas_hw_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_m_cci_sclk_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_div_m_cci_sclk : 2; /* [ 6: 5], r/w, 0x1 */ + uint32_t cfg_cci1_pre_read : 1; /* [ 7], r/w, 0x0 */ + uint32_t reg_scci_clk_inv : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_mcci_clk_inv : 1; /* [ 9], r/w, 0x1 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cci_cfg; + + /* 0x4 : cci_addr */ + union { + struct + { + uint32_t apb_cci_addr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } cci_addr; + + /* 0x8 : cci_wdata */ + union { + struct + { + uint32_t apb_cci_wdata : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } cci_wdata; + + /* 0xC : cci_rdata */ + union { + struct + { + uint32_t apb_cci_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } cci_rdata; + + /* 0x10 : cci_ctl */ + union { + struct + { + uint32_t cci_write_flag : 1; /* [ 0], r, 0x0 */ + uint32_t cci_read_flag : 1; /* [ 1], r, 0x0 */ + uint32_t ahb_state : 2; /* [ 3: 2], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cci_ctl; +}; + +typedef volatile struct cci_reg cci_reg_t; + +#endif /* __CCI_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cks_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cks_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..0a7ed1b28585ffaef079352bf38c4184b82b1e0d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/cks_reg.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file cks_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __CKS_REG_H__ +#define __CKS_REG_H__ + +#include "bl702.h" + +/* 0x0 : cks_config */ +#define CKS_CONFIG_OFFSET (0x0) +#define CKS_CR_CKS_CLR CKS_CR_CKS_CLR +#define CKS_CR_CKS_CLR_POS (0U) +#define CKS_CR_CKS_CLR_LEN (1U) +#define CKS_CR_CKS_CLR_MSK (((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS) +#define CKS_CR_CKS_CLR_UMSK (~(((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS)) +#define CKS_CR_CKS_BYTE_SWAP CKS_CR_CKS_BYTE_SWAP +#define CKS_CR_CKS_BYTE_SWAP_POS (1U) +#define CKS_CR_CKS_BYTE_SWAP_LEN (1U) +#define CKS_CR_CKS_BYTE_SWAP_MSK (((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS) +#define CKS_CR_CKS_BYTE_SWAP_UMSK (~(((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS)) + +/* 0x4 : data_in */ +#define CKS_DATA_IN_OFFSET (0x4) +#define CKS_DATA_IN CKS_DATA_IN +#define CKS_DATA_IN_POS (0U) +#define CKS_DATA_IN_LEN (8U) +#define CKS_DATA_IN_MSK (((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS) +#define CKS_DATA_IN_UMSK (~(((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS)) + +/* 0x8 : cks_out */ +#define CKS_OUT_OFFSET (0x8) +#define CKS_OUT CKS_OUT +#define CKS_OUT_POS (0U) +#define CKS_OUT_LEN (16U) +#define CKS_OUT_MSK (((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS) +#define CKS_OUT_UMSK (~(((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS)) + +struct cks_reg { + /* 0x0 : cks_config */ + union { + struct + { + uint32_t cr_cks_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t cr_cks_byte_swap : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cks_config; + + /* 0x4 : data_in */ + union { + struct + { + uint32_t data_in : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } data_in; + + /* 0x8 : cks_out */ + union { + struct + { + uint32_t cks_out : 16; /* [15: 0], r, 0xffff */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cks_out; +}; + +typedef volatile struct cks_reg cks_reg_t; + +#endif /* __CKS_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/dma_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/dma_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..30438181072d65ea3246c420f18d2461d865f383 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/dma_reg.h @@ -0,0 +1,2232 @@ +/** + ****************************************************************************** + * @file dma_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __DMA_REG_H__ +#define __DMA_REG_H__ + +#include "bl702.h" + +/* 0x0 : DMA_IntStatus */ +#define DMA_INTSTATUS_OFFSET (0x0) +#define DMA_INTSTATUS DMA_INTSTATUS +#define DMA_INTSTATUS_POS (0U) +#define DMA_INTSTATUS_LEN (8U) +#define DMA_INTSTATUS_MSK (((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS) +#define DMA_INTSTATUS_UMSK (~(((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS)) + +/* 0x4 : DMA_IntTCStatus */ +#define DMA_INTTCSTATUS_OFFSET (0x4) +#define DMA_INTTCSTATUS DMA_INTTCSTATUS +#define DMA_INTTCSTATUS_POS (0U) +#define DMA_INTTCSTATUS_LEN (8U) +#define DMA_INTTCSTATUS_MSK (((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS) +#define DMA_INTTCSTATUS_UMSK (~(((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS)) + +/* 0x8 : DMA_IntTCClear */ +#define DMA_INTTCCLEAR_OFFSET (0x8) +#define DMA_INTTCCLEAR DMA_INTTCCLEAR +#define DMA_INTTCCLEAR_POS (0U) +#define DMA_INTTCCLEAR_LEN (8U) +#define DMA_INTTCCLEAR_MSK (((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS) +#define DMA_INTTCCLEAR_UMSK (~(((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS)) + +/* 0xC : DMA_IntErrorStatus */ +#define DMA_INTERRORSTATUS_OFFSET (0xC) +#define DMA_INTERRORSTATUS DMA_INTERRORSTATUS +#define DMA_INTERRORSTATUS_POS (0U) +#define DMA_INTERRORSTATUS_LEN (8U) +#define DMA_INTERRORSTATUS_MSK (((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS) +#define DMA_INTERRORSTATUS_UMSK (~(((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS)) + +/* 0x10 : DMA_IntErrClr */ +#define DMA_INTERRCLR_OFFSET (0x10) +#define DMA_INTERRCLR DMA_INTERRCLR +#define DMA_INTERRCLR_POS (0U) +#define DMA_INTERRCLR_LEN (8U) +#define DMA_INTERRCLR_MSK (((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS) +#define DMA_INTERRCLR_UMSK (~(((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS)) + +/* 0x14 : DMA_RawIntTCStatus */ +#define DMA_RAWINTTCSTATUS_OFFSET (0x14) +#define DMA_RAWINTTCSTATUS DMA_RAWINTTCSTATUS +#define DMA_RAWINTTCSTATUS_POS (0U) +#define DMA_RAWINTTCSTATUS_LEN (8U) +#define DMA_RAWINTTCSTATUS_MSK (((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS) +#define DMA_RAWINTTCSTATUS_UMSK (~(((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS)) + +/* 0x18 : DMA_RawIntErrorStatus */ +#define DMA_RAWINTERRORSTATUS_OFFSET (0x18) +#define DMA_RAWINTERRORSTATUS DMA_RAWINTERRORSTATUS +#define DMA_RAWINTERRORSTATUS_POS (0U) +#define DMA_RAWINTERRORSTATUS_LEN (8U) +#define DMA_RAWINTERRORSTATUS_MSK (((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS) +#define DMA_RAWINTERRORSTATUS_UMSK (~(((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS)) + +/* 0x1C : DMA_EnbldChns */ +#define DMA_ENBLDCHNS_OFFSET (0x1C) +#define DMA_ENABLEDCHANNELS DMA_ENABLEDCHANNELS +#define DMA_ENABLEDCHANNELS_POS (0U) +#define DMA_ENABLEDCHANNELS_LEN (8U) +#define DMA_ENABLEDCHANNELS_MSK (((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS) +#define DMA_ENABLEDCHANNELS_UMSK (~(((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS)) + +/* 0x20 : DMA_SoftBReq */ +#define DMA_SOFTBREQ_OFFSET (0x20) +#define DMA_SOFTBREQ DMA_SOFTBREQ +#define DMA_SOFTBREQ_POS (0U) +#define DMA_SOFTBREQ_LEN (32U) +#define DMA_SOFTBREQ_MSK (((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS) +#define DMA_SOFTBREQ_UMSK (~(((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS)) + +/* 0x24 : DMA_SoftSReq */ +#define DMA_SOFTSREQ_OFFSET (0x24) +#define DMA_SOFTSREQ DMA_SOFTSREQ +#define DMA_SOFTSREQ_POS (0U) +#define DMA_SOFTSREQ_LEN (32U) +#define DMA_SOFTSREQ_MSK (((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS) +#define DMA_SOFTSREQ_UMSK (~(((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS)) + +/* 0x28 : DMA_SoftLBReq */ +#define DMA_SOFTLBREQ_OFFSET (0x28) +#define DMA_SOFTLBREQ DMA_SOFTLBREQ +#define DMA_SOFTLBREQ_POS (0U) +#define DMA_SOFTLBREQ_LEN (32U) +#define DMA_SOFTLBREQ_MSK (((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS) +#define DMA_SOFTLBREQ_UMSK (~(((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS)) + +/* 0x2C : DMA_SoftLSReq */ +#define DMA_SOFTLSREQ_OFFSET (0x2C) +#define DMA_SOFTLSREQ DMA_SOFTLSREQ +#define DMA_SOFTLSREQ_POS (0U) +#define DMA_SOFTLSREQ_LEN (32U) +#define DMA_SOFTLSREQ_MSK (((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS) +#define DMA_SOFTLSREQ_UMSK (~(((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS)) + +/* 0x30 : DMA_Top_Config */ +#define DMA_TOP_CONFIG_OFFSET (0x30) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_M DMA_M +#define DMA_M_POS (1U) +#define DMA_M_LEN (1U) +#define DMA_M_MSK (((1U << DMA_M_LEN) - 1) << DMA_M_POS) +#define DMA_M_UMSK (~(((1U << DMA_M_LEN) - 1) << DMA_M_POS)) + +/* 0x34 : DMA_Sync */ +#define DMA_SYNC_OFFSET (0x34) +#define DMA_SYNC DMA_SYNC +#define DMA_SYNC_POS (0U) +#define DMA_SYNC_LEN (32U) +#define DMA_SYNC_MSK (((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS) +#define DMA_SYNC_UMSK (~(((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS)) + +#if 0 +/* 0x100 : DMA_C0SrcAddr */ +#define DMA_C0SRCADDR_OFFSET (0x100) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x104 : DMA_C0DstAddr */ +#define DMA_C0DSTADDR_OFFSET (0x104) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x108 : DMA_C0LLI */ +#define DMA_C0LLI_OFFSET (0x108) +#define DMA_LLI DMA_LLI +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x10C : DMA_C0Control */ +#define DMA_C0CONTROL_OFFSET (0x10C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (2U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (2U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SLARGERD DMA_SLARGERD +#define DMA_SLARGERD_POS (25U) +#define DMA_SLARGERD_LEN (1U) +#define DMA_SLARGERD_MSK (((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS) +#define DMA_SLARGERD_UMSK (~(((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x110 : DMA_C0Config */ +#define DMA_C0CONFIG_OFFSET (0x110) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) +#define DMA_LLICOUNTER DMA_LLICOUNTER +#define DMA_LLICOUNTER_POS (20U) +#define DMA_LLICOUNTER_LEN (10U) +#define DMA_LLICOUNTER_MSK (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS) +#define DMA_LLICOUNTER_UMSK (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)) + +/* 0x200 : DMA_C1SrcAddr */ +#define DMA_C1SRCADDR_OFFSET (0x200) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x204 : DMA_C1DstAddr */ +#define DMA_C1DSTADDR_OFFSET (0x204) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x208 : DMA_C1LLI */ +#define DMA_C1LLI_OFFSET (0x208) +#define DMA_LLI DMA_LLI +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x20C : DMA_C1Control */ +#define DMA_C1CONTROL_OFFSET (0x20C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x210 : DMA_C1Config */ +#define DMA_C1CONFIG_OFFSET (0x210) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +/* 0x300 : DMA_C2SrcAddr */ +#define DMA_C2SRCADDR_OFFSET (0x300) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x304 : DMA_C2DstAddr */ +#define DMA_C2DSTADDR_OFFSET (0x304) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x308 : DMA_C2LLI */ +#define DMA_C2LLI_OFFSET (0x308) +#define DMA_LLI DMA_LLI +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x30C : DMA_C2Control */ +#define DMA_C2CONTROL_OFFSET (0x30C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x310 : DMA_C2Config */ +#define DMA_C2CONFIG_OFFSET (0x310) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +/* 0x400 : DMA_C3SrcAddr */ +#define DMA_C3SRCADDR_OFFSET (0x400) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x404 : DMA_C3DstAddr */ +#define DMA_C3DSTADDR_OFFSET (0x404) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x408 : DMA_C3LLI */ +#define DMA_C3LLI_OFFSET (0x408) +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x40C : DMA_C3Control */ +#define DMA_C3CONTROL_OFFSET (0x40C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x410 : DMA_C3Config */ +#define DMA_C3CONFIG_OFFSET (0x410) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +/* 0x500 : DMA_C4SrcAddr */ +#define DMA_C4SRCADDR_OFFSET (0x500) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x504 : DMA_C4DstAddr */ +#define DMA_C4DSTADDR_OFFSET (0x504) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x508 : DMA_C4LLI */ +#define DMA_C4LLI_OFFSET (0x508) +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x50C : DMA_C4Control */ +#define DMA_C4CONTROL_OFFSET (0x50C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x510 : DMA_C4Config */ +#define DMA_C4CONFIG_OFFSET (0x510) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +/* 0x600 : DMA_C5SrcAddr */ +#define DMA_C5SRCADDR_OFFSET (0x600) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x604 : DMA_C5DstAddr */ +#define DMA_C5DSTADDR_OFFSET (0x604) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x608 : DMA_C5LLI */ +#define DMA_C5LLI_OFFSET (0x608) +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x60C : DMA_C5Control */ +#define DMA_C5CONTROL_OFFSET (0x60C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x610 : DMA_C5Config */ +#define DMA_C5CONFIG_OFFSET (0x610) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +/* 0x700 : DMA_C6SrcAddr */ +#define DMA_C6SRCADDR_OFFSET (0x700) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x704 : DMA_C6DstAddr */ +#define DMA_C6DSTADDR_OFFSET (0x704) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x708 : DMA_C6LLI */ +#define DMA_C6LLI_OFFSET (0x708) +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x70C : DMA_C6Control */ +#define DMA_C6CONTROL_OFFSET (0x70C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x710 : DMA_C6Config */ +#define DMA_C6CONFIG_OFFSET (0x710) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + +/* 0x800 : DMA_C7SrcAddr */ +#define DMA_C7SRCADDR_OFFSET (0x800) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x804 : DMA_C7DstAddr */ +#define DMA_C7DSTADDR_OFFSET (0x804) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x808 : DMA_C7LLI */ +#define DMA_C7LLI_OFFSET (0x808) +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0x80C : DMA_C7Control */ +#define DMA_C7CONTROL_OFFSET (0x80C) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (3U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (3U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x810 : DMA_C7Config */ +#define DMA_C7CONFIG_OFFSET (0x810) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) + + +struct dma_reg +{ + /* 0x0 : DMA_IntStatus */ + union + { + struct + { + uint32_t IntStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntStatus; + + /* 0x4 : DMA_IntTCStatus */ + union + { + struct + { + uint32_t IntTCStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntTCStatus; + + /* 0x8 : DMA_IntTCClear */ + union + { + struct + { + uint32_t IntTCClear : 8; /* [ 7: 0], w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntTCClear; + + /* 0xC : DMA_IntErrorStatus */ + union + { + struct + { + uint32_t IntErrorStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntErrorStatus; + + /* 0x10 : DMA_IntErrClr */ + union + { + struct + { + uint32_t IntErrClr : 8; /* [ 7: 0], w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_IntErrClr; + + /* 0x14 : DMA_RawIntTCStatus */ + union + { + struct + { + uint32_t RawIntTCStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_RawIntTCStatus; + + /* 0x18 : DMA_RawIntErrorStatus */ + union + { + struct + { + uint32_t RawIntErrorStatus : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_RawIntErrorStatus; + + /* 0x1C : DMA_EnbldChns */ + union + { + struct + { + uint32_t EnabledChannels : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_EnbldChns; + + /* 0x20 : DMA_SoftBReq */ + union + { + struct + { + uint32_t SoftBReq : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SoftBReq; + + /* 0x24 : DMA_SoftSReq */ + union + { + struct + { + uint32_t SoftSReq : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SoftSReq; + + /* 0x28 : DMA_SoftLBReq */ + union + { + struct + { + uint32_t SoftLBReq : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SoftLBReq; + + /* 0x2C : DMA_SoftLSReq */ + union + { + struct + { + uint32_t SoftLSReq : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SoftLSReq; + + /* 0x30 : DMA_Top_Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t M : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_Top_Config; + + /* 0x34 : DMA_Sync */ + union + { + struct + { + uint32_t DMA_Sync : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_Sync; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[200]; + + /* 0x100 : DMA_C0SrcAddr */ + union + { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0SrcAddr; + + /* 0x104 : DMA_C0DstAddr */ + union + { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0DstAddr; + + /* 0x108 : DMA_C0LLI */ + union + { + struct + { + uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0LLI; + + /* 0x10C : DMA_C0Control */ + union + { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0Control; + + /* 0x110 : DMA_C0Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C0Config; + + /* 0x114 reserved */ + uint8_t RESERVED0x114[236]; + + /* 0x200 : DMA_C1SrcAddr */ + union + { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1SrcAddr; + + /* 0x204 : DMA_C1DstAddr */ + union + { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1DstAddr; + + /* 0x208 : DMA_C1LLI */ + union + { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1LLI; + + /* 0x20C : DMA_C1Control */ + union + { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1Control; + + /* 0x210 : DMA_C1Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C1Config; + + /* 0x214 reserved */ + uint8_t RESERVED0x214[236]; + + /* 0x300 : DMA_C2SrcAddr */ + union + { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2SrcAddr; + + /* 0x304 : DMA_C2DstAddr */ + union + { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2DstAddr; + + /* 0x308 : DMA_C2LLI */ + union + { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2LLI; + + /* 0x30C : DMA_C2Control */ + union + { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2Control; + + /* 0x310 : DMA_C2Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C2Config; + + /* 0x314 reserved */ + uint8_t RESERVED0x314[236]; + + /* 0x400 : DMA_C3SrcAddr */ + union + { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3SrcAddr; + + /* 0x404 : DMA_C3DstAddr */ + union + { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3DstAddr; + + /* 0x408 : DMA_C3LLI */ + union + { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3LLI; + + /* 0x40C : DMA_C3Control */ + union + { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3Control; + + /* 0x410 : DMA_C3Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C3Config; + + /* 0x414 reserved */ + uint8_t RESERVED0x414[236]; + + /* 0x500 : DMA_C4SrcAddr */ + union + { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C4SrcAddr; + + /* 0x504 : DMA_C4DstAddr */ + union + { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C4DstAddr; + + /* 0x508 : DMA_C4LLI */ + union + { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C4LLI; + + /* 0x50C : DMA_C4Control */ + union + { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C4Control; + + /* 0x510 : DMA_C4Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C4Config; + + /* 0x514 reserved */ + uint8_t RESERVED0x514[236]; + + /* 0x600 : DMA_C5SrcAddr */ + union + { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C5SrcAddr; + + /* 0x604 : DMA_C5DstAddr */ + union + { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C5DstAddr; + + /* 0x608 : DMA_C5LLI */ + union + { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C5LLI; + + /* 0x60C : DMA_C5Control */ + union + { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C5Control; + + /* 0x610 : DMA_C5Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C5Config; + + /* 0x614 reserved */ + uint8_t RESERVED0x614[236]; + + /* 0x700 : DMA_C6SrcAddr */ + union + { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C6SrcAddr; + + /* 0x704 : DMA_C6DstAddr */ + union + { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C6DstAddr; + + /* 0x708 : DMA_C6LLI */ + union + { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C6LLI; + + /* 0x70C : DMA_C6Control */ + union + { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C6Control; + + /* 0x710 : DMA_C6Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C6Config; + + /* 0x714 reserved */ + uint8_t RESERVED0x714[236]; + + /* 0x800 : DMA_C7SrcAddr */ + union + { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C7SrcAddr; + + /* 0x804 : DMA_C7DstAddr */ + union + { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C7DstAddr; + + /* 0x808 : DMA_C7LLI */ + union + { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t LLI : 30; /* [31: 2], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C7LLI; + + /* 0x80C : DMA_C7Control */ + union + { + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C7Control; + + /* 0x810 : DMA_C7Config */ + union + { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_C7Config; + +}; +#endif + +typedef volatile struct dma_reg dma_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : DMA_SrcAddr */ +#define DMA_SRCADDR_OFFSET (0x0) +#define DMA_SRCADDR DMA_SRCADDR +#define DMA_SRCADDR_POS (0U) +#define DMA_SRCADDR_LEN (32U) +#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) +#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) + +/* 0x4 : DMA_DstAddr */ +#define DMA_DSTADDR_OFFSET (0x4) +#define DMA_DSTADDR DMA_DSTADDR +#define DMA_DSTADDR_POS (0U) +#define DMA_DSTADDR_LEN (32U) +#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) +#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) + +/* 0x8 : DMA_LLI */ +#define DMA_LLI_OFFSET (0x8) +#define DMA_LLI DMA_LLI +#define DMA_LLI_POS (0U) +#define DMA_LLI_LEN (32U) +#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) +#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) + +/* 0xc : DMA_Control */ +#define DMA_CONTROL_OFFSET (0xc) +#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE +#define DMA_TRANSFERSIZE_POS (0U) +#define DMA_TRANSFERSIZE_LEN (12U) +#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) +#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) +#define DMA_SBSIZE DMA_SBSIZE +#define DMA_SBSIZE_POS (12U) +#define DMA_SBSIZE_LEN (2U) +#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) +#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) +#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE +#define DMA_DST_MIN_MODE_POS (14U) +#define DMA_DST_MIN_MODE_LEN (1U) +#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) +#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) +#define DMA_DBSIZE DMA_DBSIZE +#define DMA_DBSIZE_POS (15U) +#define DMA_DBSIZE_LEN (2U) +#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) +#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) +#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE +#define DMA_DST_ADD_MODE_POS (17U) +#define DMA_DST_ADD_MODE_LEN (1U) +#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) +#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) +#define DMA_SWIDTH DMA_SWIDTH +#define DMA_SWIDTH_POS (18U) +#define DMA_SWIDTH_LEN (2U) +#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) +#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) +#define DMA_DWIDTH DMA_DWIDTH +#define DMA_DWIDTH_POS (21U) +#define DMA_DWIDTH_LEN (2U) +#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) +#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) +#define DMA_FIX_CNT DMA_FIX_CNT +#define DMA_FIX_CNT_POS (23U) +#define DMA_FIX_CNT_LEN (2U) +#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) +#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) +#define DMA_SLARGERD DMA_SLARGERD +#define DMA_SLARGERD_POS (25U) +#define DMA_SLARGERD_LEN (1U) +#define DMA_SLARGERD_MSK (((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS) +#define DMA_SLARGERD_UMSK (~(((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS)) +#define DMA_SI DMA_SI +#define DMA_SI_POS (26U) +#define DMA_SI_LEN (1U) +#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) +#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) +#define DMA_DI DMA_DI +#define DMA_DI_POS (27U) +#define DMA_DI_LEN (1U) +#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) +#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) +#define DMA_PROT DMA_PROT +#define DMA_PROT_POS (28U) +#define DMA_PROT_LEN (3U) +#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) +#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) +#define DMA_I DMA_I +#define DMA_I_POS (31U) +#define DMA_I_LEN (1U) +#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) +#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) + +/* 0x10 : DMA_Config */ +#define DMA_CONFIG_OFFSET (0x10) +#define DMA_E DMA_E +#define DMA_E_POS (0U) +#define DMA_E_LEN (1U) +#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) +#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) +#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL +#define DMA_SRCPERIPHERAL_POS (1U) +#define DMA_SRCPERIPHERAL_LEN (5U) +#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) +#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) +#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL +#define DMA_DSTPERIPHERAL_POS (6U) +#define DMA_DSTPERIPHERAL_LEN (5U) +#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) +#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) +#define DMA_FLOWCNTRL DMA_FLOWCNTRL +#define DMA_FLOWCNTRL_POS (11U) +#define DMA_FLOWCNTRL_LEN (3U) +#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) +#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) +#define DMA_IE DMA_IE +#define DMA_IE_POS (14U) +#define DMA_IE_LEN (1U) +#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) +#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) +#define DMA_ITC DMA_ITC +#define DMA_ITC_POS (15U) +#define DMA_ITC_LEN (1U) +#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) +#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) +#define DMA_L DMA_L +#define DMA_L_POS (16U) +#define DMA_L_LEN (1U) +#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) +#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) +#define DMA_A DMA_A +#define DMA_A_POS (17U) +#define DMA_A_LEN (1U) +#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) +#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) +#define DMA_H DMA_H +#define DMA_H_POS (18U) +#define DMA_H_LEN (1U) +#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) +#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) +#define DMA_LLICOUNTER DMA_LLICOUNTER +#define DMA_LLICOUNTER_POS (20U) +#define DMA_LLICOUNTER_LEN (10U) +#define DMA_LLICOUNTER_MSK (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS) +#define DMA_LLICOUNTER_UMSK (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)) + +struct dma_channel_reg { + /* 0x0 : DMA_SrcAddr */ + union { + struct + { + uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_SrcAddr; + + /* 0x4 : DMA_DstAddr */ + union { + struct + { + uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_DstAddr; + + /* 0x8 : DMA_LLI */ + union { + struct + { + uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_LLI; + + /* 0xc : DMA_Control */ + union { + struct DMA_Control_Reg { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DMA_Control; + + /* 0x10 : DMA_Config */ + union { + struct + { + uint32_t E : 1; /* [ 0], r/w, 0x0 */ + uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ + uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ + uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ + uint32_t IE : 1; /* [ 14], r/w, 0x0 */ + uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ + uint32_t L : 1; /* [ 16], r/w, 0x0 */ + uint32_t A : 1; /* [ 17], r, 0x0 */ + uint32_t H : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } DMA_Config; +}; + +typedef volatile struct dma_channel_reg dma_channel_reg_t; + +#define DMA_CHANNEL_OFFSET 0x100 + +#endif /* __DMA_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ef_ctrl_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ef_ctrl_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..b7e95371b2e09b775f8f2c9f053231b5cf3c4f28 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ef_ctrl_reg.h @@ -0,0 +1,812 @@ +/** + ****************************************************************************** + * @file ef_ctrl_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_CTRL_REG_H__ +#define __EF_CTRL_REG_H__ + +#include "bl702.h" + +/* 0x800 : ef_if_ctrl_0 */ +#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)) +#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY +#define EF_CTRL_EF_IF_0_BUSY_POS (2U) +#define EF_CTRL_EF_IF_0_BUSY_LEN (1U) +#define EF_CTRL_EF_IF_0_BUSY_MSK (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS) +#define EF_CTRL_EF_IF_0_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)) +#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW +#define EF_CTRL_EF_IF_0_RW_POS (3U) +#define EF_CTRL_EF_IF_0_RW_LEN (1U) +#define EF_CTRL_EF_IF_0_RW_MSK (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS) +#define EF_CTRL_EF_IF_0_RW_UMSK (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)) +#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG +#define EF_CTRL_EF_IF_0_TRIG_POS (4U) +#define EF_CTRL_EF_IF_0_TRIG_LEN (1U) +#define EF_CTRL_EF_IF_0_TRIG_MSK (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS) +#define EF_CTRL_EF_IF_0_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)) +#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN +#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U) +#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U) +#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS) +#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)) +#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY +#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL EF_CTRL_EF_CLK_SAHB_DATA_SEL +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS (7U) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN (1U) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)) +#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG +#define EF_CTRL_EF_IF_POR_DIG_POS (16U) +#define EF_CTRL_EF_IF_POR_DIG_LEN (1U) +#define EF_CTRL_EF_IF_POR_DIG_MSK (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS) +#define EF_CTRL_EF_IF_POR_DIG_UMSK (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE EF_CTRL_EF_CLK_SAHB_DATA_GATE +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS (17U) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN (1U) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)) +#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN +#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U) +#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U) +#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS) +#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)) +#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT +#define EF_CTRL_EF_IF_0_INT_POS (20U) +#define EF_CTRL_EF_IF_0_INT_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_MSK (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS) +#define EF_CTRL_EF_IF_0_INT_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)) +#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR +#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U) +#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS) +#define EF_CTRL_EF_IF_0_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)) +#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET +#define EF_CTRL_EF_IF_0_INT_SET_POS (22U) +#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_SET_MSK (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS) +#define EF_CTRL_EF_IF_0_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC +#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)) + +/* 0x804 : ef_if_cyc_0 */ +#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804) +#define EF_CTRL_EF_IF_CYC_RD_DMY EF_CTRL_EF_IF_CYC_RD_DMY +#define EF_CTRL_EF_IF_CYC_RD_DMY_POS (0U) +#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS) +#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)) +#define EF_CTRL_EF_IF_CYC_RD_DAT EF_CTRL_EF_IF_CYC_RD_DAT +#define EF_CTRL_EF_IF_CYC_RD_DAT_POS (6U) +#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS) +#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)) +#define EF_CTRL_EF_IF_CYC_RD_ADR EF_CTRL_EF_IF_CYC_RD_ADR +#define EF_CTRL_EF_IF_CYC_RD_ADR_POS (12U) +#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS) +#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)) +#define EF_CTRL_EF_IF_CYC_CS EF_CTRL_EF_IF_CYC_CS +#define EF_CTRL_EF_IF_CYC_CS_POS (18U) +#define EF_CTRL_EF_IF_CYC_CS_LEN (6U) +#define EF_CTRL_EF_IF_CYC_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS) +#define EF_CTRL_EF_IF_CYC_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)) +#define EF_CTRL_EF_IF_CYC_PD_CS_S EF_CTRL_EF_IF_CYC_PD_CS_S +#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS (24U) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN (8U) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)) + +/* 0x808 : ef_if_cyc_1 */ +#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808) +#define EF_CTRL_EF_IF_CYC_PI EF_CTRL_EF_IF_CYC_PI +#define EF_CTRL_EF_IF_CYC_PI_POS (0U) +#define EF_CTRL_EF_IF_CYC_PI_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PI_MSK (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS) +#define EF_CTRL_EF_IF_CYC_PI_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)) +#define EF_CTRL_EF_IF_CYC_PP EF_CTRL_EF_IF_CYC_PP +#define EF_CTRL_EF_IF_CYC_PP_POS (6U) +#define EF_CTRL_EF_IF_CYC_PP_LEN (8U) +#define EF_CTRL_EF_IF_CYC_PP_MSK (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS) +#define EF_CTRL_EF_IF_CYC_PP_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)) +#define EF_CTRL_EF_IF_CYC_WR_ADR EF_CTRL_EF_IF_CYC_WR_ADR +#define EF_CTRL_EF_IF_CYC_WR_ADR_POS (14U) +#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN (6U) +#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS) +#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)) +#define EF_CTRL_EF_IF_CYC_PS_CS EF_CTRL_EF_IF_CYC_PS_CS +#define EF_CTRL_EF_IF_CYC_PS_CS_POS (20U) +#define EF_CTRL_EF_IF_CYC_PS_CS_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PS_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS) +#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)) +#define EF_CTRL_EF_IF_CYC_PD_CS_H EF_CTRL_EF_IF_CYC_PD_CS_H +#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS (26U) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)) + +/* 0x80C : ef_if_0_manual */ +#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C) +#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A +#define EF_CTRL_EF_IF_A_POS (0U) +#define EF_CTRL_EF_IF_A_LEN (10U) +#define EF_CTRL_EF_IF_A_MSK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS) +#define EF_CTRL_EF_IF_A_UMSK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)) +#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD +#define EF_CTRL_EF_IF_PD_POS (10U) +#define EF_CTRL_EF_IF_PD_LEN (1U) +#define EF_CTRL_EF_IF_PD_MSK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS) +#define EF_CTRL_EF_IF_PD_UMSK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)) +#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS +#define EF_CTRL_EF_IF_PS_POS (11U) +#define EF_CTRL_EF_IF_PS_LEN (1U) +#define EF_CTRL_EF_IF_PS_MSK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS) +#define EF_CTRL_EF_IF_PS_UMSK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)) +#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE +#define EF_CTRL_EF_IF_STROBE_POS (12U) +#define EF_CTRL_EF_IF_STROBE_LEN (1U) +#define EF_CTRL_EF_IF_STROBE_MSK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS) +#define EF_CTRL_EF_IF_STROBE_UMSK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)) +#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB +#define EF_CTRL_EF_IF_PGENB_POS (13U) +#define EF_CTRL_EF_IF_PGENB_LEN (1U) +#define EF_CTRL_EF_IF_PGENB_MSK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS) +#define EF_CTRL_EF_IF_PGENB_UMSK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)) +#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD +#define EF_CTRL_EF_IF_LOAD_POS (14U) +#define EF_CTRL_EF_IF_LOAD_LEN (1U) +#define EF_CTRL_EF_IF_LOAD_MSK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS) +#define EF_CTRL_EF_IF_LOAD_UMSK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)) +#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB +#define EF_CTRL_EF_IF_CSB_POS (15U) +#define EF_CTRL_EF_IF_CSB_LEN (1U) +#define EF_CTRL_EF_IF_CSB_MSK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS) +#define EF_CTRL_EF_IF_CSB_UMSK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)) +#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q +#define EF_CTRL_EF_IF_0_Q_POS (16U) +#define EF_CTRL_EF_IF_0_Q_LEN (8U) +#define EF_CTRL_EF_IF_0_Q_MSK (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS) +#define EF_CTRL_EF_IF_0_Q_UMSK (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)) + +/* 0x810 : ef_if_0_status */ +#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810) +#define EF_CTRL_EF_IF_0_STATUS EF_CTRL_EF_IF_0_STATUS +#define EF_CTRL_EF_IF_0_STATUS_POS (0U) +#define EF_CTRL_EF_IF_0_STATUS_LEN (32U) +#define EF_CTRL_EF_IF_0_STATUS_MSK (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS) +#define EF_CTRL_EF_IF_0_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)) + +/* 0x814 : ef_if_cfg_0 */ +#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814) +#define EF_CTRL_EF_IF_SF_AES_MODE EF_CTRL_EF_IF_SF_AES_MODE +#define EF_CTRL_EF_IF_SF_AES_MODE_POS (0U) +#define EF_CTRL_EF_IF_SF_AES_MODE_LEN (2U) +#define EF_CTRL_EF_IF_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS) +#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE EF_CTRL_EF_IF_SBOOT_SIGN_MODE +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS (2U) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN (2U) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)) +#define EF_CTRL_EF_IF_SBOOT_EN EF_CTRL_EF_IF_SBOOT_EN +#define EF_CTRL_EF_IF_SBOOT_EN_POS (4U) +#define EF_CTRL_EF_IF_SBOOT_EN_LEN (2U) +#define EF_CTRL_EF_IF_SBOOT_EN_MSK (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS) +#define EF_CTRL_EF_IF_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)) +#define EF_CTRL_EF_IF_CPU1_ENC_EN EF_CTRL_EF_IF_CPU1_ENC_EN +#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS (6U) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)) +#define EF_CTRL_EF_IF_CPU0_ENC_EN EF_CTRL_EF_IF_CPU0_ENC_EN +#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS (7U) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)) +#define EF_CTRL_EF_IF_BOOT_SEL EF_CTRL_EF_IF_BOOT_SEL +#define EF_CTRL_EF_IF_BOOT_SEL_POS (8U) +#define EF_CTRL_EF_IF_BOOT_SEL_LEN (4U) +#define EF_CTRL_EF_IF_BOOT_SEL_MSK (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS) +#define EF_CTRL_EF_IF_BOOT_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)) +#define EF_CTRL_EF_IF_SF_KEY_0_SEL EF_CTRL_EF_IF_SF_KEY_0_SEL +#define EF_CTRL_EF_IF_SF_KEY_0_SEL_POS (12U) +#define EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN (2U) +#define EF_CTRL_EF_IF_SF_KEY_0_SEL_MSK (((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS) +#define EF_CTRL_EF_IF_SF_KEY_0_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS)) +#define EF_CTRL_EF_IF_SDU_DIS EF_CTRL_EF_IF_SDU_DIS +#define EF_CTRL_EF_IF_SDU_DIS_POS (14U) +#define EF_CTRL_EF_IF_SDU_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SDU_DIS_MSK (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS) +#define EF_CTRL_EF_IF_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)) +#define EF_CTRL_EF_IF_BLE_DIS EF_CTRL_EF_IF_BLE_DIS +#define EF_CTRL_EF_IF_BLE_DIS_POS (15U) +#define EF_CTRL_EF_IF_BLE_DIS_LEN (1U) +#define EF_CTRL_EF_IF_BLE_DIS_MSK (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS) +#define EF_CTRL_EF_IF_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)) +#define EF_CTRL_EF_IF_WIFI_DIS EF_CTRL_EF_IF_WIFI_DIS +#define EF_CTRL_EF_IF_WIFI_DIS_POS (16U) +#define EF_CTRL_EF_IF_WIFI_DIS_LEN (1U) +#define EF_CTRL_EF_IF_WIFI_DIS_MSK (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS) +#define EF_CTRL_EF_IF_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN EF_CTRL_EF_IF_0_KEY_ENC_EN +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS (17U) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)) +#define EF_CTRL_EF_IF_CAM_DIS EF_CTRL_EF_IF_CAM_DIS +#define EF_CTRL_EF_IF_CAM_DIS_POS (18U) +#define EF_CTRL_EF_IF_CAM_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CAM_DIS_MSK (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS) +#define EF_CTRL_EF_IF_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)) +#define EF_CTRL_EF_IF_M154_DIS EF_CTRL_EF_IF_M154_DIS +#define EF_CTRL_EF_IF_M154_DIS_POS (19U) +#define EF_CTRL_EF_IF_M154_DIS_LEN (1U) +#define EF_CTRL_EF_IF_M154_DIS_MSK (((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS) +#define EF_CTRL_EF_IF_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS)) +#define EF_CTRL_EF_IF_CPU1_DIS EF_CTRL_EF_IF_CPU1_DIS +#define EF_CTRL_EF_IF_CPU1_DIS_POS (20U) +#define EF_CTRL_EF_IF_CPU1_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CPU1_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS) +#define EF_CTRL_EF_IF_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS EF_CTRL_EF_IF_CPU_RST_DBG_DIS +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS (21U) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_SE_DBG_DIS EF_CTRL_EF_IF_SE_DBG_DIS +#define EF_CTRL_EF_IF_SE_DBG_DIS_POS (22U) +#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS) +#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS EF_CTRL_EF_IF_EFUSE_DBG_DIS +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS (23U) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS EF_CTRL_EF_IF_DBG_JTAG_1_DIS +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS (24U) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN (2U) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS EF_CTRL_EF_IF_DBG_JTAG_0_DIS +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS (26U) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN (2U) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_MODE EF_CTRL_EF_IF_DBG_MODE +#define EF_CTRL_EF_IF_DBG_MODE_POS (28U) +#define EF_CTRL_EF_IF_DBG_MODE_LEN (4U) +#define EF_CTRL_EF_IF_DBG_MODE_MSK (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS) +#define EF_CTRL_EF_IF_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)) + +/* 0x818 : ef_sw_cfg_0 */ +#define EF_CTRL_EF_SW_CFG_0_OFFSET (0x818) +#define EF_CTRL_EF_SW_SF_AES_MODE EF_CTRL_EF_SW_SF_AES_MODE +#define EF_CTRL_EF_SW_SF_AES_MODE_POS (0U) +#define EF_CTRL_EF_SW_SF_AES_MODE_LEN (2U) +#define EF_CTRL_EF_SW_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS) +#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE EF_CTRL_EF_SW_SBOOT_SIGN_MODE +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS (2U) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN (2U) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)) +#define EF_CTRL_EF_SW_SBOOT_EN EF_CTRL_EF_SW_SBOOT_EN +#define EF_CTRL_EF_SW_SBOOT_EN_POS (4U) +#define EF_CTRL_EF_SW_SBOOT_EN_LEN (2U) +#define EF_CTRL_EF_SW_SBOOT_EN_MSK (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS) +#define EF_CTRL_EF_SW_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)) +#define EF_CTRL_EF_SW_CPU1_ENC_EN EF_CTRL_EF_SW_CPU1_ENC_EN +#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS (6U) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)) +#define EF_CTRL_EF_SW_CPU0_ENC_EN EF_CTRL_EF_SW_CPU0_ENC_EN +#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS (7U) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)) +#define EF_CTRL_EF_SW_SF_KEY_0_SEL EF_CTRL_EF_SW_SF_KEY_0_SEL +#define EF_CTRL_EF_SW_SF_KEY_0_SEL_POS (12U) +#define EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN (2U) +#define EF_CTRL_EF_SW_SF_KEY_0_SEL_MSK (((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS) +#define EF_CTRL_EF_SW_SF_KEY_0_SEL_UMSK (~(((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS)) +#define EF_CTRL_EF_SW_SDU_DIS EF_CTRL_EF_SW_SDU_DIS +#define EF_CTRL_EF_SW_SDU_DIS_POS (14U) +#define EF_CTRL_EF_SW_SDU_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SDU_DIS_MSK (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS) +#define EF_CTRL_EF_SW_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)) +#define EF_CTRL_EF_SW_BLE_DIS EF_CTRL_EF_SW_BLE_DIS +#define EF_CTRL_EF_SW_BLE_DIS_POS (15U) +#define EF_CTRL_EF_SW_BLE_DIS_LEN (1U) +#define EF_CTRL_EF_SW_BLE_DIS_MSK (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS) +#define EF_CTRL_EF_SW_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)) +#define EF_CTRL_EF_SW_WIFI_DIS EF_CTRL_EF_SW_WIFI_DIS +#define EF_CTRL_EF_SW_WIFI_DIS_POS (16U) +#define EF_CTRL_EF_SW_WIFI_DIS_LEN (1U) +#define EF_CTRL_EF_SW_WIFI_DIS_MSK (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS) +#define EF_CTRL_EF_SW_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN EF_CTRL_EF_SW_0_KEY_ENC_EN +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS (17U) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)) +#define EF_CTRL_EF_SW_CAM_DIS EF_CTRL_EF_SW_CAM_DIS +#define EF_CTRL_EF_SW_CAM_DIS_POS (18U) +#define EF_CTRL_EF_SW_CAM_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CAM_DIS_MSK (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS) +#define EF_CTRL_EF_SW_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)) +#define EF_CTRL_EF_SW_M154_DIS EF_CTRL_EF_SW_M154_DIS +#define EF_CTRL_EF_SW_M154_DIS_POS (19U) +#define EF_CTRL_EF_SW_M154_DIS_LEN (1U) +#define EF_CTRL_EF_SW_M154_DIS_MSK (((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS) +#define EF_CTRL_EF_SW_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS)) +#define EF_CTRL_EF_SW_CPU1_DIS EF_CTRL_EF_SW_CPU1_DIS +#define EF_CTRL_EF_SW_CPU1_DIS_POS (20U) +#define EF_CTRL_EF_SW_CPU1_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CPU1_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS) +#define EF_CTRL_EF_SW_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS EF_CTRL_EF_SW_CPU_RST_DBG_DIS +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS (21U) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_SE_DBG_DIS EF_CTRL_EF_SW_SE_DBG_DIS +#define EF_CTRL_EF_SW_SE_DBG_DIS_POS (22U) +#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS) +#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS EF_CTRL_EF_SW_EFUSE_DBG_DIS +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS (23U) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS EF_CTRL_EF_SW_DBG_JTAG_1_DIS +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS (24U) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN (2U) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS EF_CTRL_EF_SW_DBG_JTAG_0_DIS +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS (26U) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN (2U) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_MODE EF_CTRL_EF_SW_DBG_MODE +#define EF_CTRL_EF_SW_DBG_MODE_POS (28U) +#define EF_CTRL_EF_SW_DBG_MODE_LEN (4U) +#define EF_CTRL_EF_SW_DBG_MODE_MSK (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS) +#define EF_CTRL_EF_SW_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)) + +/* 0x81C : ef_reserved */ +#define EF_CTRL_EF_RESERVED_OFFSET (0x81C) +#define EF_CTRL_EF_RESERVED EF_CTRL_EF_RESERVED +#define EF_CTRL_EF_RESERVED_POS (0U) +#define EF_CTRL_EF_RESERVED_LEN (32U) +#define EF_CTRL_EF_RESERVED_MSK (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS) +#define EF_CTRL_EF_RESERVED_UMSK (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)) + +/* 0x820 : ef_if_ana_trim_0 */ +#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820) +#define EF_CTRL_EF_IF_ANA_TRIM_0 EF_CTRL_EF_IF_ANA_TRIM_0 +#define EF_CTRL_EF_IF_ANA_TRIM_0_POS (0U) +#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN (32U) +#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS) +#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)) + +/* 0x824 : ef_if_sw_usage_0 */ +#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824) +#define EF_CTRL_EF_IF_SW_USAGE_0 EF_CTRL_EF_IF_SW_USAGE_0 +#define EF_CTRL_EF_IF_SW_USAGE_0_POS (0U) +#define EF_CTRL_EF_IF_SW_USAGE_0_LEN (32U) +#define EF_CTRL_EF_IF_SW_USAGE_0_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS) +#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)) + +/* 0xA00 : ef_crc_ctrl_0 */ +#define EF_CTRL_EF_CRC_CTRL_0_OFFSET (0xA00) +#define EF_CTRL_EF_CRC_BUSY EF_CTRL_EF_CRC_BUSY +#define EF_CTRL_EF_CRC_BUSY_POS (0U) +#define EF_CTRL_EF_CRC_BUSY_LEN (1U) +#define EF_CTRL_EF_CRC_BUSY_MSK (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS) +#define EF_CTRL_EF_CRC_BUSY_UMSK (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)) +#define EF_CTRL_EF_CRC_TRIG EF_CTRL_EF_CRC_TRIG +#define EF_CTRL_EF_CRC_TRIG_POS (1U) +#define EF_CTRL_EF_CRC_TRIG_LEN (1U) +#define EF_CTRL_EF_CRC_TRIG_MSK (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS) +#define EF_CTRL_EF_CRC_TRIG_UMSK (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)) +#define EF_CTRL_EF_CRC_EN EF_CTRL_EF_CRC_EN +#define EF_CTRL_EF_CRC_EN_POS (2U) +#define EF_CTRL_EF_CRC_EN_LEN (1U) +#define EF_CTRL_EF_CRC_EN_MSK (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS) +#define EF_CTRL_EF_CRC_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)) +#define EF_CTRL_EF_CRC_MODE EF_CTRL_EF_CRC_MODE +#define EF_CTRL_EF_CRC_MODE_POS (3U) +#define EF_CTRL_EF_CRC_MODE_LEN (1U) +#define EF_CTRL_EF_CRC_MODE_MSK (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS) +#define EF_CTRL_EF_CRC_MODE_UMSK (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)) +#define EF_CTRL_EF_CRC_ERROR EF_CTRL_EF_CRC_ERROR +#define EF_CTRL_EF_CRC_ERROR_POS (4U) +#define EF_CTRL_EF_CRC_ERROR_LEN (1U) +#define EF_CTRL_EF_CRC_ERROR_MSK (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS) +#define EF_CTRL_EF_CRC_ERROR_UMSK (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)) +#define EF_CTRL_EF_CRC_DOUT_INV_EN EF_CTRL_EF_CRC_DOUT_INV_EN +#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS (5U) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN (1U) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN EF_CTRL_EF_CRC_DOUT_ENDIAN +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS (6U) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN (1U) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)) +#define EF_CTRL_EF_CRC_DIN_ENDIAN EF_CTRL_EF_CRC_DIN_ENDIAN +#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS (7U) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN (1U) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)) +#define EF_CTRL_EF_CRC_INT EF_CTRL_EF_CRC_INT +#define EF_CTRL_EF_CRC_INT_POS (8U) +#define EF_CTRL_EF_CRC_INT_LEN (1U) +#define EF_CTRL_EF_CRC_INT_MSK (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS) +#define EF_CTRL_EF_CRC_INT_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)) +#define EF_CTRL_EF_CRC_INT_CLR EF_CTRL_EF_CRC_INT_CLR +#define EF_CTRL_EF_CRC_INT_CLR_POS (9U) +#define EF_CTRL_EF_CRC_INT_CLR_LEN (1U) +#define EF_CTRL_EF_CRC_INT_CLR_MSK (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS) +#define EF_CTRL_EF_CRC_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)) +#define EF_CTRL_EF_CRC_INT_SET EF_CTRL_EF_CRC_INT_SET +#define EF_CTRL_EF_CRC_INT_SET_POS (10U) +#define EF_CTRL_EF_CRC_INT_SET_LEN (1U) +#define EF_CTRL_EF_CRC_INT_SET_MSK (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS) +#define EF_CTRL_EF_CRC_INT_SET_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)) +#define EF_CTRL_EF_CRC_LOCK EF_CTRL_EF_CRC_LOCK +#define EF_CTRL_EF_CRC_LOCK_POS (11U) +#define EF_CTRL_EF_CRC_LOCK_LEN (1U) +#define EF_CTRL_EF_CRC_LOCK_MSK (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS) +#define EF_CTRL_EF_CRC_LOCK_UMSK (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)) +#define EF_CTRL_EF_CRC_SLP_N EF_CTRL_EF_CRC_SLP_N +#define EF_CTRL_EF_CRC_SLP_N_POS (16U) +#define EF_CTRL_EF_CRC_SLP_N_LEN (16U) +#define EF_CTRL_EF_CRC_SLP_N_MSK (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS) +#define EF_CTRL_EF_CRC_SLP_N_UMSK (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)) + +/* 0xA04 : ef_crc_ctrl_1 */ +#define EF_CTRL_EF_CRC_CTRL_1_OFFSET (0xA04) +#define EF_CTRL_EF_CRC_DATA_0_EN EF_CTRL_EF_CRC_DATA_0_EN +#define EF_CTRL_EF_CRC_DATA_0_EN_POS (0U) +#define EF_CTRL_EF_CRC_DATA_0_EN_LEN (32U) +#define EF_CTRL_EF_CRC_DATA_0_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS) +#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)) + +/* 0xA08 : ef_crc_ctrl_2 */ +#define EF_CTRL_EF_CRC_CTRL_2_OFFSET (0xA08) +#define EF_CTRL_EF_CRC_DATA_1_EN EF_CTRL_EF_CRC_DATA_1_EN +#define EF_CTRL_EF_CRC_DATA_1_EN_POS (0U) +#define EF_CTRL_EF_CRC_DATA_1_EN_LEN (32U) +#define EF_CTRL_EF_CRC_DATA_1_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS) +#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)) + +/* 0xA0C : ef_crc_ctrl_3 */ +#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C) +#define EF_CTRL_EF_CRC_IV EF_CTRL_EF_CRC_IV +#define EF_CTRL_EF_CRC_IV_POS (0U) +#define EF_CTRL_EF_CRC_IV_LEN (32U) +#define EF_CTRL_EF_CRC_IV_MSK (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS) +#define EF_CTRL_EF_CRC_IV_UMSK (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)) + +/* 0xA10 : ef_crc_ctrl_4 */ +#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10) +#define EF_CTRL_EF_CRC_GOLDEN EF_CTRL_EF_CRC_GOLDEN +#define EF_CTRL_EF_CRC_GOLDEN_POS (0U) +#define EF_CTRL_EF_CRC_GOLDEN_LEN (32U) +#define EF_CTRL_EF_CRC_GOLDEN_MSK (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS) +#define EF_CTRL_EF_CRC_GOLDEN_UMSK (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)) + +/* 0xA14 : ef_crc_ctrl_5 */ +#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14) +#define EF_CTRL_EF_CRC_DOUT EF_CTRL_EF_CRC_DOUT +#define EF_CTRL_EF_CRC_DOUT_POS (0U) +#define EF_CTRL_EF_CRC_DOUT_LEN (32U) +#define EF_CTRL_EF_CRC_DOUT_MSK (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS) +#define EF_CTRL_EF_CRC_DOUT_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)) + +struct ef_ctrl_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[2048]; + + /* 0x800 : ef_if_ctrl_0 */ + union { + struct + { + uint32_t ef_if_0_autoload_p1_done : 1; /* [ 0], r, 0x1 */ + uint32_t ef_if_0_autoload_done : 1; /* [ 1], r, 0x1 */ + uint32_t ef_if_0_busy : 1; /* [ 2], r, 0x0 */ + uint32_t ef_if_0_rw : 1; /* [ 3], r/w, 0x0 */ + uint32_t ef_if_0_trig : 1; /* [ 4], r/w, 0x0 */ + uint32_t ef_if_0_manual_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t ef_if_0_cyc_modify : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_clk_sahb_data_sel : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_if_prot_code_ctrl : 8; /* [15: 8], r/w, 0x0 */ + uint32_t ef_if_por_dig : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_clk_sahb_data_gate : 1; /* [ 17], r/w, 0x0 */ + uint32_t ef_if_auto_rd_en : 1; /* [ 18], r/w, 0x1 */ + uint32_t ef_if_cyc_modify_lock : 1; /* [ 19], r/w, 0x0 */ + uint32_t ef_if_0_int : 1; /* [ 20], r, 0x0 */ + uint32_t ef_if_0_int_clr : 1; /* [ 21], r/w, 0x1 */ + uint32_t ef_if_0_int_set : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t ef_if_prot_code_cyc : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_ctrl_0; + + /* 0x804 : ef_if_cyc_0 */ + union { + struct + { + uint32_t ef_if_cyc_rd_dmy : 6; /* [ 5: 0], r/w, 0x0 */ + uint32_t ef_if_cyc_rd_dat : 6; /* [11: 6], r/w, 0x1 */ + uint32_t ef_if_cyc_rd_adr : 6; /* [17:12], r/w, 0x0 */ + uint32_t ef_if_cyc_cs : 6; /* [23:18], r/w, 0x0 */ + uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24], r/w, 0x16 */ + } BF; + uint32_t WORD; + } ef_if_cyc_0; + + /* 0x808 : ef_if_cyc_1 */ + union { + struct + { + uint32_t ef_if_cyc_pi : 6; /* [ 5: 0], r/w, 0x9 */ + uint32_t ef_if_cyc_pp : 8; /* [13: 6], r/w, 0x98 */ + uint32_t ef_if_cyc_wr_adr : 6; /* [19:14], r/w, 0x1 */ + uint32_t ef_if_cyc_ps_cs : 6; /* [25:20], r/w, 0x2 */ + uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_cyc_1; + + /* 0x80C : ef_if_0_manual */ + union { + struct + { + uint32_t ef_if_a : 10; /* [ 9: 0], r/w, 0x0 */ + uint32_t ef_if_pd : 1; /* [ 10], r/w, 0x1 */ + uint32_t ef_if_ps : 1; /* [ 11], r/w, 0x0 */ + uint32_t ef_if_strobe : 1; /* [ 12], r/w, 0x0 */ + uint32_t ef_if_pgenb : 1; /* [ 13], r/w, 0x1 */ + uint32_t ef_if_load : 1; /* [ 14], r/w, 0x1 */ + uint32_t ef_if_csb : 1; /* [ 15], r/w, 0x1 */ + uint32_t ef_if_0_q : 8; /* [23:16], r, 0x0 */ + uint32_t ef_if_prot_code_manual : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_0_manual; + + /* 0x810 : ef_if_0_status */ + union { + struct + { + uint32_t ef_if_0_status : 32; /* [31: 0], r, 0xe400 */ + } BF; + uint32_t WORD; + } ef_if_0_status; + + /* 0x814 : ef_if_cfg_0 */ + union { + struct + { + uint32_t ef_if_sf_aes_mode : 2; /* [ 1: 0], r, 0x0 */ + uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2], r, 0x0 */ + uint32_t ef_if_sboot_en : 2; /* [ 5: 4], r, 0x0 */ + uint32_t ef_if_cpu1_enc_en : 1; /* [ 6], r, 0x0 */ + uint32_t ef_if_cpu0_enc_en : 1; /* [ 7], r, 0x0 */ + uint32_t ef_if_boot_sel : 4; /* [11: 8], r, 0x0 */ + uint32_t ef_if_sf_key_0_sel : 2; /* [13:12], r, 0x0 */ + uint32_t ef_if_sdu_dis : 1; /* [ 14], r, 0x0 */ + uint32_t ef_if_ble_dis : 1; /* [ 15], r, 0x0 */ + uint32_t ef_if_wifi_dis : 1; /* [ 16], r, 0x0 */ + uint32_t ef_if_0_key_enc_en : 1; /* [ 17], r, 0x0 */ + uint32_t ef_if_cam_dis : 1; /* [ 18], r, 0x0 */ + uint32_t ef_if_m154_dis : 1; /* [ 19], r, 0x0 */ + uint32_t ef_if_cpu1_dis : 1; /* [ 20], r, 0x0 */ + uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [ 21], r, 0x0 */ + uint32_t ef_if_se_dbg_dis : 1; /* [ 22], r, 0x0 */ + uint32_t ef_if_efuse_dbg_dis : 1; /* [ 23], r, 0x0 */ + uint32_t ef_if_dbg_jtag_1_dis : 2; /* [25:24], r, 0x0 */ + uint32_t ef_if_dbg_jtag_0_dis : 2; /* [27:26], r, 0x0 */ + uint32_t ef_if_dbg_mode : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_cfg_0; + + /* 0x818 : ef_sw_cfg_0 */ + union { + struct + { + uint32_t ef_sw_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t ef_sw_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t ef_sw_cpu1_enc_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_sw_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t ef_sw_sf_key_0_sel : 2; /* [13:12], r/w, 0x0 */ + uint32_t ef_sw_sdu_dis : 1; /* [ 14], r/w, 0x0 */ + uint32_t ef_sw_ble_dis : 1; /* [ 15], r/w, 0x0 */ + uint32_t ef_sw_wifi_dis : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_sw_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t ef_sw_cam_dis : 1; /* [ 18], r/w, 0x0 */ + uint32_t ef_sw_m154_dis : 1; /* [ 19], r/w, 0x0 */ + uint32_t ef_sw_cpu1_dis : 1; /* [ 20], r/w, 0x0 */ + uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */ + uint32_t ef_sw_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */ + uint32_t ef_sw_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */ + uint32_t ef_sw_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */ + uint32_t ef_sw_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ + uint32_t ef_sw_dbg_mode : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_sw_cfg_0; + + /* 0x81C : ef_reserved */ + union { + struct + { + uint32_t ef_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } ef_reserved; + + /* 0x820 : ef_if_ana_trim_0 */ + union { + struct + { + uint32_t ef_if_ana_trim_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_ana_trim_0; + + /* 0x824 : ef_if_sw_usage_0 */ + union { + struct + { + uint32_t ef_if_sw_usage_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_sw_usage_0; + + /* 0x828 reserved */ + uint8_t RESERVED0x828[472]; + + /* 0xA00 : ef_crc_ctrl_0 */ + union { + struct + { + uint32_t ef_crc_busy : 1; /* [ 0], r, 0x0 */ + uint32_t ef_crc_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t ef_crc_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t ef_crc_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t ef_crc_error : 1; /* [ 4], r, 0x0 */ + uint32_t ef_crc_dout_inv_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t ef_crc_dout_endian : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_crc_din_endian : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_crc_int : 1; /* [ 8], r, 0x0 */ + uint32_t ef_crc_int_clr : 1; /* [ 9], r/w, 0x1 */ + uint32_t ef_crc_int_set : 1; /* [ 10], r/w, 0x0 */ + uint32_t ef_crc_lock : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t ef_crc_slp_n : 16; /* [31:16], r/w, 0xff */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_0; + + /* 0xA04 : ef_crc_ctrl_1 */ + union { + struct + { + uint32_t ef_crc_data_0_en : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_1; + + /* 0xA08 : ef_crc_ctrl_2 */ + union { + struct + { + uint32_t ef_crc_data_1_en : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_2; + + /* 0xA0C : ef_crc_ctrl_3 */ + union { + struct + { + uint32_t ef_crc_iv : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_3; + + /* 0xA10 : ef_crc_ctrl_4 */ + union { + struct + { + uint32_t ef_crc_golden : 32; /* [31: 0], r/w, 0xc2a8fa9dL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_4; + + /* 0xA14 : ef_crc_ctrl_5 */ + union { + struct + { + uint32_t ef_crc_dout : 32; /* [31: 0], r, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_5; +}; + +typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t; + +#endif /* __EF_CTRL_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ef_data_0_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ef_data_0_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..84dec1d3382eb6bbf28bf87f06193555240f9904 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ef_data_0_reg.h @@ -0,0 +1,762 @@ +/** + ****************************************************************************** + * @file ef_data_0_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_DATA_0_REG_H__ +#define __EF_DATA_0_REG_H__ + +#include "bl702.h" + +/* 0x0 : ef_cfg_0 */ +#define EF_DATA_0_EF_CFG_0_OFFSET (0x0) +#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE +#define EF_DATA_0_EF_SF_AES_MODE_POS (0U) +#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U) +#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS) +#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (2U) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)) +#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN +#define EF_DATA_0_EF_SBOOT_EN_POS (4U) +#define EF_DATA_0_EF_SBOOT_EN_LEN (2U) +#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS) +#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)) +#define EF_DATA_0_EF_CPU0_ENC_EN EF_DATA_0_EF_CPU0_ENC_EN +#define EF_DATA_0_EF_CPU0_ENC_EN_POS (7U) +#define EF_DATA_0_EF_CPU0_ENC_EN_LEN (1U) +#define EF_DATA_0_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS) +#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)) +#define EF_DATA_0_EF_BOOT_SEL EF_DATA_0_EF_BOOT_SEL +#define EF_DATA_0_EF_BOOT_SEL_POS (8U) +#define EF_DATA_0_EF_BOOT_SEL_LEN (4U) +#define EF_DATA_0_EF_BOOT_SEL_MSK (((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS) +#define EF_DATA_0_EF_BOOT_SEL_UMSK (~(((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS)) +#define EF_DATA_0_EF_SF_KEY_0_SEL EF_DATA_0_EF_SF_KEY_0_SEL +#define EF_DATA_0_EF_SF_KEY_0_SEL_POS (12U) +#define EF_DATA_0_EF_SF_KEY_0_SEL_LEN (2U) +#define EF_DATA_0_EF_SF_KEY_0_SEL_MSK (((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS) +#define EF_DATA_0_EF_SF_KEY_0_SEL_UMSK (~(((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS)) +#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN +#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U) +#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U) +#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS) +#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)) +#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE +#define EF_DATA_0_EF_DBG_MODE_POS (28U) +#define EF_DATA_0_EF_DBG_MODE_LEN (4U) +#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS) +#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)) + +/* 0x4 : ef_dbg_pwd_low */ +#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4) +#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW +#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U) +#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U) +#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS) +#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)) + +/* 0x8 : ef_dbg_pwd_high */ +#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8) +#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH +#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U) +#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U) +#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS) +#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)) + +/* 0xC : ef_ana_trim_0 */ +#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC) +#define EF_DATA_0_EF_ANA_TRIM_0 EF_DATA_0_EF_ANA_TRIM_0 +#define EF_DATA_0_EF_ANA_TRIM_0_POS (0U) +#define EF_DATA_0_EF_ANA_TRIM_0_LEN (32U) +#define EF_DATA_0_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS) +#define EF_DATA_0_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)) + +/* 0x10 : ef_sw_usage_0 */ +#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10) +#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0 +#define EF_DATA_0_EF_SW_USAGE_0_POS (0U) +#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U) +#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS) +#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)) + +/* 0x14 : ef_wifi_mac_low */ +#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14) +#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW +#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U) +#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U) +#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS) +#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)) + +/* 0x18 : ef_wifi_mac_high */ +#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18) +#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH +#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)) + +/* 0x1C : ef_key_slot_0_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C) +#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0 +#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)) + +/* 0x20 : ef_key_slot_0_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20) +#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1 +#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)) + +/* 0x24 : ef_key_slot_0_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24) +#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2 +#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)) + +/* 0x28 : ef_key_slot_0_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28) +#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3 +#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)) + +/* 0x2C : ef_key_slot_1_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C) +#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0 +#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)) + +/* 0x30 : ef_key_slot_1_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30) +#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1 +#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)) + +/* 0x34 : ef_key_slot_1_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34) +#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2 +#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)) + +/* 0x38 : ef_key_slot_1_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38) +#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3 +#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)) + +/* 0x3C : ef_key_slot_2_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C) +#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0 +#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)) + +/* 0x40 : ef_key_slot_2_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40) +#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1 +#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)) + +/* 0x44 : ef_key_slot_2_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44) +#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2 +#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)) + +/* 0x48 : ef_key_slot_2_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48) +#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3 +#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)) + +/* 0x4C : ef_key_slot_3_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C) +#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0 +#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)) + +/* 0x50 : ef_key_slot_3_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50) +#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1 +#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)) + +/* 0x54 : ef_key_slot_3_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54) +#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2 +#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)) + +/* 0x58 : ef_key_slot_3_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58) +#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3 +#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)) + +/* 0x5C : ef_key_slot_4_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C) +#define EF_DATA_0_EF_KEY_SLOT_4_W0 EF_DATA_0_EF_KEY_SLOT_4_W0 +#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)) + +/* 0x60 : ef_key_slot_4_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60) +#define EF_DATA_0_EF_KEY_SLOT_4_W1 EF_DATA_0_EF_KEY_SLOT_4_W1 +#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)) + +/* 0x64 : ef_key_slot_4_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64) +#define EF_DATA_0_EF_KEY_SLOT_4_W2 EF_DATA_0_EF_KEY_SLOT_4_W2 +#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)) + +/* 0x68 : ef_key_slot_4_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68) +#define EF_DATA_0_EF_KEY_SLOT_4_W3 EF_DATA_0_EF_KEY_SLOT_4_W3 +#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)) + +/* 0x6C : ef_key_slot_5_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C) +#define EF_DATA_0_EF_KEY_SLOT_5_W0 EF_DATA_0_EF_KEY_SLOT_5_W0 +#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)) + +/* 0x70 : ef_key_slot_5_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70) +#define EF_DATA_0_EF_KEY_SLOT_5_W1 EF_DATA_0_EF_KEY_SLOT_5_W1 +#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)) + +/* 0x74 : ef_key_slot_5_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74) +#define EF_DATA_0_EF_KEY_SLOT_5_W2 EF_DATA_0_EF_KEY_SLOT_5_W2 +#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)) + +/* 0x78 : ef_key_slot_5_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78) +#define EF_DATA_0_EF_KEY_SLOT_5_W3 EF_DATA_0_EF_KEY_SLOT_5_W3 +#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)) + +/* 0x7C : ef_data_0_lock */ +#define EF_DATA_0_LOCK_OFFSET (0x7C) +#define EF_DATA_0_EF_ANA_TRIM_1 EF_DATA_0_EF_ANA_TRIM_1 +#define EF_DATA_0_EF_ANA_TRIM_1_POS (0U) +#define EF_DATA_0_EF_ANA_TRIM_1_LEN (13U) +#define EF_DATA_0_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS) +#define EF_DATA_0_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L EF_DATA_0_WR_LOCK_KEY_SLOT_4_L +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS (13U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L EF_DATA_0_WR_LOCK_KEY_SLOT_5_L +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS (14U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)) +#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE +#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (15U) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)) +#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD +#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (16U) +#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U) +#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS) +#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0 +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (17U) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)) +#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC +#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (18U) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (19U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (20U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (21U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (22U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H EF_DATA_0_WR_LOCK_KEY_SLOT_4_H +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS (23U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H EF_DATA_0_WR_LOCK_KEY_SLOT_5_H +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS (24U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)) +#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD +#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (25U) +#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U) +#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS) +#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (26U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (27U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (28U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (29U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4 EF_DATA_0_RD_LOCK_KEY_SLOT_4 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS (30U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5 EF_DATA_0_RD_LOCK_KEY_SLOT_5 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS (31U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)) + +struct ef_data_0_reg { + /* 0x0 : ef_cfg_0 */ + union { + struct + { + uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t rsvd0 : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t rsvd1 : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_boot_sel : 4; /* [11: 8], r/w, 0x0 */ + uint32_t ef_sf_key_0_sel : 2; /* [13:12], r/w, 0x0 */ + uint32_t rsvd2 : 1; /* [ 14], r/w, 0x0 */ + uint32_t rsvd3 : 1; /* [ 15], r/w, 0x0 */ + uint32_t rsvd4 : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t rsvd5 : 1; /* [ 18], r/w, 0x0 */ + uint32_t rsvd6 : 1; /* [ 19], r/w, 0x0 */ + uint32_t rsvd7 : 1; /* [ 20], r/w, 0x0 */ + uint32_t rsvd8 : 1; /* [ 21], r/w, 0x0 */ + uint32_t rsvd9 : 1; /* [ 22], r/w, 0x0 */ + uint32_t rsvd10 : 1; /* [ 23], r/w, 0x0 */ + uint32_t rsvd11 : 2; /* [25:24], r/w, 0x0 */ + uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ + uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_cfg_0; + + /* 0x4 : ef_dbg_pwd_low */ + union { + struct + { + uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_dbg_pwd_low; + + /* 0x8 : ef_dbg_pwd_high */ + union { + struct + { + uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_dbg_pwd_high; + + /* 0xC : ef_ana_trim_0 */ + union { + struct + { + uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_ana_trim_0; + + /* 0x10 : ef_sw_usage_0 */ + union { + struct + { + uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_sw_usage_0; + + /* 0x14 : ef_wifi_mac_low */ + union { + struct + { + uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_wifi_mac_low; + + /* 0x18 : ef_wifi_mac_high */ + union { + struct + { + uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_wifi_mac_high; + + /* 0x1C : ef_key_slot_0_w0 */ + union { + struct + { + uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w0; + + /* 0x20 : ef_key_slot_0_w1 */ + union { + struct + { + uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w1; + + /* 0x24 : ef_key_slot_0_w2 */ + union { + struct + { + uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w2; + + /* 0x28 : ef_key_slot_0_w3 */ + union { + struct + { + uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w3; + + /* 0x2C : ef_key_slot_1_w0 */ + union { + struct + { + uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w0; + + /* 0x30 : ef_key_slot_1_w1 */ + union { + struct + { + uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w1; + + /* 0x34 : ef_key_slot_1_w2 */ + union { + struct + { + uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w2; + + /* 0x38 : ef_key_slot_1_w3 */ + union { + struct + { + uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w3; + + /* 0x3C : ef_key_slot_2_w0 */ + union { + struct + { + uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w0; + + /* 0x40 : ef_key_slot_2_w1 */ + union { + struct + { + uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w1; + + /* 0x44 : ef_key_slot_2_w2 */ + union { + struct + { + uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w2; + + /* 0x48 : ef_key_slot_2_w3 */ + union { + struct + { + uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w3; + + /* 0x4C : ef_key_slot_3_w0 */ + union { + struct + { + uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w0; + + /* 0x50 : ef_key_slot_3_w1 */ + union { + struct + { + uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w1; + + /* 0x54 : ef_key_slot_3_w2 */ + union { + struct + { + uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w2; + + /* 0x58 : ef_key_slot_3_w3 */ + union { + struct + { + uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w3; + + /* 0x5C : ef_key_slot_4_w0 */ + union { + struct + { + uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w0; + + /* 0x60 : ef_key_slot_4_w1 */ + union { + struct + { + uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w1; + + /* 0x64 : ef_key_slot_4_w2 */ + union { + struct + { + uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w2; + + /* 0x68 : ef_key_slot_4_w3 */ + union { + struct + { + uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w3; + + /* 0x6C : ef_key_slot_5_w0 */ + union { + struct + { + uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w0; + + /* 0x70 : ef_key_slot_5_w1 */ + union { + struct + { + uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w1; + + /* 0x74 : ef_key_slot_5_w2 */ + union { + struct + { + uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w2; + + /* 0x78 : ef_key_slot_5_w3 */ + union { + struct + { + uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w3; + + /* 0x7C : ef_data_0_lock */ + union { + struct + { + uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */ + uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */ + uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */ + uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */ + uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */ + uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */ + uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */ + uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */ + uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */ + uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */ + uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */ + uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */ + uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */ + uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */ + uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */ + uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */ + uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */ + uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */ + uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_data_0_lock; +}; + +typedef volatile struct ef_data_0_reg ef_data_0_reg_t; + +#endif /* __EF_DATA_0_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/emac_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/emac_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..bf32c19a4972b74dcbdfbe4a228193a7ce1fc89b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/emac_reg.h @@ -0,0 +1,601 @@ +/** + ****************************************************************************** + * @file emac_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EMAC_REG_H__ +#define __EMAC_REG_H__ + +#include "bl702.h" + +/* 0x0 : MODE */ +#define EMAC_MODE_OFFSET (0x0) +#define EMAC_RXEN EMAC_RXEN +#define EMAC_RXEN_POS (0U) +#define EMAC_RXEN_LEN (1U) +#define EMAC_RXEN_MSK (((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS) +#define EMAC_RXEN_UMSK (~(((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS)) +#define EMAC_TXEN EMAC_TXEN +#define EMAC_TXEN_POS (1U) +#define EMAC_TXEN_LEN (1U) +#define EMAC_TXEN_MSK (((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS) +#define EMAC_TXEN_UMSK (~(((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS)) +#define EMAC_NOPRE EMAC_NOPRE +#define EMAC_NOPRE_POS (2U) +#define EMAC_NOPRE_LEN (1U) +#define EMAC_NOPRE_MSK (((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS) +#define EMAC_NOPRE_UMSK (~(((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS)) +#define EMAC_BRO EMAC_BRO +#define EMAC_BRO_POS (3U) +#define EMAC_BRO_LEN (1U) +#define EMAC_BRO_MSK (((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS) +#define EMAC_BRO_UMSK (~(((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS)) +#define EMAC_PRO EMAC_PRO +#define EMAC_PRO_POS (5U) +#define EMAC_PRO_LEN (1U) +#define EMAC_PRO_MSK (((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS) +#define EMAC_PRO_UMSK (~(((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS)) +#define EMAC_IFG EMAC_IFG +#define EMAC_IFG_POS (6U) +#define EMAC_IFG_LEN (1U) +#define EMAC_IFG_MSK (((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS) +#define EMAC_IFG_UMSK (~(((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS)) +#define EMAC_FULLD EMAC_FULLD +#define EMAC_FULLD_POS (10U) +#define EMAC_FULLD_LEN (1U) +#define EMAC_FULLD_MSK (((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS) +#define EMAC_FULLD_UMSK (~(((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS)) +#define EMAC_CRCEN EMAC_CRCEN +#define EMAC_CRCEN_POS (13U) +#define EMAC_CRCEN_LEN (1U) +#define EMAC_CRCEN_MSK (((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS) +#define EMAC_CRCEN_UMSK (~(((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS)) +#define EMAC_HUGEN EMAC_HUGEN +#define EMAC_HUGEN_POS (14U) +#define EMAC_HUGEN_LEN (1U) +#define EMAC_HUGEN_MSK (((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS) +#define EMAC_HUGEN_UMSK (~(((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS)) +#define EMAC_PAD EMAC_PAD +#define EMAC_PAD_POS (15U) +#define EMAC_PAD_LEN (1U) +#define EMAC_PAD_MSK (((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS) +#define EMAC_PAD_UMSK (~(((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS)) +#define EMAC_RECSMALL EMAC_RECSMALL +#define EMAC_RECSMALL_POS (16U) +#define EMAC_RECSMALL_LEN (1U) +#define EMAC_RECSMALL_MSK (((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS) +#define EMAC_RECSMALL_UMSK (~(((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS)) +#define EMAC_RMII_EN EMAC_RMII_EN +#define EMAC_RMII_EN_POS (17U) +#define EMAC_RMII_EN_LEN (1U) +#define EMAC_RMII_EN_MSK (((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS) +#define EMAC_RMII_EN_UMSK (~(((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS)) + +/* 0x4 : INT_SOURCE */ +#define EMAC_INT_SOURCE_OFFSET (0x4) +#define EMAC_TXB EMAC_TXB +#define EMAC_TXB_POS (0U) +#define EMAC_TXB_LEN (1U) +#define EMAC_TXB_MSK (((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS) +#define EMAC_TXB_UMSK (~(((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS)) +#define EMAC_TXE EMAC_TXE +#define EMAC_TXE_POS (1U) +#define EMAC_TXE_LEN (1U) +#define EMAC_TXE_MSK (((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS) +#define EMAC_TXE_UMSK (~(((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS)) +#define EMAC_RXB EMAC_RXB +#define EMAC_RXB_POS (2U) +#define EMAC_RXB_LEN (1U) +#define EMAC_RXB_MSK (((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS) +#define EMAC_RXB_UMSK (~(((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS)) +#define EMAC_RXE EMAC_RXE +#define EMAC_RXE_POS (3U) +#define EMAC_RXE_LEN (1U) +#define EMAC_RXE_MSK (((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS) +#define EMAC_RXE_UMSK (~(((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS)) +#define EMAC_BUSY EMAC_BUSY +#define EMAC_BUSY_POS (4U) +#define EMAC_BUSY_LEN (1U) +#define EMAC_BUSY_MSK (((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS) +#define EMAC_BUSY_UMSK (~(((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS)) +#define EMAC_TXC EMAC_TXC +#define EMAC_TXC_POS (5U) +#define EMAC_TXC_LEN (1U) +#define EMAC_TXC_MSK (((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS) +#define EMAC_TXC_UMSK (~(((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS)) +#define EMAC_RXC EMAC_RXC +#define EMAC_RXC_POS (6U) +#define EMAC_RXC_LEN (1U) +#define EMAC_RXC_MSK (((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS) +#define EMAC_RXC_UMSK (~(((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS)) + +/* 0x8 : INT_MASK */ +#define EMAC_INT_MASK_OFFSET (0x8) +#define EMAC_TXB_M EMAC_TXB_M +#define EMAC_TXB_M_POS (0U) +#define EMAC_TXB_M_LEN (1U) +#define EMAC_TXB_M_MSK (((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS) +#define EMAC_TXB_M_UMSK (~(((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS)) +#define EMAC_TXE_M EMAC_TXE_M +#define EMAC_TXE_M_POS (1U) +#define EMAC_TXE_M_LEN (1U) +#define EMAC_TXE_M_MSK (((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS) +#define EMAC_TXE_M_UMSK (~(((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS)) +#define EMAC_RXB_M EMAC_RXB_M +#define EMAC_RXB_M_POS (2U) +#define EMAC_RXB_M_LEN (1U) +#define EMAC_RXB_M_MSK (((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS) +#define EMAC_RXB_M_UMSK (~(((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS)) +#define EMAC_RXE_M EMAC_RXE_M +#define EMAC_RXE_M_POS (3U) +#define EMAC_RXE_M_LEN (1U) +#define EMAC_RXE_M_MSK (((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS) +#define EMAC_RXE_M_UMSK (~(((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS)) +#define EMAC_BUSY_M EMAC_BUSY_M +#define EMAC_BUSY_M_POS (4U) +#define EMAC_BUSY_M_LEN (1U) +#define EMAC_BUSY_M_MSK (((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS) +#define EMAC_BUSY_M_UMSK (~(((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS)) +#define EMAC_TXC_M EMAC_TXC_M +#define EMAC_TXC_M_POS (5U) +#define EMAC_TXC_M_LEN (1U) +#define EMAC_TXC_M_MSK (((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS) +#define EMAC_TXC_M_UMSK (~(((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS)) +#define EMAC_RXC_M EMAC_RXC_M +#define EMAC_RXC_M_POS (6U) +#define EMAC_RXC_M_LEN (1U) +#define EMAC_RXC_M_MSK (((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS) +#define EMAC_RXC_M_UMSK (~(((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS)) + +/* 0xC : IPGT */ +#define EMAC_IPGT_OFFSET (0xC) +#define EMAC_IPGT EMAC_IPGT +#define EMAC_IPGT_POS (0U) +#define EMAC_IPGT_LEN (7U) +#define EMAC_IPGT_MSK (((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS) +#define EMAC_IPGT_UMSK (~(((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS)) + +/* 0x18 : PACKETLEN */ +#define EMAC_PACKETLEN_OFFSET (0x18) +#define EMAC_MAXFL EMAC_MAXFL +#define EMAC_MAXFL_POS (0U) +#define EMAC_MAXFL_LEN (16U) +#define EMAC_MAXFL_MSK (((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS) +#define EMAC_MAXFL_UMSK (~(((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS)) +#define EMAC_MINFL EMAC_MINFL +#define EMAC_MINFL_POS (16U) +#define EMAC_MINFL_LEN (16U) +#define EMAC_MINFL_MSK (((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS) +#define EMAC_MINFL_UMSK (~(((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS)) + +/* 0x1C : COLLCONFIG */ +#define EMAC_COLLCONFIG_OFFSET (0x1C) +#define EMAC_COLLVALID EMAC_COLLVALID +#define EMAC_COLLVALID_POS (0U) +#define EMAC_COLLVALID_LEN (6U) +#define EMAC_COLLVALID_MSK (((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS) +#define EMAC_COLLVALID_UMSK (~(((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS)) +#define EMAC_MAXRET EMAC_MAXRET +#define EMAC_MAXRET_POS (16U) +#define EMAC_MAXRET_LEN (4U) +#define EMAC_MAXRET_MSK (((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS) +#define EMAC_MAXRET_UMSK (~(((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS)) + +/* 0x20 : TX_BD_NUM */ +#define EMAC_TX_BD_NUM_OFFSET (0x20) +#define EMAC_TXBDNUM EMAC_TXBDNUM +#define EMAC_TXBDNUM_POS (0U) +#define EMAC_TXBDNUM_LEN (8U) +#define EMAC_TXBDNUM_MSK (((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS) +#define EMAC_TXBDNUM_UMSK (~(((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS)) +#define EMAC_TXBDPTR EMAC_TXBDPTR +#define EMAC_TXBDPTR_POS (16U) +#define EMAC_TXBDPTR_LEN (7U) +#define EMAC_TXBDPTR_MSK (((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS) +#define EMAC_TXBDPTR_UMSK (~(((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS)) +#define EMAC_RXBDPTR EMAC_RXBDPTR +#define EMAC_RXBDPTR_POS (24U) +#define EMAC_RXBDPTR_LEN (7U) +#define EMAC_RXBDPTR_MSK (((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS) +#define EMAC_RXBDPTR_UMSK (~(((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS)) + +/* 0x28 : MIIMODE */ +#define EMAC_MIIMODE_OFFSET (0x28) +#define EMAC_CLKDIV EMAC_CLKDIV +#define EMAC_CLKDIV_POS (0U) +#define EMAC_CLKDIV_LEN (8U) +#define EMAC_CLKDIV_MSK (((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS) +#define EMAC_CLKDIV_UMSK (~(((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS)) +#define EMAC_MIINOPRE EMAC_MIINOPRE +#define EMAC_MIINOPRE_POS (8U) +#define EMAC_MIINOPRE_LEN (1U) +#define EMAC_MIINOPRE_MSK (((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS) +#define EMAC_MIINOPRE_UMSK (~(((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS)) + +/* 0x2C : MIICOMMAND */ +#define EMAC_MIICOMMAND_OFFSET (0x2C) +#define EMAC_SCANSTAT EMAC_SCANSTAT +#define EMAC_SCANSTAT_POS (0U) +#define EMAC_SCANSTAT_LEN (1U) +#define EMAC_SCANSTAT_MSK (((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS) +#define EMAC_SCANSTAT_UMSK (~(((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS)) +#define EMAC_RSTAT EMAC_RSTAT +#define EMAC_RSTAT_POS (1U) +#define EMAC_RSTAT_LEN (1U) +#define EMAC_RSTAT_MSK (((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS) +#define EMAC_RSTAT_UMSK (~(((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS)) +#define EMAC_WCTRLDATA EMAC_WCTRLDATA +#define EMAC_WCTRLDATA_POS (2U) +#define EMAC_WCTRLDATA_LEN (1U) +#define EMAC_WCTRLDATA_MSK (((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS) +#define EMAC_WCTRLDATA_UMSK (~(((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS)) + +/* 0x30 : MIIADDRESS */ +#define EMAC_MIIADDRESS_OFFSET (0x30) +#define EMAC_FIAD EMAC_FIAD +#define EMAC_FIAD_POS (0U) +#define EMAC_FIAD_LEN (5U) +#define EMAC_FIAD_MSK (((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS) +#define EMAC_FIAD_UMSK (~(((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS)) +#define EMAC_RGAD EMAC_RGAD +#define EMAC_RGAD_POS (8U) +#define EMAC_RGAD_LEN (5U) +#define EMAC_RGAD_MSK (((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS) +#define EMAC_RGAD_UMSK (~(((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS)) + +/* 0x34 : MIITX_DATA */ +#define EMAC_MIITX_DATA_OFFSET (0x34) +#define EMAC_CTRLDATA EMAC_CTRLDATA +#define EMAC_CTRLDATA_POS (0U) +#define EMAC_CTRLDATA_LEN (16U) +#define EMAC_CTRLDATA_MSK (((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS) +#define EMAC_CTRLDATA_UMSK (~(((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS)) + +/* 0x38 : MIIRX_DATA */ +#define EMAC_MIIRX_DATA_OFFSET (0x38) +#define EMAC_PRSD EMAC_PRSD +#define EMAC_PRSD_POS (0U) +#define EMAC_PRSD_LEN (16U) +#define EMAC_PRSD_MSK (((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS) +#define EMAC_PRSD_UMSK (~(((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS)) + +/* 0x3C : MIISTATUS */ +#define EMAC_MIISTATUS_OFFSET (0x3C) +#define EMAC_MIIM_LINKFAIL EMAC_MIIM_LINKFAIL +#define EMAC_MIIM_LINKFAIL_POS (0U) +#define EMAC_MIIM_LINKFAIL_LEN (1U) +#define EMAC_MIIM_LINKFAIL_MSK (((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS) +#define EMAC_MIIM_LINKFAIL_UMSK (~(((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS)) +#define EMAC_MIIM_BUSY EMAC_MIIM_BUSY +#define EMAC_MIIM_BUSY_POS (1U) +#define EMAC_MIIM_BUSY_LEN (1U) +#define EMAC_MIIM_BUSY_MSK (((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS) +#define EMAC_MIIM_BUSY_UMSK (~(((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS)) + +/* 0x40 : MAC_ADDR0 */ +#define EMAC_MAC_ADDR0_OFFSET (0x40) +#define EMAC_MAC_B5 EMAC_MAC_B5 +#define EMAC_MAC_B5_POS (0U) +#define EMAC_MAC_B5_LEN (8U) +#define EMAC_MAC_B5_MSK (((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS) +#define EMAC_MAC_B5_UMSK (~(((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS)) +#define EMAC_MAC_B4 EMAC_MAC_B4 +#define EMAC_MAC_B4_POS (8U) +#define EMAC_MAC_B4_LEN (8U) +#define EMAC_MAC_B4_MSK (((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS) +#define EMAC_MAC_B4_UMSK (~(((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS)) +#define EMAC_MAC_B3 EMAC_MAC_B3 +#define EMAC_MAC_B3_POS (16U) +#define EMAC_MAC_B3_LEN (8U) +#define EMAC_MAC_B3_MSK (((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS) +#define EMAC_MAC_B3_UMSK (~(((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS)) +#define EMAC_MAC_B2 EMAC_MAC_B2 +#define EMAC_MAC_B2_POS (24U) +#define EMAC_MAC_B2_LEN (8U) +#define EMAC_MAC_B2_MSK (((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS) +#define EMAC_MAC_B2_UMSK (~(((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS)) + +/* 0x44 : MAC_ADDR1 */ +#define EMAC_MAC_ADDR1_OFFSET (0x44) +#define EMAC_MAC_B1 EMAC_MAC_B1 +#define EMAC_MAC_B1_POS (0U) +#define EMAC_MAC_B1_LEN (8U) +#define EMAC_MAC_B1_MSK (((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS) +#define EMAC_MAC_B1_UMSK (~(((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS)) +#define EMAC_MAC_B0 EMAC_MAC_B0 +#define EMAC_MAC_B0_POS (8U) +#define EMAC_MAC_B0_LEN (8U) +#define EMAC_MAC_B0_MSK (((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS) +#define EMAC_MAC_B0_UMSK (~(((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS)) + +/* 0x48 : HASH0_ADDR */ +#define EMAC_HASH0_ADDR_OFFSET (0x48) +#define EMAC_HASH0 EMAC_HASH0 +#define EMAC_HASH0_POS (0U) +#define EMAC_HASH0_LEN (32U) +#define EMAC_HASH0_MSK (((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS) +#define EMAC_HASH0_UMSK (~(((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS)) + +/* 0x4C : HASH1_ADDR */ +#define EMAC_HASH1_ADDR_OFFSET (0x4C) +#define EMAC_HASH1 EMAC_HASH1 +#define EMAC_HASH1_POS (0U) +#define EMAC_HASH1_LEN (32U) +#define EMAC_HASH1_MSK (((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS) +#define EMAC_HASH1_UMSK (~(((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS)) + +/* 0x50 : TXCTRL */ +#define EMAC_TXCTRL_OFFSET (0x50) +#define EMAC_TXPAUSETV EMAC_TXPAUSETV +#define EMAC_TXPAUSETV_POS (0U) +#define EMAC_TXPAUSETV_LEN (16U) +#define EMAC_TXPAUSETV_MSK (((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS) +#define EMAC_TXPAUSETV_UMSK (~(((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS)) +#define EMAC_TXPAUSERQ EMAC_TXPAUSERQ +#define EMAC_TXPAUSERQ_POS (16U) +#define EMAC_TXPAUSERQ_LEN (1U) +#define EMAC_TXPAUSERQ_MSK (((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS) +#define EMAC_TXPAUSERQ_UMSK (~(((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS)) + +struct emac_reg { + /* 0x0 : MODE */ + union { + struct + { + uint32_t RXEN : 1; /* [ 0], r/w, 0x0 */ + uint32_t TXEN : 1; /* [ 1], r/w, 0x0 */ + uint32_t NOPRE : 1; /* [ 2], r/w, 0x0 */ + uint32_t BRO : 1; /* [ 3], r/w, 0x1 */ + uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ + uint32_t PRO : 1; /* [ 5], r/w, 0x0 */ + uint32_t IFG : 1; /* [ 6], r/w, 0x0 */ + uint32_t rsvd_9_7 : 3; /* [ 9: 7], rsvd, 0x0 */ + uint32_t FULLD : 1; /* [ 10], r/w, 0x0 */ + uint32_t rsvd_12_11 : 2; /* [12:11], rsvd, 0x0 */ + uint32_t CRCEN : 1; /* [ 13], r/w, 0x1 */ + uint32_t HUGEN : 1; /* [ 14], r/w, 0x0 */ + uint32_t PAD : 1; /* [ 15], r/w, 0x1 */ + uint32_t RECSMALL : 1; /* [ 16], r/w, 0x0 */ + uint32_t RMII_EN : 1; /* [ 17], r/w, 0x0 */ + uint32_t rsvd_23_18 : 6; /* [23:18], rsvd, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MODE; + + /* 0x4 : INT_SOURCE */ + union { + struct + { + uint32_t TXB : 1; /* [ 0], r/w, 0x0 */ + uint32_t TXE : 1; /* [ 1], r/w, 0x0 */ + uint32_t RXB : 1; /* [ 2], r/w, 0x0 */ + uint32_t RXE : 1; /* [ 3], r/w, 0x0 */ + uint32_t BUSY : 1; /* [ 4], r/w, 0x0 */ + uint32_t TXC : 1; /* [ 5], r/w, 0x0 */ + uint32_t RXC : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } INT_SOURCE; + + /* 0x8 : INT_MASK */ + union { + struct + { + uint32_t TXB_M : 1; /* [ 0], r/w, 0x1 */ + uint32_t TXE_M : 1; /* [ 1], r/w, 0x1 */ + uint32_t RXB_M : 1; /* [ 2], r/w, 0x1 */ + uint32_t RXE_M : 1; /* [ 3], r/w, 0x1 */ + uint32_t BUSY_M : 1; /* [ 4], r/w, 0x1 */ + uint32_t TXC_M : 1; /* [ 5], r/w, 0x1 */ + uint32_t RXC_M : 1; /* [ 6], r/w, 0x1 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } INT_MASK; + + /* 0xC : IPGT */ + union { + struct + { + uint32_t IPGT : 7; /* [ 6: 0], r/w, 0x18 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } IPGT; + + /* 0x10 reserved */ + uint8_t RESERVED0x10[8]; + + /* 0x18 : PACKETLEN */ + union { + struct + { + uint32_t MAXFL : 16; /* [15: 0], r/w, 0x600 */ + uint32_t MINFL : 16; /* [31:16], r/w, 0x40 */ + } BF; + uint32_t WORD; + } PACKETLEN; + + /* 0x1C : COLLCONFIG */ + union { + struct + { + uint32_t COLLVALID : 6; /* [ 5: 0], r/w, 0x3f */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t MAXRET : 4; /* [19:16], r/w, 0xf */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } COLLCONFIG; + + /* 0x20 : TX_BD_NUM */ + union { + struct + { + uint32_t TXBDNUM : 8; /* [ 7: 0], r/w, 0x40 */ + uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ + uint32_t TXBDPTR : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t RXBDPTR : 7; /* [30:24], r, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TX_BD_NUM; + + /* 0x24 reserved */ + uint8_t RESERVED0x24[4]; + + /* 0x28 : MIIMODE */ + union { + struct + { + uint32_t CLKDIV : 8; /* [ 7: 0], r/w, 0x64 */ + uint32_t MIINOPRE : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MIIMODE; + + /* 0x2C : MIICOMMAND */ + union { + struct + { + uint32_t SCANSTAT : 1; /* [ 0], r/w, 0x0 */ + uint32_t RSTAT : 1; /* [ 1], r/w, 0x0 */ + uint32_t WCTRLDATA : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MIICOMMAND; + + /* 0x30 : MIIADDRESS */ + union { + struct + { + uint32_t FIAD : 5; /* [ 4: 0], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t RGAD : 5; /* [12: 8], r/w, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MIIADDRESS; + + /* 0x34 : MIITX_DATA */ + union { + struct + { + uint32_t CTRLDATA : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MIITX_DATA; + + /* 0x38 : MIIRX_DATA */ + union { + struct + { + uint32_t PRSD : 16; /* [15: 0], r, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MIIRX_DATA; + + /* 0x3C : MIISTATUS */ + union { + struct + { + uint32_t MIIM_LINKFAIL : 1; /* [ 0], r, 0x0 */ + uint32_t MIIM_BUSY : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MIISTATUS; + + /* 0x40 : MAC_ADDR0 */ + union { + struct + { + uint32_t MAC_B5 : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t MAC_B4 : 8; /* [15: 8], r/w, 0x0 */ + uint32_t MAC_B3 : 8; /* [23:16], r/w, 0x0 */ + uint32_t MAC_B2 : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } MAC_ADDR0; + + /* 0x44 : MAC_ADDR1 */ + union { + struct + { + uint32_t MAC_B1 : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t MAC_B0 : 8; /* [15: 8], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MAC_ADDR1; + + /* 0x48 : HASH0_ADDR */ + union { + struct + { + uint32_t HASH0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HASH0_ADDR; + + /* 0x4C : HASH1_ADDR */ + union { + struct + { + uint32_t HASH1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HASH1_ADDR; + + /* 0x50 : TXCTRL */ + union { + struct + { + uint32_t TXPAUSETV : 16; /* [15: 0], r/w, 0x0 */ + uint32_t TXPAUSERQ : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TXCTRL; +}; + +typedef volatile struct emac_reg emac_reg_t; + +#endif /* __EMAC_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/glb_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/glb_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..19fd12de5927ffb62ce257a3a4ed9963f787140d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/glb_reg.h @@ -0,0 +1,5498 @@ +/** + ****************************************************************************** + * @file glb_reg.h + * @version V1.2 + * @date 2020-07-08 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __GLB_REG_H__ +#define __GLB_REG_H__ + +#include "bl702.h" + +/* 0x0 : clk_cfg0 */ +#define GLB_CLK_CFG0_OFFSET (0x0) +#define GLB_REG_PLL_EN GLB_REG_PLL_EN +#define GLB_REG_PLL_EN_POS (0U) +#define GLB_REG_PLL_EN_LEN (1U) +#define GLB_REG_PLL_EN_MSK (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS) +#define GLB_REG_PLL_EN_UMSK (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)) +#define GLB_REG_FCLK_EN GLB_REG_FCLK_EN +#define GLB_REG_FCLK_EN_POS (1U) +#define GLB_REG_FCLK_EN_LEN (1U) +#define GLB_REG_FCLK_EN_MSK (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS) +#define GLB_REG_FCLK_EN_UMSK (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)) +#define GLB_REG_HCLK_EN GLB_REG_HCLK_EN +#define GLB_REG_HCLK_EN_POS (2U) +#define GLB_REG_HCLK_EN_LEN (1U) +#define GLB_REG_HCLK_EN_MSK (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS) +#define GLB_REG_HCLK_EN_UMSK (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)) +#define GLB_REG_BCLK_EN GLB_REG_BCLK_EN +#define GLB_REG_BCLK_EN_POS (3U) +#define GLB_REG_BCLK_EN_LEN (1U) +#define GLB_REG_BCLK_EN_MSK (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS) +#define GLB_REG_BCLK_EN_UMSK (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)) +#define GLB_REG_PLL_SEL GLB_REG_PLL_SEL +#define GLB_REG_PLL_SEL_POS (4U) +#define GLB_REG_PLL_SEL_LEN (2U) +#define GLB_REG_PLL_SEL_MSK (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS) +#define GLB_REG_PLL_SEL_UMSK (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)) +#define GLB_HBN_ROOT_CLK_SEL GLB_HBN_ROOT_CLK_SEL +#define GLB_HBN_ROOT_CLK_SEL_POS (6U) +#define GLB_HBN_ROOT_CLK_SEL_LEN (2U) +#define GLB_HBN_ROOT_CLK_SEL_MSK (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS) +#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)) +#define GLB_REG_HCLK_DIV GLB_REG_HCLK_DIV +#define GLB_REG_HCLK_DIV_POS (8U) +#define GLB_REG_HCLK_DIV_LEN (8U) +#define GLB_REG_HCLK_DIV_MSK (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS) +#define GLB_REG_HCLK_DIV_UMSK (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)) +#define GLB_REG_BCLK_DIV GLB_REG_BCLK_DIV +#define GLB_REG_BCLK_DIV_POS (16U) +#define GLB_REG_BCLK_DIV_LEN (8U) +#define GLB_REG_BCLK_DIV_MSK (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS) +#define GLB_REG_BCLK_DIV_UMSK (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)) +#define GLB_FCLK_SW_STATE GLB_FCLK_SW_STATE +#define GLB_FCLK_SW_STATE_POS (24U) +#define GLB_FCLK_SW_STATE_LEN (3U) +#define GLB_FCLK_SW_STATE_MSK (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS) +#define GLB_FCLK_SW_STATE_UMSK (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)) +#define GLB_CHIP_RDY GLB_CHIP_RDY +#define GLB_CHIP_RDY_POS (27U) +#define GLB_CHIP_RDY_LEN (1U) +#define GLB_CHIP_RDY_MSK (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS) +#define GLB_CHIP_RDY_UMSK (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)) +#define GLB_ID GLB_ID +#define GLB_ID_POS (28U) +#define GLB_ID_LEN (4U) +#define GLB_ID_MSK (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS) +#define GLB_ID_UMSK (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)) + +/* 0x4 : clk_cfg1 */ +#define GLB_CLK_CFG1_OFFSET (0x4) +#define GLB_QDEC_CLK_DIV GLB_QDEC_CLK_DIV +#define GLB_QDEC_CLK_DIV_POS (0U) +#define GLB_QDEC_CLK_DIV_LEN (5U) +#define GLB_QDEC_CLK_DIV_MSK (((1U << GLB_QDEC_CLK_DIV_LEN) - 1) << GLB_QDEC_CLK_DIV_POS) +#define GLB_QDEC_CLK_DIV_UMSK (~(((1U << GLB_QDEC_CLK_DIV_LEN) - 1) << GLB_QDEC_CLK_DIV_POS)) +#define GLB_QDEC_CLK_SEL GLB_QDEC_CLK_SEL +#define GLB_QDEC_CLK_SEL_POS (7U) +#define GLB_QDEC_CLK_SEL_LEN (1U) +#define GLB_QDEC_CLK_SEL_MSK (((1U << GLB_QDEC_CLK_SEL_LEN) - 1) << GLB_QDEC_CLK_SEL_POS) +#define GLB_QDEC_CLK_SEL_UMSK (~(((1U << GLB_QDEC_CLK_SEL_LEN) - 1) << GLB_QDEC_CLK_SEL_POS)) +#define GLB_USB_CLK_EN GLB_USB_CLK_EN +#define GLB_USB_CLK_EN_POS (8U) +#define GLB_USB_CLK_EN_LEN (1U) +#define GLB_USB_CLK_EN_MSK (((1U << GLB_USB_CLK_EN_LEN) - 1) << GLB_USB_CLK_EN_POS) +#define GLB_USB_CLK_EN_UMSK (~(((1U << GLB_USB_CLK_EN_LEN) - 1) << GLB_USB_CLK_EN_POS)) +#define GLB_DLL_48M_DIV_EN GLB_DLL_48M_DIV_EN +#define GLB_DLL_48M_DIV_EN_POS (9U) +#define GLB_DLL_48M_DIV_EN_LEN (1U) +#define GLB_DLL_48M_DIV_EN_MSK (((1U << GLB_DLL_48M_DIV_EN_LEN) - 1) << GLB_DLL_48M_DIV_EN_POS) +#define GLB_DLL_48M_DIV_EN_UMSK (~(((1U << GLB_DLL_48M_DIV_EN_LEN) - 1) << GLB_DLL_48M_DIV_EN_POS)) +#define GLB_REG_I2S_CLK_SEL GLB_REG_I2S_CLK_SEL +#define GLB_REG_I2S_CLK_SEL_POS (12U) +#define GLB_REG_I2S_CLK_SEL_LEN (1U) +#define GLB_REG_I2S_CLK_SEL_MSK (((1U << GLB_REG_I2S_CLK_SEL_LEN) - 1) << GLB_REG_I2S_CLK_SEL_POS) +#define GLB_REG_I2S_CLK_SEL_UMSK (~(((1U << GLB_REG_I2S_CLK_SEL_LEN) - 1) << GLB_REG_I2S_CLK_SEL_POS)) +#define GLB_REG_I2S0_CLK_EN GLB_REG_I2S0_CLK_EN +#define GLB_REG_I2S0_CLK_EN_POS (13U) +#define GLB_REG_I2S0_CLK_EN_LEN (1U) +#define GLB_REG_I2S0_CLK_EN_MSK (((1U << GLB_REG_I2S0_CLK_EN_LEN) - 1) << GLB_REG_I2S0_CLK_EN_POS) +#define GLB_REG_I2S0_CLK_EN_UMSK (~(((1U << GLB_REG_I2S0_CLK_EN_LEN) - 1) << GLB_REG_I2S0_CLK_EN_POS)) +#define GLB_REG_I2S_0_REF_CLK_OE GLB_REG_I2S_0_REF_CLK_OE +#define GLB_REG_I2S_0_REF_CLK_OE_POS (14U) +#define GLB_REG_I2S_0_REF_CLK_OE_LEN (1U) +#define GLB_REG_I2S_0_REF_CLK_OE_MSK (((1U << GLB_REG_I2S_0_REF_CLK_OE_LEN) - 1) << GLB_REG_I2S_0_REF_CLK_OE_POS) +#define GLB_REG_I2S_0_REF_CLK_OE_UMSK (~(((1U << GLB_REG_I2S_0_REF_CLK_OE_LEN) - 1) << GLB_REG_I2S_0_REF_CLK_OE_POS)) +#define GLB_BLE_CLK_SEL GLB_BLE_CLK_SEL +#define GLB_BLE_CLK_SEL_POS (16U) +#define GLB_BLE_CLK_SEL_LEN (6U) +#define GLB_BLE_CLK_SEL_MSK (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS) +#define GLB_BLE_CLK_SEL_UMSK (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)) +#define GLB_BLE_EN GLB_BLE_EN +#define GLB_BLE_EN_POS (24U) +#define GLB_BLE_EN_LEN (1U) +#define GLB_BLE_EN_MSK (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS) +#define GLB_BLE_EN_UMSK (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)) +#define GLB_M154_ZBEN GLB_M154_ZBEN +#define GLB_M154_ZBEN_POS (25U) +#define GLB_M154_ZBEN_LEN (1U) +#define GLB_M154_ZBEN_MSK (((1U << GLB_M154_ZBEN_LEN) - 1) << GLB_M154_ZBEN_POS) +#define GLB_M154_ZBEN_UMSK (~(((1U << GLB_M154_ZBEN_LEN) - 1) << GLB_M154_ZBEN_POS)) +#define GLB_REG_CAM_REF_CLK_EN GLB_REG_CAM_REF_CLK_EN +#define GLB_REG_CAM_REF_CLK_EN_POS (28U) +#define GLB_REG_CAM_REF_CLK_EN_LEN (1U) +#define GLB_REG_CAM_REF_CLK_EN_MSK (((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS) +#define GLB_REG_CAM_REF_CLK_EN_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS)) +#define GLB_REG_CAM_REF_CLK_SRC_SEL GLB_REG_CAM_REF_CLK_SRC_SEL +#define GLB_REG_CAM_REF_CLK_SRC_SEL_POS (29U) +#define GLB_REG_CAM_REF_CLK_SRC_SEL_LEN (1U) +#define GLB_REG_CAM_REF_CLK_SRC_SEL_MSK (((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS) +#define GLB_REG_CAM_REF_CLK_SRC_SEL_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS)) +#define GLB_REG_CAM_REF_CLK_DIV GLB_REG_CAM_REF_CLK_DIV +#define GLB_REG_CAM_REF_CLK_DIV_POS (30U) +#define GLB_REG_CAM_REF_CLK_DIV_LEN (2U) +#define GLB_REG_CAM_REF_CLK_DIV_MSK (((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS) +#define GLB_REG_CAM_REF_CLK_DIV_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS)) + +/* 0x8 : clk_cfg2 */ +#define GLB_CLK_CFG2_OFFSET (0x8) +#define GLB_UART_CLK_DIV GLB_UART_CLK_DIV +#define GLB_UART_CLK_DIV_POS (0U) +#define GLB_UART_CLK_DIV_LEN (3U) +#define GLB_UART_CLK_DIV_MSK (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS) +#define GLB_UART_CLK_DIV_UMSK (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)) +#define GLB_UART_CLK_EN GLB_UART_CLK_EN +#define GLB_UART_CLK_EN_POS (4U) +#define GLB_UART_CLK_EN_LEN (1U) +#define GLB_UART_CLK_EN_MSK (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS) +#define GLB_UART_CLK_EN_UMSK (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)) +#define GLB_HBN_UART_CLK_SEL GLB_HBN_UART_CLK_SEL +#define GLB_HBN_UART_CLK_SEL_POS (7U) +#define GLB_HBN_UART_CLK_SEL_LEN (1U) +#define GLB_HBN_UART_CLK_SEL_MSK (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS) +#define GLB_HBN_UART_CLK_SEL_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)) +#define GLB_SF_CLK_DIV GLB_SF_CLK_DIV +#define GLB_SF_CLK_DIV_POS (8U) +#define GLB_SF_CLK_DIV_LEN (3U) +#define GLB_SF_CLK_DIV_MSK (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS) +#define GLB_SF_CLK_DIV_UMSK (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)) +#define GLB_SF_CLK_EN GLB_SF_CLK_EN +#define GLB_SF_CLK_EN_POS (11U) +#define GLB_SF_CLK_EN_LEN (1U) +#define GLB_SF_CLK_EN_MSK (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS) +#define GLB_SF_CLK_EN_UMSK (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)) +#define GLB_SF_CLK_SEL GLB_SF_CLK_SEL +#define GLB_SF_CLK_SEL_POS (12U) +#define GLB_SF_CLK_SEL_LEN (2U) +#define GLB_SF_CLK_SEL_MSK (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS) +#define GLB_SF_CLK_SEL_UMSK (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)) +#define GLB_SF_CLK_SEL2 GLB_SF_CLK_SEL2 +#define GLB_SF_CLK_SEL2_POS (14U) +#define GLB_SF_CLK_SEL2_LEN (2U) +#define GLB_SF_CLK_SEL2_MSK (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS) +#define GLB_SF_CLK_SEL2_UMSK (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)) +#define GLB_IR_CLK_DIV GLB_IR_CLK_DIV +#define GLB_IR_CLK_DIV_POS (16U) +#define GLB_IR_CLK_DIV_LEN (6U) +#define GLB_IR_CLK_DIV_MSK (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS) +#define GLB_IR_CLK_DIV_UMSK (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)) +#define GLB_IR_CLK_EN GLB_IR_CLK_EN +#define GLB_IR_CLK_EN_POS (23U) +#define GLB_IR_CLK_EN_LEN (1U) +#define GLB_IR_CLK_EN_MSK (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS) +#define GLB_IR_CLK_EN_UMSK (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)) +#define GLB_DMA_CLK_EN GLB_DMA_CLK_EN +#define GLB_DMA_CLK_EN_POS (24U) +#define GLB_DMA_CLK_EN_LEN (8U) +#define GLB_DMA_CLK_EN_MSK (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS) +#define GLB_DMA_CLK_EN_UMSK (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)) + +/* 0xC : clk_cfg3 */ +#define GLB_CLK_CFG3_OFFSET (0xC) +#define GLB_SPI_CLK_DIV GLB_SPI_CLK_DIV +#define GLB_SPI_CLK_DIV_POS (0U) +#define GLB_SPI_CLK_DIV_LEN (5U) +#define GLB_SPI_CLK_DIV_MSK (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS) +#define GLB_SPI_CLK_DIV_UMSK (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)) +#define GLB_CFG_SEL_ETH_REF_CLK_O GLB_CFG_SEL_ETH_REF_CLK_O +#define GLB_CFG_SEL_ETH_REF_CLK_O_POS (5U) +#define GLB_CFG_SEL_ETH_REF_CLK_O_LEN (1U) +#define GLB_CFG_SEL_ETH_REF_CLK_O_MSK (((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS) +#define GLB_CFG_SEL_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS)) +#define GLB_CFG_INV_ETH_REF_CLK_O GLB_CFG_INV_ETH_REF_CLK_O +#define GLB_CFG_INV_ETH_REF_CLK_O_POS (6U) +#define GLB_CFG_INV_ETH_REF_CLK_O_LEN (1U) +#define GLB_CFG_INV_ETH_REF_CLK_O_MSK (((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS) +#define GLB_CFG_INV_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS)) +#define GLB_CFG_INV_ETH_TX_CLK GLB_CFG_INV_ETH_TX_CLK +#define GLB_CFG_INV_ETH_TX_CLK_POS (7U) +#define GLB_CFG_INV_ETH_TX_CLK_LEN (1U) +#define GLB_CFG_INV_ETH_TX_CLK_MSK (((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS) +#define GLB_CFG_INV_ETH_TX_CLK_UMSK (~(((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS)) +#define GLB_SPI_CLK_EN GLB_SPI_CLK_EN +#define GLB_SPI_CLK_EN_POS (8U) +#define GLB_SPI_CLK_EN_LEN (1U) +#define GLB_SPI_CLK_EN_MSK (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS) +#define GLB_SPI_CLK_EN_UMSK (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)) +#define GLB_CFG_INV_RF_TEST_CLK_O GLB_CFG_INV_RF_TEST_CLK_O +#define GLB_CFG_INV_RF_TEST_CLK_O_POS (9U) +#define GLB_CFG_INV_RF_TEST_CLK_O_LEN (1U) +#define GLB_CFG_INV_RF_TEST_CLK_O_MSK (((1U << GLB_CFG_INV_RF_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF_TEST_CLK_O_POS) +#define GLB_CFG_INV_RF_TEST_CLK_O_UMSK (~(((1U << GLB_CFG_INV_RF_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF_TEST_CLK_O_POS)) +#define GLB_CFG_INV_ETH_RX_CLK GLB_CFG_INV_ETH_RX_CLK +#define GLB_CFG_INV_ETH_RX_CLK_POS (10U) +#define GLB_CFG_INV_ETH_RX_CLK_LEN (1U) +#define GLB_CFG_INV_ETH_RX_CLK_MSK (((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS) +#define GLB_CFG_INV_ETH_RX_CLK_UMSK (~(((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS)) +#define GLB_I2C_CLK_DIV GLB_I2C_CLK_DIV +#define GLB_I2C_CLK_DIV_POS (16U) +#define GLB_I2C_CLK_DIV_LEN (8U) +#define GLB_I2C_CLK_DIV_MSK (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS) +#define GLB_I2C_CLK_DIV_UMSK (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)) +#define GLB_I2C_CLK_EN GLB_I2C_CLK_EN +#define GLB_I2C_CLK_EN_POS (24U) +#define GLB_I2C_CLK_EN_LEN (1U) +#define GLB_I2C_CLK_EN_MSK (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS) +#define GLB_I2C_CLK_EN_UMSK (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)) +#define GLB_CHIP_CLK_OUT_0_SEL GLB_CHIP_CLK_OUT_0_SEL +#define GLB_CHIP_CLK_OUT_0_SEL_POS (28U) +#define GLB_CHIP_CLK_OUT_0_SEL_LEN (2U) +#define GLB_CHIP_CLK_OUT_0_SEL_MSK (((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS) +#define GLB_CHIP_CLK_OUT_0_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS)) +#define GLB_CHIP_CLK_OUT_1_SEL GLB_CHIP_CLK_OUT_1_SEL +#define GLB_CHIP_CLK_OUT_1_SEL_POS (30U) +#define GLB_CHIP_CLK_OUT_1_SEL_LEN (2U) +#define GLB_CHIP_CLK_OUT_1_SEL_MSK (((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS) +#define GLB_CHIP_CLK_OUT_1_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS)) + +/* 0x10 : swrst_cfg0 */ +#define GLB_SWRST_CFG0_OFFSET (0x10) +#define GLB_SWRST_S00 GLB_SWRST_S00 +#define GLB_SWRST_S00_POS (0U) +#define GLB_SWRST_S00_LEN (1U) +#define GLB_SWRST_S00_MSK (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS) +#define GLB_SWRST_S00_UMSK (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)) +#define GLB_SWRST_S01 GLB_SWRST_S01 +#define GLB_SWRST_S01_POS (1U) +#define GLB_SWRST_S01_LEN (1U) +#define GLB_SWRST_S01_MSK (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS) +#define GLB_SWRST_S01_UMSK (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)) +#define GLB_SWRST_S20 GLB_SWRST_S20 +#define GLB_SWRST_S20_POS (4U) +#define GLB_SWRST_S20_LEN (1U) +#define GLB_SWRST_S20_MSK (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS) +#define GLB_SWRST_S20_UMSK (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)) +#define GLB_SWRST_S30 GLB_SWRST_S30 +#define GLB_SWRST_S30_POS (8U) +#define GLB_SWRST_S30_LEN (1U) +#define GLB_SWRST_S30_MSK (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS) +#define GLB_SWRST_S30_UMSK (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)) + +/* 0x14 : swrst_cfg1 */ +#define GLB_SWRST_CFG1_OFFSET (0x14) +#define GLB_SWRST_S10 GLB_SWRST_S10 +#define GLB_SWRST_S10_POS (0U) +#define GLB_SWRST_S10_LEN (1U) +#define GLB_SWRST_S10_MSK (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS) +#define GLB_SWRST_S10_UMSK (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)) +#define GLB_SWRST_S11 GLB_SWRST_S11 +#define GLB_SWRST_S11_POS (1U) +#define GLB_SWRST_S11_LEN (1U) +#define GLB_SWRST_S11_MSK (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS) +#define GLB_SWRST_S11_UMSK (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)) +#define GLB_SWRST_S12 GLB_SWRST_S12 +#define GLB_SWRST_S12_POS (2U) +#define GLB_SWRST_S12_LEN (1U) +#define GLB_SWRST_S12_MSK (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS) +#define GLB_SWRST_S12_UMSK (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)) +#define GLB_SWRST_S13 GLB_SWRST_S13 +#define GLB_SWRST_S13_POS (3U) +#define GLB_SWRST_S13_LEN (1U) +#define GLB_SWRST_S13_MSK (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS) +#define GLB_SWRST_S13_UMSK (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)) +#define GLB_SWRST_S14 GLB_SWRST_S14 +#define GLB_SWRST_S14_POS (4U) +#define GLB_SWRST_S14_LEN (1U) +#define GLB_SWRST_S14_MSK (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS) +#define GLB_SWRST_S14_UMSK (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)) +#define GLB_SWRST_S15 GLB_SWRST_S15 +#define GLB_SWRST_S15_POS (5U) +#define GLB_SWRST_S15_LEN (1U) +#define GLB_SWRST_S15_MSK (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS) +#define GLB_SWRST_S15_UMSK (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)) +#define GLB_SWRST_S16 GLB_SWRST_S16 +#define GLB_SWRST_S16_POS (6U) +#define GLB_SWRST_S16_LEN (1U) +#define GLB_SWRST_S16_MSK (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS) +#define GLB_SWRST_S16_UMSK (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)) +#define GLB_SWRST_S17 GLB_SWRST_S17 +#define GLB_SWRST_S17_POS (7U) +#define GLB_SWRST_S17_LEN (1U) +#define GLB_SWRST_S17_MSK (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS) +#define GLB_SWRST_S17_UMSK (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)) +#define GLB_SWRST_S18 GLB_SWRST_S18 +#define GLB_SWRST_S18_POS (8U) +#define GLB_SWRST_S18_LEN (1U) +#define GLB_SWRST_S18_MSK (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS) +#define GLB_SWRST_S18_UMSK (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)) +#define GLB_SWRST_S19 GLB_SWRST_S19 +#define GLB_SWRST_S19_POS (9U) +#define GLB_SWRST_S19_LEN (1U) +#define GLB_SWRST_S19_MSK (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS) +#define GLB_SWRST_S19_UMSK (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)) +#define GLB_SWRST_S1A GLB_SWRST_S1A +#define GLB_SWRST_S1A_POS (10U) +#define GLB_SWRST_S1A_LEN (1U) +#define GLB_SWRST_S1A_MSK (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS) +#define GLB_SWRST_S1A_UMSK (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)) +#define GLB_SWRST_S1B GLB_SWRST_S1B +#define GLB_SWRST_S1B_POS (11U) +#define GLB_SWRST_S1B_LEN (1U) +#define GLB_SWRST_S1B_MSK (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS) +#define GLB_SWRST_S1B_UMSK (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)) +#define GLB_SWRST_S1C GLB_SWRST_S1C +#define GLB_SWRST_S1C_POS (12U) +#define GLB_SWRST_S1C_LEN (1U) +#define GLB_SWRST_S1C_MSK (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS) +#define GLB_SWRST_S1C_UMSK (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)) +#define GLB_SWRST_S1D GLB_SWRST_S1D +#define GLB_SWRST_S1D_POS (13U) +#define GLB_SWRST_S1D_LEN (1U) +#define GLB_SWRST_S1D_MSK (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS) +#define GLB_SWRST_S1D_UMSK (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)) +#define GLB_SWRST_S1E GLB_SWRST_S1E +#define GLB_SWRST_S1E_POS (14U) +#define GLB_SWRST_S1E_LEN (1U) +#define GLB_SWRST_S1E_MSK (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS) +#define GLB_SWRST_S1E_UMSK (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)) +#define GLB_SWRST_S1F GLB_SWRST_S1F +#define GLB_SWRST_S1F_POS (15U) +#define GLB_SWRST_S1F_LEN (1U) +#define GLB_SWRST_S1F_MSK (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS) +#define GLB_SWRST_S1F_UMSK (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)) +#define GLB_SWRST_S1A0 GLB_SWRST_S1A0 +#define GLB_SWRST_S1A0_POS (16U) +#define GLB_SWRST_S1A0_LEN (1U) +#define GLB_SWRST_S1A0_MSK (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS) +#define GLB_SWRST_S1A0_UMSK (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)) +#define GLB_SWRST_S1A1 GLB_SWRST_S1A1 +#define GLB_SWRST_S1A1_POS (17U) +#define GLB_SWRST_S1A1_LEN (1U) +#define GLB_SWRST_S1A1_MSK (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS) +#define GLB_SWRST_S1A1_UMSK (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)) +#define GLB_SWRST_S1A2 GLB_SWRST_S1A2 +#define GLB_SWRST_S1A2_POS (18U) +#define GLB_SWRST_S1A2_LEN (1U) +#define GLB_SWRST_S1A2_MSK (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS) +#define GLB_SWRST_S1A2_UMSK (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)) +#define GLB_SWRST_S1A3 GLB_SWRST_S1A3 +#define GLB_SWRST_S1A3_POS (19U) +#define GLB_SWRST_S1A3_LEN (1U) +#define GLB_SWRST_S1A3_MSK (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS) +#define GLB_SWRST_S1A3_UMSK (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)) +#define GLB_SWRST_S1A4 GLB_SWRST_S1A4 +#define GLB_SWRST_S1A4_POS (20U) +#define GLB_SWRST_S1A4_LEN (1U) +#define GLB_SWRST_S1A4_MSK (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS) +#define GLB_SWRST_S1A4_UMSK (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)) +#define GLB_SWRST_S1A5 GLB_SWRST_S1A5 +#define GLB_SWRST_S1A5_POS (21U) +#define GLB_SWRST_S1A5_LEN (1U) +#define GLB_SWRST_S1A5_MSK (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS) +#define GLB_SWRST_S1A5_UMSK (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)) +#define GLB_SWRST_S1A6 GLB_SWRST_S1A6 +#define GLB_SWRST_S1A6_POS (22U) +#define GLB_SWRST_S1A6_LEN (1U) +#define GLB_SWRST_S1A6_MSK (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS) +#define GLB_SWRST_S1A6_UMSK (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)) +#define GLB_SWRST_S1A7 GLB_SWRST_S1A7 +#define GLB_SWRST_S1A7_POS (23U) +#define GLB_SWRST_S1A7_LEN (1U) +#define GLB_SWRST_S1A7_MSK (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS) +#define GLB_SWRST_S1A7_UMSK (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)) +#define GLB_SWRST_S1A8 GLB_SWRST_S1A8 +#define GLB_SWRST_S1A8_POS (24U) +#define GLB_SWRST_S1A8_LEN (1U) +#define GLB_SWRST_S1A8_MSK (((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS) +#define GLB_SWRST_S1A8_UMSK (~(((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS)) +#define GLB_SWRST_S1A9 GLB_SWRST_S1A9 +#define GLB_SWRST_S1A9_POS (25U) +#define GLB_SWRST_S1A9_LEN (1U) +#define GLB_SWRST_S1A9_MSK (((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS) +#define GLB_SWRST_S1A9_UMSK (~(((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS)) +#define GLB_SWRST_S1AA GLB_SWRST_S1AA +#define GLB_SWRST_S1AA_POS (26U) +#define GLB_SWRST_S1AA_LEN (1U) +#define GLB_SWRST_S1AA_MSK (((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS) +#define GLB_SWRST_S1AA_UMSK (~(((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS)) +#define GLB_SWRST_S1AB GLB_SWRST_S1AB +#define GLB_SWRST_S1AB_POS (27U) +#define GLB_SWRST_S1AB_LEN (1U) +#define GLB_SWRST_S1AB_MSK (((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS) +#define GLB_SWRST_S1AB_UMSK (~(((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS)) +#define GLB_SWRST_S1AC GLB_SWRST_S1AC +#define GLB_SWRST_S1AC_POS (28U) +#define GLB_SWRST_S1AC_LEN (1U) +#define GLB_SWRST_S1AC_MSK (((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS) +#define GLB_SWRST_S1AC_UMSK (~(((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS)) +#define GLB_SWRST_S1AD GLB_SWRST_S1AD +#define GLB_SWRST_S1AD_POS (29U) +#define GLB_SWRST_S1AD_LEN (1U) +#define GLB_SWRST_S1AD_MSK (((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS) +#define GLB_SWRST_S1AD_UMSK (~(((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS)) +#define GLB_SWRST_S1AE GLB_SWRST_S1AE +#define GLB_SWRST_S1AE_POS (30U) +#define GLB_SWRST_S1AE_LEN (1U) +#define GLB_SWRST_S1AE_MSK (((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS) +#define GLB_SWRST_S1AE_UMSK (~(((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS)) + +/* 0x18 : swrst_cfg2 */ +#define GLB_SWRST_CFG2_OFFSET (0x18) +#define GLB_REG_CTRL_PWRON_RST GLB_REG_CTRL_PWRON_RST +#define GLB_REG_CTRL_PWRON_RST_POS (0U) +#define GLB_REG_CTRL_PWRON_RST_LEN (1U) +#define GLB_REG_CTRL_PWRON_RST_MSK (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS) +#define GLB_REG_CTRL_PWRON_RST_UMSK (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)) +#define GLB_REG_CTRL_CPU_RESET GLB_REG_CTRL_CPU_RESET +#define GLB_REG_CTRL_CPU_RESET_POS (1U) +#define GLB_REG_CTRL_CPU_RESET_LEN (1U) +#define GLB_REG_CTRL_CPU_RESET_MSK (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS) +#define GLB_REG_CTRL_CPU_RESET_UMSK (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)) +#define GLB_REG_CTRL_SYS_RESET GLB_REG_CTRL_SYS_RESET +#define GLB_REG_CTRL_SYS_RESET_POS (2U) +#define GLB_REG_CTRL_SYS_RESET_LEN (1U) +#define GLB_REG_CTRL_SYS_RESET_MSK (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS) +#define GLB_REG_CTRL_SYS_RESET_UMSK (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)) +#define GLB_REG_CTRL_RESET_DUMMY GLB_REG_CTRL_RESET_DUMMY +#define GLB_REG_CTRL_RESET_DUMMY_POS (4U) +#define GLB_REG_CTRL_RESET_DUMMY_LEN (4U) +#define GLB_REG_CTRL_RESET_DUMMY_MSK (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS) +#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)) +#define GLB_PKA_CLK_SEL GLB_PKA_CLK_SEL +#define GLB_PKA_CLK_SEL_POS (24U) +#define GLB_PKA_CLK_SEL_LEN (1U) +#define GLB_PKA_CLK_SEL_MSK (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS) +#define GLB_PKA_CLK_SEL_UMSK (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)) + +/* 0x1C : swrst_cfg3 */ +#define GLB_SWRST_CFG3_OFFSET (0x1C) + +/* 0x20 : cgen_cfg0 */ +#define GLB_CGEN_CFG0_OFFSET (0x20) +#define GLB_CGEN_M GLB_CGEN_M +#define GLB_CGEN_M_POS (0U) +#define GLB_CGEN_M_LEN (8U) +#define GLB_CGEN_M_MSK (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS) +#define GLB_CGEN_M_UMSK (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)) + +/* 0x24 : cgen_cfg1 */ +#define GLB_CGEN_CFG1_OFFSET (0x24) +#define GLB_CGEN_S1 GLB_CGEN_S1 +#define GLB_CGEN_S1_POS (0U) +#define GLB_CGEN_S1_LEN (16U) +#define GLB_CGEN_S1_MSK (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS) +#define GLB_CGEN_S1_UMSK (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)) +#define GLB_CGEN_S1A GLB_CGEN_S1A +#define GLB_CGEN_S1A_POS (16U) +#define GLB_CGEN_S1A_LEN (16U) +#define GLB_CGEN_S1A_MSK (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS) +#define GLB_CGEN_S1A_UMSK (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)) + +/* 0x28 : cgen_cfg2 */ +#define GLB_CGEN_CFG2_OFFSET (0x28) +#define GLB_CGEN_S2 GLB_CGEN_S2 +#define GLB_CGEN_S2_POS (0U) +#define GLB_CGEN_S2_LEN (1U) +#define GLB_CGEN_S2_MSK (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS) +#define GLB_CGEN_S2_UMSK (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)) +#define GLB_CGEN_S3 GLB_CGEN_S3 +#define GLB_CGEN_S3_POS (4U) +#define GLB_CGEN_S3_LEN (1U) +#define GLB_CGEN_S3_MSK (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS) +#define GLB_CGEN_S3_UMSK (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)) + +/* 0x2C : cgen_cfg3 */ +#define GLB_CGEN_CFG3_OFFSET (0x2C) + +/* 0x30 : MBIST_CTL */ +#define GLB_MBIST_CTL_OFFSET (0x30) +#define GLB_IROM_MBIST_MODE GLB_IROM_MBIST_MODE +#define GLB_IROM_MBIST_MODE_POS (0U) +#define GLB_IROM_MBIST_MODE_LEN (1U) +#define GLB_IROM_MBIST_MODE_MSK (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS) +#define GLB_IROM_MBIST_MODE_UMSK (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)) +#define GLB_HSRAM_MEM_MBIST_MODE GLB_HSRAM_MEM_MBIST_MODE +#define GLB_HSRAM_MEM_MBIST_MODE_POS (1U) +#define GLB_HSRAM_MEM_MBIST_MODE_LEN (1U) +#define GLB_HSRAM_MEM_MBIST_MODE_MSK (((1U << GLB_HSRAM_MEM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_MODE_POS) +#define GLB_HSRAM_MEM_MBIST_MODE_UMSK (~(((1U << GLB_HSRAM_MEM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_MODE_POS)) +#define GLB_HSRAM_CACHE_MBIST_MODE GLB_HSRAM_CACHE_MBIST_MODE +#define GLB_HSRAM_CACHE_MBIST_MODE_POS (2U) +#define GLB_HSRAM_CACHE_MBIST_MODE_LEN (1U) +#define GLB_HSRAM_CACHE_MBIST_MODE_MSK (((1U << GLB_HSRAM_CACHE_MBIST_MODE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_MODE_POS) +#define GLB_HSRAM_CACHE_MBIST_MODE_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_MODE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_MODE_POS)) +#define GLB_TAG_MBIST_MODE GLB_TAG_MBIST_MODE +#define GLB_TAG_MBIST_MODE_POS (3U) +#define GLB_TAG_MBIST_MODE_LEN (1U) +#define GLB_TAG_MBIST_MODE_MSK (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS) +#define GLB_TAG_MBIST_MODE_UMSK (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)) +#define GLB_OCRAM_MBIST_MODE GLB_OCRAM_MBIST_MODE +#define GLB_OCRAM_MBIST_MODE_POS (4U) +#define GLB_OCRAM_MBIST_MODE_LEN (1U) +#define GLB_OCRAM_MBIST_MODE_MSK (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS) +#define GLB_OCRAM_MBIST_MODE_UMSK (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)) +#define GLB_EM_RAM_MBIST_MODE GLB_EM_RAM_MBIST_MODE +#define GLB_EM_RAM_MBIST_MODE_POS (5U) +#define GLB_EM_RAM_MBIST_MODE_LEN (1U) +#define GLB_EM_RAM_MBIST_MODE_MSK (((1U << GLB_EM_RAM_MBIST_MODE_LEN) - 1) << GLB_EM_RAM_MBIST_MODE_POS) +#define GLB_EM_RAM_MBIST_MODE_UMSK (~(((1U << GLB_EM_RAM_MBIST_MODE_LEN) - 1) << GLB_EM_RAM_MBIST_MODE_POS)) +#define GLB_REG_MBIST_RST_N GLB_REG_MBIST_RST_N +#define GLB_REG_MBIST_RST_N_POS (31U) +#define GLB_REG_MBIST_RST_N_LEN (1U) +#define GLB_REG_MBIST_RST_N_MSK (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS) +#define GLB_REG_MBIST_RST_N_UMSK (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)) + +/* 0x34 : MBIST_STAT */ +#define GLB_MBIST_STAT_OFFSET (0x34) +#define GLB_IROM_MBIST_DONE GLB_IROM_MBIST_DONE +#define GLB_IROM_MBIST_DONE_POS (0U) +#define GLB_IROM_MBIST_DONE_LEN (1U) +#define GLB_IROM_MBIST_DONE_MSK (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS) +#define GLB_IROM_MBIST_DONE_UMSK (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)) +#define GLB_HSRAM_MEM_MBIST_DONE GLB_HSRAM_MEM_MBIST_DONE +#define GLB_HSRAM_MEM_MBIST_DONE_POS (1U) +#define GLB_HSRAM_MEM_MBIST_DONE_LEN (1U) +#define GLB_HSRAM_MEM_MBIST_DONE_MSK (((1U << GLB_HSRAM_MEM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_DONE_POS) +#define GLB_HSRAM_MEM_MBIST_DONE_UMSK (~(((1U << GLB_HSRAM_MEM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_DONE_POS)) +#define GLB_HSRAM_CACHE_MBIST_DONE GLB_HSRAM_CACHE_MBIST_DONE +#define GLB_HSRAM_CACHE_MBIST_DONE_POS (2U) +#define GLB_HSRAM_CACHE_MBIST_DONE_LEN (1U) +#define GLB_HSRAM_CACHE_MBIST_DONE_MSK (((1U << GLB_HSRAM_CACHE_MBIST_DONE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_DONE_POS) +#define GLB_HSRAM_CACHE_MBIST_DONE_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_DONE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_DONE_POS)) +#define GLB_TAG_MBIST_DONE GLB_TAG_MBIST_DONE +#define GLB_TAG_MBIST_DONE_POS (3U) +#define GLB_TAG_MBIST_DONE_LEN (1U) +#define GLB_TAG_MBIST_DONE_MSK (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS) +#define GLB_TAG_MBIST_DONE_UMSK (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)) +#define GLB_OCRAM_MBIST_DONE GLB_OCRAM_MBIST_DONE +#define GLB_OCRAM_MBIST_DONE_POS (4U) +#define GLB_OCRAM_MBIST_DONE_LEN (1U) +#define GLB_OCRAM_MBIST_DONE_MSK (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS) +#define GLB_OCRAM_MBIST_DONE_UMSK (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)) +#define GLB_EM_RAM_MBIST_DONE GLB_EM_RAM_MBIST_DONE +#define GLB_EM_RAM_MBIST_DONE_POS (5U) +#define GLB_EM_RAM_MBIST_DONE_LEN (1U) +#define GLB_EM_RAM_MBIST_DONE_MSK (((1U << GLB_EM_RAM_MBIST_DONE_LEN) - 1) << GLB_EM_RAM_MBIST_DONE_POS) +#define GLB_EM_RAM_MBIST_DONE_UMSK (~(((1U << GLB_EM_RAM_MBIST_DONE_LEN) - 1) << GLB_EM_RAM_MBIST_DONE_POS)) +#define GLB_IROM_MBIST_FAIL GLB_IROM_MBIST_FAIL +#define GLB_IROM_MBIST_FAIL_POS (16U) +#define GLB_IROM_MBIST_FAIL_LEN (1U) +#define GLB_IROM_MBIST_FAIL_MSK (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS) +#define GLB_IROM_MBIST_FAIL_UMSK (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)) +#define GLB_HSRAM_MEM_MBIST_FAIL GLB_HSRAM_MEM_MBIST_FAIL +#define GLB_HSRAM_MEM_MBIST_FAIL_POS (17U) +#define GLB_HSRAM_MEM_MBIST_FAIL_LEN (1U) +#define GLB_HSRAM_MEM_MBIST_FAIL_MSK (((1U << GLB_HSRAM_MEM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MEM_MBIST_FAIL_POS) +#define GLB_HSRAM_MEM_MBIST_FAIL_UMSK (~(((1U << GLB_HSRAM_MEM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MEM_MBIST_FAIL_POS)) +#define GLB_HSRAM_CACHE_MBIST_FAIL GLB_HSRAM_CACHE_MBIST_FAIL +#define GLB_HSRAM_CACHE_MBIST_FAIL_POS (18U) +#define GLB_HSRAM_CACHE_MBIST_FAIL_LEN (1U) +#define GLB_HSRAM_CACHE_MBIST_FAIL_MSK (((1U << GLB_HSRAM_CACHE_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_FAIL_POS) +#define GLB_HSRAM_CACHE_MBIST_FAIL_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_FAIL_POS)) +#define GLB_TAG_MBIST_FAIL GLB_TAG_MBIST_FAIL +#define GLB_TAG_MBIST_FAIL_POS (19U) +#define GLB_TAG_MBIST_FAIL_LEN (1U) +#define GLB_TAG_MBIST_FAIL_MSK (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS) +#define GLB_TAG_MBIST_FAIL_UMSK (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)) +#define GLB_OCRAM_MBIST_FAIL GLB_OCRAM_MBIST_FAIL +#define GLB_OCRAM_MBIST_FAIL_POS (20U) +#define GLB_OCRAM_MBIST_FAIL_LEN (1U) +#define GLB_OCRAM_MBIST_FAIL_MSK (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS) +#define GLB_OCRAM_MBIST_FAIL_UMSK (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)) +#define GLB_EM_RAM_MBIST_FAIL GLB_EM_RAM_MBIST_FAIL +#define GLB_EM_RAM_MBIST_FAIL_POS (21U) +#define GLB_EM_RAM_MBIST_FAIL_LEN (1U) +#define GLB_EM_RAM_MBIST_FAIL_MSK (((1U << GLB_EM_RAM_MBIST_FAIL_LEN) - 1) << GLB_EM_RAM_MBIST_FAIL_POS) +#define GLB_EM_RAM_MBIST_FAIL_UMSK (~(((1U << GLB_EM_RAM_MBIST_FAIL_LEN) - 1) << GLB_EM_RAM_MBIST_FAIL_POS)) + +/* 0x50 : bmx_cfg1 */ +#define GLB_BMX_CFG1_OFFSET (0x50) +#define GLB_BMX_TIMEOUT_EN GLB_BMX_TIMEOUT_EN +#define GLB_BMX_TIMEOUT_EN_POS (0U) +#define GLB_BMX_TIMEOUT_EN_LEN (4U) +#define GLB_BMX_TIMEOUT_EN_MSK (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS) +#define GLB_BMX_TIMEOUT_EN_UMSK (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)) +#define GLB_BMX_ARB_MODE GLB_BMX_ARB_MODE +#define GLB_BMX_ARB_MODE_POS (4U) +#define GLB_BMX_ARB_MODE_LEN (2U) +#define GLB_BMX_ARB_MODE_MSK (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS) +#define GLB_BMX_ARB_MODE_UMSK (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)) +#define GLB_BMX_ERR_EN GLB_BMX_ERR_EN +#define GLB_BMX_ERR_EN_POS (8U) +#define GLB_BMX_ERR_EN_LEN (1U) +#define GLB_BMX_ERR_EN_MSK (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS) +#define GLB_BMX_ERR_EN_UMSK (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)) +#define GLB_BMX_BUSY_OPTION_DIS GLB_BMX_BUSY_OPTION_DIS +#define GLB_BMX_BUSY_OPTION_DIS_POS (9U) +#define GLB_BMX_BUSY_OPTION_DIS_LEN (1U) +#define GLB_BMX_BUSY_OPTION_DIS_MSK (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS) +#define GLB_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)) +#define GLB_BMX_GATING_DIS GLB_BMX_GATING_DIS +#define GLB_BMX_GATING_DIS_POS (10U) +#define GLB_BMX_GATING_DIS_LEN (1U) +#define GLB_BMX_GATING_DIS_MSK (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS) +#define GLB_BMX_GATING_DIS_UMSK (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)) +#define GLB_HSEL_OPTION GLB_HSEL_OPTION +#define GLB_HSEL_OPTION_POS (12U) +#define GLB_HSEL_OPTION_LEN (4U) +#define GLB_HSEL_OPTION_MSK (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS) +#define GLB_HSEL_OPTION_UMSK (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)) +#define GLB_PDS_APB_CFG GLB_PDS_APB_CFG +#define GLB_PDS_APB_CFG_POS (16U) +#define GLB_PDS_APB_CFG_LEN (8U) +#define GLB_PDS_APB_CFG_MSK (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS) +#define GLB_PDS_APB_CFG_UMSK (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)) +#define GLB_HBN_APB_CFG GLB_HBN_APB_CFG +#define GLB_HBN_APB_CFG_POS (24U) +#define GLB_HBN_APB_CFG_LEN (8U) +#define GLB_HBN_APB_CFG_MSK (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS) +#define GLB_HBN_APB_CFG_UMSK (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)) + +/* 0x54 : bmx_cfg2 */ +#define GLB_BMX_CFG2_OFFSET (0x54) +#define GLB_BMX_ERR_ADDR_DIS GLB_BMX_ERR_ADDR_DIS +#define GLB_BMX_ERR_ADDR_DIS_POS (0U) +#define GLB_BMX_ERR_ADDR_DIS_LEN (1U) +#define GLB_BMX_ERR_ADDR_DIS_MSK (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS) +#define GLB_BMX_ERR_ADDR_DIS_UMSK (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)) +#define GLB_BMX_ERR_DEC GLB_BMX_ERR_DEC +#define GLB_BMX_ERR_DEC_POS (4U) +#define GLB_BMX_ERR_DEC_LEN (1U) +#define GLB_BMX_ERR_DEC_MSK (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS) +#define GLB_BMX_ERR_DEC_UMSK (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)) +#define GLB_BMX_ERR_TZ GLB_BMX_ERR_TZ +#define GLB_BMX_ERR_TZ_POS (5U) +#define GLB_BMX_ERR_TZ_LEN (1U) +#define GLB_BMX_ERR_TZ_MSK (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS) +#define GLB_BMX_ERR_TZ_UMSK (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)) +#define GLB_REG_W_THRE_BMX GLB_REG_W_THRE_BMX +#define GLB_REG_W_THRE_BMX_POS (8U) +#define GLB_REG_W_THRE_BMX_LEN (2U) +#define GLB_REG_W_THRE_BMX_MSK (((1U << GLB_REG_W_THRE_BMX_LEN) - 1) << GLB_REG_W_THRE_BMX_POS) +#define GLB_REG_W_THRE_BMX_UMSK (~(((1U << GLB_REG_W_THRE_BMX_LEN) - 1) << GLB_REG_W_THRE_BMX_POS)) +#define GLB_REG_W_THRE_L1C GLB_REG_W_THRE_L1C +#define GLB_REG_W_THRE_L1C_POS (10U) +#define GLB_REG_W_THRE_L1C_LEN (2U) +#define GLB_REG_W_THRE_L1C_MSK (((1U << GLB_REG_W_THRE_L1C_LEN) - 1) << GLB_REG_W_THRE_L1C_POS) +#define GLB_REG_W_THRE_L1C_UMSK (~(((1U << GLB_REG_W_THRE_L1C_LEN) - 1) << GLB_REG_W_THRE_L1C_POS)) +#define GLB_BMX_DBG_SEL GLB_BMX_DBG_SEL +#define GLB_BMX_DBG_SEL_POS (28U) +#define GLB_BMX_DBG_SEL_LEN (4U) +#define GLB_BMX_DBG_SEL_MSK (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS) +#define GLB_BMX_DBG_SEL_UMSK (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)) + +/* 0x58 : bmx_err_addr */ +#define GLB_BMX_ERR_ADDR_OFFSET (0x58) +#define GLB_BMX_ERR_ADDR GLB_BMX_ERR_ADDR +#define GLB_BMX_ERR_ADDR_POS (0U) +#define GLB_BMX_ERR_ADDR_LEN (32U) +#define GLB_BMX_ERR_ADDR_MSK (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS) +#define GLB_BMX_ERR_ADDR_UMSK (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)) + +/* 0x5C : bmx_dbg_out */ +#define GLB_BMX_DBG_OUT_OFFSET (0x5C) +#define GLB_BMX_DBG_OUT GLB_BMX_DBG_OUT +#define GLB_BMX_DBG_OUT_POS (0U) +#define GLB_BMX_DBG_OUT_LEN (32U) +#define GLB_BMX_DBG_OUT_MSK (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS) +#define GLB_BMX_DBG_OUT_UMSK (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)) + +/* 0x60 : rsv0 */ +#define GLB_RSV0_OFFSET (0x60) + +/* 0x64 : rsv1 */ +#define GLB_RSV1_OFFSET (0x64) + +/* 0x68 : rsv2 */ +#define GLB_RSV2_OFFSET (0x68) + +/* 0x6C : rsv3 */ +#define GLB_RSV3_OFFSET (0x6C) + +/* 0x70 : sram_ret */ +#define GLB_SRAM_RET_OFFSET (0x70) +#define GLB_REG_SRAM_RET GLB_REG_SRAM_RET +#define GLB_REG_SRAM_RET_POS (0U) +#define GLB_REG_SRAM_RET_LEN (32U) +#define GLB_REG_SRAM_RET_MSK (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS) +#define GLB_REG_SRAM_RET_UMSK (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)) + +/* 0x74 : sram_slp */ +#define GLB_SRAM_SLP_OFFSET (0x74) +#define GLB_REG_SRAM_SLP GLB_REG_SRAM_SLP +#define GLB_REG_SRAM_SLP_POS (0U) +#define GLB_REG_SRAM_SLP_LEN (32U) +#define GLB_REG_SRAM_SLP_MSK (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS) +#define GLB_REG_SRAM_SLP_UMSK (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)) + +/* 0x78 : sram_parm */ +#define GLB_SRAM_PARM_OFFSET (0x78) +#define GLB_REG_SRAM_PARM GLB_REG_SRAM_PARM +#define GLB_REG_SRAM_PARM_POS (0U) +#define GLB_REG_SRAM_PARM_LEN (32U) +#define GLB_REG_SRAM_PARM_MSK (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS) +#define GLB_REG_SRAM_PARM_UMSK (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)) + +/* 0x7C : seam_misc */ +#define GLB_SEAM_MISC_OFFSET (0x7C) +#define GLB_EM_SEL GLB_EM_SEL +#define GLB_EM_SEL_POS (0U) +#define GLB_EM_SEL_LEN (4U) +#define GLB_EM_SEL_MSK (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS) +#define GLB_EM_SEL_UMSK (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)) + +/* 0x80 : glb_parm */ +#define GLB_PARM_OFFSET (0x80) +#define GLB_JTAG_SWAP_SET GLB_JTAG_SWAP_SET +#define GLB_JTAG_SWAP_SET_POS (0U) +#define GLB_JTAG_SWAP_SET_LEN (8U) +#define GLB_JTAG_SWAP_SET_MSK (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS) +#define GLB_JTAG_SWAP_SET_UMSK (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)) +#define GLB_CFG_SFLASH2_SWAP_IO0_IO3 GLB_CFG_SFLASH2_SWAP_IO0_IO3 +#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS (8U) +#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN (1U) +#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_MSK (((1U << GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS) +#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_UMSK (~(((1U << GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS)) +#define GLB_CFG_SFLASH2_SWAP_CS_IO2 GLB_CFG_SFLASH2_SWAP_CS_IO2 +#define GLB_CFG_SFLASH2_SWAP_CS_IO2_POS (9U) +#define GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN (1U) +#define GLB_CFG_SFLASH2_SWAP_CS_IO2_MSK (((1U << GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_CS_IO2_POS) +#define GLB_CFG_SFLASH2_SWAP_CS_IO2_UMSK (~(((1U << GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_CS_IO2_POS)) +#define GLB_CFG_FLASH_SCENARIO GLB_CFG_FLASH_SCENARIO +#define GLB_CFG_FLASH_SCENARIO_POS (10U) +#define GLB_CFG_FLASH_SCENARIO_LEN (2U) +#define GLB_CFG_FLASH_SCENARIO_MSK (((1U << GLB_CFG_FLASH_SCENARIO_LEN) - 1) << GLB_CFG_FLASH_SCENARIO_POS) +#define GLB_CFG_FLASH_SCENARIO_UMSK (~(((1U << GLB_CFG_FLASH_SCENARIO_LEN) - 1) << GLB_CFG_FLASH_SCENARIO_POS)) +#define GLB_REG_SPI_0_MASTER_MODE GLB_REG_SPI_0_MASTER_MODE +#define GLB_REG_SPI_0_MASTER_MODE_POS (12U) +#define GLB_REG_SPI_0_MASTER_MODE_LEN (1U) +#define GLB_REG_SPI_0_MASTER_MODE_MSK (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS) +#define GLB_REG_SPI_0_MASTER_MODE_UMSK (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)) +#define GLB_REG_SPI_0_SWAP GLB_REG_SPI_0_SWAP +#define GLB_REG_SPI_0_SWAP_POS (13U) +#define GLB_REG_SPI_0_SWAP_LEN (1U) +#define GLB_REG_SPI_0_SWAP_MSK (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS) +#define GLB_REG_SPI_0_SWAP_UMSK (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)) +#define GLB_REG_CCI_USE_JTAG_PIN GLB_REG_CCI_USE_JTAG_PIN +#define GLB_REG_CCI_USE_JTAG_PIN_POS (16U) +#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1U) +#define GLB_REG_CCI_USE_JTAG_PIN_MSK (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS) +#define GLB_REG_CCI_USE_JTAG_PIN_UMSK (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)) +#define GLB_P1_ADC_TEST_WITH_CCI GLB_P1_ADC_TEST_WITH_CCI +#define GLB_P1_ADC_TEST_WITH_CCI_POS (17U) +#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1U) +#define GLB_P1_ADC_TEST_WITH_CCI_MSK (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS) +#define GLB_P1_ADC_TEST_WITH_CCI_UMSK (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)) +#define GLB_P2_DAC_TEST_WITH_CCI GLB_P2_DAC_TEST_WITH_CCI +#define GLB_P2_DAC_TEST_WITH_CCI_POS (18U) +#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1U) +#define GLB_P2_DAC_TEST_WITH_CCI_MSK (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS) +#define GLB_P2_DAC_TEST_WITH_CCI_UMSK (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)) +#define GLB_P3_CCI_USE_IO_0_2_7 GLB_P3_CCI_USE_IO_0_2_7 +#define GLB_P3_CCI_USE_IO_0_2_7_POS (19U) +#define GLB_P3_CCI_USE_IO_0_2_7_LEN (1U) +#define GLB_P3_CCI_USE_IO_0_2_7_MSK (((1U << GLB_P3_CCI_USE_IO_0_2_7_LEN) - 1) << GLB_P3_CCI_USE_IO_0_2_7_POS) +#define GLB_P3_CCI_USE_IO_0_2_7_UMSK (~(((1U << GLB_P3_CCI_USE_IO_0_2_7_LEN) - 1) << GLB_P3_CCI_USE_IO_0_2_7_POS)) +#define GLB_P4_ADC_TEST_WITH_JTAG GLB_P4_ADC_TEST_WITH_JTAG +#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20U) +#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1U) +#define GLB_P4_ADC_TEST_WITH_JTAG_MSK (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS) +#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS)) +#define GLB_P5_DAC_TEST_WITH_JTAG GLB_P5_DAC_TEST_WITH_JTAG +#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21U) +#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1U) +#define GLB_P5_DAC_TEST_WITH_JTAG_MSK (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS) +#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS)) +#define GLB_P6_JTAG_USE_IO_0_2_7 GLB_P6_JTAG_USE_IO_0_2_7 +#define GLB_P6_JTAG_USE_IO_0_2_7_POS (23U) +#define GLB_P6_JTAG_USE_IO_0_2_7_LEN (1U) +#define GLB_P6_JTAG_USE_IO_0_2_7_MSK (((1U << GLB_P6_JTAG_USE_IO_0_2_7_LEN) - 1) << GLB_P6_JTAG_USE_IO_0_2_7_POS) +#define GLB_P6_JTAG_USE_IO_0_2_7_UMSK (~(((1U << GLB_P6_JTAG_USE_IO_0_2_7_LEN) - 1) << GLB_P6_JTAG_USE_IO_0_2_7_POS)) +#define GLB_UART_SWAP_SET GLB_UART_SWAP_SET +#define GLB_UART_SWAP_SET_POS (24U) +#define GLB_UART_SWAP_SET_LEN (4U) +#define GLB_UART_SWAP_SET_MSK (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS) +#define GLB_UART_SWAP_SET_UMSK (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)) +#define GLB_REG_KYS_DRV_VAL GLB_REG_KYS_DRV_VAL +#define GLB_REG_KYS_DRV_VAL_POS (29U) +#define GLB_REG_KYS_DRV_VAL_LEN (1U) +#define GLB_REG_KYS_DRV_VAL_MSK (((1U << GLB_REG_KYS_DRV_VAL_LEN) - 1) << GLB_REG_KYS_DRV_VAL_POS) +#define GLB_REG_KYS_DRV_VAL_UMSK (~(((1U << GLB_REG_KYS_DRV_VAL_LEN) - 1) << GLB_REG_KYS_DRV_VAL_POS)) +#define GLB_REG_EXT_RST_SMT GLB_REG_EXT_RST_SMT +#define GLB_REG_EXT_RST_SMT_POS (30U) +#define GLB_REG_EXT_RST_SMT_LEN (1U) +#define GLB_REG_EXT_RST_SMT_MSK (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS) +#define GLB_REG_EXT_RST_SMT_UMSK (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)) +#define GLB_PIN_SEL_EMAC_CAM GLB_PIN_SEL_EMAC_CAM +#define GLB_PIN_SEL_EMAC_CAM_POS (31U) +#define GLB_PIN_SEL_EMAC_CAM_LEN (1U) +#define GLB_PIN_SEL_EMAC_CAM_MSK (((1U << GLB_PIN_SEL_EMAC_CAM_LEN) - 1) << GLB_PIN_SEL_EMAC_CAM_POS) +#define GLB_PIN_SEL_EMAC_CAM_UMSK (~(((1U << GLB_PIN_SEL_EMAC_CAM_LEN) - 1) << GLB_PIN_SEL_EMAC_CAM_POS)) + +/* 0x84 : PDM_CLK_CTRL */ +#define GLB_PDM_CLK_CTRL_OFFSET (0x84) +#define GLB_REG_PDM0_CLK_DIV GLB_REG_PDM0_CLK_DIV +#define GLB_REG_PDM0_CLK_DIV_POS (0U) +#define GLB_REG_PDM0_CLK_DIV_LEN (6U) +#define GLB_REG_PDM0_CLK_DIV_MSK (((1U << GLB_REG_PDM0_CLK_DIV_LEN) - 1) << GLB_REG_PDM0_CLK_DIV_POS) +#define GLB_REG_PDM0_CLK_DIV_UMSK (~(((1U << GLB_REG_PDM0_CLK_DIV_LEN) - 1) << GLB_REG_PDM0_CLK_DIV_POS)) +#define GLB_REG_PDM0_CLK_EN GLB_REG_PDM0_CLK_EN +#define GLB_REG_PDM0_CLK_EN_POS (7U) +#define GLB_REG_PDM0_CLK_EN_LEN (1U) +#define GLB_REG_PDM0_CLK_EN_MSK (((1U << GLB_REG_PDM0_CLK_EN_LEN) - 1) << GLB_REG_PDM0_CLK_EN_POS) +#define GLB_REG_PDM0_CLK_EN_UMSK (~(((1U << GLB_REG_PDM0_CLK_EN_LEN) - 1) << GLB_REG_PDM0_CLK_EN_POS)) + +/* 0x88 : GPIO_USE_PSRAM__IO */ +#define GLB_GPIO_USE_PSRAM__IO_OFFSET (0x88) +#define GLB_CFG_GPIO_USE_PSRAM_IO GLB_CFG_GPIO_USE_PSRAM_IO +#define GLB_CFG_GPIO_USE_PSRAM_IO_POS (0U) +#define GLB_CFG_GPIO_USE_PSRAM_IO_LEN (6U) +#define GLB_CFG_GPIO_USE_PSRAM_IO_MSK (((1U << GLB_CFG_GPIO_USE_PSRAM_IO_LEN) - 1) << GLB_CFG_GPIO_USE_PSRAM_IO_POS) +#define GLB_CFG_GPIO_USE_PSRAM_IO_UMSK (~(((1U << GLB_CFG_GPIO_USE_PSRAM_IO_LEN) - 1) << GLB_CFG_GPIO_USE_PSRAM_IO_POS)) + +/* 0x90 : CPU_CLK_CFG */ +#define GLB_CPU_CLK_CFG_OFFSET (0x90) +#define GLB_CPU_RTC_DIV GLB_CPU_RTC_DIV +#define GLB_CPU_RTC_DIV_POS (0U) +#define GLB_CPU_RTC_DIV_LEN (17U) +#define GLB_CPU_RTC_DIV_MSK (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS) +#define GLB_CPU_RTC_DIV_UMSK (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)) +#define GLB_CPU_RTC_EN GLB_CPU_RTC_EN +#define GLB_CPU_RTC_EN_POS (18U) +#define GLB_CPU_RTC_EN_LEN (1U) +#define GLB_CPU_RTC_EN_MSK (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS) +#define GLB_CPU_RTC_EN_UMSK (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)) +#define GLB_CPU_RTC_SEL GLB_CPU_RTC_SEL +#define GLB_CPU_RTC_SEL_POS (19U) +#define GLB_CPU_RTC_SEL_LEN (1U) +#define GLB_CPU_RTC_SEL_MSK (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS) +#define GLB_CPU_RTC_SEL_UMSK (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)) +#define GLB_DEBUG_NDRESET_GATE GLB_DEBUG_NDRESET_GATE +#define GLB_DEBUG_NDRESET_GATE_POS (20U) +#define GLB_DEBUG_NDRESET_GATE_LEN (1U) +#define GLB_DEBUG_NDRESET_GATE_MSK (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS) +#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)) + +/* 0xA4 : GPADC_32M_SRC_CTRL */ +#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4) +#define GLB_GPADC_32M_CLK_DIV GLB_GPADC_32M_CLK_DIV +#define GLB_GPADC_32M_CLK_DIV_POS (0U) +#define GLB_GPADC_32M_CLK_DIV_LEN (6U) +#define GLB_GPADC_32M_CLK_DIV_MSK (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS) +#define GLB_GPADC_32M_CLK_DIV_UMSK (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)) +#define GLB_GPADC_32M_CLK_SEL GLB_GPADC_32M_CLK_SEL +#define GLB_GPADC_32M_CLK_SEL_POS (7U) +#define GLB_GPADC_32M_CLK_SEL_LEN (1U) +#define GLB_GPADC_32M_CLK_SEL_MSK (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS) +#define GLB_GPADC_32M_CLK_SEL_UMSK (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)) +#define GLB_GPADC_32M_DIV_EN GLB_GPADC_32M_DIV_EN +#define GLB_GPADC_32M_DIV_EN_POS (8U) +#define GLB_GPADC_32M_DIV_EN_LEN (1U) +#define GLB_GPADC_32M_DIV_EN_MSK (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS) +#define GLB_GPADC_32M_DIV_EN_UMSK (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)) + +/* 0xA8 : DIG32K_WAKEUP_CTRL */ +#define GLB_DIG32K_WAKEUP_CTRL_OFFSET (0xA8) +#define GLB_DIG_32K_DIV GLB_DIG_32K_DIV +#define GLB_DIG_32K_DIV_POS (0U) +#define GLB_DIG_32K_DIV_LEN (11U) +#define GLB_DIG_32K_DIV_MSK (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS) +#define GLB_DIG_32K_DIV_UMSK (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)) +#define GLB_DIG_32K_EN GLB_DIG_32K_EN +#define GLB_DIG_32K_EN_POS (12U) +#define GLB_DIG_32K_EN_LEN (1U) +#define GLB_DIG_32K_EN_MSK (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS) +#define GLB_DIG_32K_EN_UMSK (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)) +#define GLB_DIG_32K_COMP GLB_DIG_32K_COMP +#define GLB_DIG_32K_COMP_POS (13U) +#define GLB_DIG_32K_COMP_LEN (1U) +#define GLB_DIG_32K_COMP_MSK (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS) +#define GLB_DIG_32K_COMP_UMSK (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)) +#define GLB_DIG_512K_DIV GLB_DIG_512K_DIV +#define GLB_DIG_512K_DIV_POS (16U) +#define GLB_DIG_512K_DIV_LEN (7U) +#define GLB_DIG_512K_DIV_MSK (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS) +#define GLB_DIG_512K_DIV_UMSK (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)) +#define GLB_DIG_512K_EN GLB_DIG_512K_EN +#define GLB_DIG_512K_EN_POS (24U) +#define GLB_DIG_512K_EN_LEN (1U) +#define GLB_DIG_512K_EN_MSK (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS) +#define GLB_DIG_512K_EN_UMSK (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)) +#define GLB_DIG_512K_COMP GLB_DIG_512K_COMP +#define GLB_DIG_512K_COMP_POS (25U) +#define GLB_DIG_512K_COMP_LEN (1U) +#define GLB_DIG_512K_COMP_MSK (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS) +#define GLB_DIG_512K_COMP_UMSK (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)) +#define GLB_DIG_CLK_SRC_SEL GLB_DIG_CLK_SRC_SEL +#define GLB_DIG_CLK_SRC_SEL_POS (28U) +#define GLB_DIG_CLK_SRC_SEL_LEN (2U) +#define GLB_DIG_CLK_SRC_SEL_MSK (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS) +#define GLB_DIG_CLK_SRC_SEL_UMSK (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)) +#define GLB_REG_EN_PLATFORM_WAKEUP GLB_REG_EN_PLATFORM_WAKEUP +#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31U) +#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1U) +#define GLB_REG_EN_PLATFORM_WAKEUP_MSK (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS) +#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)) + +/* 0xAC : WIFI_BT_COEX_CTRL */ +#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC) +#define GLB_COEX_BT_CHANNEL GLB_COEX_BT_CHANNEL +#define GLB_COEX_BT_CHANNEL_POS (0U) +#define GLB_COEX_BT_CHANNEL_LEN (7U) +#define GLB_COEX_BT_CHANNEL_MSK (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS) +#define GLB_COEX_BT_CHANNEL_UMSK (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)) +#define GLB_COEX_BT_PTI GLB_COEX_BT_PTI +#define GLB_COEX_BT_PTI_POS (7U) +#define GLB_COEX_BT_PTI_LEN (4U) +#define GLB_COEX_BT_PTI_MSK (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS) +#define GLB_COEX_BT_PTI_UMSK (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)) +#define GLB_COEX_BT_BW GLB_COEX_BT_BW +#define GLB_COEX_BT_BW_POS (11U) +#define GLB_COEX_BT_BW_LEN (1U) +#define GLB_COEX_BT_BW_MSK (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS) +#define GLB_COEX_BT_BW_UMSK (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)) +#define GLB_EN_GPIO_BT_COEX GLB_EN_GPIO_BT_COEX +#define GLB_EN_GPIO_BT_COEX_POS (12U) +#define GLB_EN_GPIO_BT_COEX_LEN (1U) +#define GLB_EN_GPIO_BT_COEX_MSK (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS) +#define GLB_EN_GPIO_BT_COEX_UMSK (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)) + +/* 0xB0 : BZ_COEX_CTRL */ +#define GLB_BZ_COEX_CTRL_OFFSET (0xB0) +#define GLB_COEX_EN GLB_COEX_EN +#define GLB_COEX_EN_POS (0U) +#define GLB_COEX_EN_LEN (1U) +#define GLB_COEX_EN_MSK (((1U << GLB_COEX_EN_LEN) - 1) << GLB_COEX_EN_POS) +#define GLB_COEX_EN_UMSK (~(((1U << GLB_COEX_EN_LEN) - 1) << GLB_COEX_EN_POS)) +#define GLB_WLAN_EN GLB_WLAN_EN +#define GLB_WLAN_EN_POS (1U) +#define GLB_WLAN_EN_LEN (1U) +#define GLB_WLAN_EN_MSK (((1U << GLB_WLAN_EN_LEN) - 1) << GLB_WLAN_EN_POS) +#define GLB_WLAN_EN_UMSK (~(((1U << GLB_WLAN_EN_LEN) - 1) << GLB_WLAN_EN_POS)) +#define GLB_BLE_RX_IGNORE GLB_BLE_RX_IGNORE +#define GLB_BLE_RX_IGNORE_POS (2U) +#define GLB_BLE_RX_IGNORE_LEN (1U) +#define GLB_BLE_RX_IGNORE_MSK (((1U << GLB_BLE_RX_IGNORE_LEN) - 1) << GLB_BLE_RX_IGNORE_POS) +#define GLB_BLE_RX_IGNORE_UMSK (~(((1U << GLB_BLE_RX_IGNORE_LEN) - 1) << GLB_BLE_RX_IGNORE_POS)) +#define GLB_M154_RX_IGNORE GLB_M154_RX_IGNORE +#define GLB_M154_RX_IGNORE_POS (3U) +#define GLB_M154_RX_IGNORE_LEN (1U) +#define GLB_M154_RX_IGNORE_MSK (((1U << GLB_M154_RX_IGNORE_LEN) - 1) << GLB_M154_RX_IGNORE_POS) +#define GLB_M154_RX_IGNORE_UMSK (~(((1U << GLB_M154_RX_IGNORE_LEN) - 1) << GLB_M154_RX_IGNORE_POS)) +#define GLB_BZ_PRI_THR GLB_BZ_PRI_THR +#define GLB_BZ_PRI_THR_POS (4U) +#define GLB_BZ_PRI_THR_LEN (4U) +#define GLB_BZ_PRI_THR_MSK (((1U << GLB_BZ_PRI_THR_LEN) - 1) << GLB_BZ_PRI_THR_POS) +#define GLB_BZ_PRI_THR_UMSK (~(((1U << GLB_BZ_PRI_THR_LEN) - 1) << GLB_BZ_PRI_THR_POS)) +#define GLB_BZ_PRI_EN GLB_BZ_PRI_EN +#define GLB_BZ_PRI_EN_POS (8U) +#define GLB_BZ_PRI_EN_LEN (1U) +#define GLB_BZ_PRI_EN_MSK (((1U << GLB_BZ_PRI_EN_LEN) - 1) << GLB_BZ_PRI_EN_POS) +#define GLB_BZ_PRI_EN_UMSK (~(((1U << GLB_BZ_PRI_EN_LEN) - 1) << GLB_BZ_PRI_EN_POS)) +#define GLB_BZ_PRI_POL GLB_BZ_PRI_POL +#define GLB_BZ_PRI_POL_POS (9U) +#define GLB_BZ_PRI_POL_LEN (1U) +#define GLB_BZ_PRI_POL_MSK (((1U << GLB_BZ_PRI_POL_LEN) - 1) << GLB_BZ_PRI_POL_POS) +#define GLB_BZ_PRI_POL_UMSK (~(((1U << GLB_BZ_PRI_POL_LEN) - 1) << GLB_BZ_PRI_POL_POS)) +#define GLB_BZ_ACTIVE_POL GLB_BZ_ACTIVE_POL +#define GLB_BZ_ACTIVE_POL_POS (10U) +#define GLB_BZ_ACTIVE_POL_LEN (1U) +#define GLB_BZ_ACTIVE_POL_MSK (((1U << GLB_BZ_ACTIVE_POL_LEN) - 1) << GLB_BZ_ACTIVE_POL_POS) +#define GLB_BZ_ACTIVE_POL_UMSK (~(((1U << GLB_BZ_ACTIVE_POL_LEN) - 1) << GLB_BZ_ACTIVE_POL_POS)) +#define GLB_BZ_ABORT_POL GLB_BZ_ABORT_POL +#define GLB_BZ_ABORT_POL_POS (11U) +#define GLB_BZ_ABORT_POL_LEN (1U) +#define GLB_BZ_ABORT_POL_MSK (((1U << GLB_BZ_ABORT_POL_LEN) - 1) << GLB_BZ_ABORT_POL_POS) +#define GLB_BZ_ABORT_POL_UMSK (~(((1U << GLB_BZ_ABORT_POL_LEN) - 1) << GLB_BZ_ABORT_POL_POS)) +#define GLB_COEX_PRI GLB_COEX_PRI +#define GLB_COEX_PRI_POS (12U) +#define GLB_COEX_PRI_LEN (1U) +#define GLB_COEX_PRI_MSK (((1U << GLB_COEX_PRI_LEN) - 1) << GLB_COEX_PRI_POS) +#define GLB_COEX_PRI_UMSK (~(((1U << GLB_COEX_PRI_LEN) - 1) << GLB_COEX_PRI_POS)) +#define GLB_FORCE_M154_WIN GLB_FORCE_M154_WIN +#define GLB_FORCE_M154_WIN_POS (13U) +#define GLB_FORCE_M154_WIN_LEN (1U) +#define GLB_FORCE_M154_WIN_MSK (((1U << GLB_FORCE_M154_WIN_LEN) - 1) << GLB_FORCE_M154_WIN_POS) +#define GLB_FORCE_M154_WIN_UMSK (~(((1U << GLB_FORCE_M154_WIN_LEN) - 1) << GLB_FORCE_M154_WIN_POS)) +#define GLB_FORCE_BLE_WIN GLB_FORCE_BLE_WIN +#define GLB_FORCE_BLE_WIN_POS (14U) +#define GLB_FORCE_BLE_WIN_LEN (1U) +#define GLB_FORCE_BLE_WIN_MSK (((1U << GLB_FORCE_BLE_WIN_LEN) - 1) << GLB_FORCE_BLE_WIN_POS) +#define GLB_FORCE_BLE_WIN_UMSK (~(((1U << GLB_FORCE_BLE_WIN_LEN) - 1) << GLB_FORCE_BLE_WIN_POS)) +#define GLB_COEX_OPTION GLB_COEX_OPTION +#define GLB_COEX_OPTION_POS (15U) +#define GLB_COEX_OPTION_LEN (1U) +#define GLB_COEX_OPTION_MSK (((1U << GLB_COEX_OPTION_LEN) - 1) << GLB_COEX_OPTION_POS) +#define GLB_COEX_OPTION_UMSK (~(((1U << GLB_COEX_OPTION_LEN) - 1) << GLB_COEX_OPTION_POS)) +#define GLB_COEX_FORCE_CH GLB_COEX_FORCE_CH +#define GLB_COEX_FORCE_CH_POS (16U) +#define GLB_COEX_FORCE_CH_LEN (7U) +#define GLB_COEX_FORCE_CH_MSK (((1U << GLB_COEX_FORCE_CH_LEN) - 1) << GLB_COEX_FORCE_CH_POS) +#define GLB_COEX_FORCE_CH_UMSK (~(((1U << GLB_COEX_FORCE_CH_LEN) - 1) << GLB_COEX_FORCE_CH_POS)) +#define GLB_M154_RX_ABORT_DIS GLB_M154_RX_ABORT_DIS +#define GLB_M154_RX_ABORT_DIS_POS (24U) +#define GLB_M154_RX_ABORT_DIS_LEN (1U) +#define GLB_M154_RX_ABORT_DIS_MSK (((1U << GLB_M154_RX_ABORT_DIS_LEN) - 1) << GLB_M154_RX_ABORT_DIS_POS) +#define GLB_M154_RX_ABORT_DIS_UMSK (~(((1U << GLB_M154_RX_ABORT_DIS_LEN) - 1) << GLB_M154_RX_ABORT_DIS_POS)) +#define GLB_M154_TX_ABORT_DIS GLB_M154_TX_ABORT_DIS +#define GLB_M154_TX_ABORT_DIS_POS (25U) +#define GLB_M154_TX_ABORT_DIS_LEN (1U) +#define GLB_M154_TX_ABORT_DIS_MSK (((1U << GLB_M154_TX_ABORT_DIS_LEN) - 1) << GLB_M154_TX_ABORT_DIS_POS) +#define GLB_M154_TX_ABORT_DIS_UMSK (~(((1U << GLB_M154_TX_ABORT_DIS_LEN) - 1) << GLB_M154_TX_ABORT_DIS_POS)) +#define GLB_BLE_RX_ABORT_DIS GLB_BLE_RX_ABORT_DIS +#define GLB_BLE_RX_ABORT_DIS_POS (26U) +#define GLB_BLE_RX_ABORT_DIS_LEN (1U) +#define GLB_BLE_RX_ABORT_DIS_MSK (((1U << GLB_BLE_RX_ABORT_DIS_LEN) - 1) << GLB_BLE_RX_ABORT_DIS_POS) +#define GLB_BLE_RX_ABORT_DIS_UMSK (~(((1U << GLB_BLE_RX_ABORT_DIS_LEN) - 1) << GLB_BLE_RX_ABORT_DIS_POS)) +#define GLB_BLE_TX_ABORT_DIS GLB_BLE_TX_ABORT_DIS +#define GLB_BLE_TX_ABORT_DIS_POS (27U) +#define GLB_BLE_TX_ABORT_DIS_LEN (1U) +#define GLB_BLE_TX_ABORT_DIS_MSK (((1U << GLB_BLE_TX_ABORT_DIS_LEN) - 1) << GLB_BLE_TX_ABORT_DIS_POS) +#define GLB_BLE_TX_ABORT_DIS_UMSK (~(((1U << GLB_BLE_TX_ABORT_DIS_LEN) - 1) << GLB_BLE_TX_ABORT_DIS_POS)) +#define GLB_COEX_ARB GLB_COEX_ARB +#define GLB_COEX_ARB_POS (28U) +#define GLB_COEX_ARB_LEN (4U) +#define GLB_COEX_ARB_MSK (((1U << GLB_COEX_ARB_LEN) - 1) << GLB_COEX_ARB_POS) +#define GLB_COEX_ARB_UMSK (~(((1U << GLB_COEX_ARB_LEN) - 1) << GLB_COEX_ARB_POS)) + +/* 0xC0 : UART_SIG_SEL_0 */ +#define GLB_UART_SIG_SEL_0_OFFSET (0xC0) +#define GLB_UART_SIG_0_SEL GLB_UART_SIG_0_SEL +#define GLB_UART_SIG_0_SEL_POS (0U) +#define GLB_UART_SIG_0_SEL_LEN (4U) +#define GLB_UART_SIG_0_SEL_MSK (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS) +#define GLB_UART_SIG_0_SEL_UMSK (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)) +#define GLB_UART_SIG_1_SEL GLB_UART_SIG_1_SEL +#define GLB_UART_SIG_1_SEL_POS (4U) +#define GLB_UART_SIG_1_SEL_LEN (4U) +#define GLB_UART_SIG_1_SEL_MSK (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS) +#define GLB_UART_SIG_1_SEL_UMSK (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)) +#define GLB_UART_SIG_2_SEL GLB_UART_SIG_2_SEL +#define GLB_UART_SIG_2_SEL_POS (8U) +#define GLB_UART_SIG_2_SEL_LEN (4U) +#define GLB_UART_SIG_2_SEL_MSK (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS) +#define GLB_UART_SIG_2_SEL_UMSK (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)) +#define GLB_UART_SIG_3_SEL GLB_UART_SIG_3_SEL +#define GLB_UART_SIG_3_SEL_POS (12U) +#define GLB_UART_SIG_3_SEL_LEN (4U) +#define GLB_UART_SIG_3_SEL_MSK (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS) +#define GLB_UART_SIG_3_SEL_UMSK (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)) +#define GLB_UART_SIG_4_SEL GLB_UART_SIG_4_SEL +#define GLB_UART_SIG_4_SEL_POS (16U) +#define GLB_UART_SIG_4_SEL_LEN (4U) +#define GLB_UART_SIG_4_SEL_MSK (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS) +#define GLB_UART_SIG_4_SEL_UMSK (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)) +#define GLB_UART_SIG_5_SEL GLB_UART_SIG_5_SEL +#define GLB_UART_SIG_5_SEL_POS (20U) +#define GLB_UART_SIG_5_SEL_LEN (4U) +#define GLB_UART_SIG_5_SEL_MSK (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS) +#define GLB_UART_SIG_5_SEL_UMSK (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)) +#define GLB_UART_SIG_6_SEL GLB_UART_SIG_6_SEL +#define GLB_UART_SIG_6_SEL_POS (24U) +#define GLB_UART_SIG_6_SEL_LEN (4U) +#define GLB_UART_SIG_6_SEL_MSK (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS) +#define GLB_UART_SIG_6_SEL_UMSK (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)) +#define GLB_UART_SIG_7_SEL GLB_UART_SIG_7_SEL +#define GLB_UART_SIG_7_SEL_POS (28U) +#define GLB_UART_SIG_7_SEL_LEN (4U) +#define GLB_UART_SIG_7_SEL_MSK (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS) +#define GLB_UART_SIG_7_SEL_UMSK (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)) + +/* 0xD0 : DBG_SEL_LL */ +#define GLB_DBG_SEL_LL_OFFSET (0xD0) +#define GLB_REG_DBG_LL_CTRL GLB_REG_DBG_LL_CTRL +#define GLB_REG_DBG_LL_CTRL_POS (0U) +#define GLB_REG_DBG_LL_CTRL_LEN (32U) +#define GLB_REG_DBG_LL_CTRL_MSK (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS) +#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)) + +/* 0xD4 : DBG_SEL_LH */ +#define GLB_DBG_SEL_LH_OFFSET (0xD4) +#define GLB_REG_DBG_LH_CTRL GLB_REG_DBG_LH_CTRL +#define GLB_REG_DBG_LH_CTRL_POS (0U) +#define GLB_REG_DBG_LH_CTRL_LEN (32U) +#define GLB_REG_DBG_LH_CTRL_MSK (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS) +#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)) + +/* 0xD8 : DBG_SEL_HL */ +#define GLB_DBG_SEL_HL_OFFSET (0xD8) +#define GLB_REG_DBG_HL_CTRL GLB_REG_DBG_HL_CTRL +#define GLB_REG_DBG_HL_CTRL_POS (0U) +#define GLB_REG_DBG_HL_CTRL_LEN (32U) +#define GLB_REG_DBG_HL_CTRL_MSK (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS) +#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)) + +/* 0xDC : DBG_SEL_HH */ +#define GLB_DBG_SEL_HH_OFFSET (0xDC) +#define GLB_REG_DBG_HH_CTRL GLB_REG_DBG_HH_CTRL +#define GLB_REG_DBG_HH_CTRL_POS (0U) +#define GLB_REG_DBG_HH_CTRL_LEN (32U) +#define GLB_REG_DBG_HH_CTRL_MSK (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS) +#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)) + +/* 0xE0 : debug */ +#define GLB_DEBUG_OFFSET (0xE0) +#define GLB_DEBUG_OE GLB_DEBUG_OE +#define GLB_DEBUG_OE_POS (0U) +#define GLB_DEBUG_OE_LEN (1U) +#define GLB_DEBUG_OE_MSK (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS) +#define GLB_DEBUG_OE_UMSK (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)) +#define GLB_DEBUG_I GLB_DEBUG_I +#define GLB_DEBUG_I_POS (1U) +#define GLB_DEBUG_I_LEN (31U) +#define GLB_DEBUG_I_MSK (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS) +#define GLB_DEBUG_I_UMSK (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)) + +/* 0x100 : GPIO_CFGCTL0 */ +#define GLB_GPIO_CFGCTL0_OFFSET (0x100) +#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE +#define GLB_REG_GPIO_0_IE_POS (0U) +#define GLB_REG_GPIO_0_IE_LEN (1U) +#define GLB_REG_GPIO_0_IE_MSK (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) +#define GLB_REG_GPIO_0_IE_UMSK (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) +#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT +#define GLB_REG_GPIO_0_SMT_POS (1U) +#define GLB_REG_GPIO_0_SMT_LEN (1U) +#define GLB_REG_GPIO_0_SMT_MSK (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) +#define GLB_REG_GPIO_0_SMT_UMSK (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) +#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV +#define GLB_REG_GPIO_0_DRV_POS (2U) +#define GLB_REG_GPIO_0_DRV_LEN (2U) +#define GLB_REG_GPIO_0_DRV_MSK (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) +#define GLB_REG_GPIO_0_DRV_UMSK (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) +#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU +#define GLB_REG_GPIO_0_PU_POS (4U) +#define GLB_REG_GPIO_0_PU_LEN (1U) +#define GLB_REG_GPIO_0_PU_MSK (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) +#define GLB_REG_GPIO_0_PU_UMSK (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) +#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD +#define GLB_REG_GPIO_0_PD_POS (5U) +#define GLB_REG_GPIO_0_PD_LEN (1U) +#define GLB_REG_GPIO_0_PD_MSK (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) +#define GLB_REG_GPIO_0_PD_UMSK (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) +#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL +#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_0_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) +#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)) +#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE +#define GLB_REG_GPIO_1_IE_POS (16U) +#define GLB_REG_GPIO_1_IE_LEN (1U) +#define GLB_REG_GPIO_1_IE_MSK (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) +#define GLB_REG_GPIO_1_IE_UMSK (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) +#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT +#define GLB_REG_GPIO_1_SMT_POS (17U) +#define GLB_REG_GPIO_1_SMT_LEN (1U) +#define GLB_REG_GPIO_1_SMT_MSK (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) +#define GLB_REG_GPIO_1_SMT_UMSK (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) +#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV +#define GLB_REG_GPIO_1_DRV_POS (18U) +#define GLB_REG_GPIO_1_DRV_LEN (2U) +#define GLB_REG_GPIO_1_DRV_MSK (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) +#define GLB_REG_GPIO_1_DRV_UMSK (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) +#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU +#define GLB_REG_GPIO_1_PU_POS (20U) +#define GLB_REG_GPIO_1_PU_LEN (1U) +#define GLB_REG_GPIO_1_PU_MSK (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) +#define GLB_REG_GPIO_1_PU_UMSK (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) +#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD +#define GLB_REG_GPIO_1_PD_POS (21U) +#define GLB_REG_GPIO_1_PD_LEN (1U) +#define GLB_REG_GPIO_1_PD_MSK (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) +#define GLB_REG_GPIO_1_PD_UMSK (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) +#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL +#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_1_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) +#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)) + +/* 0x104 : GPIO_CFGCTL1 */ +#define GLB_GPIO_CFGCTL1_OFFSET (0x104) +#define GLB_REG_GPIO_2_IE GLB_REG_GPIO_2_IE +#define GLB_REG_GPIO_2_IE_POS (0U) +#define GLB_REG_GPIO_2_IE_LEN (1U) +#define GLB_REG_GPIO_2_IE_MSK (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS) +#define GLB_REG_GPIO_2_IE_UMSK (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)) +#define GLB_REG_GPIO_2_SMT GLB_REG_GPIO_2_SMT +#define GLB_REG_GPIO_2_SMT_POS (1U) +#define GLB_REG_GPIO_2_SMT_LEN (1U) +#define GLB_REG_GPIO_2_SMT_MSK (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS) +#define GLB_REG_GPIO_2_SMT_UMSK (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)) +#define GLB_REG_GPIO_2_DRV GLB_REG_GPIO_2_DRV +#define GLB_REG_GPIO_2_DRV_POS (2U) +#define GLB_REG_GPIO_2_DRV_LEN (2U) +#define GLB_REG_GPIO_2_DRV_MSK (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS) +#define GLB_REG_GPIO_2_DRV_UMSK (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)) +#define GLB_REG_GPIO_2_PU GLB_REG_GPIO_2_PU +#define GLB_REG_GPIO_2_PU_POS (4U) +#define GLB_REG_GPIO_2_PU_LEN (1U) +#define GLB_REG_GPIO_2_PU_MSK (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS) +#define GLB_REG_GPIO_2_PU_UMSK (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)) +#define GLB_REG_GPIO_2_PD GLB_REG_GPIO_2_PD +#define GLB_REG_GPIO_2_PD_POS (5U) +#define GLB_REG_GPIO_2_PD_LEN (1U) +#define GLB_REG_GPIO_2_PD_MSK (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS) +#define GLB_REG_GPIO_2_PD_UMSK (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)) +#define GLB_REG_GPIO_2_FUNC_SEL GLB_REG_GPIO_2_FUNC_SEL +#define GLB_REG_GPIO_2_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_2_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_2_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS) +#define GLB_REG_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)) +#define GLB_REG_GPIO_3_IE GLB_REG_GPIO_3_IE +#define GLB_REG_GPIO_3_IE_POS (16U) +#define GLB_REG_GPIO_3_IE_LEN (1U) +#define GLB_REG_GPIO_3_IE_MSK (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS) +#define GLB_REG_GPIO_3_IE_UMSK (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)) +#define GLB_REG_GPIO_3_SMT GLB_REG_GPIO_3_SMT +#define GLB_REG_GPIO_3_SMT_POS (17U) +#define GLB_REG_GPIO_3_SMT_LEN (1U) +#define GLB_REG_GPIO_3_SMT_MSK (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS) +#define GLB_REG_GPIO_3_SMT_UMSK (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)) +#define GLB_REG_GPIO_3_DRV GLB_REG_GPIO_3_DRV +#define GLB_REG_GPIO_3_DRV_POS (18U) +#define GLB_REG_GPIO_3_DRV_LEN (2U) +#define GLB_REG_GPIO_3_DRV_MSK (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS) +#define GLB_REG_GPIO_3_DRV_UMSK (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)) +#define GLB_REG_GPIO_3_PU GLB_REG_GPIO_3_PU +#define GLB_REG_GPIO_3_PU_POS (20U) +#define GLB_REG_GPIO_3_PU_LEN (1U) +#define GLB_REG_GPIO_3_PU_MSK (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS) +#define GLB_REG_GPIO_3_PU_UMSK (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)) +#define GLB_REG_GPIO_3_PD GLB_REG_GPIO_3_PD +#define GLB_REG_GPIO_3_PD_POS (21U) +#define GLB_REG_GPIO_3_PD_LEN (1U) +#define GLB_REG_GPIO_3_PD_MSK (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS) +#define GLB_REG_GPIO_3_PD_UMSK (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)) +#define GLB_REG_GPIO_3_FUNC_SEL GLB_REG_GPIO_3_FUNC_SEL +#define GLB_REG_GPIO_3_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_3_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_3_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS) +#define GLB_REG_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)) + +/* 0x108 : GPIO_CFGCTL2 */ +#define GLB_GPIO_CFGCTL2_OFFSET (0x108) +#define GLB_REG_GPIO_4_IE GLB_REG_GPIO_4_IE +#define GLB_REG_GPIO_4_IE_POS (0U) +#define GLB_REG_GPIO_4_IE_LEN (1U) +#define GLB_REG_GPIO_4_IE_MSK (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS) +#define GLB_REG_GPIO_4_IE_UMSK (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)) +#define GLB_REG_GPIO_4_SMT GLB_REG_GPIO_4_SMT +#define GLB_REG_GPIO_4_SMT_POS (1U) +#define GLB_REG_GPIO_4_SMT_LEN (1U) +#define GLB_REG_GPIO_4_SMT_MSK (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS) +#define GLB_REG_GPIO_4_SMT_UMSK (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)) +#define GLB_REG_GPIO_4_DRV GLB_REG_GPIO_4_DRV +#define GLB_REG_GPIO_4_DRV_POS (2U) +#define GLB_REG_GPIO_4_DRV_LEN (2U) +#define GLB_REG_GPIO_4_DRV_MSK (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS) +#define GLB_REG_GPIO_4_DRV_UMSK (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)) +#define GLB_REG_GPIO_4_PU GLB_REG_GPIO_4_PU +#define GLB_REG_GPIO_4_PU_POS (4U) +#define GLB_REG_GPIO_4_PU_LEN (1U) +#define GLB_REG_GPIO_4_PU_MSK (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS) +#define GLB_REG_GPIO_4_PU_UMSK (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)) +#define GLB_REG_GPIO_4_PD GLB_REG_GPIO_4_PD +#define GLB_REG_GPIO_4_PD_POS (5U) +#define GLB_REG_GPIO_4_PD_LEN (1U) +#define GLB_REG_GPIO_4_PD_MSK (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS) +#define GLB_REG_GPIO_4_PD_UMSK (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)) +#define GLB_REG_GPIO_4_FUNC_SEL GLB_REG_GPIO_4_FUNC_SEL +#define GLB_REG_GPIO_4_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_4_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_4_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS) +#define GLB_REG_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)) +#define GLB_REG_GPIO_5_IE GLB_REG_GPIO_5_IE +#define GLB_REG_GPIO_5_IE_POS (16U) +#define GLB_REG_GPIO_5_IE_LEN (1U) +#define GLB_REG_GPIO_5_IE_MSK (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS) +#define GLB_REG_GPIO_5_IE_UMSK (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)) +#define GLB_REG_GPIO_5_SMT GLB_REG_GPIO_5_SMT +#define GLB_REG_GPIO_5_SMT_POS (17U) +#define GLB_REG_GPIO_5_SMT_LEN (1U) +#define GLB_REG_GPIO_5_SMT_MSK (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS) +#define GLB_REG_GPIO_5_SMT_UMSK (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)) +#define GLB_REG_GPIO_5_DRV GLB_REG_GPIO_5_DRV +#define GLB_REG_GPIO_5_DRV_POS (18U) +#define GLB_REG_GPIO_5_DRV_LEN (2U) +#define GLB_REG_GPIO_5_DRV_MSK (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS) +#define GLB_REG_GPIO_5_DRV_UMSK (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)) +#define GLB_REG_GPIO_5_PU GLB_REG_GPIO_5_PU +#define GLB_REG_GPIO_5_PU_POS (20U) +#define GLB_REG_GPIO_5_PU_LEN (1U) +#define GLB_REG_GPIO_5_PU_MSK (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS) +#define GLB_REG_GPIO_5_PU_UMSK (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)) +#define GLB_REG_GPIO_5_PD GLB_REG_GPIO_5_PD +#define GLB_REG_GPIO_5_PD_POS (21U) +#define GLB_REG_GPIO_5_PD_LEN (1U) +#define GLB_REG_GPIO_5_PD_MSK (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS) +#define GLB_REG_GPIO_5_PD_UMSK (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)) +#define GLB_REG_GPIO_5_FUNC_SEL GLB_REG_GPIO_5_FUNC_SEL +#define GLB_REG_GPIO_5_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_5_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_5_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS) +#define GLB_REG_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)) + +/* 0x10C : GPIO_CFGCTL3 */ +#define GLB_GPIO_CFGCTL3_OFFSET (0x10C) +#define GLB_REG_GPIO_6_IE GLB_REG_GPIO_6_IE +#define GLB_REG_GPIO_6_IE_POS (0U) +#define GLB_REG_GPIO_6_IE_LEN (1U) +#define GLB_REG_GPIO_6_IE_MSK (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS) +#define GLB_REG_GPIO_6_IE_UMSK (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)) +#define GLB_REG_GPIO_6_SMT GLB_REG_GPIO_6_SMT +#define GLB_REG_GPIO_6_SMT_POS (1U) +#define GLB_REG_GPIO_6_SMT_LEN (1U) +#define GLB_REG_GPIO_6_SMT_MSK (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS) +#define GLB_REG_GPIO_6_SMT_UMSK (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)) +#define GLB_REG_GPIO_6_DRV GLB_REG_GPIO_6_DRV +#define GLB_REG_GPIO_6_DRV_POS (2U) +#define GLB_REG_GPIO_6_DRV_LEN (2U) +#define GLB_REG_GPIO_6_DRV_MSK (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS) +#define GLB_REG_GPIO_6_DRV_UMSK (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)) +#define GLB_REG_GPIO_6_PU GLB_REG_GPIO_6_PU +#define GLB_REG_GPIO_6_PU_POS (4U) +#define GLB_REG_GPIO_6_PU_LEN (1U) +#define GLB_REG_GPIO_6_PU_MSK (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS) +#define GLB_REG_GPIO_6_PU_UMSK (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)) +#define GLB_REG_GPIO_6_PD GLB_REG_GPIO_6_PD +#define GLB_REG_GPIO_6_PD_POS (5U) +#define GLB_REG_GPIO_6_PD_LEN (1U) +#define GLB_REG_GPIO_6_PD_MSK (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS) +#define GLB_REG_GPIO_6_PD_UMSK (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)) +#define GLB_REG_GPIO_6_FUNC_SEL GLB_REG_GPIO_6_FUNC_SEL +#define GLB_REG_GPIO_6_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_6_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_6_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS) +#define GLB_REG_GPIO_6_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)) +#define GLB_REG_GPIO_7_IE GLB_REG_GPIO_7_IE +#define GLB_REG_GPIO_7_IE_POS (16U) +#define GLB_REG_GPIO_7_IE_LEN (1U) +#define GLB_REG_GPIO_7_IE_MSK (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS) +#define GLB_REG_GPIO_7_IE_UMSK (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)) +#define GLB_REG_GPIO_7_SMT GLB_REG_GPIO_7_SMT +#define GLB_REG_GPIO_7_SMT_POS (17U) +#define GLB_REG_GPIO_7_SMT_LEN (1U) +#define GLB_REG_GPIO_7_SMT_MSK (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS) +#define GLB_REG_GPIO_7_SMT_UMSK (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)) +#define GLB_REG_GPIO_7_DRV GLB_REG_GPIO_7_DRV +#define GLB_REG_GPIO_7_DRV_POS (18U) +#define GLB_REG_GPIO_7_DRV_LEN (2U) +#define GLB_REG_GPIO_7_DRV_MSK (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS) +#define GLB_REG_GPIO_7_DRV_UMSK (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)) +#define GLB_REG_GPIO_7_PU GLB_REG_GPIO_7_PU +#define GLB_REG_GPIO_7_PU_POS (20U) +#define GLB_REG_GPIO_7_PU_LEN (1U) +#define GLB_REG_GPIO_7_PU_MSK (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS) +#define GLB_REG_GPIO_7_PU_UMSK (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)) +#define GLB_REG_GPIO_7_PD GLB_REG_GPIO_7_PD +#define GLB_REG_GPIO_7_PD_POS (21U) +#define GLB_REG_GPIO_7_PD_LEN (1U) +#define GLB_REG_GPIO_7_PD_MSK (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS) +#define GLB_REG_GPIO_7_PD_UMSK (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)) +#define GLB_REG_GPIO_7_FUNC_SEL GLB_REG_GPIO_7_FUNC_SEL +#define GLB_REG_GPIO_7_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_7_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_7_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS) +#define GLB_REG_GPIO_7_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)) + +/* 0x110 : GPIO_CFGCTL4 */ +#define GLB_GPIO_CFGCTL4_OFFSET (0x110) +#define GLB_REG_GPIO_8_IE GLB_REG_GPIO_8_IE +#define GLB_REG_GPIO_8_IE_POS (0U) +#define GLB_REG_GPIO_8_IE_LEN (1U) +#define GLB_REG_GPIO_8_IE_MSK (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS) +#define GLB_REG_GPIO_8_IE_UMSK (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)) +#define GLB_REG_GPIO_8_SMT GLB_REG_GPIO_8_SMT +#define GLB_REG_GPIO_8_SMT_POS (1U) +#define GLB_REG_GPIO_8_SMT_LEN (1U) +#define GLB_REG_GPIO_8_SMT_MSK (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS) +#define GLB_REG_GPIO_8_SMT_UMSK (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)) +#define GLB_REG_GPIO_8_DRV GLB_REG_GPIO_8_DRV +#define GLB_REG_GPIO_8_DRV_POS (2U) +#define GLB_REG_GPIO_8_DRV_LEN (2U) +#define GLB_REG_GPIO_8_DRV_MSK (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS) +#define GLB_REG_GPIO_8_DRV_UMSK (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)) +#define GLB_REG_GPIO_8_PU GLB_REG_GPIO_8_PU +#define GLB_REG_GPIO_8_PU_POS (4U) +#define GLB_REG_GPIO_8_PU_LEN (1U) +#define GLB_REG_GPIO_8_PU_MSK (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS) +#define GLB_REG_GPIO_8_PU_UMSK (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)) +#define GLB_REG_GPIO_8_PD GLB_REG_GPIO_8_PD +#define GLB_REG_GPIO_8_PD_POS (5U) +#define GLB_REG_GPIO_8_PD_LEN (1U) +#define GLB_REG_GPIO_8_PD_MSK (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS) +#define GLB_REG_GPIO_8_PD_UMSK (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)) +#define GLB_REG_GPIO_8_FUNC_SEL GLB_REG_GPIO_8_FUNC_SEL +#define GLB_REG_GPIO_8_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_8_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_8_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS) +#define GLB_REG_GPIO_8_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)) +#define GLB_REG_GPIO_9_IE GLB_REG_GPIO_9_IE +#define GLB_REG_GPIO_9_IE_POS (16U) +#define GLB_REG_GPIO_9_IE_LEN (1U) +#define GLB_REG_GPIO_9_IE_MSK (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS) +#define GLB_REG_GPIO_9_IE_UMSK (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)) +#define GLB_REG_GPIO_9_SMT GLB_REG_GPIO_9_SMT +#define GLB_REG_GPIO_9_SMT_POS (17U) +#define GLB_REG_GPIO_9_SMT_LEN (1U) +#define GLB_REG_GPIO_9_SMT_MSK (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS) +#define GLB_REG_GPIO_9_SMT_UMSK (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)) +#define GLB_REG_GPIO_9_DRV GLB_REG_GPIO_9_DRV +#define GLB_REG_GPIO_9_DRV_POS (18U) +#define GLB_REG_GPIO_9_DRV_LEN (2U) +#define GLB_REG_GPIO_9_DRV_MSK (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS) +#define GLB_REG_GPIO_9_DRV_UMSK (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)) +#define GLB_REG_GPIO_9_PU GLB_REG_GPIO_9_PU +#define GLB_REG_GPIO_9_PU_POS (20U) +#define GLB_REG_GPIO_9_PU_LEN (1U) +#define GLB_REG_GPIO_9_PU_MSK (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS) +#define GLB_REG_GPIO_9_PU_UMSK (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)) +#define GLB_REG_GPIO_9_PD GLB_REG_GPIO_9_PD +#define GLB_REG_GPIO_9_PD_POS (21U) +#define GLB_REG_GPIO_9_PD_LEN (1U) +#define GLB_REG_GPIO_9_PD_MSK (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS) +#define GLB_REG_GPIO_9_PD_UMSK (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)) +#define GLB_REG_GPIO_9_FUNC_SEL GLB_REG_GPIO_9_FUNC_SEL +#define GLB_REG_GPIO_9_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_9_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_9_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS) +#define GLB_REG_GPIO_9_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)) + +/* 0x114 : GPIO_CFGCTL5 */ +#define GLB_GPIO_CFGCTL5_OFFSET (0x114) +#define GLB_REG_GPIO_10_IE GLB_REG_GPIO_10_IE +#define GLB_REG_GPIO_10_IE_POS (0U) +#define GLB_REG_GPIO_10_IE_LEN (1U) +#define GLB_REG_GPIO_10_IE_MSK (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS) +#define GLB_REG_GPIO_10_IE_UMSK (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)) +#define GLB_REG_GPIO_10_SMT GLB_REG_GPIO_10_SMT +#define GLB_REG_GPIO_10_SMT_POS (1U) +#define GLB_REG_GPIO_10_SMT_LEN (1U) +#define GLB_REG_GPIO_10_SMT_MSK (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS) +#define GLB_REG_GPIO_10_SMT_UMSK (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)) +#define GLB_REG_GPIO_10_DRV GLB_REG_GPIO_10_DRV +#define GLB_REG_GPIO_10_DRV_POS (2U) +#define GLB_REG_GPIO_10_DRV_LEN (2U) +#define GLB_REG_GPIO_10_DRV_MSK (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS) +#define GLB_REG_GPIO_10_DRV_UMSK (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)) +#define GLB_REG_GPIO_10_PU GLB_REG_GPIO_10_PU +#define GLB_REG_GPIO_10_PU_POS (4U) +#define GLB_REG_GPIO_10_PU_LEN (1U) +#define GLB_REG_GPIO_10_PU_MSK (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS) +#define GLB_REG_GPIO_10_PU_UMSK (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)) +#define GLB_REG_GPIO_10_PD GLB_REG_GPIO_10_PD +#define GLB_REG_GPIO_10_PD_POS (5U) +#define GLB_REG_GPIO_10_PD_LEN (1U) +#define GLB_REG_GPIO_10_PD_MSK (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS) +#define GLB_REG_GPIO_10_PD_UMSK (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)) +#define GLB_REG_GPIO_10_FUNC_SEL GLB_REG_GPIO_10_FUNC_SEL +#define GLB_REG_GPIO_10_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_10_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_10_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS) +#define GLB_REG_GPIO_10_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)) +#define GLB_REG_GPIO_11_IE GLB_REG_GPIO_11_IE +#define GLB_REG_GPIO_11_IE_POS (16U) +#define GLB_REG_GPIO_11_IE_LEN (1U) +#define GLB_REG_GPIO_11_IE_MSK (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS) +#define GLB_REG_GPIO_11_IE_UMSK (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)) +#define GLB_REG_GPIO_11_SMT GLB_REG_GPIO_11_SMT +#define GLB_REG_GPIO_11_SMT_POS (17U) +#define GLB_REG_GPIO_11_SMT_LEN (1U) +#define GLB_REG_GPIO_11_SMT_MSK (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS) +#define GLB_REG_GPIO_11_SMT_UMSK (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)) +#define GLB_REG_GPIO_11_DRV GLB_REG_GPIO_11_DRV +#define GLB_REG_GPIO_11_DRV_POS (18U) +#define GLB_REG_GPIO_11_DRV_LEN (2U) +#define GLB_REG_GPIO_11_DRV_MSK (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS) +#define GLB_REG_GPIO_11_DRV_UMSK (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)) +#define GLB_REG_GPIO_11_PU GLB_REG_GPIO_11_PU +#define GLB_REG_GPIO_11_PU_POS (20U) +#define GLB_REG_GPIO_11_PU_LEN (1U) +#define GLB_REG_GPIO_11_PU_MSK (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS) +#define GLB_REG_GPIO_11_PU_UMSK (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)) +#define GLB_REG_GPIO_11_PD GLB_REG_GPIO_11_PD +#define GLB_REG_GPIO_11_PD_POS (21U) +#define GLB_REG_GPIO_11_PD_LEN (1U) +#define GLB_REG_GPIO_11_PD_MSK (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS) +#define GLB_REG_GPIO_11_PD_UMSK (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)) +#define GLB_REG_GPIO_11_FUNC_SEL GLB_REG_GPIO_11_FUNC_SEL +#define GLB_REG_GPIO_11_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_11_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_11_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS) +#define GLB_REG_GPIO_11_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)) + +/* 0x118 : GPIO_CFGCTL6 */ +#define GLB_GPIO_CFGCTL6_OFFSET (0x118) +#define GLB_REG_GPIO_12_IE GLB_REG_GPIO_12_IE +#define GLB_REG_GPIO_12_IE_POS (0U) +#define GLB_REG_GPIO_12_IE_LEN (1U) +#define GLB_REG_GPIO_12_IE_MSK (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS) +#define GLB_REG_GPIO_12_IE_UMSK (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)) +#define GLB_REG_GPIO_12_SMT GLB_REG_GPIO_12_SMT +#define GLB_REG_GPIO_12_SMT_POS (1U) +#define GLB_REG_GPIO_12_SMT_LEN (1U) +#define GLB_REG_GPIO_12_SMT_MSK (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS) +#define GLB_REG_GPIO_12_SMT_UMSK (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)) +#define GLB_REG_GPIO_12_DRV GLB_REG_GPIO_12_DRV +#define GLB_REG_GPIO_12_DRV_POS (2U) +#define GLB_REG_GPIO_12_DRV_LEN (2U) +#define GLB_REG_GPIO_12_DRV_MSK (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS) +#define GLB_REG_GPIO_12_DRV_UMSK (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)) +#define GLB_REG_GPIO_12_PU GLB_REG_GPIO_12_PU +#define GLB_REG_GPIO_12_PU_POS (4U) +#define GLB_REG_GPIO_12_PU_LEN (1U) +#define GLB_REG_GPIO_12_PU_MSK (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS) +#define GLB_REG_GPIO_12_PU_UMSK (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)) +#define GLB_REG_GPIO_12_PD GLB_REG_GPIO_12_PD +#define GLB_REG_GPIO_12_PD_POS (5U) +#define GLB_REG_GPIO_12_PD_LEN (1U) +#define GLB_REG_GPIO_12_PD_MSK (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS) +#define GLB_REG_GPIO_12_PD_UMSK (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)) +#define GLB_REG_GPIO_12_FUNC_SEL GLB_REG_GPIO_12_FUNC_SEL +#define GLB_REG_GPIO_12_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_12_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_12_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS) +#define GLB_REG_GPIO_12_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)) +#define GLB_REG_GPIO_13_IE GLB_REG_GPIO_13_IE +#define GLB_REG_GPIO_13_IE_POS (16U) +#define GLB_REG_GPIO_13_IE_LEN (1U) +#define GLB_REG_GPIO_13_IE_MSK (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS) +#define GLB_REG_GPIO_13_IE_UMSK (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)) +#define GLB_REG_GPIO_13_SMT GLB_REG_GPIO_13_SMT +#define GLB_REG_GPIO_13_SMT_POS (17U) +#define GLB_REG_GPIO_13_SMT_LEN (1U) +#define GLB_REG_GPIO_13_SMT_MSK (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS) +#define GLB_REG_GPIO_13_SMT_UMSK (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)) +#define GLB_REG_GPIO_13_DRV GLB_REG_GPIO_13_DRV +#define GLB_REG_GPIO_13_DRV_POS (18U) +#define GLB_REG_GPIO_13_DRV_LEN (2U) +#define GLB_REG_GPIO_13_DRV_MSK (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS) +#define GLB_REG_GPIO_13_DRV_UMSK (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)) +#define GLB_REG_GPIO_13_PU GLB_REG_GPIO_13_PU +#define GLB_REG_GPIO_13_PU_POS (20U) +#define GLB_REG_GPIO_13_PU_LEN (1U) +#define GLB_REG_GPIO_13_PU_MSK (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS) +#define GLB_REG_GPIO_13_PU_UMSK (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)) +#define GLB_REG_GPIO_13_PD GLB_REG_GPIO_13_PD +#define GLB_REG_GPIO_13_PD_POS (21U) +#define GLB_REG_GPIO_13_PD_LEN (1U) +#define GLB_REG_GPIO_13_PD_MSK (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS) +#define GLB_REG_GPIO_13_PD_UMSK (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)) +#define GLB_REG_GPIO_13_FUNC_SEL GLB_REG_GPIO_13_FUNC_SEL +#define GLB_REG_GPIO_13_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_13_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_13_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS) +#define GLB_REG_GPIO_13_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)) + +/* 0x11C : GPIO_CFGCTL7 */ +#define GLB_GPIO_CFGCTL7_OFFSET (0x11C) +#define GLB_REG_GPIO_14_IE GLB_REG_GPIO_14_IE +#define GLB_REG_GPIO_14_IE_POS (0U) +#define GLB_REG_GPIO_14_IE_LEN (1U) +#define GLB_REG_GPIO_14_IE_MSK (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS) +#define GLB_REG_GPIO_14_IE_UMSK (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)) +#define GLB_REG_GPIO_14_SMT GLB_REG_GPIO_14_SMT +#define GLB_REG_GPIO_14_SMT_POS (1U) +#define GLB_REG_GPIO_14_SMT_LEN (1U) +#define GLB_REG_GPIO_14_SMT_MSK (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS) +#define GLB_REG_GPIO_14_SMT_UMSK (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)) +#define GLB_REG_GPIO_14_DRV GLB_REG_GPIO_14_DRV +#define GLB_REG_GPIO_14_DRV_POS (2U) +#define GLB_REG_GPIO_14_DRV_LEN (2U) +#define GLB_REG_GPIO_14_DRV_MSK (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS) +#define GLB_REG_GPIO_14_DRV_UMSK (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)) +#define GLB_REG_GPIO_14_PU GLB_REG_GPIO_14_PU +#define GLB_REG_GPIO_14_PU_POS (4U) +#define GLB_REG_GPIO_14_PU_LEN (1U) +#define GLB_REG_GPIO_14_PU_MSK (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS) +#define GLB_REG_GPIO_14_PU_UMSK (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)) +#define GLB_REG_GPIO_14_PD GLB_REG_GPIO_14_PD +#define GLB_REG_GPIO_14_PD_POS (5U) +#define GLB_REG_GPIO_14_PD_LEN (1U) +#define GLB_REG_GPIO_14_PD_MSK (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS) +#define GLB_REG_GPIO_14_PD_UMSK (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)) +#define GLB_REG_GPIO_14_FUNC_SEL GLB_REG_GPIO_14_FUNC_SEL +#define GLB_REG_GPIO_14_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_14_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_14_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS) +#define GLB_REG_GPIO_14_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)) +#define GLB_REG_GPIO_15_IE GLB_REG_GPIO_15_IE +#define GLB_REG_GPIO_15_IE_POS (16U) +#define GLB_REG_GPIO_15_IE_LEN (1U) +#define GLB_REG_GPIO_15_IE_MSK (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS) +#define GLB_REG_GPIO_15_IE_UMSK (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)) +#define GLB_REG_GPIO_15_SMT GLB_REG_GPIO_15_SMT +#define GLB_REG_GPIO_15_SMT_POS (17U) +#define GLB_REG_GPIO_15_SMT_LEN (1U) +#define GLB_REG_GPIO_15_SMT_MSK (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS) +#define GLB_REG_GPIO_15_SMT_UMSK (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)) +#define GLB_REG_GPIO_15_DRV GLB_REG_GPIO_15_DRV +#define GLB_REG_GPIO_15_DRV_POS (18U) +#define GLB_REG_GPIO_15_DRV_LEN (2U) +#define GLB_REG_GPIO_15_DRV_MSK (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS) +#define GLB_REG_GPIO_15_DRV_UMSK (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)) +#define GLB_REG_GPIO_15_PU GLB_REG_GPIO_15_PU +#define GLB_REG_GPIO_15_PU_POS (20U) +#define GLB_REG_GPIO_15_PU_LEN (1U) +#define GLB_REG_GPIO_15_PU_MSK (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS) +#define GLB_REG_GPIO_15_PU_UMSK (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)) +#define GLB_REG_GPIO_15_PD GLB_REG_GPIO_15_PD +#define GLB_REG_GPIO_15_PD_POS (21U) +#define GLB_REG_GPIO_15_PD_LEN (1U) +#define GLB_REG_GPIO_15_PD_MSK (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS) +#define GLB_REG_GPIO_15_PD_UMSK (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)) +#define GLB_REG_GPIO_15_FUNC_SEL GLB_REG_GPIO_15_FUNC_SEL +#define GLB_REG_GPIO_15_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_15_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_15_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS) +#define GLB_REG_GPIO_15_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)) + +/* 0x120 : GPIO_CFGCTL8 */ +#define GLB_GPIO_CFGCTL8_OFFSET (0x120) +#define GLB_REG_GPIO_16_IE GLB_REG_GPIO_16_IE +#define GLB_REG_GPIO_16_IE_POS (0U) +#define GLB_REG_GPIO_16_IE_LEN (1U) +#define GLB_REG_GPIO_16_IE_MSK (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS) +#define GLB_REG_GPIO_16_IE_UMSK (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)) +#define GLB_REG_GPIO_16_SMT GLB_REG_GPIO_16_SMT +#define GLB_REG_GPIO_16_SMT_POS (1U) +#define GLB_REG_GPIO_16_SMT_LEN (1U) +#define GLB_REG_GPIO_16_SMT_MSK (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS) +#define GLB_REG_GPIO_16_SMT_UMSK (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)) +#define GLB_REG_GPIO_16_DRV GLB_REG_GPIO_16_DRV +#define GLB_REG_GPIO_16_DRV_POS (2U) +#define GLB_REG_GPIO_16_DRV_LEN (2U) +#define GLB_REG_GPIO_16_DRV_MSK (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS) +#define GLB_REG_GPIO_16_DRV_UMSK (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)) +#define GLB_REG_GPIO_16_PU GLB_REG_GPIO_16_PU +#define GLB_REG_GPIO_16_PU_POS (4U) +#define GLB_REG_GPIO_16_PU_LEN (1U) +#define GLB_REG_GPIO_16_PU_MSK (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS) +#define GLB_REG_GPIO_16_PU_UMSK (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)) +#define GLB_REG_GPIO_16_PD GLB_REG_GPIO_16_PD +#define GLB_REG_GPIO_16_PD_POS (5U) +#define GLB_REG_GPIO_16_PD_LEN (1U) +#define GLB_REG_GPIO_16_PD_MSK (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS) +#define GLB_REG_GPIO_16_PD_UMSK (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)) +#define GLB_REG_GPIO_16_FUNC_SEL GLB_REG_GPIO_16_FUNC_SEL +#define GLB_REG_GPIO_16_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_16_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_16_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS) +#define GLB_REG_GPIO_16_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)) +#define GLB_REG_GPIO_17_IE GLB_REG_GPIO_17_IE +#define GLB_REG_GPIO_17_IE_POS (16U) +#define GLB_REG_GPIO_17_IE_LEN (1U) +#define GLB_REG_GPIO_17_IE_MSK (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS) +#define GLB_REG_GPIO_17_IE_UMSK (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)) +#define GLB_REG_GPIO_17_SMT GLB_REG_GPIO_17_SMT +#define GLB_REG_GPIO_17_SMT_POS (17U) +#define GLB_REG_GPIO_17_SMT_LEN (1U) +#define GLB_REG_GPIO_17_SMT_MSK (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS) +#define GLB_REG_GPIO_17_SMT_UMSK (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)) +#define GLB_REG_GPIO_17_DRV GLB_REG_GPIO_17_DRV +#define GLB_REG_GPIO_17_DRV_POS (18U) +#define GLB_REG_GPIO_17_DRV_LEN (2U) +#define GLB_REG_GPIO_17_DRV_MSK (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS) +#define GLB_REG_GPIO_17_DRV_UMSK (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)) +#define GLB_REG_GPIO_17_PU GLB_REG_GPIO_17_PU +#define GLB_REG_GPIO_17_PU_POS (20U) +#define GLB_REG_GPIO_17_PU_LEN (1U) +#define GLB_REG_GPIO_17_PU_MSK (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS) +#define GLB_REG_GPIO_17_PU_UMSK (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)) +#define GLB_REG_GPIO_17_PD GLB_REG_GPIO_17_PD +#define GLB_REG_GPIO_17_PD_POS (21U) +#define GLB_REG_GPIO_17_PD_LEN (1U) +#define GLB_REG_GPIO_17_PD_MSK (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS) +#define GLB_REG_GPIO_17_PD_UMSK (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)) +#define GLB_REG_GPIO_17_FUNC_SEL GLB_REG_GPIO_17_FUNC_SEL +#define GLB_REG_GPIO_17_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_17_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_17_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS) +#define GLB_REG_GPIO_17_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)) + +/* 0x124 : GPIO_CFGCTL9 */ +#define GLB_GPIO_CFGCTL9_OFFSET (0x124) +#define GLB_REG_GPIO_18_IE GLB_REG_GPIO_18_IE +#define GLB_REG_GPIO_18_IE_POS (0U) +#define GLB_REG_GPIO_18_IE_LEN (1U) +#define GLB_REG_GPIO_18_IE_MSK (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS) +#define GLB_REG_GPIO_18_IE_UMSK (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)) +#define GLB_REG_GPIO_18_SMT GLB_REG_GPIO_18_SMT +#define GLB_REG_GPIO_18_SMT_POS (1U) +#define GLB_REG_GPIO_18_SMT_LEN (1U) +#define GLB_REG_GPIO_18_SMT_MSK (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS) +#define GLB_REG_GPIO_18_SMT_UMSK (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)) +#define GLB_REG_GPIO_18_DRV GLB_REG_GPIO_18_DRV +#define GLB_REG_GPIO_18_DRV_POS (2U) +#define GLB_REG_GPIO_18_DRV_LEN (2U) +#define GLB_REG_GPIO_18_DRV_MSK (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS) +#define GLB_REG_GPIO_18_DRV_UMSK (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)) +#define GLB_REG_GPIO_18_PU GLB_REG_GPIO_18_PU +#define GLB_REG_GPIO_18_PU_POS (4U) +#define GLB_REG_GPIO_18_PU_LEN (1U) +#define GLB_REG_GPIO_18_PU_MSK (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS) +#define GLB_REG_GPIO_18_PU_UMSK (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)) +#define GLB_REG_GPIO_18_PD GLB_REG_GPIO_18_PD +#define GLB_REG_GPIO_18_PD_POS (5U) +#define GLB_REG_GPIO_18_PD_LEN (1U) +#define GLB_REG_GPIO_18_PD_MSK (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS) +#define GLB_REG_GPIO_18_PD_UMSK (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)) +#define GLB_REG_GPIO_18_FUNC_SEL GLB_REG_GPIO_18_FUNC_SEL +#define GLB_REG_GPIO_18_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_18_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_18_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS) +#define GLB_REG_GPIO_18_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)) +#define GLB_REG_GPIO_19_IE GLB_REG_GPIO_19_IE +#define GLB_REG_GPIO_19_IE_POS (16U) +#define GLB_REG_GPIO_19_IE_LEN (1U) +#define GLB_REG_GPIO_19_IE_MSK (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS) +#define GLB_REG_GPIO_19_IE_UMSK (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)) +#define GLB_REG_GPIO_19_SMT GLB_REG_GPIO_19_SMT +#define GLB_REG_GPIO_19_SMT_POS (17U) +#define GLB_REG_GPIO_19_SMT_LEN (1U) +#define GLB_REG_GPIO_19_SMT_MSK (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS) +#define GLB_REG_GPIO_19_SMT_UMSK (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)) +#define GLB_REG_GPIO_19_DRV GLB_REG_GPIO_19_DRV +#define GLB_REG_GPIO_19_DRV_POS (18U) +#define GLB_REG_GPIO_19_DRV_LEN (2U) +#define GLB_REG_GPIO_19_DRV_MSK (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS) +#define GLB_REG_GPIO_19_DRV_UMSK (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)) +#define GLB_REG_GPIO_19_PU GLB_REG_GPIO_19_PU +#define GLB_REG_GPIO_19_PU_POS (20U) +#define GLB_REG_GPIO_19_PU_LEN (1U) +#define GLB_REG_GPIO_19_PU_MSK (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS) +#define GLB_REG_GPIO_19_PU_UMSK (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)) +#define GLB_REG_GPIO_19_PD GLB_REG_GPIO_19_PD +#define GLB_REG_GPIO_19_PD_POS (21U) +#define GLB_REG_GPIO_19_PD_LEN (1U) +#define GLB_REG_GPIO_19_PD_MSK (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS) +#define GLB_REG_GPIO_19_PD_UMSK (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)) +#define GLB_REG_GPIO_19_FUNC_SEL GLB_REG_GPIO_19_FUNC_SEL +#define GLB_REG_GPIO_19_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_19_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_19_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS) +#define GLB_REG_GPIO_19_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)) + +/* 0x128 : GPIO_CFGCTL10 */ +#define GLB_GPIO_CFGCTL10_OFFSET (0x128) +#define GLB_REG_GPIO_20_IE GLB_REG_GPIO_20_IE +#define GLB_REG_GPIO_20_IE_POS (0U) +#define GLB_REG_GPIO_20_IE_LEN (1U) +#define GLB_REG_GPIO_20_IE_MSK (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS) +#define GLB_REG_GPIO_20_IE_UMSK (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)) +#define GLB_REG_GPIO_20_SMT GLB_REG_GPIO_20_SMT +#define GLB_REG_GPIO_20_SMT_POS (1U) +#define GLB_REG_GPIO_20_SMT_LEN (1U) +#define GLB_REG_GPIO_20_SMT_MSK (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS) +#define GLB_REG_GPIO_20_SMT_UMSK (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)) +#define GLB_REG_GPIO_20_DRV GLB_REG_GPIO_20_DRV +#define GLB_REG_GPIO_20_DRV_POS (2U) +#define GLB_REG_GPIO_20_DRV_LEN (2U) +#define GLB_REG_GPIO_20_DRV_MSK (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS) +#define GLB_REG_GPIO_20_DRV_UMSK (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)) +#define GLB_REG_GPIO_20_PU GLB_REG_GPIO_20_PU +#define GLB_REG_GPIO_20_PU_POS (4U) +#define GLB_REG_GPIO_20_PU_LEN (1U) +#define GLB_REG_GPIO_20_PU_MSK (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS) +#define GLB_REG_GPIO_20_PU_UMSK (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)) +#define GLB_REG_GPIO_20_PD GLB_REG_GPIO_20_PD +#define GLB_REG_GPIO_20_PD_POS (5U) +#define GLB_REG_GPIO_20_PD_LEN (1U) +#define GLB_REG_GPIO_20_PD_MSK (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS) +#define GLB_REG_GPIO_20_PD_UMSK (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)) +#define GLB_REG_GPIO_20_FUNC_SEL GLB_REG_GPIO_20_FUNC_SEL +#define GLB_REG_GPIO_20_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_20_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_20_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS) +#define GLB_REG_GPIO_20_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)) +#define GLB_REG_GPIO_21_IE GLB_REG_GPIO_21_IE +#define GLB_REG_GPIO_21_IE_POS (16U) +#define GLB_REG_GPIO_21_IE_LEN (1U) +#define GLB_REG_GPIO_21_IE_MSK (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS) +#define GLB_REG_GPIO_21_IE_UMSK (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)) +#define GLB_REG_GPIO_21_SMT GLB_REG_GPIO_21_SMT +#define GLB_REG_GPIO_21_SMT_POS (17U) +#define GLB_REG_GPIO_21_SMT_LEN (1U) +#define GLB_REG_GPIO_21_SMT_MSK (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS) +#define GLB_REG_GPIO_21_SMT_UMSK (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)) +#define GLB_REG_GPIO_21_DRV GLB_REG_GPIO_21_DRV +#define GLB_REG_GPIO_21_DRV_POS (18U) +#define GLB_REG_GPIO_21_DRV_LEN (2U) +#define GLB_REG_GPIO_21_DRV_MSK (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS) +#define GLB_REG_GPIO_21_DRV_UMSK (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)) +#define GLB_REG_GPIO_21_PU GLB_REG_GPIO_21_PU +#define GLB_REG_GPIO_21_PU_POS (20U) +#define GLB_REG_GPIO_21_PU_LEN (1U) +#define GLB_REG_GPIO_21_PU_MSK (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS) +#define GLB_REG_GPIO_21_PU_UMSK (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)) +#define GLB_REG_GPIO_21_PD GLB_REG_GPIO_21_PD +#define GLB_REG_GPIO_21_PD_POS (21U) +#define GLB_REG_GPIO_21_PD_LEN (1U) +#define GLB_REG_GPIO_21_PD_MSK (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS) +#define GLB_REG_GPIO_21_PD_UMSK (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)) +#define GLB_REG_GPIO_21_FUNC_SEL GLB_REG_GPIO_21_FUNC_SEL +#define GLB_REG_GPIO_21_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_21_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_21_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS) +#define GLB_REG_GPIO_21_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)) + +/* 0x12C : GPIO_CFGCTL11 */ +#define GLB_GPIO_CFGCTL11_OFFSET (0x12C) +#define GLB_REG_GPIO_22_IE GLB_REG_GPIO_22_IE +#define GLB_REG_GPIO_22_IE_POS (0U) +#define GLB_REG_GPIO_22_IE_LEN (1U) +#define GLB_REG_GPIO_22_IE_MSK (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS) +#define GLB_REG_GPIO_22_IE_UMSK (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)) +#define GLB_REG_GPIO_22_SMT GLB_REG_GPIO_22_SMT +#define GLB_REG_GPIO_22_SMT_POS (1U) +#define GLB_REG_GPIO_22_SMT_LEN (1U) +#define GLB_REG_GPIO_22_SMT_MSK (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS) +#define GLB_REG_GPIO_22_SMT_UMSK (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)) +#define GLB_REG_GPIO_22_DRV GLB_REG_GPIO_22_DRV +#define GLB_REG_GPIO_22_DRV_POS (2U) +#define GLB_REG_GPIO_22_DRV_LEN (2U) +#define GLB_REG_GPIO_22_DRV_MSK (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS) +#define GLB_REG_GPIO_22_DRV_UMSK (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)) +#define GLB_REG_GPIO_22_PU GLB_REG_GPIO_22_PU +#define GLB_REG_GPIO_22_PU_POS (4U) +#define GLB_REG_GPIO_22_PU_LEN (1U) +#define GLB_REG_GPIO_22_PU_MSK (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS) +#define GLB_REG_GPIO_22_PU_UMSK (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)) +#define GLB_REG_GPIO_22_PD GLB_REG_GPIO_22_PD +#define GLB_REG_GPIO_22_PD_POS (5U) +#define GLB_REG_GPIO_22_PD_LEN (1U) +#define GLB_REG_GPIO_22_PD_MSK (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS) +#define GLB_REG_GPIO_22_PD_UMSK (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)) +#define GLB_REG_GPIO_22_FUNC_SEL GLB_REG_GPIO_22_FUNC_SEL +#define GLB_REG_GPIO_22_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_22_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_22_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS) +#define GLB_REG_GPIO_22_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)) +#define GLB_REG_GPIO_23_IE GLB_REG_GPIO_23_IE +#define GLB_REG_GPIO_23_IE_POS (16U) +#define GLB_REG_GPIO_23_IE_LEN (1U) +#define GLB_REG_GPIO_23_IE_MSK (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS) +#define GLB_REG_GPIO_23_IE_UMSK (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)) +#define GLB_REG_GPIO_23_SMT GLB_REG_GPIO_23_SMT +#define GLB_REG_GPIO_23_SMT_POS (17U) +#define GLB_REG_GPIO_23_SMT_LEN (1U) +#define GLB_REG_GPIO_23_SMT_MSK (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS) +#define GLB_REG_GPIO_23_SMT_UMSK (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)) +#define GLB_REG_GPIO_23_DRV GLB_REG_GPIO_23_DRV +#define GLB_REG_GPIO_23_DRV_POS (18U) +#define GLB_REG_GPIO_23_DRV_LEN (2U) +#define GLB_REG_GPIO_23_DRV_MSK (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS) +#define GLB_REG_GPIO_23_DRV_UMSK (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)) +#define GLB_REG_GPIO_23_PU GLB_REG_GPIO_23_PU +#define GLB_REG_GPIO_23_PU_POS (20U) +#define GLB_REG_GPIO_23_PU_LEN (1U) +#define GLB_REG_GPIO_23_PU_MSK (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS) +#define GLB_REG_GPIO_23_PU_UMSK (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)) +#define GLB_REG_GPIO_23_PD GLB_REG_GPIO_23_PD +#define GLB_REG_GPIO_23_PD_POS (21U) +#define GLB_REG_GPIO_23_PD_LEN (1U) +#define GLB_REG_GPIO_23_PD_MSK (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS) +#define GLB_REG_GPIO_23_PD_UMSK (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)) +#define GLB_REG_GPIO_23_FUNC_SEL GLB_REG_GPIO_23_FUNC_SEL +#define GLB_REG_GPIO_23_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_23_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_23_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS) +#define GLB_REG_GPIO_23_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS)) + +/* 0x130 : GPIO_CFGCTL12 */ +#define GLB_GPIO_CFGCTL12_OFFSET (0x130) +#define GLB_REG_GPIO_24_IE GLB_REG_GPIO_24_IE +#define GLB_REG_GPIO_24_IE_POS (0U) +#define GLB_REG_GPIO_24_IE_LEN (1U) +#define GLB_REG_GPIO_24_IE_MSK (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS) +#define GLB_REG_GPIO_24_IE_UMSK (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)) +#define GLB_REG_GPIO_24_SMT GLB_REG_GPIO_24_SMT +#define GLB_REG_GPIO_24_SMT_POS (1U) +#define GLB_REG_GPIO_24_SMT_LEN (1U) +#define GLB_REG_GPIO_24_SMT_MSK (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS) +#define GLB_REG_GPIO_24_SMT_UMSK (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)) +#define GLB_REG_GPIO_24_DRV GLB_REG_GPIO_24_DRV +#define GLB_REG_GPIO_24_DRV_POS (2U) +#define GLB_REG_GPIO_24_DRV_LEN (2U) +#define GLB_REG_GPIO_24_DRV_MSK (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS) +#define GLB_REG_GPIO_24_DRV_UMSK (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)) +#define GLB_REG_GPIO_24_PU GLB_REG_GPIO_24_PU +#define GLB_REG_GPIO_24_PU_POS (4U) +#define GLB_REG_GPIO_24_PU_LEN (1U) +#define GLB_REG_GPIO_24_PU_MSK (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS) +#define GLB_REG_GPIO_24_PU_UMSK (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)) +#define GLB_REG_GPIO_24_PD GLB_REG_GPIO_24_PD +#define GLB_REG_GPIO_24_PD_POS (5U) +#define GLB_REG_GPIO_24_PD_LEN (1U) +#define GLB_REG_GPIO_24_PD_MSK (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS) +#define GLB_REG_GPIO_24_PD_UMSK (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)) +#define GLB_REG_GPIO_24_FUNC_SEL GLB_REG_GPIO_24_FUNC_SEL +#define GLB_REG_GPIO_24_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_24_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_24_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS) +#define GLB_REG_GPIO_24_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS)) +#define GLB_REG_GPIO_25_IE GLB_REG_GPIO_25_IE +#define GLB_REG_GPIO_25_IE_POS (16U) +#define GLB_REG_GPIO_25_IE_LEN (1U) +#define GLB_REG_GPIO_25_IE_MSK (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS) +#define GLB_REG_GPIO_25_IE_UMSK (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)) +#define GLB_REG_GPIO_25_SMT GLB_REG_GPIO_25_SMT +#define GLB_REG_GPIO_25_SMT_POS (17U) +#define GLB_REG_GPIO_25_SMT_LEN (1U) +#define GLB_REG_GPIO_25_SMT_MSK (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS) +#define GLB_REG_GPIO_25_SMT_UMSK (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)) +#define GLB_REG_GPIO_25_DRV GLB_REG_GPIO_25_DRV +#define GLB_REG_GPIO_25_DRV_POS (18U) +#define GLB_REG_GPIO_25_DRV_LEN (2U) +#define GLB_REG_GPIO_25_DRV_MSK (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS) +#define GLB_REG_GPIO_25_DRV_UMSK (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)) +#define GLB_REG_GPIO_25_PU GLB_REG_GPIO_25_PU +#define GLB_REG_GPIO_25_PU_POS (20U) +#define GLB_REG_GPIO_25_PU_LEN (1U) +#define GLB_REG_GPIO_25_PU_MSK (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS) +#define GLB_REG_GPIO_25_PU_UMSK (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)) +#define GLB_REG_GPIO_25_PD GLB_REG_GPIO_25_PD +#define GLB_REG_GPIO_25_PD_POS (21U) +#define GLB_REG_GPIO_25_PD_LEN (1U) +#define GLB_REG_GPIO_25_PD_MSK (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS) +#define GLB_REG_GPIO_25_PD_UMSK (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)) +#define GLB_REG_GPIO_25_FUNC_SEL GLB_REG_GPIO_25_FUNC_SEL +#define GLB_REG_GPIO_25_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_25_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_25_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS) +#define GLB_REG_GPIO_25_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS)) + +/* 0x134 : GPIO_CFGCTL13 */ +#define GLB_GPIO_CFGCTL13_OFFSET (0x134) +#define GLB_REG_GPIO_26_IE GLB_REG_GPIO_26_IE +#define GLB_REG_GPIO_26_IE_POS (0U) +#define GLB_REG_GPIO_26_IE_LEN (1U) +#define GLB_REG_GPIO_26_IE_MSK (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS) +#define GLB_REG_GPIO_26_IE_UMSK (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)) +#define GLB_REG_GPIO_26_SMT GLB_REG_GPIO_26_SMT +#define GLB_REG_GPIO_26_SMT_POS (1U) +#define GLB_REG_GPIO_26_SMT_LEN (1U) +#define GLB_REG_GPIO_26_SMT_MSK (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS) +#define GLB_REG_GPIO_26_SMT_UMSK (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)) +#define GLB_REG_GPIO_26_DRV GLB_REG_GPIO_26_DRV +#define GLB_REG_GPIO_26_DRV_POS (2U) +#define GLB_REG_GPIO_26_DRV_LEN (2U) +#define GLB_REG_GPIO_26_DRV_MSK (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS) +#define GLB_REG_GPIO_26_DRV_UMSK (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)) +#define GLB_REG_GPIO_26_PU GLB_REG_GPIO_26_PU +#define GLB_REG_GPIO_26_PU_POS (4U) +#define GLB_REG_GPIO_26_PU_LEN (1U) +#define GLB_REG_GPIO_26_PU_MSK (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS) +#define GLB_REG_GPIO_26_PU_UMSK (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)) +#define GLB_REG_GPIO_26_PD GLB_REG_GPIO_26_PD +#define GLB_REG_GPIO_26_PD_POS (5U) +#define GLB_REG_GPIO_26_PD_LEN (1U) +#define GLB_REG_GPIO_26_PD_MSK (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS) +#define GLB_REG_GPIO_26_PD_UMSK (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)) +#define GLB_REG_GPIO_26_FUNC_SEL GLB_REG_GPIO_26_FUNC_SEL +#define GLB_REG_GPIO_26_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_26_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_26_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS) +#define GLB_REG_GPIO_26_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS)) +#define GLB_REG_GPIO_27_IE GLB_REG_GPIO_27_IE +#define GLB_REG_GPIO_27_IE_POS (16U) +#define GLB_REG_GPIO_27_IE_LEN (1U) +#define GLB_REG_GPIO_27_IE_MSK (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS) +#define GLB_REG_GPIO_27_IE_UMSK (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)) +#define GLB_REG_GPIO_27_SMT GLB_REG_GPIO_27_SMT +#define GLB_REG_GPIO_27_SMT_POS (17U) +#define GLB_REG_GPIO_27_SMT_LEN (1U) +#define GLB_REG_GPIO_27_SMT_MSK (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS) +#define GLB_REG_GPIO_27_SMT_UMSK (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)) +#define GLB_REG_GPIO_27_DRV GLB_REG_GPIO_27_DRV +#define GLB_REG_GPIO_27_DRV_POS (18U) +#define GLB_REG_GPIO_27_DRV_LEN (2U) +#define GLB_REG_GPIO_27_DRV_MSK (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS) +#define GLB_REG_GPIO_27_DRV_UMSK (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)) +#define GLB_REG_GPIO_27_PU GLB_REG_GPIO_27_PU +#define GLB_REG_GPIO_27_PU_POS (20U) +#define GLB_REG_GPIO_27_PU_LEN (1U) +#define GLB_REG_GPIO_27_PU_MSK (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS) +#define GLB_REG_GPIO_27_PU_UMSK (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)) +#define GLB_REG_GPIO_27_PD GLB_REG_GPIO_27_PD +#define GLB_REG_GPIO_27_PD_POS (21U) +#define GLB_REG_GPIO_27_PD_LEN (1U) +#define GLB_REG_GPIO_27_PD_MSK (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS) +#define GLB_REG_GPIO_27_PD_UMSK (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)) +#define GLB_REG_GPIO_27_FUNC_SEL GLB_REG_GPIO_27_FUNC_SEL +#define GLB_REG_GPIO_27_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_27_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_27_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS) +#define GLB_REG_GPIO_27_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS)) + +/* 0x138 : GPIO_CFGCTL14 */ +#define GLB_GPIO_CFGCTL14_OFFSET (0x138) +#define GLB_REG_GPIO_28_IE GLB_REG_GPIO_28_IE +#define GLB_REG_GPIO_28_IE_POS (0U) +#define GLB_REG_GPIO_28_IE_LEN (1U) +#define GLB_REG_GPIO_28_IE_MSK (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS) +#define GLB_REG_GPIO_28_IE_UMSK (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)) +#define GLB_REG_GPIO_28_SMT GLB_REG_GPIO_28_SMT +#define GLB_REG_GPIO_28_SMT_POS (1U) +#define GLB_REG_GPIO_28_SMT_LEN (1U) +#define GLB_REG_GPIO_28_SMT_MSK (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS) +#define GLB_REG_GPIO_28_SMT_UMSK (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)) +#define GLB_REG_GPIO_28_DRV GLB_REG_GPIO_28_DRV +#define GLB_REG_GPIO_28_DRV_POS (2U) +#define GLB_REG_GPIO_28_DRV_LEN (2U) +#define GLB_REG_GPIO_28_DRV_MSK (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS) +#define GLB_REG_GPIO_28_DRV_UMSK (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)) +#define GLB_REG_GPIO_28_PU GLB_REG_GPIO_28_PU +#define GLB_REG_GPIO_28_PU_POS (4U) +#define GLB_REG_GPIO_28_PU_LEN (1U) +#define GLB_REG_GPIO_28_PU_MSK (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS) +#define GLB_REG_GPIO_28_PU_UMSK (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)) +#define GLB_REG_GPIO_28_PD GLB_REG_GPIO_28_PD +#define GLB_REG_GPIO_28_PD_POS (5U) +#define GLB_REG_GPIO_28_PD_LEN (1U) +#define GLB_REG_GPIO_28_PD_MSK (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS) +#define GLB_REG_GPIO_28_PD_UMSK (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)) +#define GLB_REG_GPIO_28_FUNC_SEL GLB_REG_GPIO_28_FUNC_SEL +#define GLB_REG_GPIO_28_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_28_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_28_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS) +#define GLB_REG_GPIO_28_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS)) +#define GLB_REG_GPIO_29_IE GLB_REG_GPIO_29_IE +#define GLB_REG_GPIO_29_IE_POS (16U) +#define GLB_REG_GPIO_29_IE_LEN (1U) +#define GLB_REG_GPIO_29_IE_MSK (((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS) +#define GLB_REG_GPIO_29_IE_UMSK (~(((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS)) +#define GLB_REG_GPIO_29_SMT GLB_REG_GPIO_29_SMT +#define GLB_REG_GPIO_29_SMT_POS (17U) +#define GLB_REG_GPIO_29_SMT_LEN (1U) +#define GLB_REG_GPIO_29_SMT_MSK (((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS) +#define GLB_REG_GPIO_29_SMT_UMSK (~(((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS)) +#define GLB_REG_GPIO_29_DRV GLB_REG_GPIO_29_DRV +#define GLB_REG_GPIO_29_DRV_POS (18U) +#define GLB_REG_GPIO_29_DRV_LEN (2U) +#define GLB_REG_GPIO_29_DRV_MSK (((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS) +#define GLB_REG_GPIO_29_DRV_UMSK (~(((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS)) +#define GLB_REG_GPIO_29_PU GLB_REG_GPIO_29_PU +#define GLB_REG_GPIO_29_PU_POS (20U) +#define GLB_REG_GPIO_29_PU_LEN (1U) +#define GLB_REG_GPIO_29_PU_MSK (((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS) +#define GLB_REG_GPIO_29_PU_UMSK (~(((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS)) +#define GLB_REG_GPIO_29_PD GLB_REG_GPIO_29_PD +#define GLB_REG_GPIO_29_PD_POS (21U) +#define GLB_REG_GPIO_29_PD_LEN (1U) +#define GLB_REG_GPIO_29_PD_MSK (((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS) +#define GLB_REG_GPIO_29_PD_UMSK (~(((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS)) +#define GLB_REG_GPIO_29_FUNC_SEL GLB_REG_GPIO_29_FUNC_SEL +#define GLB_REG_GPIO_29_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_29_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_29_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS) +#define GLB_REG_GPIO_29_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS)) + +/* 0x13C : GPIO_CFGCTL15 */ +#define GLB_GPIO_CFGCTL15_OFFSET (0x13C) +#define GLB_REG_GPIO_30_IE GLB_REG_GPIO_30_IE +#define GLB_REG_GPIO_30_IE_POS (0U) +#define GLB_REG_GPIO_30_IE_LEN (1U) +#define GLB_REG_GPIO_30_IE_MSK (((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS) +#define GLB_REG_GPIO_30_IE_UMSK (~(((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS)) +#define GLB_REG_GPIO_30_SMT GLB_REG_GPIO_30_SMT +#define GLB_REG_GPIO_30_SMT_POS (1U) +#define GLB_REG_GPIO_30_SMT_LEN (1U) +#define GLB_REG_GPIO_30_SMT_MSK (((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS) +#define GLB_REG_GPIO_30_SMT_UMSK (~(((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS)) +#define GLB_REG_GPIO_30_DRV GLB_REG_GPIO_30_DRV +#define GLB_REG_GPIO_30_DRV_POS (2U) +#define GLB_REG_GPIO_30_DRV_LEN (2U) +#define GLB_REG_GPIO_30_DRV_MSK (((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS) +#define GLB_REG_GPIO_30_DRV_UMSK (~(((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS)) +#define GLB_REG_GPIO_30_PU GLB_REG_GPIO_30_PU +#define GLB_REG_GPIO_30_PU_POS (4U) +#define GLB_REG_GPIO_30_PU_LEN (1U) +#define GLB_REG_GPIO_30_PU_MSK (((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS) +#define GLB_REG_GPIO_30_PU_UMSK (~(((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS)) +#define GLB_REG_GPIO_30_PD GLB_REG_GPIO_30_PD +#define GLB_REG_GPIO_30_PD_POS (5U) +#define GLB_REG_GPIO_30_PD_LEN (1U) +#define GLB_REG_GPIO_30_PD_MSK (((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS) +#define GLB_REG_GPIO_30_PD_UMSK (~(((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS)) +#define GLB_REG_GPIO_30_FUNC_SEL GLB_REG_GPIO_30_FUNC_SEL +#define GLB_REG_GPIO_30_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_30_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_30_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS) +#define GLB_REG_GPIO_30_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS)) +#define GLB_REG_GPIO_31_IE GLB_REG_GPIO_31_IE +#define GLB_REG_GPIO_31_IE_POS (16U) +#define GLB_REG_GPIO_31_IE_LEN (1U) +#define GLB_REG_GPIO_31_IE_MSK (((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS) +#define GLB_REG_GPIO_31_IE_UMSK (~(((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS)) +#define GLB_REG_GPIO_31_SMT GLB_REG_GPIO_31_SMT +#define GLB_REG_GPIO_31_SMT_POS (17U) +#define GLB_REG_GPIO_31_SMT_LEN (1U) +#define GLB_REG_GPIO_31_SMT_MSK (((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS) +#define GLB_REG_GPIO_31_SMT_UMSK (~(((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS)) +#define GLB_REG_GPIO_31_DRV GLB_REG_GPIO_31_DRV +#define GLB_REG_GPIO_31_DRV_POS (18U) +#define GLB_REG_GPIO_31_DRV_LEN (2U) +#define GLB_REG_GPIO_31_DRV_MSK (((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS) +#define GLB_REG_GPIO_31_DRV_UMSK (~(((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS)) +#define GLB_REG_GPIO_31_PU GLB_REG_GPIO_31_PU +#define GLB_REG_GPIO_31_PU_POS (20U) +#define GLB_REG_GPIO_31_PU_LEN (1U) +#define GLB_REG_GPIO_31_PU_MSK (((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS) +#define GLB_REG_GPIO_31_PU_UMSK (~(((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS)) +#define GLB_REG_GPIO_31_PD GLB_REG_GPIO_31_PD +#define GLB_REG_GPIO_31_PD_POS (21U) +#define GLB_REG_GPIO_31_PD_LEN (1U) +#define GLB_REG_GPIO_31_PD_MSK (((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS) +#define GLB_REG_GPIO_31_PD_UMSK (~(((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS)) +#define GLB_REG_GPIO_31_FUNC_SEL GLB_REG_GPIO_31_FUNC_SEL +#define GLB_REG_GPIO_31_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_31_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_31_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS) +#define GLB_REG_GPIO_31_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS)) + +/* 0x140 : GPIO_CFGCTL16 */ +#define GLB_GPIO_CFGCTL16_OFFSET (0x140) +#define GLB_REG_GPIO_32_IE GLB_REG_GPIO_32_IE +#define GLB_REG_GPIO_32_IE_POS (0U) +#define GLB_REG_GPIO_32_IE_LEN (1U) +#define GLB_REG_GPIO_32_IE_MSK (((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS) +#define GLB_REG_GPIO_32_IE_UMSK (~(((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS)) +#define GLB_REG_GPIO_32_SMT GLB_REG_GPIO_32_SMT +#define GLB_REG_GPIO_32_SMT_POS (1U) +#define GLB_REG_GPIO_32_SMT_LEN (1U) +#define GLB_REG_GPIO_32_SMT_MSK (((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS) +#define GLB_REG_GPIO_32_SMT_UMSK (~(((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS)) +#define GLB_REG_GPIO_32_DRV GLB_REG_GPIO_32_DRV +#define GLB_REG_GPIO_32_DRV_POS (2U) +#define GLB_REG_GPIO_32_DRV_LEN (2U) +#define GLB_REG_GPIO_32_DRV_MSK (((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS) +#define GLB_REG_GPIO_32_DRV_UMSK (~(((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS)) +#define GLB_REG_GPIO_32_PU GLB_REG_GPIO_32_PU +#define GLB_REG_GPIO_32_PU_POS (4U) +#define GLB_REG_GPIO_32_PU_LEN (1U) +#define GLB_REG_GPIO_32_PU_MSK (((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS) +#define GLB_REG_GPIO_32_PU_UMSK (~(((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS)) +#define GLB_REG_GPIO_32_PD GLB_REG_GPIO_32_PD +#define GLB_REG_GPIO_32_PD_POS (5U) +#define GLB_REG_GPIO_32_PD_LEN (1U) +#define GLB_REG_GPIO_32_PD_MSK (((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS) +#define GLB_REG_GPIO_32_PD_UMSK (~(((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS)) +#define GLB_REG_GPIO_33_IE GLB_REG_GPIO_33_IE +#define GLB_REG_GPIO_33_IE_POS (16U) +#define GLB_REG_GPIO_33_IE_LEN (1U) +#define GLB_REG_GPIO_33_IE_MSK (((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS) +#define GLB_REG_GPIO_33_IE_UMSK (~(((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS)) +#define GLB_REG_GPIO_33_SMT GLB_REG_GPIO_33_SMT +#define GLB_REG_GPIO_33_SMT_POS (17U) +#define GLB_REG_GPIO_33_SMT_LEN (1U) +#define GLB_REG_GPIO_33_SMT_MSK (((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS) +#define GLB_REG_GPIO_33_SMT_UMSK (~(((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS)) +#define GLB_REG_GPIO_33_DRV GLB_REG_GPIO_33_DRV +#define GLB_REG_GPIO_33_DRV_POS (18U) +#define GLB_REG_GPIO_33_DRV_LEN (2U) +#define GLB_REG_GPIO_33_DRV_MSK (((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS) +#define GLB_REG_GPIO_33_DRV_UMSK (~(((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS)) +#define GLB_REG_GPIO_33_PU GLB_REG_GPIO_33_PU +#define GLB_REG_GPIO_33_PU_POS (20U) +#define GLB_REG_GPIO_33_PU_LEN (1U) +#define GLB_REG_GPIO_33_PU_MSK (((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS) +#define GLB_REG_GPIO_33_PU_UMSK (~(((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS)) +#define GLB_REG_GPIO_33_PD GLB_REG_GPIO_33_PD +#define GLB_REG_GPIO_33_PD_POS (21U) +#define GLB_REG_GPIO_33_PD_LEN (1U) +#define GLB_REG_GPIO_33_PD_MSK (((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS) +#define GLB_REG_GPIO_33_PD_UMSK (~(((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS)) + +/* 0x144 : GPIO_CFGCTL17 */ +#define GLB_GPIO_CFGCTL17_OFFSET (0x144) +#define GLB_REG_GPIO_34_IE GLB_REG_GPIO_34_IE +#define GLB_REG_GPIO_34_IE_POS (0U) +#define GLB_REG_GPIO_34_IE_LEN (1U) +#define GLB_REG_GPIO_34_IE_MSK (((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS) +#define GLB_REG_GPIO_34_IE_UMSK (~(((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS)) +#define GLB_REG_GPIO_34_SMT GLB_REG_GPIO_34_SMT +#define GLB_REG_GPIO_34_SMT_POS (1U) +#define GLB_REG_GPIO_34_SMT_LEN (1U) +#define GLB_REG_GPIO_34_SMT_MSK (((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS) +#define GLB_REG_GPIO_34_SMT_UMSK (~(((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS)) +#define GLB_REG_GPIO_34_DRV GLB_REG_GPIO_34_DRV +#define GLB_REG_GPIO_34_DRV_POS (2U) +#define GLB_REG_GPIO_34_DRV_LEN (2U) +#define GLB_REG_GPIO_34_DRV_MSK (((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS) +#define GLB_REG_GPIO_34_DRV_UMSK (~(((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS)) +#define GLB_REG_GPIO_34_PU GLB_REG_GPIO_34_PU +#define GLB_REG_GPIO_34_PU_POS (4U) +#define GLB_REG_GPIO_34_PU_LEN (1U) +#define GLB_REG_GPIO_34_PU_MSK (((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS) +#define GLB_REG_GPIO_34_PU_UMSK (~(((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS)) +#define GLB_REG_GPIO_34_PD GLB_REG_GPIO_34_PD +#define GLB_REG_GPIO_34_PD_POS (5U) +#define GLB_REG_GPIO_34_PD_LEN (1U) +#define GLB_REG_GPIO_34_PD_MSK (((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS) +#define GLB_REG_GPIO_34_PD_UMSK (~(((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS)) +#define GLB_REG_GPIO_35_IE GLB_REG_GPIO_35_IE +#define GLB_REG_GPIO_35_IE_POS (16U) +#define GLB_REG_GPIO_35_IE_LEN (1U) +#define GLB_REG_GPIO_35_IE_MSK (((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS) +#define GLB_REG_GPIO_35_IE_UMSK (~(((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS)) +#define GLB_REG_GPIO_35_SMT GLB_REG_GPIO_35_SMT +#define GLB_REG_GPIO_35_SMT_POS (17U) +#define GLB_REG_GPIO_35_SMT_LEN (1U) +#define GLB_REG_GPIO_35_SMT_MSK (((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS) +#define GLB_REG_GPIO_35_SMT_UMSK (~(((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS)) +#define GLB_REG_GPIO_35_DRV GLB_REG_GPIO_35_DRV +#define GLB_REG_GPIO_35_DRV_POS (18U) +#define GLB_REG_GPIO_35_DRV_LEN (2U) +#define GLB_REG_GPIO_35_DRV_MSK (((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS) +#define GLB_REG_GPIO_35_DRV_UMSK (~(((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS)) +#define GLB_REG_GPIO_35_PU GLB_REG_GPIO_35_PU +#define GLB_REG_GPIO_35_PU_POS (20U) +#define GLB_REG_GPIO_35_PU_LEN (1U) +#define GLB_REG_GPIO_35_PU_MSK (((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS) +#define GLB_REG_GPIO_35_PU_UMSK (~(((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS)) +#define GLB_REG_GPIO_35_PD GLB_REG_GPIO_35_PD +#define GLB_REG_GPIO_35_PD_POS (21U) +#define GLB_REG_GPIO_35_PD_LEN (1U) +#define GLB_REG_GPIO_35_PD_MSK (((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS) +#define GLB_REG_GPIO_35_PD_UMSK (~(((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS)) + +/* 0x148 : GPIO_CFGCTL18 */ +#define GLB_GPIO_CFGCTL18_OFFSET (0x148) +#define GLB_REG_GPIO_36_IE GLB_REG_GPIO_36_IE +#define GLB_REG_GPIO_36_IE_POS (0U) +#define GLB_REG_GPIO_36_IE_LEN (1U) +#define GLB_REG_GPIO_36_IE_MSK (((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS) +#define GLB_REG_GPIO_36_IE_UMSK (~(((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS)) +#define GLB_REG_GPIO_36_SMT GLB_REG_GPIO_36_SMT +#define GLB_REG_GPIO_36_SMT_POS (1U) +#define GLB_REG_GPIO_36_SMT_LEN (1U) +#define GLB_REG_GPIO_36_SMT_MSK (((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS) +#define GLB_REG_GPIO_36_SMT_UMSK (~(((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS)) +#define GLB_REG_GPIO_36_DRV GLB_REG_GPIO_36_DRV +#define GLB_REG_GPIO_36_DRV_POS (2U) +#define GLB_REG_GPIO_36_DRV_LEN (2U) +#define GLB_REG_GPIO_36_DRV_MSK (((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS) +#define GLB_REG_GPIO_36_DRV_UMSK (~(((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS)) +#define GLB_REG_GPIO_36_PU GLB_REG_GPIO_36_PU +#define GLB_REG_GPIO_36_PU_POS (4U) +#define GLB_REG_GPIO_36_PU_LEN (1U) +#define GLB_REG_GPIO_36_PU_MSK (((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS) +#define GLB_REG_GPIO_36_PU_UMSK (~(((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS)) +#define GLB_REG_GPIO_36_PD GLB_REG_GPIO_36_PD +#define GLB_REG_GPIO_36_PD_POS (5U) +#define GLB_REG_GPIO_36_PD_LEN (1U) +#define GLB_REG_GPIO_36_PD_MSK (((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS) +#define GLB_REG_GPIO_36_PD_UMSK (~(((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS)) +#define GLB_REG_GPIO_37_IE GLB_REG_GPIO_37_IE +#define GLB_REG_GPIO_37_IE_POS (16U) +#define GLB_REG_GPIO_37_IE_LEN (1U) +#define GLB_REG_GPIO_37_IE_MSK (((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS) +#define GLB_REG_GPIO_37_IE_UMSK (~(((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS)) +#define GLB_REG_GPIO_37_SMT GLB_REG_GPIO_37_SMT +#define GLB_REG_GPIO_37_SMT_POS (17U) +#define GLB_REG_GPIO_37_SMT_LEN (1U) +#define GLB_REG_GPIO_37_SMT_MSK (((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS) +#define GLB_REG_GPIO_37_SMT_UMSK (~(((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS)) +#define GLB_REG_GPIO_37_DRV GLB_REG_GPIO_37_DRV +#define GLB_REG_GPIO_37_DRV_POS (18U) +#define GLB_REG_GPIO_37_DRV_LEN (2U) +#define GLB_REG_GPIO_37_DRV_MSK (((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS) +#define GLB_REG_GPIO_37_DRV_UMSK (~(((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS)) +#define GLB_REG_GPIO_37_PU GLB_REG_GPIO_37_PU +#define GLB_REG_GPIO_37_PU_POS (20U) +#define GLB_REG_GPIO_37_PU_LEN (1U) +#define GLB_REG_GPIO_37_PU_MSK (((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS) +#define GLB_REG_GPIO_37_PU_UMSK (~(((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS)) +#define GLB_REG_GPIO_37_PD GLB_REG_GPIO_37_PD +#define GLB_REG_GPIO_37_PD_POS (21U) +#define GLB_REG_GPIO_37_PD_LEN (1U) +#define GLB_REG_GPIO_37_PD_MSK (((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS) +#define GLB_REG_GPIO_37_PD_UMSK (~(((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS)) + +/* 0x180 : GPIO_CFGCTL30 */ +#define GLB_GPIO_CFGCTL30_OFFSET (0x180) +#define GLB_REG_GPIO_0_I GLB_REG_GPIO_0_I +#define GLB_REG_GPIO_0_I_POS (0U) +#define GLB_REG_GPIO_0_I_LEN (1U) +#define GLB_REG_GPIO_0_I_MSK (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS) +#define GLB_REG_GPIO_0_I_UMSK (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)) +#define GLB_REG_GPIO_1_I GLB_REG_GPIO_1_I +#define GLB_REG_GPIO_1_I_POS (1U) +#define GLB_REG_GPIO_1_I_LEN (1U) +#define GLB_REG_GPIO_1_I_MSK (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS) +#define GLB_REG_GPIO_1_I_UMSK (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)) +#define GLB_REG_GPIO_2_I GLB_REG_GPIO_2_I +#define GLB_REG_GPIO_2_I_POS (2U) +#define GLB_REG_GPIO_2_I_LEN (1U) +#define GLB_REG_GPIO_2_I_MSK (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS) +#define GLB_REG_GPIO_2_I_UMSK (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)) +#define GLB_REG_GPIO_3_I GLB_REG_GPIO_3_I +#define GLB_REG_GPIO_3_I_POS (3U) +#define GLB_REG_GPIO_3_I_LEN (1U) +#define GLB_REG_GPIO_3_I_MSK (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS) +#define GLB_REG_GPIO_3_I_UMSK (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)) +#define GLB_REG_GPIO_4_I GLB_REG_GPIO_4_I +#define GLB_REG_GPIO_4_I_POS (4U) +#define GLB_REG_GPIO_4_I_LEN (1U) +#define GLB_REG_GPIO_4_I_MSK (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS) +#define GLB_REG_GPIO_4_I_UMSK (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)) +#define GLB_REG_GPIO_5_I GLB_REG_GPIO_5_I +#define GLB_REG_GPIO_5_I_POS (5U) +#define GLB_REG_GPIO_5_I_LEN (1U) +#define GLB_REG_GPIO_5_I_MSK (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS) +#define GLB_REG_GPIO_5_I_UMSK (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)) +#define GLB_REG_GPIO_6_I GLB_REG_GPIO_6_I +#define GLB_REG_GPIO_6_I_POS (6U) +#define GLB_REG_GPIO_6_I_LEN (1U) +#define GLB_REG_GPIO_6_I_MSK (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS) +#define GLB_REG_GPIO_6_I_UMSK (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)) +#define GLB_REG_GPIO_7_I GLB_REG_GPIO_7_I +#define GLB_REG_GPIO_7_I_POS (7U) +#define GLB_REG_GPIO_7_I_LEN (1U) +#define GLB_REG_GPIO_7_I_MSK (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS) +#define GLB_REG_GPIO_7_I_UMSK (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)) +#define GLB_REG_GPIO_8_I GLB_REG_GPIO_8_I +#define GLB_REG_GPIO_8_I_POS (8U) +#define GLB_REG_GPIO_8_I_LEN (1U) +#define GLB_REG_GPIO_8_I_MSK (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS) +#define GLB_REG_GPIO_8_I_UMSK (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)) +#define GLB_REG_GPIO_9_I GLB_REG_GPIO_9_I +#define GLB_REG_GPIO_9_I_POS (9U) +#define GLB_REG_GPIO_9_I_LEN (1U) +#define GLB_REG_GPIO_9_I_MSK (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS) +#define GLB_REG_GPIO_9_I_UMSK (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)) +#define GLB_REG_GPIO_10_I GLB_REG_GPIO_10_I +#define GLB_REG_GPIO_10_I_POS (10U) +#define GLB_REG_GPIO_10_I_LEN (1U) +#define GLB_REG_GPIO_10_I_MSK (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS) +#define GLB_REG_GPIO_10_I_UMSK (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)) +#define GLB_REG_GPIO_11_I GLB_REG_GPIO_11_I +#define GLB_REG_GPIO_11_I_POS (11U) +#define GLB_REG_GPIO_11_I_LEN (1U) +#define GLB_REG_GPIO_11_I_MSK (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS) +#define GLB_REG_GPIO_11_I_UMSK (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)) +#define GLB_REG_GPIO_12_I GLB_REG_GPIO_12_I +#define GLB_REG_GPIO_12_I_POS (12U) +#define GLB_REG_GPIO_12_I_LEN (1U) +#define GLB_REG_GPIO_12_I_MSK (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS) +#define GLB_REG_GPIO_12_I_UMSK (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)) +#define GLB_REG_GPIO_13_I GLB_REG_GPIO_13_I +#define GLB_REG_GPIO_13_I_POS (13U) +#define GLB_REG_GPIO_13_I_LEN (1U) +#define GLB_REG_GPIO_13_I_MSK (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS) +#define GLB_REG_GPIO_13_I_UMSK (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)) +#define GLB_REG_GPIO_14_I GLB_REG_GPIO_14_I +#define GLB_REG_GPIO_14_I_POS (14U) +#define GLB_REG_GPIO_14_I_LEN (1U) +#define GLB_REG_GPIO_14_I_MSK (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS) +#define GLB_REG_GPIO_14_I_UMSK (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)) +#define GLB_REG_GPIO_15_I GLB_REG_GPIO_15_I +#define GLB_REG_GPIO_15_I_POS (15U) +#define GLB_REG_GPIO_15_I_LEN (1U) +#define GLB_REG_GPIO_15_I_MSK (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS) +#define GLB_REG_GPIO_15_I_UMSK (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)) +#define GLB_REG_GPIO_16_I GLB_REG_GPIO_16_I +#define GLB_REG_GPIO_16_I_POS (16U) +#define GLB_REG_GPIO_16_I_LEN (1U) +#define GLB_REG_GPIO_16_I_MSK (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS) +#define GLB_REG_GPIO_16_I_UMSK (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)) +#define GLB_REG_GPIO_17_I GLB_REG_GPIO_17_I +#define GLB_REG_GPIO_17_I_POS (17U) +#define GLB_REG_GPIO_17_I_LEN (1U) +#define GLB_REG_GPIO_17_I_MSK (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS) +#define GLB_REG_GPIO_17_I_UMSK (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)) +#define GLB_REG_GPIO_18_I GLB_REG_GPIO_18_I +#define GLB_REG_GPIO_18_I_POS (18U) +#define GLB_REG_GPIO_18_I_LEN (1U) +#define GLB_REG_GPIO_18_I_MSK (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS) +#define GLB_REG_GPIO_18_I_UMSK (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)) +#define GLB_REG_GPIO_19_I GLB_REG_GPIO_19_I +#define GLB_REG_GPIO_19_I_POS (19U) +#define GLB_REG_GPIO_19_I_LEN (1U) +#define GLB_REG_GPIO_19_I_MSK (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS) +#define GLB_REG_GPIO_19_I_UMSK (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)) +#define GLB_REG_GPIO_20_I GLB_REG_GPIO_20_I +#define GLB_REG_GPIO_20_I_POS (20U) +#define GLB_REG_GPIO_20_I_LEN (1U) +#define GLB_REG_GPIO_20_I_MSK (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS) +#define GLB_REG_GPIO_20_I_UMSK (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)) +#define GLB_REG_GPIO_21_I GLB_REG_GPIO_21_I +#define GLB_REG_GPIO_21_I_POS (21U) +#define GLB_REG_GPIO_21_I_LEN (1U) +#define GLB_REG_GPIO_21_I_MSK (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS) +#define GLB_REG_GPIO_21_I_UMSK (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)) +#define GLB_REG_GPIO_22_I GLB_REG_GPIO_22_I +#define GLB_REG_GPIO_22_I_POS (22U) +#define GLB_REG_GPIO_22_I_LEN (1U) +#define GLB_REG_GPIO_22_I_MSK (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS) +#define GLB_REG_GPIO_22_I_UMSK (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)) +#define GLB_REG_GPIO_23_I GLB_REG_GPIO_23_I +#define GLB_REG_GPIO_23_I_POS (23U) +#define GLB_REG_GPIO_23_I_LEN (1U) +#define GLB_REG_GPIO_23_I_MSK (((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS) +#define GLB_REG_GPIO_23_I_UMSK (~(((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS)) +#define GLB_REG_GPIO_24_I GLB_REG_GPIO_24_I +#define GLB_REG_GPIO_24_I_POS (24U) +#define GLB_REG_GPIO_24_I_LEN (1U) +#define GLB_REG_GPIO_24_I_MSK (((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS) +#define GLB_REG_GPIO_24_I_UMSK (~(((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS)) +#define GLB_REG_GPIO_25_I GLB_REG_GPIO_25_I +#define GLB_REG_GPIO_25_I_POS (25U) +#define GLB_REG_GPIO_25_I_LEN (1U) +#define GLB_REG_GPIO_25_I_MSK (((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS) +#define GLB_REG_GPIO_25_I_UMSK (~(((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS)) +#define GLB_REG_GPIO_26_I GLB_REG_GPIO_26_I +#define GLB_REG_GPIO_26_I_POS (26U) +#define GLB_REG_GPIO_26_I_LEN (1U) +#define GLB_REG_GPIO_26_I_MSK (((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS) +#define GLB_REG_GPIO_26_I_UMSK (~(((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS)) +#define GLB_REG_GPIO_27_I GLB_REG_GPIO_27_I +#define GLB_REG_GPIO_27_I_POS (27U) +#define GLB_REG_GPIO_27_I_LEN (1U) +#define GLB_REG_GPIO_27_I_MSK (((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS) +#define GLB_REG_GPIO_27_I_UMSK (~(((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS)) +#define GLB_REG_GPIO_28_I GLB_REG_GPIO_28_I +#define GLB_REG_GPIO_28_I_POS (28U) +#define GLB_REG_GPIO_28_I_LEN (1U) +#define GLB_REG_GPIO_28_I_MSK (((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS) +#define GLB_REG_GPIO_28_I_UMSK (~(((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS)) +#define GLB_REG_GPIO_29_I GLB_REG_GPIO_29_I +#define GLB_REG_GPIO_29_I_POS (29U) +#define GLB_REG_GPIO_29_I_LEN (1U) +#define GLB_REG_GPIO_29_I_MSK (((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS) +#define GLB_REG_GPIO_29_I_UMSK (~(((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS)) +#define GLB_REG_GPIO_30_I GLB_REG_GPIO_30_I +#define GLB_REG_GPIO_30_I_POS (30U) +#define GLB_REG_GPIO_30_I_LEN (1U) +#define GLB_REG_GPIO_30_I_MSK (((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS) +#define GLB_REG_GPIO_30_I_UMSK (~(((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS)) +#define GLB_REG_GPIO_31_I GLB_REG_GPIO_31_I +#define GLB_REG_GPIO_31_I_POS (31U) +#define GLB_REG_GPIO_31_I_LEN (1U) +#define GLB_REG_GPIO_31_I_MSK (((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS) +#define GLB_REG_GPIO_31_I_UMSK (~(((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS)) + +/* 0x184 : GPIO_CFGCTL31 */ +#define GLB_GPIO_CFGCTL31_OFFSET (0x184) + +/* 0x188 : GPIO_CFGCTL32 */ +#define GLB_GPIO_CFGCTL32_OFFSET (0x188) +#define GLB_REG_GPIO_0_O GLB_REG_GPIO_0_O +#define GLB_REG_GPIO_0_O_POS (0U) +#define GLB_REG_GPIO_0_O_LEN (1U) +#define GLB_REG_GPIO_0_O_MSK (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS) +#define GLB_REG_GPIO_0_O_UMSK (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)) +#define GLB_REG_GPIO_1_O GLB_REG_GPIO_1_O +#define GLB_REG_GPIO_1_O_POS (1U) +#define GLB_REG_GPIO_1_O_LEN (1U) +#define GLB_REG_GPIO_1_O_MSK (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS) +#define GLB_REG_GPIO_1_O_UMSK (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)) +#define GLB_REG_GPIO_2_O GLB_REG_GPIO_2_O +#define GLB_REG_GPIO_2_O_POS (2U) +#define GLB_REG_GPIO_2_O_LEN (1U) +#define GLB_REG_GPIO_2_O_MSK (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS) +#define GLB_REG_GPIO_2_O_UMSK (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)) +#define GLB_REG_GPIO_3_O GLB_REG_GPIO_3_O +#define GLB_REG_GPIO_3_O_POS (3U) +#define GLB_REG_GPIO_3_O_LEN (1U) +#define GLB_REG_GPIO_3_O_MSK (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS) +#define GLB_REG_GPIO_3_O_UMSK (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)) +#define GLB_REG_GPIO_4_O GLB_REG_GPIO_4_O +#define GLB_REG_GPIO_4_O_POS (4U) +#define GLB_REG_GPIO_4_O_LEN (1U) +#define GLB_REG_GPIO_4_O_MSK (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS) +#define GLB_REG_GPIO_4_O_UMSK (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)) +#define GLB_REG_GPIO_5_O GLB_REG_GPIO_5_O +#define GLB_REG_GPIO_5_O_POS (5U) +#define GLB_REG_GPIO_5_O_LEN (1U) +#define GLB_REG_GPIO_5_O_MSK (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS) +#define GLB_REG_GPIO_5_O_UMSK (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)) +#define GLB_REG_GPIO_6_O GLB_REG_GPIO_6_O +#define GLB_REG_GPIO_6_O_POS (6U) +#define GLB_REG_GPIO_6_O_LEN (1U) +#define GLB_REG_GPIO_6_O_MSK (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS) +#define GLB_REG_GPIO_6_O_UMSK (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)) +#define GLB_REG_GPIO_7_O GLB_REG_GPIO_7_O +#define GLB_REG_GPIO_7_O_POS (7U) +#define GLB_REG_GPIO_7_O_LEN (1U) +#define GLB_REG_GPIO_7_O_MSK (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS) +#define GLB_REG_GPIO_7_O_UMSK (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)) +#define GLB_REG_GPIO_8_O GLB_REG_GPIO_8_O +#define GLB_REG_GPIO_8_O_POS (8U) +#define GLB_REG_GPIO_8_O_LEN (1U) +#define GLB_REG_GPIO_8_O_MSK (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS) +#define GLB_REG_GPIO_8_O_UMSK (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)) +#define GLB_REG_GPIO_9_O GLB_REG_GPIO_9_O +#define GLB_REG_GPIO_9_O_POS (9U) +#define GLB_REG_GPIO_9_O_LEN (1U) +#define GLB_REG_GPIO_9_O_MSK (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS) +#define GLB_REG_GPIO_9_O_UMSK (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)) +#define GLB_REG_GPIO_10_O GLB_REG_GPIO_10_O +#define GLB_REG_GPIO_10_O_POS (10U) +#define GLB_REG_GPIO_10_O_LEN (1U) +#define GLB_REG_GPIO_10_O_MSK (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS) +#define GLB_REG_GPIO_10_O_UMSK (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)) +#define GLB_REG_GPIO_11_O GLB_REG_GPIO_11_O +#define GLB_REG_GPIO_11_O_POS (11U) +#define GLB_REG_GPIO_11_O_LEN (1U) +#define GLB_REG_GPIO_11_O_MSK (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS) +#define GLB_REG_GPIO_11_O_UMSK (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)) +#define GLB_REG_GPIO_12_O GLB_REG_GPIO_12_O +#define GLB_REG_GPIO_12_O_POS (12U) +#define GLB_REG_GPIO_12_O_LEN (1U) +#define GLB_REG_GPIO_12_O_MSK (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS) +#define GLB_REG_GPIO_12_O_UMSK (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)) +#define GLB_REG_GPIO_13_O GLB_REG_GPIO_13_O +#define GLB_REG_GPIO_13_O_POS (13U) +#define GLB_REG_GPIO_13_O_LEN (1U) +#define GLB_REG_GPIO_13_O_MSK (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS) +#define GLB_REG_GPIO_13_O_UMSK (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)) +#define GLB_REG_GPIO_14_O GLB_REG_GPIO_14_O +#define GLB_REG_GPIO_14_O_POS (14U) +#define GLB_REG_GPIO_14_O_LEN (1U) +#define GLB_REG_GPIO_14_O_MSK (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS) +#define GLB_REG_GPIO_14_O_UMSK (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)) +#define GLB_REG_GPIO_15_O GLB_REG_GPIO_15_O +#define GLB_REG_GPIO_15_O_POS (15U) +#define GLB_REG_GPIO_15_O_LEN (1U) +#define GLB_REG_GPIO_15_O_MSK (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS) +#define GLB_REG_GPIO_15_O_UMSK (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)) +#define GLB_REG_GPIO_16_O GLB_REG_GPIO_16_O +#define GLB_REG_GPIO_16_O_POS (16U) +#define GLB_REG_GPIO_16_O_LEN (1U) +#define GLB_REG_GPIO_16_O_MSK (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS) +#define GLB_REG_GPIO_16_O_UMSK (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)) +#define GLB_REG_GPIO_17_O GLB_REG_GPIO_17_O +#define GLB_REG_GPIO_17_O_POS (17U) +#define GLB_REG_GPIO_17_O_LEN (1U) +#define GLB_REG_GPIO_17_O_MSK (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS) +#define GLB_REG_GPIO_17_O_UMSK (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)) +#define GLB_REG_GPIO_18_O GLB_REG_GPIO_18_O +#define GLB_REG_GPIO_18_O_POS (18U) +#define GLB_REG_GPIO_18_O_LEN (1U) +#define GLB_REG_GPIO_18_O_MSK (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS) +#define GLB_REG_GPIO_18_O_UMSK (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)) +#define GLB_REG_GPIO_19_O GLB_REG_GPIO_19_O +#define GLB_REG_GPIO_19_O_POS (19U) +#define GLB_REG_GPIO_19_O_LEN (1U) +#define GLB_REG_GPIO_19_O_MSK (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS) +#define GLB_REG_GPIO_19_O_UMSK (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)) +#define GLB_REG_GPIO_20_O GLB_REG_GPIO_20_O +#define GLB_REG_GPIO_20_O_POS (20U) +#define GLB_REG_GPIO_20_O_LEN (1U) +#define GLB_REG_GPIO_20_O_MSK (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS) +#define GLB_REG_GPIO_20_O_UMSK (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)) +#define GLB_REG_GPIO_21_O GLB_REG_GPIO_21_O +#define GLB_REG_GPIO_21_O_POS (21U) +#define GLB_REG_GPIO_21_O_LEN (1U) +#define GLB_REG_GPIO_21_O_MSK (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS) +#define GLB_REG_GPIO_21_O_UMSK (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)) +#define GLB_REG_GPIO_22_O GLB_REG_GPIO_22_O +#define GLB_REG_GPIO_22_O_POS (22U) +#define GLB_REG_GPIO_22_O_LEN (1U) +#define GLB_REG_GPIO_22_O_MSK (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS) +#define GLB_REG_GPIO_22_O_UMSK (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)) +#define GLB_REG_GPIO_23_O GLB_REG_GPIO_23_O +#define GLB_REG_GPIO_23_O_POS (23U) +#define GLB_REG_GPIO_23_O_LEN (1U) +#define GLB_REG_GPIO_23_O_MSK (((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS) +#define GLB_REG_GPIO_23_O_UMSK (~(((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS)) +#define GLB_REG_GPIO_24_O GLB_REG_GPIO_24_O +#define GLB_REG_GPIO_24_O_POS (24U) +#define GLB_REG_GPIO_24_O_LEN (1U) +#define GLB_REG_GPIO_24_O_MSK (((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS) +#define GLB_REG_GPIO_24_O_UMSK (~(((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS)) +#define GLB_REG_GPIO_25_O GLB_REG_GPIO_25_O +#define GLB_REG_GPIO_25_O_POS (25U) +#define GLB_REG_GPIO_25_O_LEN (1U) +#define GLB_REG_GPIO_25_O_MSK (((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS) +#define GLB_REG_GPIO_25_O_UMSK (~(((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS)) +#define GLB_REG_GPIO_26_O GLB_REG_GPIO_26_O +#define GLB_REG_GPIO_26_O_POS (26U) +#define GLB_REG_GPIO_26_O_LEN (1U) +#define GLB_REG_GPIO_26_O_MSK (((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS) +#define GLB_REG_GPIO_26_O_UMSK (~(((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS)) +#define GLB_REG_GPIO_27_O GLB_REG_GPIO_27_O +#define GLB_REG_GPIO_27_O_POS (27U) +#define GLB_REG_GPIO_27_O_LEN (1U) +#define GLB_REG_GPIO_27_O_MSK (((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS) +#define GLB_REG_GPIO_27_O_UMSK (~(((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS)) +#define GLB_REG_GPIO_28_O GLB_REG_GPIO_28_O +#define GLB_REG_GPIO_28_O_POS (28U) +#define GLB_REG_GPIO_28_O_LEN (1U) +#define GLB_REG_GPIO_28_O_MSK (((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS) +#define GLB_REG_GPIO_28_O_UMSK (~(((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS)) +#define GLB_REG_GPIO_29_O GLB_REG_GPIO_29_O +#define GLB_REG_GPIO_29_O_POS (29U) +#define GLB_REG_GPIO_29_O_LEN (1U) +#define GLB_REG_GPIO_29_O_MSK (((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS) +#define GLB_REG_GPIO_29_O_UMSK (~(((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS)) +#define GLB_REG_GPIO_30_O GLB_REG_GPIO_30_O +#define GLB_REG_GPIO_30_O_POS (30U) +#define GLB_REG_GPIO_30_O_LEN (1U) +#define GLB_REG_GPIO_30_O_MSK (((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS) +#define GLB_REG_GPIO_30_O_UMSK (~(((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS)) +#define GLB_REG_GPIO_31_O GLB_REG_GPIO_31_O +#define GLB_REG_GPIO_31_O_POS (31U) +#define GLB_REG_GPIO_31_O_LEN (1U) +#define GLB_REG_GPIO_31_O_MSK (((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS) +#define GLB_REG_GPIO_31_O_UMSK (~(((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS)) + +/* 0x18C : GPIO_CFGCTL33 */ +#define GLB_GPIO_CFGCTL33_OFFSET (0x18C) + +/* 0x190 : GPIO_CFGCTL34 */ +#define GLB_GPIO_CFGCTL34_OFFSET (0x190) +#define GLB_REG_GPIO_0_OE GLB_REG_GPIO_0_OE +#define GLB_REG_GPIO_0_OE_POS (0U) +#define GLB_REG_GPIO_0_OE_LEN (1U) +#define GLB_REG_GPIO_0_OE_MSK (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS) +#define GLB_REG_GPIO_0_OE_UMSK (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)) +#define GLB_REG_GPIO_1_OE GLB_REG_GPIO_1_OE +#define GLB_REG_GPIO_1_OE_POS (1U) +#define GLB_REG_GPIO_1_OE_LEN (1U) +#define GLB_REG_GPIO_1_OE_MSK (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS) +#define GLB_REG_GPIO_1_OE_UMSK (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)) +#define GLB_REG_GPIO_2_OE GLB_REG_GPIO_2_OE +#define GLB_REG_GPIO_2_OE_POS (2U) +#define GLB_REG_GPIO_2_OE_LEN (1U) +#define GLB_REG_GPIO_2_OE_MSK (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS) +#define GLB_REG_GPIO_2_OE_UMSK (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)) +#define GLB_REG_GPIO_3_OE GLB_REG_GPIO_3_OE +#define GLB_REG_GPIO_3_OE_POS (3U) +#define GLB_REG_GPIO_3_OE_LEN (1U) +#define GLB_REG_GPIO_3_OE_MSK (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS) +#define GLB_REG_GPIO_3_OE_UMSK (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)) +#define GLB_REG_GPIO_4_OE GLB_REG_GPIO_4_OE +#define GLB_REG_GPIO_4_OE_POS (4U) +#define GLB_REG_GPIO_4_OE_LEN (1U) +#define GLB_REG_GPIO_4_OE_MSK (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS) +#define GLB_REG_GPIO_4_OE_UMSK (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)) +#define GLB_REG_GPIO_5_OE GLB_REG_GPIO_5_OE +#define GLB_REG_GPIO_5_OE_POS (5U) +#define GLB_REG_GPIO_5_OE_LEN (1U) +#define GLB_REG_GPIO_5_OE_MSK (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS) +#define GLB_REG_GPIO_5_OE_UMSK (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)) +#define GLB_REG_GPIO_6_OE GLB_REG_GPIO_6_OE +#define GLB_REG_GPIO_6_OE_POS (6U) +#define GLB_REG_GPIO_6_OE_LEN (1U) +#define GLB_REG_GPIO_6_OE_MSK (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS) +#define GLB_REG_GPIO_6_OE_UMSK (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)) +#define GLB_REG_GPIO_7_OE GLB_REG_GPIO_7_OE +#define GLB_REG_GPIO_7_OE_POS (7U) +#define GLB_REG_GPIO_7_OE_LEN (1U) +#define GLB_REG_GPIO_7_OE_MSK (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS) +#define GLB_REG_GPIO_7_OE_UMSK (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)) +#define GLB_REG_GPIO_8_OE GLB_REG_GPIO_8_OE +#define GLB_REG_GPIO_8_OE_POS (8U) +#define GLB_REG_GPIO_8_OE_LEN (1U) +#define GLB_REG_GPIO_8_OE_MSK (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS) +#define GLB_REG_GPIO_8_OE_UMSK (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)) +#define GLB_REG_GPIO_9_OE GLB_REG_GPIO_9_OE +#define GLB_REG_GPIO_9_OE_POS (9U) +#define GLB_REG_GPIO_9_OE_LEN (1U) +#define GLB_REG_GPIO_9_OE_MSK (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS) +#define GLB_REG_GPIO_9_OE_UMSK (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)) +#define GLB_REG_GPIO_10_OE GLB_REG_GPIO_10_OE +#define GLB_REG_GPIO_10_OE_POS (10U) +#define GLB_REG_GPIO_10_OE_LEN (1U) +#define GLB_REG_GPIO_10_OE_MSK (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS) +#define GLB_REG_GPIO_10_OE_UMSK (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)) +#define GLB_REG_GPIO_11_OE GLB_REG_GPIO_11_OE +#define GLB_REG_GPIO_11_OE_POS (11U) +#define GLB_REG_GPIO_11_OE_LEN (1U) +#define GLB_REG_GPIO_11_OE_MSK (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS) +#define GLB_REG_GPIO_11_OE_UMSK (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)) +#define GLB_REG_GPIO_12_OE GLB_REG_GPIO_12_OE +#define GLB_REG_GPIO_12_OE_POS (12U) +#define GLB_REG_GPIO_12_OE_LEN (1U) +#define GLB_REG_GPIO_12_OE_MSK (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS) +#define GLB_REG_GPIO_12_OE_UMSK (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)) +#define GLB_REG_GPIO_13_OE GLB_REG_GPIO_13_OE +#define GLB_REG_GPIO_13_OE_POS (13U) +#define GLB_REG_GPIO_13_OE_LEN (1U) +#define GLB_REG_GPIO_13_OE_MSK (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS) +#define GLB_REG_GPIO_13_OE_UMSK (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)) +#define GLB_REG_GPIO_14_OE GLB_REG_GPIO_14_OE +#define GLB_REG_GPIO_14_OE_POS (14U) +#define GLB_REG_GPIO_14_OE_LEN (1U) +#define GLB_REG_GPIO_14_OE_MSK (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS) +#define GLB_REG_GPIO_14_OE_UMSK (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)) +#define GLB_REG_GPIO_15_OE GLB_REG_GPIO_15_OE +#define GLB_REG_GPIO_15_OE_POS (15U) +#define GLB_REG_GPIO_15_OE_LEN (1U) +#define GLB_REG_GPIO_15_OE_MSK (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS) +#define GLB_REG_GPIO_15_OE_UMSK (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)) +#define GLB_REG_GPIO_16_OE GLB_REG_GPIO_16_OE +#define GLB_REG_GPIO_16_OE_POS (16U) +#define GLB_REG_GPIO_16_OE_LEN (1U) +#define GLB_REG_GPIO_16_OE_MSK (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS) +#define GLB_REG_GPIO_16_OE_UMSK (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)) +#define GLB_REG_GPIO_17_OE GLB_REG_GPIO_17_OE +#define GLB_REG_GPIO_17_OE_POS (17U) +#define GLB_REG_GPIO_17_OE_LEN (1U) +#define GLB_REG_GPIO_17_OE_MSK (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS) +#define GLB_REG_GPIO_17_OE_UMSK (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)) +#define GLB_REG_GPIO_18_OE GLB_REG_GPIO_18_OE +#define GLB_REG_GPIO_18_OE_POS (18U) +#define GLB_REG_GPIO_18_OE_LEN (1U) +#define GLB_REG_GPIO_18_OE_MSK (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS) +#define GLB_REG_GPIO_18_OE_UMSK (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)) +#define GLB_REG_GPIO_19_OE GLB_REG_GPIO_19_OE +#define GLB_REG_GPIO_19_OE_POS (19U) +#define GLB_REG_GPIO_19_OE_LEN (1U) +#define GLB_REG_GPIO_19_OE_MSK (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS) +#define GLB_REG_GPIO_19_OE_UMSK (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)) +#define GLB_REG_GPIO_20_OE GLB_REG_GPIO_20_OE +#define GLB_REG_GPIO_20_OE_POS (20U) +#define GLB_REG_GPIO_20_OE_LEN (1U) +#define GLB_REG_GPIO_20_OE_MSK (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS) +#define GLB_REG_GPIO_20_OE_UMSK (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)) +#define GLB_REG_GPIO_21_OE GLB_REG_GPIO_21_OE +#define GLB_REG_GPIO_21_OE_POS (21U) +#define GLB_REG_GPIO_21_OE_LEN (1U) +#define GLB_REG_GPIO_21_OE_MSK (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS) +#define GLB_REG_GPIO_21_OE_UMSK (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)) +#define GLB_REG_GPIO_22_OE GLB_REG_GPIO_22_OE +#define GLB_REG_GPIO_22_OE_POS (22U) +#define GLB_REG_GPIO_22_OE_LEN (1U) +#define GLB_REG_GPIO_22_OE_MSK (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS) +#define GLB_REG_GPIO_22_OE_UMSK (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)) +#define GLB_REG_GPIO_23_OE GLB_REG_GPIO_23_OE +#define GLB_REG_GPIO_23_OE_POS (23U) +#define GLB_REG_GPIO_23_OE_LEN (1U) +#define GLB_REG_GPIO_23_OE_MSK (((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS) +#define GLB_REG_GPIO_23_OE_UMSK (~(((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS)) +#define GLB_REG_GPIO_24_OE GLB_REG_GPIO_24_OE +#define GLB_REG_GPIO_24_OE_POS (24U) +#define GLB_REG_GPIO_24_OE_LEN (1U) +#define GLB_REG_GPIO_24_OE_MSK (((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS) +#define GLB_REG_GPIO_24_OE_UMSK (~(((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS)) +#define GLB_REG_GPIO_25_OE GLB_REG_GPIO_25_OE +#define GLB_REG_GPIO_25_OE_POS (25U) +#define GLB_REG_GPIO_25_OE_LEN (1U) +#define GLB_REG_GPIO_25_OE_MSK (((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS) +#define GLB_REG_GPIO_25_OE_UMSK (~(((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS)) +#define GLB_REG_GPIO_26_OE GLB_REG_GPIO_26_OE +#define GLB_REG_GPIO_26_OE_POS (26U) +#define GLB_REG_GPIO_26_OE_LEN (1U) +#define GLB_REG_GPIO_26_OE_MSK (((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS) +#define GLB_REG_GPIO_26_OE_UMSK (~(((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS)) +#define GLB_REG_GPIO_27_OE GLB_REG_GPIO_27_OE +#define GLB_REG_GPIO_27_OE_POS (27U) +#define GLB_REG_GPIO_27_OE_LEN (1U) +#define GLB_REG_GPIO_27_OE_MSK (((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS) +#define GLB_REG_GPIO_27_OE_UMSK (~(((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS)) +#define GLB_REG_GPIO_28_OE GLB_REG_GPIO_28_OE +#define GLB_REG_GPIO_28_OE_POS (28U) +#define GLB_REG_GPIO_28_OE_LEN (1U) +#define GLB_REG_GPIO_28_OE_MSK (((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS) +#define GLB_REG_GPIO_28_OE_UMSK (~(((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS)) +#define GLB_REG_GPIO_29_OE GLB_REG_GPIO_29_OE +#define GLB_REG_GPIO_29_OE_POS (29U) +#define GLB_REG_GPIO_29_OE_LEN (1U) +#define GLB_REG_GPIO_29_OE_MSK (((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS) +#define GLB_REG_GPIO_29_OE_UMSK (~(((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS)) +#define GLB_REG_GPIO_30_OE GLB_REG_GPIO_30_OE +#define GLB_REG_GPIO_30_OE_POS (30U) +#define GLB_REG_GPIO_30_OE_LEN (1U) +#define GLB_REG_GPIO_30_OE_MSK (((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS) +#define GLB_REG_GPIO_30_OE_UMSK (~(((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS)) +#define GLB_REG_GPIO_31_OE GLB_REG_GPIO_31_OE +#define GLB_REG_GPIO_31_OE_POS (31U) +#define GLB_REG_GPIO_31_OE_LEN (1U) +#define GLB_REG_GPIO_31_OE_MSK (((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS) +#define GLB_REG_GPIO_31_OE_UMSK (~(((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS)) + +/* 0x194 : GPIO_CFGCTL35 */ +#define GLB_GPIO_CFGCTL35_OFFSET (0x194) + +/* 0x1A0 : GPIO_INT_MASK1 */ +#define GLB_GPIO_INT_MASK1_OFFSET (0x1A0) +#define GLB_REG_GPIO_INT_MASK1 GLB_REG_GPIO_INT_MASK1 +#define GLB_REG_GPIO_INT_MASK1_POS (0U) +#define GLB_REG_GPIO_INT_MASK1_LEN (32U) +#define GLB_REG_GPIO_INT_MASK1_MSK (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS) +#define GLB_REG_GPIO_INT_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)) + +/* 0x1A8 : GPIO_INT_STAT1 */ +#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8) +#define GLB_GPIO_INT_STAT1 GLB_GPIO_INT_STAT1 +#define GLB_GPIO_INT_STAT1_POS (0U) +#define GLB_GPIO_INT_STAT1_LEN (32U) +#define GLB_GPIO_INT_STAT1_MSK (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS) +#define GLB_GPIO_INT_STAT1_UMSK (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)) + +/* 0x1B0 : GPIO_INT_CLR1 */ +#define GLB_GPIO_INT_CLR1_OFFSET (0x1B0) +#define GLB_REG_GPIO_INT_CLR1 GLB_REG_GPIO_INT_CLR1 +#define GLB_REG_GPIO_INT_CLR1_POS (0U) +#define GLB_REG_GPIO_INT_CLR1_LEN (32U) +#define GLB_REG_GPIO_INT_CLR1_MSK (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS) +#define GLB_REG_GPIO_INT_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)) + +/* 0x1C0 : GPIO_INT_MODE_SET1 */ +#define GLB_GPIO_INT_MODE_SET1_OFFSET (0x1C0) +#define GLB_REG_GPIO_INT_MODE_SET1 GLB_REG_GPIO_INT_MODE_SET1 +#define GLB_REG_GPIO_INT_MODE_SET1_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET1_LEN (30U) +#define GLB_REG_GPIO_INT_MODE_SET1_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS) +#define GLB_REG_GPIO_INT_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS)) + +/* 0x1C4 : GPIO_INT_MODE_SET2 */ +#define GLB_GPIO_INT_MODE_SET2_OFFSET (0x1C4) +#define GLB_REG_GPIO_INT_MODE_SET2 GLB_REG_GPIO_INT_MODE_SET2 +#define GLB_REG_GPIO_INT_MODE_SET2_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET2_LEN (30U) +#define GLB_REG_GPIO_INT_MODE_SET2_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS) +#define GLB_REG_GPIO_INT_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS)) + +/* 0x1C8 : GPIO_INT_MODE_SET3 */ +#define GLB_GPIO_INT_MODE_SET3_OFFSET (0x1C8) +#define GLB_REG_GPIO_INT_MODE_SET3 GLB_REG_GPIO_INT_MODE_SET3 +#define GLB_REG_GPIO_INT_MODE_SET3_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET3_LEN (30U) +#define GLB_REG_GPIO_INT_MODE_SET3_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS) +#define GLB_REG_GPIO_INT_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS)) + +/* 0x1CC : GPIO_INT_MODE_SET4 */ +#define GLB_GPIO_INT_MODE_SET4_OFFSET (0x1CC) +#define GLB_REG_GPIO_INT_MODE_SET4 GLB_REG_GPIO_INT_MODE_SET4 +#define GLB_REG_GPIO_INT_MODE_SET4_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET4_LEN (6U) +#define GLB_REG_GPIO_INT_MODE_SET4_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET4_POS) +#define GLB_REG_GPIO_INT_MODE_SET4_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET4_POS)) + +/* 0x1D0 : GPIO_INT2_MASK1 */ +#define GLB_GPIO_INT2_MASK1_OFFSET (0x1D0) +#define GLB_REG_GPIO_INT2_MASK1 GLB_REG_GPIO_INT2_MASK1 +#define GLB_REG_GPIO_INT2_MASK1_POS (0U) +#define GLB_REG_GPIO_INT2_MASK1_LEN (32U) +#define GLB_REG_GPIO_INT2_MASK1_MSK (((1U << GLB_REG_GPIO_INT2_MASK1_LEN) - 1) << GLB_REG_GPIO_INT2_MASK1_POS) +#define GLB_REG_GPIO_INT2_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT2_MASK1_LEN) - 1) << GLB_REG_GPIO_INT2_MASK1_POS)) + +/* 0x1D4 : GPIO_INT2_STAT1 */ +#define GLB_GPIO_INT2_STAT1_OFFSET (0x1D4) +#define GLB_GPIO_INT2_STAT1 GLB_GPIO_INT2_STAT1 +#define GLB_GPIO_INT2_STAT1_POS (0U) +#define GLB_GPIO_INT2_STAT1_LEN (32U) +#define GLB_GPIO_INT2_STAT1_MSK (((1U << GLB_GPIO_INT2_STAT1_LEN) - 1) << GLB_GPIO_INT2_STAT1_POS) +#define GLB_GPIO_INT2_STAT1_UMSK (~(((1U << GLB_GPIO_INT2_STAT1_LEN) - 1) << GLB_GPIO_INT2_STAT1_POS)) + +/* 0x1D8 : GPIO_INT2_CLR1 */ +#define GLB_GPIO_INT2_CLR1_OFFSET (0x1D8) +#define GLB_REG_GPIO_INT2_CLR1 GLB_REG_GPIO_INT2_CLR1 +#define GLB_REG_GPIO_INT2_CLR1_POS (0U) +#define GLB_REG_GPIO_INT2_CLR1_LEN (32U) +#define GLB_REG_GPIO_INT2_CLR1_MSK (((1U << GLB_REG_GPIO_INT2_CLR1_LEN) - 1) << GLB_REG_GPIO_INT2_CLR1_POS) +#define GLB_REG_GPIO_INT2_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT2_CLR1_LEN) - 1) << GLB_REG_GPIO_INT2_CLR1_POS)) + +/* 0x1DC : GPIO_INT2_MODE_SET1 */ +#define GLB_GPIO_INT2_MODE_SET1_OFFSET (0x1DC) +#define GLB_REG_GPIO_INT2_MODE_SET1 GLB_REG_GPIO_INT2_MODE_SET1 +#define GLB_REG_GPIO_INT2_MODE_SET1_POS (0U) +#define GLB_REG_GPIO_INT2_MODE_SET1_LEN (30U) +#define GLB_REG_GPIO_INT2_MODE_SET1_MSK (((1U << GLB_REG_GPIO_INT2_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET1_POS) +#define GLB_REG_GPIO_INT2_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET1_POS)) + +/* 0x1E0 : GPIO_INT2_MODE_SET2 */ +#define GLB_GPIO_INT2_MODE_SET2_OFFSET (0x1E0) +#define GLB_REG_GPIO_INT2_MODE_SET2 GLB_REG_GPIO_INT2_MODE_SET2 +#define GLB_REG_GPIO_INT2_MODE_SET2_POS (0U) +#define GLB_REG_GPIO_INT2_MODE_SET2_LEN (30U) +#define GLB_REG_GPIO_INT2_MODE_SET2_MSK (((1U << GLB_REG_GPIO_INT2_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET2_POS) +#define GLB_REG_GPIO_INT2_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET2_POS)) + +/* 0x1E4 : GPIO_INT2_MODE_SET3 */ +#define GLB_GPIO_INT2_MODE_SET3_OFFSET (0x1E4) +#define GLB_REG_GPIO_INT2_MODE_SET3 GLB_REG_GPIO_INT2_MODE_SET3 +#define GLB_REG_GPIO_INT2_MODE_SET3_POS (0U) +#define GLB_REG_GPIO_INT2_MODE_SET3_LEN (30U) +#define GLB_REG_GPIO_INT2_MODE_SET3_MSK (((1U << GLB_REG_GPIO_INT2_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET3_POS) +#define GLB_REG_GPIO_INT2_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET3_POS)) + +/* 0x1E8 : GPIO_INT2_MODE_SET4 */ +#define GLB_GPIO_INT2_MODE_SET4_OFFSET (0x1E8) +#define GLB_REG_GPIO_INT2_MODE_SET4 GLB_REG_GPIO_INT2_MODE_SET4 +#define GLB_REG_GPIO_INT2_MODE_SET4_POS (0U) +#define GLB_REG_GPIO_INT2_MODE_SET4_LEN (6U) +#define GLB_REG_GPIO_INT2_MODE_SET4_MSK (((1U << GLB_REG_GPIO_INT2_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET4_POS) +#define GLB_REG_GPIO_INT2_MODE_SET4_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET4_POS)) + +/* 0x200 : dll */ +#define GLB_DLL_OFFSET (0x200) +#define GLB_DTEST_EN_DLL_REFCLK GLB_DTEST_EN_DLL_REFCLK +#define GLB_DTEST_EN_DLL_REFCLK_POS (0U) +#define GLB_DTEST_EN_DLL_REFCLK_LEN (1U) +#define GLB_DTEST_EN_DLL_REFCLK_MSK (((1U << GLB_DTEST_EN_DLL_REFCLK_LEN) - 1) << GLB_DTEST_EN_DLL_REFCLK_POS) +#define GLB_DTEST_EN_DLL_REFCLK_UMSK (~(((1U << GLB_DTEST_EN_DLL_REFCLK_LEN) - 1) << GLB_DTEST_EN_DLL_REFCLK_POS)) +#define GLB_DTEST_EN_DLL_OUTCLK GLB_DTEST_EN_DLL_OUTCLK +#define GLB_DTEST_EN_DLL_OUTCLK_POS (1U) +#define GLB_DTEST_EN_DLL_OUTCLK_LEN (1U) +#define GLB_DTEST_EN_DLL_OUTCLK_MSK (((1U << GLB_DTEST_EN_DLL_OUTCLK_LEN) - 1) << GLB_DTEST_EN_DLL_OUTCLK_POS) +#define GLB_DTEST_EN_DLL_OUTCLK_UMSK (~(((1U << GLB_DTEST_EN_DLL_OUTCLK_LEN) - 1) << GLB_DTEST_EN_DLL_OUTCLK_POS)) +#define GLB_TEN_DLL GLB_TEN_DLL +#define GLB_TEN_DLL_POS (2U) +#define GLB_TEN_DLL_LEN (1U) +#define GLB_TEN_DLL_MSK (((1U << GLB_TEN_DLL_LEN) - 1) << GLB_TEN_DLL_POS) +#define GLB_TEN_DLL_UMSK (~(((1U << GLB_TEN_DLL_LEN) - 1) << GLB_TEN_DLL_POS)) +#define GLB_DLL_CLK_MMDIV_EN GLB_DLL_CLK_MMDIV_EN +#define GLB_DLL_CLK_MMDIV_EN_POS (3U) +#define GLB_DLL_CLK_MMDIV_EN_LEN (1U) +#define GLB_DLL_CLK_MMDIV_EN_MSK (((1U << GLB_DLL_CLK_MMDIV_EN_LEN) - 1) << GLB_DLL_CLK_MMDIV_EN_POS) +#define GLB_DLL_CLK_MMDIV_EN_UMSK (~(((1U << GLB_DLL_CLK_MMDIV_EN_LEN) - 1) << GLB_DLL_CLK_MMDIV_EN_POS)) +#define GLB_DLL_CLK_288M_EN GLB_DLL_CLK_288M_EN +#define GLB_DLL_CLK_288M_EN_POS (4U) +#define GLB_DLL_CLK_288M_EN_LEN (1U) +#define GLB_DLL_CLK_288M_EN_MSK (((1U << GLB_DLL_CLK_288M_EN_LEN) - 1) << GLB_DLL_CLK_288M_EN_POS) +#define GLB_DLL_CLK_288M_EN_UMSK (~(((1U << GLB_DLL_CLK_288M_EN_LEN) - 1) << GLB_DLL_CLK_288M_EN_POS)) +#define GLB_DLL_CLK_144M_EN GLB_DLL_CLK_144M_EN +#define GLB_DLL_CLK_144M_EN_POS (5U) +#define GLB_DLL_CLK_144M_EN_LEN (1U) +#define GLB_DLL_CLK_144M_EN_MSK (((1U << GLB_DLL_CLK_144M_EN_LEN) - 1) << GLB_DLL_CLK_144M_EN_POS) +#define GLB_DLL_CLK_144M_EN_UMSK (~(((1U << GLB_DLL_CLK_144M_EN_LEN) - 1) << GLB_DLL_CLK_144M_EN_POS)) +#define GLB_DLL_CLK_96M_EN GLB_DLL_CLK_96M_EN +#define GLB_DLL_CLK_96M_EN_POS (6U) +#define GLB_DLL_CLK_96M_EN_LEN (1U) +#define GLB_DLL_CLK_96M_EN_MSK (((1U << GLB_DLL_CLK_96M_EN_LEN) - 1) << GLB_DLL_CLK_96M_EN_POS) +#define GLB_DLL_CLK_96M_EN_UMSK (~(((1U << GLB_DLL_CLK_96M_EN_LEN) - 1) << GLB_DLL_CLK_96M_EN_POS)) +#define GLB_DLL_CLK_57P6M_EN GLB_DLL_CLK_57P6M_EN +#define GLB_DLL_CLK_57P6M_EN_POS (7U) +#define GLB_DLL_CLK_57P6M_EN_LEN (1U) +#define GLB_DLL_CLK_57P6M_EN_MSK (((1U << GLB_DLL_CLK_57P6M_EN_LEN) - 1) << GLB_DLL_CLK_57P6M_EN_POS) +#define GLB_DLL_CLK_57P6M_EN_UMSK (~(((1U << GLB_DLL_CLK_57P6M_EN_LEN) - 1) << GLB_DLL_CLK_57P6M_EN_POS)) +#define GLB_DLL_VCTRL_SEL GLB_DLL_VCTRL_SEL +#define GLB_DLL_VCTRL_SEL_POS (8U) +#define GLB_DLL_VCTRL_SEL_LEN (3U) +#define GLB_DLL_VCTRL_SEL_MSK (((1U << GLB_DLL_VCTRL_SEL_LEN) - 1) << GLB_DLL_VCTRL_SEL_POS) +#define GLB_DLL_VCTRL_SEL_UMSK (~(((1U << GLB_DLL_VCTRL_SEL_LEN) - 1) << GLB_DLL_VCTRL_SEL_POS)) +#define GLB_DLL_PRECHG_SEL GLB_DLL_PRECHG_SEL +#define GLB_DLL_PRECHG_SEL_POS (12U) +#define GLB_DLL_PRECHG_SEL_LEN (1U) +#define GLB_DLL_PRECHG_SEL_MSK (((1U << GLB_DLL_PRECHG_SEL_LEN) - 1) << GLB_DLL_PRECHG_SEL_POS) +#define GLB_DLL_PRECHG_SEL_UMSK (~(((1U << GLB_DLL_PRECHG_SEL_LEN) - 1) << GLB_DLL_PRECHG_SEL_POS)) +#define GLB_DLL_PRECHG_REG GLB_DLL_PRECHG_REG +#define GLB_DLL_PRECHG_REG_POS (13U) +#define GLB_DLL_PRECHG_REG_LEN (1U) +#define GLB_DLL_PRECHG_REG_MSK (((1U << GLB_DLL_PRECHG_REG_LEN) - 1) << GLB_DLL_PRECHG_REG_POS) +#define GLB_DLL_PRECHG_REG_UMSK (~(((1U << GLB_DLL_PRECHG_REG_LEN) - 1) << GLB_DLL_PRECHG_REG_POS)) +#define GLB_DLL_PRECHG_EN GLB_DLL_PRECHG_EN +#define GLB_DLL_PRECHG_EN_POS (14U) +#define GLB_DLL_PRECHG_EN_LEN (1U) +#define GLB_DLL_PRECHG_EN_MSK (((1U << GLB_DLL_PRECHG_EN_LEN) - 1) << GLB_DLL_PRECHG_EN_POS) +#define GLB_DLL_PRECHG_EN_UMSK (~(((1U << GLB_DLL_PRECHG_EN_LEN) - 1) << GLB_DLL_PRECHG_EN_POS)) +#define GLB_DLL_VCTRL_FORCE_EN GLB_DLL_VCTRL_FORCE_EN +#define GLB_DLL_VCTRL_FORCE_EN_POS (15U) +#define GLB_DLL_VCTRL_FORCE_EN_LEN (1U) +#define GLB_DLL_VCTRL_FORCE_EN_MSK (((1U << GLB_DLL_VCTRL_FORCE_EN_LEN) - 1) << GLB_DLL_VCTRL_FORCE_EN_POS) +#define GLB_DLL_VCTRL_FORCE_EN_UMSK (~(((1U << GLB_DLL_VCTRL_FORCE_EN_LEN) - 1) << GLB_DLL_VCTRL_FORCE_EN_POS)) +#define GLB_DLL_POST_DIV GLB_DLL_POST_DIV +#define GLB_DLL_POST_DIV_POS (16U) +#define GLB_DLL_POST_DIV_LEN (4U) +#define GLB_DLL_POST_DIV_MSK (((1U << GLB_DLL_POST_DIV_LEN) - 1) << GLB_DLL_POST_DIV_POS) +#define GLB_DLL_POST_DIV_UMSK (~(((1U << GLB_DLL_POST_DIV_LEN) - 1) << GLB_DLL_POST_DIV_POS)) +#define GLB_DLL_DELAY_SEL GLB_DLL_DELAY_SEL +#define GLB_DLL_DELAY_SEL_POS (20U) +#define GLB_DLL_DELAY_SEL_LEN (2U) +#define GLB_DLL_DELAY_SEL_MSK (((1U << GLB_DLL_DELAY_SEL_LEN) - 1) << GLB_DLL_DELAY_SEL_POS) +#define GLB_DLL_DELAY_SEL_UMSK (~(((1U << GLB_DLL_DELAY_SEL_LEN) - 1) << GLB_DLL_DELAY_SEL_POS)) +#define GLB_DLL_CP_OP_EN GLB_DLL_CP_OP_EN +#define GLB_DLL_CP_OP_EN_POS (22U) +#define GLB_DLL_CP_OP_EN_LEN (1U) +#define GLB_DLL_CP_OP_EN_MSK (((1U << GLB_DLL_CP_OP_EN_LEN) - 1) << GLB_DLL_CP_OP_EN_POS) +#define GLB_DLL_CP_OP_EN_UMSK (~(((1U << GLB_DLL_CP_OP_EN_LEN) - 1) << GLB_DLL_CP_OP_EN_POS)) +#define GLB_DLL_CP_HIZ GLB_DLL_CP_HIZ +#define GLB_DLL_CP_HIZ_POS (23U) +#define GLB_DLL_CP_HIZ_LEN (1U) +#define GLB_DLL_CP_HIZ_MSK (((1U << GLB_DLL_CP_HIZ_LEN) - 1) << GLB_DLL_CP_HIZ_POS) +#define GLB_DLL_CP_HIZ_UMSK (~(((1U << GLB_DLL_CP_HIZ_LEN) - 1) << GLB_DLL_CP_HIZ_POS)) +#define GLB_DLL_REFCLK_SEL GLB_DLL_REFCLK_SEL +#define GLB_DLL_REFCLK_SEL_POS (28U) +#define GLB_DLL_REFCLK_SEL_LEN (1U) +#define GLB_DLL_REFCLK_SEL_MSK (((1U << GLB_DLL_REFCLK_SEL_LEN) - 1) << GLB_DLL_REFCLK_SEL_POS) +#define GLB_DLL_REFCLK_SEL_UMSK (~(((1U << GLB_DLL_REFCLK_SEL_LEN) - 1) << GLB_DLL_REFCLK_SEL_POS)) +#define GLB_DLL_RESET GLB_DLL_RESET +#define GLB_DLL_RESET_POS (29U) +#define GLB_DLL_RESET_LEN (1U) +#define GLB_DLL_RESET_MSK (((1U << GLB_DLL_RESET_LEN) - 1) << GLB_DLL_RESET_POS) +#define GLB_DLL_RESET_UMSK (~(((1U << GLB_DLL_RESET_LEN) - 1) << GLB_DLL_RESET_POS)) +#define GLB_PU_DLL GLB_PU_DLL +#define GLB_PU_DLL_POS (30U) +#define GLB_PU_DLL_LEN (1U) +#define GLB_PU_DLL_MSK (((1U << GLB_PU_DLL_LEN) - 1) << GLB_PU_DLL_POS) +#define GLB_PU_DLL_UMSK (~(((1U << GLB_PU_DLL_LEN) - 1) << GLB_PU_DLL_POS)) +#define GLB_PPU_DLL GLB_PPU_DLL +#define GLB_PPU_DLL_POS (31U) +#define GLB_PPU_DLL_LEN (1U) +#define GLB_PPU_DLL_MSK (((1U << GLB_PPU_DLL_LEN) - 1) << GLB_PPU_DLL_POS) +#define GLB_PPU_DLL_UMSK (~(((1U << GLB_PPU_DLL_LEN) - 1) << GLB_PPU_DLL_POS)) + +/* 0x224 : led_driver */ +#define GLB_LED_DRIVER_OFFSET (0x224) +#define GLB_LED_DIN_REG GLB_LED_DIN_REG +#define GLB_LED_DIN_REG_POS (0U) +#define GLB_LED_DIN_REG_LEN (1U) +#define GLB_LED_DIN_REG_MSK (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS) +#define GLB_LED_DIN_REG_UMSK (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)) +#define GLB_LED_DIN_SEL GLB_LED_DIN_SEL +#define GLB_LED_DIN_SEL_POS (1U) +#define GLB_LED_DIN_SEL_LEN (1U) +#define GLB_LED_DIN_SEL_MSK (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS) +#define GLB_LED_DIN_SEL_UMSK (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)) +#define GLB_LED_DIN_POLARITY_SEL GLB_LED_DIN_POLARITY_SEL +#define GLB_LED_DIN_POLARITY_SEL_POS (2U) +#define GLB_LED_DIN_POLARITY_SEL_LEN (1U) +#define GLB_LED_DIN_POLARITY_SEL_MSK (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS) +#define GLB_LED_DIN_POLARITY_SEL_UMSK (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)) +#define GLB_LEDDRV_IBIAS GLB_LEDDRV_IBIAS +#define GLB_LEDDRV_IBIAS_POS (4U) +#define GLB_LEDDRV_IBIAS_LEN (4U) +#define GLB_LEDDRV_IBIAS_MSK (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS) +#define GLB_LEDDRV_IBIAS_UMSK (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)) +#define GLB_IR_RX_GPIO_SEL GLB_IR_RX_GPIO_SEL +#define GLB_IR_RX_GPIO_SEL_POS (8U) +#define GLB_IR_RX_GPIO_SEL_LEN (4U) +#define GLB_IR_RX_GPIO_SEL_MSK (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS) +#define GLB_IR_RX_GPIO_SEL_UMSK (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)) +#define GLB_LEDDRV_OUT_EN GLB_LEDDRV_OUT_EN +#define GLB_LEDDRV_OUT_EN_POS (28U) +#define GLB_LEDDRV_OUT_EN_LEN (2U) +#define GLB_LEDDRV_OUT_EN_MSK (((1U << GLB_LEDDRV_OUT_EN_LEN) - 1) << GLB_LEDDRV_OUT_EN_POS) +#define GLB_LEDDRV_OUT_EN_UMSK (~(((1U << GLB_LEDDRV_OUT_EN_LEN) - 1) << GLB_LEDDRV_OUT_EN_POS)) +#define GLB_PU_LEDDRV GLB_PU_LEDDRV +#define GLB_PU_LEDDRV_POS (31U) +#define GLB_PU_LEDDRV_LEN (1U) +#define GLB_PU_LEDDRV_MSK (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS) +#define GLB_PU_LEDDRV_UMSK (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)) + +/* 0x228 : usb_xcvr */ +#define GLB_USB_XCVR_OFFSET (0x228) +#define GLB_USB_LDO_VFB GLB_USB_LDO_VFB +#define GLB_USB_LDO_VFB_POS (0U) +#define GLB_USB_LDO_VFB_LEN (3U) +#define GLB_USB_LDO_VFB_MSK (((1U << GLB_USB_LDO_VFB_LEN) - 1) << GLB_USB_LDO_VFB_POS) +#define GLB_USB_LDO_VFB_UMSK (~(((1U << GLB_USB_LDO_VFB_LEN) - 1) << GLB_USB_LDO_VFB_POS)) +#define GLB_PU_USB_LDO GLB_PU_USB_LDO +#define GLB_PU_USB_LDO_POS (3U) +#define GLB_PU_USB_LDO_LEN (1U) +#define GLB_PU_USB_LDO_MSK (((1U << GLB_PU_USB_LDO_LEN) - 1) << GLB_PU_USB_LDO_POS) +#define GLB_PU_USB_LDO_UMSK (~(((1U << GLB_PU_USB_LDO_LEN) - 1) << GLB_PU_USB_LDO_POS)) +#define GLB_USB_ROUT_NMOS GLB_USB_ROUT_NMOS +#define GLB_USB_ROUT_NMOS_POS (4U) +#define GLB_USB_ROUT_NMOS_LEN (3U) +#define GLB_USB_ROUT_NMOS_MSK (((1U << GLB_USB_ROUT_NMOS_LEN) - 1) << GLB_USB_ROUT_NMOS_POS) +#define GLB_USB_ROUT_NMOS_UMSK (~(((1U << GLB_USB_ROUT_NMOS_LEN) - 1) << GLB_USB_ROUT_NMOS_POS)) +#define GLB_USB_ROUT_PMOS GLB_USB_ROUT_PMOS +#define GLB_USB_ROUT_PMOS_POS (8U) +#define GLB_USB_ROUT_PMOS_LEN (3U) +#define GLB_USB_ROUT_PMOS_MSK (((1U << GLB_USB_ROUT_PMOS_LEN) - 1) << GLB_USB_ROUT_PMOS_POS) +#define GLB_USB_ROUT_PMOS_UMSK (~(((1U << GLB_USB_ROUT_PMOS_LEN) - 1) << GLB_USB_ROUT_PMOS_POS)) +#define GLB_USB_OEB_SEL GLB_USB_OEB_SEL +#define GLB_USB_OEB_SEL_POS (12U) +#define GLB_USB_OEB_SEL_LEN (1U) +#define GLB_USB_OEB_SEL_MSK (((1U << GLB_USB_OEB_SEL_LEN) - 1) << GLB_USB_OEB_SEL_POS) +#define GLB_USB_OEB_SEL_UMSK (~(((1U << GLB_USB_OEB_SEL_LEN) - 1) << GLB_USB_OEB_SEL_POS)) +#define GLB_USB_OEB_REG GLB_USB_OEB_REG +#define GLB_USB_OEB_REG_POS (13U) +#define GLB_USB_OEB_REG_LEN (1U) +#define GLB_USB_OEB_REG_MSK (((1U << GLB_USB_OEB_REG_LEN) - 1) << GLB_USB_OEB_REG_POS) +#define GLB_USB_OEB_REG_UMSK (~(((1U << GLB_USB_OEB_REG_LEN) - 1) << GLB_USB_OEB_REG_POS)) +#define GLB_USB_OEB GLB_USB_OEB +#define GLB_USB_OEB_POS (14U) +#define GLB_USB_OEB_LEN (1U) +#define GLB_USB_OEB_MSK (((1U << GLB_USB_OEB_LEN) - 1) << GLB_USB_OEB_POS) +#define GLB_USB_OEB_UMSK (~(((1U << GLB_USB_OEB_LEN) - 1) << GLB_USB_OEB_POS)) +#define GLB_USB_DATA_CONVERT GLB_USB_DATA_CONVERT +#define GLB_USB_DATA_CONVERT_POS (16U) +#define GLB_USB_DATA_CONVERT_LEN (1U) +#define GLB_USB_DATA_CONVERT_MSK (((1U << GLB_USB_DATA_CONVERT_LEN) - 1) << GLB_USB_DATA_CONVERT_POS) +#define GLB_USB_DATA_CONVERT_UMSK (~(((1U << GLB_USB_DATA_CONVERT_LEN) - 1) << GLB_USB_DATA_CONVERT_POS)) +#define GLB_USB_ENUM GLB_USB_ENUM +#define GLB_USB_ENUM_POS (20U) +#define GLB_USB_ENUM_LEN (1U) +#define GLB_USB_ENUM_MSK (((1U << GLB_USB_ENUM_LEN) - 1) << GLB_USB_ENUM_POS) +#define GLB_USB_ENUM_UMSK (~(((1U << GLB_USB_ENUM_LEN) - 1) << GLB_USB_ENUM_POS)) +#define GLB_USB_SPD GLB_USB_SPD +#define GLB_USB_SPD_POS (21U) +#define GLB_USB_SPD_LEN (1U) +#define GLB_USB_SPD_MSK (((1U << GLB_USB_SPD_LEN) - 1) << GLB_USB_SPD_POS) +#define GLB_USB_SPD_UMSK (~(((1U << GLB_USB_SPD_LEN) - 1) << GLB_USB_SPD_POS)) +#define GLB_USB_SUS GLB_USB_SUS +#define GLB_USB_SUS_POS (22U) +#define GLB_USB_SUS_LEN (1U) +#define GLB_USB_SUS_MSK (((1U << GLB_USB_SUS_LEN) - 1) << GLB_USB_SUS_POS) +#define GLB_USB_SUS_UMSK (~(((1U << GLB_USB_SUS_LEN) - 1) << GLB_USB_SUS_POS)) +#define GLB_PU_USB GLB_PU_USB +#define GLB_PU_USB_POS (23U) +#define GLB_PU_USB_LEN (1U) +#define GLB_PU_USB_MSK (((1U << GLB_PU_USB_LEN) - 1) << GLB_PU_USB_POS) +#define GLB_PU_USB_UMSK (~(((1U << GLB_PU_USB_LEN) - 1) << GLB_PU_USB_POS)) +#define GLB_USB_BD GLB_USB_BD +#define GLB_USB_BD_POS (24U) +#define GLB_USB_BD_LEN (1U) +#define GLB_USB_BD_MSK (((1U << GLB_USB_BD_LEN) - 1) << GLB_USB_BD_POS) +#define GLB_USB_BD_UMSK (~(((1U << GLB_USB_BD_LEN) - 1) << GLB_USB_BD_POS)) +#define GLB_USB_VIM GLB_USB_VIM +#define GLB_USB_VIM_POS (25U) +#define GLB_USB_VIM_LEN (1U) +#define GLB_USB_VIM_MSK (((1U << GLB_USB_VIM_LEN) - 1) << GLB_USB_VIM_POS) +#define GLB_USB_VIM_UMSK (~(((1U << GLB_USB_VIM_LEN) - 1) << GLB_USB_VIM_POS)) +#define GLB_USB_VIP GLB_USB_VIP +#define GLB_USB_VIP_POS (26U) +#define GLB_USB_VIP_LEN (1U) +#define GLB_USB_VIP_MSK (((1U << GLB_USB_VIP_LEN) - 1) << GLB_USB_VIP_POS) +#define GLB_USB_VIP_UMSK (~(((1U << GLB_USB_VIP_LEN) - 1) << GLB_USB_VIP_POS)) +#define GLB_USB_RCV GLB_USB_RCV +#define GLB_USB_RCV_POS (27U) +#define GLB_USB_RCV_LEN (1U) +#define GLB_USB_RCV_MSK (((1U << GLB_USB_RCV_LEN) - 1) << GLB_USB_RCV_POS) +#define GLB_USB_RCV_UMSK (~(((1U << GLB_USB_RCV_LEN) - 1) << GLB_USB_RCV_POS)) + +/* 0x22C : usb_xcvr_config */ +#define GLB_USB_XCVR_CONFIG_OFFSET (0x22C) +#define GLB_USB_V_HYS_M GLB_USB_V_HYS_M +#define GLB_USB_V_HYS_M_POS (0U) +#define GLB_USB_V_HYS_M_LEN (2U) +#define GLB_USB_V_HYS_M_MSK (((1U << GLB_USB_V_HYS_M_LEN) - 1) << GLB_USB_V_HYS_M_POS) +#define GLB_USB_V_HYS_M_UMSK (~(((1U << GLB_USB_V_HYS_M_LEN) - 1) << GLB_USB_V_HYS_M_POS)) +#define GLB_USB_V_HYS_P GLB_USB_V_HYS_P +#define GLB_USB_V_HYS_P_POS (2U) +#define GLB_USB_V_HYS_P_LEN (2U) +#define GLB_USB_V_HYS_P_MSK (((1U << GLB_USB_V_HYS_P_LEN) - 1) << GLB_USB_V_HYS_P_POS) +#define GLB_USB_V_HYS_P_UMSK (~(((1U << GLB_USB_V_HYS_P_LEN) - 1) << GLB_USB_V_HYS_P_POS)) +#define GLB_USB_BD_VTH GLB_USB_BD_VTH +#define GLB_USB_BD_VTH_POS (4U) +#define GLB_USB_BD_VTH_LEN (3U) +#define GLB_USB_BD_VTH_MSK (((1U << GLB_USB_BD_VTH_LEN) - 1) << GLB_USB_BD_VTH_POS) +#define GLB_USB_BD_VTH_UMSK (~(((1U << GLB_USB_BD_VTH_LEN) - 1) << GLB_USB_BD_VTH_POS)) +#define GLB_REG_USB_USE_XCVR GLB_REG_USB_USE_XCVR +#define GLB_REG_USB_USE_XCVR_POS (7U) +#define GLB_REG_USB_USE_XCVR_LEN (1U) +#define GLB_REG_USB_USE_XCVR_MSK (((1U << GLB_REG_USB_USE_XCVR_LEN) - 1) << GLB_REG_USB_USE_XCVR_POS) +#define GLB_REG_USB_USE_XCVR_UMSK (~(((1U << GLB_REG_USB_USE_XCVR_LEN) - 1) << GLB_REG_USB_USE_XCVR_POS)) +#define GLB_USB_STR_DRV GLB_USB_STR_DRV +#define GLB_USB_STR_DRV_POS (8U) +#define GLB_USB_STR_DRV_LEN (3U) +#define GLB_USB_STR_DRV_MSK (((1U << GLB_USB_STR_DRV_LEN) - 1) << GLB_USB_STR_DRV_POS) +#define GLB_USB_STR_DRV_UMSK (~(((1U << GLB_USB_STR_DRV_LEN) - 1) << GLB_USB_STR_DRV_POS)) +#define GLB_REG_USB_USE_CTRL GLB_REG_USB_USE_CTRL +#define GLB_REG_USB_USE_CTRL_POS (11U) +#define GLB_REG_USB_USE_CTRL_LEN (1U) +#define GLB_REG_USB_USE_CTRL_MSK (((1U << GLB_REG_USB_USE_CTRL_LEN) - 1) << GLB_REG_USB_USE_CTRL_POS) +#define GLB_REG_USB_USE_CTRL_UMSK (~(((1U << GLB_REG_USB_USE_CTRL_LEN) - 1) << GLB_REG_USB_USE_CTRL_POS)) +#define GLB_USB_RES_PULLUP_TUNE GLB_USB_RES_PULLUP_TUNE +#define GLB_USB_RES_PULLUP_TUNE_POS (12U) +#define GLB_USB_RES_PULLUP_TUNE_LEN (3U) +#define GLB_USB_RES_PULLUP_TUNE_MSK (((1U << GLB_USB_RES_PULLUP_TUNE_LEN) - 1) << GLB_USB_RES_PULLUP_TUNE_POS) +#define GLB_USB_RES_PULLUP_TUNE_UMSK (~(((1U << GLB_USB_RES_PULLUP_TUNE_LEN) - 1) << GLB_USB_RES_PULLUP_TUNE_POS)) +#define GLB_USB_SLEWRATE_M_FALL GLB_USB_SLEWRATE_M_FALL +#define GLB_USB_SLEWRATE_M_FALL_POS (16U) +#define GLB_USB_SLEWRATE_M_FALL_LEN (3U) +#define GLB_USB_SLEWRATE_M_FALL_MSK (((1U << GLB_USB_SLEWRATE_M_FALL_LEN) - 1) << GLB_USB_SLEWRATE_M_FALL_POS) +#define GLB_USB_SLEWRATE_M_FALL_UMSK (~(((1U << GLB_USB_SLEWRATE_M_FALL_LEN) - 1) << GLB_USB_SLEWRATE_M_FALL_POS)) +#define GLB_USB_SLEWRATE_M_RISE GLB_USB_SLEWRATE_M_RISE +#define GLB_USB_SLEWRATE_M_RISE_POS (20U) +#define GLB_USB_SLEWRATE_M_RISE_LEN (3U) +#define GLB_USB_SLEWRATE_M_RISE_MSK (((1U << GLB_USB_SLEWRATE_M_RISE_LEN) - 1) << GLB_USB_SLEWRATE_M_RISE_POS) +#define GLB_USB_SLEWRATE_M_RISE_UMSK (~(((1U << GLB_USB_SLEWRATE_M_RISE_LEN) - 1) << GLB_USB_SLEWRATE_M_RISE_POS)) +#define GLB_USB_SLEWRATE_P_FALL GLB_USB_SLEWRATE_P_FALL +#define GLB_USB_SLEWRATE_P_FALL_POS (24U) +#define GLB_USB_SLEWRATE_P_FALL_LEN (3U) +#define GLB_USB_SLEWRATE_P_FALL_MSK (((1U << GLB_USB_SLEWRATE_P_FALL_LEN) - 1) << GLB_USB_SLEWRATE_P_FALL_POS) +#define GLB_USB_SLEWRATE_P_FALL_UMSK (~(((1U << GLB_USB_SLEWRATE_P_FALL_LEN) - 1) << GLB_USB_SLEWRATE_P_FALL_POS)) +#define GLB_USB_SLEWRATE_P_RISE GLB_USB_SLEWRATE_P_RISE +#define GLB_USB_SLEWRATE_P_RISE_POS (28U) +#define GLB_USB_SLEWRATE_P_RISE_LEN (3U) +#define GLB_USB_SLEWRATE_P_RISE_MSK (((1U << GLB_USB_SLEWRATE_P_RISE_LEN) - 1) << GLB_USB_SLEWRATE_P_RISE_POS) +#define GLB_USB_SLEWRATE_P_RISE_UMSK (~(((1U << GLB_USB_SLEWRATE_P_RISE_LEN) - 1) << GLB_USB_SLEWRATE_P_RISE_POS)) + +/* 0x308 : gpdac_ctrl */ +#define GLB_GPDAC_CTRL_OFFSET (0x308) +#define GLB_GPDACA_RSTN_ANA GLB_GPDACA_RSTN_ANA +#define GLB_GPDACA_RSTN_ANA_POS (0U) +#define GLB_GPDACA_RSTN_ANA_LEN (1U) +#define GLB_GPDACA_RSTN_ANA_MSK (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS) +#define GLB_GPDACA_RSTN_ANA_UMSK (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)) +#define GLB_GPDACB_RSTN_ANA GLB_GPDACB_RSTN_ANA +#define GLB_GPDACB_RSTN_ANA_POS (1U) +#define GLB_GPDACB_RSTN_ANA_LEN (1U) +#define GLB_GPDACB_RSTN_ANA_MSK (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS) +#define GLB_GPDACB_RSTN_ANA_UMSK (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)) +#define GLB_GPDAC_TEST_EN GLB_GPDAC_TEST_EN +#define GLB_GPDAC_TEST_EN_POS (7U) +#define GLB_GPDAC_TEST_EN_LEN (1U) +#define GLB_GPDAC_TEST_EN_MSK (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS) +#define GLB_GPDAC_TEST_EN_UMSK (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)) +#define GLB_GPDAC_REF_SEL GLB_GPDAC_REF_SEL +#define GLB_GPDAC_REF_SEL_POS (8U) +#define GLB_GPDAC_REF_SEL_LEN (1U) +#define GLB_GPDAC_REF_SEL_MSK (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS) +#define GLB_GPDAC_REF_SEL_UMSK (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)) +#define GLB_GPDAC_TEST_SEL GLB_GPDAC_TEST_SEL +#define GLB_GPDAC_TEST_SEL_POS (9U) +#define GLB_GPDAC_TEST_SEL_LEN (3U) +#define GLB_GPDAC_TEST_SEL_MSK (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS) +#define GLB_GPDAC_TEST_SEL_UMSK (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)) +#define GLB_GPDAC_RESERVED GLB_GPDAC_RESERVED +#define GLB_GPDAC_RESERVED_POS (24U) +#define GLB_GPDAC_RESERVED_LEN (8U) +#define GLB_GPDAC_RESERVED_MSK (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS) +#define GLB_GPDAC_RESERVED_UMSK (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)) + +/* 0x30C : gpdac_actrl */ +#define GLB_GPDAC_ACTRL_OFFSET (0x30C) +#define GLB_GPDAC_A_EN GLB_GPDAC_A_EN +#define GLB_GPDAC_A_EN_POS (0U) +#define GLB_GPDAC_A_EN_LEN (1U) +#define GLB_GPDAC_A_EN_MSK (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS) +#define GLB_GPDAC_A_EN_UMSK (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)) +#define GLB_GPDAC_IOA_EN GLB_GPDAC_IOA_EN +#define GLB_GPDAC_IOA_EN_POS (1U) +#define GLB_GPDAC_IOA_EN_LEN (1U) +#define GLB_GPDAC_IOA_EN_MSK (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS) +#define GLB_GPDAC_IOA_EN_UMSK (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)) +#define GLB_GPDAC_A_RNG GLB_GPDAC_A_RNG +#define GLB_GPDAC_A_RNG_POS (18U) +#define GLB_GPDAC_A_RNG_LEN (2U) +#define GLB_GPDAC_A_RNG_MSK (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS) +#define GLB_GPDAC_A_RNG_UMSK (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)) +#define GLB_GPDAC_A_OUTMUX GLB_GPDAC_A_OUTMUX +#define GLB_GPDAC_A_OUTMUX_POS (20U) +#define GLB_GPDAC_A_OUTMUX_LEN (3U) +#define GLB_GPDAC_A_OUTMUX_MSK (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS) +#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)) + +/* 0x310 : gpdac_bctrl */ +#define GLB_GPDAC_BCTRL_OFFSET (0x310) +#define GLB_GPDAC_B_EN GLB_GPDAC_B_EN +#define GLB_GPDAC_B_EN_POS (0U) +#define GLB_GPDAC_B_EN_LEN (1U) +#define GLB_GPDAC_B_EN_MSK (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS) +#define GLB_GPDAC_B_EN_UMSK (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)) +#define GLB_GPDAC_IOB_EN GLB_GPDAC_IOB_EN +#define GLB_GPDAC_IOB_EN_POS (1U) +#define GLB_GPDAC_IOB_EN_LEN (1U) +#define GLB_GPDAC_IOB_EN_MSK (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS) +#define GLB_GPDAC_IOB_EN_UMSK (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)) +#define GLB_GPDAC_B_RNG GLB_GPDAC_B_RNG +#define GLB_GPDAC_B_RNG_POS (18U) +#define GLB_GPDAC_B_RNG_LEN (2U) +#define GLB_GPDAC_B_RNG_MSK (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS) +#define GLB_GPDAC_B_RNG_UMSK (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)) +#define GLB_GPDAC_B_OUTMUX GLB_GPDAC_B_OUTMUX +#define GLB_GPDAC_B_OUTMUX_POS (20U) +#define GLB_GPDAC_B_OUTMUX_LEN (3U) +#define GLB_GPDAC_B_OUTMUX_MSK (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS) +#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)) + +/* 0x314 : gpdac_data */ +#define GLB_GPDAC_DATA_OFFSET (0x314) +#define GLB_GPDAC_B_DATA GLB_GPDAC_B_DATA +#define GLB_GPDAC_B_DATA_POS (0U) +#define GLB_GPDAC_B_DATA_LEN (10U) +#define GLB_GPDAC_B_DATA_MSK (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS) +#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)) +#define GLB_GPDAC_A_DATA GLB_GPDAC_A_DATA +#define GLB_GPDAC_A_DATA_POS (16U) +#define GLB_GPDAC_A_DATA_LEN (10U) +#define GLB_GPDAC_A_DATA_MSK (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS) +#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)) + +/* 0xE00 : chip_revision */ +#define GLB_CHIP_REVISION_OFFSET (0xE00) +#define GLB_CHIP_REV GLB_CHIP_REV +#define GLB_CHIP_REV_POS (0U) +#define GLB_CHIP_REV_LEN (4U) +#define GLB_CHIP_REV_MSK (((1U << GLB_CHIP_REV_LEN) - 1) << GLB_CHIP_REV_POS) +#define GLB_CHIP_REV_UMSK (~(((1U << GLB_CHIP_REV_LEN) - 1) << GLB_CHIP_REV_POS)) + +/* 0xF00 : tzc_glb_ctrl_0 */ +#define GLB_TZC_GLB_CTRL_0_OFFSET (0xF00) +#define GLB_TZC_GLB_SWRST_S00_LOCK GLB_TZC_GLB_SWRST_S00_LOCK +#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0U) +#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S01_LOCK GLB_TZC_GLB_SWRST_S01_LOCK +#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1U) +#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S30_LOCK GLB_TZC_GLB_SWRST_S30_LOCK +#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8U) +#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK GLB_TZC_GLB_CTRL_PWRON_RST_LOCK +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12U) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK GLB_TZC_GLB_CTRL_CPU_RESET_LOCK +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13U) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK GLB_TZC_GLB_CTRL_SYS_RESET_LOCK +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14U) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15U) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)) +#define GLB_TZC_GLB_MISC_LOCK GLB_TZC_GLB_MISC_LOCK +#define GLB_TZC_GLB_MISC_LOCK_POS (25U) +#define GLB_TZC_GLB_MISC_LOCK_LEN (1U) +#define GLB_TZC_GLB_MISC_LOCK_MSK (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS) +#define GLB_TZC_GLB_MISC_LOCK_UMSK (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)) +#define GLB_TZC_GLB_SRAM_LOCK GLB_TZC_GLB_SRAM_LOCK +#define GLB_TZC_GLB_SRAM_LOCK_POS (26U) +#define GLB_TZC_GLB_SRAM_LOCK_LEN (1U) +#define GLB_TZC_GLB_SRAM_LOCK_MSK (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS) +#define GLB_TZC_GLB_SRAM_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)) +#define GLB_TZC_GLB_L2C_LOCK GLB_TZC_GLB_L2C_LOCK +#define GLB_TZC_GLB_L2C_LOCK_POS (27U) +#define GLB_TZC_GLB_L2C_LOCK_LEN (1U) +#define GLB_TZC_GLB_L2C_LOCK_MSK (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS) +#define GLB_TZC_GLB_L2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)) +#define GLB_TZC_GLB_BMX_LOCK GLB_TZC_GLB_BMX_LOCK +#define GLB_TZC_GLB_BMX_LOCK_POS (28U) +#define GLB_TZC_GLB_BMX_LOCK_LEN (1U) +#define GLB_TZC_GLB_BMX_LOCK_MSK (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS) +#define GLB_TZC_GLB_BMX_LOCK_UMSK (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)) +#define GLB_TZC_GLB_DBG_LOCK GLB_TZC_GLB_DBG_LOCK +#define GLB_TZC_GLB_DBG_LOCK_POS (29U) +#define GLB_TZC_GLB_DBG_LOCK_LEN (1U) +#define GLB_TZC_GLB_DBG_LOCK_MSK (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS) +#define GLB_TZC_GLB_DBG_LOCK_UMSK (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)) +#define GLB_TZC_GLB_MBIST_LOCK GLB_TZC_GLB_MBIST_LOCK +#define GLB_TZC_GLB_MBIST_LOCK_POS (30U) +#define GLB_TZC_GLB_MBIST_LOCK_LEN (1U) +#define GLB_TZC_GLB_MBIST_LOCK_MSK (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS) +#define GLB_TZC_GLB_MBIST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)) +#define GLB_TZC_GLB_CLK_LOCK GLB_TZC_GLB_CLK_LOCK +#define GLB_TZC_GLB_CLK_LOCK_POS (31U) +#define GLB_TZC_GLB_CLK_LOCK_LEN (1U) +#define GLB_TZC_GLB_CLK_LOCK_MSK (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS) +#define GLB_TZC_GLB_CLK_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)) + +/* 0xF04 : tzc_glb_ctrl_1 */ +#define GLB_TZC_GLB_CTRL_1_OFFSET (0xF04) +#define GLB_TZC_GLB_SWRST_S20_LOCK GLB_TZC_GLB_SWRST_S20_LOCK +#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0U) +#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S21_LOCK GLB_TZC_GLB_SWRST_S21_LOCK +#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1U) +#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S22_LOCK GLB_TZC_GLB_SWRST_S22_LOCK +#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2U) +#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S23_LOCK GLB_TZC_GLB_SWRST_S23_LOCK +#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3U) +#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S24_LOCK GLB_TZC_GLB_SWRST_S24_LOCK +#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4U) +#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S25_LOCK GLB_TZC_GLB_SWRST_S25_LOCK +#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5U) +#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S26_LOCK GLB_TZC_GLB_SWRST_S26_LOCK +#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6U) +#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S27_LOCK GLB_TZC_GLB_SWRST_S27_LOCK +#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7U) +#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S28_LOCK GLB_TZC_GLB_SWRST_S28_LOCK +#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8U) +#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S29_LOCK GLB_TZC_GLB_SWRST_S29_LOCK +#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9U) +#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2A_LOCK GLB_TZC_GLB_SWRST_S2A_LOCK +#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10U) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2B_LOCK GLB_TZC_GLB_SWRST_S2B_LOCK +#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11U) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2C_LOCK GLB_TZC_GLB_SWRST_S2C_LOCK +#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12U) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2D_LOCK GLB_TZC_GLB_SWRST_S2D_LOCK +#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13U) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2E_LOCK GLB_TZC_GLB_SWRST_S2E_LOCK +#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14U) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2F_LOCK GLB_TZC_GLB_SWRST_S2F_LOCK +#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15U) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S10_LOCK GLB_TZC_GLB_SWRST_S10_LOCK +#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16U) +#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S11_LOCK GLB_TZC_GLB_SWRST_S11_LOCK +#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17U) +#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S12_LOCK GLB_TZC_GLB_SWRST_S12_LOCK +#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18U) +#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S13_LOCK GLB_TZC_GLB_SWRST_S13_LOCK +#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19U) +#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S14_LOCK GLB_TZC_GLB_SWRST_S14_LOCK +#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20U) +#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S15_LOCK GLB_TZC_GLB_SWRST_S15_LOCK +#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21U) +#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S16_LOCK GLB_TZC_GLB_SWRST_S16_LOCK +#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22U) +#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S17_LOCK GLB_TZC_GLB_SWRST_S17_LOCK +#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23U) +#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S18_LOCK GLB_TZC_GLB_SWRST_S18_LOCK +#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24U) +#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S19_LOCK GLB_TZC_GLB_SWRST_S19_LOCK +#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25U) +#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1A_LOCK GLB_TZC_GLB_SWRST_S1A_LOCK +#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26U) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1B_LOCK GLB_TZC_GLB_SWRST_S1B_LOCK +#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27U) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1C_LOCK GLB_TZC_GLB_SWRST_S1C_LOCK +#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28U) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1D_LOCK GLB_TZC_GLB_SWRST_S1D_LOCK +#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29U) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1E_LOCK GLB_TZC_GLB_SWRST_S1E_LOCK +#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30U) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1F_LOCK GLB_TZC_GLB_SWRST_S1F_LOCK +#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31U) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)) + +/* 0xF08 : tzc_glb_ctrl_2 */ +#define GLB_TZC_GLB_CTRL_2_OFFSET (0xF08) +#define GLB_TZC_GLB_GPIO_0_LOCK GLB_TZC_GLB_GPIO_0_LOCK +#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0U) +#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_0_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS) +#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_1_LOCK GLB_TZC_GLB_GPIO_1_LOCK +#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1U) +#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_1_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS) +#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_2_LOCK GLB_TZC_GLB_GPIO_2_LOCK +#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2U) +#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_2_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS) +#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_3_LOCK GLB_TZC_GLB_GPIO_3_LOCK +#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3U) +#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_3_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS) +#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_4_LOCK GLB_TZC_GLB_GPIO_4_LOCK +#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4U) +#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_4_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS) +#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_5_LOCK GLB_TZC_GLB_GPIO_5_LOCK +#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5U) +#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_5_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS) +#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_6_LOCK GLB_TZC_GLB_GPIO_6_LOCK +#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6U) +#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_6_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS) +#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_7_LOCK GLB_TZC_GLB_GPIO_7_LOCK +#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7U) +#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_7_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS) +#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_8_LOCK GLB_TZC_GLB_GPIO_8_LOCK +#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8U) +#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_8_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS) +#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_9_LOCK GLB_TZC_GLB_GPIO_9_LOCK +#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9U) +#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_9_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS) +#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_10_LOCK GLB_TZC_GLB_GPIO_10_LOCK +#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10U) +#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_10_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS) +#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_11_LOCK GLB_TZC_GLB_GPIO_11_LOCK +#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11U) +#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_11_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS) +#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_12_LOCK GLB_TZC_GLB_GPIO_12_LOCK +#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12U) +#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_12_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS) +#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_13_LOCK GLB_TZC_GLB_GPIO_13_LOCK +#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13U) +#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_13_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS) +#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_14_LOCK GLB_TZC_GLB_GPIO_14_LOCK +#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14U) +#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_14_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS) +#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_15_LOCK GLB_TZC_GLB_GPIO_15_LOCK +#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15U) +#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_15_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS) +#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_16_LOCK GLB_TZC_GLB_GPIO_16_LOCK +#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16U) +#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_16_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS) +#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_17_LOCK GLB_TZC_GLB_GPIO_17_LOCK +#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17U) +#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_17_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS) +#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_18_LOCK GLB_TZC_GLB_GPIO_18_LOCK +#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18U) +#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_18_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS) +#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_19_LOCK GLB_TZC_GLB_GPIO_19_LOCK +#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19U) +#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_19_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS) +#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_20_LOCK GLB_TZC_GLB_GPIO_20_LOCK +#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20U) +#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_20_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS) +#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_21_LOCK GLB_TZC_GLB_GPIO_21_LOCK +#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21U) +#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_21_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS) +#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_22_LOCK GLB_TZC_GLB_GPIO_22_LOCK +#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22U) +#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_22_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS) +#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_23_LOCK GLB_TZC_GLB_GPIO_23_LOCK +#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23U) +#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_23_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS) +#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_24_LOCK GLB_TZC_GLB_GPIO_24_LOCK +#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24U) +#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_24_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS) +#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_25_LOCK GLB_TZC_GLB_GPIO_25_LOCK +#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25U) +#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_25_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS) +#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_26_LOCK GLB_TZC_GLB_GPIO_26_LOCK +#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26U) +#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_26_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS) +#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_27_LOCK GLB_TZC_GLB_GPIO_27_LOCK +#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27U) +#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_27_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS) +#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_28_LOCK GLB_TZC_GLB_GPIO_28_LOCK +#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28U) +#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_28_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS) +#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_29_LOCK GLB_TZC_GLB_GPIO_29_LOCK +#define GLB_TZC_GLB_GPIO_29_LOCK_POS (29U) +#define GLB_TZC_GLB_GPIO_29_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_29_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_29_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_29_LOCK_POS) +#define GLB_TZC_GLB_GPIO_29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_29_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_29_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_30_LOCK GLB_TZC_GLB_GPIO_30_LOCK +#define GLB_TZC_GLB_GPIO_30_LOCK_POS (30U) +#define GLB_TZC_GLB_GPIO_30_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_30_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_30_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_30_LOCK_POS) +#define GLB_TZC_GLB_GPIO_30_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_30_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_30_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_31_LOCK GLB_TZC_GLB_GPIO_31_LOCK +#define GLB_TZC_GLB_GPIO_31_LOCK_POS (31U) +#define GLB_TZC_GLB_GPIO_31_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_31_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_31_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_31_LOCK_POS) +#define GLB_TZC_GLB_GPIO_31_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_31_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_31_LOCK_POS)) + +/* 0xF0C : tzc_glb_ctrl_3 */ +#define GLB_TZC_GLB_CTRL_3_OFFSET (0xF0C) +#define GLB_TZC_GLB_GPIO_32_LOCK GLB_TZC_GLB_GPIO_32_LOCK +#define GLB_TZC_GLB_GPIO_32_LOCK_POS (0U) +#define GLB_TZC_GLB_GPIO_32_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_32_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_32_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_32_LOCK_POS) +#define GLB_TZC_GLB_GPIO_32_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_32_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_32_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_33_LOCK GLB_TZC_GLB_GPIO_33_LOCK +#define GLB_TZC_GLB_GPIO_33_LOCK_POS (1U) +#define GLB_TZC_GLB_GPIO_33_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_33_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_33_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_33_LOCK_POS) +#define GLB_TZC_GLB_GPIO_33_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_33_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_33_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_34_LOCK GLB_TZC_GLB_GPIO_34_LOCK +#define GLB_TZC_GLB_GPIO_34_LOCK_POS (2U) +#define GLB_TZC_GLB_GPIO_34_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_34_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_34_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_34_LOCK_POS) +#define GLB_TZC_GLB_GPIO_34_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_34_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_34_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_35_LOCK GLB_TZC_GLB_GPIO_35_LOCK +#define GLB_TZC_GLB_GPIO_35_LOCK_POS (3U) +#define GLB_TZC_GLB_GPIO_35_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_35_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_35_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_35_LOCK_POS) +#define GLB_TZC_GLB_GPIO_35_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_35_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_35_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_36_LOCK GLB_TZC_GLB_GPIO_36_LOCK +#define GLB_TZC_GLB_GPIO_36_LOCK_POS (4U) +#define GLB_TZC_GLB_GPIO_36_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_36_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_36_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_36_LOCK_POS) +#define GLB_TZC_GLB_GPIO_36_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_36_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_36_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_37_LOCK GLB_TZC_GLB_GPIO_37_LOCK +#define GLB_TZC_GLB_GPIO_37_LOCK_POS (5U) +#define GLB_TZC_GLB_GPIO_37_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_37_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_37_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_37_LOCK_POS) +#define GLB_TZC_GLB_GPIO_37_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_37_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_37_LOCK_POS)) + +struct glb_reg { + /* 0x0 : clk_cfg0 */ + union { + struct + { + uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_fclk_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_hclk_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reg_bclk_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t reg_pll_sel : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t hbn_root_clk_sel : 2; /* [ 7: 6], r, 0x0 */ + uint32_t reg_hclk_div : 8; /* [15: 8], r/w, 0x0 */ + uint32_t reg_bclk_div : 8; /* [23:16], r/w, 0x0 */ + uint32_t fclk_sw_state : 3; /* [26:24], r, 0x0 */ + uint32_t chip_rdy : 1; /* [ 27], r, 0x0 */ + uint32_t glb_id : 4; /* [31:28], r, 0x7 */ + } BF; + uint32_t WORD; + } clk_cfg0; + + /* 0x4 : clk_cfg1 */ + union { + struct + { + uint32_t qdec_clk_div : 5; /* [ 4: 0], r/w, 0x1f */ + uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ + uint32_t qdec_clk_sel : 1; /* [ 7], r/w, 0x0 */ + uint32_t usb_clk_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t dll_48m_div_en : 1; /* [ 9], r/w, 0x1 */ + uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ + uint32_t reg_i2s_clk_sel : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_i2s0_clk_en : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_i2s_0_ref_clk_oe : 1; /* [ 14], r/w, 0x0 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t ble_clk_sel : 6; /* [21:16], r/w, 0x10 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t ble_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t m154_zbEn : 1; /* [ 25], r/w, 0x1 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t reg_cam_ref_clk_en : 1; /* [ 28], r/w, 0x0 */ + uint32_t reg_cam_ref_clk_src_sel : 1; /* [ 29], r/w, 0x0 */ + uint32_t reg_cam_ref_clk_div : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } clk_cfg1; + + /* 0x8 : clk_cfg2 */ + union { + struct + { + uint32_t uart_clk_div : 3; /* [ 2: 0], r/w, 0x7 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t uart_clk_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ + uint32_t hbn_uart_clk_sel : 1; /* [ 7], r, 0x0 */ + uint32_t sf_clk_div : 3; /* [10: 8], r/w, 0x3 */ + uint32_t sf_clk_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t sf_clk_sel : 2; /* [13:12], r/w, 0x2 */ + uint32_t sf_clk_sel2 : 2; /* [15:14], r/w, 0x0 */ + uint32_t ir_clk_div : 6; /* [21:16], r/w, 0xf */ + uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ + uint32_t ir_clk_en : 1; /* [ 23], r/w, 0x1 */ + uint32_t dma_clk_en : 8; /* [31:24], r/w, 0xff */ + } BF; + uint32_t WORD; + } clk_cfg2; + + /* 0xC : clk_cfg3 */ + union { + struct + { + uint32_t spi_clk_div : 5; /* [ 4: 0], r/w, 0x3 */ + uint32_t cfg_sel_eth_ref_clk_o : 1; /* [ 5], r/w, 0x0 */ + uint32_t cfg_inv_eth_ref_clk_o : 1; /* [ 6], r/w, 0x1 */ + uint32_t cfg_inv_eth_tx_clk : 1; /* [ 7], r/w, 0x1 */ + uint32_t spi_clk_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t cfg_inv_rf_test_clk_o : 1; /* [ 9], r/w, 0x1 */ + uint32_t cfg_inv_eth_rx_clk : 1; /* [ 10], r/w, 0x1 */ + uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ + uint32_t i2c_clk_div : 8; /* [23:16], r/w, 0xff */ + uint32_t i2c_clk_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_27 : 3; /* [27:25], rsvd, 0x0 */ + uint32_t chip_clk_out_0_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t chip_clk_out_1_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } clk_cfg3; + + /* 0x10 : swrst_cfg0 */ + union { + struct + { + uint32_t swrst_s00 : 1; /* [ 0], r/w, 0x0 */ + uint32_t swrst_s01 : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t swrst_s20 : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t swrst_s30 : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg0; + + /* 0x14 : swrst_cfg1 */ + union { + struct + { + uint32_t swrst_s10 : 1; /* [ 0], r/w, 0x0 */ + uint32_t swrst_s11 : 1; /* [ 1], r/w, 0x0 */ + uint32_t swrst_s12 : 1; /* [ 2], r/w, 0x0 */ + uint32_t swrst_s13 : 1; /* [ 3], r/w, 0x0 */ + uint32_t swrst_s14 : 1; /* [ 4], r/w, 0x0 */ + uint32_t swrst_s15 : 1; /* [ 5], r/w, 0x0 */ + uint32_t swrst_s16 : 1; /* [ 6], r/w, 0x0 */ + uint32_t swrst_s17 : 1; /* [ 7], r/w, 0x0 */ + uint32_t swrst_s18 : 1; /* [ 8], r/w, 0x0 */ + uint32_t swrst_s19 : 1; /* [ 9], r/w, 0x0 */ + uint32_t swrst_s1a : 1; /* [ 10], r/w, 0x0 */ + uint32_t swrst_s1b : 1; /* [ 11], r/w, 0x0 */ + uint32_t swrst_s1c : 1; /* [ 12], r/w, 0x0 */ + uint32_t swrst_s1d : 1; /* [ 13], r/w, 0x0 */ + uint32_t swrst_s1e : 1; /* [ 14], r/w, 0x0 */ + uint32_t swrst_s1f : 1; /* [ 15], r/w, 0x0 */ + uint32_t swrst_s1a0 : 1; /* [ 16], r/w, 0x0 */ + uint32_t swrst_s1a1 : 1; /* [ 17], r/w, 0x0 */ + uint32_t swrst_s1a2 : 1; /* [ 18], r/w, 0x0 */ + uint32_t swrst_s1a3 : 1; /* [ 19], r/w, 0x0 */ + uint32_t swrst_s1a4 : 1; /* [ 20], r/w, 0x0 */ + uint32_t swrst_s1a5 : 1; /* [ 21], r/w, 0x0 */ + uint32_t swrst_s1a6 : 1; /* [ 22], r/w, 0x0 */ + uint32_t swrst_s1a7 : 1; /* [ 23], r/w, 0x0 */ + uint32_t swrst_s1a8 : 1; /* [ 24], r/w, 0x0 */ + uint32_t swrst_s1a9 : 1; /* [ 25], r/w, 0x0 */ + uint32_t swrst_s1aa : 1; /* [ 26], r/w, 0x0 */ + uint32_t swrst_s1ab : 1; /* [ 27], r/w, 0x0 */ + uint32_t swrst_s1ac : 1; /* [ 28], r/w, 0x0 */ + uint32_t swrst_s1ad : 1; /* [ 29], r/w, 0x0 */ + uint32_t swrst_s1ae : 1; /* [ 30], r/w, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg1; + + /* 0x18 : swrst_cfg2 */ + union { + struct + { + uint32_t reg_ctrl_pwron_rst : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_ctrl_cpu_reset : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_ctrl_sys_reset : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t reg_ctrl_reset_dummy : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t reserved_8_23 : 16; /* [23: 8], rsvd, 0x0 */ + uint32_t pka_clk_sel : 1; /* [ 24], r/w, 0x0 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg2; + + /* 0x1C : swrst_cfg3 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg3; + + /* 0x20 : cgen_cfg0 */ + union { + struct + { + uint32_t cgen_m : 8; /* [ 7: 0], r/w, 0xff */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg0; + + /* 0x24 : cgen_cfg1 */ + union { + struct + { + uint32_t cgen_s1 : 16; /* [15: 0], r/w, 0xcfff */ + uint32_t cgen_s1a : 16; /* [31:16], r/w, 0x9b23 */ + } BF; + uint32_t WORD; + } cgen_cfg1; + + /* 0x28 : cgen_cfg2 */ + union { + struct + { + uint32_t cgen_s2 : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t cgen_s3 : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg2; + + /* 0x2C : cgen_cfg3 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg3; + + /* 0x30 : MBIST_CTL */ + union { + struct + { + uint32_t irom_mbist_mode : 1; /* [ 0], r/w, 0x0 */ + uint32_t hsram_mem_mbist_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t hsram_cache_mbist_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t tag_mbist_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t ocram_mbist_mode : 1; /* [ 4], r/w, 0x0 */ + uint32_t em_ram_mbist_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_30 : 25; /* [30: 6], rsvd, 0x0 */ + uint32_t reg_mbist_rst_n : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } MBIST_CTL; + + /* 0x34 : MBIST_STAT */ + union { + struct + { + uint32_t irom_mbist_done : 1; /* [ 0], r, 0x0 */ + uint32_t hsram_mem_mbist_done : 1; /* [ 1], r, 0x0 */ + uint32_t hsram_cache_mbist_done : 1; /* [ 2], r, 0x0 */ + uint32_t tag_mbist_done : 1; /* [ 3], r, 0x0 */ + uint32_t ocram_mbist_done : 1; /* [ 4], r, 0x0 */ + uint32_t em_ram_mbist_done : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t irom_mbist_fail : 1; /* [ 16], r, 0x0 */ + uint32_t hsram_mem_mbist_fail : 1; /* [ 17], r, 0x0 */ + uint32_t hsram_cache_mbist_fail : 1; /* [ 18], r, 0x0 */ + uint32_t tag_mbist_fail : 1; /* [ 19], r, 0x0 */ + uint32_t ocram_mbist_fail : 1; /* [ 20], r, 0x0 */ + uint32_t em_ram_mbist_fail : 1; /* [ 21], r, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MBIST_STAT; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[24]; + + /* 0x50 : bmx_cfg1 */ + union { + struct + { + uint32_t bmx_timeout_en : 4; /* [ 3: 0], r/w, 0x0 */ + uint32_t bmx_arb_mode : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t bmx_err_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t bmx_busy_option_dis : 1; /* [ 9], r/w, 0x0 */ + uint32_t bmx_gating_dis : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t hsel_option : 4; /* [15:12], r/w, 0x0 */ + uint32_t pds_apb_cfg : 8; /* [23:16], r/w, 0x0 */ + uint32_t hbn_apb_cfg : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } bmx_cfg1; + + /* 0x54 : bmx_cfg2 */ + union { + struct + { + uint32_t bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t bmx_err_dec : 1; /* [ 4], r, 0x0 */ + uint32_t bmx_err_tz : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_w_thre_bmx : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reg_w_thre_l1c : 2; /* [11:10], r/w, 0x0 */ + uint32_t reserved_12_27 : 16; /* [27:12], rsvd, 0x0 */ + uint32_t bmx_dbg_sel : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } bmx_cfg2; + + /* 0x58 : bmx_err_addr */ + union { + struct + { + uint32_t bmx_err_addr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } bmx_err_addr; + + /* 0x5C : bmx_dbg_out */ + union { + struct + { + uint32_t bmx_dbg_out : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } bmx_dbg_out; + + /* 0x60 : rsv0 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv0; + + /* 0x64 : rsv1 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv1; + + /* 0x68 : rsv2 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv2; + + /* 0x6C : rsv3 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0xffffffffL */ + } BF; + uint32_t WORD; + } rsv3; + + /* 0x70 : sram_ret */ + union { + struct + { + uint32_t reg_sram_ret : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sram_ret; + + /* 0x74 : sram_slp */ + union { + struct + { + uint32_t reg_sram_slp : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sram_slp; + + /* 0x78 : sram_parm */ + union { + struct + { + uint32_t reg_sram_parm : 32; /* [31: 0], r/w, 0x6a4c0c0c */ + } BF; + uint32_t WORD; + } sram_parm; + + /* 0x7C : seam_misc */ + union { + struct + { + uint32_t em_sel : 4; /* [ 3: 0], r/w, 0x3 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } seam_misc; + + /* 0x80 : glb_parm */ + union { + struct + { + uint32_t jtag_swap_set : 8; /* [ 7: 0], r/w, 0x4 */ + uint32_t cfg_sflash2_swap_io0_io3 : 1; /* [ 8], r/w, 0x0 */ + uint32_t cfg_sflash2_swap_cs_io2 : 1; /* [ 9], r/w, 0x0 */ + uint32_t cfg_flash_scenario : 2; /* [11:10], r/w, 0x0 */ + uint32_t reg_spi_0_master_mode : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_spi_0_swap : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t reg_cci_use_jtag_pin : 1; /* [ 16], r/w, 0x1 */ + uint32_t p1_adc_test_with_cci : 1; /* [ 17], r/w, 0x0 */ + uint32_t p2_dac_test_with_cci : 1; /* [ 18], r/w, 0x0 */ + uint32_t p3_cci_use_io_0_2_7 : 1; /* [ 19], r/w, 0x0 */ + uint32_t p4_adc_test_with_jtag : 1; /* [ 20], r/w, 0x0 */ + uint32_t p5_dac_test_with_jtag : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ + uint32_t p6_jtag_use_io_0_2_7 : 1; /* [ 23], r/w, 0x0 */ + uint32_t uart_swap_set : 4; /* [27:24], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t reg_kys_drv_val : 1; /* [ 29], r/w, 0x0 */ + uint32_t reg_ext_rst_smt : 1; /* [ 30], r/w, 0x0 */ + uint32_t pin_sel_emac_cam : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } glb_parm; + + /* 0x84 : PDM_CLK_CTRL */ + union { + struct + { + uint32_t reg_pdm0_clk_div : 6; /* [ 5: 0], r/w, 0x1 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t reg_pdm0_clk_en : 1; /* [ 7], r/w, 0x1 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDM_CLK_CTRL; + + /* 0x88 : GPIO_USE_PSRAM__IO */ + union { + struct + { + uint32_t cfg_gpio_use_psram_io : 6; /* [ 5: 0], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_USE_PSRAM__IO; + + /* 0x8c reserved */ + uint8_t RESERVED0x8c[4]; + + /* 0x90 : CPU_CLK_CFG */ + union { + struct + { + uint32_t cpu_rtc_div : 17; /* [16: 0], r/w, 0x10 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t cpu_rtc_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t cpu_rtc_sel : 1; /* [ 19], r/w, 0x1 */ + uint32_t debug_ndreset_gate : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } CPU_CLK_CFG; + + /* 0x94 reserved */ + uint8_t RESERVED0x94[16]; + + /* 0xA4 : GPADC_32M_SRC_CTRL */ + union { + struct + { + uint32_t gpadc_32m_clk_div : 6; /* [ 5: 0], r/w, 0x2 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t gpadc_32m_clk_sel : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpadc_32m_div_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPADC_32M_SRC_CTRL; + + /* 0xA8 : DIG32K_WAKEUP_CTRL */ + union { + struct + { + uint32_t dig_32k_div : 11; /* [10: 0], r/w, 0x3e8 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t dig_32k_en : 1; /* [ 12], r/w, 0x1 */ + uint32_t dig_32k_comp : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t dig_512k_div : 7; /* [22:16], r/w, 0x3e */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t dig_512k_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t dig_512k_comp : 1; /* [ 25], r/w, 0x1 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t dig_clk_src_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ + uint32_t reg_en_platform_wakeup : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DIG32K_WAKEUP_CTRL; + + /* 0xAC : WIFI_BT_COEX_CTRL */ + union { + struct + { + uint32_t coex_bt_channel : 7; /* [ 6: 0], r/w, 0x0 */ + uint32_t coex_bt_pti : 4; /* [10: 7], r/w, 0x0 */ + uint32_t coex_bt_bw : 1; /* [ 11], r/w, 0x0 */ + uint32_t en_gpio_bt_coex : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WIFI_BT_COEX_CTRL; + + /* 0xB0 : BZ_COEX_CTRL */ + union { + struct + { + uint32_t coex_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t wlan_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ble_rx_ignore : 1; /* [ 2], r/w, 0x0 */ + uint32_t m154_rx_ignore : 1; /* [ 3], r/w, 0x0 */ + uint32_t bz_pri_thr : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t bz_pri_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t bz_pri_pol : 1; /* [ 9], r/w, 0x1 */ + uint32_t bz_active_pol : 1; /* [ 10], r/w, 0x1 */ + uint32_t bz_abort_pol : 1; /* [ 11], r/w, 0x1 */ + uint32_t coex_pri : 1; /* [ 12], r/w, 0x0 */ + uint32_t force_m154_win : 1; /* [ 13], r/w, 0x0 */ + uint32_t force_ble_win : 1; /* [ 14], r/w, 0x0 */ + uint32_t coex_option : 1; /* [ 15], r/w, 0x0 */ + uint32_t coex_force_ch : 7; /* [22:16], r/w, 0x4 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t m154_rx_abort_dis : 1; /* [ 24], r/w, 0x0 */ + uint32_t m154_tx_abort_dis : 1; /* [ 25], r/w, 0x0 */ + uint32_t ble_rx_abort_dis : 1; /* [ 26], r/w, 0x0 */ + uint32_t ble_tx_abort_dis : 1; /* [ 27], r/w, 0x0 */ + uint32_t coex_arb : 4; /* [31:28], r, 0x8 */ + } BF; + uint32_t WORD; + } BZ_COEX_CTRL; + + /* 0xb4 reserved */ + uint8_t RESERVED0xb4[12]; + + /* 0xC0 : UART_SIG_SEL_0 */ + union { + struct + { + uint32_t uart_sig_0_sel : 4; /* [ 3: 0], r/w, 0x0 */ + uint32_t uart_sig_1_sel : 4; /* [ 7: 4], r/w, 0x1 */ + uint32_t uart_sig_2_sel : 4; /* [11: 8], r/w, 0x2 */ + uint32_t uart_sig_3_sel : 4; /* [15:12], r/w, 0x3 */ + uint32_t uart_sig_4_sel : 4; /* [19:16], r/w, 0x4 */ + uint32_t uart_sig_5_sel : 4; /* [23:20], r/w, 0x5 */ + uint32_t uart_sig_6_sel : 4; /* [27:24], r/w, 0x6 */ + uint32_t uart_sig_7_sel : 4; /* [31:28], r/w, 0x7 */ + } BF; + uint32_t WORD; + } UART_SIG_SEL_0; + + /* 0xc4 reserved */ + uint8_t RESERVED0xc4[12]; + + /* 0xD0 : DBG_SEL_LL */ + union { + struct + { + uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_LL; + + /* 0xD4 : DBG_SEL_LH */ + union { + struct + { + uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_LH; + + /* 0xD8 : DBG_SEL_HL */ + union { + struct + { + uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_HL; + + /* 0xDC : DBG_SEL_HH */ + union { + struct + { + uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_HH; + + /* 0xE0 : debug */ + union { + struct + { + uint32_t debug_oe : 1; /* [ 0], r/w, 0x0 */ + uint32_t debug_i : 31; /* [31: 1], r, 0x0 */ + } BF; + uint32_t WORD; + } debug; + + /* 0xe4 reserved */ + uint8_t RESERVED0xe4[28]; + + /* 0x100 : GPIO_CFGCTL0 */ + union { + struct + { + uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_0_func_sel : 5; /* [12: 8], r/w, 0xe */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_1_func_sel : 5; /* [28:24], r/w, 0xe */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL0; + + /* 0x104 : GPIO_CFGCTL1 */ + union { + struct + { + uint32_t reg_gpio_2_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_2_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_2_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_2_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_2_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_2_func_sel : 5; /* [12: 8], r/w, 0xe */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_3_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_3_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_3_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_3_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_3_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_3_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL1; + + /* 0x108 : GPIO_CFGCTL2 */ + union { + struct + { + uint32_t reg_gpio_4_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_4_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_4_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_4_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_4_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_4_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_5_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_5_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_5_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_5_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_5_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_5_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL2; + + /* 0x10C : GPIO_CFGCTL3 */ + union { + struct + { + uint32_t reg_gpio_6_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_6_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_6_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_6_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_6_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_6_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_7_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_7_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_7_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_7_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_7_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_7_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL3; + + /* 0x110 : GPIO_CFGCTL4 */ + union { + struct + { + uint32_t reg_gpio_8_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_8_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_8_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_8_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_8_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_8_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_9_ie : 1; /* [ 16], r/w, 0x0 */ + uint32_t reg_gpio_9_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_9_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_9_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_9_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_9_func_sel : 5; /* [28:24], r/w, 0xe */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL4; + + /* 0x114 : GPIO_CFGCTL5 */ + union { + struct + { + uint32_t reg_gpio_10_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_10_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_10_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_10_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_10_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_10_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_11_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_11_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_11_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_11_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_11_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_11_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL5; + + /* 0x118 : GPIO_CFGCTL6 */ + union { + struct + { + uint32_t reg_gpio_12_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_12_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_12_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_12_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_12_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_12_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_13_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_13_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_13_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_13_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_13_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_13_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL6; + + /* 0x11C : GPIO_CFGCTL7 */ + union { + struct + { + uint32_t reg_gpio_14_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_14_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_14_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_14_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_14_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_14_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_15_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_15_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_15_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_15_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_15_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_15_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL7; + + /* 0x120 : GPIO_CFGCTL8 */ + union { + struct + { + uint32_t reg_gpio_16_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_16_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_16_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_16_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_16_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_16_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_17_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_17_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_17_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_17_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_17_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_17_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL8; + + /* 0x124 : GPIO_CFGCTL9 */ + union { + struct + { + uint32_t reg_gpio_18_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_18_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_18_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_18_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_18_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_18_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_19_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_19_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_19_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_19_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_19_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_19_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL9; + + /* 0x128 : GPIO_CFGCTL10 */ + union { + struct + { + uint32_t reg_gpio_20_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_20_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_20_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_20_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_20_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_20_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_21_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_21_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_21_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_21_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_21_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL10; + + /* 0x12C : GPIO_CFGCTL11 */ + union { + struct + { + uint32_t reg_gpio_22_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_22_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_22_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_22_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_22_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_22_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_23_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_23_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_23_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_23_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_23_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_23_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL11; + + /* 0x130 : GPIO_CFGCTL12 */ + union { + struct + { + uint32_t reg_gpio_24_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_24_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_24_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_24_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_24_pd : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_24_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_25_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_25_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_25_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_25_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_25_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_25_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL12; + + /* 0x134 : GPIO_CFGCTL13 */ + union { + struct + { + uint32_t reg_gpio_26_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_26_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_26_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_26_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_26_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_26_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_27_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_27_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_27_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_27_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_27_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_27_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL13; + + /* 0x138 : GPIO_CFGCTL14 */ + union { + struct + { + uint32_t reg_gpio_28_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_28_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_28_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_28_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_28_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_28_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_29_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_29_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_29_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_29_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_29_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_29_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL14; + + /* 0x13C : GPIO_CFGCTL15 */ + union { + struct + { + uint32_t reg_gpio_30_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_30_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_30_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_30_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_30_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_30_func_sel : 5; /* [12: 8], r/w, 0xb */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_31_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_31_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_31_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_31_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_31_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_31_func_sel : 5; /* [28:24], r/w, 0xb */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL15; + + /* 0x140 : GPIO_CFGCTL16 */ + union { + struct + { + uint32_t reg_gpio_32_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_32_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_32_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_32_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_32_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t reg_gpio_33_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_33_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_33_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_33_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_33_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL16; + + /* 0x144 : GPIO_CFGCTL17 */ + union { + struct + { + uint32_t reg_gpio_34_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_34_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_34_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_34_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_34_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t reg_gpio_35_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_35_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_35_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_35_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_35_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL17; + + /* 0x148 : GPIO_CFGCTL18 */ + union { + struct + { + uint32_t reg_gpio_36_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_36_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_36_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_36_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_36_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t reg_gpio_37_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_37_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_37_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_37_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_37_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL18; + + /* 0x14c reserved */ + uint8_t RESERVED0x14c[52]; + + /* 0x180 : GPIO_CFGCTL30 */ + union { + struct + { + uint32_t reg_gpio_0_i : 1; /* [ 0], r, 0x0 */ + uint32_t reg_gpio_1_i : 1; /* [ 1], r, 0x0 */ + uint32_t reg_gpio_2_i : 1; /* [ 2], r, 0x0 */ + uint32_t reg_gpio_3_i : 1; /* [ 3], r, 0x0 */ + uint32_t reg_gpio_4_i : 1; /* [ 4], r, 0x0 */ + uint32_t reg_gpio_5_i : 1; /* [ 5], r, 0x0 */ + uint32_t reg_gpio_6_i : 1; /* [ 6], r, 0x0 */ + uint32_t reg_gpio_7_i : 1; /* [ 7], r, 0x0 */ + uint32_t reg_gpio_8_i : 1; /* [ 8], r, 0x0 */ + uint32_t reg_gpio_9_i : 1; /* [ 9], r, 0x0 */ + uint32_t reg_gpio_10_i : 1; /* [ 10], r, 0x0 */ + uint32_t reg_gpio_11_i : 1; /* [ 11], r, 0x0 */ + uint32_t reg_gpio_12_i : 1; /* [ 12], r, 0x0 */ + uint32_t reg_gpio_13_i : 1; /* [ 13], r, 0x0 */ + uint32_t reg_gpio_14_i : 1; /* [ 14], r, 0x0 */ + uint32_t reg_gpio_15_i : 1; /* [ 15], r, 0x0 */ + uint32_t reg_gpio_16_i : 1; /* [ 16], r, 0x0 */ + uint32_t reg_gpio_17_i : 1; /* [ 17], r, 0x0 */ + uint32_t reg_gpio_18_i : 1; /* [ 18], r, 0x0 */ + uint32_t reg_gpio_19_i : 1; /* [ 19], r, 0x0 */ + uint32_t reg_gpio_20_i : 1; /* [ 20], r, 0x0 */ + uint32_t reg_gpio_21_i : 1; /* [ 21], r, 0x0 */ + uint32_t reg_gpio_22_i : 1; /* [ 22], r, 0x0 */ + uint32_t reg_gpio_23_i : 1; /* [ 23], r, 0x0 */ + uint32_t reg_gpio_24_i : 1; /* [ 24], r, 0x0 */ + uint32_t reg_gpio_25_i : 1; /* [ 25], r, 0x0 */ + uint32_t reg_gpio_26_i : 1; /* [ 26], r, 0x0 */ + uint32_t reg_gpio_27_i : 1; /* [ 27], r, 0x0 */ + uint32_t reg_gpio_28_i : 1; /* [ 28], r, 0x0 */ + uint32_t reg_gpio_29_i : 1; /* [ 29], r, 0x0 */ + uint32_t reg_gpio_30_i : 1; /* [ 30], r, 0x0 */ + uint32_t reg_gpio_31_i : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL30; + + /* 0x184 : GPIO_CFGCTL31 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL31; + + /* 0x188 : GPIO_CFGCTL32 */ + union { + struct + { + uint32_t reg_gpio_0_o : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_gpio_1_o : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_gpio_2_o : 1; /* [ 2], r/w, 0x0 */ + uint32_t reg_gpio_3_o : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_gpio_4_o : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_5_o : 1; /* [ 5], r/w, 0x0 */ + uint32_t reg_gpio_6_o : 1; /* [ 6], r/w, 0x0 */ + uint32_t reg_gpio_7_o : 1; /* [ 7], r/w, 0x0 */ + uint32_t reg_gpio_8_o : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_gpio_9_o : 1; /* [ 9], r/w, 0x0 */ + uint32_t reg_gpio_10_o : 1; /* [ 10], r/w, 0x0 */ + uint32_t reg_gpio_11_o : 1; /* [ 11], r/w, 0x0 */ + uint32_t reg_gpio_12_o : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_gpio_13_o : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_gpio_14_o : 1; /* [ 14], r/w, 0x0 */ + uint32_t reg_gpio_15_o : 1; /* [ 15], r/w, 0x0 */ + uint32_t reg_gpio_16_o : 1; /* [ 16], r/w, 0x0 */ + uint32_t reg_gpio_17_o : 1; /* [ 17], r/w, 0x0 */ + uint32_t reg_gpio_18_o : 1; /* [ 18], r/w, 0x0 */ + uint32_t reg_gpio_19_o : 1; /* [ 19], r/w, 0x0 */ + uint32_t reg_gpio_20_o : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_o : 1; /* [ 21], r/w, 0x0 */ + uint32_t reg_gpio_22_o : 1; /* [ 22], r/w, 0x0 */ + uint32_t reg_gpio_23_o : 1; /* [ 23], r/w, 0x0 */ + uint32_t reg_gpio_24_o : 1; /* [ 24], r/w, 0x0 */ + uint32_t reg_gpio_25_o : 1; /* [ 25], r/w, 0x0 */ + uint32_t reg_gpio_26_o : 1; /* [ 26], r/w, 0x0 */ + uint32_t reg_gpio_27_o : 1; /* [ 27], r/w, 0x0 */ + uint32_t reg_gpio_28_o : 1; /* [ 28], r/w, 0x0 */ + uint32_t reg_gpio_29_o : 1; /* [ 29], r/w, 0x0 */ + uint32_t reg_gpio_30_o : 1; /* [ 30], r/w, 0x0 */ + uint32_t reg_gpio_31_o : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL32; + + /* 0x18C : GPIO_CFGCTL33 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL33; + + /* 0x190 : GPIO_CFGCTL34 */ + union { + struct + { + uint32_t reg_gpio_0_oe : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_gpio_1_oe : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_gpio_2_oe : 1; /* [ 2], r/w, 0x0 */ + uint32_t reg_gpio_3_oe : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_gpio_4_oe : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_5_oe : 1; /* [ 5], r/w, 0x0 */ + uint32_t reg_gpio_6_oe : 1; /* [ 6], r/w, 0x0 */ + uint32_t reg_gpio_7_oe : 1; /* [ 7], r/w, 0x0 */ + uint32_t reg_gpio_8_oe : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_gpio_9_oe : 1; /* [ 9], r/w, 0x0 */ + uint32_t reg_gpio_10_oe : 1; /* [ 10], r/w, 0x0 */ + uint32_t reg_gpio_11_oe : 1; /* [ 11], r/w, 0x0 */ + uint32_t reg_gpio_12_oe : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_gpio_13_oe : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_gpio_14_oe : 1; /* [ 14], r/w, 0x0 */ + uint32_t reg_gpio_15_oe : 1; /* [ 15], r/w, 0x0 */ + uint32_t reg_gpio_16_oe : 1; /* [ 16], r/w, 0x0 */ + uint32_t reg_gpio_17_oe : 1; /* [ 17], r/w, 0x0 */ + uint32_t reg_gpio_18_oe : 1; /* [ 18], r/w, 0x0 */ + uint32_t reg_gpio_19_oe : 1; /* [ 19], r/w, 0x0 */ + uint32_t reg_gpio_20_oe : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_oe : 1; /* [ 21], r/w, 0x0 */ + uint32_t reg_gpio_22_oe : 1; /* [ 22], r/w, 0x0 */ + uint32_t reg_gpio_23_oe : 1; /* [ 23], r/w, 0x0 */ + uint32_t reg_gpio_24_oe : 1; /* [ 24], r/w, 0x0 */ + uint32_t reg_gpio_25_oe : 1; /* [ 25], r/w, 0x0 */ + uint32_t reg_gpio_26_oe : 1; /* [ 26], r/w, 0x0 */ + uint32_t reg_gpio_27_oe : 1; /* [ 27], r/w, 0x0 */ + uint32_t reg_gpio_28_oe : 1; /* [ 28], r/w, 0x0 */ + uint32_t reg_gpio_29_oe : 1; /* [ 29], r/w, 0x0 */ + uint32_t reg_gpio_30_oe : 1; /* [ 30], r/w, 0x0 */ + uint32_t reg_gpio_31_oe : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL34; + + /* 0x194 : GPIO_CFGCTL35 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL35; + + /* 0x198 reserved */ + uint8_t RESERVED0x198[8]; + + /* 0x1A0 : GPIO_INT_MASK1 */ + union { + struct + { + uint32_t reg_gpio_int_mask1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } GPIO_INT_MASK1; + + /* 0x1a4 reserved */ + uint8_t RESERVED0x1a4[4]; + + /* 0x1A8 : GPIO_INT_STAT1 */ + union { + struct + { + uint32_t gpio_int_stat1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_STAT1; + + /* 0x1ac reserved */ + uint8_t RESERVED0x1ac[4]; + + /* 0x1B0 : GPIO_INT_CLR1 */ + union { + struct + { + uint32_t reg_gpio_int_clr1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_CLR1; + + /* 0x1b4 reserved */ + uint8_t RESERVED0x1b4[12]; + + /* 0x1C0 : GPIO_INT_MODE_SET1 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set1 : 30; /* [29: 0], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET1; + + /* 0x1C4 : GPIO_INT_MODE_SET2 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set2 : 30; /* [29: 0], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET2; + + /* 0x1C8 : GPIO_INT_MODE_SET3 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set3 : 30; /* [29: 0], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET3; + + /* 0x1CC : GPIO_INT_MODE_SET4 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set4 : 6; /* [ 5: 0], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET4; + + /* 0x1D0 : GPIO_INT2_MASK1 */ + union { + struct + { + uint32_t reg_gpio_int2_mask1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } GPIO_INT2_MASK1; + + /* 0x1D4 : GPIO_INT2_STAT1 */ + union { + struct + { + uint32_t gpio_int2_stat1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT2_STAT1; + + /* 0x1D8 : GPIO_INT2_CLR1 */ + union { + struct + { + uint32_t reg_gpio_int2_clr1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT2_CLR1; + + /* 0x1DC : GPIO_INT2_MODE_SET1 */ + union { + struct + { + uint32_t reg_gpio_int2_mode_set1 : 30; /* [29: 0], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT2_MODE_SET1; + + /* 0x1E0 : GPIO_INT2_MODE_SET2 */ + union { + struct + { + uint32_t reg_gpio_int2_mode_set2 : 30; /* [29: 0], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT2_MODE_SET2; + + /* 0x1E4 : GPIO_INT2_MODE_SET3 */ + union { + struct + { + uint32_t reg_gpio_int2_mode_set3 : 30; /* [29: 0], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT2_MODE_SET3; + + /* 0x1E8 : GPIO_INT2_MODE_SET4 */ + union { + struct + { + uint32_t reg_gpio_int2_mode_set4 : 6; /* [ 5: 0], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT2_MODE_SET4; + + /* 0x1ec reserved */ + uint8_t RESERVED0x1ec[20]; + + /* 0x200 : dll */ + union { + struct + { + uint32_t dtest_en_dll_refclk : 1; /* [ 0], r/w, 0x0 */ + uint32_t dtest_en_dll_outclk : 1; /* [ 1], r/w, 0x0 */ + uint32_t ten_dll : 1; /* [ 2], r/w, 0x0 */ + uint32_t dll_clk_mmdiv_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t dll_clk_288M_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t dll_clk_144M_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t dll_clk_96M_en : 1; /* [ 6], r/w, 0x1 */ + uint32_t dll_clk_57p6M_en : 1; /* [ 7], r/w, 0x1 */ + uint32_t dll_vctrl_sel : 3; /* [10: 8], r/w, 0x4 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t dll_prechg_sel : 1; /* [ 12], r/w, 0x0 */ + uint32_t dll_prechg_reg : 1; /* [ 13], r/w, 0x1 */ + uint32_t dll_prechg_en : 1; /* [ 14], r/w, 0x1 */ + uint32_t dll_vctrl_force_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t dll_post_div : 4; /* [19:16], r/w, 0x2 */ + uint32_t dll_delay_sel : 2; /* [21:20], r/w, 0x1 */ + uint32_t dll_cp_op_en : 1; /* [ 22], r/w, 0x1 */ + uint32_t dll_cp_hiz : 1; /* [ 23], r/w, 0x0 */ + uint32_t reserved_24_27 : 4; /* [27:24], rsvd, 0x0 */ + uint32_t dll_refclk_sel : 1; /* [ 28], r/w, 0x0 */ + uint32_t dll_reset : 1; /* [ 29], r/w, 0x1 */ + uint32_t pu_dll : 1; /* [ 30], r/w, 0x0 */ + uint32_t ppu_dll : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } dll; + + /* 0x204 reserved */ + uint8_t RESERVED0x204[32]; + + /* 0x224 : led_driver */ + union { + struct + { + uint32_t led_din_reg : 1; /* [ 0], r/w, 0x0 */ + uint32_t led_din_sel : 1; /* [ 1], r/w, 0x0 */ + uint32_t led_din_polarity_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t leddrv_ibias : 4; /* [ 7: 4], r/w, 0x8 */ + uint32_t ir_rx_gpio_sel : 4; /* [11: 8], r/w, 0x0 */ + uint32_t reserved_12_27 : 16; /* [27:12], rsvd, 0x0 */ + uint32_t leddrv_out_en : 2; /* [29:28], r/w, 0x3 */ + uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ + uint32_t pu_leddrv : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } led_driver; + + /* 0x228 : usb_xcvr */ + union { + struct + { + uint32_t usb_ldo_vfb : 3; /* [ 2: 0], r/w, 0x3 */ + uint32_t pu_usb_ldo : 1; /* [ 3], r/w, 0x0 */ + uint32_t usb_rout_nmos : 3; /* [ 6: 4], r/w, 0x3 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t usb_rout_pmos : 3; /* [10: 8], r/w, 0x3 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t usb_oeb_sel : 1; /* [ 12], rw, 0x0 */ + uint32_t usb_oeb_reg : 1; /* [ 13], rw, 0x1 */ + uint32_t usb_oeb : 1; /* [ 14], r, 0x1 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t usb_data_convert : 1; /* [ 16], rw, 0x0 */ + uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ + uint32_t usb_enum : 1; /* [ 20], r/w, 0x0 */ + uint32_t usb_spd : 1; /* [ 21], r/w, 0x1 */ + uint32_t usb_sus : 1; /* [ 22], r/w, 0x0 */ + uint32_t pu_usb : 1; /* [ 23], r/w, 0x0 */ + uint32_t usb_bd : 1; /* [ 24], r, 0x0 */ + uint32_t usb_vim : 1; /* [ 25], r, 0x0 */ + uint32_t usb_vip : 1; /* [ 26], r, 0x0 */ + uint32_t usb_rcv : 1; /* [ 27], r, 0x0 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } usb_xcvr; + + /* 0x22C : usb_xcvr_config */ + union { + struct + { + uint32_t usb_v_hys_m : 2; /* [ 1: 0], r/w, 0x1 */ + uint32_t usb_v_hys_p : 2; /* [ 3: 2], r/w, 0x1 */ + uint32_t usb_bd_vth : 3; /* [ 6: 4], r/w, 0x1 */ + uint32_t reg_usb_use_xcvr : 1; /* [ 7], r/w, 0x1 */ + uint32_t usb_str_drv : 3; /* [10: 8], r/w, 0x0 */ + uint32_t reg_usb_use_ctrl : 1; /* [ 11], r/w, 0x1 */ + uint32_t usb_res_pullup_tune : 3; /* [14:12], r/w, 0x2 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t usb_slewrate_m_fall : 3; /* [18:16], r/w, 0x3 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t usb_slewrate_m_rise : 3; /* [22:20], r/w, 0x4 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t usb_slewrate_p_fall : 3; /* [26:24], r/w, 0x3 */ + uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */ + uint32_t usb_slewrate_p_rise : 3; /* [30:28], r/w, 0x4 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } usb_xcvr_config; + + /* 0x230 reserved */ + uint8_t RESERVED0x230[216]; + + /* 0x308 : gpdac_ctrl */ + union { + struct + { + uint32_t gpdaca_rstn_ana : 1; /* [ 0], r/w, 0x1 */ + uint32_t gpdacb_rstn_ana : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_6 : 5; /* [ 6: 2], rsvd, 0x0 */ + uint32_t gpdac_test_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpdac_ref_sel : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpdac_test_sel : 3; /* [11: 9], r/w, 0x0 */ + uint32_t reserved_12_23 : 12; /* [23:12], rsvd, 0x0 */ + uint32_t gpdac_reserved : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } gpdac_ctrl; + + /* 0x30C : gpdac_actrl */ + union { + struct + { + uint32_t gpdac_a_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpdac_ioa_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */ + uint32_t gpdac_a_rng : 2; /* [19:18], r/w, 0x3 */ + uint32_t gpdac_a_outmux : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_actrl; + + /* 0x310 : gpdac_bctrl */ + union { + struct + { + uint32_t gpdac_b_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpdac_iob_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */ + uint32_t gpdac_b_rng : 2; /* [19:18], r/w, 0x3 */ + uint32_t gpdac_b_outmux : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_bctrl; + + /* 0x314 : gpdac_data */ + union { + struct + { + uint32_t gpdac_b_data : 10; /* [ 9: 0], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t gpdac_a_data : 10; /* [25:16], r/w, 0x0 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_data; + + /* 0x318 reserved */ + uint8_t RESERVED0x318[2792]; + + /* 0xE00 : chip_revision */ + union { + struct + { + uint32_t chip_rev : 4; /* [ 3: 0], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } chip_revision; + + /* 0xe04 reserved */ + uint8_t RESERVED0xe04[252]; + + /* 0xF00 : tzc_glb_ctrl_0 */ + union { + struct + { + uint32_t tzc_glb_swrst_s00_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_swrst_s01_lock : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t tzc_glb_swrst_s30_lock : 1; /* [ 8], r, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t tzc_glb_ctrl_pwron_rst_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_ctrl_cpu_reset_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_ctrl_sys_reset_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [ 15], r, 0x0 */ + uint32_t reserved_16_24 : 9; /* [24:16], rsvd, 0x0 */ + uint32_t tzc_glb_misc_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_sram_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_l2c_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_bmx_lock : 1; /* [ 28], r, 0x0 */ + uint32_t tzc_glb_dbg_lock : 1; /* [ 29], r, 0x0 */ + uint32_t tzc_glb_mbist_lock : 1; /* [ 30], r, 0x0 */ + uint32_t tzc_glb_clk_lock : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_0; + + /* 0xF04 : tzc_glb_ctrl_1 */ + union { + struct + { + uint32_t tzc_glb_swrst_s20_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_swrst_s21_lock : 1; /* [ 1], r, 0x0 */ + uint32_t tzc_glb_swrst_s22_lock : 1; /* [ 2], r, 0x0 */ + uint32_t tzc_glb_swrst_s23_lock : 1; /* [ 3], r, 0x0 */ + uint32_t tzc_glb_swrst_s24_lock : 1; /* [ 4], r, 0x0 */ + uint32_t tzc_glb_swrst_s25_lock : 1; /* [ 5], r, 0x0 */ + uint32_t tzc_glb_swrst_s26_lock : 1; /* [ 6], r, 0x0 */ + uint32_t tzc_glb_swrst_s27_lock : 1; /* [ 7], r, 0x0 */ + uint32_t tzc_glb_swrst_s28_lock : 1; /* [ 8], r, 0x0 */ + uint32_t tzc_glb_swrst_s29_lock : 1; /* [ 9], r, 0x0 */ + uint32_t tzc_glb_swrst_s2a_lock : 1; /* [ 10], r, 0x0 */ + uint32_t tzc_glb_swrst_s2b_lock : 1; /* [ 11], r, 0x0 */ + uint32_t tzc_glb_swrst_s2c_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_swrst_s2d_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_swrst_s2e_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_swrst_s2f_lock : 1; /* [ 15], r, 0x0 */ + uint32_t tzc_glb_swrst_s10_lock : 1; /* [ 16], r, 0x0 */ + uint32_t tzc_glb_swrst_s11_lock : 1; /* [ 17], r, 0x0 */ + uint32_t tzc_glb_swrst_s12_lock : 1; /* [ 18], r, 0x0 */ + uint32_t tzc_glb_swrst_s13_lock : 1; /* [ 19], r, 0x0 */ + uint32_t tzc_glb_swrst_s14_lock : 1; /* [ 20], r, 0x0 */ + uint32_t tzc_glb_swrst_s15_lock : 1; /* [ 21], r, 0x0 */ + uint32_t tzc_glb_swrst_s16_lock : 1; /* [ 22], r, 0x0 */ + uint32_t tzc_glb_swrst_s17_lock : 1; /* [ 23], r, 0x0 */ + uint32_t tzc_glb_swrst_s18_lock : 1; /* [ 24], r, 0x0 */ + uint32_t tzc_glb_swrst_s19_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_swrst_s1a_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_swrst_s1b_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_swrst_s1c_lock : 1; /* [ 28], r, 0x0 */ + uint32_t tzc_glb_swrst_s1d_lock : 1; /* [ 29], r, 0x0 */ + uint32_t tzc_glb_swrst_s1e_lock : 1; /* [ 30], r, 0x0 */ + uint32_t tzc_glb_swrst_s1f_lock : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_1; + + /* 0xF08 : tzc_glb_ctrl_2 */ + union { + struct + { + uint32_t tzc_glb_gpio_0_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_gpio_1_lock : 1; /* [ 1], r, 0x0 */ + uint32_t tzc_glb_gpio_2_lock : 1; /* [ 2], r, 0x0 */ + uint32_t tzc_glb_gpio_3_lock : 1; /* [ 3], r, 0x0 */ + uint32_t tzc_glb_gpio_4_lock : 1; /* [ 4], r, 0x0 */ + uint32_t tzc_glb_gpio_5_lock : 1; /* [ 5], r, 0x0 */ + uint32_t tzc_glb_gpio_6_lock : 1; /* [ 6], r, 0x0 */ + uint32_t tzc_glb_gpio_7_lock : 1; /* [ 7], r, 0x0 */ + uint32_t tzc_glb_gpio_8_lock : 1; /* [ 8], r, 0x0 */ + uint32_t tzc_glb_gpio_9_lock : 1; /* [ 9], r, 0x0 */ + uint32_t tzc_glb_gpio_10_lock : 1; /* [ 10], r, 0x0 */ + uint32_t tzc_glb_gpio_11_lock : 1; /* [ 11], r, 0x0 */ + uint32_t tzc_glb_gpio_12_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_gpio_13_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_gpio_14_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_gpio_15_lock : 1; /* [ 15], r, 0x0 */ + uint32_t tzc_glb_gpio_16_lock : 1; /* [ 16], r, 0x0 */ + uint32_t tzc_glb_gpio_17_lock : 1; /* [ 17], r, 0x0 */ + uint32_t tzc_glb_gpio_18_lock : 1; /* [ 18], r, 0x0 */ + uint32_t tzc_glb_gpio_19_lock : 1; /* [ 19], r, 0x0 */ + uint32_t tzc_glb_gpio_20_lock : 1; /* [ 20], r, 0x0 */ + uint32_t tzc_glb_gpio_21_lock : 1; /* [ 21], r, 0x0 */ + uint32_t tzc_glb_gpio_22_lock : 1; /* [ 22], r, 0x0 */ + uint32_t tzc_glb_gpio_23_lock : 1; /* [ 23], r, 0x0 */ + uint32_t tzc_glb_gpio_24_lock : 1; /* [ 24], r, 0x0 */ + uint32_t tzc_glb_gpio_25_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_gpio_26_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_gpio_27_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_gpio_28_lock : 1; /* [ 28], r, 0x0 */ + uint32_t tzc_glb_gpio_29_lock : 1; /* [ 29], r, 0x0 */ + uint32_t tzc_glb_gpio_30_lock : 1; /* [ 30], r, 0x0 */ + uint32_t tzc_glb_gpio_31_lock : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_2; + + /* 0xF0C : tzc_glb_ctrl_3 */ + union { + struct + { + uint32_t tzc_glb_gpio_32_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_gpio_33_lock : 1; /* [ 1], r, 0x0 */ + uint32_t tzc_glb_gpio_34_lock : 1; /* [ 2], r, 0x0 */ + uint32_t tzc_glb_gpio_35_lock : 1; /* [ 3], r, 0x0 */ + uint32_t tzc_glb_gpio_36_lock : 1; /* [ 4], r, 0x0 */ + uint32_t tzc_glb_gpio_37_lock : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_3; +}; + +typedef volatile struct glb_reg glb_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : GPIO_CFGCTL */ +#define GLB_GPIO_CFGCTL_OFFSET (0x0) +#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE +#define GLB_REG_GPIO_0_IE_POS (0U) +#define GLB_REG_GPIO_0_IE_LEN (1U) +#define GLB_REG_GPIO_0_IE_MSK (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) +#define GLB_REG_GPIO_0_IE_UMSK (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) +#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT +#define GLB_REG_GPIO_0_SMT_POS (1U) +#define GLB_REG_GPIO_0_SMT_LEN (1U) +#define GLB_REG_GPIO_0_SMT_MSK (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) +#define GLB_REG_GPIO_0_SMT_UMSK (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) +#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV +#define GLB_REG_GPIO_0_DRV_POS (2U) +#define GLB_REG_GPIO_0_DRV_LEN (2U) +#define GLB_REG_GPIO_0_DRV_MSK (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) +#define GLB_REG_GPIO_0_DRV_UMSK (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) +#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU +#define GLB_REG_GPIO_0_PU_POS (4U) +#define GLB_REG_GPIO_0_PU_LEN (1U) +#define GLB_REG_GPIO_0_PU_MSK (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) +#define GLB_REG_GPIO_0_PU_UMSK (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) +#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD +#define GLB_REG_GPIO_0_PD_POS (5U) +#define GLB_REG_GPIO_0_PD_LEN (1U) +#define GLB_REG_GPIO_0_PD_MSK (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) +#define GLB_REG_GPIO_0_PD_UMSK (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) +#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL +#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_0_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) +#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)) +#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE +#define GLB_REG_GPIO_1_IE_POS (16U) +#define GLB_REG_GPIO_1_IE_LEN (1U) +#define GLB_REG_GPIO_1_IE_MSK (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) +#define GLB_REG_GPIO_1_IE_UMSK (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) +#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT +#define GLB_REG_GPIO_1_SMT_POS (17U) +#define GLB_REG_GPIO_1_SMT_LEN (1U) +#define GLB_REG_GPIO_1_SMT_MSK (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) +#define GLB_REG_GPIO_1_SMT_UMSK (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) +#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV +#define GLB_REG_GPIO_1_DRV_POS (18U) +#define GLB_REG_GPIO_1_DRV_LEN (2U) +#define GLB_REG_GPIO_1_DRV_MSK (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) +#define GLB_REG_GPIO_1_DRV_UMSK (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) +#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU +#define GLB_REG_GPIO_1_PU_POS (20U) +#define GLB_REG_GPIO_1_PU_LEN (1U) +#define GLB_REG_GPIO_1_PU_MSK (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) +#define GLB_REG_GPIO_1_PU_UMSK (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) +#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD +#define GLB_REG_GPIO_1_PD_POS (21U) +#define GLB_REG_GPIO_1_PD_LEN (1U) +#define GLB_REG_GPIO_1_PD_MSK (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) +#define GLB_REG_GPIO_1_PD_UMSK (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) +#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL +#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_1_FUNC_SEL_LEN (5U) +#define GLB_REG_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) +#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)) + +struct glb_gpio_reg { + /* 0x0 : GPIO_CFGCTL */ + union { + struct + { + uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_0_func_sel : 5; /* [12: 8], r/w, 0xe */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_1_func_sel : 5; /* [28:24], r/w, 0xe */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL; +}; + +typedef volatile struct glb_gpio_reg glb_gpio_reg_t; + +#define GLB_GPIO_OFFSET 0x100 +#define GLB_GPIO_INPUT_OFFSET 0x180 +#define GLB_GPIO_OUTPUT_OFFSET 0x188 +#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190 + +#endif /* __GLB_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/gpip_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/gpip_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..13a5e8920136f20c0b7ba897e6633c14f9702aa2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/gpip_reg.h @@ -0,0 +1,317 @@ +/** + ****************************************************************************** + * @file gpip_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __GPIP_REG_H__ +#define __GPIP_REG_H__ + +#include "bl702.h" + +/* 0x0 : gpadc_config */ +#define GPIP_GPADC_CONFIG_OFFSET (0x0) +#define GPIP_GPADC_DMA_EN GPIP_GPADC_DMA_EN +#define GPIP_GPADC_DMA_EN_POS (0U) +#define GPIP_GPADC_DMA_EN_LEN (1U) +#define GPIP_GPADC_DMA_EN_MSK (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS) +#define GPIP_GPADC_DMA_EN_UMSK (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)) +#define GPIP_GPADC_FIFO_CLR GPIP_GPADC_FIFO_CLR +#define GPIP_GPADC_FIFO_CLR_POS (1U) +#define GPIP_GPADC_FIFO_CLR_LEN (1U) +#define GPIP_GPADC_FIFO_CLR_MSK (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS) +#define GPIP_GPADC_FIFO_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)) +#define GPIP_GPADC_FIFO_NE GPIP_GPADC_FIFO_NE +#define GPIP_GPADC_FIFO_NE_POS (2U) +#define GPIP_GPADC_FIFO_NE_LEN (1U) +#define GPIP_GPADC_FIFO_NE_MSK (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS) +#define GPIP_GPADC_FIFO_NE_UMSK (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)) +#define GPIP_GPADC_FIFO_FULL GPIP_GPADC_FIFO_FULL +#define GPIP_GPADC_FIFO_FULL_POS (3U) +#define GPIP_GPADC_FIFO_FULL_LEN (1U) +#define GPIP_GPADC_FIFO_FULL_MSK (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS) +#define GPIP_GPADC_FIFO_FULL_UMSK (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)) +#define GPIP_GPADC_RDY GPIP_GPADC_RDY +#define GPIP_GPADC_RDY_POS (4U) +#define GPIP_GPADC_RDY_LEN (1U) +#define GPIP_GPADC_RDY_MSK (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS) +#define GPIP_GPADC_RDY_UMSK (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)) +#define GPIP_GPADC_FIFO_OVERRUN GPIP_GPADC_FIFO_OVERRUN +#define GPIP_GPADC_FIFO_OVERRUN_POS (5U) +#define GPIP_GPADC_FIFO_OVERRUN_LEN (1U) +#define GPIP_GPADC_FIFO_OVERRUN_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS) +#define GPIP_GPADC_FIFO_OVERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)) +#define GPIP_GPADC_FIFO_UNDERRUN GPIP_GPADC_FIFO_UNDERRUN +#define GPIP_GPADC_FIFO_UNDERRUN_POS (6U) +#define GPIP_GPADC_FIFO_UNDERRUN_LEN (1U) +#define GPIP_GPADC_FIFO_UNDERRUN_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS) +#define GPIP_GPADC_FIFO_UNDERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)) +#define GPIP_GPADC_FIFO_RDY GPIP_GPADC_FIFO_RDY +#define GPIP_GPADC_FIFO_RDY_POS (7U) +#define GPIP_GPADC_FIFO_RDY_LEN (1U) +#define GPIP_GPADC_FIFO_RDY_MSK (((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS) +#define GPIP_GPADC_FIFO_RDY_UMSK (~(((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS)) +#define GPIP_GPADC_RDY_CLR GPIP_GPADC_RDY_CLR +#define GPIP_GPADC_RDY_CLR_POS (8U) +#define GPIP_GPADC_RDY_CLR_LEN (1U) +#define GPIP_GPADC_RDY_CLR_MSK (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS) +#define GPIP_GPADC_RDY_CLR_UMSK (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)) +#define GPIP_GPADC_FIFO_OVERRUN_CLR GPIP_GPADC_FIFO_OVERRUN_CLR +#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS (9U) +#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN (1U) +#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS) +#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)) +#define GPIP_GPADC_FIFO_UNDERRUN_CLR GPIP_GPADC_FIFO_UNDERRUN_CLR +#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS (10U) +#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN (1U) +#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS) +#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)) +#define GPIP_GPADC_RDY_MASK GPIP_GPADC_RDY_MASK +#define GPIP_GPADC_RDY_MASK_POS (12U) +#define GPIP_GPADC_RDY_MASK_LEN (1U) +#define GPIP_GPADC_RDY_MASK_MSK (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS) +#define GPIP_GPADC_RDY_MASK_UMSK (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)) +#define GPIP_GPADC_FIFO_OVERRUN_MASK GPIP_GPADC_FIFO_OVERRUN_MASK +#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS (13U) +#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN (1U) +#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS) +#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)) +#define GPIP_GPADC_FIFO_UNDERRUN_MASK GPIP_GPADC_FIFO_UNDERRUN_MASK +#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS (14U) +#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN (1U) +#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS) +#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)) +#define GPIP_GPADC_FIFO_RDY_MASK GPIP_GPADC_FIFO_RDY_MASK +#define GPIP_GPADC_FIFO_RDY_MASK_POS (15U) +#define GPIP_GPADC_FIFO_RDY_MASK_LEN (1U) +#define GPIP_GPADC_FIFO_RDY_MASK_MSK (((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS) +#define GPIP_GPADC_FIFO_RDY_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS)) +#define GPIP_GPADC_FIFO_DATA_COUNT GPIP_GPADC_FIFO_DATA_COUNT +#define GPIP_GPADC_FIFO_DATA_COUNT_POS (16U) +#define GPIP_GPADC_FIFO_DATA_COUNT_LEN (6U) +#define GPIP_GPADC_FIFO_DATA_COUNT_MSK (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS) +#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)) +#define GPIP_GPADC_FIFO_THL GPIP_GPADC_FIFO_THL +#define GPIP_GPADC_FIFO_THL_POS (22U) +#define GPIP_GPADC_FIFO_THL_LEN (2U) +#define GPIP_GPADC_FIFO_THL_MSK (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS) +#define GPIP_GPADC_FIFO_THL_UMSK (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)) + +/* 0x4 : gpadc_dma_rdata */ +#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4) +#define GPIP_GPADC_DMA_RDATA GPIP_GPADC_DMA_RDATA +#define GPIP_GPADC_DMA_RDATA_POS (0U) +#define GPIP_GPADC_DMA_RDATA_LEN (26U) +#define GPIP_GPADC_DMA_RDATA_MSK (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS) +#define GPIP_GPADC_DMA_RDATA_UMSK (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)) + +/* 0x40 : gpdac_config */ +#define GPIP_GPDAC_CONFIG_OFFSET (0x40) +#define GPIP_GPDAC_EN GPIP_GPDAC_EN +#define GPIP_GPDAC_EN_POS (0U) +#define GPIP_GPDAC_EN_LEN (1U) +#define GPIP_GPDAC_EN_MSK (((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS) +#define GPIP_GPDAC_EN_UMSK (~(((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS)) +#define GPIP_GPDAC_EN2 GPIP_GPDAC_EN2 +#define GPIP_GPDAC_EN2_POS (1U) +#define GPIP_GPDAC_EN2_LEN (1U) +#define GPIP_GPDAC_EN2_MSK (((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS) +#define GPIP_GPDAC_EN2_UMSK (~(((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS)) +#define GPIP_DSM_MODE GPIP_DSM_MODE +#define GPIP_DSM_MODE_POS (4U) +#define GPIP_DSM_MODE_LEN (2U) +#define GPIP_DSM_MODE_MSK (((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS) +#define GPIP_DSM_MODE_UMSK (~(((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS)) +#define GPIP_GPDAC_MODE GPIP_GPDAC_MODE +#define GPIP_GPDAC_MODE_POS (8U) +#define GPIP_GPDAC_MODE_LEN (3U) +#define GPIP_GPDAC_MODE_MSK (((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS) +#define GPIP_GPDAC_MODE_UMSK (~(((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS)) +#define GPIP_GPDAC_CH_A_SEL GPIP_GPDAC_CH_A_SEL +#define GPIP_GPDAC_CH_A_SEL_POS (16U) +#define GPIP_GPDAC_CH_A_SEL_LEN (4U) +#define GPIP_GPDAC_CH_A_SEL_MSK (((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS) +#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS)) +#define GPIP_GPDAC_CH_B_SEL GPIP_GPDAC_CH_B_SEL +#define GPIP_GPDAC_CH_B_SEL_POS (20U) +#define GPIP_GPDAC_CH_B_SEL_LEN (4U) +#define GPIP_GPDAC_CH_B_SEL_MSK (((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS) +#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS)) + +/* 0x44 : gpdac_dma_config */ +#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44) +#define GPIP_GPDAC_DMA_TX_EN GPIP_GPDAC_DMA_TX_EN +#define GPIP_GPDAC_DMA_TX_EN_POS (0U) +#define GPIP_GPDAC_DMA_TX_EN_LEN (1U) +#define GPIP_GPDAC_DMA_TX_EN_MSK (((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS) +#define GPIP_GPDAC_DMA_TX_EN_UMSK (~(((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS)) +#define GPIP_GPDAC_DMA_FORMAT GPIP_GPDAC_DMA_FORMAT +#define GPIP_GPDAC_DMA_FORMAT_POS (4U) +#define GPIP_GPDAC_DMA_FORMAT_LEN (2U) +#define GPIP_GPDAC_DMA_FORMAT_MSK (((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS) +#define GPIP_GPDAC_DMA_FORMAT_UMSK (~(((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS)) + +/* 0x48 : gpdac_dma_wdata */ +#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48) +#define GPIP_GPDAC_DMA_WDATA GPIP_GPDAC_DMA_WDATA +#define GPIP_GPDAC_DMA_WDATA_POS (0U) +#define GPIP_GPDAC_DMA_WDATA_LEN (32U) +#define GPIP_GPDAC_DMA_WDATA_MSK (((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS) +#define GPIP_GPDAC_DMA_WDATA_UMSK (~(((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS)) + +/* 0x4C : gpdac_tx_fifo_status */ +#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C) +#define GPIP_TX_FIFO_EMPTY GPIP_TX_FIFO_EMPTY +#define GPIP_TX_FIFO_EMPTY_POS (0U) +#define GPIP_TX_FIFO_EMPTY_LEN (1U) +#define GPIP_TX_FIFO_EMPTY_MSK (((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS) +#define GPIP_TX_FIFO_EMPTY_UMSK (~(((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS)) +#define GPIP_TX_FIFO_FULL GPIP_TX_FIFO_FULL +#define GPIP_TX_FIFO_FULL_POS (1U) +#define GPIP_TX_FIFO_FULL_LEN (1U) +#define GPIP_TX_FIFO_FULL_MSK (((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS) +#define GPIP_TX_FIFO_FULL_UMSK (~(((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS)) +#define GPIP_TX_CS GPIP_TX_CS +#define GPIP_TX_CS_POS (2U) +#define GPIP_TX_CS_LEN (2U) +#define GPIP_TX_CS_MSK (((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS) +#define GPIP_TX_CS_UMSK (~(((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS)) +#define GPIP_TXFIFORDPTR GPIP_TXFIFORDPTR +#define GPIP_TXFIFORDPTR_POS (4U) +#define GPIP_TXFIFORDPTR_LEN (3U) +#define GPIP_TXFIFORDPTR_MSK (((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS) +#define GPIP_TXFIFORDPTR_UMSK (~(((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS)) +#define GPIP_TXFIFOWRPTR GPIP_TXFIFOWRPTR +#define GPIP_TXFIFOWRPTR_POS (8U) +#define GPIP_TXFIFOWRPTR_LEN (2U) +#define GPIP_TXFIFOWRPTR_MSK (((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS) +#define GPIP_TXFIFOWRPTR_UMSK (~(((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS)) + +struct gpip_reg { + /* 0x0 : gpadc_config */ + union { + struct + { + uint32_t gpadc_dma_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpadc_fifo_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t gpadc_fifo_ne : 1; /* [ 2], r, 0x0 */ + uint32_t gpadc_fifo_full : 1; /* [ 3], r, 0x0 */ + uint32_t gpadc_rdy : 1; /* [ 4], r, 0x0 */ + uint32_t gpadc_fifo_overrun : 1; /* [ 5], r, 0x0 */ + uint32_t gpadc_fifo_underrun : 1; /* [ 6], r, 0x0 */ + uint32_t gpadc_fifo_rdy : 1; /* [ 7], r, 0x0 */ + uint32_t gpadc_rdy_clr : 1; /* [ 8], w1c, 0x0 */ + uint32_t gpadc_fifo_overrun_clr : 1; /* [ 9], w1c, 0x0 */ + uint32_t gpadc_fifo_underrun_clr : 1; /* [ 10], w1c, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t gpadc_rdy_mask : 1; /* [ 12], r/w, 0x0 */ + uint32_t gpadc_fifo_overrun_mask : 1; /* [ 13], r/w, 0x0 */ + uint32_t gpadc_fifo_underrun_mask : 1; /* [ 14], r/w, 0x0 */ + uint32_t gpadc_fifo_rdy_mask : 1; /* [ 15], r/w, 0x1 */ + uint32_t gpadc_fifo_data_count : 6; /* [21:16], r, 0x0 */ + uint32_t gpadc_fifo_thl : 2; /* [23:22], r/w, 0x0 */ + uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_config; + + /* 0x4 : gpadc_dma_rdata */ + union { + struct + { + uint32_t gpadc_dma_rdata : 26; /* [25: 0], r, 0x0 */ + uint32_t rsvd_31_26 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_dma_rdata; + + /* 0x8 reserved */ + uint8_t RESERVED0x8[56]; + + /* 0x40 : gpdac_config */ + union { + struct + { + uint32_t gpdac_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpdac_en2 : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t dsm_mode : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t gpdac_mode : 3; /* [10: 8], r/w, 0x0 */ + uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ + uint32_t gpdac_ch_a_sel : 4; /* [19:16], r/w, 0x0 */ + uint32_t gpdac_ch_b_sel : 4; /* [23:20], r/w, 0x0 */ + uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0xd */ + } BF; + uint32_t WORD; + } gpdac_config; + + /* 0x44 : gpdac_dma_config */ + union { + struct + { + uint32_t gpdac_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t gpdac_dma_format : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_dma_config; + + /* 0x48 : gpdac_dma_wdata */ + union { + struct + { + uint32_t gpdac_dma_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } gpdac_dma_wdata; + + /* 0x4C : gpdac_tx_fifo_status */ + union { + struct + { + uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */ + uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */ + uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */ + uint32_t TxFifoRdPtr : 3; /* [ 6: 4], r, 0x4 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_tx_fifo_status; +}; + +typedef volatile struct gpip_reg gpip_reg_t; + +#endif /* __GPIP_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/hbn_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/hbn_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..26a2158ca0c86b1328d91f77966f010fc9205657 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/hbn_reg.h @@ -0,0 +1,814 @@ +/** + ****************************************************************************** + * @file hbn_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HBN_REG_H__ +#define __HBN_REG_H__ + +#include "bl702.h" + +/* 0x0 : HBN_CTL */ +#define HBN_CTL_OFFSET (0x0) +#define HBN_RTC_CTL HBN_RTC_CTL +#define HBN_RTC_CTL_POS (0U) +#define HBN_RTC_CTL_LEN (7U) +#define HBN_RTC_CTL_MSK (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS) +#define HBN_RTC_CTL_UMSK (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)) +#define HBN_MODE HBN_MODE +#define HBN_MODE_POS (7U) +#define HBN_MODE_LEN (1U) +#define HBN_MODE_MSK (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS) +#define HBN_MODE_UMSK (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)) +#define HBN_TRAP_MODE HBN_TRAP_MODE +#define HBN_TRAP_MODE_POS (8U) +#define HBN_TRAP_MODE_LEN (1U) +#define HBN_TRAP_MODE_MSK (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS) +#define HBN_TRAP_MODE_UMSK (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)) +#define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE +#define HBN_PWRDN_HBN_CORE_POS (9U) +#define HBN_PWRDN_HBN_CORE_LEN (1U) +#define HBN_PWRDN_HBN_CORE_MSK (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS) +#define HBN_PWRDN_HBN_CORE_UMSK (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)) +#define HBN_PWRDN_HBN_RTC HBN_PWRDN_HBN_RTC +#define HBN_PWRDN_HBN_RTC_POS (11U) +#define HBN_PWRDN_HBN_RTC_LEN (1U) +#define HBN_PWRDN_HBN_RTC_MSK (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS) +#define HBN_PWRDN_HBN_RTC_UMSK (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)) +#define HBN_SW_RST HBN_SW_RST +#define HBN_SW_RST_POS (12U) +#define HBN_SW_RST_LEN (1U) +#define HBN_SW_RST_MSK (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS) +#define HBN_SW_RST_UMSK (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)) +#define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11 +#define HBN_DIS_PWR_OFF_LDO11_POS (13U) +#define HBN_DIS_PWR_OFF_LDO11_LEN (1U) +#define HBN_DIS_PWR_OFF_LDO11_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS) +#define HBN_DIS_PWR_OFF_LDO11_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)) +#define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT +#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U) +#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U) +#define HBN_DIS_PWR_OFF_LDO11_RT_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS) +#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)) +#define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL +#define HBN_LDO11_RT_VOUT_SEL_POS (15U) +#define HBN_LDO11_RT_VOUT_SEL_LEN (4U) +#define HBN_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS) +#define HBN_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)) +#define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL +#define HBN_LDO11_AON_VOUT_SEL_POS (19U) +#define HBN_LDO11_AON_VOUT_SEL_LEN (4U) +#define HBN_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS) +#define HBN_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)) +#define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON +#define HBN_PU_DCDC18_AON_POS (23U) +#define HBN_PU_DCDC18_AON_LEN (1U) +#define HBN_PU_DCDC18_AON_MSK (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS) +#define HBN_PU_DCDC18_AON_UMSK (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)) +#define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION +#define HBN_RTC_DLY_OPTION_POS (24U) +#define HBN_RTC_DLY_OPTION_LEN (1U) +#define HBN_RTC_DLY_OPTION_MSK (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS) +#define HBN_RTC_DLY_OPTION_UMSK (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)) +#define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION +#define HBN_PWR_ON_OPTION_POS (25U) +#define HBN_PWR_ON_OPTION_LEN (1U) +#define HBN_PWR_ON_OPTION_MSK (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS) +#define HBN_PWR_ON_OPTION_UMSK (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)) +#define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION +#define HBN_SRAM_SLP_OPTION_POS (26U) +#define HBN_SRAM_SLP_OPTION_LEN (1U) +#define HBN_SRAM_SLP_OPTION_MSK (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS) +#define HBN_SRAM_SLP_OPTION_UMSK (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)) +#define HBN_SRAM_SLP HBN_SRAM_SLP +#define HBN_SRAM_SLP_POS (27U) +#define HBN_SRAM_SLP_LEN (1U) +#define HBN_SRAM_SLP_MSK (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS) +#define HBN_SRAM_SLP_UMSK (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)) +#define HBN_STATE HBN_STATE +#define HBN_STATE_POS (28U) +#define HBN_STATE_LEN (4U) +#define HBN_STATE_MSK (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS) +#define HBN_STATE_UMSK (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)) + +/* 0x4 : HBN_TIME_L */ +#define HBN_TIME_L_OFFSET (0x4) +#define HBN_TIME_L HBN_TIME_L +#define HBN_TIME_L_POS (0U) +#define HBN_TIME_L_LEN (32U) +#define HBN_TIME_L_MSK (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS) +#define HBN_TIME_L_UMSK (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)) + +/* 0x8 : HBN_TIME_H */ +#define HBN_TIME_H_OFFSET (0x8) +#define HBN_TIME_H HBN_TIME_H +#define HBN_TIME_H_POS (0U) +#define HBN_TIME_H_LEN (8U) +#define HBN_TIME_H_MSK (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS) +#define HBN_TIME_H_UMSK (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)) + +/* 0xC : RTC_TIME_L */ +#define HBN_RTC_TIME_L_OFFSET (0xC) +#define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L +#define HBN_RTC_TIME_LATCH_L_POS (0U) +#define HBN_RTC_TIME_LATCH_L_LEN (32U) +#define HBN_RTC_TIME_LATCH_L_MSK (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS) +#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)) + +/* 0x10 : RTC_TIME_H */ +#define HBN_RTC_TIME_H_OFFSET (0x10) +#define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H +#define HBN_RTC_TIME_LATCH_H_POS (0U) +#define HBN_RTC_TIME_LATCH_H_LEN (8U) +#define HBN_RTC_TIME_LATCH_H_MSK (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS) +#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)) +#define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH +#define HBN_RTC_TIME_LATCH_POS (31U) +#define HBN_RTC_TIME_LATCH_LEN (1U) +#define HBN_RTC_TIME_LATCH_MSK (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS) +#define HBN_RTC_TIME_LATCH_UMSK (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)) + +/* 0x14 : HBN_IRQ_MODE */ +#define HBN_IRQ_MODE_OFFSET (0x14) +#define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE +#define HBN_PIN_WAKEUP_MODE_POS (0U) +#define HBN_PIN_WAKEUP_MODE_LEN (3U) +#define HBN_PIN_WAKEUP_MODE_MSK (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS) +#define HBN_PIN_WAKEUP_MODE_UMSK (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)) +#define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK +#define HBN_PIN_WAKEUP_MASK_POS (3U) +#define HBN_PIN_WAKEUP_MASK_LEN (5U) +#define HBN_PIN_WAKEUP_MASK_MSK (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS) +#define HBN_PIN_WAKEUP_MASK_UMSK (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)) +#define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT +#define HBN_REG_AON_PAD_IE_SMT_POS (8U) +#define HBN_REG_AON_PAD_IE_SMT_LEN (5U) +#define HBN_REG_AON_PAD_IE_SMT_MSK (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS) +#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)) +#define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD +#define HBN_REG_EN_HW_PU_PD_POS (16U) +#define HBN_REG_EN_HW_PU_PD_LEN (1U) +#define HBN_REG_EN_HW_PU_PD_MSK (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS) +#define HBN_REG_EN_HW_PU_PD_UMSK (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)) +#define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN +#define HBN_IRQ_BOR_EN_POS (18U) +#define HBN_IRQ_BOR_EN_LEN (1U) +#define HBN_IRQ_BOR_EN_MSK (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS) +#define HBN_IRQ_BOR_EN_UMSK (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)) +#define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN +#define HBN_IRQ_ACOMP0_EN_POS (20U) +#define HBN_IRQ_ACOMP0_EN_LEN (2U) +#define HBN_IRQ_ACOMP0_EN_MSK (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS) +#define HBN_IRQ_ACOMP0_EN_UMSK (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)) +#define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN +#define HBN_IRQ_ACOMP1_EN_POS (22U) +#define HBN_IRQ_ACOMP1_EN_LEN (2U) +#define HBN_IRQ_ACOMP1_EN_MSK (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS) +#define HBN_IRQ_ACOMP1_EN_UMSK (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)) +#define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL +#define HBN_PIN_WAKEUP_SEL_POS (24U) +#define HBN_PIN_WAKEUP_SEL_LEN (3U) +#define HBN_PIN_WAKEUP_SEL_MSK (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS) +#define HBN_PIN_WAKEUP_SEL_UMSK (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)) +#define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN +#define HBN_PIN_WAKEUP_EN_POS (27U) +#define HBN_PIN_WAKEUP_EN_LEN (1U) +#define HBN_PIN_WAKEUP_EN_MSK (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS) +#define HBN_PIN_WAKEUP_EN_UMSK (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)) + +/* 0x18 : HBN_IRQ_STAT */ +#define HBN_IRQ_STAT_OFFSET (0x18) +#define HBN_IRQ_STAT HBN_IRQ_STAT +#define HBN_IRQ_STAT_POS (0U) +#define HBN_IRQ_STAT_LEN (32U) +#define HBN_IRQ_STAT_MSK (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS) +#define HBN_IRQ_STAT_UMSK (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)) + +/* 0x1C : HBN_IRQ_CLR */ +#define HBN_IRQ_CLR_OFFSET (0x1C) +#define HBN_IRQ_CLR HBN_IRQ_CLR +#define HBN_IRQ_CLR_POS (0U) +#define HBN_IRQ_CLR_LEN (32U) +#define HBN_IRQ_CLR_MSK (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS) +#define HBN_IRQ_CLR_UMSK (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)) + +/* 0x20 : HBN_PIR_CFG */ +#define HBN_PIR_CFG_OFFSET (0x20) +#define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL +#define HBN_PIR_HPF_SEL_POS (0U) +#define HBN_PIR_HPF_SEL_LEN (2U) +#define HBN_PIR_HPF_SEL_MSK (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS) +#define HBN_PIR_HPF_SEL_UMSK (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)) +#define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL +#define HBN_PIR_LPF_SEL_POS (2U) +#define HBN_PIR_LPF_SEL_LEN (1U) +#define HBN_PIR_LPF_SEL_MSK (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS) +#define HBN_PIR_LPF_SEL_UMSK (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)) +#define HBN_PIR_DIS HBN_PIR_DIS +#define HBN_PIR_DIS_POS (4U) +#define HBN_PIR_DIS_LEN (2U) +#define HBN_PIR_DIS_MSK (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS) +#define HBN_PIR_DIS_UMSK (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)) +#define HBN_PIR_EN HBN_PIR_EN +#define HBN_PIR_EN_POS (7U) +#define HBN_PIR_EN_LEN (1U) +#define HBN_PIR_EN_MSK (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS) +#define HBN_PIR_EN_UMSK (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)) +#define HBN_GPADC_CGEN HBN_GPADC_CGEN +#define HBN_GPADC_CGEN_POS (8U) +#define HBN_GPADC_CGEN_LEN (1U) +#define HBN_GPADC_CGEN_MSK (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS) +#define HBN_GPADC_CGEN_UMSK (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)) +#define HBN_GPADC_NOSYNC HBN_GPADC_NOSYNC +#define HBN_GPADC_NOSYNC_POS (9U) +#define HBN_GPADC_NOSYNC_LEN (1U) +#define HBN_GPADC_NOSYNC_MSK (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS) +#define HBN_GPADC_NOSYNC_UMSK (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)) + +/* 0x24 : HBN_PIR_VTH */ +#define HBN_PIR_VTH_OFFSET (0x24) +#define HBN_PIR_VTH HBN_PIR_VTH +#define HBN_PIR_VTH_POS (0U) +#define HBN_PIR_VTH_LEN (14U) +#define HBN_PIR_VTH_MSK (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS) +#define HBN_PIR_VTH_UMSK (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)) + +/* 0x28 : HBN_PIR_INTERVAL */ +#define HBN_PIR_INTERVAL_OFFSET (0x28) +#define HBN_PIR_INTERVAL HBN_PIR_INTERVAL +#define HBN_PIR_INTERVAL_POS (0U) +#define HBN_PIR_INTERVAL_LEN (12U) +#define HBN_PIR_INTERVAL_MSK (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS) +#define HBN_PIR_INTERVAL_UMSK (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)) + +/* 0x2C : HBN_MISC */ +#define HBN_MISC_OFFSET (0x2C) +#define HBN_BOR_SEL HBN_BOR_SEL +#define HBN_BOR_SEL_POS (0U) +#define HBN_BOR_SEL_LEN (1U) +#define HBN_BOR_SEL_MSK (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS) +#define HBN_BOR_SEL_UMSK (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)) +#define HBN_BOR_VTH HBN_BOR_VTH +#define HBN_BOR_VTH_POS (1U) +#define HBN_BOR_VTH_LEN (1U) +#define HBN_BOR_VTH_MSK (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS) +#define HBN_BOR_VTH_UMSK (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)) +#define HBN_PU_BOR HBN_PU_BOR +#define HBN_PU_BOR_POS (2U) +#define HBN_PU_BOR_LEN (1U) +#define HBN_PU_BOR_MSK (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS) +#define HBN_PU_BOR_UMSK (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)) +#define HBN_R_BOR_OUT HBN_R_BOR_OUT +#define HBN_R_BOR_OUT_POS (3U) +#define HBN_R_BOR_OUT_LEN (1U) +#define HBN_R_BOR_OUT_MSK (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS) +#define HBN_R_BOR_OUT_UMSK (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)) +#define HBN_FLASH_PULLUP_AON HBN_FLASH_PULLUP_AON +#define HBN_FLASH_PULLUP_AON_POS (16U) +#define HBN_FLASH_PULLUP_AON_LEN (6U) +#define HBN_FLASH_PULLUP_AON_MSK (((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS) +#define HBN_FLASH_PULLUP_AON_UMSK (~(((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS)) +#define HBN_FLASH_PULLDOWN_AON HBN_FLASH_PULLDOWN_AON +#define HBN_FLASH_PULLDOWN_AON_POS (24U) +#define HBN_FLASH_PULLDOWN_AON_LEN (6U) +#define HBN_FLASH_PULLDOWN_AON_MSK (((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS) +#define HBN_FLASH_PULLDOWN_AON_UMSK (~(((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS)) + +/* 0x30 : HBN_GLB */ +#define HBN_GLB_OFFSET (0x30) +#define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL +#define HBN_ROOT_CLK_SEL_POS (0U) +#define HBN_ROOT_CLK_SEL_LEN (2U) +#define HBN_ROOT_CLK_SEL_MSK (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS) +#define HBN_ROOT_CLK_SEL_UMSK (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)) +#define HBN_UART_CLK_SEL HBN_UART_CLK_SEL +#define HBN_UART_CLK_SEL_POS (2U) +#define HBN_UART_CLK_SEL_LEN (1U) +#define HBN_UART_CLK_SEL_MSK (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS) +#define HBN_UART_CLK_SEL_UMSK (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)) +#define HBN_F32K_SEL HBN_F32K_SEL +#define HBN_F32K_SEL_POS (3U) +#define HBN_F32K_SEL_LEN (2U) +#define HBN_F32K_SEL_MSK (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS) +#define HBN_F32K_SEL_UMSK (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)) +#define HBN_PU_RC32K HBN_PU_RC32K +#define HBN_PU_RC32K_POS (5U) +#define HBN_PU_RC32K_LEN (1U) +#define HBN_PU_RC32K_MSK (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS) +#define HBN_PU_RC32K_UMSK (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)) +#define HBN_LDO11_RT_ILOAD_SEL HBN_LDO11_RT_ILOAD_SEL +#define HBN_LDO11_RT_ILOAD_SEL_POS (6U) +#define HBN_LDO11_RT_ILOAD_SEL_LEN (2U) +#define HBN_LDO11_RT_ILOAD_SEL_MSK (((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS) +#define HBN_LDO11_RT_ILOAD_SEL_UMSK (~(((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS)) +#define HBN_RESET_EVENT HBN_RESET_EVENT +#define HBN_RESET_EVENT_POS (8U) +#define HBN_RESET_EVENT_LEN (5U) +#define HBN_RESET_EVENT_MSK (((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS) +#define HBN_RESET_EVENT_UMSK (~(((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS)) +#define HBN_CLEAR_RESET_EVENT HBN_CLEAR_RESET_EVENT +#define HBN_CLEAR_RESET_EVENT_POS (13U) +#define HBN_CLEAR_RESET_EVENT_LEN (1U) +#define HBN_CLEAR_RESET_EVENT_MSK (((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS) +#define HBN_CLEAR_RESET_EVENT_UMSK (~(((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS)) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)) +#define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL +#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U) +#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U) +#define HBN_SW_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS) +#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)) +#define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL +#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U) +#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U) +#define HBN_SW_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS) +#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)) + +/* 0x34 : HBN_SRAM */ +#define HBN_SRAM_OFFSET (0x34) +#define HBN_RETRAM_EMA HBN_RETRAM_EMA +#define HBN_RETRAM_EMA_POS (0U) +#define HBN_RETRAM_EMA_LEN (3U) +#define HBN_RETRAM_EMA_MSK (((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS) +#define HBN_RETRAM_EMA_UMSK (~(((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS)) +#define HBN_RETRAM_EMAW HBN_RETRAM_EMAW +#define HBN_RETRAM_EMAW_POS (3U) +#define HBN_RETRAM_EMAW_LEN (2U) +#define HBN_RETRAM_EMAW_MSK (((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS) +#define HBN_RETRAM_EMAW_UMSK (~(((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS)) +#define HBN_RETRAM_RET HBN_RETRAM_RET +#define HBN_RETRAM_RET_POS (6U) +#define HBN_RETRAM_RET_LEN (1U) +#define HBN_RETRAM_RET_MSK (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS) +#define HBN_RETRAM_RET_UMSK (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)) +#define HBN_RETRAM_SLP HBN_RETRAM_SLP +#define HBN_RETRAM_SLP_POS (7U) +#define HBN_RETRAM_SLP_LEN (1U) +#define HBN_RETRAM_SLP_MSK (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS) +#define HBN_RETRAM_SLP_UMSK (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)) + +/* 0x100 : HBN_RSV0 */ +#define HBN_RSV0_OFFSET (0x100) +#define HBN_RSV0 HBN_RSV0 +#define HBN_RSV0_POS (0U) +#define HBN_RSV0_LEN (32U) +#define HBN_RSV0_MSK (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS) +#define HBN_RSV0_UMSK (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)) + +/* 0x104 : HBN_RSV1 */ +#define HBN_RSV1_OFFSET (0x104) +#define HBN_RSV1 HBN_RSV1 +#define HBN_RSV1_POS (0U) +#define HBN_RSV1_LEN (32U) +#define HBN_RSV1_MSK (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS) +#define HBN_RSV1_UMSK (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)) + +/* 0x108 : HBN_RSV2 */ +#define HBN_RSV2_OFFSET (0x108) +#define HBN_RSV2 HBN_RSV2 +#define HBN_RSV2_POS (0U) +#define HBN_RSV2_LEN (32U) +#define HBN_RSV2_MSK (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS) +#define HBN_RSV2_UMSK (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)) + +/* 0x10C : HBN_RSV3 */ +#define HBN_RSV3_OFFSET (0x10C) +#define HBN_RSV3 HBN_RSV3 +#define HBN_RSV3_POS (0U) +#define HBN_RSV3_LEN (32U) +#define HBN_RSV3_MSK (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS) +#define HBN_RSV3_UMSK (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)) + +/* 0x200 : rc32k_ctrl0 */ +#define HBN_RC32K_CTRL0_OFFSET (0x200) +#define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE +#define HBN_RC32K_CAL_DONE_POS (0U) +#define HBN_RC32K_CAL_DONE_LEN (1U) +#define HBN_RC32K_CAL_DONE_MSK (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS) +#define HBN_RC32K_CAL_DONE_UMSK (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)) +#define HBN_RC32K_RDY HBN_RC32K_RDY +#define HBN_RC32K_RDY_POS (1U) +#define HBN_RC32K_RDY_LEN (1U) +#define HBN_RC32K_RDY_MSK (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS) +#define HBN_RC32K_RDY_UMSK (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)) +#define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS +#define HBN_RC32K_CAL_INPROGRESS_POS (2U) +#define HBN_RC32K_CAL_INPROGRESS_LEN (1U) +#define HBN_RC32K_CAL_INPROGRESS_MSK (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS) +#define HBN_RC32K_CAL_INPROGRESS_UMSK (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)) +#define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV +#define HBN_RC32K_CAL_DIV_POS (3U) +#define HBN_RC32K_CAL_DIV_LEN (2U) +#define HBN_RC32K_CAL_DIV_MSK (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS) +#define HBN_RC32K_CAL_DIV_UMSK (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)) +#define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE +#define HBN_RC32K_CAL_PRECHARGE_POS (5U) +#define HBN_RC32K_CAL_PRECHARGE_LEN (1U) +#define HBN_RC32K_CAL_PRECHARGE_MSK (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS) +#define HBN_RC32K_CAL_PRECHARGE_UMSK (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)) +#define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL +#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U) +#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U) +#define HBN_RC32K_DIG_CODE_FR_CAL_MSK (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS) +#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)) +#define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY +#define HBN_RC32K_VREF_DLY_POS (16U) +#define HBN_RC32K_VREF_DLY_LEN (2U) +#define HBN_RC32K_VREF_DLY_MSK (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS) +#define HBN_RC32K_VREF_DLY_UMSK (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)) +#define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL +#define HBN_RC32K_ALLOW_CAL_POS (18U) +#define HBN_RC32K_ALLOW_CAL_LEN (1U) +#define HBN_RC32K_ALLOW_CAL_MSK (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS) +#define HBN_RC32K_ALLOW_CAL_UMSK (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)) +#define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN +#define HBN_RC32K_EXT_CODE_EN_POS (19U) +#define HBN_RC32K_EXT_CODE_EN_LEN (1U) +#define HBN_RC32K_EXT_CODE_EN_MSK (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS) +#define HBN_RC32K_EXT_CODE_EN_UMSK (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)) +#define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN +#define HBN_RC32K_CAL_EN_POS (20U) +#define HBN_RC32K_CAL_EN_LEN (1U) +#define HBN_RC32K_CAL_EN_MSK (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS) +#define HBN_RC32K_CAL_EN_UMSK (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)) +#define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT +#define HBN_RC32K_CODE_FR_EXT_POS (22U) +#define HBN_RC32K_CODE_FR_EXT_LEN (10U) +#define HBN_RC32K_CODE_FR_EXT_MSK (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS) +#define HBN_RC32K_CODE_FR_EXT_UMSK (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)) + +/* 0x204 : xtal32k */ +#define HBN_XTAL32K_OFFSET (0x204) +#define HBN_XTAL32K_HIZ_EN HBN_XTAL32K_HIZ_EN +#define HBN_XTAL32K_HIZ_EN_POS (0U) +#define HBN_XTAL32K_HIZ_EN_LEN (1U) +#define HBN_XTAL32K_HIZ_EN_MSK (((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS) +#define HBN_XTAL32K_HIZ_EN_UMSK (~(((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS)) +#define HBN_XTAL32K_LOWV_EN HBN_XTAL32K_LOWV_EN +#define HBN_XTAL32K_LOWV_EN_POS (1U) +#define HBN_XTAL32K_LOWV_EN_LEN (1U) +#define HBN_XTAL32K_LOWV_EN_MSK (((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS) +#define HBN_XTAL32K_LOWV_EN_UMSK (~(((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS)) +#define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL +#define HBN_XTAL32K_EXT_SEL_POS (2U) +#define HBN_XTAL32K_EXT_SEL_LEN (1U) +#define HBN_XTAL32K_EXT_SEL_MSK (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS) +#define HBN_XTAL32K_EXT_SEL_UMSK (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)) +#define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL +#define HBN_XTAL32K_AMP_CTRL_POS (3U) +#define HBN_XTAL32K_AMP_CTRL_LEN (2U) +#define HBN_XTAL32K_AMP_CTRL_MSK (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS) +#define HBN_XTAL32K_AMP_CTRL_UMSK (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)) +#define HBN_XTAL32K_REG HBN_XTAL32K_REG +#define HBN_XTAL32K_REG_POS (5U) +#define HBN_XTAL32K_REG_LEN (2U) +#define HBN_XTAL32K_REG_MSK (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS) +#define HBN_XTAL32K_REG_UMSK (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)) +#define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE +#define HBN_XTAL32K_OUTBUF_STRE_POS (7U) +#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U) +#define HBN_XTAL32K_OUTBUF_STRE_MSK (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS) +#define HBN_XTAL32K_OUTBUF_STRE_UMSK (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)) +#define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT +#define HBN_XTAL32K_OTF_SHORT_POS (8U) +#define HBN_XTAL32K_OTF_SHORT_LEN (1U) +#define HBN_XTAL32K_OTF_SHORT_MSK (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS) +#define HBN_XTAL32K_OTF_SHORT_UMSK (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)) +#define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE +#define HBN_XTAL32K_INV_STRE_POS (9U) +#define HBN_XTAL32K_INV_STRE_LEN (2U) +#define HBN_XTAL32K_INV_STRE_MSK (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS) +#define HBN_XTAL32K_INV_STRE_UMSK (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)) +#define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK +#define HBN_XTAL32K_CAPBANK_POS (11U) +#define HBN_XTAL32K_CAPBANK_LEN (6U) +#define HBN_XTAL32K_CAPBANK_MSK (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS) +#define HBN_XTAL32K_CAPBANK_UMSK (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)) +#define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT +#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U) +#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U) +#define HBN_XTAL32K_AC_CAP_SHORT_MSK (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS) +#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)) +#define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF +#define HBN_PU_XTAL32K_BUF_POS (18U) +#define HBN_PU_XTAL32K_BUF_LEN (1U) +#define HBN_PU_XTAL32K_BUF_MSK (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS) +#define HBN_PU_XTAL32K_BUF_UMSK (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)) +#define HBN_PU_XTAL32K HBN_PU_XTAL32K +#define HBN_PU_XTAL32K_POS (19U) +#define HBN_PU_XTAL32K_LEN (1U) +#define HBN_PU_XTAL32K_MSK (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS) +#define HBN_PU_XTAL32K_UMSK (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)) + +struct hbn_reg { + /* 0x0 : HBN_CTL */ + union { + struct + { + uint32_t rtc_ctl : 7; /* [ 6: 0], r/w, 0x0 */ + uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */ + uint32_t trap_mode : 1; /* [ 8], r, 0x0 */ + uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ + uint32_t pwrdn_hbn_rtc : 1; /* [ 11], r/w, 0x0 */ + uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */ + uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */ + uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */ + uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */ + uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */ + uint32_t pu_dcdc18_aon : 1; /* [ 23], r/w, 0x1 */ + uint32_t rtc_dly_option : 1; /* [ 24], r/w, 0x0 */ + uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */ + uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */ + uint32_t sram_slp : 1; /* [ 27], r, 0x0 */ + uint32_t hbn_state : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } HBN_CTL; + + /* 0x4 : HBN_TIME_L */ + union { + struct + { + uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_TIME_L; + + /* 0x8 : HBN_TIME_H */ + union { + struct + { + uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_TIME_H; + + /* 0xC : RTC_TIME_L */ + union { + struct + { + uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } RTC_TIME_L; + + /* 0x10 : RTC_TIME_H */ + union { + struct + { + uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */ + uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */ + } BF; + uint32_t WORD; + } RTC_TIME_H; + + /* 0x14 : HBN_IRQ_MODE */ + union { + struct + { + uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0], r/w, 0x5 */ + uint32_t hbn_pin_wakeup_mask : 5; /* [ 7: 3], r/w, 0x0 */ + uint32_t reg_aon_pad_ie_smt : 5; /* [12: 8], r/w, 0x1f */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */ + uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */ + uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */ + uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_MODE; + + /* 0x18 : HBN_IRQ_STAT */ + union { + struct + { + uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_STAT; + + /* 0x1C : HBN_IRQ_CLR */ + union { + struct + { + uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_CLR; + + /* 0x20 : HBN_PIR_CFG */ + union { + struct + { + uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpadc_cgen : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpadc_nosync : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_CFG; + + /* 0x24 : HBN_PIR_VTH */ + union { + struct + { + uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */ + uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_VTH; + + /* 0x28 : HBN_PIR_INTERVAL */ + union { + struct + { + uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_INTERVAL; + + /* 0x2C : HBN_MISC */ + union { + struct + { + uint32_t bor_sel : 1; /* [ 0], r/w, 0x0 */ + uint32_t bor_vth : 1; /* [ 1], r/w, 0x1 */ + uint32_t pu_bor : 1; /* [ 2], r/w, 0x0 */ + uint32_t r_bor_out : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ + uint32_t hbn_flash_pullup_aon : 6; /* [21:16], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t hbn_flash_pulldown_aon : 6; /* [29:24], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_MISC; + + /* 0x30 : HBN_GLB */ + union { + struct + { + uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t hbn_pu_rc32k : 1; /* [ 5], r/w, 0x1 */ + uint32_t ldo11_rt_iload_sel : 2; /* [ 7: 6], r/w, 0x1 */ + uint32_t hbn_reset_event : 5; /* [12: 8], r, 0x0 */ + uint32_t hbn_clear_reset_event : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */ + uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */ + } BF; + uint32_t WORD; + } HBN_GLB; + + /* 0x34 : HBN_SRAM */ + union { + struct + { + uint32_t retram_ema : 3; /* [ 2: 0], r/w, 0x3 */ + uint32_t retram_emaw : 2; /* [ 4: 3], r/w, 0x1 */ + uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ + uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */ + uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_SRAM; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[200]; + + /* 0x100 : HBN_RSV0 */ + union { + struct + { + uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_RSV0; + + /* 0x104 : HBN_RSV1 */ + union { + struct + { + uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } HBN_RSV1; + + /* 0x108 : HBN_RSV2 */ + union { + struct + { + uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_RSV2; + + /* 0x10C : HBN_RSV3 */ + union { + struct + { + uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } HBN_RSV3; + + /* 0x110 reserved */ + uint8_t RESERVED0x110[240]; + + /* 0x200 : rc32k_ctrl0 */ + union { + struct + { + uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */ + uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */ + uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */ + uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */ + uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */ + uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */ + uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */ + uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */ + uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */ + uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */ + uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x12c */ + } BF; + uint32_t WORD; + } rc32k_ctrl0; + + /* 0x204 : xtal32k */ + union { + struct + { + uint32_t xtal32k_hiz_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t xtal32k_lowv_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */ + uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */ + uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */ + uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */ + uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */ + uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */ + uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x1 */ + uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */ + uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x1 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } xtal32k; +}; + +typedef volatile struct hbn_reg hbn_reg_t; + +#endif /* __HBN_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/i2c_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/i2c_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..aab28de667f0ba09ae52775b5af422ba1f6e8a5f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/i2c_reg.h @@ -0,0 +1,557 @@ +/** + ****************************************************************************** + * @file i2c_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +#include "bl702.h" + +/* 0x0 : i2c_config */ +#define I2C_CONFIG_OFFSET (0x0) +#define I2C_CR_I2C_M_EN I2C_CR_I2C_M_EN +#define I2C_CR_I2C_M_EN_POS (0U) +#define I2C_CR_I2C_M_EN_LEN (1U) +#define I2C_CR_I2C_M_EN_MSK (((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS) +#define I2C_CR_I2C_M_EN_UMSK (~(((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS)) +#define I2C_CR_I2C_PKT_DIR I2C_CR_I2C_PKT_DIR +#define I2C_CR_I2C_PKT_DIR_POS (1U) +#define I2C_CR_I2C_PKT_DIR_LEN (1U) +#define I2C_CR_I2C_PKT_DIR_MSK (((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS) +#define I2C_CR_I2C_PKT_DIR_UMSK (~(((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS)) +#define I2C_CR_I2C_DEG_EN I2C_CR_I2C_DEG_EN +#define I2C_CR_I2C_DEG_EN_POS (2U) +#define I2C_CR_I2C_DEG_EN_LEN (1U) +#define I2C_CR_I2C_DEG_EN_MSK (((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS) +#define I2C_CR_I2C_DEG_EN_UMSK (~(((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS)) +#define I2C_CR_I2C_SCL_SYNC_EN I2C_CR_I2C_SCL_SYNC_EN +#define I2C_CR_I2C_SCL_SYNC_EN_POS (3U) +#define I2C_CR_I2C_SCL_SYNC_EN_LEN (1U) +#define I2C_CR_I2C_SCL_SYNC_EN_MSK (((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS) +#define I2C_CR_I2C_SCL_SYNC_EN_UMSK (~(((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS)) +#define I2C_CR_I2C_SUB_ADDR_EN I2C_CR_I2C_SUB_ADDR_EN +#define I2C_CR_I2C_SUB_ADDR_EN_POS (4U) +#define I2C_CR_I2C_SUB_ADDR_EN_LEN (1U) +#define I2C_CR_I2C_SUB_ADDR_EN_MSK (((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS) +#define I2C_CR_I2C_SUB_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS)) +#define I2C_CR_I2C_SUB_ADDR_BC I2C_CR_I2C_SUB_ADDR_BC +#define I2C_CR_I2C_SUB_ADDR_BC_POS (5U) +#define I2C_CR_I2C_SUB_ADDR_BC_LEN (2U) +#define I2C_CR_I2C_SUB_ADDR_BC_MSK (((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS) +#define I2C_CR_I2C_SUB_ADDR_BC_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS)) +#define I2C_CR_I2C_SLV_ADDR I2C_CR_I2C_SLV_ADDR +#define I2C_CR_I2C_SLV_ADDR_POS (8U) +#define I2C_CR_I2C_SLV_ADDR_LEN (7U) +#define I2C_CR_I2C_SLV_ADDR_MSK (((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS) +#define I2C_CR_I2C_SLV_ADDR_UMSK (~(((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS)) +#define I2C_CR_I2C_PKT_LEN I2C_CR_I2C_PKT_LEN +#define I2C_CR_I2C_PKT_LEN_POS (16U) +#define I2C_CR_I2C_PKT_LEN_LEN (8U) +#define I2C_CR_I2C_PKT_LEN_MSK (((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS) +#define I2C_CR_I2C_PKT_LEN_UMSK (~(((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS)) +#define I2C_CR_I2C_DEG_CNT I2C_CR_I2C_DEG_CNT +#define I2C_CR_I2C_DEG_CNT_POS (28U) +#define I2C_CR_I2C_DEG_CNT_LEN (4U) +#define I2C_CR_I2C_DEG_CNT_MSK (((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS) +#define I2C_CR_I2C_DEG_CNT_UMSK (~(((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS)) + +/* 0x4 : i2c_int_sts */ +#define I2C_INT_STS_OFFSET (0x4) +#define I2C_END_INT I2C_END_INT +#define I2C_END_INT_POS (0U) +#define I2C_END_INT_LEN (1U) +#define I2C_END_INT_MSK (((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS) +#define I2C_END_INT_UMSK (~(((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS)) +#define I2C_TXF_INT I2C_TXF_INT +#define I2C_TXF_INT_POS (1U) +#define I2C_TXF_INT_LEN (1U) +#define I2C_TXF_INT_MSK (((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS) +#define I2C_TXF_INT_UMSK (~(((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS)) +#define I2C_RXF_INT I2C_RXF_INT +#define I2C_RXF_INT_POS (2U) +#define I2C_RXF_INT_LEN (1U) +#define I2C_RXF_INT_MSK (((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS) +#define I2C_RXF_INT_UMSK (~(((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS)) +#define I2C_NAK_INT I2C_NAK_INT +#define I2C_NAK_INT_POS (3U) +#define I2C_NAK_INT_LEN (1U) +#define I2C_NAK_INT_MSK (((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS) +#define I2C_NAK_INT_UMSK (~(((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS)) +#define I2C_ARB_INT I2C_ARB_INT +#define I2C_ARB_INT_POS (4U) +#define I2C_ARB_INT_LEN (1U) +#define I2C_ARB_INT_MSK (((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS) +#define I2C_ARB_INT_UMSK (~(((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS)) +#define I2C_FER_INT I2C_FER_INT +#define I2C_FER_INT_POS (5U) +#define I2C_FER_INT_LEN (1U) +#define I2C_FER_INT_MSK (((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS) +#define I2C_FER_INT_UMSK (~(((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS)) +#define I2C_CR_I2C_END_MASK I2C_CR_I2C_END_MASK +#define I2C_CR_I2C_END_MASK_POS (8U) +#define I2C_CR_I2C_END_MASK_LEN (1U) +#define I2C_CR_I2C_END_MASK_MSK (((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS) +#define I2C_CR_I2C_END_MASK_UMSK (~(((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS)) +#define I2C_CR_I2C_TXF_MASK I2C_CR_I2C_TXF_MASK +#define I2C_CR_I2C_TXF_MASK_POS (9U) +#define I2C_CR_I2C_TXF_MASK_LEN (1U) +#define I2C_CR_I2C_TXF_MASK_MSK (((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS) +#define I2C_CR_I2C_TXF_MASK_UMSK (~(((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS)) +#define I2C_CR_I2C_RXF_MASK I2C_CR_I2C_RXF_MASK +#define I2C_CR_I2C_RXF_MASK_POS (10U) +#define I2C_CR_I2C_RXF_MASK_LEN (1U) +#define I2C_CR_I2C_RXF_MASK_MSK (((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS) +#define I2C_CR_I2C_RXF_MASK_UMSK (~(((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS)) +#define I2C_CR_I2C_NAK_MASK I2C_CR_I2C_NAK_MASK +#define I2C_CR_I2C_NAK_MASK_POS (11U) +#define I2C_CR_I2C_NAK_MASK_LEN (1U) +#define I2C_CR_I2C_NAK_MASK_MSK (((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS) +#define I2C_CR_I2C_NAK_MASK_UMSK (~(((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS)) +#define I2C_CR_I2C_ARB_MASK I2C_CR_I2C_ARB_MASK +#define I2C_CR_I2C_ARB_MASK_POS (12U) +#define I2C_CR_I2C_ARB_MASK_LEN (1U) +#define I2C_CR_I2C_ARB_MASK_MSK (((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS) +#define I2C_CR_I2C_ARB_MASK_UMSK (~(((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS)) +#define I2C_CR_I2C_FER_MASK I2C_CR_I2C_FER_MASK +#define I2C_CR_I2C_FER_MASK_POS (13U) +#define I2C_CR_I2C_FER_MASK_LEN (1U) +#define I2C_CR_I2C_FER_MASK_MSK (((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS) +#define I2C_CR_I2C_FER_MASK_UMSK (~(((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS)) +#define I2C_CR_I2C_END_CLR I2C_CR_I2C_END_CLR +#define I2C_CR_I2C_END_CLR_POS (16U) +#define I2C_CR_I2C_END_CLR_LEN (1U) +#define I2C_CR_I2C_END_CLR_MSK (((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS) +#define I2C_CR_I2C_END_CLR_UMSK (~(((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS)) +#define I2C_CR_I2C_NAK_CLR I2C_CR_I2C_NAK_CLR +#define I2C_CR_I2C_NAK_CLR_POS (19U) +#define I2C_CR_I2C_NAK_CLR_LEN (1U) +#define I2C_CR_I2C_NAK_CLR_MSK (((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS) +#define I2C_CR_I2C_NAK_CLR_UMSK (~(((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS)) +#define I2C_CR_I2C_ARB_CLR I2C_CR_I2C_ARB_CLR +#define I2C_CR_I2C_ARB_CLR_POS (20U) +#define I2C_CR_I2C_ARB_CLR_LEN (1U) +#define I2C_CR_I2C_ARB_CLR_MSK (((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS) +#define I2C_CR_I2C_ARB_CLR_UMSK (~(((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS)) +#define I2C_CR_I2C_END_EN I2C_CR_I2C_END_EN +#define I2C_CR_I2C_END_EN_POS (24U) +#define I2C_CR_I2C_END_EN_LEN (1U) +#define I2C_CR_I2C_END_EN_MSK (((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS) +#define I2C_CR_I2C_END_EN_UMSK (~(((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS)) +#define I2C_CR_I2C_TXF_EN I2C_CR_I2C_TXF_EN +#define I2C_CR_I2C_TXF_EN_POS (25U) +#define I2C_CR_I2C_TXF_EN_LEN (1U) +#define I2C_CR_I2C_TXF_EN_MSK (((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS) +#define I2C_CR_I2C_TXF_EN_UMSK (~(((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS)) +#define I2C_CR_I2C_RXF_EN I2C_CR_I2C_RXF_EN +#define I2C_CR_I2C_RXF_EN_POS (26U) +#define I2C_CR_I2C_RXF_EN_LEN (1U) +#define I2C_CR_I2C_RXF_EN_MSK (((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS) +#define I2C_CR_I2C_RXF_EN_UMSK (~(((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS)) +#define I2C_CR_I2C_NAK_EN I2C_CR_I2C_NAK_EN +#define I2C_CR_I2C_NAK_EN_POS (27U) +#define I2C_CR_I2C_NAK_EN_LEN (1U) +#define I2C_CR_I2C_NAK_EN_MSK (((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS) +#define I2C_CR_I2C_NAK_EN_UMSK (~(((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS)) +#define I2C_CR_I2C_ARB_EN I2C_CR_I2C_ARB_EN +#define I2C_CR_I2C_ARB_EN_POS (28U) +#define I2C_CR_I2C_ARB_EN_LEN (1U) +#define I2C_CR_I2C_ARB_EN_MSK (((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS) +#define I2C_CR_I2C_ARB_EN_UMSK (~(((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS)) +#define I2C_CR_I2C_FER_EN I2C_CR_I2C_FER_EN +#define I2C_CR_I2C_FER_EN_POS (29U) +#define I2C_CR_I2C_FER_EN_LEN (1U) +#define I2C_CR_I2C_FER_EN_MSK (((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS) +#define I2C_CR_I2C_FER_EN_UMSK (~(((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS)) + +/* 0x8 : i2c_sub_addr */ +#define I2C_SUB_ADDR_OFFSET (0x8) +#define I2C_CR_I2C_SUB_ADDR_B0 I2C_CR_I2C_SUB_ADDR_B0 +#define I2C_CR_I2C_SUB_ADDR_B0_POS (0U) +#define I2C_CR_I2C_SUB_ADDR_B0_LEN (8U) +#define I2C_CR_I2C_SUB_ADDR_B0_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS) +#define I2C_CR_I2C_SUB_ADDR_B0_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS)) +#define I2C_CR_I2C_SUB_ADDR_B1 I2C_CR_I2C_SUB_ADDR_B1 +#define I2C_CR_I2C_SUB_ADDR_B1_POS (8U) +#define I2C_CR_I2C_SUB_ADDR_B1_LEN (8U) +#define I2C_CR_I2C_SUB_ADDR_B1_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS) +#define I2C_CR_I2C_SUB_ADDR_B1_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS)) +#define I2C_CR_I2C_SUB_ADDR_B2 I2C_CR_I2C_SUB_ADDR_B2 +#define I2C_CR_I2C_SUB_ADDR_B2_POS (16U) +#define I2C_CR_I2C_SUB_ADDR_B2_LEN (8U) +#define I2C_CR_I2C_SUB_ADDR_B2_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS) +#define I2C_CR_I2C_SUB_ADDR_B2_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS)) +#define I2C_CR_I2C_SUB_ADDR_B3 I2C_CR_I2C_SUB_ADDR_B3 +#define I2C_CR_I2C_SUB_ADDR_B3_POS (24U) +#define I2C_CR_I2C_SUB_ADDR_B3_LEN (8U) +#define I2C_CR_I2C_SUB_ADDR_B3_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS) +#define I2C_CR_I2C_SUB_ADDR_B3_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS)) + +/* 0xC : i2c_bus_busy */ +#define I2C_BUS_BUSY_OFFSET (0xC) +#define I2C_STS_I2C_BUS_BUSY I2C_STS_I2C_BUS_BUSY +#define I2C_STS_I2C_BUS_BUSY_POS (0U) +#define I2C_STS_I2C_BUS_BUSY_LEN (1U) +#define I2C_STS_I2C_BUS_BUSY_MSK (((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS) +#define I2C_STS_I2C_BUS_BUSY_UMSK (~(((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS)) +#define I2C_CR_I2C_BUS_BUSY_CLR I2C_CR_I2C_BUS_BUSY_CLR +#define I2C_CR_I2C_BUS_BUSY_CLR_POS (1U) +#define I2C_CR_I2C_BUS_BUSY_CLR_LEN (1U) +#define I2C_CR_I2C_BUS_BUSY_CLR_MSK (((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS) +#define I2C_CR_I2C_BUS_BUSY_CLR_UMSK (~(((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS)) + +/* 0x10 : i2c_prd_start */ +#define I2C_PRD_START_OFFSET (0x10) +#define I2C_CR_I2C_PRD_S_PH_0 I2C_CR_I2C_PRD_S_PH_0 +#define I2C_CR_I2C_PRD_S_PH_0_POS (0U) +#define I2C_CR_I2C_PRD_S_PH_0_LEN (8U) +#define I2C_CR_I2C_PRD_S_PH_0_MSK (((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS) +#define I2C_CR_I2C_PRD_S_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS)) +#define I2C_CR_I2C_PRD_S_PH_1 I2C_CR_I2C_PRD_S_PH_1 +#define I2C_CR_I2C_PRD_S_PH_1_POS (8U) +#define I2C_CR_I2C_PRD_S_PH_1_LEN (8U) +#define I2C_CR_I2C_PRD_S_PH_1_MSK (((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS) +#define I2C_CR_I2C_PRD_S_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS)) +#define I2C_CR_I2C_PRD_S_PH_2 I2C_CR_I2C_PRD_S_PH_2 +#define I2C_CR_I2C_PRD_S_PH_2_POS (16U) +#define I2C_CR_I2C_PRD_S_PH_2_LEN (8U) +#define I2C_CR_I2C_PRD_S_PH_2_MSK (((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS) +#define I2C_CR_I2C_PRD_S_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS)) +#define I2C_CR_I2C_PRD_S_PH_3 I2C_CR_I2C_PRD_S_PH_3 +#define I2C_CR_I2C_PRD_S_PH_3_POS (24U) +#define I2C_CR_I2C_PRD_S_PH_3_LEN (8U) +#define I2C_CR_I2C_PRD_S_PH_3_MSK (((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS) +#define I2C_CR_I2C_PRD_S_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS)) + +/* 0x14 : i2c_prd_stop */ +#define I2C_PRD_STOP_OFFSET (0x14) +#define I2C_CR_I2C_PRD_P_PH_0 I2C_CR_I2C_PRD_P_PH_0 +#define I2C_CR_I2C_PRD_P_PH_0_POS (0U) +#define I2C_CR_I2C_PRD_P_PH_0_LEN (8U) +#define I2C_CR_I2C_PRD_P_PH_0_MSK (((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS) +#define I2C_CR_I2C_PRD_P_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS)) +#define I2C_CR_I2C_PRD_P_PH_1 I2C_CR_I2C_PRD_P_PH_1 +#define I2C_CR_I2C_PRD_P_PH_1_POS (8U) +#define I2C_CR_I2C_PRD_P_PH_1_LEN (8U) +#define I2C_CR_I2C_PRD_P_PH_1_MSK (((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS) +#define I2C_CR_I2C_PRD_P_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS)) +#define I2C_CR_I2C_PRD_P_PH_2 I2C_CR_I2C_PRD_P_PH_2 +#define I2C_CR_I2C_PRD_P_PH_2_POS (16U) +#define I2C_CR_I2C_PRD_P_PH_2_LEN (8U) +#define I2C_CR_I2C_PRD_P_PH_2_MSK (((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS) +#define I2C_CR_I2C_PRD_P_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS)) +#define I2C_CR_I2C_PRD_P_PH_3 I2C_CR_I2C_PRD_P_PH_3 +#define I2C_CR_I2C_PRD_P_PH_3_POS (24U) +#define I2C_CR_I2C_PRD_P_PH_3_LEN (8U) +#define I2C_CR_I2C_PRD_P_PH_3_MSK (((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS) +#define I2C_CR_I2C_PRD_P_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS)) + +/* 0x18 : i2c_prd_data */ +#define I2C_PRD_DATA_OFFSET (0x18) +#define I2C_CR_I2C_PRD_D_PH_0 I2C_CR_I2C_PRD_D_PH_0 +#define I2C_CR_I2C_PRD_D_PH_0_POS (0U) +#define I2C_CR_I2C_PRD_D_PH_0_LEN (8U) +#define I2C_CR_I2C_PRD_D_PH_0_MSK (((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS) +#define I2C_CR_I2C_PRD_D_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS)) +#define I2C_CR_I2C_PRD_D_PH_1 I2C_CR_I2C_PRD_D_PH_1 +#define I2C_CR_I2C_PRD_D_PH_1_POS (8U) +#define I2C_CR_I2C_PRD_D_PH_1_LEN (8U) +#define I2C_CR_I2C_PRD_D_PH_1_MSK (((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS) +#define I2C_CR_I2C_PRD_D_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS)) +#define I2C_CR_I2C_PRD_D_PH_2 I2C_CR_I2C_PRD_D_PH_2 +#define I2C_CR_I2C_PRD_D_PH_2_POS (16U) +#define I2C_CR_I2C_PRD_D_PH_2_LEN (8U) +#define I2C_CR_I2C_PRD_D_PH_2_MSK (((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS) +#define I2C_CR_I2C_PRD_D_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS)) +#define I2C_CR_I2C_PRD_D_PH_3 I2C_CR_I2C_PRD_D_PH_3 +#define I2C_CR_I2C_PRD_D_PH_3_POS (24U) +#define I2C_CR_I2C_PRD_D_PH_3_LEN (8U) +#define I2C_CR_I2C_PRD_D_PH_3_MSK (((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS) +#define I2C_CR_I2C_PRD_D_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS)) + +/* 0x80 : i2c_fifo_config_0 */ +#define I2C_FIFO_CONFIG_0_OFFSET (0x80) +#define I2C_DMA_TX_EN I2C_DMA_TX_EN +#define I2C_DMA_TX_EN_POS (0U) +#define I2C_DMA_TX_EN_LEN (1U) +#define I2C_DMA_TX_EN_MSK (((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS) +#define I2C_DMA_TX_EN_UMSK (~(((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS)) +#define I2C_DMA_RX_EN I2C_DMA_RX_EN +#define I2C_DMA_RX_EN_POS (1U) +#define I2C_DMA_RX_EN_LEN (1U) +#define I2C_DMA_RX_EN_MSK (((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS) +#define I2C_DMA_RX_EN_UMSK (~(((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS)) +#define I2C_TX_FIFO_CLR I2C_TX_FIFO_CLR +#define I2C_TX_FIFO_CLR_POS (2U) +#define I2C_TX_FIFO_CLR_LEN (1U) +#define I2C_TX_FIFO_CLR_MSK (((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS) +#define I2C_TX_FIFO_CLR_UMSK (~(((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS)) +#define I2C_RX_FIFO_CLR I2C_RX_FIFO_CLR +#define I2C_RX_FIFO_CLR_POS (3U) +#define I2C_RX_FIFO_CLR_LEN (1U) +#define I2C_RX_FIFO_CLR_MSK (((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS) +#define I2C_RX_FIFO_CLR_UMSK (~(((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS)) +#define I2C_TX_FIFO_OVERFLOW I2C_TX_FIFO_OVERFLOW +#define I2C_TX_FIFO_OVERFLOW_POS (4U) +#define I2C_TX_FIFO_OVERFLOW_LEN (1U) +#define I2C_TX_FIFO_OVERFLOW_MSK (((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS) +#define I2C_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS)) +#define I2C_TX_FIFO_UNDERFLOW I2C_TX_FIFO_UNDERFLOW +#define I2C_TX_FIFO_UNDERFLOW_POS (5U) +#define I2C_TX_FIFO_UNDERFLOW_LEN (1U) +#define I2C_TX_FIFO_UNDERFLOW_MSK (((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS) +#define I2C_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS)) +#define I2C_RX_FIFO_OVERFLOW I2C_RX_FIFO_OVERFLOW +#define I2C_RX_FIFO_OVERFLOW_POS (6U) +#define I2C_RX_FIFO_OVERFLOW_LEN (1U) +#define I2C_RX_FIFO_OVERFLOW_MSK (((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS) +#define I2C_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS)) +#define I2C_RX_FIFO_UNDERFLOW I2C_RX_FIFO_UNDERFLOW +#define I2C_RX_FIFO_UNDERFLOW_POS (7U) +#define I2C_RX_FIFO_UNDERFLOW_LEN (1U) +#define I2C_RX_FIFO_UNDERFLOW_MSK (((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS) +#define I2C_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS)) + +/* 0x84 : i2c_fifo_config_1 */ +#define I2C_FIFO_CONFIG_1_OFFSET (0x84) +#define I2C_TX_FIFO_CNT I2C_TX_FIFO_CNT +#define I2C_TX_FIFO_CNT_POS (0U) +#define I2C_TX_FIFO_CNT_LEN (2U) +#define I2C_TX_FIFO_CNT_MSK (((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS) +#define I2C_TX_FIFO_CNT_UMSK (~(((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS)) +#define I2C_RX_FIFO_CNT I2C_RX_FIFO_CNT +#define I2C_RX_FIFO_CNT_POS (8U) +#define I2C_RX_FIFO_CNT_LEN (2U) +#define I2C_RX_FIFO_CNT_MSK (((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS) +#define I2C_RX_FIFO_CNT_UMSK (~(((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS)) +#define I2C_TX_FIFO_TH I2C_TX_FIFO_TH +#define I2C_TX_FIFO_TH_POS (16U) +#define I2C_TX_FIFO_TH_LEN (1U) +#define I2C_TX_FIFO_TH_MSK (((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS) +#define I2C_TX_FIFO_TH_UMSK (~(((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS)) +#define I2C_RX_FIFO_TH I2C_RX_FIFO_TH +#define I2C_RX_FIFO_TH_POS (24U) +#define I2C_RX_FIFO_TH_LEN (1U) +#define I2C_RX_FIFO_TH_MSK (((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS) +#define I2C_RX_FIFO_TH_UMSK (~(((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS)) + +/* 0x88 : i2c_fifo_wdata */ +#define I2C_FIFO_WDATA_OFFSET (0x88) +#define I2C_FIFO_WDATA I2C_FIFO_WDATA +#define I2C_FIFO_WDATA_POS (0U) +#define I2C_FIFO_WDATA_LEN (32U) +#define I2C_FIFO_WDATA_MSK (((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS) +#define I2C_FIFO_WDATA_UMSK (~(((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS)) + +/* 0x8C : i2c_fifo_rdata */ +#define I2C_FIFO_RDATA_OFFSET (0x8C) +#define I2C_FIFO_RDATA I2C_FIFO_RDATA +#define I2C_FIFO_RDATA_POS (0U) +#define I2C_FIFO_RDATA_LEN (32U) +#define I2C_FIFO_RDATA_MSK (((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS) +#define I2C_FIFO_RDATA_UMSK (~(((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS)) + +struct i2c_reg { + /* 0x0 : i2c_config */ + union { + struct + { + uint32_t cr_i2c_m_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_i2c_pkt_dir : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_i2c_deg_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_i2c_scl_sync_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t cr_i2c_sub_addr_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_i2c_sub_addr_bc : 2; /* [ 6: 5], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cr_i2c_slv_addr : 7; /* [14: 8], r/w, 0x0 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t cr_i2c_pkt_len : 8; /* [23:16], r/w, 0x0 */ + uint32_t reserved_24_27 : 4; /* [27:24], rsvd, 0x0 */ + uint32_t cr_i2c_deg_cnt : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } i2c_config; + + /* 0x4 : i2c_int_sts */ + union { + struct + { + uint32_t i2c_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t i2c_txf_int : 1; /* [ 1], r, 0x0 */ + uint32_t i2c_rxf_int : 1; /* [ 2], r, 0x0 */ + uint32_t i2c_nak_int : 1; /* [ 3], r, 0x0 */ + uint32_t i2c_arb_int : 1; /* [ 4], r, 0x0 */ + uint32_t i2c_fer_int : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t cr_i2c_end_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_i2c_txf_mask : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_i2c_rxf_mask : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_i2c_nak_mask : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_i2c_arb_mask : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_i2c_fer_mask : 1; /* [ 13], r/w, 0x1 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t cr_i2c_end_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t cr_i2c_nak_clr : 1; /* [ 19], w1c, 0x0 */ + uint32_t cr_i2c_arb_clr : 1; /* [ 20], w1c, 0x0 */ + uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t cr_i2c_end_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t cr_i2c_txf_en : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_i2c_rxf_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t cr_i2c_nak_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t cr_i2c_arb_en : 1; /* [ 28], r/w, 0x1 */ + uint32_t cr_i2c_fer_en : 1; /* [ 29], r/w, 0x1 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2c_int_sts; + + /* 0x8 : i2c_sub_addr */ + union { + struct + { + uint32_t cr_i2c_sub_addr_b0 : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t cr_i2c_sub_addr_b1 : 8; /* [15: 8], r/w, 0x0 */ + uint32_t cr_i2c_sub_addr_b2 : 8; /* [23:16], r/w, 0x0 */ + uint32_t cr_i2c_sub_addr_b3 : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } i2c_sub_addr; + + /* 0xC : i2c_bus_busy */ + union { + struct + { + uint32_t sts_i2c_bus_busy : 1; /* [ 0], r, 0x0 */ + uint32_t cr_i2c_bus_busy_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2c_bus_busy; + + /* 0x10 : i2c_prd_start */ + union { + struct + { + uint32_t cr_i2c_prd_s_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t cr_i2c_prd_s_ph_1 : 8; /* [15: 8], r/w, 0xf */ + uint32_t cr_i2c_prd_s_ph_2 : 8; /* [23:16], r/w, 0xf */ + uint32_t cr_i2c_prd_s_ph_3 : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } i2c_prd_start; + + /* 0x14 : i2c_prd_stop */ + union { + struct + { + uint32_t cr_i2c_prd_p_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t cr_i2c_prd_p_ph_1 : 8; /* [15: 8], r/w, 0xf */ + uint32_t cr_i2c_prd_p_ph_2 : 8; /* [23:16], r/w, 0xf */ + uint32_t cr_i2c_prd_p_ph_3 : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } i2c_prd_stop; + + /* 0x18 : i2c_prd_data */ + union { + struct + { + uint32_t cr_i2c_prd_d_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t cr_i2c_prd_d_ph_1 : 8; /* [15: 8], r/w, 0xf */ + uint32_t cr_i2c_prd_d_ph_2 : 8; /* [23:16], r/w, 0xf */ + uint32_t cr_i2c_prd_d_ph_3 : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } i2c_prd_data; + + /* 0x1c reserved */ + uint8_t RESERVED0x1c[100]; + + /* 0x80 : i2c_fifo_config_0 */ + union { + struct + { + uint32_t i2c_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t i2c_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2c_fifo_config_0; + + /* 0x84 : i2c_fifo_config_1 */ + union { + struct + { + uint32_t tx_fifo_cnt : 2; /* [ 1: 0], r, 0x2 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t rx_fifo_cnt : 2; /* [ 9: 8], r, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t tx_fifo_th : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ + uint32_t rx_fifo_th : 1; /* [ 24], r/w, 0x0 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2c_fifo_config_1; + + /* 0x88 : i2c_fifo_wdata */ + union { + struct + { + uint32_t i2c_fifo_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } i2c_fifo_wdata; + + /* 0x8C : i2c_fifo_rdata */ + union { + struct + { + uint32_t i2c_fifo_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } i2c_fifo_rdata; +}; + +typedef volatile struct i2c_reg i2c_reg_t; + +#endif /* __I2C_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/i2s_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/i2s_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..342fbe28a05945ded6a268cc56650196ef42304e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/i2s_reg.h @@ -0,0 +1,455 @@ +/** + ****************************************************************************** + * @file i2s_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __I2S_REG_H__ +#define __I2S_REG_H__ + +#include "bl702.h" + +/* 0x0 : i2s_config */ +#define I2S_CONFIG_OFFSET (0x0) +#define I2S_CR_I2S_M_EN I2S_CR_I2S_M_EN +#define I2S_CR_I2S_M_EN_POS (0U) +#define I2S_CR_I2S_M_EN_LEN (1U) +#define I2S_CR_I2S_M_EN_MSK (((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS) +#define I2S_CR_I2S_M_EN_UMSK (~(((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS)) +#define I2S_CR_I2S_S_EN I2S_CR_I2S_S_EN +#define I2S_CR_I2S_S_EN_POS (1U) +#define I2S_CR_I2S_S_EN_LEN (1U) +#define I2S_CR_I2S_S_EN_MSK (((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS) +#define I2S_CR_I2S_S_EN_UMSK (~(((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS)) +#define I2S_CR_I2S_TXD_EN I2S_CR_I2S_TXD_EN +#define I2S_CR_I2S_TXD_EN_POS (2U) +#define I2S_CR_I2S_TXD_EN_LEN (1U) +#define I2S_CR_I2S_TXD_EN_MSK (((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS) +#define I2S_CR_I2S_TXD_EN_UMSK (~(((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS)) +#define I2S_CR_I2S_RXD_EN I2S_CR_I2S_RXD_EN +#define I2S_CR_I2S_RXD_EN_POS (3U) +#define I2S_CR_I2S_RXD_EN_LEN (1U) +#define I2S_CR_I2S_RXD_EN_MSK (((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS) +#define I2S_CR_I2S_RXD_EN_UMSK (~(((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS)) +#define I2S_CR_MONO_MODE I2S_CR_MONO_MODE +#define I2S_CR_MONO_MODE_POS (4U) +#define I2S_CR_MONO_MODE_LEN (1U) +#define I2S_CR_MONO_MODE_MSK (((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS) +#define I2S_CR_MONO_MODE_UMSK (~(((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS)) +#define I2S_CR_MUTE_MODE I2S_CR_MUTE_MODE +#define I2S_CR_MUTE_MODE_POS (5U) +#define I2S_CR_MUTE_MODE_LEN (1U) +#define I2S_CR_MUTE_MODE_MSK (((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS) +#define I2S_CR_MUTE_MODE_UMSK (~(((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS)) +#define I2S_CR_FS_1T_MODE I2S_CR_FS_1T_MODE +#define I2S_CR_FS_1T_MODE_POS (6U) +#define I2S_CR_FS_1T_MODE_LEN (1U) +#define I2S_CR_FS_1T_MODE_MSK (((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS) +#define I2S_CR_FS_1T_MODE_UMSK (~(((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS)) +#define I2S_CR_FS_4CH_MODE I2S_CR_FS_4CH_MODE +#define I2S_CR_FS_4CH_MODE_POS (7U) +#define I2S_CR_FS_4CH_MODE_LEN (1U) +#define I2S_CR_FS_4CH_MODE_MSK (((1U << I2S_CR_FS_4CH_MODE_LEN) - 1) << I2S_CR_FS_4CH_MODE_POS) +#define I2S_CR_FS_4CH_MODE_UMSK (~(((1U << I2S_CR_FS_4CH_MODE_LEN) - 1) << I2S_CR_FS_4CH_MODE_POS)) +#define I2S_CR_FS_3CH_MODE I2S_CR_FS_3CH_MODE +#define I2S_CR_FS_3CH_MODE_POS (8U) +#define I2S_CR_FS_3CH_MODE_LEN (1U) +#define I2S_CR_FS_3CH_MODE_MSK (((1U << I2S_CR_FS_3CH_MODE_LEN) - 1) << I2S_CR_FS_3CH_MODE_POS) +#define I2S_CR_FS_3CH_MODE_UMSK (~(((1U << I2S_CR_FS_3CH_MODE_LEN) - 1) << I2S_CR_FS_3CH_MODE_POS)) +#define I2S_CR_FRAME_SIZE I2S_CR_FRAME_SIZE +#define I2S_CR_FRAME_SIZE_POS (12U) +#define I2S_CR_FRAME_SIZE_LEN (2U) +#define I2S_CR_FRAME_SIZE_MSK (((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS) +#define I2S_CR_FRAME_SIZE_UMSK (~(((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS)) +#define I2S_CR_DATA_SIZE I2S_CR_DATA_SIZE +#define I2S_CR_DATA_SIZE_POS (14U) +#define I2S_CR_DATA_SIZE_LEN (2U) +#define I2S_CR_DATA_SIZE_MSK (((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS) +#define I2S_CR_DATA_SIZE_UMSK (~(((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS)) +#define I2S_CR_I2S_MODE I2S_CR_I2S_MODE +#define I2S_CR_I2S_MODE_POS (16U) +#define I2S_CR_I2S_MODE_LEN (2U) +#define I2S_CR_I2S_MODE_MSK (((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS) +#define I2S_CR_I2S_MODE_UMSK (~(((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS)) +#define I2S_CR_ENDIAN I2S_CR_ENDIAN +#define I2S_CR_ENDIAN_POS (18U) +#define I2S_CR_ENDIAN_LEN (1U) +#define I2S_CR_ENDIAN_MSK (((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS) +#define I2S_CR_ENDIAN_UMSK (~(((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS)) +#define I2S_CR_MONO_RX_CH I2S_CR_MONO_RX_CH +#define I2S_CR_MONO_RX_CH_POS (19U) +#define I2S_CR_MONO_RX_CH_LEN (1U) +#define I2S_CR_MONO_RX_CH_MSK (((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS) +#define I2S_CR_MONO_RX_CH_UMSK (~(((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS)) +#define I2S_CR_OFS_CNT I2S_CR_OFS_CNT +#define I2S_CR_OFS_CNT_POS (20U) +#define I2S_CR_OFS_CNT_LEN (5U) +#define I2S_CR_OFS_CNT_MSK (((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS) +#define I2S_CR_OFS_CNT_UMSK (~(((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS)) +#define I2S_CR_OFS_EN I2S_CR_OFS_EN +#define I2S_CR_OFS_EN_POS (25U) +#define I2S_CR_OFS_EN_LEN (1U) +#define I2S_CR_OFS_EN_MSK (((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS) +#define I2S_CR_OFS_EN_UMSK (~(((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS)) + +/* 0x4 : i2s_int_sts */ +#define I2S_INT_STS_OFFSET (0x4) +#define I2S_TXF_INT I2S_TXF_INT +#define I2S_TXF_INT_POS (0U) +#define I2S_TXF_INT_LEN (1U) +#define I2S_TXF_INT_MSK (((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS) +#define I2S_TXF_INT_UMSK (~(((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS)) +#define I2S_RXF_INT I2S_RXF_INT +#define I2S_RXF_INT_POS (1U) +#define I2S_RXF_INT_LEN (1U) +#define I2S_RXF_INT_MSK (((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS) +#define I2S_RXF_INT_UMSK (~(((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS)) +#define I2S_FER_INT I2S_FER_INT +#define I2S_FER_INT_POS (2U) +#define I2S_FER_INT_LEN (1U) +#define I2S_FER_INT_MSK (((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS) +#define I2S_FER_INT_UMSK (~(((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS)) +#define I2S_CR_I2S_TXF_MASK I2S_CR_I2S_TXF_MASK +#define I2S_CR_I2S_TXF_MASK_POS (8U) +#define I2S_CR_I2S_TXF_MASK_LEN (1U) +#define I2S_CR_I2S_TXF_MASK_MSK (((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS) +#define I2S_CR_I2S_TXF_MASK_UMSK (~(((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS)) +#define I2S_CR_I2S_RXF_MASK I2S_CR_I2S_RXF_MASK +#define I2S_CR_I2S_RXF_MASK_POS (9U) +#define I2S_CR_I2S_RXF_MASK_LEN (1U) +#define I2S_CR_I2S_RXF_MASK_MSK (((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS) +#define I2S_CR_I2S_RXF_MASK_UMSK (~(((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS)) +#define I2S_CR_I2S_FER_MASK I2S_CR_I2S_FER_MASK +#define I2S_CR_I2S_FER_MASK_POS (10U) +#define I2S_CR_I2S_FER_MASK_LEN (1U) +#define I2S_CR_I2S_FER_MASK_MSK (((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS) +#define I2S_CR_I2S_FER_MASK_UMSK (~(((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS)) +#define I2S_CR_I2S_TXF_EN I2S_CR_I2S_TXF_EN +#define I2S_CR_I2S_TXF_EN_POS (24U) +#define I2S_CR_I2S_TXF_EN_LEN (1U) +#define I2S_CR_I2S_TXF_EN_MSK (((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS) +#define I2S_CR_I2S_TXF_EN_UMSK (~(((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS)) +#define I2S_CR_I2S_RXF_EN I2S_CR_I2S_RXF_EN +#define I2S_CR_I2S_RXF_EN_POS (25U) +#define I2S_CR_I2S_RXF_EN_LEN (1U) +#define I2S_CR_I2S_RXF_EN_MSK (((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS) +#define I2S_CR_I2S_RXF_EN_UMSK (~(((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS)) +#define I2S_CR_I2S_FER_EN I2S_CR_I2S_FER_EN +#define I2S_CR_I2S_FER_EN_POS (26U) +#define I2S_CR_I2S_FER_EN_LEN (1U) +#define I2S_CR_I2S_FER_EN_MSK (((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS) +#define I2S_CR_I2S_FER_EN_UMSK (~(((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS)) + +/* 0x10 : i2s_bclk_config */ +#define I2S_BCLK_CONFIG_OFFSET (0x10) +#define I2S_CR_BCLK_DIV_L I2S_CR_BCLK_DIV_L +#define I2S_CR_BCLK_DIV_L_POS (0U) +#define I2S_CR_BCLK_DIV_L_LEN (12U) +#define I2S_CR_BCLK_DIV_L_MSK (((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS) +#define I2S_CR_BCLK_DIV_L_UMSK (~(((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS)) +#define I2S_CR_BCLK_DIV_H I2S_CR_BCLK_DIV_H +#define I2S_CR_BCLK_DIV_H_POS (16U) +#define I2S_CR_BCLK_DIV_H_LEN (12U) +#define I2S_CR_BCLK_DIV_H_MSK (((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS) +#define I2S_CR_BCLK_DIV_H_UMSK (~(((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS)) + +/* 0x80 : i2s_fifo_config_0 */ +#define I2S_FIFO_CONFIG_0_OFFSET (0x80) +#define I2S_DMA_TX_EN I2S_DMA_TX_EN +#define I2S_DMA_TX_EN_POS (0U) +#define I2S_DMA_TX_EN_LEN (1U) +#define I2S_DMA_TX_EN_MSK (((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS) +#define I2S_DMA_TX_EN_UMSK (~(((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS)) +#define I2S_DMA_RX_EN I2S_DMA_RX_EN +#define I2S_DMA_RX_EN_POS (1U) +#define I2S_DMA_RX_EN_LEN (1U) +#define I2S_DMA_RX_EN_MSK (((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS) +#define I2S_DMA_RX_EN_UMSK (~(((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS)) +#define I2S_TX_FIFO_CLR I2S_TX_FIFO_CLR +#define I2S_TX_FIFO_CLR_POS (2U) +#define I2S_TX_FIFO_CLR_LEN (1U) +#define I2S_TX_FIFO_CLR_MSK (((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS) +#define I2S_TX_FIFO_CLR_UMSK (~(((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS)) +#define I2S_RX_FIFO_CLR I2S_RX_FIFO_CLR +#define I2S_RX_FIFO_CLR_POS (3U) +#define I2S_RX_FIFO_CLR_LEN (1U) +#define I2S_RX_FIFO_CLR_MSK (((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS) +#define I2S_RX_FIFO_CLR_UMSK (~(((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS)) +#define I2S_TX_FIFO_OVERFLOW I2S_TX_FIFO_OVERFLOW +#define I2S_TX_FIFO_OVERFLOW_POS (4U) +#define I2S_TX_FIFO_OVERFLOW_LEN (1U) +#define I2S_TX_FIFO_OVERFLOW_MSK (((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS) +#define I2S_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS)) +#define I2S_TX_FIFO_UNDERFLOW I2S_TX_FIFO_UNDERFLOW +#define I2S_TX_FIFO_UNDERFLOW_POS (5U) +#define I2S_TX_FIFO_UNDERFLOW_LEN (1U) +#define I2S_TX_FIFO_UNDERFLOW_MSK (((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS) +#define I2S_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS)) +#define I2S_RX_FIFO_OVERFLOW I2S_RX_FIFO_OVERFLOW +#define I2S_RX_FIFO_OVERFLOW_POS (6U) +#define I2S_RX_FIFO_OVERFLOW_LEN (1U) +#define I2S_RX_FIFO_OVERFLOW_MSK (((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS) +#define I2S_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS)) +#define I2S_RX_FIFO_UNDERFLOW I2S_RX_FIFO_UNDERFLOW +#define I2S_RX_FIFO_UNDERFLOW_POS (7U) +#define I2S_RX_FIFO_UNDERFLOW_LEN (1U) +#define I2S_RX_FIFO_UNDERFLOW_MSK (((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS) +#define I2S_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS)) +#define I2S_CR_FIFO_LR_MERGE I2S_CR_FIFO_LR_MERGE +#define I2S_CR_FIFO_LR_MERGE_POS (8U) +#define I2S_CR_FIFO_LR_MERGE_LEN (1U) +#define I2S_CR_FIFO_LR_MERGE_MSK (((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS) +#define I2S_CR_FIFO_LR_MERGE_UMSK (~(((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS)) +#define I2S_CR_FIFO_LR_EXCHG I2S_CR_FIFO_LR_EXCHG +#define I2S_CR_FIFO_LR_EXCHG_POS (9U) +#define I2S_CR_FIFO_LR_EXCHG_LEN (1U) +#define I2S_CR_FIFO_LR_EXCHG_MSK (((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS) +#define I2S_CR_FIFO_LR_EXCHG_UMSK (~(((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS)) +#define I2S_CR_FIFO_24B_LJ I2S_CR_FIFO_24B_LJ +#define I2S_CR_FIFO_24B_LJ_POS (10U) +#define I2S_CR_FIFO_24B_LJ_LEN (1U) +#define I2S_CR_FIFO_24B_LJ_MSK (((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS) +#define I2S_CR_FIFO_24B_LJ_UMSK (~(((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS)) + +/* 0x84 : i2s_fifo_config_1 */ +#define I2S_FIFO_CONFIG_1_OFFSET (0x84) +#define I2S_TX_FIFO_CNT I2S_TX_FIFO_CNT +#define I2S_TX_FIFO_CNT_POS (0U) +#define I2S_TX_FIFO_CNT_LEN (5U) +#define I2S_TX_FIFO_CNT_MSK (((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS) +#define I2S_TX_FIFO_CNT_UMSK (~(((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS)) +#define I2S_RX_FIFO_CNT I2S_RX_FIFO_CNT +#define I2S_RX_FIFO_CNT_POS (8U) +#define I2S_RX_FIFO_CNT_LEN (5U) +#define I2S_RX_FIFO_CNT_MSK (((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS) +#define I2S_RX_FIFO_CNT_UMSK (~(((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS)) +#define I2S_TX_FIFO_TH I2S_TX_FIFO_TH +#define I2S_TX_FIFO_TH_POS (16U) +#define I2S_TX_FIFO_TH_LEN (4U) +#define I2S_TX_FIFO_TH_MSK (((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS) +#define I2S_TX_FIFO_TH_UMSK (~(((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS)) +#define I2S_RX_FIFO_TH I2S_RX_FIFO_TH +#define I2S_RX_FIFO_TH_POS (24U) +#define I2S_RX_FIFO_TH_LEN (4U) +#define I2S_RX_FIFO_TH_MSK (((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS) +#define I2S_RX_FIFO_TH_UMSK (~(((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS)) + +/* 0x88 : i2s_fifo_wdata */ +#define I2S_FIFO_WDATA_OFFSET (0x88) +#define I2S_FIFO_WDATA I2S_FIFO_WDATA +#define I2S_FIFO_WDATA_POS (0U) +#define I2S_FIFO_WDATA_LEN (32U) +#define I2S_FIFO_WDATA_MSK (((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS) +#define I2S_FIFO_WDATA_UMSK (~(((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS)) + +/* 0x8C : i2s_fifo_rdata */ +#define I2S_FIFO_RDATA_OFFSET (0x8C) +#define I2S_FIFO_RDATA I2S_FIFO_RDATA +#define I2S_FIFO_RDATA_POS (0U) +#define I2S_FIFO_RDATA_LEN (32U) +#define I2S_FIFO_RDATA_MSK (((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS) +#define I2S_FIFO_RDATA_UMSK (~(((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS)) + +/* 0xFC : i2s_io_config */ +#define I2S_IO_CONFIG_OFFSET (0xFC) +#define I2S_CR_I2S_TXD_INV I2S_CR_I2S_TXD_INV +#define I2S_CR_I2S_TXD_INV_POS (0U) +#define I2S_CR_I2S_TXD_INV_LEN (1U) +#define I2S_CR_I2S_TXD_INV_MSK (((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS) +#define I2S_CR_I2S_TXD_INV_UMSK (~(((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS)) +#define I2S_CR_I2S_RXD_INV I2S_CR_I2S_RXD_INV +#define I2S_CR_I2S_RXD_INV_POS (1U) +#define I2S_CR_I2S_RXD_INV_LEN (1U) +#define I2S_CR_I2S_RXD_INV_MSK (((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS) +#define I2S_CR_I2S_RXD_INV_UMSK (~(((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS)) +#define I2S_CR_I2S_FS_INV I2S_CR_I2S_FS_INV +#define I2S_CR_I2S_FS_INV_POS (2U) +#define I2S_CR_I2S_FS_INV_LEN (1U) +#define I2S_CR_I2S_FS_INV_MSK (((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS) +#define I2S_CR_I2S_FS_INV_UMSK (~(((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS)) +#define I2S_CR_I2S_BCLK_INV I2S_CR_I2S_BCLK_INV +#define I2S_CR_I2S_BCLK_INV_POS (3U) +#define I2S_CR_I2S_BCLK_INV_LEN (1U) +#define I2S_CR_I2S_BCLK_INV_MSK (((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS) +#define I2S_CR_I2S_BCLK_INV_UMSK (~(((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS)) +#define I2S_CR_DEG_CNT I2S_CR_DEG_CNT +#define I2S_CR_DEG_CNT_POS (4U) +#define I2S_CR_DEG_CNT_LEN (3U) +#define I2S_CR_DEG_CNT_MSK (((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS) +#define I2S_CR_DEG_CNT_UMSK (~(((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS)) +#define I2S_CR_DEG_EN I2S_CR_DEG_EN +#define I2S_CR_DEG_EN_POS (7U) +#define I2S_CR_DEG_EN_LEN (1U) +#define I2S_CR_DEG_EN_MSK (((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS) +#define I2S_CR_DEG_EN_UMSK (~(((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS)) + +struct i2s_reg { + /* 0x0 : i2s_config */ + union { + struct + { + uint32_t cr_i2s_m_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_i2s_s_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_i2s_txd_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_i2s_rxd_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_mono_mode : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_mute_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_fs_1t_mode : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_fs_4ch_mode : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_fs_3ch_mode : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t cr_frame_size : 2; /* [13:12], r/w, 0x1 */ + uint32_t cr_data_size : 2; /* [15:14], r/w, 0x1 */ + uint32_t cr_i2s_mode : 2; /* [17:16], r/w, 0x0 */ + uint32_t cr_endian : 1; /* [ 18], r/w, 0x0 */ + uint32_t cr_mono_rx_ch : 1; /* [ 19], r/w, 0x0 */ + uint32_t cr_ofs_cnt : 5; /* [24:20], r/w, 0x0 */ + uint32_t cr_ofs_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2s_config; + + /* 0x4 : i2s_int_sts */ + union { + struct + { + uint32_t i2s_txf_int : 1; /* [ 0], r, 0x0 */ + uint32_t i2s_rxf_int : 1; /* [ 1], r, 0x0 */ + uint32_t i2s_fer_int : 1; /* [ 2], r, 0x0 */ + uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ + uint32_t cr_i2s_txf_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_i2s_rxf_mask : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_i2s_fer_mask : 1; /* [ 10], r/w, 0x1 */ + uint32_t reserved_11_23 : 13; /* [23:11], rsvd, 0x0 */ + uint32_t cr_i2s_txf_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t cr_i2s_rxf_en : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_i2s_fer_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2s_int_sts; + + /* 0x8 reserved */ + uint8_t RESERVED0x8[8]; + + /* 0x10 : i2s_bclk_config */ + union { + struct + { + uint32_t cr_bclk_div_l : 12; /* [11: 0], r/w, 0x1 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t cr_bclk_div_h : 12; /* [27:16], r/w, 0x1 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2s_bclk_config; + + /* 0x14 reserved */ + uint8_t RESERVED0x14[108]; + + /* 0x80 : i2s_fifo_config_0 */ + union { + struct + { + uint32_t i2s_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t i2s_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t cr_fifo_lr_merge : 1; /* [ 8], r/w, 0x0 */ + uint32_t cr_fifo_lr_exchg : 1; /* [ 9], r/w, 0x0 */ + uint32_t cr_fifo_24b_lj : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2s_fifo_config_0; + + /* 0x84 : i2s_fifo_config_1 */ + union { + struct + { + uint32_t tx_fifo_cnt : 5; /* [ 4: 0], r, 0x10 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t rx_fifo_cnt : 5; /* [12: 8], r, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t tx_fifo_th : 4; /* [19:16], r/w, 0x0 */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t rx_fifo_th : 4; /* [27:24], r/w, 0x0 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2s_fifo_config_1; + + /* 0x88 : i2s_fifo_wdata */ + union { + struct + { + uint32_t i2s_fifo_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } i2s_fifo_wdata; + + /* 0x8C : i2s_fifo_rdata */ + union { + struct + { + uint32_t i2s_fifo_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } i2s_fifo_rdata; + + /* 0x90 reserved */ + uint8_t RESERVED0x90[108]; + + /* 0xFC : i2s_io_config */ + union { + struct + { + uint32_t cr_i2s_txd_inv : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_i2s_rxd_inv : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_i2s_fs_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_i2s_bclk_inv : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_deg_cnt : 3; /* [ 6: 4], r/w, 0x0 */ + uint32_t cr_deg_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } i2s_io_config; +}; + +typedef volatile struct i2s_reg i2s_reg_t; + +#endif /* __I2S_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ir_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ir_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..de0cc214b89281664a4273ae57b7bf6d63ea0fcb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/ir_reg.h @@ -0,0 +1,652 @@ +/** + ****************************************************************************** + * @file ir_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __IR_REG_H__ +#define __IR_REG_H__ + +#include "bl702.h" + +/* 0x0 : irtx_config */ +#define IRTX_CONFIG_OFFSET (0x0) +#define IR_CR_IRTX_EN IR_CR_IRTX_EN +#define IR_CR_IRTX_EN_POS (0U) +#define IR_CR_IRTX_EN_LEN (1U) +#define IR_CR_IRTX_EN_MSK (((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS) +#define IR_CR_IRTX_EN_UMSK (~(((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS)) +#define IR_CR_IRTX_OUT_INV IR_CR_IRTX_OUT_INV +#define IR_CR_IRTX_OUT_INV_POS (1U) +#define IR_CR_IRTX_OUT_INV_LEN (1U) +#define IR_CR_IRTX_OUT_INV_MSK (((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS) +#define IR_CR_IRTX_OUT_INV_UMSK (~(((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS)) +#define IR_CR_IRTX_MOD_EN IR_CR_IRTX_MOD_EN +#define IR_CR_IRTX_MOD_EN_POS (2U) +#define IR_CR_IRTX_MOD_EN_LEN (1U) +#define IR_CR_IRTX_MOD_EN_MSK (((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS) +#define IR_CR_IRTX_MOD_EN_UMSK (~(((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS)) +#define IR_CR_IRTX_SWM_EN IR_CR_IRTX_SWM_EN +#define IR_CR_IRTX_SWM_EN_POS (3U) +#define IR_CR_IRTX_SWM_EN_LEN (1U) +#define IR_CR_IRTX_SWM_EN_MSK (((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS) +#define IR_CR_IRTX_SWM_EN_UMSK (~(((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS)) +#define IR_CR_IRTX_DATA_EN IR_CR_IRTX_DATA_EN +#define IR_CR_IRTX_DATA_EN_POS (4U) +#define IR_CR_IRTX_DATA_EN_LEN (1U) +#define IR_CR_IRTX_DATA_EN_MSK (((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS) +#define IR_CR_IRTX_DATA_EN_UMSK (~(((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS)) +#define IR_CR_IRTX_LOGIC0_HL_INV IR_CR_IRTX_LOGIC0_HL_INV +#define IR_CR_IRTX_LOGIC0_HL_INV_POS (5U) +#define IR_CR_IRTX_LOGIC0_HL_INV_LEN (1U) +#define IR_CR_IRTX_LOGIC0_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS) +#define IR_CR_IRTX_LOGIC0_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS)) +#define IR_CR_IRTX_LOGIC1_HL_INV IR_CR_IRTX_LOGIC1_HL_INV +#define IR_CR_IRTX_LOGIC1_HL_INV_POS (6U) +#define IR_CR_IRTX_LOGIC1_HL_INV_LEN (1U) +#define IR_CR_IRTX_LOGIC1_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS) +#define IR_CR_IRTX_LOGIC1_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS)) +#define IR_CR_IRTX_HEAD_EN IR_CR_IRTX_HEAD_EN +#define IR_CR_IRTX_HEAD_EN_POS (8U) +#define IR_CR_IRTX_HEAD_EN_LEN (1U) +#define IR_CR_IRTX_HEAD_EN_MSK (((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS) +#define IR_CR_IRTX_HEAD_EN_UMSK (~(((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS)) +#define IR_CR_IRTX_HEAD_HL_INV IR_CR_IRTX_HEAD_HL_INV +#define IR_CR_IRTX_HEAD_HL_INV_POS (9U) +#define IR_CR_IRTX_HEAD_HL_INV_LEN (1U) +#define IR_CR_IRTX_HEAD_HL_INV_MSK (((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS) +#define IR_CR_IRTX_HEAD_HL_INV_UMSK (~(((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS)) +#define IR_CR_IRTX_TAIL_EN IR_CR_IRTX_TAIL_EN +#define IR_CR_IRTX_TAIL_EN_POS (10U) +#define IR_CR_IRTX_TAIL_EN_LEN (1U) +#define IR_CR_IRTX_TAIL_EN_MSK (((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS) +#define IR_CR_IRTX_TAIL_EN_UMSK (~(((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS)) +#define IR_CR_IRTX_TAIL_HL_INV IR_CR_IRTX_TAIL_HL_INV +#define IR_CR_IRTX_TAIL_HL_INV_POS (11U) +#define IR_CR_IRTX_TAIL_HL_INV_LEN (1U) +#define IR_CR_IRTX_TAIL_HL_INV_MSK (((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS) +#define IR_CR_IRTX_TAIL_HL_INV_UMSK (~(((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS)) +#define IR_CR_IRTX_DATA_NUM IR_CR_IRTX_DATA_NUM +#define IR_CR_IRTX_DATA_NUM_POS (12U) +#define IR_CR_IRTX_DATA_NUM_LEN (6U) +#define IR_CR_IRTX_DATA_NUM_MSK (((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS) +#define IR_CR_IRTX_DATA_NUM_UMSK (~(((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS)) + +/* 0x4 : irtx_int_sts */ +#define IRTX_INT_STS_OFFSET (0x4) +#define IRTX_END_INT IRTX_END_INT +#define IRTX_END_INT_POS (0U) +#define IRTX_END_INT_LEN (1U) +#define IRTX_END_INT_MSK (((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS) +#define IRTX_END_INT_UMSK (~(((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS)) +#define IR_CR_IRTX_END_MASK IR_CR_IRTX_END_MASK +#define IR_CR_IRTX_END_MASK_POS (8U) +#define IR_CR_IRTX_END_MASK_LEN (1U) +#define IR_CR_IRTX_END_MASK_MSK (((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS) +#define IR_CR_IRTX_END_MASK_UMSK (~(((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS)) +#define IR_CR_IRTX_END_CLR IR_CR_IRTX_END_CLR +#define IR_CR_IRTX_END_CLR_POS (16U) +#define IR_CR_IRTX_END_CLR_LEN (1U) +#define IR_CR_IRTX_END_CLR_MSK (((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS) +#define IR_CR_IRTX_END_CLR_UMSK (~(((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS)) +#define IR_CR_IRTX_END_EN IR_CR_IRTX_END_EN +#define IR_CR_IRTX_END_EN_POS (24U) +#define IR_CR_IRTX_END_EN_LEN (1U) +#define IR_CR_IRTX_END_EN_MSK (((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS) +#define IR_CR_IRTX_END_EN_UMSK (~(((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS)) + +/* 0x8 : irtx_data_word0 */ +#define IRTX_DATA_WORD0_OFFSET (0x8) +#define IR_CR_IRTX_DATA_WORD0 IR_CR_IRTX_DATA_WORD0 +#define IR_CR_IRTX_DATA_WORD0_POS (0U) +#define IR_CR_IRTX_DATA_WORD0_LEN (32U) +#define IR_CR_IRTX_DATA_WORD0_MSK (((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS) +#define IR_CR_IRTX_DATA_WORD0_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS)) + +/* 0xC : irtx_data_word1 */ +#define IRTX_DATA_WORD1_OFFSET (0xC) +#define IR_CR_IRTX_DATA_WORD1 IR_CR_IRTX_DATA_WORD1 +#define IR_CR_IRTX_DATA_WORD1_POS (0U) +#define IR_CR_IRTX_DATA_WORD1_LEN (32U) +#define IR_CR_IRTX_DATA_WORD1_MSK (((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS) +#define IR_CR_IRTX_DATA_WORD1_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS)) + +/* 0x10 : irtx_pulse_width */ +#define IRTX_PULSE_WIDTH_OFFSET (0x10) +#define IR_CR_IRTX_PW_UNIT IR_CR_IRTX_PW_UNIT +#define IR_CR_IRTX_PW_UNIT_POS (0U) +#define IR_CR_IRTX_PW_UNIT_LEN (12U) +#define IR_CR_IRTX_PW_UNIT_MSK (((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS) +#define IR_CR_IRTX_PW_UNIT_UMSK (~(((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS)) +#define IR_CR_IRTX_MOD_PH0_W IR_CR_IRTX_MOD_PH0_W +#define IR_CR_IRTX_MOD_PH0_W_POS (16U) +#define IR_CR_IRTX_MOD_PH0_W_LEN (8U) +#define IR_CR_IRTX_MOD_PH0_W_MSK (((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS) +#define IR_CR_IRTX_MOD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS)) +#define IR_CR_IRTX_MOD_PH1_W IR_CR_IRTX_MOD_PH1_W +#define IR_CR_IRTX_MOD_PH1_W_POS (24U) +#define IR_CR_IRTX_MOD_PH1_W_LEN (8U) +#define IR_CR_IRTX_MOD_PH1_W_MSK (((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS) +#define IR_CR_IRTX_MOD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS)) + +/* 0x14 : irtx_pw */ +#define IRTX_PW_OFFSET (0x14) +#define IR_CR_IRTX_LOGIC0_PH0_W IR_CR_IRTX_LOGIC0_PH0_W +#define IR_CR_IRTX_LOGIC0_PH0_W_POS (0U) +#define IR_CR_IRTX_LOGIC0_PH0_W_LEN (4U) +#define IR_CR_IRTX_LOGIC0_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS) +#define IR_CR_IRTX_LOGIC0_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS)) +#define IR_CR_IRTX_LOGIC0_PH1_W IR_CR_IRTX_LOGIC0_PH1_W +#define IR_CR_IRTX_LOGIC0_PH1_W_POS (4U) +#define IR_CR_IRTX_LOGIC0_PH1_W_LEN (4U) +#define IR_CR_IRTX_LOGIC0_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS) +#define IR_CR_IRTX_LOGIC0_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS)) +#define IR_CR_IRTX_LOGIC1_PH0_W IR_CR_IRTX_LOGIC1_PH0_W +#define IR_CR_IRTX_LOGIC1_PH0_W_POS (8U) +#define IR_CR_IRTX_LOGIC1_PH0_W_LEN (4U) +#define IR_CR_IRTX_LOGIC1_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS) +#define IR_CR_IRTX_LOGIC1_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS)) +#define IR_CR_IRTX_LOGIC1_PH1_W IR_CR_IRTX_LOGIC1_PH1_W +#define IR_CR_IRTX_LOGIC1_PH1_W_POS (12U) +#define IR_CR_IRTX_LOGIC1_PH1_W_LEN (4U) +#define IR_CR_IRTX_LOGIC1_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS) +#define IR_CR_IRTX_LOGIC1_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS)) +#define IR_CR_IRTX_HEAD_PH0_W IR_CR_IRTX_HEAD_PH0_W +#define IR_CR_IRTX_HEAD_PH0_W_POS (16U) +#define IR_CR_IRTX_HEAD_PH0_W_LEN (4U) +#define IR_CR_IRTX_HEAD_PH0_W_MSK (((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS) +#define IR_CR_IRTX_HEAD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS)) +#define IR_CR_IRTX_HEAD_PH1_W IR_CR_IRTX_HEAD_PH1_W +#define IR_CR_IRTX_HEAD_PH1_W_POS (20U) +#define IR_CR_IRTX_HEAD_PH1_W_LEN (4U) +#define IR_CR_IRTX_HEAD_PH1_W_MSK (((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS) +#define IR_CR_IRTX_HEAD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS)) +#define IR_CR_IRTX_TAIL_PH0_W IR_CR_IRTX_TAIL_PH0_W +#define IR_CR_IRTX_TAIL_PH0_W_POS (24U) +#define IR_CR_IRTX_TAIL_PH0_W_LEN (4U) +#define IR_CR_IRTX_TAIL_PH0_W_MSK (((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS) +#define IR_CR_IRTX_TAIL_PH0_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS)) +#define IR_CR_IRTX_TAIL_PH1_W IR_CR_IRTX_TAIL_PH1_W +#define IR_CR_IRTX_TAIL_PH1_W_POS (28U) +#define IR_CR_IRTX_TAIL_PH1_W_LEN (4U) +#define IR_CR_IRTX_TAIL_PH1_W_MSK (((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS) +#define IR_CR_IRTX_TAIL_PH1_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS)) + +/* 0x40 : irtx_swm_pw_0 */ +#define IRTX_SWM_PW_0_OFFSET (0x40) +#define IR_CR_IRTX_SWM_PW_0 IR_CR_IRTX_SWM_PW_0 +#define IR_CR_IRTX_SWM_PW_0_POS (0U) +#define IR_CR_IRTX_SWM_PW_0_LEN (32U) +#define IR_CR_IRTX_SWM_PW_0_MSK (((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS) +#define IR_CR_IRTX_SWM_PW_0_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS)) + +/* 0x44 : irtx_swm_pw_1 */ +#define IRTX_SWM_PW_1_OFFSET (0x44) +#define IR_CR_IRTX_SWM_PW_1 IR_CR_IRTX_SWM_PW_1 +#define IR_CR_IRTX_SWM_PW_1_POS (0U) +#define IR_CR_IRTX_SWM_PW_1_LEN (32U) +#define IR_CR_IRTX_SWM_PW_1_MSK (((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS) +#define IR_CR_IRTX_SWM_PW_1_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS)) + +/* 0x48 : irtx_swm_pw_2 */ +#define IRTX_SWM_PW_2_OFFSET (0x48) +#define IR_CR_IRTX_SWM_PW_2 IR_CR_IRTX_SWM_PW_2 +#define IR_CR_IRTX_SWM_PW_2_POS (0U) +#define IR_CR_IRTX_SWM_PW_2_LEN (32U) +#define IR_CR_IRTX_SWM_PW_2_MSK (((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS) +#define IR_CR_IRTX_SWM_PW_2_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS)) + +/* 0x4C : irtx_swm_pw_3 */ +#define IRTX_SWM_PW_3_OFFSET (0x4C) +#define IR_CR_IRTX_SWM_PW_3 IR_CR_IRTX_SWM_PW_3 +#define IR_CR_IRTX_SWM_PW_3_POS (0U) +#define IR_CR_IRTX_SWM_PW_3_LEN (32U) +#define IR_CR_IRTX_SWM_PW_3_MSK (((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS) +#define IR_CR_IRTX_SWM_PW_3_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS)) + +/* 0x50 : irtx_swm_pw_4 */ +#define IRTX_SWM_PW_4_OFFSET (0x50) +#define IR_CR_IRTX_SWM_PW_4 IR_CR_IRTX_SWM_PW_4 +#define IR_CR_IRTX_SWM_PW_4_POS (0U) +#define IR_CR_IRTX_SWM_PW_4_LEN (32U) +#define IR_CR_IRTX_SWM_PW_4_MSK (((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS) +#define IR_CR_IRTX_SWM_PW_4_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS)) + +/* 0x54 : irtx_swm_pw_5 */ +#define IRTX_SWM_PW_5_OFFSET (0x54) +#define IR_CR_IRTX_SWM_PW_5 IR_CR_IRTX_SWM_PW_5 +#define IR_CR_IRTX_SWM_PW_5_POS (0U) +#define IR_CR_IRTX_SWM_PW_5_LEN (32U) +#define IR_CR_IRTX_SWM_PW_5_MSK (((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS) +#define IR_CR_IRTX_SWM_PW_5_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS)) + +/* 0x58 : irtx_swm_pw_6 */ +#define IRTX_SWM_PW_6_OFFSET (0x58) +#define IR_CR_IRTX_SWM_PW_6 IR_CR_IRTX_SWM_PW_6 +#define IR_CR_IRTX_SWM_PW_6_POS (0U) +#define IR_CR_IRTX_SWM_PW_6_LEN (32U) +#define IR_CR_IRTX_SWM_PW_6_MSK (((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS) +#define IR_CR_IRTX_SWM_PW_6_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS)) + +/* 0x5C : irtx_swm_pw_7 */ +#define IRTX_SWM_PW_7_OFFSET (0x5C) +#define IR_CR_IRTX_SWM_PW_7 IR_CR_IRTX_SWM_PW_7 +#define IR_CR_IRTX_SWM_PW_7_POS (0U) +#define IR_CR_IRTX_SWM_PW_7_LEN (32U) +#define IR_CR_IRTX_SWM_PW_7_MSK (((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS) +#define IR_CR_IRTX_SWM_PW_7_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS)) + +/* 0x80 : irrx_config */ +#define IRRX_CONFIG_OFFSET (0x80) +#define IR_CR_IRRX_EN IR_CR_IRRX_EN +#define IR_CR_IRRX_EN_POS (0U) +#define IR_CR_IRRX_EN_LEN (1U) +#define IR_CR_IRRX_EN_MSK (((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS) +#define IR_CR_IRRX_EN_UMSK (~(((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS)) +#define IR_CR_IRRX_IN_INV IR_CR_IRRX_IN_INV +#define IR_CR_IRRX_IN_INV_POS (1U) +#define IR_CR_IRRX_IN_INV_LEN (1U) +#define IR_CR_IRRX_IN_INV_MSK (((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS) +#define IR_CR_IRRX_IN_INV_UMSK (~(((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS)) +#define IR_CR_IRRX_MODE IR_CR_IRRX_MODE +#define IR_CR_IRRX_MODE_POS (2U) +#define IR_CR_IRRX_MODE_LEN (2U) +#define IR_CR_IRRX_MODE_MSK (((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS) +#define IR_CR_IRRX_MODE_UMSK (~(((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS)) +#define IR_CR_IRRX_DEG_EN IR_CR_IRRX_DEG_EN +#define IR_CR_IRRX_DEG_EN_POS (4U) +#define IR_CR_IRRX_DEG_EN_LEN (1U) +#define IR_CR_IRRX_DEG_EN_MSK (((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS) +#define IR_CR_IRRX_DEG_EN_UMSK (~(((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS)) +#define IR_CR_IRRX_DEG_CNT IR_CR_IRRX_DEG_CNT +#define IR_CR_IRRX_DEG_CNT_POS (8U) +#define IR_CR_IRRX_DEG_CNT_LEN (4U) +#define IR_CR_IRRX_DEG_CNT_MSK (((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS) +#define IR_CR_IRRX_DEG_CNT_UMSK (~(((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS)) + +/* 0x84 : irrx_int_sts */ +#define IRRX_INT_STS_OFFSET (0x84) +#define IRRX_END_INT IRRX_END_INT +#define IRRX_END_INT_POS (0U) +#define IRRX_END_INT_LEN (1U) +#define IRRX_END_INT_MSK (((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS) +#define IRRX_END_INT_UMSK (~(((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS)) +#define IR_CR_IRRX_END_MASK IR_CR_IRRX_END_MASK +#define IR_CR_IRRX_END_MASK_POS (8U) +#define IR_CR_IRRX_END_MASK_LEN (1U) +#define IR_CR_IRRX_END_MASK_MSK (((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS) +#define IR_CR_IRRX_END_MASK_UMSK (~(((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS)) +#define IR_CR_IRRX_END_CLR IR_CR_IRRX_END_CLR +#define IR_CR_IRRX_END_CLR_POS (16U) +#define IR_CR_IRRX_END_CLR_LEN (1U) +#define IR_CR_IRRX_END_CLR_MSK (((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS) +#define IR_CR_IRRX_END_CLR_UMSK (~(((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS)) +#define IR_CR_IRRX_END_EN IR_CR_IRRX_END_EN +#define IR_CR_IRRX_END_EN_POS (24U) +#define IR_CR_IRRX_END_EN_LEN (1U) +#define IR_CR_IRRX_END_EN_MSK (((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS) +#define IR_CR_IRRX_END_EN_UMSK (~(((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS)) + +/* 0x88 : irrx_pw_config */ +#define IRRX_PW_CONFIG_OFFSET (0x88) +#define IR_CR_IRRX_DATA_TH IR_CR_IRRX_DATA_TH +#define IR_CR_IRRX_DATA_TH_POS (0U) +#define IR_CR_IRRX_DATA_TH_LEN (16U) +#define IR_CR_IRRX_DATA_TH_MSK (((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS) +#define IR_CR_IRRX_DATA_TH_UMSK (~(((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS)) +#define IR_CR_IRRX_END_TH IR_CR_IRRX_END_TH +#define IR_CR_IRRX_END_TH_POS (16U) +#define IR_CR_IRRX_END_TH_LEN (16U) +#define IR_CR_IRRX_END_TH_MSK (((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS) +#define IR_CR_IRRX_END_TH_UMSK (~(((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS)) + +/* 0x90 : irrx_data_count */ +#define IRRX_DATA_COUNT_OFFSET (0x90) +#define IR_STS_IRRX_DATA_CNT IR_STS_IRRX_DATA_CNT +#define IR_STS_IRRX_DATA_CNT_POS (0U) +#define IR_STS_IRRX_DATA_CNT_LEN (7U) +#define IR_STS_IRRX_DATA_CNT_MSK (((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS) +#define IR_STS_IRRX_DATA_CNT_UMSK (~(((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS)) + +/* 0x94 : irrx_data_word0 */ +#define IRRX_DATA_WORD0_OFFSET (0x94) +#define IR_STS_IRRX_DATA_WORD0 IR_STS_IRRX_DATA_WORD0 +#define IR_STS_IRRX_DATA_WORD0_POS (0U) +#define IR_STS_IRRX_DATA_WORD0_LEN (32U) +#define IR_STS_IRRX_DATA_WORD0_MSK (((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS) +#define IR_STS_IRRX_DATA_WORD0_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS)) + +/* 0x98 : irrx_data_word1 */ +#define IRRX_DATA_WORD1_OFFSET (0x98) +#define IR_STS_IRRX_DATA_WORD1 IR_STS_IRRX_DATA_WORD1 +#define IR_STS_IRRX_DATA_WORD1_POS (0U) +#define IR_STS_IRRX_DATA_WORD1_LEN (32U) +#define IR_STS_IRRX_DATA_WORD1_MSK (((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS) +#define IR_STS_IRRX_DATA_WORD1_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS)) + +/* 0xC0 : irrx_swm_fifo_config_0 */ +#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0) +#define IR_RX_FIFO_CLR IR_RX_FIFO_CLR +#define IR_RX_FIFO_CLR_POS (0U) +#define IR_RX_FIFO_CLR_LEN (1U) +#define IR_RX_FIFO_CLR_MSK (((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS) +#define IR_RX_FIFO_CLR_UMSK (~(((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS)) +#define IR_RX_FIFO_OVERFLOW IR_RX_FIFO_OVERFLOW +#define IR_RX_FIFO_OVERFLOW_POS (2U) +#define IR_RX_FIFO_OVERFLOW_LEN (1U) +#define IR_RX_FIFO_OVERFLOW_MSK (((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS) +#define IR_RX_FIFO_OVERFLOW_UMSK (~(((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS)) +#define IR_RX_FIFO_UNDERFLOW IR_RX_FIFO_UNDERFLOW +#define IR_RX_FIFO_UNDERFLOW_POS (3U) +#define IR_RX_FIFO_UNDERFLOW_LEN (1U) +#define IR_RX_FIFO_UNDERFLOW_MSK (((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS) +#define IR_RX_FIFO_UNDERFLOW_UMSK (~(((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS)) +#define IR_RX_FIFO_CNT IR_RX_FIFO_CNT +#define IR_RX_FIFO_CNT_POS (4U) +#define IR_RX_FIFO_CNT_LEN (7U) +#define IR_RX_FIFO_CNT_MSK (((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS) +#define IR_RX_FIFO_CNT_UMSK (~(((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS)) + +/* 0xC4 : irrx_swm_fifo_rdata */ +#define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4) +#define IR_RX_FIFO_RDATA IR_RX_FIFO_RDATA +#define IR_RX_FIFO_RDATA_POS (0U) +#define IR_RX_FIFO_RDATA_LEN (16U) +#define IR_RX_FIFO_RDATA_MSK (((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS) +#define IR_RX_FIFO_RDATA_UMSK (~(((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS)) + +struct ir_reg { + /* 0x0 : irtx_config */ + union { + struct + { + uint32_t cr_irtx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_irtx_out_inv : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_irtx_mod_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_irtx_swm_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_irtx_data_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t cr_irtx_logic0_hl_inv : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_irtx_logic1_hl_inv : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cr_irtx_head_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_irtx_head_hl_inv : 1; /* [ 9], r/w, 0x0 */ + uint32_t cr_irtx_tail_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_irtx_tail_hl_inv : 1; /* [ 11], r/w, 0x0 */ + uint32_t cr_irtx_data_num : 6; /* [17:12], r/w, 0x1f */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irtx_config; + + /* 0x4 : irtx_int_sts */ + union { + struct + { + uint32_t irtx_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ + uint32_t cr_irtx_end_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ + uint32_t cr_irtx_end_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ + uint32_t cr_irtx_end_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irtx_int_sts; + + /* 0x8 : irtx_data_word0 */ + union { + struct + { + uint32_t cr_irtx_data_word0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_data_word0; + + /* 0xC : irtx_data_word1 */ + union { + struct + { + uint32_t cr_irtx_data_word1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_data_word1; + + /* 0x10 : irtx_pulse_width */ + union { + struct + { + uint32_t cr_irtx_pw_unit : 12; /* [11: 0], r/w, 0x464 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t cr_irtx_mod_ph0_w : 8; /* [23:16], r/w, 0x11 */ + uint32_t cr_irtx_mod_ph1_w : 8; /* [31:24], r/w, 0x22 */ + } BF; + uint32_t WORD; + } irtx_pulse_width; + + /* 0x14 : irtx_pw */ + union { + struct + { + uint32_t cr_irtx_logic0_ph0_w : 4; /* [ 3: 0], r/w, 0x0 */ + uint32_t cr_irtx_logic0_ph1_w : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t cr_irtx_logic1_ph0_w : 4; /* [11: 8], r/w, 0x0 */ + uint32_t cr_irtx_logic1_ph1_w : 4; /* [15:12], r/w, 0x2 */ + uint32_t cr_irtx_head_ph0_w : 4; /* [19:16], r/w, 0xf */ + uint32_t cr_irtx_head_ph1_w : 4; /* [23:20], r/w, 0x7 */ + uint32_t cr_irtx_tail_ph0_w : 4; /* [27:24], r/w, 0x0 */ + uint32_t cr_irtx_tail_ph1_w : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_pw; + + /* 0x18 reserved */ + uint8_t RESERVED0x18[40]; + + /* 0x40 : irtx_swm_pw_0 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_0; + + /* 0x44 : irtx_swm_pw_1 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_1; + + /* 0x48 : irtx_swm_pw_2 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_2; + + /* 0x4C : irtx_swm_pw_3 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_3; + + /* 0x50 : irtx_swm_pw_4 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_4; + + /* 0x54 : irtx_swm_pw_5 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_5; + + /* 0x58 : irtx_swm_pw_6 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_6; + + /* 0x5C : irtx_swm_pw_7 */ + union { + struct + { + uint32_t cr_irtx_swm_pw_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } irtx_swm_pw_7; + + /* 0x60 reserved */ + uint8_t RESERVED0x60[32]; + + /* 0x80 : irrx_config */ + union { + struct + { + uint32_t cr_irrx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_irrx_in_inv : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_irrx_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t cr_irrx_deg_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t cr_irrx_deg_cnt : 4; /* [11: 8], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_config; + + /* 0x84 : irrx_int_sts */ + union { + struct + { + uint32_t irrx_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ + uint32_t cr_irrx_end_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ + uint32_t cr_irrx_end_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ + uint32_t cr_irrx_end_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_int_sts; + + /* 0x88 : irrx_pw_config */ + union { + struct + { + uint32_t cr_irrx_data_th : 16; /* [15: 0], r/w, 0xd47 */ + uint32_t cr_irrx_end_th : 16; /* [31:16], r/w, 0x2327 */ + } BF; + uint32_t WORD; + } irrx_pw_config; + + /* 0x8c reserved */ + uint8_t RESERVED0x8c[4]; + + /* 0x90 : irrx_data_count */ + union { + struct + { + uint32_t sts_irrx_data_cnt : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_data_count; + + /* 0x94 : irrx_data_word0 */ + union { + struct + { + uint32_t sts_irrx_data_word0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } irrx_data_word0; + + /* 0x98 : irrx_data_word1 */ + union { + struct + { + uint32_t sts_irrx_data_word1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } irrx_data_word1; + + /* 0x9c reserved */ + uint8_t RESERVED0x9c[36]; + + /* 0xC0 : irrx_swm_fifo_config_0 */ + union { + struct + { + uint32_t rx_fifo_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 2], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 3], r, 0x0 */ + uint32_t rx_fifo_cnt : 7; /* [10: 4], r, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_swm_fifo_config_0; + + /* 0xC4 : irrx_swm_fifo_rdata */ + union { + struct + { + uint32_t rx_fifo_rdata : 16; /* [15: 0], r, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } irrx_swm_fifo_rdata; +}; + +typedef volatile struct ir_reg ir_reg_t; + +#endif /* __IR_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/kys_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/kys_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..b2a9890a35a4b34c9f052b1a5a5fe32e25575513 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/kys_reg.h @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file kys_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __KYS_REG_H__ +#define __KYS_REG_H__ + +#include "bl702.h" + +/* 0x0 : ks_ctrl */ +#define KYS_KS_CTRL_OFFSET (0x0) +#define KYS_KS_EN KYS_KS_EN +#define KYS_KS_EN_POS (0U) +#define KYS_KS_EN_LEN (1U) +#define KYS_KS_EN_MSK (((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS) +#define KYS_KS_EN_UMSK (~(((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS)) +#define KYS_GHOST_EN KYS_GHOST_EN +#define KYS_GHOST_EN_POS (2U) +#define KYS_GHOST_EN_LEN (1U) +#define KYS_GHOST_EN_MSK (((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS) +#define KYS_GHOST_EN_UMSK (~(((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS)) +#define KYS_DEG_EN KYS_DEG_EN +#define KYS_DEG_EN_POS (3U) +#define KYS_DEG_EN_LEN (1U) +#define KYS_DEG_EN_MSK (((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS) +#define KYS_DEG_EN_UMSK (~(((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS)) +#define KYS_DEG_CNT KYS_DEG_CNT +#define KYS_DEG_CNT_POS (4U) +#define KYS_DEG_CNT_LEN (4U) +#define KYS_DEG_CNT_MSK (((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS) +#define KYS_DEG_CNT_UMSK (~(((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS)) +#define KYS_RC_EXT KYS_RC_EXT +#define KYS_RC_EXT_POS (8U) +#define KYS_RC_EXT_LEN (2U) +#define KYS_RC_EXT_MSK (((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS) +#define KYS_RC_EXT_UMSK (~(((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS)) +#define KYS_ROW_NUM KYS_ROW_NUM +#define KYS_ROW_NUM_POS (16U) +#define KYS_ROW_NUM_LEN (3U) +#define KYS_ROW_NUM_MSK (((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS) +#define KYS_ROW_NUM_UMSK (~(((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS)) +#define KYS_COL_NUM KYS_COL_NUM +#define KYS_COL_NUM_POS (20U) +#define KYS_COL_NUM_LEN (5U) +#define KYS_COL_NUM_MSK (((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS) +#define KYS_COL_NUM_UMSK (~(((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS)) + +/* 0x10 : ks_int_en */ +#define KYS_KS_INT_EN_OFFSET (0x10) +#define KYS_KS_INT_EN KYS_KS_INT_EN +#define KYS_KS_INT_EN_POS (0U) +#define KYS_KS_INT_EN_LEN (1U) +#define KYS_KS_INT_EN_MSK (((1U << KYS_KS_INT_EN_LEN) - 1) << KYS_KS_INT_EN_POS) +#define KYS_KS_INT_EN_UMSK (~(((1U << KYS_KS_INT_EN_LEN) - 1) << KYS_KS_INT_EN_POS)) + +/* 0x14 : ks_int_sts */ +#define KYS_KS_INT_STS_OFFSET (0x14) +#define KYS_KEYCODE_VALID KYS_KEYCODE_VALID +#define KYS_KEYCODE_VALID_POS (0U) +#define KYS_KEYCODE_VALID_LEN (4U) +#define KYS_KEYCODE_VALID_MSK (((1U << KYS_KEYCODE_VALID_LEN) - 1) << KYS_KEYCODE_VALID_POS) +#define KYS_KEYCODE_VALID_UMSK (~(((1U << KYS_KEYCODE_VALID_LEN) - 1) << KYS_KEYCODE_VALID_POS)) + +/* 0x18 : keycode_clr */ +#define KYS_KEYCODE_CLR_OFFSET (0x18) +#define KYS_KEYCODE_CLR KYS_KEYCODE_CLR +#define KYS_KEYCODE_CLR_POS (0U) +#define KYS_KEYCODE_CLR_LEN (4U) +#define KYS_KEYCODE_CLR_MSK (((1U << KYS_KEYCODE_CLR_LEN) - 1) << KYS_KEYCODE_CLR_POS) +#define KYS_KEYCODE_CLR_UMSK (~(((1U << KYS_KEYCODE_CLR_LEN) - 1) << KYS_KEYCODE_CLR_POS)) + +/* 0x1C : keycode_value */ +#define KYS_KEYCODE_VALUE_OFFSET (0x1C) +#define KYS_KEYCODE0 KYS_KEYCODE0 +#define KYS_KEYCODE0_POS (0U) +#define KYS_KEYCODE0_LEN (8U) +#define KYS_KEYCODE0_MSK (((1U << KYS_KEYCODE0_LEN) - 1) << KYS_KEYCODE0_POS) +#define KYS_KEYCODE0_UMSK (~(((1U << KYS_KEYCODE0_LEN) - 1) << KYS_KEYCODE0_POS)) +#define KYS_KEYCODE1 KYS_KEYCODE1 +#define KYS_KEYCODE1_POS (8U) +#define KYS_KEYCODE1_LEN (8U) +#define KYS_KEYCODE1_MSK (((1U << KYS_KEYCODE1_LEN) - 1) << KYS_KEYCODE1_POS) +#define KYS_KEYCODE1_UMSK (~(((1U << KYS_KEYCODE1_LEN) - 1) << KYS_KEYCODE1_POS)) +#define KYS_KEYCODE2 KYS_KEYCODE2 +#define KYS_KEYCODE2_POS (16U) +#define KYS_KEYCODE2_LEN (8U) +#define KYS_KEYCODE2_MSK (((1U << KYS_KEYCODE2_LEN) - 1) << KYS_KEYCODE2_POS) +#define KYS_KEYCODE2_UMSK (~(((1U << KYS_KEYCODE2_LEN) - 1) << KYS_KEYCODE2_POS)) +#define KYS_KEYCODE3 KYS_KEYCODE3 +#define KYS_KEYCODE3_POS (24U) +#define KYS_KEYCODE3_LEN (8U) +#define KYS_KEYCODE3_MSK (((1U << KYS_KEYCODE3_LEN) - 1) << KYS_KEYCODE3_POS) +#define KYS_KEYCODE3_UMSK (~(((1U << KYS_KEYCODE3_LEN) - 1) << KYS_KEYCODE3_POS)) + +struct kys_reg { + /* 0x0 : ks_ctrl */ + union { + struct + { + uint32_t ks_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t ghost_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t rc_ext : 2; /* [ 9: 8], r/w, 0x3 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t row_num : 3; /* [18:16], r/w, 0x7 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t col_num : 5; /* [24:20], r/w, 0x13 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ks_ctrl; + + /* 0x4 reserved */ + uint8_t RESERVED0x4[12]; + + /* 0x10 : ks_int_en */ + union { + struct + { + uint32_t ks_int_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ks_int_en; + + /* 0x14 : ks_int_sts */ + union { + struct + { + uint32_t keycode_valid : 4; /* [ 3: 0], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ks_int_sts; + + /* 0x18 : keycode_clr */ + union { + struct + { + uint32_t keycode_clr : 4; /* [ 3: 0], w1c, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } keycode_clr; + + /* 0x1C : keycode_value */ + union { + struct + { + uint32_t keycode0 : 8; /* [ 7: 0], r, 0xff */ + uint32_t keycode1 : 8; /* [15: 8], r, 0xff */ + uint32_t keycode2 : 8; /* [23:16], r, 0xff */ + uint32_t keycode3 : 8; /* [31:24], r, 0xff */ + } BF; + uint32_t WORD; + } keycode_value; +}; + +typedef volatile struct kys_reg kys_reg_t; + +#endif /* __KYS_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/l1c_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/l1c_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..f9ae45eddb2dfbff9f1f05da4fae9cc5755909d9 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/l1c_reg.h @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file l1c_reg.h + * @version V1.2 + * @date 2020-07-08 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __L1C_REG_H__ +#define __L1C_REG_H__ + +#include "bl702.h" + +/* 0x0 : l1c_config */ +#define L1C_CONFIG_OFFSET (0x0) +#define L1C_CACHEABLE L1C_CACHEABLE +#define L1C_CACHEABLE_POS (0U) +#define L1C_CACHEABLE_LEN (1U) +#define L1C_CACHEABLE_MSK (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS) +#define L1C_CACHEABLE_UMSK (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)) +#define L1C_CNT_EN L1C_CNT_EN +#define L1C_CNT_EN_POS (1U) +#define L1C_CNT_EN_LEN (1U) +#define L1C_CNT_EN_MSK (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS) +#define L1C_CNT_EN_UMSK (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)) +#define L1C_INVALID_EN L1C_INVALID_EN +#define L1C_INVALID_EN_POS (2U) +#define L1C_INVALID_EN_LEN (1U) +#define L1C_INVALID_EN_MSK (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS) +#define L1C_INVALID_EN_UMSK (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)) +#define L1C_INVALID_DONE L1C_INVALID_DONE +#define L1C_INVALID_DONE_POS (3U) +#define L1C_INVALID_DONE_LEN (1U) +#define L1C_INVALID_DONE_MSK (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS) +#define L1C_INVALID_DONE_UMSK (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)) +#define L1C_WT_EN L1C_WT_EN +#define L1C_WT_EN_POS (4U) +#define L1C_WT_EN_LEN (1U) +#define L1C_WT_EN_MSK (((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS) +#define L1C_WT_EN_UMSK (~(((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS)) +#define L1C_WB_EN L1C_WB_EN +#define L1C_WB_EN_POS (5U) +#define L1C_WB_EN_LEN (1U) +#define L1C_WB_EN_MSK (((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS) +#define L1C_WB_EN_UMSK (~(((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS)) +#define L1C_WA_EN L1C_WA_EN +#define L1C_WA_EN_POS (6U) +#define L1C_WA_EN_LEN (1U) +#define L1C_WA_EN_MSK (((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS) +#define L1C_WA_EN_UMSK (~(((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS)) +#define L1C_RANDOM_REPLACE L1C_RANDOM_REPLACE +#define L1C_RANDOM_REPLACE_POS (7U) +#define L1C_RANDOM_REPLACE_LEN (1U) +#define L1C_RANDOM_REPLACE_MSK (((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS) +#define L1C_RANDOM_REPLACE_UMSK (~(((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS)) +#define L1C_WAY_DIS L1C_WAY_DIS +#define L1C_WAY_DIS_POS (8U) +#define L1C_WAY_DIS_LEN (4U) +#define L1C_WAY_DIS_MSK (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS) +#define L1C_WAY_DIS_UMSK (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)) +#define L1C_IROM_2T_ACCESS L1C_IROM_2T_ACCESS +#define L1C_IROM_2T_ACCESS_POS (12U) +#define L1C_IROM_2T_ACCESS_LEN (1U) +#define L1C_IROM_2T_ACCESS_MSK (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS) +#define L1C_IROM_2T_ACCESS_UMSK (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)) +#define L1C_BYPASS L1C_BYPASS +#define L1C_BYPASS_POS (14U) +#define L1C_BYPASS_LEN (1U) +#define L1C_BYPASS_MSK (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS) +#define L1C_BYPASS_UMSK (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)) +#define L1C_BMX_ERR_EN L1C_BMX_ERR_EN +#define L1C_BMX_ERR_EN_POS (15U) +#define L1C_BMX_ERR_EN_LEN (1U) +#define L1C_BMX_ERR_EN_MSK (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS) +#define L1C_BMX_ERR_EN_UMSK (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)) +#define L1C_BMX_ARB_MODE L1C_BMX_ARB_MODE +#define L1C_BMX_ARB_MODE_POS (16U) +#define L1C_BMX_ARB_MODE_LEN (2U) +#define L1C_BMX_ARB_MODE_MSK (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS) +#define L1C_BMX_ARB_MODE_UMSK (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)) +#define L1C_BMX_TIMEOUT_EN L1C_BMX_TIMEOUT_EN +#define L1C_BMX_TIMEOUT_EN_POS (20U) +#define L1C_BMX_TIMEOUT_EN_LEN (4U) +#define L1C_BMX_TIMEOUT_EN_MSK (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS) +#define L1C_BMX_TIMEOUT_EN_UMSK (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)) +#define L1C_BMX_BUSY_OPTION_DIS L1C_BMX_BUSY_OPTION_DIS +#define L1C_BMX_BUSY_OPTION_DIS_POS (24U) +#define L1C_BMX_BUSY_OPTION_DIS_LEN (1U) +#define L1C_BMX_BUSY_OPTION_DIS_MSK (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS) +#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)) +#define L1C_EARLY_RESP_DIS L1C_EARLY_RESP_DIS +#define L1C_EARLY_RESP_DIS_POS (25U) +#define L1C_EARLY_RESP_DIS_LEN (1U) +#define L1C_EARLY_RESP_DIS_MSK (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS) +#define L1C_EARLY_RESP_DIS_UMSK (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)) +#define L1C_WRAP_DIS L1C_WRAP_DIS +#define L1C_WRAP_DIS_POS (26U) +#define L1C_WRAP_DIS_LEN (1U) +#define L1C_WRAP_DIS_MSK (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS) +#define L1C_WRAP_DIS_UMSK (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)) +#define L1C_FLUSH_EN L1C_FLUSH_EN +#define L1C_FLUSH_EN_POS (28U) +#define L1C_FLUSH_EN_LEN (1U) +#define L1C_FLUSH_EN_MSK (((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS) +#define L1C_FLUSH_EN_UMSK (~(((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS)) +#define L1C_FLUSH_DONE L1C_FLUSH_DONE +#define L1C_FLUSH_DONE_POS (29U) +#define L1C_FLUSH_DONE_LEN (1U) +#define L1C_FLUSH_DONE_MSK (((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS) +#define L1C_FLUSH_DONE_UMSK (~(((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS)) + +/* 0x4 : hit_cnt_lsb */ +#define L1C_HIT_CNT_LSB_OFFSET (0x4) +#define L1C_HIT_CNT_LSB L1C_HIT_CNT_LSB +#define L1C_HIT_CNT_LSB_POS (0U) +#define L1C_HIT_CNT_LSB_LEN (32U) +#define L1C_HIT_CNT_LSB_MSK (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS) +#define L1C_HIT_CNT_LSB_UMSK (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)) + +/* 0x8 : hit_cnt_msb */ +#define L1C_HIT_CNT_MSB_OFFSET (0x8) +#define L1C_HIT_CNT_MSB L1C_HIT_CNT_MSB +#define L1C_HIT_CNT_MSB_POS (0U) +#define L1C_HIT_CNT_MSB_LEN (32U) +#define L1C_HIT_CNT_MSB_MSK (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS) +#define L1C_HIT_CNT_MSB_UMSK (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)) + +/* 0xC : miss_cnt */ +#define L1C_MISS_CNT_OFFSET (0xC) +#define L1C_MISS_CNT L1C_MISS_CNT +#define L1C_MISS_CNT_POS (0U) +#define L1C_MISS_CNT_LEN (32U) +#define L1C_MISS_CNT_MSK (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS) +#define L1C_MISS_CNT_UMSK (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)) + +/* 0x10 : l1c_misc */ +#define L1C_MISC_OFFSET (0x10) +#define L1C_FSM L1C_FSM +#define L1C_FSM_POS (28U) +#define L1C_FSM_LEN (3U) +#define L1C_FSM_MSK (((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS) +#define L1C_FSM_UMSK (~(((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS)) + +/* 0x200 : l1c_bmx_err_addr_en */ +#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200) +#define L1C_BMX_ERR_ADDR_DIS L1C_BMX_ERR_ADDR_DIS +#define L1C_BMX_ERR_ADDR_DIS_POS (0U) +#define L1C_BMX_ERR_ADDR_DIS_LEN (1U) +#define L1C_BMX_ERR_ADDR_DIS_MSK (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS) +#define L1C_BMX_ERR_ADDR_DIS_UMSK (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)) +#define L1C_BMX_ERR_DEC L1C_BMX_ERR_DEC +#define L1C_BMX_ERR_DEC_POS (4U) +#define L1C_BMX_ERR_DEC_LEN (1U) +#define L1C_BMX_ERR_DEC_MSK (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS) +#define L1C_BMX_ERR_DEC_UMSK (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)) +#define L1C_BMX_ERR_TZ L1C_BMX_ERR_TZ +#define L1C_BMX_ERR_TZ_POS (5U) +#define L1C_BMX_ERR_TZ_LEN (1U) +#define L1C_BMX_ERR_TZ_MSK (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS) +#define L1C_BMX_ERR_TZ_UMSK (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)) +#define L1C_HSEL_OPTION L1C_HSEL_OPTION +#define L1C_HSEL_OPTION_POS (16U) +#define L1C_HSEL_OPTION_LEN (4U) +#define L1C_HSEL_OPTION_MSK (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS) +#define L1C_HSEL_OPTION_UMSK (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)) + +/* 0x204 : l1c_bmx_err_addr */ +#define L1C_BMX_ERR_ADDR_OFFSET (0x204) +#define L1C_BMX_ERR_ADDR L1C_BMX_ERR_ADDR +#define L1C_BMX_ERR_ADDR_POS (0U) +#define L1C_BMX_ERR_ADDR_LEN (32U) +#define L1C_BMX_ERR_ADDR_MSK (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS) +#define L1C_BMX_ERR_ADDR_UMSK (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)) + +/* 0x208 : irom1_misr_dataout_0 */ +#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208) +#define L1C_IROM1_MISR_DATAOUT_0 L1C_IROM1_MISR_DATAOUT_0 +#define L1C_IROM1_MISR_DATAOUT_0_POS (0U) +#define L1C_IROM1_MISR_DATAOUT_0_LEN (32U) +#define L1C_IROM1_MISR_DATAOUT_0_MSK (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS) +#define L1C_IROM1_MISR_DATAOUT_0_UMSK (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)) + +/* 0x20C : irom1_misr_dataout_1 */ +#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C) +#define L1C_IROM1_MISR_DATAOUT_1 L1C_IROM1_MISR_DATAOUT_1 +#define L1C_IROM1_MISR_DATAOUT_1_POS (0U) +#define L1C_IROM1_MISR_DATAOUT_1_LEN (32U) +#define L1C_IROM1_MISR_DATAOUT_1_MSK (((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS) +#define L1C_IROM1_MISR_DATAOUT_1_UMSK (~(((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS)) + +/* 0x210 : cpu_clk_gate */ +#define L1C_CPU_CLK_GATE_OFFSET (0x210) +#define L1C_FORCE_E21_CLOCK_ON_0 L1C_FORCE_E21_CLOCK_ON_0 +#define L1C_FORCE_E21_CLOCK_ON_0_POS (0U) +#define L1C_FORCE_E21_CLOCK_ON_0_LEN (1U) +#define L1C_FORCE_E21_CLOCK_ON_0_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS) +#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)) +#define L1C_FORCE_E21_CLOCK_ON_1 L1C_FORCE_E21_CLOCK_ON_1 +#define L1C_FORCE_E21_CLOCK_ON_1_POS (1U) +#define L1C_FORCE_E21_CLOCK_ON_1_LEN (1U) +#define L1C_FORCE_E21_CLOCK_ON_1_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS) +#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)) +#define L1C_FORCE_E21_CLOCK_ON_2 L1C_FORCE_E21_CLOCK_ON_2 +#define L1C_FORCE_E21_CLOCK_ON_2_POS (2U) +#define L1C_FORCE_E21_CLOCK_ON_2_LEN (1U) +#define L1C_FORCE_E21_CLOCK_ON_2_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS) +#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)) + +struct l1c_reg { + /* 0x0 : l1c_config */ + union { + struct + { + uint32_t l1c_cacheable : 1; /* [ 0], r/w, 0x0 */ + uint32_t l1c_cnt_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t l1c_invalid_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t l1c_invalid_done : 1; /* [ 3], r, 0x0 */ + uint32_t l1c_wt_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t l1c_wb_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t l1c_wa_en : 1; /* [ 6], r/w, 0x1 */ + uint32_t l1c_random_replace : 1; /* [ 7], r/w, 0x0 */ + uint32_t l1c_way_dis : 4; /* [11: 8], r/w, 0xf */ + uint32_t irom_2t_access : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */ + uint32_t l1c_bypass : 1; /* [ 14], r/w, 0x0 */ + uint32_t l1c_bmx_err_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t l1c_bmx_arb_mode : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */ + uint32_t l1c_bmx_timeout_en : 4; /* [23:20], r/w, 0x0 */ + uint32_t l1c_bmx_busy_option_dis : 1; /* [ 24], r/w, 0x0 */ + uint32_t early_resp_dis : 1; /* [ 25], r/w, 0x1 */ + uint32_t wrap_dis : 1; /* [ 26], r/w, 0x1 */ + uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */ + uint32_t l1c_flush_en : 1; /* [ 28], r/w, 0x0 */ + uint32_t l1c_flush_done : 1; /* [ 29], r, 0x0 */ + uint32_t reserved_31_30 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } l1c_config; + + /* 0x4 : hit_cnt_lsb */ + union { + struct + { + uint32_t hit_cnt_lsb : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } hit_cnt_lsb; + + /* 0x8 : hit_cnt_msb */ + union { + struct + { + uint32_t hit_cnt_msb : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } hit_cnt_msb; + + /* 0xC : miss_cnt */ + union { + struct + { + uint32_t miss_cnt : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } miss_cnt; + + /* 0x10 : l1c_misc */ + union { + struct + { + uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ + uint32_t l1c_fsm : 3; /* [30:28], r, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } l1c_misc; + + /* 0x14 reserved */ + uint8_t RESERVED0x14[492]; + + /* 0x200 : l1c_bmx_err_addr_en */ + union { + struct + { + uint32_t l1c_bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t l1c_bmx_err_dec : 1; /* [ 4], r, 0x0 */ + uint32_t l1c_bmx_err_tz : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t l1c_hsel_option : 4; /* [19:16], r/w, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } l1c_bmx_err_addr_en; + + /* 0x204 : l1c_bmx_err_addr */ + union { + struct + { + uint32_t l1c_bmx_err_addr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } l1c_bmx_err_addr; + + /* 0x208 : irom1_misr_dataout_0 */ + union { + struct + { + uint32_t irom1_misr_dataout_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } irom1_misr_dataout_0; + + /* 0x20C : irom1_misr_dataout_1 */ + union { + struct + { + uint32_t irom1_misr_dataout_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } irom1_misr_dataout_1; + + /* 0x210 : cpu_clk_gate */ + union { + struct + { + uint32_t force_e21_clock_on_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t force_e21_clock_on_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t force_e21_clock_on_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cpu_clk_gate; +}; + +typedef volatile struct l1c_reg l1c_reg_t; + +#endif /* __L1C_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/mjpeg_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/mjpeg_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..078deba0591d4a586c24c04e662f58d89236f979 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/mjpeg_reg.h @@ -0,0 +1,1726 @@ +/** + ****************************************************************************** + * @file mjpeg_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __MJPEG_REG_H__ +#define __MJPEG_REG_H__ + +#include "bl702.h" + +/* 0x0 : mjpeg_control_1 */ +#define MJPEG_CONTROL_1_OFFSET (0x0) +#define MJPEG_REG_MJPEG_ENABLE MJPEG_REG_MJPEG_ENABLE +#define MJPEG_REG_MJPEG_ENABLE_POS (0U) +#define MJPEG_REG_MJPEG_ENABLE_LEN (1U) +#define MJPEG_REG_MJPEG_ENABLE_MSK (((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS) +#define MJPEG_REG_MJPEG_ENABLE_UMSK (~(((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS)) +#define MJPEG_REG_MJPEG_BIT_ORDER MJPEG_REG_MJPEG_BIT_ORDER +#define MJPEG_REG_MJPEG_BIT_ORDER_POS (1U) +#define MJPEG_REG_MJPEG_BIT_ORDER_LEN (1U) +#define MJPEG_REG_MJPEG_BIT_ORDER_MSK (((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS) +#define MJPEG_REG_MJPEG_BIT_ORDER_UMSK (~(((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS)) +#define MJPEG_REG_ORDER_U_EVEN MJPEG_REG_ORDER_U_EVEN +#define MJPEG_REG_ORDER_U_EVEN_POS (2U) +#define MJPEG_REG_ORDER_U_EVEN_LEN (1U) +#define MJPEG_REG_ORDER_U_EVEN_MSK (((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS) +#define MJPEG_REG_ORDER_U_EVEN_UMSK (~(((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS)) +#define MJPEG_REG_WR_OVER_STOP MJPEG_REG_WR_OVER_STOP +#define MJPEG_REG_WR_OVER_STOP_POS (3U) +#define MJPEG_REG_WR_OVER_STOP_LEN (1U) +#define MJPEG_REG_WR_OVER_STOP_MSK (((1U << MJPEG_REG_WR_OVER_STOP_LEN) - 1) << MJPEG_REG_WR_OVER_STOP_POS) +#define MJPEG_REG_WR_OVER_STOP_UMSK (~(((1U << MJPEG_REG_WR_OVER_STOP_LEN) - 1) << MJPEG_REG_WR_OVER_STOP_POS)) +#define MJPEG_REG_LAST_HF_WBLK_DMY MJPEG_REG_LAST_HF_WBLK_DMY +#define MJPEG_REG_LAST_HF_WBLK_DMY_POS (4U) +#define MJPEG_REG_LAST_HF_WBLK_DMY_LEN (1U) +#define MJPEG_REG_LAST_HF_WBLK_DMY_MSK (((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS) +#define MJPEG_REG_LAST_HF_WBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS)) +#define MJPEG_REG_LAST_HF_HBLK_DMY MJPEG_REG_LAST_HF_HBLK_DMY +#define MJPEG_REG_LAST_HF_HBLK_DMY_POS (5U) +#define MJPEG_REG_LAST_HF_HBLK_DMY_LEN (1U) +#define MJPEG_REG_LAST_HF_HBLK_DMY_MSK (((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS) +#define MJPEG_REG_LAST_HF_HBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS)) +#define MJPEG_REG_REFLECT_DMY MJPEG_REG_REFLECT_DMY +#define MJPEG_REG_REFLECT_DMY_POS (6U) +#define MJPEG_REG_REFLECT_DMY_LEN (1U) +#define MJPEG_REG_REFLECT_DMY_MSK (((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS) +#define MJPEG_REG_REFLECT_DMY_UMSK (~(((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS)) +#define MJPEG_REG_H_BUST MJPEG_REG_H_BUST +#define MJPEG_REG_H_BUST_POS (8U) +#define MJPEG_REG_H_BUST_LEN (2U) +#define MJPEG_REG_H_BUST_MSK (((1U << MJPEG_REG_H_BUST_LEN) - 1) << MJPEG_REG_H_BUST_POS) +#define MJPEG_REG_H_BUST_UMSK (~(((1U << MJPEG_REG_H_BUST_LEN) - 1) << MJPEG_REG_H_BUST_POS)) +#define MJPEG_REG_YUV_MODE MJPEG_REG_YUV_MODE +#define MJPEG_REG_YUV_MODE_POS (12U) +#define MJPEG_REG_YUV_MODE_LEN (2U) +#define MJPEG_REG_YUV_MODE_MSK (((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS) +#define MJPEG_REG_YUV_MODE_UMSK (~(((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS)) +#define MJPEG_REG_Q_MODE MJPEG_REG_Q_MODE +#define MJPEG_REG_Q_MODE_POS (16U) +#define MJPEG_REG_Q_MODE_LEN (7U) +#define MJPEG_REG_Q_MODE_MSK (((1U << MJPEG_REG_Q_MODE_LEN) - 1) << MJPEG_REG_Q_MODE_POS) +#define MJPEG_REG_Q_MODE_UMSK (~(((1U << MJPEG_REG_Q_MODE_LEN) - 1) << MJPEG_REG_Q_MODE_POS)) +#define MJPEG_REG_Y0_ORDER MJPEG_REG_Y0_ORDER +#define MJPEG_REG_Y0_ORDER_POS (24U) +#define MJPEG_REG_Y0_ORDER_LEN (2U) +#define MJPEG_REG_Y0_ORDER_MSK (((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS) +#define MJPEG_REG_Y0_ORDER_UMSK (~(((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS)) +#define MJPEG_REG_U0_ORDER MJPEG_REG_U0_ORDER +#define MJPEG_REG_U0_ORDER_POS (26U) +#define MJPEG_REG_U0_ORDER_LEN (2U) +#define MJPEG_REG_U0_ORDER_MSK (((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS) +#define MJPEG_REG_U0_ORDER_UMSK (~(((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS)) +#define MJPEG_REG_Y1_ORDER MJPEG_REG_Y1_ORDER +#define MJPEG_REG_Y1_ORDER_POS (28U) +#define MJPEG_REG_Y1_ORDER_LEN (2U) +#define MJPEG_REG_Y1_ORDER_MSK (((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS) +#define MJPEG_REG_Y1_ORDER_UMSK (~(((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS)) +#define MJPEG_REG_V0_ORDER MJPEG_REG_V0_ORDER +#define MJPEG_REG_V0_ORDER_POS (30U) +#define MJPEG_REG_V0_ORDER_LEN (2U) +#define MJPEG_REG_V0_ORDER_MSK (((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS) +#define MJPEG_REG_V0_ORDER_UMSK (~(((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS)) + +/* 0x4 : mjpeg_control_2 */ +#define MJPEG_CONTROL_2_OFFSET (0x4) +#define MJPEG_REG_SW_FRAME MJPEG_REG_SW_FRAME +#define MJPEG_REG_SW_FRAME_POS (0U) +#define MJPEG_REG_SW_FRAME_LEN (5U) +#define MJPEG_REG_SW_FRAME_MSK (((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS) +#define MJPEG_REG_SW_FRAME_UMSK (~(((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS)) +#define MJPEG_REG_MJPEG_SW_MODE MJPEG_REG_MJPEG_SW_MODE +#define MJPEG_REG_MJPEG_SW_MODE_POS (8U) +#define MJPEG_REG_MJPEG_SW_MODE_LEN (1U) +#define MJPEG_REG_MJPEG_SW_MODE_MSK (((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS) +#define MJPEG_REG_MJPEG_SW_MODE_UMSK (~(((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS)) +#define MJPEG_REG_MJPEG_SW_RUN MJPEG_REG_MJPEG_SW_RUN +#define MJPEG_REG_MJPEG_SW_RUN_POS (9U) +#define MJPEG_REG_MJPEG_SW_RUN_LEN (1U) +#define MJPEG_REG_MJPEG_SW_RUN_MSK (((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS) +#define MJPEG_REG_MJPEG_SW_RUN_UMSK (~(((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS)) +#define MJPEG_REG_YY_DVP2AHB_LSEL MJPEG_REG_YY_DVP2AHB_LSEL +#define MJPEG_REG_YY_DVP2AHB_LSEL_POS (12U) +#define MJPEG_REG_YY_DVP2AHB_LSEL_LEN (1U) +#define MJPEG_REG_YY_DVP2AHB_LSEL_MSK (((1U << MJPEG_REG_YY_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_LSEL_POS) +#define MJPEG_REG_YY_DVP2AHB_LSEL_UMSK (~(((1U << MJPEG_REG_YY_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_LSEL_POS)) +#define MJPEG_REG_YY_DVP2AHB_FSEL MJPEG_REG_YY_DVP2AHB_FSEL +#define MJPEG_REG_YY_DVP2AHB_FSEL_POS (13U) +#define MJPEG_REG_YY_DVP2AHB_FSEL_LEN (1U) +#define MJPEG_REG_YY_DVP2AHB_FSEL_MSK (((1U << MJPEG_REG_YY_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_FSEL_POS) +#define MJPEG_REG_YY_DVP2AHB_FSEL_UMSK (~(((1U << MJPEG_REG_YY_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_FSEL_POS)) +#define MJPEG_REG_UV_DVP2AHB_LSEL MJPEG_REG_UV_DVP2AHB_LSEL +#define MJPEG_REG_UV_DVP2AHB_LSEL_POS (14U) +#define MJPEG_REG_UV_DVP2AHB_LSEL_LEN (1U) +#define MJPEG_REG_UV_DVP2AHB_LSEL_MSK (((1U << MJPEG_REG_UV_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_LSEL_POS) +#define MJPEG_REG_UV_DVP2AHB_LSEL_UMSK (~(((1U << MJPEG_REG_UV_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_LSEL_POS)) +#define MJPEG_REG_UV_DVP2AHB_FSEL MJPEG_REG_UV_DVP2AHB_FSEL +#define MJPEG_REG_UV_DVP2AHB_FSEL_POS (15U) +#define MJPEG_REG_UV_DVP2AHB_FSEL_LEN (1U) +#define MJPEG_REG_UV_DVP2AHB_FSEL_MSK (((1U << MJPEG_REG_UV_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_FSEL_POS) +#define MJPEG_REG_UV_DVP2AHB_FSEL_UMSK (~(((1U << MJPEG_REG_UV_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_FSEL_POS)) +#define MJPEG_REG_MJPEG_WAIT_CYCLE MJPEG_REG_MJPEG_WAIT_CYCLE +#define MJPEG_REG_MJPEG_WAIT_CYCLE_POS (16U) +#define MJPEG_REG_MJPEG_WAIT_CYCLE_LEN (16U) +#define MJPEG_REG_MJPEG_WAIT_CYCLE_MSK (((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS) +#define MJPEG_REG_MJPEG_WAIT_CYCLE_UMSK (~(((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS)) + +/* 0x08 : mjpeg_yy_frame_addr */ +#define MJPEG_YY_FRAME_ADDR_OFFSET (0x08) +#define MJPEG_REG_YY_ADDR_START MJPEG_REG_YY_ADDR_START +#define MJPEG_REG_YY_ADDR_START_POS (0U) +#define MJPEG_REG_YY_ADDR_START_LEN (32U) +#define MJPEG_REG_YY_ADDR_START_MSK (((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS) +#define MJPEG_REG_YY_ADDR_START_UMSK (~(((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS)) + +/* 0x0C : mjpeg_uv_frame_addr */ +#define MJPEG_UV_FRAME_ADDR_OFFSET (0x0C) +#define MJPEG_REG_UV_ADDR_START MJPEG_REG_UV_ADDR_START +#define MJPEG_REG_UV_ADDR_START_POS (0U) +#define MJPEG_REG_UV_ADDR_START_LEN (32U) +#define MJPEG_REG_UV_ADDR_START_MSK (((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS) +#define MJPEG_REG_UV_ADDR_START_UMSK (~(((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS)) + +/* 0x10 : mjpeg_yuv_mem */ +#define MJPEG_YUV_MEM_OFFSET (0x10) +#define MJPEG_REG_YY_MEM_HBLK MJPEG_REG_YY_MEM_HBLK +#define MJPEG_REG_YY_MEM_HBLK_POS (0U) +#define MJPEG_REG_YY_MEM_HBLK_LEN (13U) +#define MJPEG_REG_YY_MEM_HBLK_MSK (((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS) +#define MJPEG_REG_YY_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS)) +#define MJPEG_REG_UV_MEM_HBLK MJPEG_REG_UV_MEM_HBLK +#define MJPEG_REG_UV_MEM_HBLK_POS (16U) +#define MJPEG_REG_UV_MEM_HBLK_LEN (13U) +#define MJPEG_REG_UV_MEM_HBLK_MSK (((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS) +#define MJPEG_REG_UV_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS)) + +/* 0x14 : jpeg_frame_addr */ +#define MJPEG_JPEG_FRAME_ADDR_OFFSET (0x14) +#define MJPEG_REG_W_ADDR_START MJPEG_REG_W_ADDR_START +#define MJPEG_REG_W_ADDR_START_POS (0U) +#define MJPEG_REG_W_ADDR_START_LEN (32U) +#define MJPEG_REG_W_ADDR_START_MSK (((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS) +#define MJPEG_REG_W_ADDR_START_UMSK (~(((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS)) + +/* 0x18 : jpeg_store_memory */ +#define MJPEG_JPEG_STORE_MEMORY_OFFSET (0x18) +#define MJPEG_REG_W_BURST_CNT MJPEG_REG_W_BURST_CNT +#define MJPEG_REG_W_BURST_CNT_POS (0U) +#define MJPEG_REG_W_BURST_CNT_LEN (32U) +#define MJPEG_REG_W_BURST_CNT_MSK (((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS) +#define MJPEG_REG_W_BURST_CNT_UMSK (~(((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS)) + +/* 0x1C : mjpeg_control_3 */ +#define MJPEG_CONTROL_3_OFFSET (0x1C) +#define MJPEG_REG_INT_NORMAL_EN MJPEG_REG_INT_NORMAL_EN +#define MJPEG_REG_INT_NORMAL_EN_POS (0U) +#define MJPEG_REG_INT_NORMAL_EN_LEN (1U) +#define MJPEG_REG_INT_NORMAL_EN_MSK (((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS) +#define MJPEG_REG_INT_NORMAL_EN_UMSK (~(((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS)) +#define MJPEG_REG_INT_CAM_EN MJPEG_REG_INT_CAM_EN +#define MJPEG_REG_INT_CAM_EN_POS (1U) +#define MJPEG_REG_INT_CAM_EN_LEN (1U) +#define MJPEG_REG_INT_CAM_EN_MSK (((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS) +#define MJPEG_REG_INT_CAM_EN_UMSK (~(((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS)) +#define MJPEG_REG_INT_MEM_EN MJPEG_REG_INT_MEM_EN +#define MJPEG_REG_INT_MEM_EN_POS (2U) +#define MJPEG_REG_INT_MEM_EN_LEN (1U) +#define MJPEG_REG_INT_MEM_EN_MSK (((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS) +#define MJPEG_REG_INT_MEM_EN_UMSK (~(((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS)) +#define MJPEG_REG_INT_FRAME_EN MJPEG_REG_INT_FRAME_EN +#define MJPEG_REG_INT_FRAME_EN_POS (3U) +#define MJPEG_REG_INT_FRAME_EN_LEN (1U) +#define MJPEG_REG_INT_FRAME_EN_MSK (((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS) +#define MJPEG_REG_INT_FRAME_EN_UMSK (~(((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS)) +#define MJPEG_STS_NORMAL_INT MJPEG_STS_NORMAL_INT +#define MJPEG_STS_NORMAL_INT_POS (4U) +#define MJPEG_STS_NORMAL_INT_LEN (1U) +#define MJPEG_STS_NORMAL_INT_MSK (((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS) +#define MJPEG_STS_NORMAL_INT_UMSK (~(((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS)) +#define MJPEG_STS_CAM_INT MJPEG_STS_CAM_INT +#define MJPEG_STS_CAM_INT_POS (5U) +#define MJPEG_STS_CAM_INT_LEN (1U) +#define MJPEG_STS_CAM_INT_MSK (((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS) +#define MJPEG_STS_CAM_INT_UMSK (~(((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS)) +#define MJPEG_STS_MEM_INT MJPEG_STS_MEM_INT +#define MJPEG_STS_MEM_INT_POS (6U) +#define MJPEG_STS_MEM_INT_LEN (1U) +#define MJPEG_STS_MEM_INT_MSK (((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS) +#define MJPEG_STS_MEM_INT_UMSK (~(((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS)) +#define MJPEG_STS_FRAME_INT MJPEG_STS_FRAME_INT +#define MJPEG_STS_FRAME_INT_POS (7U) +#define MJPEG_STS_FRAME_INT_LEN (1U) +#define MJPEG_STS_FRAME_INT_MSK (((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS) +#define MJPEG_STS_FRAME_INT_UMSK (~(((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS)) +#define MJPEG_IDLE MJPEG_IDLE +#define MJPEG_IDLE_POS (8U) +#define MJPEG_IDLE_LEN (1U) +#define MJPEG_IDLE_MSK (((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS) +#define MJPEG_IDLE_UMSK (~(((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS)) +#define MJPEG_FUNC MJPEG_FUNC +#define MJPEG_FUNC_POS (9U) +#define MJPEG_FUNC_LEN (1U) +#define MJPEG_FUNC_MSK (((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS) +#define MJPEG_FUNC_UMSK (~(((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS)) +#define MJPEG_WAIT MJPEG_WAIT +#define MJPEG_WAIT_POS (10U) +#define MJPEG_WAIT_LEN (1U) +#define MJPEG_WAIT_MSK (((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS) +#define MJPEG_WAIT_UMSK (~(((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS)) +#define MJPEG_FLSH MJPEG_FLSH +#define MJPEG_FLSH_POS (11U) +#define MJPEG_FLSH_LEN (1U) +#define MJPEG_FLSH_MSK (((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS) +#define MJPEG_FLSH_UMSK (~(((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS)) +#define MJPEG_MANS MJPEG_MANS +#define MJPEG_MANS_POS (12U) +#define MJPEG_MANS_LEN (1U) +#define MJPEG_MANS_MSK (((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS) +#define MJPEG_MANS_UMSK (~(((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS)) +#define MJPEG_MANF MJPEG_MANF +#define MJPEG_MANF_POS (13U) +#define MJPEG_MANF_LEN (1U) +#define MJPEG_MANF_MSK (((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS) +#define MJPEG_MANF_UMSK (~(((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS)) +#define MJPEG_AHB_IDLE MJPEG_AHB_IDLE +#define MJPEG_AHB_IDLE_POS (14U) +#define MJPEG_AHB_IDLE_LEN (1U) +#define MJPEG_AHB_IDLE_MSK (((1U << MJPEG_AHB_IDLE_LEN) - 1) << MJPEG_AHB_IDLE_POS) +#define MJPEG_AHB_IDLE_UMSK (~(((1U << MJPEG_AHB_IDLE_LEN) - 1) << MJPEG_AHB_IDLE_POS)) +#define MJPEG_REG_FRAME_CNT_TRGR_INT MJPEG_REG_FRAME_CNT_TRGR_INT +#define MJPEG_REG_FRAME_CNT_TRGR_INT_POS (16U) +#define MJPEG_REG_FRAME_CNT_TRGR_INT_LEN (5U) +#define MJPEG_REG_FRAME_CNT_TRGR_INT_MSK (((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS) +#define MJPEG_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS)) +#define MJPEG_REG_INT_IDLE_EN MJPEG_REG_INT_IDLE_EN +#define MJPEG_REG_INT_IDLE_EN_POS (21U) +#define MJPEG_REG_INT_IDLE_EN_LEN (1U) +#define MJPEG_REG_INT_IDLE_EN_MSK (((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS) +#define MJPEG_REG_INT_IDLE_EN_UMSK (~(((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS)) +#define MJPEG_STS_IDLE_INT MJPEG_STS_IDLE_INT +#define MJPEG_STS_IDLE_INT_POS (22U) +#define MJPEG_STS_IDLE_INT_LEN (1U) +#define MJPEG_STS_IDLE_INT_MSK (((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS) +#define MJPEG_STS_IDLE_INT_UMSK (~(((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS)) +#define MJPEG_FRAME_VALID_CNT MJPEG_FRAME_VALID_CNT +#define MJPEG_FRAME_VALID_CNT_POS (24U) +#define MJPEG_FRAME_VALID_CNT_LEN (5U) +#define MJPEG_FRAME_VALID_CNT_MSK (((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS) +#define MJPEG_FRAME_VALID_CNT_UMSK (~(((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS)) +#define MJPEG_REG_INT_SWAP_EN MJPEG_REG_INT_SWAP_EN +#define MJPEG_REG_INT_SWAP_EN_POS (29U) +#define MJPEG_REG_INT_SWAP_EN_LEN (1U) +#define MJPEG_REG_INT_SWAP_EN_MSK (((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS) +#define MJPEG_REG_INT_SWAP_EN_UMSK (~(((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS)) +#define MJPEG_STS_SWAP_INT MJPEG_STS_SWAP_INT +#define MJPEG_STS_SWAP_INT_POS (30U) +#define MJPEG_STS_SWAP_INT_LEN (1U) +#define MJPEG_STS_SWAP_INT_MSK (((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS) +#define MJPEG_STS_SWAP_INT_UMSK (~(((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS)) + +/* 0x20 : mjpeg_frame_fifo_pop */ +#define MJPEG_FRAME_FIFO_POP_OFFSET (0x20) +#define MJPEG_RFIFO_POP MJPEG_RFIFO_POP +#define MJPEG_RFIFO_POP_POS (0U) +#define MJPEG_RFIFO_POP_LEN (1U) +#define MJPEG_RFIFO_POP_MSK (((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS) +#define MJPEG_RFIFO_POP_UMSK (~(((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS)) +#define MJPEG_REG_W_SWAP_CLR MJPEG_REG_W_SWAP_CLR +#define MJPEG_REG_W_SWAP_CLR_POS (1U) +#define MJPEG_REG_W_SWAP_CLR_LEN (1U) +#define MJPEG_REG_W_SWAP_CLR_MSK (((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS) +#define MJPEG_REG_W_SWAP_CLR_UMSK (~(((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS)) +#define MJPEG_REG_INT_NORMAL_CLR MJPEG_REG_INT_NORMAL_CLR +#define MJPEG_REG_INT_NORMAL_CLR_POS (8U) +#define MJPEG_REG_INT_NORMAL_CLR_LEN (1U) +#define MJPEG_REG_INT_NORMAL_CLR_MSK (((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS) +#define MJPEG_REG_INT_NORMAL_CLR_UMSK (~(((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS)) +#define MJPEG_REG_INT_CAM_CLR MJPEG_REG_INT_CAM_CLR +#define MJPEG_REG_INT_CAM_CLR_POS (9U) +#define MJPEG_REG_INT_CAM_CLR_LEN (1U) +#define MJPEG_REG_INT_CAM_CLR_MSK (((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS) +#define MJPEG_REG_INT_CAM_CLR_UMSK (~(((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS)) +#define MJPEG_REG_INT_MEM_CLR MJPEG_REG_INT_MEM_CLR +#define MJPEG_REG_INT_MEM_CLR_POS (10U) +#define MJPEG_REG_INT_MEM_CLR_LEN (1U) +#define MJPEG_REG_INT_MEM_CLR_MSK (((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS) +#define MJPEG_REG_INT_MEM_CLR_UMSK (~(((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS)) +#define MJPEG_REG_INT_FRAME_CLR MJPEG_REG_INT_FRAME_CLR +#define MJPEG_REG_INT_FRAME_CLR_POS (11U) +#define MJPEG_REG_INT_FRAME_CLR_LEN (1U) +#define MJPEG_REG_INT_FRAME_CLR_MSK (((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS) +#define MJPEG_REG_INT_FRAME_CLR_UMSK (~(((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS)) +#define MJPEG_REG_INT_IDLE_CLR MJPEG_REG_INT_IDLE_CLR +#define MJPEG_REG_INT_IDLE_CLR_POS (12U) +#define MJPEG_REG_INT_IDLE_CLR_LEN (1U) +#define MJPEG_REG_INT_IDLE_CLR_MSK (((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS) +#define MJPEG_REG_INT_IDLE_CLR_UMSK (~(((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS)) +#define MJPEG_REG_INT_SWAP_CLR MJPEG_REG_INT_SWAP_CLR +#define MJPEG_REG_INT_SWAP_CLR_POS (13U) +#define MJPEG_REG_INT_SWAP_CLR_LEN (1U) +#define MJPEG_REG_INT_SWAP_CLR_MSK (((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS) +#define MJPEG_REG_INT_SWAP_CLR_UMSK (~(((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS)) + +/* 0x24 : mjpeg_frame_size */ +#define MJPEG_FRAME_SIZE_OFFSET (0x24) +#define MJPEG_REG_FRAME_WBLK MJPEG_REG_FRAME_WBLK +#define MJPEG_REG_FRAME_WBLK_POS (0U) +#define MJPEG_REG_FRAME_WBLK_LEN (12U) +#define MJPEG_REG_FRAME_WBLK_MSK (((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS) +#define MJPEG_REG_FRAME_WBLK_UMSK (~(((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS)) +#define MJPEG_REG_FRAME_HBLK MJPEG_REG_FRAME_HBLK +#define MJPEG_REG_FRAME_HBLK_POS (16U) +#define MJPEG_REG_FRAME_HBLK_LEN (12U) +#define MJPEG_REG_FRAME_HBLK_MSK (((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS) +#define MJPEG_REG_FRAME_HBLK_UMSK (~(((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS)) + +/* 0x28 : mjpeg_header_byte */ +#define MJPEG_HEADER_BYTE_OFFSET (0x28) +#define MJPEG_REG_HEAD_BYTE MJPEG_REG_HEAD_BYTE +#define MJPEG_REG_HEAD_BYTE_POS (0U) +#define MJPEG_REG_HEAD_BYTE_LEN (12U) +#define MJPEG_REG_HEAD_BYTE_MSK (((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS) +#define MJPEG_REG_HEAD_BYTE_UMSK (~(((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS)) +#define MJPEG_REG_TAIL_EXP MJPEG_REG_TAIL_EXP +#define MJPEG_REG_TAIL_EXP_POS (16U) +#define MJPEG_REG_TAIL_EXP_LEN (1U) +#define MJPEG_REG_TAIL_EXP_MSK (((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS) +#define MJPEG_REG_TAIL_EXP_UMSK (~(((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS)) + +/* 0x30 : mjpeg_swap_mode */ +#define MJPEG_SWAP_MODE_OFFSET (0x30) +#define MJPEG_REG_W_SWAP_MODE MJPEG_REG_W_SWAP_MODE +#define MJPEG_REG_W_SWAP_MODE_POS (0U) +#define MJPEG_REG_W_SWAP_MODE_LEN (1U) +#define MJPEG_REG_W_SWAP_MODE_MSK (((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS) +#define MJPEG_REG_W_SWAP_MODE_UMSK (~(((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS)) +#define MJPEG_STS_SWAP0_FULL MJPEG_STS_SWAP0_FULL +#define MJPEG_STS_SWAP0_FULL_POS (8U) +#define MJPEG_STS_SWAP0_FULL_LEN (1U) +#define MJPEG_STS_SWAP0_FULL_MSK (((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS) +#define MJPEG_STS_SWAP0_FULL_UMSK (~(((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS)) +#define MJPEG_STS_SWAP1_FULL MJPEG_STS_SWAP1_FULL +#define MJPEG_STS_SWAP1_FULL_POS (9U) +#define MJPEG_STS_SWAP1_FULL_LEN (1U) +#define MJPEG_STS_SWAP1_FULL_MSK (((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS) +#define MJPEG_STS_SWAP1_FULL_UMSK (~(((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS)) +#define MJPEG_STS_READ_SWAP_IDX MJPEG_STS_READ_SWAP_IDX +#define MJPEG_STS_READ_SWAP_IDX_POS (10U) +#define MJPEG_STS_READ_SWAP_IDX_LEN (1U) +#define MJPEG_STS_READ_SWAP_IDX_MSK (((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS) +#define MJPEG_STS_READ_SWAP_IDX_UMSK (~(((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS)) +#define MJPEG_STS_SWAP_FSTART MJPEG_STS_SWAP_FSTART +#define MJPEG_STS_SWAP_FSTART_POS (11U) +#define MJPEG_STS_SWAP_FSTART_LEN (1U) +#define MJPEG_STS_SWAP_FSTART_MSK (((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS) +#define MJPEG_STS_SWAP_FSTART_UMSK (~(((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS)) +#define MJPEG_STS_SWAP_FEND MJPEG_STS_SWAP_FEND +#define MJPEG_STS_SWAP_FEND_POS (12U) +#define MJPEG_STS_SWAP_FEND_LEN (1U) +#define MJPEG_STS_SWAP_FEND_MSK (((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS) +#define MJPEG_STS_SWAP_FEND_UMSK (~(((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS)) + +/* 0x34 : mjpeg_swap_bit_cnt */ +#define MJPEG_SWAP_BIT_CNT_OFFSET (0x34) +#define MJPEG_FRAME_SWAP_END_BIT_CNT MJPEG_FRAME_SWAP_END_BIT_CNT +#define MJPEG_FRAME_SWAP_END_BIT_CNT_POS (0U) +#define MJPEG_FRAME_SWAP_END_BIT_CNT_LEN (32U) +#define MJPEG_FRAME_SWAP_END_BIT_CNT_MSK (((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS) +#define MJPEG_FRAME_SWAP_END_BIT_CNT_UMSK (~(((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS)) + +/* 0x38 : mjpeg_paket_ctrl */ +#define MJPEG_PAKET_CTRL_OFFSET (0x38) +#define MJPEG_REG_PKET_EN MJPEG_REG_PKET_EN +#define MJPEG_REG_PKET_EN_POS (0U) +#define MJPEG_REG_PKET_EN_LEN (1U) +#define MJPEG_REG_PKET_EN_MSK (((1U << MJPEG_REG_PKET_EN_LEN) - 1) << MJPEG_REG_PKET_EN_POS) +#define MJPEG_REG_PKET_EN_UMSK (~(((1U << MJPEG_REG_PKET_EN_LEN) - 1) << MJPEG_REG_PKET_EN_POS)) +#define MJPEG_REG_JEND_TO_PEND MJPEG_REG_JEND_TO_PEND +#define MJPEG_REG_JEND_TO_PEND_POS (1U) +#define MJPEG_REG_JEND_TO_PEND_LEN (1U) +#define MJPEG_REG_JEND_TO_PEND_MSK (((1U << MJPEG_REG_JEND_TO_PEND_LEN) - 1) << MJPEG_REG_JEND_TO_PEND_POS) +#define MJPEG_REG_JEND_TO_PEND_UMSK (~(((1U << MJPEG_REG_JEND_TO_PEND_LEN) - 1) << MJPEG_REG_JEND_TO_PEND_POS)) +#define MJPEG_REG_PKET_BODY_BYTE MJPEG_REG_PKET_BODY_BYTE +#define MJPEG_REG_PKET_BODY_BYTE_POS (16U) +#define MJPEG_REG_PKET_BODY_BYTE_LEN (16U) +#define MJPEG_REG_PKET_BODY_BYTE_MSK (((1U << MJPEG_REG_PKET_BODY_BYTE_LEN) - 1) << MJPEG_REG_PKET_BODY_BYTE_POS) +#define MJPEG_REG_PKET_BODY_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_BODY_BYTE_LEN) - 1) << MJPEG_REG_PKET_BODY_BYTE_POS)) + +/* 0x3C : mjpeg_paket_head_tail */ +#define MJPEG_PAKET_HEAD_TAIL_OFFSET (0x3C) +#define MJPEG_REG_PKET_HEAD_BYTE MJPEG_REG_PKET_HEAD_BYTE +#define MJPEG_REG_PKET_HEAD_BYTE_POS (0U) +#define MJPEG_REG_PKET_HEAD_BYTE_LEN (12U) +#define MJPEG_REG_PKET_HEAD_BYTE_MSK (((1U << MJPEG_REG_PKET_HEAD_BYTE_LEN) - 1) << MJPEG_REG_PKET_HEAD_BYTE_POS) +#define MJPEG_REG_PKET_HEAD_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_HEAD_BYTE_LEN) - 1) << MJPEG_REG_PKET_HEAD_BYTE_POS)) +#define MJPEG_REG_PKET_TAIL_BYTE MJPEG_REG_PKET_TAIL_BYTE +#define MJPEG_REG_PKET_TAIL_BYTE_POS (16U) +#define MJPEG_REG_PKET_TAIL_BYTE_LEN (12U) +#define MJPEG_REG_PKET_TAIL_BYTE_MSK (((1U << MJPEG_REG_PKET_TAIL_BYTE_LEN) - 1) << MJPEG_REG_PKET_TAIL_BYTE_POS) +#define MJPEG_REG_PKET_TAIL_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_TAIL_BYTE_LEN) - 1) << MJPEG_REG_PKET_TAIL_BYTE_POS)) + +/* 0x40 : mjpeg_Y_frame_read_status_1 */ +#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET (0x40) +#define MJPEG_YY_MEM_HBLK_R MJPEG_YY_MEM_HBLK_R +#define MJPEG_YY_MEM_HBLK_R_POS (0U) +#define MJPEG_YY_MEM_HBLK_R_LEN (13U) +#define MJPEG_YY_MEM_HBLK_R_MSK (((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS) +#define MJPEG_YY_MEM_HBLK_R_UMSK (~(((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS)) +#define MJPEG_YY_FRM_HBLK_R MJPEG_YY_FRM_HBLK_R +#define MJPEG_YY_FRM_HBLK_R_POS (16U) +#define MJPEG_YY_FRM_HBLK_R_LEN (13U) +#define MJPEG_YY_FRM_HBLK_R_MSK (((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS) +#define MJPEG_YY_FRM_HBLK_R_UMSK (~(((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS)) + +/* 0x44 : mjpeg_Y_frame_read_status_2 */ +#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET (0x44) +#define MJPEG_YY_WBLK_R MJPEG_YY_WBLK_R +#define MJPEG_YY_WBLK_R_POS (0U) +#define MJPEG_YY_WBLK_R_LEN (13U) +#define MJPEG_YY_WBLK_R_MSK (((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS) +#define MJPEG_YY_WBLK_R_UMSK (~(((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS)) +#define MJPEG_YY_MEM_RND_R MJPEG_YY_MEM_RND_R +#define MJPEG_YY_MEM_RND_R_POS (16U) +#define MJPEG_YY_MEM_RND_R_LEN (8U) +#define MJPEG_YY_MEM_RND_R_MSK (((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS) +#define MJPEG_YY_MEM_RND_R_UMSK (~(((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS)) +#define MJPEG_YY_FRM_CNT_R MJPEG_YY_FRM_CNT_R +#define MJPEG_YY_FRM_CNT_R_POS (24U) +#define MJPEG_YY_FRM_CNT_R_LEN (8U) +#define MJPEG_YY_FRM_CNT_R_MSK (((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS) +#define MJPEG_YY_FRM_CNT_R_UMSK (~(((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS)) + +/* 0x48 : mjpeg_Y_frame_write_status */ +#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET (0x48) +#define MJPEG_YY_MEM_HBLK_W MJPEG_YY_MEM_HBLK_W +#define MJPEG_YY_MEM_HBLK_W_POS (0U) +#define MJPEG_YY_MEM_HBLK_W_LEN (13U) +#define MJPEG_YY_MEM_HBLK_W_MSK (((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS) +#define MJPEG_YY_MEM_HBLK_W_UMSK (~(((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS)) +#define MJPEG_YY_MEM_RND_W MJPEG_YY_MEM_RND_W +#define MJPEG_YY_MEM_RND_W_POS (16U) +#define MJPEG_YY_MEM_RND_W_LEN (8U) +#define MJPEG_YY_MEM_RND_W_MSK (((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS) +#define MJPEG_YY_MEM_RND_W_UMSK (~(((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS)) +#define MJPEG_YY_FRM_CNT_W MJPEG_YY_FRM_CNT_W +#define MJPEG_YY_FRM_CNT_W_POS (24U) +#define MJPEG_YY_FRM_CNT_W_LEN (8U) +#define MJPEG_YY_FRM_CNT_W_MSK (((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS) +#define MJPEG_YY_FRM_CNT_W_UMSK (~(((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS)) + +/* 0x4C : mjpeg_UV_frame_read_status_1 */ +#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET (0x4C) +#define MJPEG_UV_MEM_HBLK_R MJPEG_UV_MEM_HBLK_R +#define MJPEG_UV_MEM_HBLK_R_POS (0U) +#define MJPEG_UV_MEM_HBLK_R_LEN (13U) +#define MJPEG_UV_MEM_HBLK_R_MSK (((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS) +#define MJPEG_UV_MEM_HBLK_R_UMSK (~(((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS)) +#define MJPEG_UV_FRM_HBLK_R MJPEG_UV_FRM_HBLK_R +#define MJPEG_UV_FRM_HBLK_R_POS (16U) +#define MJPEG_UV_FRM_HBLK_R_LEN (13U) +#define MJPEG_UV_FRM_HBLK_R_MSK (((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS) +#define MJPEG_UV_FRM_HBLK_R_UMSK (~(((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS)) + +/* 0x50 : mjpeg_UV_frame_read_status_2 */ +#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET (0x50) +#define MJPEG_UV_WBLK_R MJPEG_UV_WBLK_R +#define MJPEG_UV_WBLK_R_POS (0U) +#define MJPEG_UV_WBLK_R_LEN (13U) +#define MJPEG_UV_WBLK_R_MSK (((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS) +#define MJPEG_UV_WBLK_R_UMSK (~(((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS)) +#define MJPEG_UV_MEM_RND_R MJPEG_UV_MEM_RND_R +#define MJPEG_UV_MEM_RND_R_POS (16U) +#define MJPEG_UV_MEM_RND_R_LEN (8U) +#define MJPEG_UV_MEM_RND_R_MSK (((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS) +#define MJPEG_UV_MEM_RND_R_UMSK (~(((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS)) +#define MJPEG_UV_FRM_CNT_R MJPEG_UV_FRM_CNT_R +#define MJPEG_UV_FRM_CNT_R_POS (24U) +#define MJPEG_UV_FRM_CNT_R_LEN (8U) +#define MJPEG_UV_FRM_CNT_R_MSK (((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS) +#define MJPEG_UV_FRM_CNT_R_UMSK (~(((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS)) + +/* 0x54 : mjpeg_UV_frame_write_status */ +#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET (0x54) +#define MJPEG_UV_MEM_HBLK_W MJPEG_UV_MEM_HBLK_W +#define MJPEG_UV_MEM_HBLK_W_POS (0U) +#define MJPEG_UV_MEM_HBLK_W_LEN (13U) +#define MJPEG_UV_MEM_HBLK_W_MSK (((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS) +#define MJPEG_UV_MEM_HBLK_W_UMSK (~(((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS)) +#define MJPEG_UV_MEM_RND_W MJPEG_UV_MEM_RND_W +#define MJPEG_UV_MEM_RND_W_POS (16U) +#define MJPEG_UV_MEM_RND_W_LEN (8U) +#define MJPEG_UV_MEM_RND_W_MSK (((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS) +#define MJPEG_UV_MEM_RND_W_UMSK (~(((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS)) +#define MJPEG_UV_FRM_CNT_W MJPEG_UV_FRM_CNT_W +#define MJPEG_UV_FRM_CNT_W_POS (24U) +#define MJPEG_UV_FRM_CNT_W_LEN (8U) +#define MJPEG_UV_FRM_CNT_W_MSK (((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS) +#define MJPEG_UV_FRM_CNT_W_UMSK (~(((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS)) + +/* 0x80 : mjpeg_start_addr0 */ +#define MJPEG_START_ADDR0_OFFSET (0x80) +#define MJPEG_FRAME_START_ADDR_0 MJPEG_FRAME_START_ADDR_0 +#define MJPEG_FRAME_START_ADDR_0_POS (0U) +#define MJPEG_FRAME_START_ADDR_0_LEN (32U) +#define MJPEG_FRAME_START_ADDR_0_MSK (((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS) +#define MJPEG_FRAME_START_ADDR_0_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS)) + +/* 0x84 : mjpeg_bit_cnt0 */ +#define MJPEG_BIT_CNT0_OFFSET (0x84) +#define MJPEG_FRAME_BIT_CNT_0 MJPEG_FRAME_BIT_CNT_0 +#define MJPEG_FRAME_BIT_CNT_0_POS (0U) +#define MJPEG_FRAME_BIT_CNT_0_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_0_MSK (((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS) +#define MJPEG_FRAME_BIT_CNT_0_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS)) + +/* 0x88 : mjpeg_start_addr1 */ +#define MJPEG_START_ADDR1_OFFSET (0x88) +#define MJPEG_FRAME_START_ADDR_1 MJPEG_FRAME_START_ADDR_1 +#define MJPEG_FRAME_START_ADDR_1_POS (0U) +#define MJPEG_FRAME_START_ADDR_1_LEN (32U) +#define MJPEG_FRAME_START_ADDR_1_MSK (((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS) +#define MJPEG_FRAME_START_ADDR_1_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS)) + +/* 0x8C : mjpeg_bit_cnt1 */ +#define MJPEG_BIT_CNT1_OFFSET (0x8C) +#define MJPEG_FRAME_BIT_CNT_1 MJPEG_FRAME_BIT_CNT_1 +#define MJPEG_FRAME_BIT_CNT_1_POS (0U) +#define MJPEG_FRAME_BIT_CNT_1_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_1_MSK (((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS) +#define MJPEG_FRAME_BIT_CNT_1_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS)) + +/* 0x90 : mjpeg_start_addr2 */ +#define MJPEG_START_ADDR2_OFFSET (0x90) +#define MJPEG_FRAME_START_ADDR_2 MJPEG_FRAME_START_ADDR_2 +#define MJPEG_FRAME_START_ADDR_2_POS (0U) +#define MJPEG_FRAME_START_ADDR_2_LEN (32U) +#define MJPEG_FRAME_START_ADDR_2_MSK (((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS) +#define MJPEG_FRAME_START_ADDR_2_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS)) + +/* 0x94 : mjpeg_bit_cnt2 */ +#define MJPEG_BIT_CNT2_OFFSET (0x94) +#define MJPEG_FRAME_BIT_CNT_2 MJPEG_FRAME_BIT_CNT_2 +#define MJPEG_FRAME_BIT_CNT_2_POS (0U) +#define MJPEG_FRAME_BIT_CNT_2_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_2_MSK (((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS) +#define MJPEG_FRAME_BIT_CNT_2_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS)) + +/* 0x98 : mjpeg_start_addr3 */ +#define MJPEG_START_ADDR3_OFFSET (0x98) +#define MJPEG_FRAME_START_ADDR_3 MJPEG_FRAME_START_ADDR_3 +#define MJPEG_FRAME_START_ADDR_3_POS (0U) +#define MJPEG_FRAME_START_ADDR_3_LEN (32U) +#define MJPEG_FRAME_START_ADDR_3_MSK (((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS) +#define MJPEG_FRAME_START_ADDR_3_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS)) + +/* 0x9C : mjpeg_bit_cnt3 */ +#define MJPEG_BIT_CNT3_OFFSET (0x9C) +#define MJPEG_FRAME_BIT_CNT_3 MJPEG_FRAME_BIT_CNT_3 +#define MJPEG_FRAME_BIT_CNT_3_POS (0U) +#define MJPEG_FRAME_BIT_CNT_3_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_3_MSK (((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS) +#define MJPEG_FRAME_BIT_CNT_3_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS)) + +/* 0xA0 : mjpeg_start_addr4 */ +#define MJPEG_START_ADDR4_OFFSET (0xA0) +#define MJPEG_FRAME_START_ADDR_4 MJPEG_FRAME_START_ADDR_4 +#define MJPEG_FRAME_START_ADDR_4_POS (0U) +#define MJPEG_FRAME_START_ADDR_4_LEN (32U) +#define MJPEG_FRAME_START_ADDR_4_MSK (((1U << MJPEG_FRAME_START_ADDR_4_LEN) - 1) << MJPEG_FRAME_START_ADDR_4_POS) +#define MJPEG_FRAME_START_ADDR_4_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_4_LEN) - 1) << MJPEG_FRAME_START_ADDR_4_POS)) + +/* 0xA4 : mjpeg_bit_cnt4 */ +#define MJPEG_BIT_CNT4_OFFSET (0xA4) +#define MJPEG_FRAME_BIT_CNT_4 MJPEG_FRAME_BIT_CNT_4 +#define MJPEG_FRAME_BIT_CNT_4_POS (0U) +#define MJPEG_FRAME_BIT_CNT_4_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_4_MSK (((1U << MJPEG_FRAME_BIT_CNT_4_LEN) - 1) << MJPEG_FRAME_BIT_CNT_4_POS) +#define MJPEG_FRAME_BIT_CNT_4_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_4_LEN) - 1) << MJPEG_FRAME_BIT_CNT_4_POS)) + +/* 0xA8 : mjpeg_start_addr5 */ +#define MJPEG_START_ADDR5_OFFSET (0xA8) +#define MJPEG_FRAME_START_ADDR_5 MJPEG_FRAME_START_ADDR_5 +#define MJPEG_FRAME_START_ADDR_5_POS (0U) +#define MJPEG_FRAME_START_ADDR_5_LEN (32U) +#define MJPEG_FRAME_START_ADDR_5_MSK (((1U << MJPEG_FRAME_START_ADDR_5_LEN) - 1) << MJPEG_FRAME_START_ADDR_5_POS) +#define MJPEG_FRAME_START_ADDR_5_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_5_LEN) - 1) << MJPEG_FRAME_START_ADDR_5_POS)) + +/* 0xAC : mjpeg_bit_cnt5 */ +#define MJPEG_BIT_CNT5_OFFSET (0xAC) +#define MJPEG_FRAME_BIT_CNT_5 MJPEG_FRAME_BIT_CNT_5 +#define MJPEG_FRAME_BIT_CNT_5_POS (0U) +#define MJPEG_FRAME_BIT_CNT_5_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_5_MSK (((1U << MJPEG_FRAME_BIT_CNT_5_LEN) - 1) << MJPEG_FRAME_BIT_CNT_5_POS) +#define MJPEG_FRAME_BIT_CNT_5_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_5_LEN) - 1) << MJPEG_FRAME_BIT_CNT_5_POS)) + +/* 0xB0 : mjpeg_start_addr6 */ +#define MJPEG_START_ADDR6_OFFSET (0xB0) +#define MJPEG_FRAME_START_ADDR_6 MJPEG_FRAME_START_ADDR_6 +#define MJPEG_FRAME_START_ADDR_6_POS (0U) +#define MJPEG_FRAME_START_ADDR_6_LEN (32U) +#define MJPEG_FRAME_START_ADDR_6_MSK (((1U << MJPEG_FRAME_START_ADDR_6_LEN) - 1) << MJPEG_FRAME_START_ADDR_6_POS) +#define MJPEG_FRAME_START_ADDR_6_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_6_LEN) - 1) << MJPEG_FRAME_START_ADDR_6_POS)) + +/* 0xB4 : mjpeg_bit_cnt6 */ +#define MJPEG_BIT_CNT6_OFFSET (0xB4) +#define MJPEG_FRAME_BIT_CNT_6 MJPEG_FRAME_BIT_CNT_6 +#define MJPEG_FRAME_BIT_CNT_6_POS (0U) +#define MJPEG_FRAME_BIT_CNT_6_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_6_MSK (((1U << MJPEG_FRAME_BIT_CNT_6_LEN) - 1) << MJPEG_FRAME_BIT_CNT_6_POS) +#define MJPEG_FRAME_BIT_CNT_6_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_6_LEN) - 1) << MJPEG_FRAME_BIT_CNT_6_POS)) + +/* 0xB8 : mjpeg_start_addr7 */ +#define MJPEG_START_ADDR7_OFFSET (0xB8) +#define MJPEG_FRAME_START_ADDR_7 MJPEG_FRAME_START_ADDR_7 +#define MJPEG_FRAME_START_ADDR_7_POS (0U) +#define MJPEG_FRAME_START_ADDR_7_LEN (32U) +#define MJPEG_FRAME_START_ADDR_7_MSK (((1U << MJPEG_FRAME_START_ADDR_7_LEN) - 1) << MJPEG_FRAME_START_ADDR_7_POS) +#define MJPEG_FRAME_START_ADDR_7_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_7_LEN) - 1) << MJPEG_FRAME_START_ADDR_7_POS)) + +/* 0xBC : mjpeg_bit_cnt7 */ +#define MJPEG_BIT_CNT7_OFFSET (0xBC) +#define MJPEG_FRAME_BIT_CNT_7 MJPEG_FRAME_BIT_CNT_7 +#define MJPEG_FRAME_BIT_CNT_7_POS (0U) +#define MJPEG_FRAME_BIT_CNT_7_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_7_MSK (((1U << MJPEG_FRAME_BIT_CNT_7_LEN) - 1) << MJPEG_FRAME_BIT_CNT_7_POS) +#define MJPEG_FRAME_BIT_CNT_7_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_7_LEN) - 1) << MJPEG_FRAME_BIT_CNT_7_POS)) + +/* 0xC0 : mjpeg_start_addr_8 */ +#define MJPEG_START_ADDR_8_OFFSET (0xC0) +#define MJPEG_FRAME_START_ADDR_8 MJPEG_FRAME_START_ADDR_8 +#define MJPEG_FRAME_START_ADDR_8_POS (0U) +#define MJPEG_FRAME_START_ADDR_8_LEN (32U) +#define MJPEG_FRAME_START_ADDR_8_MSK (((1U << MJPEG_FRAME_START_ADDR_8_LEN) - 1) << MJPEG_FRAME_START_ADDR_8_POS) +#define MJPEG_FRAME_START_ADDR_8_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_8_LEN) - 1) << MJPEG_FRAME_START_ADDR_8_POS)) + +/* 0xC4 : mjpeg_bit_cnt_8 */ +#define MJPEG_BIT_CNT_8_OFFSET (0xC4) +#define MJPEG_FRAME_BIT_CNT_8 MJPEG_FRAME_BIT_CNT_8 +#define MJPEG_FRAME_BIT_CNT_8_POS (0U) +#define MJPEG_FRAME_BIT_CNT_8_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_8_MSK (((1U << MJPEG_FRAME_BIT_CNT_8_LEN) - 1) << MJPEG_FRAME_BIT_CNT_8_POS) +#define MJPEG_FRAME_BIT_CNT_8_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_8_LEN) - 1) << MJPEG_FRAME_BIT_CNT_8_POS)) + +/* 0xC8 : mjpeg_start_addr_9 */ +#define MJPEG_START_ADDR_9_OFFSET (0xC8) +#define MJPEG_FRAME_START_ADDR_9 MJPEG_FRAME_START_ADDR_9 +#define MJPEG_FRAME_START_ADDR_9_POS (0U) +#define MJPEG_FRAME_START_ADDR_9_LEN (32U) +#define MJPEG_FRAME_START_ADDR_9_MSK (((1U << MJPEG_FRAME_START_ADDR_9_LEN) - 1) << MJPEG_FRAME_START_ADDR_9_POS) +#define MJPEG_FRAME_START_ADDR_9_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_9_LEN) - 1) << MJPEG_FRAME_START_ADDR_9_POS)) + +/* 0xCC : mjpeg_bit_cnt_9 */ +#define MJPEG_BIT_CNT_9_OFFSET (0xCC) +#define MJPEG_FRAME_BIT_CNT_9 MJPEG_FRAME_BIT_CNT_9 +#define MJPEG_FRAME_BIT_CNT_9_POS (0U) +#define MJPEG_FRAME_BIT_CNT_9_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_9_MSK (((1U << MJPEG_FRAME_BIT_CNT_9_LEN) - 1) << MJPEG_FRAME_BIT_CNT_9_POS) +#define MJPEG_FRAME_BIT_CNT_9_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_9_LEN) - 1) << MJPEG_FRAME_BIT_CNT_9_POS)) + +/* 0xD0 : mjpeg_start_addr_a */ +#define MJPEG_START_ADDR_A_OFFSET (0xD0) +#define MJPEG_FRAME_START_ADDR_A MJPEG_FRAME_START_ADDR_A +#define MJPEG_FRAME_START_ADDR_A_POS (0U) +#define MJPEG_FRAME_START_ADDR_A_LEN (32U) +#define MJPEG_FRAME_START_ADDR_A_MSK (((1U << MJPEG_FRAME_START_ADDR_A_LEN) - 1) << MJPEG_FRAME_START_ADDR_A_POS) +#define MJPEG_FRAME_START_ADDR_A_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_A_LEN) - 1) << MJPEG_FRAME_START_ADDR_A_POS)) + +/* 0xD4 : mjpeg_bit_cnt_a */ +#define MJPEG_BIT_CNT_A_OFFSET (0xD4) +#define MJPEG_FRAME_BIT_CNT_A MJPEG_FRAME_BIT_CNT_A +#define MJPEG_FRAME_BIT_CNT_A_POS (0U) +#define MJPEG_FRAME_BIT_CNT_A_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_A_MSK (((1U << MJPEG_FRAME_BIT_CNT_A_LEN) - 1) << MJPEG_FRAME_BIT_CNT_A_POS) +#define MJPEG_FRAME_BIT_CNT_A_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_A_LEN) - 1) << MJPEG_FRAME_BIT_CNT_A_POS)) + +/* 0xD8 : mjpeg_start_addr_b */ +#define MJPEG_START_ADDR_B_OFFSET (0xD8) +#define MJPEG_FRAME_START_ADDR_B MJPEG_FRAME_START_ADDR_B +#define MJPEG_FRAME_START_ADDR_B_POS (0U) +#define MJPEG_FRAME_START_ADDR_B_LEN (32U) +#define MJPEG_FRAME_START_ADDR_B_MSK (((1U << MJPEG_FRAME_START_ADDR_B_LEN) - 1) << MJPEG_FRAME_START_ADDR_B_POS) +#define MJPEG_FRAME_START_ADDR_B_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_B_LEN) - 1) << MJPEG_FRAME_START_ADDR_B_POS)) + +/* 0xDC : mjpeg_bit_cnt_b */ +#define MJPEG_BIT_CNT_B_OFFSET (0xDC) +#define MJPEG_FRAME_BIT_CNT_B MJPEG_FRAME_BIT_CNT_B +#define MJPEG_FRAME_BIT_CNT_B_POS (0U) +#define MJPEG_FRAME_BIT_CNT_B_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_B_MSK (((1U << MJPEG_FRAME_BIT_CNT_B_LEN) - 1) << MJPEG_FRAME_BIT_CNT_B_POS) +#define MJPEG_FRAME_BIT_CNT_B_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_B_LEN) - 1) << MJPEG_FRAME_BIT_CNT_B_POS)) + +/* 0xE0 : mjpeg_start_addr_c */ +#define MJPEG_START_ADDR_C_OFFSET (0xE0) +#define MJPEG_FRAME_START_ADDR_C MJPEG_FRAME_START_ADDR_C +#define MJPEG_FRAME_START_ADDR_C_POS (0U) +#define MJPEG_FRAME_START_ADDR_C_LEN (32U) +#define MJPEG_FRAME_START_ADDR_C_MSK (((1U << MJPEG_FRAME_START_ADDR_C_LEN) - 1) << MJPEG_FRAME_START_ADDR_C_POS) +#define MJPEG_FRAME_START_ADDR_C_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_C_LEN) - 1) << MJPEG_FRAME_START_ADDR_C_POS)) + +/* 0xE4 : mjpeg_bit_cnt_c */ +#define MJPEG_BIT_CNT_C_OFFSET (0xE4) +#define MJPEG_FRAME_BIT_CNT_C MJPEG_FRAME_BIT_CNT_C +#define MJPEG_FRAME_BIT_CNT_C_POS (0U) +#define MJPEG_FRAME_BIT_CNT_C_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_C_MSK (((1U << MJPEG_FRAME_BIT_CNT_C_LEN) - 1) << MJPEG_FRAME_BIT_CNT_C_POS) +#define MJPEG_FRAME_BIT_CNT_C_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_C_LEN) - 1) << MJPEG_FRAME_BIT_CNT_C_POS)) + +/* 0xE8 : mjpeg_start_addr_d */ +#define MJPEG_START_ADDR_D_OFFSET (0xE8) +#define MJPEG_FRAME_START_ADDR_D MJPEG_FRAME_START_ADDR_D +#define MJPEG_FRAME_START_ADDR_D_POS (0U) +#define MJPEG_FRAME_START_ADDR_D_LEN (32U) +#define MJPEG_FRAME_START_ADDR_D_MSK (((1U << MJPEG_FRAME_START_ADDR_D_LEN) - 1) << MJPEG_FRAME_START_ADDR_D_POS) +#define MJPEG_FRAME_START_ADDR_D_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_D_LEN) - 1) << MJPEG_FRAME_START_ADDR_D_POS)) + +/* 0xEC : mjpeg_bit_cnt_d */ +#define MJPEG_BIT_CNT_D_OFFSET (0xEC) +#define MJPEG_FRAME_BIT_CNT_D MJPEG_FRAME_BIT_CNT_D +#define MJPEG_FRAME_BIT_CNT_D_POS (0U) +#define MJPEG_FRAME_BIT_CNT_D_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_D_MSK (((1U << MJPEG_FRAME_BIT_CNT_D_LEN) - 1) << MJPEG_FRAME_BIT_CNT_D_POS) +#define MJPEG_FRAME_BIT_CNT_D_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_D_LEN) - 1) << MJPEG_FRAME_BIT_CNT_D_POS)) + +/* 0xF0 : mjpeg_start_addr_e */ +#define MJPEG_START_ADDR_E_OFFSET (0xF0) +#define MJPEG_FRAME_START_ADDR_E MJPEG_FRAME_START_ADDR_E +#define MJPEG_FRAME_START_ADDR_E_POS (0U) +#define MJPEG_FRAME_START_ADDR_E_LEN (32U) +#define MJPEG_FRAME_START_ADDR_E_MSK (((1U << MJPEG_FRAME_START_ADDR_E_LEN) - 1) << MJPEG_FRAME_START_ADDR_E_POS) +#define MJPEG_FRAME_START_ADDR_E_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_E_LEN) - 1) << MJPEG_FRAME_START_ADDR_E_POS)) + +/* 0xF4 : mjpeg_bit_cnt_e */ +#define MJPEG_BIT_CNT_E_OFFSET (0xF4) +#define MJPEG_FRAME_BIT_CNT_E MJPEG_FRAME_BIT_CNT_E +#define MJPEG_FRAME_BIT_CNT_E_POS (0U) +#define MJPEG_FRAME_BIT_CNT_E_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_E_MSK (((1U << MJPEG_FRAME_BIT_CNT_E_LEN) - 1) << MJPEG_FRAME_BIT_CNT_E_POS) +#define MJPEG_FRAME_BIT_CNT_E_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_E_LEN) - 1) << MJPEG_FRAME_BIT_CNT_E_POS)) + +/* 0xF8 : mjpeg_start_addr_f */ +#define MJPEG_START_ADDR_F_OFFSET (0xF8) +#define MJPEG_FRAME_START_ADDR_F MJPEG_FRAME_START_ADDR_F +#define MJPEG_FRAME_START_ADDR_F_POS (0U) +#define MJPEG_FRAME_START_ADDR_F_LEN (32U) +#define MJPEG_FRAME_START_ADDR_F_MSK (((1U << MJPEG_FRAME_START_ADDR_F_LEN) - 1) << MJPEG_FRAME_START_ADDR_F_POS) +#define MJPEG_FRAME_START_ADDR_F_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_F_LEN) - 1) << MJPEG_FRAME_START_ADDR_F_POS)) + +/* 0xFC : mjpeg_bit_cnt_f */ +#define MJPEG_BIT_CNT_F_OFFSET (0xFC) +#define MJPEG_FRAME_BIT_CNT_F MJPEG_FRAME_BIT_CNT_F +#define MJPEG_FRAME_BIT_CNT_F_POS (0U) +#define MJPEG_FRAME_BIT_CNT_F_LEN (32U) +#define MJPEG_FRAME_BIT_CNT_F_MSK (((1U << MJPEG_FRAME_BIT_CNT_F_LEN) - 1) << MJPEG_FRAME_BIT_CNT_F_POS) +#define MJPEG_FRAME_BIT_CNT_F_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_F_LEN) - 1) << MJPEG_FRAME_BIT_CNT_F_POS)) + +/* 0x100 : mjpeg_q_mode0 */ +#define MJPEG_Q_MODE0_OFFSET (0x100) +#define MJPEG_FRAME_Q_MODE_0 MJPEG_FRAME_Q_MODE_0 +#define MJPEG_FRAME_Q_MODE_0_POS (0U) +#define MJPEG_FRAME_Q_MODE_0_LEN (7U) +#define MJPEG_FRAME_Q_MODE_0_MSK (((1U << MJPEG_FRAME_Q_MODE_0_LEN) - 1) << MJPEG_FRAME_Q_MODE_0_POS) +#define MJPEG_FRAME_Q_MODE_0_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_0_LEN) - 1) << MJPEG_FRAME_Q_MODE_0_POS)) + +/* 0x104 : mjpeg_q_mode1 */ +#define MJPEG_Q_MODE1_OFFSET (0x104) +#define MJPEG_FRAME_Q_MODE_1 MJPEG_FRAME_Q_MODE_1 +#define MJPEG_FRAME_Q_MODE_1_POS (0U) +#define MJPEG_FRAME_Q_MODE_1_LEN (7U) +#define MJPEG_FRAME_Q_MODE_1_MSK (((1U << MJPEG_FRAME_Q_MODE_1_LEN) - 1) << MJPEG_FRAME_Q_MODE_1_POS) +#define MJPEG_FRAME_Q_MODE_1_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_1_LEN) - 1) << MJPEG_FRAME_Q_MODE_1_POS)) + +/* 0x108 : mjpeg_q_mode2 */ +#define MJPEG_Q_MODE2_OFFSET (0x108) +#define MJPEG_FRAME_Q_MODE_2 MJPEG_FRAME_Q_MODE_2 +#define MJPEG_FRAME_Q_MODE_2_POS (0U) +#define MJPEG_FRAME_Q_MODE_2_LEN (7U) +#define MJPEG_FRAME_Q_MODE_2_MSK (((1U << MJPEG_FRAME_Q_MODE_2_LEN) - 1) << MJPEG_FRAME_Q_MODE_2_POS) +#define MJPEG_FRAME_Q_MODE_2_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_2_LEN) - 1) << MJPEG_FRAME_Q_MODE_2_POS)) + +/* 0x10C : mjpeg_q_mode3 */ +#define MJPEG_Q_MODE3_OFFSET (0x10C) +#define MJPEG_FRAME_Q_MODE_3 MJPEG_FRAME_Q_MODE_3 +#define MJPEG_FRAME_Q_MODE_3_POS (0U) +#define MJPEG_FRAME_Q_MODE_3_LEN (7U) +#define MJPEG_FRAME_Q_MODE_3_MSK (((1U << MJPEG_FRAME_Q_MODE_3_LEN) - 1) << MJPEG_FRAME_Q_MODE_3_POS) +#define MJPEG_FRAME_Q_MODE_3_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_3_LEN) - 1) << MJPEG_FRAME_Q_MODE_3_POS)) + +/* 0x110 : mjpeg_q_mode4 */ +#define MJPEG_Q_MODE4_OFFSET (0x110) +#define MJPEG_FRAME_Q_MODE_4 MJPEG_FRAME_Q_MODE_4 +#define MJPEG_FRAME_Q_MODE_4_POS (0U) +#define MJPEG_FRAME_Q_MODE_4_LEN (7U) +#define MJPEG_FRAME_Q_MODE_4_MSK (((1U << MJPEG_FRAME_Q_MODE_4_LEN) - 1) << MJPEG_FRAME_Q_MODE_4_POS) +#define MJPEG_FRAME_Q_MODE_4_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_4_LEN) - 1) << MJPEG_FRAME_Q_MODE_4_POS)) + +/* 0x114 : mjpeg_q_mode5 */ +#define MJPEG_Q_MODE5_OFFSET (0x114) +#define MJPEG_FRAME_Q_MODE_5 MJPEG_FRAME_Q_MODE_5 +#define MJPEG_FRAME_Q_MODE_5_POS (0U) +#define MJPEG_FRAME_Q_MODE_5_LEN (7U) +#define MJPEG_FRAME_Q_MODE_5_MSK (((1U << MJPEG_FRAME_Q_MODE_5_LEN) - 1) << MJPEG_FRAME_Q_MODE_5_POS) +#define MJPEG_FRAME_Q_MODE_5_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_5_LEN) - 1) << MJPEG_FRAME_Q_MODE_5_POS)) + +/* 0x118 : mjpeg_q_mode6 */ +#define MJPEG_Q_MODE6_OFFSET (0x118) +#define MJPEG_FRAME_Q_MODE_6 MJPEG_FRAME_Q_MODE_6 +#define MJPEG_FRAME_Q_MODE_6_POS (0U) +#define MJPEG_FRAME_Q_MODE_6_LEN (7U) +#define MJPEG_FRAME_Q_MODE_6_MSK (((1U << MJPEG_FRAME_Q_MODE_6_LEN) - 1) << MJPEG_FRAME_Q_MODE_6_POS) +#define MJPEG_FRAME_Q_MODE_6_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_6_LEN) - 1) << MJPEG_FRAME_Q_MODE_6_POS)) + +/* 0x11C : mjpeg_q_mode7 */ +#define MJPEG_Q_MODE7_OFFSET (0x11C) +#define MJPEG_FRAME_Q_MODE_7 MJPEG_FRAME_Q_MODE_7 +#define MJPEG_FRAME_Q_MODE_7_POS (0U) +#define MJPEG_FRAME_Q_MODE_7_LEN (7U) +#define MJPEG_FRAME_Q_MODE_7_MSK (((1U << MJPEG_FRAME_Q_MODE_7_LEN) - 1) << MJPEG_FRAME_Q_MODE_7_POS) +#define MJPEG_FRAME_Q_MODE_7_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_7_LEN) - 1) << MJPEG_FRAME_Q_MODE_7_POS)) + +/* 0x120 : mjpeg_q_mode_8 */ +#define MJPEG_Q_MODE_8_OFFSET (0x120) +#define MJPEG_FRAME_Q_MODE_8 MJPEG_FRAME_Q_MODE_8 +#define MJPEG_FRAME_Q_MODE_8_POS (0U) +#define MJPEG_FRAME_Q_MODE_8_LEN (7U) +#define MJPEG_FRAME_Q_MODE_8_MSK (((1U << MJPEG_FRAME_Q_MODE_8_LEN) - 1) << MJPEG_FRAME_Q_MODE_8_POS) +#define MJPEG_FRAME_Q_MODE_8_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_8_LEN) - 1) << MJPEG_FRAME_Q_MODE_8_POS)) + +/* 0x124 : mjpeg_q_mode_9 */ +#define MJPEG_Q_MODE_9_OFFSET (0x124) +#define MJPEG_FRAME_Q_MODE_9 MJPEG_FRAME_Q_MODE_9 +#define MJPEG_FRAME_Q_MODE_9_POS (0U) +#define MJPEG_FRAME_Q_MODE_9_LEN (7U) +#define MJPEG_FRAME_Q_MODE_9_MSK (((1U << MJPEG_FRAME_Q_MODE_9_LEN) - 1) << MJPEG_FRAME_Q_MODE_9_POS) +#define MJPEG_FRAME_Q_MODE_9_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_9_LEN) - 1) << MJPEG_FRAME_Q_MODE_9_POS)) + +/* 0x128 : mjpeg_q_mode_a */ +#define MJPEG_Q_MODE_A_OFFSET (0x128) +#define MJPEG_FRAME_Q_MODE_A MJPEG_FRAME_Q_MODE_A +#define MJPEG_FRAME_Q_MODE_A_POS (0U) +#define MJPEG_FRAME_Q_MODE_A_LEN (7U) +#define MJPEG_FRAME_Q_MODE_A_MSK (((1U << MJPEG_FRAME_Q_MODE_A_LEN) - 1) << MJPEG_FRAME_Q_MODE_A_POS) +#define MJPEG_FRAME_Q_MODE_A_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_A_LEN) - 1) << MJPEG_FRAME_Q_MODE_A_POS)) + +/* 0x12C : mjpeg_q_mode_b */ +#define MJPEG_Q_MODE_B_OFFSET (0x12C) +#define MJPEG_FRAME_Q_MODE_B MJPEG_FRAME_Q_MODE_B +#define MJPEG_FRAME_Q_MODE_B_POS (0U) +#define MJPEG_FRAME_Q_MODE_B_LEN (7U) +#define MJPEG_FRAME_Q_MODE_B_MSK (((1U << MJPEG_FRAME_Q_MODE_B_LEN) - 1) << MJPEG_FRAME_Q_MODE_B_POS) +#define MJPEG_FRAME_Q_MODE_B_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_B_LEN) - 1) << MJPEG_FRAME_Q_MODE_B_POS)) + +/* 0x130 : mjpeg_q_mode_c */ +#define MJPEG_Q_MODE_C_OFFSET (0x130) +#define MJPEG_FRAME_Q_MODE_C MJPEG_FRAME_Q_MODE_C +#define MJPEG_FRAME_Q_MODE_C_POS (0U) +#define MJPEG_FRAME_Q_MODE_C_LEN (7U) +#define MJPEG_FRAME_Q_MODE_C_MSK (((1U << MJPEG_FRAME_Q_MODE_C_LEN) - 1) << MJPEG_FRAME_Q_MODE_C_POS) +#define MJPEG_FRAME_Q_MODE_C_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_C_LEN) - 1) << MJPEG_FRAME_Q_MODE_C_POS)) + +/* 0x134 : mjpeg_q_mode_d */ +#define MJPEG_Q_MODE_D_OFFSET (0x134) +#define MJPEG_FRAME_Q_MODE_D MJPEG_FRAME_Q_MODE_D +#define MJPEG_FRAME_Q_MODE_D_POS (0U) +#define MJPEG_FRAME_Q_MODE_D_LEN (7U) +#define MJPEG_FRAME_Q_MODE_D_MSK (((1U << MJPEG_FRAME_Q_MODE_D_LEN) - 1) << MJPEG_FRAME_Q_MODE_D_POS) +#define MJPEG_FRAME_Q_MODE_D_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_D_LEN) - 1) << MJPEG_FRAME_Q_MODE_D_POS)) + +/* 0x138 : mjpeg_q_mode_e */ +#define MJPEG_Q_MODE_E_OFFSET (0x138) +#define MJPEG_FRAME_Q_MODE_E MJPEG_FRAME_Q_MODE_E +#define MJPEG_FRAME_Q_MODE_E_POS (0U) +#define MJPEG_FRAME_Q_MODE_E_LEN (7U) +#define MJPEG_FRAME_Q_MODE_E_MSK (((1U << MJPEG_FRAME_Q_MODE_E_LEN) - 1) << MJPEG_FRAME_Q_MODE_E_POS) +#define MJPEG_FRAME_Q_MODE_E_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_E_LEN) - 1) << MJPEG_FRAME_Q_MODE_E_POS)) + +/* 0x13C : mjpeg_q_mode_f */ +#define MJPEG_Q_MODE_F_OFFSET (0x13C) +#define MJPEG_FRAME_Q_MODE_F MJPEG_FRAME_Q_MODE_F +#define MJPEG_FRAME_Q_MODE_F_POS (0U) +#define MJPEG_FRAME_Q_MODE_F_LEN (7U) +#define MJPEG_FRAME_Q_MODE_F_MSK (((1U << MJPEG_FRAME_Q_MODE_F_LEN) - 1) << MJPEG_FRAME_Q_MODE_F_POS) +#define MJPEG_FRAME_Q_MODE_F_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_F_LEN) - 1) << MJPEG_FRAME_Q_MODE_F_POS)) + +/* 0x1F0 : mjpeg_debug */ +#define MJPEG_DEBUG_OFFSET (0x1F0) +#define MJPEG_REG_MJPEG_DBG_EN MJPEG_REG_MJPEG_DBG_EN +#define MJPEG_REG_MJPEG_DBG_EN_POS (0U) +#define MJPEG_REG_MJPEG_DBG_EN_LEN (1U) +#define MJPEG_REG_MJPEG_DBG_EN_MSK (((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS) +#define MJPEG_REG_MJPEG_DBG_EN_UMSK (~(((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS)) +#define MJPEG_REG_MJPEG_DBG_SEL MJPEG_REG_MJPEG_DBG_SEL +#define MJPEG_REG_MJPEG_DBG_SEL_POS (4U) +#define MJPEG_REG_MJPEG_DBG_SEL_LEN (4U) +#define MJPEG_REG_MJPEG_DBG_SEL_MSK (((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS) +#define MJPEG_REG_MJPEG_DBG_SEL_UMSK (~(((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS)) + +/* 0x1FC : mjpeg_dummy_reg */ +#define MJPEG_DUMMY_REG_OFFSET (0x1FC) +#define MJPEG_DUMMY_REG MJPEG_DUMMY_REG +#define MJPEG_DUMMY_REG_POS (0U) +#define MJPEG_DUMMY_REG_LEN (32U) +#define MJPEG_DUMMY_REG_MSK (((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS) +#define MJPEG_DUMMY_REG_UMSK (~(((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS)) + +struct mjpeg_reg { + /* 0x0 : mjpeg_control_1 */ + union { + struct + { + uint32_t reg_mjpeg_enable : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_mjpeg_bit_order : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_order_u_even : 1; /* [ 2], r/w, 0x1 */ + uint32_t reg_wr_over_stop : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_last_hf_wblk_dmy : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_last_hf_hblk_dmy : 1; /* [ 5], r/w, 0x0 */ + uint32_t reg_reflect_dmy : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t reg_h_bust : 2; /* [ 9: 8], r/w, 0x3 */ + uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ + uint32_t reg_yuv_mode : 2; /* [13:12], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t reg_q_mode : 7; /* [22:16], r/w, 0x32 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t reg_y0_order : 2; /* [25:24], r/w, 0x0 */ + uint32_t reg_u0_order : 2; /* [27:26], r/w, 0x1 */ + uint32_t reg_y1_order : 2; /* [29:28], r/w, 0x2 */ + uint32_t reg_v0_order : 2; /* [31:30], r/w, 0x3 */ + } BF; + uint32_t WORD; + } mjpeg_control_1; + + /* 0x4 : mjpeg_control_2 */ + union { + struct + { + uint32_t reg_sw_frame : 5; /* [ 4: 0], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t reg_mjpeg_sw_mode : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_mjpeg_sw_run : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ + uint32_t reg_yy_dvp2ahb_lsel : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_yy_dvp2ahb_fsel : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_uv_dvp2ahb_lsel : 1; /* [ 14], r/w, 0x0 */ + uint32_t reg_uv_dvp2ahb_fsel : 1; /* [ 15], r/w, 0x0 */ + uint32_t reg_mjpeg_wait_cycle : 16; /* [31:16], r/w, 0x400 */ + } BF; + uint32_t WORD; + } mjpeg_control_2; + + /* 0x08 : mjpeg_yy_frame_addr */ + union { + struct + { + uint32_t reg_yy_addr_start : 32; /* [31: 0], r/w, 0x80000000L */ + } BF; + uint32_t WORD; + } mjpeg_yy_frame_addr; + + /* 0x0C : mjpeg_uv_frame_addr */ + union { + struct + { + uint32_t reg_uv_addr_start : 32; /* [31: 0], r/w, 0x80000000L */ + } BF; + uint32_t WORD; + } mjpeg_uv_frame_addr; + + /* 0x10 : mjpeg_yuv_mem */ + union { + struct + { + uint32_t reg_yy_mem_hblk : 13; /* [12: 0], r/w, 0x2 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t reg_uv_mem_hblk : 13; /* [28:16], r/w, 0x2 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_yuv_mem; + + /* 0x14 : jpeg_frame_addr */ + union { + struct + { + uint32_t reg_w_addr_start : 32; /* [31: 0], r/w, 0x80400000L */ + } BF; + uint32_t WORD; + } jpeg_frame_addr; + + /* 0x18 : jpeg_store_memory */ + union { + struct + { + uint32_t reg_w_burst_cnt : 32; /* [31: 0], r/w, 0x4000 */ + } BF; + uint32_t WORD; + } jpeg_store_memory; + + /* 0x1C : mjpeg_control_3 */ + union { + struct + { + uint32_t reg_int_normal_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_int_cam_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_int_mem_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t reg_int_frame_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t sts_normal_int : 1; /* [ 4], r, 0x0 */ + uint32_t sts_cam_int : 1; /* [ 5], r, 0x0 */ + uint32_t sts_mem_int : 1; /* [ 6], r, 0x0 */ + uint32_t sts_frame_int : 1; /* [ 7], r, 0x0 */ + uint32_t mjpeg_idle : 1; /* [ 8], r, 0x1 */ + uint32_t mjpeg_func : 1; /* [ 9], r, 0x0 */ + uint32_t mjpeg_wait : 1; /* [ 10], r, 0x0 */ + uint32_t mjpeg_flsh : 1; /* [ 11], r, 0x0 */ + uint32_t mjpeg_mans : 1; /* [ 12], r, 0x0 */ + uint32_t mjpeg_manf : 1; /* [ 13], r, 0x0 */ + uint32_t ahb_idle : 1; /* [ 14], r, 0x0 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t reg_frame_cnt_trgr_int : 5; /* [20:16], r/w, 0x0 */ + uint32_t reg_int_idle_en : 1; /* [ 21], r/w, 0x0 */ + uint32_t sts_idle_int : 1; /* [ 22], r, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t frame_valid_cnt : 5; /* [28:24], r, 0x0 */ + uint32_t reg_int_swap_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sts_swap_int : 1; /* [ 30], r, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_control_3; + + /* 0x20 : mjpeg_frame_fifo_pop */ + union { + struct + { + uint32_t rfifo_pop : 1; /* [ 0], w1p, 0x0 */ + uint32_t reg_w_swap_clr : 1; /* [ 1], w1p, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t reg_int_normal_clr : 1; /* [ 8], w1p, 0x0 */ + uint32_t reg_int_cam_clr : 1; /* [ 9], w1p, 0x0 */ + uint32_t reg_int_mem_clr : 1; /* [ 10], w1p, 0x0 */ + uint32_t reg_int_frame_clr : 1; /* [ 11], w1p, 0x0 */ + uint32_t reg_int_idle_clr : 1; /* [ 12], w1p, 0x0 */ + uint32_t reg_int_swap_clr : 1; /* [ 13], w1p, 0x0 */ + uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_frame_fifo_pop; + + /* 0x24 : mjpeg_frame_size */ + union { + struct + { + uint32_t reg_frame_wblk : 12; /* [11: 0], r/w, 0xf */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_frame_hblk : 12; /* [27:16], r/w, 0x14 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_frame_size; + + /* 0x28 : mjpeg_header_byte */ + union { + struct + { + uint32_t reg_head_byte : 12; /* [11: 0], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_tail_exp : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_header_byte; + + /* 0x2c reserved */ + uint8_t RESERVED0x2c[4]; + + /* 0x30 : mjpeg_swap_mode */ + union { + struct + { + uint32_t reg_w_swap_mode : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ + uint32_t sts_swap0_full : 1; /* [ 8], r, 0x0 */ + uint32_t sts_swap1_full : 1; /* [ 9], r, 0x0 */ + uint32_t sts_read_swap_idx : 1; /* [ 10], r, 0x0 */ + uint32_t sts_swap_fstart : 1; /* [ 11], r, 0x0 */ + uint32_t sts_swap_fend : 1; /* [ 12], r, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_swap_mode; + + /* 0x34 : mjpeg_swap_bit_cnt */ + union { + struct + { + uint32_t frame_swap_end_bit_cnt : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_swap_bit_cnt; + + /* 0x38 : mjpeg_paket_ctrl */ + union { + struct + { + uint32_t reg_pket_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_jend_to_pend : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ + uint32_t reg_pket_body_byte : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_paket_ctrl; + + /* 0x3C : mjpeg_paket_head_tail */ + union { + struct + { + uint32_t reg_pket_head_byte : 12; /* [11: 0], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_pket_tail_byte : 12; /* [27:16], r/w, 0x0 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_paket_head_tail; + + /* 0x40 : mjpeg_Y_frame_read_status_1 */ + union { + struct + { + uint32_t yy_mem_hblk_r : 13; /* [12: 0], r, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t yy_frm_hblk_r : 13; /* [28:16], r, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_Y_frame_read_status_1; + + /* 0x44 : mjpeg_Y_frame_read_status_2 */ + union { + struct + { + uint32_t yy_wblk_r : 13; /* [12: 0], r, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t yy_mem_rnd_r : 8; /* [23:16], r, 0x0 */ + uint32_t yy_frm_cnt_r : 8; /* [31:24], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_Y_frame_read_status_2; + + /* 0x48 : mjpeg_Y_frame_write_status */ + union { + struct + { + uint32_t yy_mem_hblk_w : 13; /* [12: 0], r, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t yy_mem_rnd_w : 8; /* [23:16], r, 0x0 */ + uint32_t yy_frm_cnt_w : 8; /* [31:24], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_Y_frame_write_status; + + /* 0x4C : mjpeg_UV_frame_read_status_1 */ + union { + struct + { + uint32_t uv_mem_hblk_r : 13; /* [12: 0], r, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t uv_frm_hblk_r : 13; /* [28:16], r, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_UV_frame_read_status_1; + + /* 0x50 : mjpeg_UV_frame_read_status_2 */ + union { + struct + { + uint32_t uv_wblk_r : 13; /* [12: 0], r, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t uv_mem_rnd_r : 8; /* [23:16], r, 0x0 */ + uint32_t uv_frm_cnt_r : 8; /* [31:24], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_UV_frame_read_status_2; + + /* 0x54 : mjpeg_UV_frame_write_status */ + union { + struct + { + uint32_t uv_mem_hblk_w : 13; /* [12: 0], r, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t uv_mem_rnd_w : 8; /* [23:16], r, 0x0 */ + uint32_t uv_frm_cnt_w : 8; /* [31:24], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_UV_frame_write_status; + + /* 0x58 reserved */ + uint8_t RESERVED0x58[40]; + + /* 0x80 : mjpeg_start_addr0 */ + union { + struct + { + uint32_t frame_start_addr_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr0; + + /* 0x84 : mjpeg_bit_cnt0 */ + union { + struct + { + uint32_t frame_bit_cnt_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt0; + + /* 0x88 : mjpeg_start_addr1 */ + union { + struct + { + uint32_t frame_start_addr_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr1; + + /* 0x8C : mjpeg_bit_cnt1 */ + union { + struct + { + uint32_t frame_bit_cnt_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt1; + + /* 0x90 : mjpeg_start_addr2 */ + union { + struct + { + uint32_t frame_start_addr_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr2; + + /* 0x94 : mjpeg_bit_cnt2 */ + union { + struct + { + uint32_t frame_bit_cnt_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt2; + + /* 0x98 : mjpeg_start_addr3 */ + union { + struct + { + uint32_t frame_start_addr_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr3; + + /* 0x9C : mjpeg_bit_cnt3 */ + union { + struct + { + uint32_t frame_bit_cnt_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt3; + + /* 0xA0 : mjpeg_start_addr4 */ + union { + struct + { + uint32_t frame_start_addr_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr4; + + /* 0xA4 : mjpeg_bit_cnt4 */ + union { + struct + { + uint32_t frame_bit_cnt_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt4; + + /* 0xA8 : mjpeg_start_addr5 */ + union { + struct + { + uint32_t frame_start_addr_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr5; + + /* 0xAC : mjpeg_bit_cnt5 */ + union { + struct + { + uint32_t frame_bit_cnt_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt5; + + /* 0xB0 : mjpeg_start_addr6 */ + union { + struct + { + uint32_t frame_start_addr_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr6; + + /* 0xB4 : mjpeg_bit_cnt6 */ + union { + struct + { + uint32_t frame_bit_cnt_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt6; + + /* 0xB8 : mjpeg_start_addr7 */ + union { + struct + { + uint32_t frame_start_addr_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr7; + + /* 0xBC : mjpeg_bit_cnt7 */ + union { + struct + { + uint32_t frame_bit_cnt_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt7; + + /* 0xC0 : mjpeg_start_addr_8 */ + union { + struct + { + uint32_t frame_start_addr_8 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr_8; + + /* 0xC4 : mjpeg_bit_cnt_8 */ + union { + struct + { + uint32_t frame_bit_cnt_8 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt_8; + + /* 0xC8 : mjpeg_start_addr_9 */ + union { + struct + { + uint32_t frame_start_addr_9 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr_9; + + /* 0xCC : mjpeg_bit_cnt_9 */ + union { + struct + { + uint32_t frame_bit_cnt_9 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt_9; + + /* 0xD0 : mjpeg_start_addr_a */ + union { + struct + { + uint32_t frame_start_addr_a : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr_a; + + /* 0xD4 : mjpeg_bit_cnt_a */ + union { + struct + { + uint32_t frame_bit_cnt_a : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt_a; + + /* 0xD8 : mjpeg_start_addr_b */ + union { + struct + { + uint32_t frame_start_addr_b : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr_b; + + /* 0xDC : mjpeg_bit_cnt_b */ + union { + struct + { + uint32_t frame_bit_cnt_b : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt_b; + + /* 0xE0 : mjpeg_start_addr_c */ + union { + struct + { + uint32_t frame_start_addr_c : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr_c; + + /* 0xE4 : mjpeg_bit_cnt_c */ + union { + struct + { + uint32_t frame_bit_cnt_c : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt_c; + + /* 0xE8 : mjpeg_start_addr_d */ + union { + struct + { + uint32_t frame_start_addr_d : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr_d; + + /* 0xEC : mjpeg_bit_cnt_d */ + union { + struct + { + uint32_t frame_bit_cnt_d : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt_d; + + /* 0xF0 : mjpeg_start_addr_e */ + union { + struct + { + uint32_t frame_start_addr_e : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr_e; + + /* 0xF4 : mjpeg_bit_cnt_e */ + union { + struct + { + uint32_t frame_bit_cnt_e : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt_e; + + /* 0xF8 : mjpeg_start_addr_f */ + union { + struct + { + uint32_t frame_start_addr_f : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_start_addr_f; + + /* 0xFC : mjpeg_bit_cnt_f */ + union { + struct + { + uint32_t frame_bit_cnt_f : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_bit_cnt_f; + + /* 0x100 : mjpeg_q_mode0 */ + union { + struct + { + uint32_t frame_q_mode_0 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode0; + + /* 0x104 : mjpeg_q_mode1 */ + union { + struct + { + uint32_t frame_q_mode_1 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode1; + + /* 0x108 : mjpeg_q_mode2 */ + union { + struct + { + uint32_t frame_q_mode_2 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode2; + + /* 0x10C : mjpeg_q_mode3 */ + union { + struct + { + uint32_t frame_q_mode_3 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode3; + + /* 0x110 : mjpeg_q_mode4 */ + union { + struct + { + uint32_t frame_q_mode_4 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode4; + + /* 0x114 : mjpeg_q_mode5 */ + union { + struct + { + uint32_t frame_q_mode_5 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode5; + + /* 0x118 : mjpeg_q_mode6 */ + union { + struct + { + uint32_t frame_q_mode_6 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode6; + + /* 0x11C : mjpeg_q_mode7 */ + union { + struct + { + uint32_t frame_q_mode_7 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode7; + + /* 0x120 : mjpeg_q_mode_8 */ + union { + struct + { + uint32_t frame_q_mode_8 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode_8; + + /* 0x124 : mjpeg_q_mode_9 */ + union { + struct + { + uint32_t frame_q_mode_9 : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode_9; + + /* 0x128 : mjpeg_q_mode_a */ + union { + struct + { + uint32_t frame_q_mode_a : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode_a; + + /* 0x12C : mjpeg_q_mode_b */ + union { + struct + { + uint32_t frame_q_mode_b : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode_b; + + /* 0x130 : mjpeg_q_mode_c */ + union { + struct + { + uint32_t frame_q_mode_c : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode_c; + + /* 0x134 : mjpeg_q_mode_d */ + union { + struct + { + uint32_t frame_q_mode_d : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode_d; + + /* 0x138 : mjpeg_q_mode_e */ + union { + struct + { + uint32_t frame_q_mode_e : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode_e; + + /* 0x13C : mjpeg_q_mode_f */ + union { + struct + { + uint32_t frame_q_mode_f : 7; /* [ 6: 0], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_q_mode_f; + + /* 0x140 reserved */ + uint8_t RESERVED0x140[176]; + + /* 0x1F0 : mjpeg_debug */ + union { + struct + { + uint32_t reg_mjpeg_dbg_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t reg_mjpeg_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_debug; + + /* 0x1f4 reserved */ + uint8_t RESERVED0x1f4[8]; + + /* 0x1FC : mjpeg_dummy_reg */ + union { + struct + { + uint32_t mjpeg_dummy_reg : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } mjpeg_dummy_reg; +}; + +typedef volatile struct mjpeg_reg mjpeg_reg_t; + +#endif /* __MJPEG_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pdm_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pdm_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..1da8106f184822bbdcf3355239085b27fdbaed5b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pdm_reg.h @@ -0,0 +1,351 @@ +/** + ****************************************************************************** + * @file pdm_reg.h + * @version V1.2 + * @date 2020-02-13 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PDM_REG_H__ +#define __PDM_REG_H__ + +#include "bl702.h" + +/* 0x0 : pdm_datapath_config */ +#define PDM_DATAPATH_CONFIG_OFFSET (0x0) +#define PDM_EN PDM_EN +#define PDM_EN_POS (0U) +#define PDM_EN_LEN (1U) +#define PDM_EN_MSK (((1U << PDM_EN_LEN) - 1) << PDM_EN_POS) +#define PDM_EN_UMSK (~(((1U << PDM_EN_LEN) - 1) << PDM_EN_POS)) +#define PDM_RX_SEL_128FS PDM_RX_SEL_128FS +#define PDM_RX_SEL_128FS_POS (2U) +#define PDM_RX_SEL_128FS_LEN (1U) +#define PDM_RX_SEL_128FS_MSK (((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS) +#define PDM_RX_SEL_128FS_UMSK (~(((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS)) +#define PDM_TX_SEL_128FS PDM_TX_SEL_128FS +#define PDM_TX_SEL_128FS_POS (3U) +#define PDM_TX_SEL_128FS_LEN (1U) +#define PDM_TX_SEL_128FS_MSK (((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS) +#define PDM_TX_SEL_128FS_UMSK (~(((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS)) +#define PDM_DC_MUL PDM_DC_MUL +#define PDM_DC_MUL_POS (4U) +#define PDM_DC_MUL_LEN (8U) +#define PDM_DC_MUL_MSK (((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS) +#define PDM_DC_MUL_UMSK (~(((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS)) +#define PDM_SCALE_SEL PDM_SCALE_SEL +#define PDM_SCALE_SEL_POS (12U) +#define PDM_SCALE_SEL_LEN (3U) +#define PDM_SCALE_SEL_MSK (((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS) +#define PDM_SCALE_SEL_UMSK (~(((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS)) +#define PDM_DITHER_SEL PDM_DITHER_SEL +#define PDM_DITHER_SEL_POS (16U) +#define PDM_DITHER_SEL_LEN (2U) +#define PDM_DITHER_SEL_MSK (((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS) +#define PDM_DITHER_SEL_UMSK (~(((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS)) +#define PDM_FORCE_LR PDM_FORCE_LR +#define PDM_FORCE_LR_POS (20U) +#define PDM_FORCE_LR_LEN (1U) +#define PDM_FORCE_LR_MSK (((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS) +#define PDM_FORCE_LR_UMSK (~(((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS)) +#define PDM_FORCE_SEL PDM_FORCE_SEL +#define PDM_FORCE_SEL_POS (21U) +#define PDM_FORCE_SEL_LEN (1U) +#define PDM_FORCE_SEL_MSK (((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS) +#define PDM_FORCE_SEL_UMSK (~(((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS)) +#define PDM_DSD_SWAP PDM_DSD_SWAP +#define PDM_DSD_SWAP_POS (22U) +#define PDM_DSD_SWAP_LEN (1U) +#define PDM_DSD_SWAP_MSK (((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS) +#define PDM_DSD_SWAP_UMSK (~(((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS)) +#define PDM_OUT_DAT_DLY PDM_OUT_DAT_DLY +#define PDM_OUT_DAT_DLY_POS (24U) +#define PDM_OUT_DAT_DLY_LEN (2U) +#define PDM_OUT_DAT_DLY_MSK (((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS) +#define PDM_OUT_DAT_DLY_UMSK (~(((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS)) +#define PDM_OUT_SEL_DLY PDM_OUT_SEL_DLY +#define PDM_OUT_SEL_DLY_POS (26U) +#define PDM_OUT_SEL_DLY_LEN (2U) +#define PDM_OUT_SEL_DLY_MSK (((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS) +#define PDM_OUT_SEL_DLY_UMSK (~(((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS)) +#define PDM_OUT_SEL_INV PDM_OUT_SEL_INV +#define PDM_OUT_SEL_INV_POS (28U) +#define PDM_OUT_SEL_INV_LEN (1U) +#define PDM_OUT_SEL_INV_MSK (((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS) +#define PDM_OUT_SEL_INV_UMSK (~(((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS)) + +/* 0x4 : pdm_dma_config */ +#define PDM_DMA_CONFIG_OFFSET (0x4) +#define PDM_DMA_RX_EN PDM_DMA_RX_EN +#define PDM_DMA_RX_EN_POS (0U) +#define PDM_DMA_RX_EN_LEN (1U) +#define PDM_DMA_RX_EN_MSK (((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS) +#define PDM_DMA_RX_EN_UMSK (~(((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS)) +#define PDM_RX_FORMAT PDM_RX_FORMAT +#define PDM_RX_FORMAT_POS (4U) +#define PDM_RX_FORMAT_LEN (3U) +#define PDM_RX_FORMAT_MSK (((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS) +#define PDM_RX_FORMAT_UMSK (~(((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS)) +#define PDM_DMA_TX_EN PDM_DMA_TX_EN +#define PDM_DMA_TX_EN_POS (8U) +#define PDM_DMA_TX_EN_LEN (1U) +#define PDM_DMA_TX_EN_MSK (((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS) +#define PDM_DMA_TX_EN_UMSK (~(((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS)) +#define PDM_TX_FORMAT PDM_TX_FORMAT +#define PDM_TX_FORMAT_POS (12U) +#define PDM_TX_FORMAT_LEN (3U) +#define PDM_TX_FORMAT_MSK (((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS) +#define PDM_TX_FORMAT_UMSK (~(((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS)) +#define PDM_TX_DATA_SHIFT PDM_TX_DATA_SHIFT +#define PDM_TX_DATA_SHIFT_POS (16U) +#define PDM_TX_DATA_SHIFT_LEN (5U) +#define PDM_TX_DATA_SHIFT_MSK (((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS) +#define PDM_TX_DATA_SHIFT_UMSK (~(((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS)) + +/* 0x8 : pdm_dma_wdata2 */ +#define PDM_DMA_WDATA2_OFFSET (0x8) +#define PDM_DMA_WDATA2 PDM_DMA_WDATA2 +#define PDM_DMA_WDATA2_POS (0U) +#define PDM_DMA_WDATA2_LEN (32U) +#define PDM_DMA_WDATA2_MSK (((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS) +#define PDM_DMA_WDATA2_UMSK (~(((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS)) + +/* 0x10 : pdm_dma_wdata */ +#define PDM_DMA_WDATA_OFFSET (0x10) +#define PDM_DMA_WDATA PDM_DMA_WDATA +#define PDM_DMA_WDATA_POS (0U) +#define PDM_DMA_WDATA_LEN (32U) +#define PDM_DMA_WDATA_MSK (((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS) +#define PDM_DMA_WDATA_UMSK (~(((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS)) + +/* 0x14 : pdm_dma_rdata */ +#define PDM_DMA_RDATA_OFFSET (0x14) +#define PDM_DMA_RDATA PDM_DMA_RDATA +#define PDM_DMA_RDATA_POS (0U) +#define PDM_DMA_RDATA_LEN (32U) +#define PDM_DMA_RDATA_MSK (((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS) +#define PDM_DMA_RDATA_UMSK (~(((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS)) + +/* 0x18 : pdm_tx_fifo_status */ +#define PDM_TX_FIFO_STATUS_OFFSET (0x18) +#define PDM_TX_FIFO_EMPTY PDM_TX_FIFO_EMPTY +#define PDM_TX_FIFO_EMPTY_POS (0U) +#define PDM_TX_FIFO_EMPTY_LEN (1U) +#define PDM_TX_FIFO_EMPTY_MSK (((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS) +#define PDM_TX_FIFO_EMPTY_UMSK (~(((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS)) +#define PDM_TX_FIFO_FULL PDM_TX_FIFO_FULL +#define PDM_TX_FIFO_FULL_POS (1U) +#define PDM_TX_FIFO_FULL_LEN (1U) +#define PDM_TX_FIFO_FULL_MSK (((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS) +#define PDM_TX_FIFO_FULL_UMSK (~(((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS)) +#define PDM_TX_CS PDM_TX_CS +#define PDM_TX_CS_POS (2U) +#define PDM_TX_CS_LEN (2U) +#define PDM_TX_CS_MSK (((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS) +#define PDM_TX_CS_UMSK (~(((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS)) +#define PDM_TXFIFORDPTR PDM_TXFIFORDPTR +#define PDM_TXFIFORDPTR_POS (4U) +#define PDM_TXFIFORDPTR_LEN (3U) +#define PDM_TXFIFORDPTR_MSK (((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS) +#define PDM_TXFIFORDPTR_UMSK (~(((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS)) +#define PDM_TXFIFOWRPTR PDM_TXFIFOWRPTR +#define PDM_TXFIFOWRPTR_POS (8U) +#define PDM_TXFIFOWRPTR_LEN (2U) +#define PDM_TXFIFOWRPTR_MSK (((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS) +#define PDM_TXFIFOWRPTR_UMSK (~(((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS)) +#define PDM_TX2_FIFO_EMPTY PDM_TX2_FIFO_EMPTY +#define PDM_TX2_FIFO_EMPTY_POS (16U) +#define PDM_TX2_FIFO_EMPTY_LEN (1U) +#define PDM_TX2_FIFO_EMPTY_MSK (((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS) +#define PDM_TX2_FIFO_EMPTY_UMSK (~(((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS)) +#define PDM_TX2_FIFO_FULL PDM_TX2_FIFO_FULL +#define PDM_TX2_FIFO_FULL_POS (17U) +#define PDM_TX2_FIFO_FULL_LEN (1U) +#define PDM_TX2_FIFO_FULL_MSK (((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS) +#define PDM_TX2_FIFO_FULL_UMSK (~(((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS)) +#define PDM_TX2_CS PDM_TX2_CS +#define PDM_TX2_CS_POS (18U) +#define PDM_TX2_CS_LEN (2U) +#define PDM_TX2_CS_MSK (((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS) +#define PDM_TX2_CS_UMSK (~(((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS)) +#define PDM_TX2FIFORDPTR PDM_TX2FIFORDPTR +#define PDM_TX2FIFORDPTR_POS (20U) +#define PDM_TX2FIFORDPTR_LEN (3U) +#define PDM_TX2FIFORDPTR_MSK (((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS) +#define PDM_TX2FIFORDPTR_UMSK (~(((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS)) +#define PDM_TX2FIFOWRPTR PDM_TX2FIFOWRPTR +#define PDM_TX2FIFOWRPTR_POS (24U) +#define PDM_TX2FIFOWRPTR_LEN (2U) +#define PDM_TX2FIFOWRPTR_MSK (((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS) +#define PDM_TX2FIFOWRPTR_UMSK (~(((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS)) + +/* 0x1C : pdm_rx_fifo_status */ +#define PDM_RX_FIFO_STATUS_OFFSET (0x1C) +#define PDM_RX_FIFO_EMPTY PDM_RX_FIFO_EMPTY +#define PDM_RX_FIFO_EMPTY_POS (0U) +#define PDM_RX_FIFO_EMPTY_LEN (1U) +#define PDM_RX_FIFO_EMPTY_MSK (((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS) +#define PDM_RX_FIFO_EMPTY_UMSK (~(((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS)) +#define PDM_RX_FIFO_FULL PDM_RX_FIFO_FULL +#define PDM_RX_FIFO_FULL_POS (1U) +#define PDM_RX_FIFO_FULL_LEN (1U) +#define PDM_RX_FIFO_FULL_MSK (((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS) +#define PDM_RX_FIFO_FULL_UMSK (~(((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS)) +#define PDM_RX_CS PDM_RX_CS +#define PDM_RX_CS_POS (2U) +#define PDM_RX_CS_LEN (2U) +#define PDM_RX_CS_MSK (((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS) +#define PDM_RX_CS_UMSK (~(((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS)) +#define PDM_RXFIFORDPTR PDM_RXFIFORDPTR +#define PDM_RXFIFORDPTR_POS (4U) +#define PDM_RXFIFORDPTR_LEN (2U) +#define PDM_RXFIFORDPTR_MSK (((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS) +#define PDM_RXFIFORDPTR_UMSK (~(((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS)) +#define PDM_RXFIFOWRPTR PDM_RXFIFOWRPTR +#define PDM_RXFIFOWRPTR_POS (8U) +#define PDM_RXFIFOWRPTR_LEN (3U) +#define PDM_RXFIFOWRPTR_MSK (((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS) +#define PDM_RXFIFOWRPTR_UMSK (~(((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS)) + +struct pdm_reg { + /* 0x0 : pdm_datapath_config */ + union { + struct + { + uint32_t pdm_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t rx_sel_128fs : 1; /* [ 2], r/w, 0x0 */ + uint32_t tx_sel_128fs : 1; /* [ 3], r/w, 0x0 */ + uint32_t dc_mul : 8; /* [11: 4], r/w, 0x64 */ + uint32_t scale_sel : 3; /* [14:12], r/w, 0x5 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t dither_sel : 2; /* [17:16], r/w, 0x1 */ + uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */ + uint32_t force_lr : 1; /* [ 20], r/w, 0x0 */ + uint32_t force_sel : 1; /* [ 21], r/w, 0x0 */ + uint32_t dsd_swap : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t out_dat_dly : 2; /* [25:24], r/w, 0x0 */ + uint32_t out_sel_dly : 2; /* [27:26], r/w, 0x0 */ + uint32_t out_sel_inv : 1; /* [ 28], r/w, 0x0 */ + uint32_t rsvd_31_29 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pdm_datapath_config; + + /* 0x4 : pdm_dma_config */ + union { + struct + { + uint32_t pdm_dma_rx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t rx_format : 3; /* [ 6: 4], r/w, 0x3 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t pdm_dma_tx_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t tx_format : 3; /* [14:12], r/w, 0x3 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t tx_data_shift : 5; /* [20:16], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pdm_dma_config; + + /* 0x8 : pdm_dma_wdata2 */ + union { + struct + { + uint32_t pdm_dma_wdata2 : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } pdm_dma_wdata2; + + /* 0xc reserved */ + uint8_t RESERVED0xc[4]; + + /* 0x10 : pdm_dma_wdata */ + union { + struct + { + uint32_t pdm_dma_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } pdm_dma_wdata; + + /* 0x14 : pdm_dma_rdata */ + union { + struct + { + uint32_t pdm_dma_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } pdm_dma_rdata; + + /* 0x18 : pdm_tx_fifo_status */ + union { + struct + { + uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */ + uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */ + uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */ + uint32_t TxFifoRdPtr : 3; /* [ 6: 4], r, 0x4 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t tx2_fifo_empty : 1; /* [ 16], r, 0x0 */ + uint32_t tx2_fifo_full : 1; /* [ 17], r, 0x0 */ + uint32_t tx2_cs : 2; /* [19:18], r, 0x0 */ + uint32_t Tx2FifoRdPtr : 3; /* [22:20], r, 0x4 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t Tx2FifoWrPtr : 2; /* [25:24], r, 0x0 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pdm_tx_fifo_status; + + /* 0x1C : pdm_rx_fifo_status */ + union { + struct + { + uint32_t rx_fifo_empty : 1; /* [ 0], r, 0x1 */ + uint32_t rx_fifo_full : 1; /* [ 1], r, 0x0 */ + uint32_t rx_cs : 2; /* [ 3: 2], r, 0x0 */ + uint32_t RxFifoRdPtr : 2; /* [ 5: 4], r, 0x3 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t RxFifoWrPtr : 3; /* [10: 8], r, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pdm_rx_fifo_status; +}; + +typedef volatile struct pdm_reg pdm_reg_t; + +#endif /* __PDM_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pds_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pds_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..9b2a0d6261759ace4de09c30c7647374b52ad709 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pds_reg.h @@ -0,0 +1,1411 @@ +/** + ****************************************************************************** + * @file pds_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PDS_REG_H__ +#define __PDS_REG_H__ + +#include "bl702.h" + +/* 0x0 : PDS_CTL */ +#define PDS_CTL_OFFSET (0x0) +#define PDS_START_PS PDS_START_PS +#define PDS_START_PS_POS (0U) +#define PDS_START_PS_LEN (1U) +#define PDS_START_PS_MSK (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS) +#define PDS_START_PS_UMSK (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)) +#define PDS_CR_SLEEP_FOREVER PDS_CR_SLEEP_FOREVER +#define PDS_CR_SLEEP_FOREVER_POS (1U) +#define PDS_CR_SLEEP_FOREVER_LEN (1U) +#define PDS_CR_SLEEP_FOREVER_MSK (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS) +#define PDS_CR_SLEEP_FOREVER_UMSK (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)) +#define PDS_CR_XTAL_FORCE_OFF PDS_CR_XTAL_FORCE_OFF +#define PDS_CR_XTAL_FORCE_OFF_POS (2U) +#define PDS_CR_XTAL_FORCE_OFF_LEN (1U) +#define PDS_CR_XTAL_FORCE_OFF_MSK (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS) +#define PDS_CR_XTAL_FORCE_OFF_UMSK (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)) +#define PDS_CR_WIFI_PDS_SAVE_STATE PDS_CR_WIFI_PDS_SAVE_STATE +#define PDS_CR_WIFI_PDS_SAVE_STATE_POS (3U) +#define PDS_CR_WIFI_PDS_SAVE_STATE_LEN (1U) +#define PDS_CR_WIFI_PDS_SAVE_STATE_MSK (((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS) +#define PDS_CR_WIFI_PDS_SAVE_STATE_UMSK (~(((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS)) +#define PDS_CR_PDS_PD_DCDC18 PDS_CR_PDS_PD_DCDC18 +#define PDS_CR_PDS_PD_DCDC18_POS (4U) +#define PDS_CR_PDS_PD_DCDC18_LEN (1U) +#define PDS_CR_PDS_PD_DCDC18_MSK (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS) +#define PDS_CR_PDS_PD_DCDC18_UMSK (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)) +#define PDS_CR_PDS_PD_BG_SYS PDS_CR_PDS_PD_BG_SYS +#define PDS_CR_PDS_PD_BG_SYS_POS (5U) +#define PDS_CR_PDS_PD_BG_SYS_LEN (1U) +#define PDS_CR_PDS_PD_BG_SYS_MSK (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS) +#define PDS_CR_PDS_PD_BG_SYS_UMSK (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)) +#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD PDS_CR_PDS_CTRL_GPIO_IE_PU_PD +#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS (6U) +#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN (1U) +#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_MSK (((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS) +#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS)) +#define PDS_CR_PDS_CTRL_PU_FLASH PDS_CR_PDS_CTRL_PU_FLASH +#define PDS_CR_PDS_CTRL_PU_FLASH_POS (7U) +#define PDS_CR_PDS_CTRL_PU_FLASH_LEN (1U) +#define PDS_CR_PDS_CTRL_PU_FLASH_MSK (((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS) +#define PDS_CR_PDS_CTRL_PU_FLASH_UMSK (~(((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS)) +#define PDS_CR_PDS_GATE_CLK PDS_CR_PDS_GATE_CLK +#define PDS_CR_PDS_GATE_CLK_POS (8U) +#define PDS_CR_PDS_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_GATE_CLK_MSK (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS) +#define PDS_CR_PDS_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)) +#define PDS_CR_PDS_MEM_STBY PDS_CR_PDS_MEM_STBY +#define PDS_CR_PDS_MEM_STBY_POS (9U) +#define PDS_CR_PDS_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_MEM_STBY_MSK (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS) +#define PDS_CR_PDS_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)) +#define PDS_CR_SW_PU_FLASH PDS_CR_SW_PU_FLASH +#define PDS_CR_SW_PU_FLASH_POS (10U) +#define PDS_CR_SW_PU_FLASH_LEN (1U) +#define PDS_CR_SW_PU_FLASH_MSK (((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS) +#define PDS_CR_SW_PU_FLASH_UMSK (~(((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS)) +#define PDS_CR_PDS_ISO_EN PDS_CR_PDS_ISO_EN +#define PDS_CR_PDS_ISO_EN_POS (11U) +#define PDS_CR_PDS_ISO_EN_LEN (1U) +#define PDS_CR_PDS_ISO_EN_MSK (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS) +#define PDS_CR_PDS_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)) +#define PDS_CR_PDS_WAIT_XTAL_RDY PDS_CR_PDS_WAIT_XTAL_RDY +#define PDS_CR_PDS_WAIT_XTAL_RDY_POS (12U) +#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN (1U) +#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS) +#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)) +#define PDS_CR_PDS_PWR_OFF PDS_CR_PDS_PWR_OFF +#define PDS_CR_PDS_PWR_OFF_POS (13U) +#define PDS_CR_PDS_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_PWR_OFF_MSK (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS) +#define PDS_CR_PDS_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)) +#define PDS_CR_PDS_PD_XTAL PDS_CR_PDS_PD_XTAL +#define PDS_CR_PDS_PD_XTAL_POS (14U) +#define PDS_CR_PDS_PD_XTAL_LEN (1U) +#define PDS_CR_PDS_PD_XTAL_MSK (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS) +#define PDS_CR_PDS_PD_XTAL_UMSK (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON PDS_CR_PDS_SOC_ENB_FORCE_ON +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_POS (15U) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN (1U) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_MSK (((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_UMSK (~(((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS)) +#define PDS_CR_PDS_RST_SOC_EN PDS_CR_PDS_RST_SOC_EN +#define PDS_CR_PDS_RST_SOC_EN_POS (16U) +#define PDS_CR_PDS_RST_SOC_EN_LEN (1U) +#define PDS_CR_PDS_RST_SOC_EN_MSK (((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS) +#define PDS_CR_PDS_RST_SOC_EN_UMSK (~(((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS)) +#define PDS_CR_PDS_RC32M_OFF_DIS PDS_CR_PDS_RC32M_OFF_DIS +#define PDS_CR_PDS_RC32M_OFF_DIS_POS (17U) +#define PDS_CR_PDS_RC32M_OFF_DIS_LEN (1U) +#define PDS_CR_PDS_RC32M_OFF_DIS_MSK (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS) +#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)) +#define PDS_CR_PDS_LDO_VSEL_EN PDS_CR_PDS_LDO_VSEL_EN +#define PDS_CR_PDS_LDO_VSEL_EN_POS (18U) +#define PDS_CR_PDS_LDO_VSEL_EN_LEN (1U) +#define PDS_CR_PDS_LDO_VSEL_EN_MSK (((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS) +#define PDS_CR_PDS_LDO_VSEL_EN_UMSK (~(((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS)) +#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN PDS_CR_PDS_RAM_LP_WITH_CLK_EN +#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS (19U) +#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN (1U) +#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_MSK (((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS) +#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_UMSK (~(((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS)) +#define PDS_CR_NP_WFI_MASK PDS_CR_NP_WFI_MASK +#define PDS_CR_NP_WFI_MASK_POS (21U) +#define PDS_CR_NP_WFI_MASK_LEN (1U) +#define PDS_CR_NP_WFI_MASK_MSK (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS) +#define PDS_CR_NP_WFI_MASK_UMSK (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)) +#define PDS_CR_PDS_PD_LDO11 PDS_CR_PDS_PD_LDO11 +#define PDS_CR_PDS_PD_LDO11_POS (22U) +#define PDS_CR_PDS_PD_LDO11_LEN (1U) +#define PDS_CR_PDS_PD_LDO11_MSK (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS) +#define PDS_CR_PDS_PD_LDO11_UMSK (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)) +#define PDS_CR_PDS_FORCE_RAM_CLK_EN PDS_CR_PDS_FORCE_RAM_CLK_EN +#define PDS_CR_PDS_FORCE_RAM_CLK_EN_POS (23U) +#define PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_RAM_CLK_EN_MSK (((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS) +#define PDS_CR_PDS_FORCE_RAM_CLK_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS)) +#define PDS_CR_PDS_LDO_VOL PDS_CR_PDS_LDO_VOL +#define PDS_CR_PDS_LDO_VOL_POS (24U) +#define PDS_CR_PDS_LDO_VOL_LEN (4U) +#define PDS_CR_PDS_LDO_VOL_MSK (((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS) +#define PDS_CR_PDS_LDO_VOL_UMSK (~(((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS)) +#define PDS_CR_PDS_CTRL_RF PDS_CR_PDS_CTRL_RF +#define PDS_CR_PDS_CTRL_RF_POS (28U) +#define PDS_CR_PDS_CTRL_RF_LEN (2U) +#define PDS_CR_PDS_CTRL_RF_MSK (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS) +#define PDS_CR_PDS_CTRL_RF_UMSK (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)) +#define PDS_CR_PDS_CTRL_PLL PDS_CR_PDS_CTRL_PLL +#define PDS_CR_PDS_CTRL_PLL_POS (30U) +#define PDS_CR_PDS_CTRL_PLL_LEN (2U) +#define PDS_CR_PDS_CTRL_PLL_MSK (((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS) +#define PDS_CR_PDS_CTRL_PLL_UMSK (~(((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS)) + +/* 0x4 : PDS_TIME1 */ +#define PDS_TIME1_OFFSET (0x4) +#define PDS_CR_SLEEP_DURATION PDS_CR_SLEEP_DURATION +#define PDS_CR_SLEEP_DURATION_POS (0U) +#define PDS_CR_SLEEP_DURATION_LEN (32U) +#define PDS_CR_SLEEP_DURATION_MSK (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS) +#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)) + +/* 0xC : PDS_INT */ +#define PDS_INT_OFFSET (0xC) +#define PDS_RO_PDS_WAKE_INT PDS_RO_PDS_WAKE_INT +#define PDS_RO_PDS_WAKE_INT_POS (0U) +#define PDS_RO_PDS_WAKE_INT_LEN (1U) +#define PDS_RO_PDS_WAKE_INT_MSK (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS) +#define PDS_RO_PDS_WAKE_INT_UMSK (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)) +#define PDS_RO_PDS_RF_DONE_INT PDS_RO_PDS_RF_DONE_INT +#define PDS_RO_PDS_RF_DONE_INT_POS (2U) +#define PDS_RO_PDS_RF_DONE_INT_LEN (1U) +#define PDS_RO_PDS_RF_DONE_INT_MSK (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS) +#define PDS_RO_PDS_RF_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)) +#define PDS_RO_PDS_PLL_DONE_INT PDS_RO_PDS_PLL_DONE_INT +#define PDS_RO_PDS_PLL_DONE_INT_POS (3U) +#define PDS_RO_PDS_PLL_DONE_INT_LEN (1U) +#define PDS_RO_PDS_PLL_DONE_INT_MSK (((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS) +#define PDS_RO_PDS_PLL_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS)) +#define PDS_RESET_EVENT PDS_RESET_EVENT +#define PDS_RESET_EVENT_POS (4U) +#define PDS_RESET_EVENT_LEN (3U) +#define PDS_RESET_EVENT_MSK (((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS) +#define PDS_RESET_EVENT_UMSK (~(((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS)) +#define PDS_CLR_RESET_EVENT PDS_CLR_RESET_EVENT +#define PDS_CLR_RESET_EVENT_POS (7U) +#define PDS_CLR_RESET_EVENT_LEN (1U) +#define PDS_CLR_RESET_EVENT_MSK (((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS) +#define PDS_CLR_RESET_EVENT_UMSK (~(((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS)) +#define PDS_CR_PDS_WAKE_INT_MASK PDS_CR_PDS_WAKE_INT_MASK +#define PDS_CR_PDS_WAKE_INT_MASK_POS (8U) +#define PDS_CR_PDS_WAKE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_WAKE_INT_MASK_MSK (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS) +#define PDS_CR_PDS_WAKE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)) +#define PDS_CR_PDS_RF_DONE_INT_MASK PDS_CR_PDS_RF_DONE_INT_MASK +#define PDS_CR_PDS_RF_DONE_INT_MASK_POS (10U) +#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS) +#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)) +#define PDS_CR_PDS_PLL_DONE_INT_MASK PDS_CR_PDS_PLL_DONE_INT_MASK +#define PDS_CR_PDS_PLL_DONE_INT_MASK_POS (11U) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS)) +#define PDS_CR_PDS_INT_CLR PDS_CR_PDS_INT_CLR +#define PDS_CR_PDS_INT_CLR_POS (15U) +#define PDS_CR_PDS_INT_CLR_LEN (1U) +#define PDS_CR_PDS_INT_CLR_MSK (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS) +#define PDS_CR_PDS_INT_CLR_UMSK (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)) +#define PDS_CR_PDS_WAKEUP_SRC_EN PDS_CR_PDS_WAKEUP_SRC_EN +#define PDS_CR_PDS_WAKEUP_SRC_EN_POS (16U) +#define PDS_CR_PDS_WAKEUP_SRC_EN_LEN (8U) +#define PDS_CR_PDS_WAKEUP_SRC_EN_MSK (((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS) +#define PDS_CR_PDS_WAKEUP_SRC_EN_UMSK (~(((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS)) +#define PDS_RO_PDS_WAKEUP_EVENT PDS_RO_PDS_WAKEUP_EVENT +#define PDS_RO_PDS_WAKEUP_EVENT_POS (24U) +#define PDS_RO_PDS_WAKEUP_EVENT_LEN (8U) +#define PDS_RO_PDS_WAKEUP_EVENT_MSK (((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS) +#define PDS_RO_PDS_WAKEUP_EVENT_UMSK (~(((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS)) + +/* 0x10 : PDS_CTL2 */ +#define PDS_CTL2_OFFSET (0x10) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF PDS_CR_PDS_FORCE_NP_PWR_OFF +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS (0U) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_BZ_PWR_OFF PDS_CR_PDS_FORCE_BZ_PWR_OFF +#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS (2U) +#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_USB_PWR_OFF PDS_CR_PDS_FORCE_USB_PWR_OFF +#define PDS_CR_PDS_FORCE_USB_PWR_OFF_POS (3U) +#define PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_USB_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_USB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_NP_ISO_EN PDS_CR_PDS_FORCE_NP_ISO_EN +#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS (4U) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_BZ_ISO_EN PDS_CR_PDS_FORCE_BZ_ISO_EN +#define PDS_CR_PDS_FORCE_BZ_ISO_EN_POS (6U) +#define PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_BZ_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_BZ_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_USB_ISO_EN PDS_CR_PDS_FORCE_USB_ISO_EN +#define PDS_CR_PDS_FORCE_USB_ISO_EN_POS (7U) +#define PDS_CR_PDS_FORCE_USB_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_USB_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_USB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_NP_PDS_RST PDS_CR_PDS_FORCE_NP_PDS_RST +#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS (8U) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_BZ_PDS_RST PDS_CR_PDS_FORCE_BZ_PDS_RST +#define PDS_CR_PDS_FORCE_BZ_PDS_RST_POS (10U) +#define PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_BZ_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_BZ_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_USB_PDS_RST PDS_CR_PDS_FORCE_USB_PDS_RST +#define PDS_CR_PDS_FORCE_USB_PDS_RST_POS (11U) +#define PDS_CR_PDS_FORCE_USB_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_USB_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_USB_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY PDS_CR_PDS_FORCE_NP_MEM_STBY +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS (12U) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_BZ_MEM_STBY PDS_CR_PDS_FORCE_BZ_MEM_STBY +#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS (14U) +#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_USB_MEM_STBY PDS_CR_PDS_FORCE_USB_MEM_STBY +#define PDS_CR_PDS_FORCE_USB_MEM_STBY_POS (15U) +#define PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_USB_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK PDS_CR_PDS_FORCE_NP_GATE_CLK +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS (16U) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)) +#define PDS_CR_PDS_FORCE_BZ_GATE_CLK PDS_CR_PDS_FORCE_BZ_GATE_CLK +#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS (18U) +#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS)) +#define PDS_CR_PDS_FORCE_USB_GATE_CLK PDS_CR_PDS_FORCE_USB_GATE_CLK +#define PDS_CR_PDS_FORCE_USB_GATE_CLK_POS (19U) +#define PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_USB_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS)) + +/* 0x14 : PDS_CTL3 */ +#define PDS_CTL3_OFFSET (0x14) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF PDS_CR_PDS_FORCE_MISC_PWR_OFF +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS (1U) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_BLE_PWR_OFF PDS_CR_PDS_FORCE_BLE_PWR_OFF +#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS (2U) +#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_BLE_ISO_EN PDS_CR_PDS_FORCE_BLE_ISO_EN +#define PDS_CR_PDS_FORCE_BLE_ISO_EN_POS (5U) +#define PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_BLE_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_BLE_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST PDS_CR_PDS_FORCE_MISC_PDS_RST +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS (7U) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_BLE_PDS_RST PDS_CR_PDS_FORCE_BLE_PDS_RST +#define PDS_CR_PDS_FORCE_BLE_PDS_RST_POS (8U) +#define PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_BLE_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_BLE_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY PDS_CR_PDS_FORCE_MISC_MEM_STBY +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS (10U) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_BLE_MEM_STBY PDS_CR_PDS_FORCE_BLE_MEM_STBY +#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS (11U) +#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK PDS_CR_PDS_FORCE_MISC_GATE_CLK +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS (13U) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)) +#define PDS_CR_PDS_FORCE_BLE_GATE_CLK PDS_CR_PDS_FORCE_BLE_GATE_CLK +#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS (14U) +#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS)) +#define PDS_CR_PDS_NP_ISO_EN PDS_CR_PDS_NP_ISO_EN +#define PDS_CR_PDS_NP_ISO_EN_POS (24U) +#define PDS_CR_PDS_NP_ISO_EN_LEN (1U) +#define PDS_CR_PDS_NP_ISO_EN_MSK (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS) +#define PDS_CR_PDS_NP_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)) +#define PDS_CR_PDS_BZ_ISO_EN PDS_CR_PDS_BZ_ISO_EN +#define PDS_CR_PDS_BZ_ISO_EN_POS (27U) +#define PDS_CR_PDS_BZ_ISO_EN_LEN (1U) +#define PDS_CR_PDS_BZ_ISO_EN_MSK (((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS) +#define PDS_CR_PDS_BZ_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS)) +#define PDS_CR_PDS_BLE_ISO_EN PDS_CR_PDS_BLE_ISO_EN +#define PDS_CR_PDS_BLE_ISO_EN_POS (28U) +#define PDS_CR_PDS_BLE_ISO_EN_LEN (1U) +#define PDS_CR_PDS_BLE_ISO_EN_MSK (((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS) +#define PDS_CR_PDS_BLE_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS)) +#define PDS_CR_PDS_USB_ISO_EN PDS_CR_PDS_USB_ISO_EN +#define PDS_CR_PDS_USB_ISO_EN_POS (29U) +#define PDS_CR_PDS_USB_ISO_EN_LEN (1U) +#define PDS_CR_PDS_USB_ISO_EN_MSK (((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS) +#define PDS_CR_PDS_USB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS)) +#define PDS_CR_PDS_MISC_ISO_EN PDS_CR_PDS_MISC_ISO_EN +#define PDS_CR_PDS_MISC_ISO_EN_POS (30U) +#define PDS_CR_PDS_MISC_ISO_EN_LEN (1U) +#define PDS_CR_PDS_MISC_ISO_EN_MSK (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS) +#define PDS_CR_PDS_MISC_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)) + +/* 0x18 : PDS_CTL4 */ +#define PDS_CTL4_OFFSET (0x18) +#define PDS_CR_PDS_NP_PWR_OFF PDS_CR_PDS_NP_PWR_OFF +#define PDS_CR_PDS_NP_PWR_OFF_POS (0U) +#define PDS_CR_PDS_NP_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_NP_PWR_OFF_MSK (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS) +#define PDS_CR_PDS_NP_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)) +#define PDS_CR_PDS_NP_RESET PDS_CR_PDS_NP_RESET +#define PDS_CR_PDS_NP_RESET_POS (1U) +#define PDS_CR_PDS_NP_RESET_LEN (1U) +#define PDS_CR_PDS_NP_RESET_MSK (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS) +#define PDS_CR_PDS_NP_RESET_UMSK (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)) +#define PDS_CR_PDS_NP_MEM_STBY PDS_CR_PDS_NP_MEM_STBY +#define PDS_CR_PDS_NP_MEM_STBY_POS (2U) +#define PDS_CR_PDS_NP_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS) +#define PDS_CR_PDS_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)) +#define PDS_CR_PDS_NP_GATE_CLK PDS_CR_PDS_NP_GATE_CLK +#define PDS_CR_PDS_NP_GATE_CLK_POS (3U) +#define PDS_CR_PDS_NP_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS) +#define PDS_CR_PDS_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)) +#define PDS_CR_PDS_BZ_PWR_OFF PDS_CR_PDS_BZ_PWR_OFF +#define PDS_CR_PDS_BZ_PWR_OFF_POS (12U) +#define PDS_CR_PDS_BZ_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_BZ_PWR_OFF_MSK (((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS) +#define PDS_CR_PDS_BZ_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS)) +#define PDS_CR_PDS_BZ_RESET PDS_CR_PDS_BZ_RESET +#define PDS_CR_PDS_BZ_RESET_POS (13U) +#define PDS_CR_PDS_BZ_RESET_LEN (1U) +#define PDS_CR_PDS_BZ_RESET_MSK (((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS) +#define PDS_CR_PDS_BZ_RESET_UMSK (~(((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS)) +#define PDS_CR_PDS_BZ_MEM_STBY PDS_CR_PDS_BZ_MEM_STBY +#define PDS_CR_PDS_BZ_MEM_STBY_POS (14U) +#define PDS_CR_PDS_BZ_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_BZ_MEM_STBY_MSK (((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS) +#define PDS_CR_PDS_BZ_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS)) +#define PDS_CR_PDS_BZ_GATE_CLK PDS_CR_PDS_BZ_GATE_CLK +#define PDS_CR_PDS_BZ_GATE_CLK_POS (15U) +#define PDS_CR_PDS_BZ_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_BZ_GATE_CLK_MSK (((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS) +#define PDS_CR_PDS_BZ_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS)) +#define PDS_CR_PDS_BLE_PWR_OFF PDS_CR_PDS_BLE_PWR_OFF +#define PDS_CR_PDS_BLE_PWR_OFF_POS (16U) +#define PDS_CR_PDS_BLE_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_BLE_PWR_OFF_MSK (((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS) +#define PDS_CR_PDS_BLE_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS)) +#define PDS_CR_PDS_BLE_RESET PDS_CR_PDS_BLE_RESET +#define PDS_CR_PDS_BLE_RESET_POS (17U) +#define PDS_CR_PDS_BLE_RESET_LEN (1U) +#define PDS_CR_PDS_BLE_RESET_MSK (((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS) +#define PDS_CR_PDS_BLE_RESET_UMSK (~(((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS)) +#define PDS_CR_PDS_BLE_MEM_STBY PDS_CR_PDS_BLE_MEM_STBY +#define PDS_CR_PDS_BLE_MEM_STBY_POS (18U) +#define PDS_CR_PDS_BLE_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_BLE_MEM_STBY_MSK (((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS) +#define PDS_CR_PDS_BLE_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS)) +#define PDS_CR_PDS_BLE_GATE_CLK PDS_CR_PDS_BLE_GATE_CLK +#define PDS_CR_PDS_BLE_GATE_CLK_POS (19U) +#define PDS_CR_PDS_BLE_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_BLE_GATE_CLK_MSK (((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS) +#define PDS_CR_PDS_BLE_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS)) +#define PDS_CR_PDS_USB_PWR_OFF PDS_CR_PDS_USB_PWR_OFF +#define PDS_CR_PDS_USB_PWR_OFF_POS (20U) +#define PDS_CR_PDS_USB_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_USB_PWR_OFF_MSK (((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS) +#define PDS_CR_PDS_USB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS)) +#define PDS_CR_PDS_USB_RESET PDS_CR_PDS_USB_RESET +#define PDS_CR_PDS_USB_RESET_POS (21U) +#define PDS_CR_PDS_USB_RESET_LEN (1U) +#define PDS_CR_PDS_USB_RESET_MSK (((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS) +#define PDS_CR_PDS_USB_RESET_UMSK (~(((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS)) +#define PDS_CR_PDS_USB_MEM_STBY PDS_CR_PDS_USB_MEM_STBY +#define PDS_CR_PDS_USB_MEM_STBY_POS (22U) +#define PDS_CR_PDS_USB_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_USB_MEM_STBY_MSK (((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS) +#define PDS_CR_PDS_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS)) +#define PDS_CR_PDS_USB_GATE_CLK PDS_CR_PDS_USB_GATE_CLK +#define PDS_CR_PDS_USB_GATE_CLK_POS (23U) +#define PDS_CR_PDS_USB_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_USB_GATE_CLK_MSK (((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS) +#define PDS_CR_PDS_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS)) +#define PDS_CR_PDS_MISC_PWR_OFF PDS_CR_PDS_MISC_PWR_OFF +#define PDS_CR_PDS_MISC_PWR_OFF_POS (24U) +#define PDS_CR_PDS_MISC_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS) +#define PDS_CR_PDS_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)) +#define PDS_CR_PDS_MISC_RESET PDS_CR_PDS_MISC_RESET +#define PDS_CR_PDS_MISC_RESET_POS (25U) +#define PDS_CR_PDS_MISC_RESET_LEN (1U) +#define PDS_CR_PDS_MISC_RESET_MSK (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS) +#define PDS_CR_PDS_MISC_RESET_UMSK (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)) +#define PDS_CR_PDS_MISC_MEM_STBY PDS_CR_PDS_MISC_MEM_STBY +#define PDS_CR_PDS_MISC_MEM_STBY_POS (26U) +#define PDS_CR_PDS_MISC_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS) +#define PDS_CR_PDS_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)) +#define PDS_CR_PDS_MISC_GATE_CLK PDS_CR_PDS_MISC_GATE_CLK +#define PDS_CR_PDS_MISC_GATE_CLK_POS (27U) +#define PDS_CR_PDS_MISC_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS) +#define PDS_CR_PDS_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)) +#define PDS_CR_PDS_MISC_ANA_PWR_OFF PDS_CR_PDS_MISC_ANA_PWR_OFF +#define PDS_CR_PDS_MISC_ANA_PWR_OFF_POS (30U) +#define PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_MISC_ANA_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS) +#define PDS_CR_PDS_MISC_ANA_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS)) +#define PDS_CR_PDS_MISC_DIG_PWR_OFF PDS_CR_PDS_MISC_DIG_PWR_OFF +#define PDS_CR_PDS_MISC_DIG_PWR_OFF_POS (31U) +#define PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_MISC_DIG_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS) +#define PDS_CR_PDS_MISC_DIG_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS)) + +/* 0x1C : pds_stat */ +#define PDS_STAT_OFFSET (0x1C) +#define PDS_RO_PDS_STATE PDS_RO_PDS_STATE +#define PDS_RO_PDS_STATE_POS (0U) +#define PDS_RO_PDS_STATE_LEN (4U) +#define PDS_RO_PDS_STATE_MSK (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS) +#define PDS_RO_PDS_STATE_UMSK (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)) +#define PDS_RO_PDS_RF_STATE PDS_RO_PDS_RF_STATE +#define PDS_RO_PDS_RF_STATE_POS (8U) +#define PDS_RO_PDS_RF_STATE_LEN (4U) +#define PDS_RO_PDS_RF_STATE_MSK (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS) +#define PDS_RO_PDS_RF_STATE_UMSK (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)) +#define PDS_RO_PDS_PLL_STATE PDS_RO_PDS_PLL_STATE +#define PDS_RO_PDS_PLL_STATE_POS (16U) +#define PDS_RO_PDS_PLL_STATE_LEN (2U) +#define PDS_RO_PDS_PLL_STATE_MSK (((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS) +#define PDS_RO_PDS_PLL_STATE_UMSK (~(((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS)) + +/* 0x20 : pds_ram1 */ +#define PDS_RAM1_OFFSET (0x20) +#define PDS_CR_PDS_RAM_RET1N PDS_CR_PDS_RAM_RET1N +#define PDS_CR_PDS_RAM_RET1N_POS (0U) +#define PDS_CR_PDS_RAM_RET1N_LEN (4U) +#define PDS_CR_PDS_RAM_RET1N_MSK (((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS) +#define PDS_CR_PDS_RAM_RET1N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS)) +#define PDS_CR_PDS_RAM_RET2N PDS_CR_PDS_RAM_RET2N +#define PDS_CR_PDS_RAM_RET2N_POS (4U) +#define PDS_CR_PDS_RAM_RET2N_LEN (4U) +#define PDS_CR_PDS_RAM_RET2N_MSK (((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS) +#define PDS_CR_PDS_RAM_RET2N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS)) +#define PDS_CR_PDS_RAM_PGEN PDS_CR_PDS_RAM_PGEN +#define PDS_CR_PDS_RAM_PGEN_POS (8U) +#define PDS_CR_PDS_RAM_PGEN_LEN (4U) +#define PDS_CR_PDS_RAM_PGEN_MSK (((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS) +#define PDS_CR_PDS_RAM_PGEN_UMSK (~(((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS)) + +/* 0x30 : pds_gpio_set_pu_pd */ +#define PDS_GPIO_SET_PU_PD_OFFSET (0x30) +#define PDS_CR_PDS_GPIO_22_17_PD PDS_CR_PDS_GPIO_22_17_PD +#define PDS_CR_PDS_GPIO_22_17_PD_POS (0U) +#define PDS_CR_PDS_GPIO_22_17_PD_LEN (6U) +#define PDS_CR_PDS_GPIO_22_17_PD_MSK (((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS) +#define PDS_CR_PDS_GPIO_22_17_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS)) +#define PDS_CR_PDS_GPIO_22_17_PU PDS_CR_PDS_GPIO_22_17_PU +#define PDS_CR_PDS_GPIO_22_17_PU_POS (8U) +#define PDS_CR_PDS_GPIO_22_17_PU_LEN (6U) +#define PDS_CR_PDS_GPIO_22_17_PU_MSK (((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS) +#define PDS_CR_PDS_GPIO_22_17_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS)) +#define PDS_CR_PDS_GPIO_28_23_PD PDS_CR_PDS_GPIO_28_23_PD +#define PDS_CR_PDS_GPIO_28_23_PD_POS (16U) +#define PDS_CR_PDS_GPIO_28_23_PD_LEN (6U) +#define PDS_CR_PDS_GPIO_28_23_PD_MSK (((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS) +#define PDS_CR_PDS_GPIO_28_23_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS)) +#define PDS_CR_PDS_GPIO_28_23_PU PDS_CR_PDS_GPIO_28_23_PU +#define PDS_CR_PDS_GPIO_28_23_PU_POS (24U) +#define PDS_CR_PDS_GPIO_28_23_PU_LEN (6U) +#define PDS_CR_PDS_GPIO_28_23_PU_MSK (((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS) +#define PDS_CR_PDS_GPIO_28_23_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS)) + +/* 0x40 : pds_gpio_int */ +#define PDS_GPIO_INT_OFFSET (0x40) +#define PDS_GPIO_INT_MASK PDS_GPIO_INT_MASK +#define PDS_GPIO_INT_MASK_POS (0U) +#define PDS_GPIO_INT_MASK_LEN (1U) +#define PDS_GPIO_INT_MASK_MSK (((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS) +#define PDS_GPIO_INT_MASK_UMSK (~(((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS)) +#define PDS_GPIO_INT_STAT PDS_GPIO_INT_STAT +#define PDS_GPIO_INT_STAT_POS (1U) +#define PDS_GPIO_INT_STAT_LEN (1U) +#define PDS_GPIO_INT_STAT_MSK (((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS) +#define PDS_GPIO_INT_STAT_UMSK (~(((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS)) +#define PDS_GPIO_INT_CLR PDS_GPIO_INT_CLR +#define PDS_GPIO_INT_CLR_POS (2U) +#define PDS_GPIO_INT_CLR_LEN (1U) +#define PDS_GPIO_INT_CLR_MSK (((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS) +#define PDS_GPIO_INT_CLR_UMSK (~(((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS)) +#define PDS_GPIO_INT_MODE PDS_GPIO_INT_MODE +#define PDS_GPIO_INT_MODE_POS (4U) +#define PDS_GPIO_INT_MODE_LEN (3U) +#define PDS_GPIO_INT_MODE_MSK (((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS) +#define PDS_GPIO_INT_MODE_UMSK (~(((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS)) +#define PDS_GPIO_INT_SELECT PDS_GPIO_INT_SELECT +#define PDS_GPIO_INT_SELECT_POS (8U) +#define PDS_GPIO_INT_SELECT_LEN (3U) +#define PDS_GPIO_INT_SELECT_MSK (((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS) +#define PDS_GPIO_INT_SELECT_UMSK (~(((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS)) + +/* 0x300 : rc32m_ctrl0 */ +#define PDS_RC32M_CTRL0_OFFSET (0x300) +#define PDS_RC32M_CAL_DONE PDS_RC32M_CAL_DONE +#define PDS_RC32M_CAL_DONE_POS (0U) +#define PDS_RC32M_CAL_DONE_LEN (1U) +#define PDS_RC32M_CAL_DONE_MSK (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS) +#define PDS_RC32M_CAL_DONE_UMSK (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)) +#define PDS_RC32M_RDY PDS_RC32M_RDY +#define PDS_RC32M_RDY_POS (1U) +#define PDS_RC32M_RDY_LEN (1U) +#define PDS_RC32M_RDY_MSK (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS) +#define PDS_RC32M_RDY_UMSK (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)) +#define PDS_RC32M_CAL_INPROGRESS PDS_RC32M_CAL_INPROGRESS +#define PDS_RC32M_CAL_INPROGRESS_POS (2U) +#define PDS_RC32M_CAL_INPROGRESS_LEN (1U) +#define PDS_RC32M_CAL_INPROGRESS_MSK (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS) +#define PDS_RC32M_CAL_INPROGRESS_UMSK (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)) +#define PDS_RC32M_CAL_DIV PDS_RC32M_CAL_DIV +#define PDS_RC32M_CAL_DIV_POS (3U) +#define PDS_RC32M_CAL_DIV_LEN (2U) +#define PDS_RC32M_CAL_DIV_MSK (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS) +#define PDS_RC32M_CAL_DIV_UMSK (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)) +#define PDS_RC32M_CAL_PRECHARGE PDS_RC32M_CAL_PRECHARGE +#define PDS_RC32M_CAL_PRECHARGE_POS (5U) +#define PDS_RC32M_CAL_PRECHARGE_LEN (1U) +#define PDS_RC32M_CAL_PRECHARGE_MSK (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS) +#define PDS_RC32M_CAL_PRECHARGE_UMSK (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)) +#define PDS_RC32M_DIG_CODE_FR_CAL PDS_RC32M_DIG_CODE_FR_CAL +#define PDS_RC32M_DIG_CODE_FR_CAL_POS (6U) +#define PDS_RC32M_DIG_CODE_FR_CAL_LEN (8U) +#define PDS_RC32M_DIG_CODE_FR_CAL_MSK (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS) +#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)) +#define PDS_RC32M_ALLOW_CAL PDS_RC32M_ALLOW_CAL +#define PDS_RC32M_ALLOW_CAL_POS (17U) +#define PDS_RC32M_ALLOW_CAL_LEN (1U) +#define PDS_RC32M_ALLOW_CAL_MSK (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS) +#define PDS_RC32M_ALLOW_CAL_UMSK (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)) +#define PDS_RC32M_REFCLK_HALF PDS_RC32M_REFCLK_HALF +#define PDS_RC32M_REFCLK_HALF_POS (18U) +#define PDS_RC32M_REFCLK_HALF_LEN (1U) +#define PDS_RC32M_REFCLK_HALF_MSK (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS) +#define PDS_RC32M_REFCLK_HALF_UMSK (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)) +#define PDS_RC32M_EXT_CODE_EN PDS_RC32M_EXT_CODE_EN +#define PDS_RC32M_EXT_CODE_EN_POS (19U) +#define PDS_RC32M_EXT_CODE_EN_LEN (1U) +#define PDS_RC32M_EXT_CODE_EN_MSK (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS) +#define PDS_RC32M_EXT_CODE_EN_UMSK (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)) +#define PDS_RC32M_CAL_EN PDS_RC32M_CAL_EN +#define PDS_RC32M_CAL_EN_POS (20U) +#define PDS_RC32M_CAL_EN_LEN (1U) +#define PDS_RC32M_CAL_EN_MSK (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS) +#define PDS_RC32M_CAL_EN_UMSK (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)) +#define PDS_RC32M_PD PDS_RC32M_PD +#define PDS_RC32M_PD_POS (21U) +#define PDS_RC32M_PD_LEN (1U) +#define PDS_RC32M_PD_MSK (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS) +#define PDS_RC32M_PD_UMSK (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)) +#define PDS_RC32M_CODE_FR_EXT PDS_RC32M_CODE_FR_EXT +#define PDS_RC32M_CODE_FR_EXT_POS (22U) +#define PDS_RC32M_CODE_FR_EXT_LEN (8U) +#define PDS_RC32M_CODE_FR_EXT_MSK (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS) +#define PDS_RC32M_CODE_FR_EXT_UMSK (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)) + +/* 0x304 : rc32m_ctrl1 */ +#define PDS_RC32M_CTRL1_OFFSET (0x304) +#define PDS_RC32M_TEST_EN PDS_RC32M_TEST_EN +#define PDS_RC32M_TEST_EN_POS (0U) +#define PDS_RC32M_TEST_EN_LEN (1U) +#define PDS_RC32M_TEST_EN_MSK (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS) +#define PDS_RC32M_TEST_EN_UMSK (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)) +#define PDS_RC32M_SOFT_RST PDS_RC32M_SOFT_RST +#define PDS_RC32M_SOFT_RST_POS (1U) +#define PDS_RC32M_SOFT_RST_LEN (1U) +#define PDS_RC32M_SOFT_RST_MSK (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS) +#define PDS_RC32M_SOFT_RST_UMSK (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)) +#define PDS_RC32M_CLK_SOFT_RST PDS_RC32M_CLK_SOFT_RST +#define PDS_RC32M_CLK_SOFT_RST_POS (2U) +#define PDS_RC32M_CLK_SOFT_RST_LEN (1U) +#define PDS_RC32M_CLK_SOFT_RST_MSK (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS) +#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)) +#define PDS_RC32M_CLK_INV PDS_RC32M_CLK_INV +#define PDS_RC32M_CLK_INV_POS (3U) +#define PDS_RC32M_CLK_INV_LEN (1U) +#define PDS_RC32M_CLK_INV_MSK (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS) +#define PDS_RC32M_CLK_INV_UMSK (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)) +#define PDS_RC32M_CLK_FORCE_ON PDS_RC32M_CLK_FORCE_ON +#define PDS_RC32M_CLK_FORCE_ON_POS (4U) +#define PDS_RC32M_CLK_FORCE_ON_LEN (1U) +#define PDS_RC32M_CLK_FORCE_ON_MSK (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS) +#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)) +#define PDS_RC32M_RESERVED PDS_RC32M_RESERVED +#define PDS_RC32M_RESERVED_POS (24U) +#define PDS_RC32M_RESERVED_LEN (8U) +#define PDS_RC32M_RESERVED_MSK (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS) +#define PDS_RC32M_RESERVED_UMSK (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)) + +/* 0x400 : pu_rst_clkpll */ +#define PDS_PU_RST_CLKPLL_OFFSET (0x400) +#define PDS_CLKPLL_SDM_RESET PDS_CLKPLL_SDM_RESET +#define PDS_CLKPLL_SDM_RESET_POS (0U) +#define PDS_CLKPLL_SDM_RESET_LEN (1U) +#define PDS_CLKPLL_SDM_RESET_MSK (((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS) +#define PDS_CLKPLL_SDM_RESET_UMSK (~(((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS)) +#define PDS_CLKPLL_RESET_POSTDIV PDS_CLKPLL_RESET_POSTDIV +#define PDS_CLKPLL_RESET_POSTDIV_POS (1U) +#define PDS_CLKPLL_RESET_POSTDIV_LEN (1U) +#define PDS_CLKPLL_RESET_POSTDIV_MSK (((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS) +#define PDS_CLKPLL_RESET_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS)) +#define PDS_CLKPLL_RESET_FBDV PDS_CLKPLL_RESET_FBDV +#define PDS_CLKPLL_RESET_FBDV_POS (2U) +#define PDS_CLKPLL_RESET_FBDV_LEN (1U) +#define PDS_CLKPLL_RESET_FBDV_MSK (((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS) +#define PDS_CLKPLL_RESET_FBDV_UMSK (~(((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS)) +#define PDS_CLKPLL_RESET_REFDIV PDS_CLKPLL_RESET_REFDIV +#define PDS_CLKPLL_RESET_REFDIV_POS (3U) +#define PDS_CLKPLL_RESET_REFDIV_LEN (1U) +#define PDS_CLKPLL_RESET_REFDIV_MSK (((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS) +#define PDS_CLKPLL_RESET_REFDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS)) +#define PDS_CLKPLL_PU_POSTDIV PDS_CLKPLL_PU_POSTDIV +#define PDS_CLKPLL_PU_POSTDIV_POS (4U) +#define PDS_CLKPLL_PU_POSTDIV_LEN (1U) +#define PDS_CLKPLL_PU_POSTDIV_MSK (((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS) +#define PDS_CLKPLL_PU_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS)) +#define PDS_CLKPLL_PU_FBDV PDS_CLKPLL_PU_FBDV +#define PDS_CLKPLL_PU_FBDV_POS (5U) +#define PDS_CLKPLL_PU_FBDV_LEN (1U) +#define PDS_CLKPLL_PU_FBDV_MSK (((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS) +#define PDS_CLKPLL_PU_FBDV_UMSK (~(((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS)) +#define PDS_CLKPLL_PU_CLAMP_OP PDS_CLKPLL_PU_CLAMP_OP +#define PDS_CLKPLL_PU_CLAMP_OP_POS (6U) +#define PDS_CLKPLL_PU_CLAMP_OP_LEN (1U) +#define PDS_CLKPLL_PU_CLAMP_OP_MSK (((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS) +#define PDS_CLKPLL_PU_CLAMP_OP_UMSK (~(((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS)) +#define PDS_CLKPLL_PU_PFD PDS_CLKPLL_PU_PFD +#define PDS_CLKPLL_PU_PFD_POS (7U) +#define PDS_CLKPLL_PU_PFD_LEN (1U) +#define PDS_CLKPLL_PU_PFD_MSK (((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS) +#define PDS_CLKPLL_PU_PFD_UMSK (~(((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS)) +#define PDS_CLKPLL_PU_CP PDS_CLKPLL_PU_CP +#define PDS_CLKPLL_PU_CP_POS (8U) +#define PDS_CLKPLL_PU_CP_LEN (1U) +#define PDS_CLKPLL_PU_CP_MSK (((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS) +#define PDS_CLKPLL_PU_CP_UMSK (~(((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS)) +#define PDS_PU_CLKPLL_SFREG PDS_PU_CLKPLL_SFREG +#define PDS_PU_CLKPLL_SFREG_POS (9U) +#define PDS_PU_CLKPLL_SFREG_LEN (1U) +#define PDS_PU_CLKPLL_SFREG_MSK (((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS) +#define PDS_PU_CLKPLL_SFREG_UMSK (~(((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS)) +#define PDS_PU_CLKPLL PDS_PU_CLKPLL +#define PDS_PU_CLKPLL_POS (10U) +#define PDS_PU_CLKPLL_LEN (1U) +#define PDS_PU_CLKPLL_MSK (((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS) +#define PDS_PU_CLKPLL_UMSK (~(((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS)) + +/* 0x404 : clkpll_top_ctrl */ +#define PDS_CLKPLL_TOP_CTRL_OFFSET (0x404) +#define PDS_CLKPLL_POSTDIV PDS_CLKPLL_POSTDIV +#define PDS_CLKPLL_POSTDIV_POS (0U) +#define PDS_CLKPLL_POSTDIV_LEN (7U) +#define PDS_CLKPLL_POSTDIV_MSK (((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS) +#define PDS_CLKPLL_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS)) +#define PDS_CLKPLL_REFDIV_RATIO PDS_CLKPLL_REFDIV_RATIO +#define PDS_CLKPLL_REFDIV_RATIO_POS (8U) +#define PDS_CLKPLL_REFDIV_RATIO_LEN (4U) +#define PDS_CLKPLL_REFDIV_RATIO_MSK (((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS) +#define PDS_CLKPLL_REFDIV_RATIO_UMSK (~(((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS)) +#define PDS_CLKPLL_XTAL_RC32M_SEL PDS_CLKPLL_XTAL_RC32M_SEL +#define PDS_CLKPLL_XTAL_RC32M_SEL_POS (12U) +#define PDS_CLKPLL_XTAL_RC32M_SEL_LEN (1U) +#define PDS_CLKPLL_XTAL_RC32M_SEL_MSK (((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS) +#define PDS_CLKPLL_XTAL_RC32M_SEL_UMSK (~(((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS)) +#define PDS_CLKPLL_REFCLK_SEL PDS_CLKPLL_REFCLK_SEL +#define PDS_CLKPLL_REFCLK_SEL_POS (16U) +#define PDS_CLKPLL_REFCLK_SEL_LEN (1U) +#define PDS_CLKPLL_REFCLK_SEL_MSK (((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS) +#define PDS_CLKPLL_REFCLK_SEL_UMSK (~(((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS)) +#define PDS_CLKPLL_VG11_SEL PDS_CLKPLL_VG11_SEL +#define PDS_CLKPLL_VG11_SEL_POS (20U) +#define PDS_CLKPLL_VG11_SEL_LEN (2U) +#define PDS_CLKPLL_VG11_SEL_MSK (((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS) +#define PDS_CLKPLL_VG11_SEL_UMSK (~(((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS)) +#define PDS_CLKPLL_RESV PDS_CLKPLL_RESV +#define PDS_CLKPLL_RESV_POS (24U) +#define PDS_CLKPLL_RESV_LEN (2U) +#define PDS_CLKPLL_RESV_MSK (((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS) +#define PDS_CLKPLL_RESV_UMSK (~(((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS)) + +/* 0x408 : clkpll_cp */ +#define PDS_CLKPLL_CP_OFFSET (0x408) +#define PDS_CLKPLL_SEL_CP_BIAS PDS_CLKPLL_SEL_CP_BIAS +#define PDS_CLKPLL_SEL_CP_BIAS_POS (0U) +#define PDS_CLKPLL_SEL_CP_BIAS_LEN (1U) +#define PDS_CLKPLL_SEL_CP_BIAS_MSK (((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS) +#define PDS_CLKPLL_SEL_CP_BIAS_UMSK (~(((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS)) +#define PDS_CLKPLL_ICP_5U PDS_CLKPLL_ICP_5U +#define PDS_CLKPLL_ICP_5U_POS (4U) +#define PDS_CLKPLL_ICP_5U_LEN (2U) +#define PDS_CLKPLL_ICP_5U_MSK (((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS) +#define PDS_CLKPLL_ICP_5U_UMSK (~(((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS)) +#define PDS_CLKPLL_ICP_1U PDS_CLKPLL_ICP_1U +#define PDS_CLKPLL_ICP_1U_POS (6U) +#define PDS_CLKPLL_ICP_1U_LEN (2U) +#define PDS_CLKPLL_ICP_1U_MSK (((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS) +#define PDS_CLKPLL_ICP_1U_UMSK (~(((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS)) +#define PDS_CLKPLL_INT_FRAC_SW PDS_CLKPLL_INT_FRAC_SW +#define PDS_CLKPLL_INT_FRAC_SW_POS (8U) +#define PDS_CLKPLL_INT_FRAC_SW_LEN (1U) +#define PDS_CLKPLL_INT_FRAC_SW_MSK (((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS) +#define PDS_CLKPLL_INT_FRAC_SW_UMSK (~(((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS)) +#define PDS_CLKPLL_CP_STARTUP_EN PDS_CLKPLL_CP_STARTUP_EN +#define PDS_CLKPLL_CP_STARTUP_EN_POS (9U) +#define PDS_CLKPLL_CP_STARTUP_EN_LEN (1U) +#define PDS_CLKPLL_CP_STARTUP_EN_MSK (((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS) +#define PDS_CLKPLL_CP_STARTUP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS)) +#define PDS_CLKPLL_CP_OPAMP_EN PDS_CLKPLL_CP_OPAMP_EN +#define PDS_CLKPLL_CP_OPAMP_EN_POS (10U) +#define PDS_CLKPLL_CP_OPAMP_EN_LEN (1U) +#define PDS_CLKPLL_CP_OPAMP_EN_MSK (((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS) +#define PDS_CLKPLL_CP_OPAMP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS)) + +/* 0x40C : clkpll_rz */ +#define PDS_CLKPLL_RZ_OFFSET (0x40C) +#define PDS_CLKPLL_C4_EN PDS_CLKPLL_C4_EN +#define PDS_CLKPLL_C4_EN_POS (0U) +#define PDS_CLKPLL_C4_EN_LEN (1U) +#define PDS_CLKPLL_C4_EN_MSK (((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS) +#define PDS_CLKPLL_C4_EN_UMSK (~(((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS)) +#define PDS_CLKPLL_R4 PDS_CLKPLL_R4 +#define PDS_CLKPLL_R4_POS (4U) +#define PDS_CLKPLL_R4_LEN (2U) +#define PDS_CLKPLL_R4_MSK (((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS) +#define PDS_CLKPLL_R4_UMSK (~(((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS)) +#define PDS_CLKPLL_R4_SHORT PDS_CLKPLL_R4_SHORT +#define PDS_CLKPLL_R4_SHORT_POS (8U) +#define PDS_CLKPLL_R4_SHORT_LEN (1U) +#define PDS_CLKPLL_R4_SHORT_MSK (((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS) +#define PDS_CLKPLL_R4_SHORT_UMSK (~(((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS)) +#define PDS_CLKPLL_C3 PDS_CLKPLL_C3 +#define PDS_CLKPLL_C3_POS (12U) +#define PDS_CLKPLL_C3_LEN (2U) +#define PDS_CLKPLL_C3_MSK (((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS) +#define PDS_CLKPLL_C3_UMSK (~(((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS)) +#define PDS_CLKPLL_CZ PDS_CLKPLL_CZ +#define PDS_CLKPLL_CZ_POS (14U) +#define PDS_CLKPLL_CZ_LEN (2U) +#define PDS_CLKPLL_CZ_MSK (((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS) +#define PDS_CLKPLL_CZ_UMSK (~(((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS)) +#define PDS_CLKPLL_RZ PDS_CLKPLL_RZ +#define PDS_CLKPLL_RZ_POS (16U) +#define PDS_CLKPLL_RZ_LEN (3U) +#define PDS_CLKPLL_RZ_MSK (((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS) +#define PDS_CLKPLL_RZ_UMSK (~(((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS)) + +/* 0x410 : clkpll_fbdv */ +#define PDS_CLKPLL_FBDV_OFFSET (0x410) +#define PDS_CLKPLL_SEL_SAMPLE_CLK PDS_CLKPLL_SEL_SAMPLE_CLK +#define PDS_CLKPLL_SEL_SAMPLE_CLK_POS (0U) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_LEN (2U) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_MSK (((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS)) +#define PDS_CLKPLL_SEL_FB_CLK PDS_CLKPLL_SEL_FB_CLK +#define PDS_CLKPLL_SEL_FB_CLK_POS (2U) +#define PDS_CLKPLL_SEL_FB_CLK_LEN (2U) +#define PDS_CLKPLL_SEL_FB_CLK_MSK (((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS) +#define PDS_CLKPLL_SEL_FB_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS)) + +/* 0x414 : clkpll_vco */ +#define PDS_CLKPLL_VCO_OFFSET (0x414) +#define PDS_CLKPLL_VCO_SPEED PDS_CLKPLL_VCO_SPEED +#define PDS_CLKPLL_VCO_SPEED_POS (0U) +#define PDS_CLKPLL_VCO_SPEED_LEN (3U) +#define PDS_CLKPLL_VCO_SPEED_MSK (((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS) +#define PDS_CLKPLL_VCO_SPEED_UMSK (~(((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS)) +#define PDS_CLKPLL_SHRTR PDS_CLKPLL_SHRTR +#define PDS_CLKPLL_SHRTR_POS (3U) +#define PDS_CLKPLL_SHRTR_LEN (1U) +#define PDS_CLKPLL_SHRTR_MSK (((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS) +#define PDS_CLKPLL_SHRTR_UMSK (~(((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS)) + +/* 0x418 : clkpll_sdm */ +#define PDS_CLKPLL_SDM_OFFSET (0x418) +#define PDS_CLKPLL_SDMIN PDS_CLKPLL_SDMIN +#define PDS_CLKPLL_SDMIN_POS (0U) +#define PDS_CLKPLL_SDMIN_LEN (24U) +#define PDS_CLKPLL_SDMIN_MSK (((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS) +#define PDS_CLKPLL_SDMIN_UMSK (~(((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS)) +#define PDS_CLKPLL_DITHER_SEL PDS_CLKPLL_DITHER_SEL +#define PDS_CLKPLL_DITHER_SEL_POS (24U) +#define PDS_CLKPLL_DITHER_SEL_LEN (2U) +#define PDS_CLKPLL_DITHER_SEL_MSK (((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS) +#define PDS_CLKPLL_DITHER_SEL_UMSK (~(((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS)) +#define PDS_CLKPLL_SDM_FLAG PDS_CLKPLL_SDM_FLAG +#define PDS_CLKPLL_SDM_FLAG_POS (28U) +#define PDS_CLKPLL_SDM_FLAG_LEN (1U) +#define PDS_CLKPLL_SDM_FLAG_MSK (((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS) +#define PDS_CLKPLL_SDM_FLAG_UMSK (~(((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS)) +#define PDS_CLKPLL_SDM_BYPASS PDS_CLKPLL_SDM_BYPASS +#define PDS_CLKPLL_SDM_BYPASS_POS (29U) +#define PDS_CLKPLL_SDM_BYPASS_LEN (1U) +#define PDS_CLKPLL_SDM_BYPASS_MSK (((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS) +#define PDS_CLKPLL_SDM_BYPASS_UMSK (~(((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS)) + +/* 0x41C : clkpll_output_en */ +#define PDS_CLKPLL_OUTPUT_EN_OFFSET (0x41C) +#define PDS_CLKPLL_EN_480M PDS_CLKPLL_EN_480M +#define PDS_CLKPLL_EN_480M_POS (0U) +#define PDS_CLKPLL_EN_480M_LEN (1U) +#define PDS_CLKPLL_EN_480M_MSK (((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS) +#define PDS_CLKPLL_EN_480M_UMSK (~(((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS)) +#define PDS_CLKPLL_EN_240M PDS_CLKPLL_EN_240M +#define PDS_CLKPLL_EN_240M_POS (1U) +#define PDS_CLKPLL_EN_240M_LEN (1U) +#define PDS_CLKPLL_EN_240M_MSK (((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS) +#define PDS_CLKPLL_EN_240M_UMSK (~(((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS)) +#define PDS_CLKPLL_EN_192M PDS_CLKPLL_EN_192M +#define PDS_CLKPLL_EN_192M_POS (2U) +#define PDS_CLKPLL_EN_192M_LEN (1U) +#define PDS_CLKPLL_EN_192M_MSK (((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS) +#define PDS_CLKPLL_EN_192M_UMSK (~(((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS)) +#define PDS_CLKPLL_EN_160M PDS_CLKPLL_EN_160M +#define PDS_CLKPLL_EN_160M_POS (3U) +#define PDS_CLKPLL_EN_160M_LEN (1U) +#define PDS_CLKPLL_EN_160M_MSK (((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS) +#define PDS_CLKPLL_EN_160M_UMSK (~(((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS)) +#define PDS_CLKPLL_EN_120M PDS_CLKPLL_EN_120M +#define PDS_CLKPLL_EN_120M_POS (4U) +#define PDS_CLKPLL_EN_120M_LEN (1U) +#define PDS_CLKPLL_EN_120M_MSK (((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS) +#define PDS_CLKPLL_EN_120M_UMSK (~(((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS)) +#define PDS_CLKPLL_EN_96M PDS_CLKPLL_EN_96M +#define PDS_CLKPLL_EN_96M_POS (5U) +#define PDS_CLKPLL_EN_96M_LEN (1U) +#define PDS_CLKPLL_EN_96M_MSK (((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS) +#define PDS_CLKPLL_EN_96M_UMSK (~(((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS)) +#define PDS_CLKPLL_EN_80M PDS_CLKPLL_EN_80M +#define PDS_CLKPLL_EN_80M_POS (6U) +#define PDS_CLKPLL_EN_80M_LEN (1U) +#define PDS_CLKPLL_EN_80M_MSK (((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS) +#define PDS_CLKPLL_EN_80M_UMSK (~(((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS)) +#define PDS_CLKPLL_EN_48M PDS_CLKPLL_EN_48M +#define PDS_CLKPLL_EN_48M_POS (7U) +#define PDS_CLKPLL_EN_48M_LEN (1U) +#define PDS_CLKPLL_EN_48M_MSK (((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS) +#define PDS_CLKPLL_EN_48M_UMSK (~(((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS)) +#define PDS_CLKPLL_EN_32M PDS_CLKPLL_EN_32M +#define PDS_CLKPLL_EN_32M_POS (8U) +#define PDS_CLKPLL_EN_32M_LEN (1U) +#define PDS_CLKPLL_EN_32M_MSK (((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS) +#define PDS_CLKPLL_EN_32M_UMSK (~(((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS)) +#define PDS_CLKPLL_EN_DIV2_480M PDS_CLKPLL_EN_DIV2_480M +#define PDS_CLKPLL_EN_DIV2_480M_POS (9U) +#define PDS_CLKPLL_EN_DIV2_480M_LEN (1U) +#define PDS_CLKPLL_EN_DIV2_480M_MSK (((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS) +#define PDS_CLKPLL_EN_DIV2_480M_UMSK (~(((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS)) + +/* 0x420 : clkpll_test_enable */ +#define PDS_CLKPLL_TEST_ENABLE_OFFSET (0x420) +#define PDS_DTEN_CLKPLL_POSTDIV_CLK PDS_DTEN_CLKPLL_POSTDIV_CLK +#define PDS_DTEN_CLKPLL_POSTDIV_CLK_POS (0U) +#define PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN (1U) +#define PDS_DTEN_CLKPLL_POSTDIV_CLK_MSK (((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS) +#define PDS_DTEN_CLKPLL_POSTDIV_CLK_UMSK (~(((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS)) +#define PDS_DTEN_CLK96M PDS_DTEN_CLK96M +#define PDS_DTEN_CLK96M_POS (1U) +#define PDS_DTEN_CLK96M_LEN (1U) +#define PDS_DTEN_CLK96M_MSK (((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS) +#define PDS_DTEN_CLK96M_UMSK (~(((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS)) +#define PDS_DTEN_CLK32M PDS_DTEN_CLK32M +#define PDS_DTEN_CLK32M_POS (2U) +#define PDS_DTEN_CLK32M_LEN (1U) +#define PDS_DTEN_CLK32M_MSK (((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS) +#define PDS_DTEN_CLK32M_UMSK (~(((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS)) +#define PDS_DTEN_CLKPLL_FSDM PDS_DTEN_CLKPLL_FSDM +#define PDS_DTEN_CLKPLL_FSDM_POS (3U) +#define PDS_DTEN_CLKPLL_FSDM_LEN (1U) +#define PDS_DTEN_CLKPLL_FSDM_MSK (((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS) +#define PDS_DTEN_CLKPLL_FSDM_UMSK (~(((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS)) +#define PDS_DTEN_CLKPLL_FREF PDS_DTEN_CLKPLL_FREF +#define PDS_DTEN_CLKPLL_FREF_POS (4U) +#define PDS_DTEN_CLKPLL_FREF_LEN (1U) +#define PDS_DTEN_CLKPLL_FREF_MSK (((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS) +#define PDS_DTEN_CLKPLL_FREF_UMSK (~(((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS)) +#define PDS_DTEN_CLKPLL_FIN PDS_DTEN_CLKPLL_FIN +#define PDS_DTEN_CLKPLL_FIN_POS (5U) +#define PDS_DTEN_CLKPLL_FIN_LEN (1U) +#define PDS_DTEN_CLKPLL_FIN_MSK (((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS) +#define PDS_DTEN_CLKPLL_FIN_UMSK (~(((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS)) +#define PDS_TEN_CLKPLL_SFREG PDS_TEN_CLKPLL_SFREG +#define PDS_TEN_CLKPLL_SFREG_POS (6U) +#define PDS_TEN_CLKPLL_SFREG_LEN (1U) +#define PDS_TEN_CLKPLL_SFREG_MSK (((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS) +#define PDS_TEN_CLKPLL_SFREG_UMSK (~(((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS)) +#define PDS_TEN_CLKPLL PDS_TEN_CLKPLL +#define PDS_TEN_CLKPLL_POS (7U) +#define PDS_TEN_CLKPLL_LEN (1U) +#define PDS_TEN_CLKPLL_MSK (((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS) +#define PDS_TEN_CLKPLL_UMSK (~(((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS)) +#define PDS_CLKPLL_DC_TP_OUT_EN PDS_CLKPLL_DC_TP_OUT_EN +#define PDS_CLKPLL_DC_TP_OUT_EN_POS (8U) +#define PDS_CLKPLL_DC_TP_OUT_EN_LEN (1U) +#define PDS_CLKPLL_DC_TP_OUT_EN_MSK (((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS) +#define PDS_CLKPLL_DC_TP_OUT_EN_UMSK (~(((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS)) + +struct pds_reg { + /* 0x0 : PDS_CTL */ + union { + struct + { + uint32_t pds_start_ps : 1; /* [ 0], w1p, 0x0 */ + uint32_t cr_sleep_forever : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_xtal_force_off : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_wifi_pds_save_state : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_pds_pd_dcdc18 : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_pds_pd_bg_sys : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_pds_ctrl_gpio_ie_pu_pd : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_pds_ctrl_pu_flash : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_pds_gate_clk : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_pds_mem_stby : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_sw_pu_flash : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_pds_iso_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_pds_wait_xtal_rdy : 1; /* [ 12], r/w, 0x0 */ + uint32_t cr_pds_pwr_off : 1; /* [ 13], r/w, 0x1 */ + uint32_t cr_pds_pd_xtal : 1; /* [ 14], r/w, 0x1 */ + uint32_t cr_pds_soc_enb_force_on : 1; /* [ 15], r/w, 0x0 */ + uint32_t cr_pds_rst_soc_en : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_pds_rc32m_off_dis : 1; /* [ 17], r/w, 0x0 */ + uint32_t cr_pds_ldo_vsel_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t cr_pds_ram_lp_with_clk_en : 1; /* [ 19], r/w, 0x0 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t cr_np_wfi_mask : 1; /* [ 21], r/w, 0x0 */ + uint32_t cr_pds_pd_ldo11 : 1; /* [ 22], r/w, 0x0 */ + uint32_t cr_pds_force_ram_clk_en : 1; /* [ 23], r/w, 0x0 */ + uint32_t cr_pds_ldo_vol : 4; /* [27:24], r/w, 0xa */ + uint32_t cr_pds_ctrl_rf : 2; /* [29:28], r/w, 0x1 */ + uint32_t cr_pds_ctrl_pll : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL; + + /* 0x4 : PDS_TIME1 */ + union { + struct + { + uint32_t cr_sleep_duration : 32; /* [31: 0], r/w, 0xca8 */ + } BF; + uint32_t WORD; + } PDS_TIME1; + + /* 0x8 reserved */ + uint8_t RESERVED0x8[4]; + + /* 0xC : PDS_INT */ + union { + struct + { + uint32_t ro_pds_wake_int : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t ro_pds_rf_done_int : 1; /* [ 2], r, 0x0 */ + uint32_t ro_pds_pll_done_int : 1; /* [ 3], r, 0x0 */ + uint32_t pds_reset_event : 3; /* [ 6: 4], r, 0x0 */ + uint32_t pds_clr_reset_event : 1; /* [ 7], w, 0x0 */ + uint32_t cr_pds_wake_int_mask : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ + uint32_t cr_pds_rf_done_int_mask : 1; /* [ 10], r/w, 0x0 */ + uint32_t cr_pds_pll_done_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_14 : 3; /* [14:12], rsvd, 0x0 */ + uint32_t cr_pds_int_clr : 1; /* [ 15], r/w, 0x0 */ + uint32_t cr_pds_wakeup_src_en : 8; /* [23:16], r/w, 0xff */ + uint32_t ro_pds_wakeup_event : 8; /* [31:24], r, 0x0 */ + } BF; + uint32_t WORD; + } PDS_INT; + + /* 0x10 : PDS_CTL2 */ + union { + struct + { + uint32_t cr_pds_force_np_pwr_off : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t cr_pds_force_bz_pwr_off : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_pds_force_usb_pwr_off : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_pds_force_np_iso_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ + uint32_t cr_pds_force_bz_iso_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_pds_force_usb_iso_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_pds_force_np_pds_rst : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ + uint32_t cr_pds_force_bz_pds_rst : 1; /* [ 10], r/w, 0x0 */ + uint32_t cr_pds_force_usb_pds_rst : 1; /* [ 11], r/w, 0x0 */ + uint32_t cr_pds_force_np_mem_stby : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */ + uint32_t cr_pds_force_bz_mem_stby : 1; /* [ 14], r/w, 0x0 */ + uint32_t cr_pds_force_usb_mem_stby : 1; /* [ 15], r/w, 0x0 */ + uint32_t cr_pds_force_np_gate_clk : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t cr_pds_force_bz_gate_clk : 1; /* [ 18], r/w, 0x0 */ + uint32_t cr_pds_force_usb_gate_clk : 1; /* [ 19], r/w, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL2; + + /* 0x14 : PDS_CTL3 */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_pwr_off : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_pds_force_ble_pwr_off : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_4 : 2; /* [ 4: 3], rsvd, 0x0 */ + uint32_t cr_pds_force_ble_iso_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_pds_rst : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_pds_force_ble_pds_rst : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_mem_stby : 1; /* [ 10], r/w, 0x0 */ + uint32_t cr_pds_force_ble_mem_stby : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_gate_clk : 1; /* [ 13], r/w, 0x0 */ + uint32_t cr_pds_force_ble_gate_clk : 1; /* [ 14], r/w, 0x0 */ + uint32_t reserved_15_23 : 9; /* [23:15], rsvd, 0x0 */ + uint32_t cr_pds_np_iso_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_26 : 2; /* [26:25], rsvd, 0x0 */ + uint32_t cr_pds_bz_iso_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t cr_pds_ble_iso_en : 1; /* [ 28], r/w, 0x1 */ + uint32_t cr_pds_usb_iso_en : 1; /* [ 29], r/w, 0x1 */ + uint32_t cr_pds_misc_iso_en : 1; /* [ 30], r/w, 0x1 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL3; + + /* 0x18 : PDS_CTL4 */ + union { + struct + { + uint32_t cr_pds_np_pwr_off : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_pds_np_reset : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_pds_np_mem_stby : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_pds_np_gate_clk : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_11 : 8; /* [11: 4], rsvd, 0x0 */ + uint32_t cr_pds_bz_pwr_off : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_pds_bz_reset : 1; /* [ 13], r/w, 0x1 */ + uint32_t cr_pds_bz_mem_stby : 1; /* [ 14], r/w, 0x1 */ + uint32_t cr_pds_bz_gate_clk : 1; /* [ 15], r/w, 0x1 */ + uint32_t cr_pds_ble_pwr_off : 1; /* [ 16], r/w, 0x1 */ + uint32_t cr_pds_ble_reset : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_pds_ble_mem_stby : 1; /* [ 18], r/w, 0x1 */ + uint32_t cr_pds_ble_gate_clk : 1; /* [ 19], r/w, 0x1 */ + uint32_t cr_pds_usb_pwr_off : 1; /* [ 20], r/w, 0x1 */ + uint32_t cr_pds_usb_reset : 1; /* [ 21], r/w, 0x1 */ + uint32_t cr_pds_usb_mem_stby : 1; /* [ 22], r/w, 0x1 */ + uint32_t cr_pds_usb_gate_clk : 1; /* [ 23], r/w, 0x1 */ + uint32_t cr_pds_misc_pwr_off : 1; /* [ 24], r/w, 0x1 */ + uint32_t cr_pds_misc_reset : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_pds_misc_mem_stby : 1; /* [ 26], r/w, 0x1 */ + uint32_t cr_pds_misc_gate_clk : 1; /* [ 27], r/w, 0x1 */ + uint32_t reserved_28_29 : 2; /* [29:28], rsvd, 0x0 */ + uint32_t cr_pds_misc_ana_pwr_off : 1; /* [ 30], r/w, 0x1 */ + uint32_t cr_pds_misc_dig_pwr_off : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } PDS_CTL4; + + /* 0x1C : pds_stat */ + union { + struct + { + uint32_t ro_pds_state : 4; /* [ 3: 0], r, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t ro_pds_rf_state : 4; /* [11: 8], r, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t ro_pds_pll_state : 2; /* [17:16], r, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pds_stat; + + /* 0x20 : pds_ram1 */ + union { + struct + { + uint32_t cr_pds_ram_ret1n : 4; /* [ 3: 0], r/w, 0xf */ + uint32_t cr_pds_ram_ret2n : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t cr_pds_ram_pgen : 4; /* [11: 8], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pds_ram1; + + /* 0x24 reserved */ + uint8_t RESERVED0x24[12]; + + /* 0x30 : pds_gpio_set_pu_pd */ + union { + struct + { + uint32_t cr_pds_gpio_22_17_pd : 6; /* [ 5: 0], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t cr_pds_gpio_22_17_pu : 6; /* [13: 8], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t cr_pds_gpio_28_23_pd : 6; /* [21:16], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t cr_pds_gpio_28_23_pu : 6; /* [29:24], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pds_gpio_set_pu_pd; + + /* 0x34 reserved */ + uint8_t RESERVED0x34[12]; + + /* 0x40 : pds_gpio_int */ + union { + struct + { + uint32_t pds_gpio_int_mask : 1; /* [ 0], r/w, 0x1 */ + uint32_t pds_gpio_int_stat : 1; /* [ 1], r, 0x0 */ + uint32_t pds_gpio_int_clr : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t pds_gpio_int_mode : 3; /* [ 6: 4], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t pds_gpio_int_select : 3; /* [10: 8], r/w, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pds_gpio_int; + + /* 0x44 reserved */ + uint8_t RESERVED0x44[700]; + + /* 0x300 : rc32m_ctrl0 */ + union { + struct + { + uint32_t rc32m_cal_done : 1; /* [ 0], r, 0x0 */ + uint32_t rc32m_rdy : 1; /* [ 1], r, 0x0 */ + uint32_t rc32m_cal_inprogress : 1; /* [ 2], r, 0x0 */ + uint32_t rc32m_cal_div : 2; /* [ 4: 3], r/w, 0x3 */ + uint32_t rc32m_cal_precharge : 1; /* [ 5], r, 0x0 */ + uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6], r, 0x0 */ + uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */ + uint32_t rc32m_allow_cal : 1; /* [ 17], r/w, 0x0 */ + uint32_t rc32m_refclk_half : 1; /* [ 18], r/w, 0x0 */ + uint32_t rc32m_ext_code_en : 1; /* [ 19], r/w, 0x1 */ + uint32_t rc32m_cal_en : 1; /* [ 20], r/w, 0x0 */ + uint32_t rc32m_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t rc32m_code_fr_ext : 8; /* [29:22], r/w, 0x60 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rc32m_ctrl0; + + /* 0x304 : rc32m_ctrl1 */ + union { + struct + { + uint32_t rc32m_test_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t rc32m_soft_rst : 1; /* [ 1], r/w, 0x0 */ + uint32_t rc32m_clk_soft_rst : 1; /* [ 2], r/w, 0x0 */ + uint32_t rc32m_clk_inv : 1; /* [ 3], r/w, 0x0 */ + uint32_t rc32m_clk_force_on : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_23 : 19; /* [23: 5], rsvd, 0x0 */ + uint32_t rc32m_reserved : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } rc32m_ctrl1; + + /* 0x308 reserved */ + uint8_t RESERVED0x308[248]; + + /* 0x400 : pu_rst_clkpll */ + union { + struct + { + uint32_t clkpll_sdm_reset : 1; /* [ 0], r/w, 0x0 */ + uint32_t clkpll_reset_postdiv : 1; /* [ 1], r/w, 0x0 */ + uint32_t clkpll_reset_fbdv : 1; /* [ 2], r/w, 0x0 */ + uint32_t clkpll_reset_refdiv : 1; /* [ 3], r/w, 0x0 */ + uint32_t clkpll_pu_postdiv : 1; /* [ 4], r/w, 0x1 */ + uint32_t clkpll_pu_fbdv : 1; /* [ 5], r/w, 0x1 */ + uint32_t clkpll_pu_clamp_op : 1; /* [ 6], r/w, 0x1 */ + uint32_t clkpll_pu_pfd : 1; /* [ 7], r/w, 0x1 */ + uint32_t clkpll_pu_cp : 1; /* [ 8], r/w, 0x1 */ + uint32_t pu_clkpll_sfreg : 1; /* [ 9], r/w, 0x0 */ + uint32_t pu_clkpll : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pu_rst_clkpll; + + /* 0x404 : clkpll_top_ctrl */ + union { + struct + { + uint32_t clkpll_postdiv : 7; /* [ 6: 0], r/w, 0x14 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t clkpll_refdiv_ratio : 4; /* [11: 8], r/w, 0x4 */ + uint32_t clkpll_xtal_rc32m_sel : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t clkpll_refclk_sel : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ + uint32_t clkpll_vg11_sel : 2; /* [21:20], r/w, 0x1 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t clkpll_resv : 2; /* [25:24], r/w, 0x1 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_top_ctrl; + + /* 0x408 : clkpll_cp */ + union { + struct + { + uint32_t clkpll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t clkpll_icp_5u : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t clkpll_icp_1u : 2; /* [ 7: 6], r/w, 0x1 */ + uint32_t clkpll_int_frac_sw : 1; /* [ 8], r/w, 0x1 */ + uint32_t clkpll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */ + uint32_t clkpll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_cp; + + /* 0x40C : clkpll_rz */ + union { + struct + { + uint32_t clkpll_c4_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t clkpll_r4 : 2; /* [ 5: 4], r/w, 0x2 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t clkpll_r4_short : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t clkpll_c3 : 2; /* [13:12], r/w, 0x2 */ + uint32_t clkpll_cz : 2; /* [15:14], r/w, 0x2 */ + uint32_t clkpll_rz : 3; /* [18:16], r/w, 0x5 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_rz; + + /* 0x410 : clkpll_fbdv */ + union { + struct + { + uint32_t clkpll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */ + uint32_t clkpll_sel_fb_clk : 2; /* [ 3: 2], r/w, 0x1 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_fbdv; + + /* 0x414 : clkpll_vco */ + union { + struct + { + uint32_t clkpll_vco_speed : 3; /* [ 2: 0], r/w, 0x6 */ + uint32_t clkpll_shrtr : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_vco; + + /* 0x418 : clkpll_sdm */ + union { + struct + { + uint32_t clkpll_sdmin : 24; /* [23: 0], r/w, 0x600000 */ + uint32_t clkpll_dither_sel : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t clkpll_sdm_flag : 1; /* [ 28], r/w, 0x1 */ + uint32_t clkpll_sdm_bypass : 1; /* [ 29], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_sdm; + + /* 0x41C : clkpll_output_en */ + union { + struct + { + uint32_t clkpll_en_480m : 1; /* [ 0], r/w, 0x0 */ + uint32_t clkpll_en_240m : 1; /* [ 1], r/w, 0x0 */ + uint32_t clkpll_en_192m : 1; /* [ 2], r/w, 0x0 */ + uint32_t clkpll_en_160m : 1; /* [ 3], r/w, 0x0 */ + uint32_t clkpll_en_120m : 1; /* [ 4], r/w, 0x0 */ + uint32_t clkpll_en_96m : 1; /* [ 5], r/w, 0x0 */ + uint32_t clkpll_en_80m : 1; /* [ 6], r/w, 0x0 */ + uint32_t clkpll_en_48m : 1; /* [ 7], r/w, 0x0 */ + uint32_t clkpll_en_32m : 1; /* [ 8], r/w, 0x1 */ + uint32_t clkpll_en_div2_480m : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_output_en; + + /* 0x420 : clkpll_test_enable */ + union { + struct + { + uint32_t dten_clkpll_postdiv_clk : 1; /* [ 0], r/w, 0x0 */ + uint32_t dten_clk96M : 1; /* [ 1], r/w, 0x0 */ + uint32_t dten_clk32M : 1; /* [ 2], r/w, 0x0 */ + uint32_t dten_clkpll_fsdm : 1; /* [ 3], r/w, 0x0 */ + uint32_t dten_clkpll_fref : 1; /* [ 4], r/w, 0x0 */ + uint32_t dten_clkpll_fin : 1; /* [ 5], r/w, 0x0 */ + uint32_t ten_clkpll_sfreg : 1; /* [ 6], r/w, 0x0 */ + uint32_t ten_clkpll : 1; /* [ 7], r/w, 0x0 */ + uint32_t clkpll_dc_tp_out_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_test_enable; +}; + +typedef volatile struct pds_reg pds_reg_t; + +#endif /* __PDS_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pwm_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pwm_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..2b0d67cefb144a29751e6e692c4ef09297bc3113 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/pwm_reg.h @@ -0,0 +1,993 @@ +/** + ****************************************************************************** + * @file pwm_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PWM_REG_H__ +#define __PWM_REG_H__ + +#include "bl702.h" + +/* 0x0 : pwm_int_config */ +#define PWM_INT_CONFIG_OFFSET (0x0) +#define PWM_INTERRUPT_STS PWM_INTERRUPT_STS +#define PWM_INTERRUPT_STS_POS (0U) +#define PWM_INTERRUPT_STS_LEN (6U) +#define PWM_INTERRUPT_STS_MSK (((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS) +#define PWM_INTERRUPT_STS_UMSK (~(((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS)) +#define PWM_INT_CLEAR PWM_INT_CLEAR +#define PWM_INT_CLEAR_POS (8U) +#define PWM_INT_CLEAR_LEN (6U) +#define PWM_INT_CLEAR_MSK (((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS) +#define PWM_INT_CLEAR_UMSK (~(((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS)) + +/* 0x20 : pwm0_clkdiv */ +#define PWM0_CLKDIV_OFFSET (0x20) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x24 : pwm0_thre1 */ +#define PWM0_THRE1_OFFSET (0x24) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x28 : pwm0_thre2 */ +#define PWM0_THRE2_OFFSET (0x28) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0x2C : pwm0_period */ +#define PWM0_PERIOD_OFFSET (0x2C) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x30 : pwm0_config */ +#define PWM0_CONFIG_OFFSET (0x30) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x34 : pwm0_interrupt */ +#define PWM0_INTERRUPT_OFFSET (0x34) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +/* 0x40 : pwm1_clkdiv */ +#define PWM1_CLKDIV_OFFSET (0x40) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x44 : pwm1_thre1 */ +#define PWM1_THRE1_OFFSET (0x44) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x48 : pwm1_thre2 */ +#define PWM1_THRE2_OFFSET (0x48) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0x4C : pwm1_period */ +#define PWM1_PERIOD_OFFSET (0x4C) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x50 : pwm1_config */ +#define PWM1_CONFIG_OFFSET (0x50) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x54 : pwm1_interrupt */ +#define PWM1_INTERRUPT_OFFSET (0x54) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +/* 0x60 : pwm2_clkdiv */ +#define PWM2_CLKDIV_OFFSET (0x60) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x64 : pwm2_thre1 */ +#define PWM2_THRE1_OFFSET (0x64) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x68 : pwm2_thre2 */ +#define PWM2_THRE2_OFFSET (0x68) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0x6C : pwm2_period */ +#define PWM2_PERIOD_OFFSET (0x6C) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x70 : pwm2_config */ +#define PWM2_CONFIG_OFFSET (0x70) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x74 : pwm2_interrupt */ +#define PWM2_INTERRUPT_OFFSET (0x74) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +/* 0x80 : pwm3_clkdiv */ +#define PWM3_CLKDIV_OFFSET (0x80) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x84 : pwm3_thre1 */ +#define PWM3_THRE1_OFFSET (0x84) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x88 : pwm3_thre2 */ +#define PWM3_THRE2_OFFSET (0x88) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0x8C : pwm3_period */ +#define PWM3_PERIOD_OFFSET (0x8C) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x90 : pwm3_config */ +#define PWM3_CONFIG_OFFSET (0x90) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x94 : pwm3_interrupt */ +#define PWM3_INTERRUPT_OFFSET (0x94) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +/* 0xA0 : pwm4_clkdiv */ +#define PWM4_CLKDIV_OFFSET (0xA0) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0xA4 : pwm4_thre1 */ +#define PWM4_THRE1_OFFSET (0xA4) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0xA8 : pwm4_thre2 */ +#define PWM4_THRE2_OFFSET (0xA8) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0xAC : pwm4_period */ +#define PWM4_PERIOD_OFFSET (0xAC) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0xB0 : pwm4_config */ +#define PWM4_CONFIG_OFFSET (0xB0) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0xB4 : pwm4_interrupt */ +#define PWM4_INTERRUPT_OFFSET (0xB4) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +struct pwm_reg { + /* 0x0 : pwm_int_config */ + union { + struct + { + uint32_t pwm_interrupt_sts : 6; /* [ 5: 0], r, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t pwm_int_clear : 6; /* [13: 8], w, 0x0 */ + uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_int_config; + + /* 0x4 reserved */ + uint8_t RESERVED0x4[28]; + + /* 0x20 : pwm0_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_clkdiv; + + /* 0x24 : pwm0_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_thre1; + + /* 0x28 : pwm0_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_thre2; + + /* 0x2C : pwm0_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_period; + + /* 0x30 : pwm0_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_config; + + /* 0x34 : pwm0_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm0_interrupt; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[8]; + + /* 0x40 : pwm1_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_clkdiv; + + /* 0x44 : pwm1_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_thre1; + + /* 0x48 : pwm1_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_thre2; + + /* 0x4C : pwm1_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_period; + + /* 0x50 : pwm1_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_config; + + /* 0x54 : pwm1_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm1_interrupt; + + /* 0x58 reserved */ + uint8_t RESERVED0x58[8]; + + /* 0x60 : pwm2_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_clkdiv; + + /* 0x64 : pwm2_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_thre1; + + /* 0x68 : pwm2_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_thre2; + + /* 0x6C : pwm2_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_period; + + /* 0x70 : pwm2_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_config; + + /* 0x74 : pwm2_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm2_interrupt; + + /* 0x78 reserved */ + uint8_t RESERVED0x78[8]; + + /* 0x80 : pwm3_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_clkdiv; + + /* 0x84 : pwm3_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_thre1; + + /* 0x88 : pwm3_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_thre2; + + /* 0x8C : pwm3_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_period; + + /* 0x90 : pwm3_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_config; + + /* 0x94 : pwm3_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm3_interrupt; + + /* 0x98 reserved */ + uint8_t RESERVED0x98[8]; + + /* 0xA0 : pwm4_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_clkdiv; + + /* 0xA4 : pwm4_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_thre1; + + /* 0xA8 : pwm4_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_thre2; + + /* 0xAC : pwm4_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_period; + + /* 0xB0 : pwm4_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_config; + + /* 0xB4 : pwm4_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm4_interrupt; +}; + +typedef volatile struct pwm_reg pwm_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : pwm_clkdiv */ +#define PWM_CLKDIV_OFFSET (0x0) +#define PWM_CLK_DIV PWM_CLK_DIV +#define PWM_CLK_DIV_POS (0U) +#define PWM_CLK_DIV_LEN (16U) +#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) +#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) + +/* 0x4 : pwm_thre1 */ +#define PWM_THRE1_OFFSET (0x4) +#define PWM_THRE1 PWM_THRE1 +#define PWM_THRE1_POS (0U) +#define PWM_THRE1_LEN (16U) +#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS) +#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)) + +/* 0x8 : pwm_thre2 */ +#define PWM_THRE2_OFFSET (0x8) +#define PWM_THRE2 PWM_THRE2 +#define PWM_THRE2_POS (0U) +#define PWM_THRE2_LEN (16U) +#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS) +#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)) + +/* 0xc : pwm_period */ +#define PWM_PERIOD_OFFSET (0xc) +#define PWM_PERIOD PWM_PERIOD +#define PWM_PERIOD_POS (0U) +#define PWM_PERIOD_LEN (16U) +#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) +#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) + +/* 0x10 : pwm_config */ +#define PWM_CONFIG_OFFSET (0x10) +#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL +#define PWM_REG_CLK_SEL_POS (0U) +#define PWM_REG_CLK_SEL_LEN (2U) +#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) +#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) +#define PWM_OUT_INV PWM_OUT_INV +#define PWM_OUT_INV_POS (2U) +#define PWM_OUT_INV_LEN (1U) +#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS) +#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)) +#define PWM_STOP_MODE PWM_STOP_MODE +#define PWM_STOP_MODE_POS (3U) +#define PWM_STOP_MODE_LEN (1U) +#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) +#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) +#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL +#define PWM_SW_FORCE_VAL_POS (4U) +#define PWM_SW_FORCE_VAL_LEN (1U) +#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS) +#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)) +#define PWM_SW_MODE PWM_SW_MODE +#define PWM_SW_MODE_POS (5U) +#define PWM_SW_MODE_LEN (1U) +#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS) +#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)) +#define PWM_STOP_EN PWM_STOP_EN +#define PWM_STOP_EN_POS (6U) +#define PWM_STOP_EN_LEN (1U) +#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) +#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) +#define PWM_STS_TOP PWM_STS_TOP +#define PWM_STS_TOP_POS (7U) +#define PWM_STS_TOP_LEN (1U) +#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS) +#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)) + +/* 0x14 : pwm_interrupt */ +#define PWM_INTERRUPT_OFFSET (0x14) +#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT +#define PWM_INT_PERIOD_CNT_POS (0U) +#define PWM_INT_PERIOD_CNT_LEN (16U) +#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) +#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) +#define PWM_INT_ENABLE PWM_INT_ENABLE +#define PWM_INT_ENABLE_POS (16U) +#define PWM_INT_ENABLE_LEN (1U) +#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS) +#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)) + +struct pwm_channel_reg { + /* 0x0 : pwm_clkdiv */ + union { + struct + { + uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_clkdiv; + + /* 0x4 : pwm_thre1 */ + union { + struct + { + uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_thre1; + + /* 0x8 : pwm_thre2 */ + union { + struct + { + uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_thre2; + + /* 0xc : pwm_period */ + union { + struct + { + uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_period; + + /* 0x10 : pwm_config */ + union { + struct + { + uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */ + uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */ + uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */ + uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */ + uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_config; + + /* 0x14 : pwm_interrupt */ + union { + struct + { + uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */ + uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pwm_interrupt; +}; + +typedef volatile struct pwm_channel_reg pwm_channel_reg_t; + +#define PWM_CHANNEL_OFFSET 0x20 + +#endif /* __PWM_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/qdec_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/qdec_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..4883db0927dd699b293433c6d79af1edbe5f80f5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/qdec_reg.h @@ -0,0 +1,768 @@ +/** + ****************************************************************************** + * @file qdec_reg.h + * @version V1.2 + * @date 2020-04-08 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __QDEC_REG_H__ +#define __QDEC_REG_H__ + +#include "bl702.h" + +/* 0x0 : qdec0_ctrl0 */ +#define QDEC0_CTRL0_OFFSET (0x0) +#define QDEC_EN QDEC_EN +#define QDEC_EN_POS (0U) +#define QDEC_EN_LEN (1U) +#define QDEC_EN_MSK (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS) +#define QDEC_EN_UMSK (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)) +#define QDEC_LED_EN QDEC_LED_EN +#define QDEC_LED_EN_POS (1U) +#define QDEC_LED_EN_LEN (1U) +#define QDEC_LED_EN_MSK (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS) +#define QDEC_LED_EN_UMSK (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)) +#define QDEC_LED_POL QDEC_LED_POL +#define QDEC_LED_POL_POS (2U) +#define QDEC_LED_POL_LEN (1U) +#define QDEC_LED_POL_MSK (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS) +#define QDEC_LED_POL_UMSK (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)) +#define QDEC_DEG_EN QDEC_DEG_EN +#define QDEC_DEG_EN_POS (3U) +#define QDEC_DEG_EN_LEN (1U) +#define QDEC_DEG_EN_MSK (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS) +#define QDEC_DEG_EN_UMSK (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)) +#define QDEC_DEG_CNT QDEC_DEG_CNT +#define QDEC_DEG_CNT_POS (4U) +#define QDEC_DEG_CNT_LEN (4U) +#define QDEC_DEG_CNT_MSK (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS) +#define QDEC_DEG_CNT_UMSK (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)) +#define QDEC_SPL_PERIOD QDEC_SPL_PERIOD +#define QDEC_SPL_PERIOD_POS (8U) +#define QDEC_SPL_PERIOD_LEN (4U) +#define QDEC_SPL_PERIOD_MSK (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS) +#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)) +#define QDEC_RPT_PERIOD QDEC_RPT_PERIOD +#define QDEC_RPT_PERIOD_POS (12U) +#define QDEC_RPT_PERIOD_LEN (16U) +#define QDEC_RPT_PERIOD_MSK (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS) +#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)) + +/* 0x4 : qdec0_ctrl1 */ +#define QDEC0_CTRL1_OFFSET (0x4) +#define QDEC_ACC_MODE QDEC_ACC_MODE +#define QDEC_ACC_MODE_POS (0U) +#define QDEC_ACC_MODE_LEN (1U) +#define QDEC_ACC_MODE_MSK (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS) +#define QDEC_ACC_MODE_UMSK (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)) +#define QDEC_SPL_MODE QDEC_SPL_MODE +#define QDEC_SPL_MODE_POS (1U) +#define QDEC_SPL_MODE_LEN (1U) +#define QDEC_SPL_MODE_MSK (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS) +#define QDEC_SPL_MODE_UMSK (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)) +#define QDEC_RPT_MODE QDEC_RPT_MODE +#define QDEC_RPT_MODE_POS (2U) +#define QDEC_RPT_MODE_LEN (1U) +#define QDEC_RPT_MODE_MSK (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS) +#define QDEC_RPT_MODE_UMSK (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)) +#define QDEC_INPUT_SWAP QDEC_INPUT_SWAP +#define QDEC_INPUT_SWAP_POS (3U) +#define QDEC_INPUT_SWAP_LEN (1U) +#define QDEC_INPUT_SWAP_MSK (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS) +#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)) +#define QDEC_LED_PERIOD QDEC_LED_PERIOD +#define QDEC_LED_PERIOD_POS (16U) +#define QDEC_LED_PERIOD_LEN (9U) +#define QDEC_LED_PERIOD_MSK (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS) +#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)) + +/* 0x8 : qdec0_value */ +#define QDEC0_VALUE_OFFSET (0x8) +#define QDEC_ACC1_VAL QDEC_ACC1_VAL +#define QDEC_ACC1_VAL_POS (0U) +#define QDEC_ACC1_VAL_LEN (16U) +#define QDEC_ACC1_VAL_MSK (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS) +#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)) +#define QDEC_ACC2_VAL QDEC_ACC2_VAL +#define QDEC_ACC2_VAL_POS (16U) +#define QDEC_ACC2_VAL_LEN (4U) +#define QDEC_ACC2_VAL_MSK (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS) +#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)) +#define QDEC_SPL_VAL QDEC_SPL_VAL +#define QDEC_SPL_VAL_POS (28U) +#define QDEC_SPL_VAL_LEN (2U) +#define QDEC_SPL_VAL_MSK (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS) +#define QDEC_SPL_VAL_UMSK (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)) + +/* 0x10 : qdec0_int_en */ +#define QDEC0_INT_EN_OFFSET (0x10) +#define QDEC_RPT_RDY_EN QDEC_RPT_RDY_EN +#define QDEC_RPT_RDY_EN_POS (0U) +#define QDEC_RPT_RDY_EN_LEN (1U) +#define QDEC_RPT_RDY_EN_MSK (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS) +#define QDEC_RPT_RDY_EN_UMSK (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)) +#define QDEC_SPL_RDY_EN QDEC_SPL_RDY_EN +#define QDEC_SPL_RDY_EN_POS (1U) +#define QDEC_SPL_RDY_EN_LEN (1U) +#define QDEC_SPL_RDY_EN_MSK (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS) +#define QDEC_SPL_RDY_EN_UMSK (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)) +#define QDEC_DBL_RDY_EN QDEC_DBL_RDY_EN +#define QDEC_DBL_RDY_EN_POS (2U) +#define QDEC_DBL_RDY_EN_LEN (1U) +#define QDEC_DBL_RDY_EN_MSK (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS) +#define QDEC_DBL_RDY_EN_UMSK (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)) +#define QDEC_OVERFLOW_EN QDEC_OVERFLOW_EN +#define QDEC_OVERFLOW_EN_POS (3U) +#define QDEC_OVERFLOW_EN_LEN (1U) +#define QDEC_OVERFLOW_EN_MSK (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS) +#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)) + +/* 0x14 : qdec0_int_sts */ +#define QDEC0_INT_STS_OFFSET (0x14) +#define QDEC_RPT_RDY_STS QDEC_RPT_RDY_STS +#define QDEC_RPT_RDY_STS_POS (0U) +#define QDEC_RPT_RDY_STS_LEN (1U) +#define QDEC_RPT_RDY_STS_MSK (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS) +#define QDEC_RPT_RDY_STS_UMSK (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)) +#define QDEC_SPL_RDY_STS QDEC_SPL_RDY_STS +#define QDEC_SPL_RDY_STS_POS (1U) +#define QDEC_SPL_RDY_STS_LEN (1U) +#define QDEC_SPL_RDY_STS_MSK (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS) +#define QDEC_SPL_RDY_STS_UMSK (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)) +#define QDEC_DBL_RDY_STS QDEC_DBL_RDY_STS +#define QDEC_DBL_RDY_STS_POS (2U) +#define QDEC_DBL_RDY_STS_LEN (1U) +#define QDEC_DBL_RDY_STS_MSK (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS) +#define QDEC_DBL_RDY_STS_UMSK (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)) +#define QDEC_OVERFLOW_STS QDEC_OVERFLOW_STS +#define QDEC_OVERFLOW_STS_POS (3U) +#define QDEC_OVERFLOW_STS_LEN (1U) +#define QDEC_OVERFLOW_STS_MSK (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS) +#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)) + +/* 0x18 : qdec0_int_clr */ +#define QDEC0_INT_CLR_OFFSET (0x18) +#define QDEC_RPT_RDY_CLR QDEC_RPT_RDY_CLR +#define QDEC_RPT_RDY_CLR_POS (0U) +#define QDEC_RPT_RDY_CLR_LEN (1U) +#define QDEC_RPT_RDY_CLR_MSK (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS) +#define QDEC_RPT_RDY_CLR_UMSK (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)) +#define QDEC_SPL_RDY_CLR QDEC_SPL_RDY_CLR +#define QDEC_SPL_RDY_CLR_POS (1U) +#define QDEC_SPL_RDY_CLR_LEN (1U) +#define QDEC_SPL_RDY_CLR_MSK (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS) +#define QDEC_SPL_RDY_CLR_UMSK (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)) +#define QDEC_DBL_RDY_CLR QDEC_DBL_RDY_CLR +#define QDEC_DBL_RDY_CLR_POS (2U) +#define QDEC_DBL_RDY_CLR_LEN (1U) +#define QDEC_DBL_RDY_CLR_MSK (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS) +#define QDEC_DBL_RDY_CLR_UMSK (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)) +#define QDEC_OVERFLOW_CLR QDEC_OVERFLOW_CLR +#define QDEC_OVERFLOW_CLR_POS (3U) +#define QDEC_OVERFLOW_CLR_LEN (1U) +#define QDEC_OVERFLOW_CLR_MSK (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS) +#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)) + +/* 0x40 : qdec1_ctrl0 */ +#define QDEC1_CTRL0_OFFSET (0x40) +#define QDEC_EN QDEC_EN +#define QDEC_EN_POS (0U) +#define QDEC_EN_LEN (1U) +#define QDEC_EN_MSK (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS) +#define QDEC_EN_UMSK (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)) +#define QDEC_LED_EN QDEC_LED_EN +#define QDEC_LED_EN_POS (1U) +#define QDEC_LED_EN_LEN (1U) +#define QDEC_LED_EN_MSK (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS) +#define QDEC_LED_EN_UMSK (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)) +#define QDEC_LED_POL QDEC_LED_POL +#define QDEC_LED_POL_POS (2U) +#define QDEC_LED_POL_LEN (1U) +#define QDEC_LED_POL_MSK (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS) +#define QDEC_LED_POL_UMSK (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)) +#define QDEC_DEG_EN QDEC_DEG_EN +#define QDEC_DEG_EN_POS (3U) +#define QDEC_DEG_EN_LEN (1U) +#define QDEC_DEG_EN_MSK (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS) +#define QDEC_DEG_EN_UMSK (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)) +#define QDEC_DEG_CNT QDEC_DEG_CNT +#define QDEC_DEG_CNT_POS (4U) +#define QDEC_DEG_CNT_LEN (4U) +#define QDEC_DEG_CNT_MSK (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS) +#define QDEC_DEG_CNT_UMSK (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)) +#define QDEC_SPL_PERIOD QDEC_SPL_PERIOD +#define QDEC_SPL_PERIOD_POS (8U) +#define QDEC_SPL_PERIOD_LEN (4U) +#define QDEC_SPL_PERIOD_MSK (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS) +#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)) +#define QDEC_RPT_PERIOD QDEC_RPT_PERIOD +#define QDEC_RPT_PERIOD_POS (12U) +#define QDEC_RPT_PERIOD_LEN (16U) +#define QDEC_RPT_PERIOD_MSK (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS) +#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)) + +/* 0x44 : qdec1_ctrl1 */ +#define QDEC1_CTRL1_OFFSET (0x44) +#define QDEC_ACC_MODE QDEC_ACC_MODE +#define QDEC_ACC_MODE_POS (0U) +#define QDEC_ACC_MODE_LEN (1U) +#define QDEC_ACC_MODE_MSK (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS) +#define QDEC_ACC_MODE_UMSK (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)) +#define QDEC_SPL_MODE QDEC_SPL_MODE +#define QDEC_SPL_MODE_POS (1U) +#define QDEC_SPL_MODE_LEN (1U) +#define QDEC_SPL_MODE_MSK (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS) +#define QDEC_SPL_MODE_UMSK (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)) +#define QDEC_RPT_MODE QDEC_RPT_MODE +#define QDEC_RPT_MODE_POS (2U) +#define QDEC_RPT_MODE_LEN (1U) +#define QDEC_RPT_MODE_MSK (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS) +#define QDEC_RPT_MODE_UMSK (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)) +#define QDEC_INPUT_SWAP QDEC_INPUT_SWAP +#define QDEC_INPUT_SWAP_POS (3U) +#define QDEC_INPUT_SWAP_LEN (1U) +#define QDEC_INPUT_SWAP_MSK (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS) +#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)) +#define QDEC_LED_PERIOD QDEC_LED_PERIOD +#define QDEC_LED_PERIOD_POS (16U) +#define QDEC_LED_PERIOD_LEN (9U) +#define QDEC_LED_PERIOD_MSK (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS) +#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)) + +/* 0x48 : qdec1_value */ +#define QDEC1_VALUE_OFFSET (0x48) +#define QDEC_ACC1_VAL QDEC_ACC1_VAL +#define QDEC_ACC1_VAL_POS (0U) +#define QDEC_ACC1_VAL_LEN (16U) +#define QDEC_ACC1_VAL_MSK (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS) +#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)) +#define QDEC_ACC2_VAL QDEC_ACC2_VAL +#define QDEC_ACC2_VAL_POS (16U) +#define QDEC_ACC2_VAL_LEN (4U) +#define QDEC_ACC2_VAL_MSK (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS) +#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)) +#define QDEC_SPL_VAL QDEC_SPL_VAL +#define QDEC_SPL_VAL_POS (28U) +#define QDEC_SPL_VAL_LEN (2U) +#define QDEC_SPL_VAL_MSK (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS) +#define QDEC_SPL_VAL_UMSK (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)) + +/* 0x50 : qdec1_int_en */ +#define QDEC1_INT_EN_OFFSET (0x50) +#define QDEC_RPT_RDY_EN QDEC_RPT_RDY_EN +#define QDEC_RPT_RDY_EN_POS (0U) +#define QDEC_RPT_RDY_EN_LEN (1U) +#define QDEC_RPT_RDY_EN_MSK (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS) +#define QDEC_RPT_RDY_EN_UMSK (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)) +#define QDEC_SPL_RDY_EN QDEC_SPL_RDY_EN +#define QDEC_SPL_RDY_EN_POS (1U) +#define QDEC_SPL_RDY_EN_LEN (1U) +#define QDEC_SPL_RDY_EN_MSK (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS) +#define QDEC_SPL_RDY_EN_UMSK (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)) +#define QDEC_DBL_RDY_EN QDEC_DBL_RDY_EN +#define QDEC_DBL_RDY_EN_POS (2U) +#define QDEC_DBL_RDY_EN_LEN (1U) +#define QDEC_DBL_RDY_EN_MSK (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS) +#define QDEC_DBL_RDY_EN_UMSK (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)) +#define QDEC_OVERFLOW_EN QDEC_OVERFLOW_EN +#define QDEC_OVERFLOW_EN_POS (3U) +#define QDEC_OVERFLOW_EN_LEN (1U) +#define QDEC_OVERFLOW_EN_MSK (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS) +#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)) + +/* 0x54 : qdec1_int_sts */ +#define QDEC1_INT_STS_OFFSET (0x54) +#define QDEC_RPT_RDY_STS QDEC_RPT_RDY_STS +#define QDEC_RPT_RDY_STS_POS (0U) +#define QDEC_RPT_RDY_STS_LEN (1U) +#define QDEC_RPT_RDY_STS_MSK (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS) +#define QDEC_RPT_RDY_STS_UMSK (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)) +#define QDEC_SPL_RDY_STS QDEC_SPL_RDY_STS +#define QDEC_SPL_RDY_STS_POS (1U) +#define QDEC_SPL_RDY_STS_LEN (1U) +#define QDEC_SPL_RDY_STS_MSK (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS) +#define QDEC_SPL_RDY_STS_UMSK (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)) +#define QDEC_DBL_RDY_STS QDEC_DBL_RDY_STS +#define QDEC_DBL_RDY_STS_POS (2U) +#define QDEC_DBL_RDY_STS_LEN (1U) +#define QDEC_DBL_RDY_STS_MSK (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS) +#define QDEC_DBL_RDY_STS_UMSK (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)) +#define QDEC_OVERFLOW_STS QDEC_OVERFLOW_STS +#define QDEC_OVERFLOW_STS_POS (3U) +#define QDEC_OVERFLOW_STS_LEN (1U) +#define QDEC_OVERFLOW_STS_MSK (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS) +#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)) + +/* 0x58 : qdec1_int_clr */ +#define QDEC1_INT_CLR_OFFSET (0x58) +#define QDEC_RPT_RDY_CLR QDEC_RPT_RDY_CLR +#define QDEC_RPT_RDY_CLR_POS (0U) +#define QDEC_RPT_RDY_CLR_LEN (1U) +#define QDEC_RPT_RDY_CLR_MSK (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS) +#define QDEC_RPT_RDY_CLR_UMSK (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)) +#define QDEC_SPL_RDY_CLR QDEC_SPL_RDY_CLR +#define QDEC_SPL_RDY_CLR_POS (1U) +#define QDEC_SPL_RDY_CLR_LEN (1U) +#define QDEC_SPL_RDY_CLR_MSK (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS) +#define QDEC_SPL_RDY_CLR_UMSK (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)) +#define QDEC_DBL_RDY_CLR QDEC_DBL_RDY_CLR +#define QDEC_DBL_RDY_CLR_POS (2U) +#define QDEC_DBL_RDY_CLR_LEN (1U) +#define QDEC_DBL_RDY_CLR_MSK (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS) +#define QDEC_DBL_RDY_CLR_UMSK (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)) +#define QDEC_OVERFLOW_CLR QDEC_OVERFLOW_CLR +#define QDEC_OVERFLOW_CLR_POS (3U) +#define QDEC_OVERFLOW_CLR_LEN (1U) +#define QDEC_OVERFLOW_CLR_MSK (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS) +#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)) + +/* 0x80 : qdec2_ctrl0 */ +#define QDEC2_CTRL0_OFFSET (0x80) +#define QDEC_EN QDEC_EN +#define QDEC_EN_POS (0U) +#define QDEC_EN_LEN (1U) +#define QDEC_EN_MSK (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS) +#define QDEC_EN_UMSK (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)) +#define QDEC_LED_EN QDEC_LED_EN +#define QDEC_LED_EN_POS (1U) +#define QDEC_LED_EN_LEN (1U) +#define QDEC_LED_EN_MSK (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS) +#define QDEC_LED_EN_UMSK (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)) +#define QDEC_LED_POL QDEC_LED_POL +#define QDEC_LED_POL_POS (2U) +#define QDEC_LED_POL_LEN (1U) +#define QDEC_LED_POL_MSK (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS) +#define QDEC_LED_POL_UMSK (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)) +#define QDEC_DEG_EN QDEC_DEG_EN +#define QDEC_DEG_EN_POS (3U) +#define QDEC_DEG_EN_LEN (1U) +#define QDEC_DEG_EN_MSK (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS) +#define QDEC_DEG_EN_UMSK (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)) +#define QDEC_DEG_CNT QDEC_DEG_CNT +#define QDEC_DEG_CNT_POS (4U) +#define QDEC_DEG_CNT_LEN (4U) +#define QDEC_DEG_CNT_MSK (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS) +#define QDEC_DEG_CNT_UMSK (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)) +#define QDEC_SPL_PERIOD QDEC_SPL_PERIOD +#define QDEC_SPL_PERIOD_POS (8U) +#define QDEC_SPL_PERIOD_LEN (4U) +#define QDEC_SPL_PERIOD_MSK (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS) +#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)) +#define QDEC_RPT_PERIOD QDEC_RPT_PERIOD +#define QDEC_RPT_PERIOD_POS (12U) +#define QDEC_RPT_PERIOD_LEN (16U) +#define QDEC_RPT_PERIOD_MSK (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS) +#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)) + +/* 0x84 : qdec2_ctrl1 */ +#define QDEC2_CTRL1_OFFSET (0x84) +#define QDEC_ACC_MODE QDEC_ACC_MODE +#define QDEC_ACC_MODE_POS (0U) +#define QDEC_ACC_MODE_LEN (1U) +#define QDEC_ACC_MODE_MSK (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS) +#define QDEC_ACC_MODE_UMSK (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)) +#define QDEC_SPL_MODE QDEC_SPL_MODE +#define QDEC_SPL_MODE_POS (1U) +#define QDEC_SPL_MODE_LEN (1U) +#define QDEC_SPL_MODE_MSK (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS) +#define QDEC_SPL_MODE_UMSK (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)) +#define QDEC_RPT_MODE QDEC_RPT_MODE +#define QDEC_RPT_MODE_POS (2U) +#define QDEC_RPT_MODE_LEN (1U) +#define QDEC_RPT_MODE_MSK (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS) +#define QDEC_RPT_MODE_UMSK (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)) +#define QDEC_INPUT_SWAP QDEC_INPUT_SWAP +#define QDEC_INPUT_SWAP_POS (3U) +#define QDEC_INPUT_SWAP_LEN (1U) +#define QDEC_INPUT_SWAP_MSK (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS) +#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)) +#define QDEC_LED_PERIOD QDEC_LED_PERIOD +#define QDEC_LED_PERIOD_POS (16U) +#define QDEC_LED_PERIOD_LEN (9U) +#define QDEC_LED_PERIOD_MSK (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS) +#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)) + +/* 0x88 : qdec2_value */ +#define QDEC2_VALUE_OFFSET (0x88) +#define QDEC_ACC1_VAL QDEC_ACC1_VAL +#define QDEC_ACC1_VAL_POS (0U) +#define QDEC_ACC1_VAL_LEN (16U) +#define QDEC_ACC1_VAL_MSK (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS) +#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)) +#define QDEC_ACC2_VAL QDEC_ACC2_VAL +#define QDEC_ACC2_VAL_POS (16U) +#define QDEC_ACC2_VAL_LEN (4U) +#define QDEC_ACC2_VAL_MSK (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS) +#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)) +#define QDEC_SPL_VAL QDEC_SPL_VAL +#define QDEC_SPL_VAL_POS (28U) +#define QDEC_SPL_VAL_LEN (2U) +#define QDEC_SPL_VAL_MSK (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS) +#define QDEC_SPL_VAL_UMSK (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)) + +/* 0x90 : qdec2_int_en */ +#define QDEC2_INT_EN_OFFSET (0x90) +#define QDEC_RPT_RDY_EN QDEC_RPT_RDY_EN +#define QDEC_RPT_RDY_EN_POS (0U) +#define QDEC_RPT_RDY_EN_LEN (1U) +#define QDEC_RPT_RDY_EN_MSK (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS) +#define QDEC_RPT_RDY_EN_UMSK (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)) +#define QDEC_SPL_RDY_EN QDEC_SPL_RDY_EN +#define QDEC_SPL_RDY_EN_POS (1U) +#define QDEC_SPL_RDY_EN_LEN (1U) +#define QDEC_SPL_RDY_EN_MSK (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS) +#define QDEC_SPL_RDY_EN_UMSK (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)) +#define QDEC_DBL_RDY_EN QDEC_DBL_RDY_EN +#define QDEC_DBL_RDY_EN_POS (2U) +#define QDEC_DBL_RDY_EN_LEN (1U) +#define QDEC_DBL_RDY_EN_MSK (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS) +#define QDEC_DBL_RDY_EN_UMSK (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)) +#define QDEC_OVERFLOW_EN QDEC_OVERFLOW_EN +#define QDEC_OVERFLOW_EN_POS (3U) +#define QDEC_OVERFLOW_EN_LEN (1U) +#define QDEC_OVERFLOW_EN_MSK (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS) +#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)) + +/* 0x94 : qdec2_int_sts */ +#define QDEC2_INT_STS_OFFSET (0x94) +#define QDEC_RPT_RDY_STS QDEC_RPT_RDY_STS +#define QDEC_RPT_RDY_STS_POS (0U) +#define QDEC_RPT_RDY_STS_LEN (1U) +#define QDEC_RPT_RDY_STS_MSK (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS) +#define QDEC_RPT_RDY_STS_UMSK (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)) +#define QDEC_SPL_RDY_STS QDEC_SPL_RDY_STS +#define QDEC_SPL_RDY_STS_POS (1U) +#define QDEC_SPL_RDY_STS_LEN (1U) +#define QDEC_SPL_RDY_STS_MSK (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS) +#define QDEC_SPL_RDY_STS_UMSK (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)) +#define QDEC_DBL_RDY_STS QDEC_DBL_RDY_STS +#define QDEC_DBL_RDY_STS_POS (2U) +#define QDEC_DBL_RDY_STS_LEN (1U) +#define QDEC_DBL_RDY_STS_MSK (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS) +#define QDEC_DBL_RDY_STS_UMSK (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)) +#define QDEC_OVERFLOW_STS QDEC_OVERFLOW_STS +#define QDEC_OVERFLOW_STS_POS (3U) +#define QDEC_OVERFLOW_STS_LEN (1U) +#define QDEC_OVERFLOW_STS_MSK (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS) +#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)) + +/* 0x98 : qdec2_int_clr */ +#define QDEC2_INT_CLR_OFFSET (0x98) +#define QDEC_RPT_RDY_CLR QDEC_RPT_RDY_CLR +#define QDEC_RPT_RDY_CLR_POS (0U) +#define QDEC_RPT_RDY_CLR_LEN (1U) +#define QDEC_RPT_RDY_CLR_MSK (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS) +#define QDEC_RPT_RDY_CLR_UMSK (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)) +#define QDEC_SPL_RDY_CLR QDEC_SPL_RDY_CLR +#define QDEC_SPL_RDY_CLR_POS (1U) +#define QDEC_SPL_RDY_CLR_LEN (1U) +#define QDEC_SPL_RDY_CLR_MSK (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS) +#define QDEC_SPL_RDY_CLR_UMSK (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)) +#define QDEC_DBL_RDY_CLR QDEC_DBL_RDY_CLR +#define QDEC_DBL_RDY_CLR_POS (2U) +#define QDEC_DBL_RDY_CLR_LEN (1U) +#define QDEC_DBL_RDY_CLR_MSK (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS) +#define QDEC_DBL_RDY_CLR_UMSK (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)) +#define QDEC_OVERFLOW_CLR QDEC_OVERFLOW_CLR +#define QDEC_OVERFLOW_CLR_POS (3U) +#define QDEC_OVERFLOW_CLR_LEN (1U) +#define QDEC_OVERFLOW_CLR_MSK (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS) +#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)) + +struct qdec_reg { + /* 0x0 : qdec0_ctrl0 */ + union { + struct + { + uint32_t qdec_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t led_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t led_pol : 1; /* [ 2], r/w, 0x1 */ + uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t spl_period : 4; /* [11: 8], r/w, 0x2 */ + uint32_t rpt_period : 16; /* [27:12], r/w, 0xa */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec0_ctrl0; + + /* 0x4 : qdec0_ctrl1 */ + union { + struct + { + uint32_t acc_mode : 1; /* [ 0], r/w, 0x1 */ + uint32_t spl_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t rpt_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t input_swap : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ + uint32_t led_period : 9; /* [24:16], r/w, 0x0 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec0_ctrl1; + + /* 0x8 : qdec0_value */ + union { + struct + { + uint32_t acc1_val : 16; /* [15: 0], r, 0x0 */ + uint32_t acc2_val : 4; /* [19:16], r, 0x0 */ + uint32_t reserved_20_27 : 8; /* [27:20], rsvd, 0x0 */ + uint32_t spl_val : 2; /* [29:28], r, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec0_value; + + /* 0xc reserved */ + uint8_t RESERVED0xc[4]; + + /* 0x10 : qdec0_int_en */ + union { + struct + { + uint32_t rpt_rdy_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t spl_rdy_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t dbl_rdy_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t overflow_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec0_int_en; + + /* 0x14 : qdec0_int_sts */ + union { + struct + { + uint32_t rpt_rdy_sts : 1; /* [ 0], r, 0x0 */ + uint32_t spl_rdy_sts : 1; /* [ 1], r, 0x0 */ + uint32_t dbl_rdy_sts : 1; /* [ 2], r, 0x0 */ + uint32_t overflow_sts : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec0_int_sts; + + /* 0x18 : qdec0_int_clr */ + union { + struct + { + uint32_t rpt_rdy_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t spl_rdy_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t dbl_rdy_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t overflow_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec0_int_clr; + + /* 0x1c reserved */ + uint8_t RESERVED0x1c[36]; + + /* 0x40 : qdec1_ctrl0 */ + union { + struct + { + uint32_t qdec_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t led_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t led_pol : 1; /* [ 2], r/w, 0x1 */ + uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t spl_period : 4; /* [11: 8], r/w, 0x2 */ + uint32_t rpt_period : 16; /* [27:12], r/w, 0xa */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec1_ctrl0; + + /* 0x44 : qdec1_ctrl1 */ + union { + struct + { + uint32_t acc_mode : 1; /* [ 0], r/w, 0x1 */ + uint32_t spl_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t rpt_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t input_swap : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ + uint32_t led_period : 9; /* [24:16], r/w, 0x0 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec1_ctrl1; + + /* 0x48 : qdec1_value */ + union { + struct + { + uint32_t acc1_val : 16; /* [15: 0], r, 0x0 */ + uint32_t acc2_val : 4; /* [19:16], r, 0x0 */ + uint32_t reserved_20_27 : 8; /* [27:20], rsvd, 0x0 */ + uint32_t spl_val : 2; /* [29:28], r, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec1_value; + + /* 0x4c reserved */ + uint8_t RESERVED0x4c[4]; + + /* 0x50 : qdec1_int_en */ + union { + struct + { + uint32_t rpt_rdy_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t spl_rdy_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t dbl_rdy_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t overflow_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec1_int_en; + + /* 0x54 : qdec1_int_sts */ + union { + struct + { + uint32_t rpt_rdy_sts : 1; /* [ 0], r, 0x0 */ + uint32_t spl_rdy_sts : 1; /* [ 1], r, 0x0 */ + uint32_t dbl_rdy_sts : 1; /* [ 2], r, 0x0 */ + uint32_t overflow_sts : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec1_int_sts; + + /* 0x58 : qdec1_int_clr */ + union { + struct + { + uint32_t rpt_rdy_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t spl_rdy_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t dbl_rdy_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t overflow_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec1_int_clr; + + /* 0x5c reserved */ + uint8_t RESERVED0x5c[36]; + + /* 0x80 : qdec2_ctrl0 */ + union { + struct + { + uint32_t qdec_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t led_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t led_pol : 1; /* [ 2], r/w, 0x1 */ + uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t spl_period : 4; /* [11: 8], r/w, 0x2 */ + uint32_t rpt_period : 16; /* [27:12], r/w, 0xa */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec2_ctrl0; + + /* 0x84 : qdec2_ctrl1 */ + union { + struct + { + uint32_t acc_mode : 1; /* [ 0], r/w, 0x1 */ + uint32_t spl_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t rpt_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t input_swap : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ + uint32_t led_period : 9; /* [24:16], r/w, 0x0 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec2_ctrl1; + + /* 0x88 : qdec2_value */ + union { + struct + { + uint32_t acc1_val : 16; /* [15: 0], r, 0x0 */ + uint32_t acc2_val : 4; /* [19:16], r, 0x0 */ + uint32_t reserved_20_27 : 8; /* [27:20], rsvd, 0x0 */ + uint32_t spl_val : 2; /* [29:28], r, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec2_value; + + /* 0x8c reserved */ + uint8_t RESERVED0x8c[4]; + + /* 0x90 : qdec2_int_en */ + union { + struct + { + uint32_t rpt_rdy_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t spl_rdy_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t dbl_rdy_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t overflow_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec2_int_en; + + /* 0x94 : qdec2_int_sts */ + union { + struct + { + uint32_t rpt_rdy_sts : 1; /* [ 0], r, 0x0 */ + uint32_t spl_rdy_sts : 1; /* [ 1], r, 0x0 */ + uint32_t dbl_rdy_sts : 1; /* [ 2], r, 0x0 */ + uint32_t overflow_sts : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec2_int_sts; + + /* 0x98 : qdec2_int_clr */ + union { + struct + { + uint32_t rpt_rdy_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t spl_rdy_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t dbl_rdy_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t overflow_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } qdec2_int_clr; +}; + +typedef volatile struct qdec_reg qdec_reg_t; + +#endif /* __QDEC_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sec_dbg_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sec_dbg_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..76e5d23ad8a51008098cb50586fc173e65e5fe71 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sec_dbg_reg.h @@ -0,0 +1,217 @@ +/** + ****************************************************************************** + * @file sec_dbg_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SEC_DBG_REG_H__ +#define __SEC_DBG_REG_H__ + +#include "bl702.h" + +/* 0x0 : sd_chip_id_low */ +#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0) +#define SEC_DBG_SD_CHIP_ID_LOW SEC_DBG_SD_CHIP_ID_LOW +#define SEC_DBG_SD_CHIP_ID_LOW_POS (0U) +#define SEC_DBG_SD_CHIP_ID_LOW_LEN (32U) +#define SEC_DBG_SD_CHIP_ID_LOW_MSK (((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS) +#define SEC_DBG_SD_CHIP_ID_LOW_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS)) + +/* 0x4 : sd_chip_id_high */ +#define SEC_DBG_SD_CHIP_ID_HIGH_OFFSET (0x4) +#define SEC_DBG_SD_CHIP_ID_HIGH SEC_DBG_SD_CHIP_ID_HIGH +#define SEC_DBG_SD_CHIP_ID_HIGH_POS (0U) +#define SEC_DBG_SD_CHIP_ID_HIGH_LEN (32U) +#define SEC_DBG_SD_CHIP_ID_HIGH_MSK (((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS) +#define SEC_DBG_SD_CHIP_ID_HIGH_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS)) + +/* 0x8 : sd_wifi_mac_low */ +#define SEC_DBG_SD_WIFI_MAC_LOW_OFFSET (0x8) +#define SEC_DBG_SD_WIFI_MAC_LOW SEC_DBG_SD_WIFI_MAC_LOW +#define SEC_DBG_SD_WIFI_MAC_LOW_POS (0U) +#define SEC_DBG_SD_WIFI_MAC_LOW_LEN (32U) +#define SEC_DBG_SD_WIFI_MAC_LOW_MSK (((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS) +#define SEC_DBG_SD_WIFI_MAC_LOW_UMSK (~(((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS)) + +/* 0xC : sd_wifi_mac_high */ +#define SEC_DBG_SD_WIFI_MAC_HIGH_OFFSET (0xC) +#define SEC_DBG_SD_WIFI_MAC_HIGH SEC_DBG_SD_WIFI_MAC_HIGH +#define SEC_DBG_SD_WIFI_MAC_HIGH_POS (0U) +#define SEC_DBG_SD_WIFI_MAC_HIGH_LEN (32U) +#define SEC_DBG_SD_WIFI_MAC_HIGH_MSK (((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS) +#define SEC_DBG_SD_WIFI_MAC_HIGH_UMSK (~(((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS)) + +/* 0x10 : sd_dbg_pwd_low */ +#define SEC_DBG_SD_DBG_PWD_LOW_OFFSET (0x10) +#define SEC_DBG_SD_DBG_PWD_LOW SEC_DBG_SD_DBG_PWD_LOW +#define SEC_DBG_SD_DBG_PWD_LOW_POS (0U) +#define SEC_DBG_SD_DBG_PWD_LOW_LEN (32U) +#define SEC_DBG_SD_DBG_PWD_LOW_MSK (((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS) +#define SEC_DBG_SD_DBG_PWD_LOW_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS)) + +/* 0x14 : sd_dbg_pwd_high */ +#define SEC_DBG_SD_DBG_PWD_HIGH_OFFSET (0x14) +#define SEC_DBG_SD_DBG_PWD_HIGH SEC_DBG_SD_DBG_PWD_HIGH +#define SEC_DBG_SD_DBG_PWD_HIGH_POS (0U) +#define SEC_DBG_SD_DBG_PWD_HIGH_LEN (32U) +#define SEC_DBG_SD_DBG_PWD_HIGH_MSK (((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS) +#define SEC_DBG_SD_DBG_PWD_HIGH_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS)) + +/* 0x18 : sd_status */ +#define SEC_DBG_SD_STATUS_OFFSET (0x18) +#define SEC_DBG_SD_DBG_PWD_BUSY SEC_DBG_SD_DBG_PWD_BUSY +#define SEC_DBG_SD_DBG_PWD_BUSY_POS (0U) +#define SEC_DBG_SD_DBG_PWD_BUSY_LEN (1U) +#define SEC_DBG_SD_DBG_PWD_BUSY_MSK (((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS) +#define SEC_DBG_SD_DBG_PWD_BUSY_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS)) +#define SEC_DBG_SD_DBG_PWD_TRIG SEC_DBG_SD_DBG_PWD_TRIG +#define SEC_DBG_SD_DBG_PWD_TRIG_POS (1U) +#define SEC_DBG_SD_DBG_PWD_TRIG_LEN (1U) +#define SEC_DBG_SD_DBG_PWD_TRIG_MSK (((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS) +#define SEC_DBG_SD_DBG_PWD_TRIG_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS)) +#define SEC_DBG_SD_DBG_CCI_READ_EN SEC_DBG_SD_DBG_CCI_READ_EN +#define SEC_DBG_SD_DBG_CCI_READ_EN_POS (2U) +#define SEC_DBG_SD_DBG_CCI_READ_EN_LEN (1U) +#define SEC_DBG_SD_DBG_CCI_READ_EN_MSK (((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS) +#define SEC_DBG_SD_DBG_CCI_READ_EN_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS)) +#define SEC_DBG_SD_DBG_CCI_CLK_SEL SEC_DBG_SD_DBG_CCI_CLK_SEL +#define SEC_DBG_SD_DBG_CCI_CLK_SEL_POS (3U) +#define SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN (1U) +#define SEC_DBG_SD_DBG_CCI_CLK_SEL_MSK (((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS) +#define SEC_DBG_SD_DBG_CCI_CLK_SEL_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS)) +#define SEC_DBG_SD_DBG_PWD_CNT SEC_DBG_SD_DBG_PWD_CNT +#define SEC_DBG_SD_DBG_PWD_CNT_POS (4U) +#define SEC_DBG_SD_DBG_PWD_CNT_LEN (20U) +#define SEC_DBG_SD_DBG_PWD_CNT_MSK (((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS) +#define SEC_DBG_SD_DBG_PWD_CNT_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS)) +#define SEC_DBG_SD_DBG_MODE SEC_DBG_SD_DBG_MODE +#define SEC_DBG_SD_DBG_MODE_POS (24U) +#define SEC_DBG_SD_DBG_MODE_LEN (4U) +#define SEC_DBG_SD_DBG_MODE_MSK (((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS) +#define SEC_DBG_SD_DBG_MODE_UMSK (~(((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS)) +#define SEC_DBG_SD_DBG_ENA SEC_DBG_SD_DBG_ENA +#define SEC_DBG_SD_DBG_ENA_POS (28U) +#define SEC_DBG_SD_DBG_ENA_LEN (4U) +#define SEC_DBG_SD_DBG_ENA_MSK (((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS) +#define SEC_DBG_SD_DBG_ENA_UMSK (~(((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS)) + +/* 0x1C : sd_dbg_reserved */ +#define SEC_DBG_SD_DBG_RESERVED_OFFSET (0x1C) +#define SEC_DBG_SD_DBG_RESERVED SEC_DBG_SD_DBG_RESERVED +#define SEC_DBG_SD_DBG_RESERVED_POS (0U) +#define SEC_DBG_SD_DBG_RESERVED_LEN (32U) +#define SEC_DBG_SD_DBG_RESERVED_MSK (((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS) +#define SEC_DBG_SD_DBG_RESERVED_UMSK (~(((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS)) + +struct sec_dbg_reg { + /* 0x0 : sd_chip_id_low */ + union { + struct + { + uint32_t sd_chip_id_low : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_chip_id_low; + + /* 0x4 : sd_chip_id_high */ + union { + struct + { + uint32_t sd_chip_id_high : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_chip_id_high; + + /* 0x8 : sd_wifi_mac_low */ + union { + struct + { + uint32_t sd_wifi_mac_low : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_wifi_mac_low; + + /* 0xC : sd_wifi_mac_high */ + union { + struct + { + uint32_t sd_wifi_mac_high : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_wifi_mac_high; + + /* 0x10 : sd_dbg_pwd_low */ + union { + struct + { + uint32_t sd_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sd_dbg_pwd_low; + + /* 0x14 : sd_dbg_pwd_high */ + union { + struct + { + uint32_t sd_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sd_dbg_pwd_high; + + /* 0x18 : sd_status */ + union { + struct + { + uint32_t sd_dbg_pwd_busy : 1; /* [ 0], r, 0x0 */ + uint32_t sd_dbg_pwd_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t sd_dbg_cci_read_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t sd_dbg_cci_clk_sel : 1; /* [ 3], r/w, 0x0 */ + uint32_t sd_dbg_pwd_cnt : 20; /* [23: 4], r, 0x0 */ + uint32_t sd_dbg_mode : 4; /* [27:24], r, 0x0 */ + uint32_t sd_dbg_ena : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } sd_status; + + /* 0x1C : sd_dbg_reserved */ + union { + struct + { + uint32_t sd_dbg_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } sd_dbg_reserved; +}; + +typedef volatile struct sec_dbg_reg sec_dbg_reg_t; + +#endif /* __SEC_DBG_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sec_eng_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sec_eng_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..5f6515af366d9b8239f92e42391a39b4e2f04156 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sec_eng_reg.h @@ -0,0 +1,3529 @@ +/** + ****************************************************************************** + * @file sec_eng_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SEC_ENG_REG_H__ +#define __SEC_ENG_REG_H__ + +#include "bl702.h" + +/* 0x0 : se_sha_0_ctrl */ +#define SEC_ENG_SE_SHA_0_CTRL_OFFSET (0x0) +#define SEC_ENG_SE_SHA_0_BUSY SEC_ENG_SE_SHA_0_BUSY +#define SEC_ENG_SE_SHA_0_BUSY_POS (0U) +#define SEC_ENG_SE_SHA_0_BUSY_LEN (1U) +#define SEC_ENG_SE_SHA_0_BUSY_MSK (((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS) +#define SEC_ENG_SE_SHA_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS)) +#define SEC_ENG_SE_SHA_0_TRIG_1T SEC_ENG_SE_SHA_0_TRIG_1T +#define SEC_ENG_SE_SHA_0_TRIG_1T_POS (1U) +#define SEC_ENG_SE_SHA_0_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_SHA_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS) +#define SEC_ENG_SE_SHA_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS)) +#define SEC_ENG_SE_SHA_0_MODE SEC_ENG_SE_SHA_0_MODE +#define SEC_ENG_SE_SHA_0_MODE_POS (2U) +#define SEC_ENG_SE_SHA_0_MODE_LEN (3U) +#define SEC_ENG_SE_SHA_0_MODE_MSK (((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS) +#define SEC_ENG_SE_SHA_0_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS)) +#define SEC_ENG_SE_SHA_0_EN SEC_ENG_SE_SHA_0_EN +#define SEC_ENG_SE_SHA_0_EN_POS (5U) +#define SEC_ENG_SE_SHA_0_EN_LEN (1U) +#define SEC_ENG_SE_SHA_0_EN_MSK (((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS) +#define SEC_ENG_SE_SHA_0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS)) +#define SEC_ENG_SE_SHA_0_HASH_SEL SEC_ENG_SE_SHA_0_HASH_SEL +#define SEC_ENG_SE_SHA_0_HASH_SEL_POS (6U) +#define SEC_ENG_SE_SHA_0_HASH_SEL_LEN (1U) +#define SEC_ENG_SE_SHA_0_HASH_SEL_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS) +#define SEC_ENG_SE_SHA_0_HASH_SEL_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS)) +#define SEC_ENG_SE_SHA_0_INT SEC_ENG_SE_SHA_0_INT +#define SEC_ENG_SE_SHA_0_INT_POS (8U) +#define SEC_ENG_SE_SHA_0_INT_LEN (1U) +#define SEC_ENG_SE_SHA_0_INT_MSK (((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS) +#define SEC_ENG_SE_SHA_0_INT_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS)) +#define SEC_ENG_SE_SHA_0_INT_CLR_1T SEC_ENG_SE_SHA_0_INT_CLR_1T +#define SEC_ENG_SE_SHA_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_SHA_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_SHA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_SHA_0_INT_SET_1T SEC_ENG_SE_SHA_0_INT_SET_1T +#define SEC_ENG_SE_SHA_0_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_SHA_0_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_SHA_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS) +#define SEC_ENG_SE_SHA_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS)) +#define SEC_ENG_SE_SHA_0_INT_MASK SEC_ENG_SE_SHA_0_INT_MASK +#define SEC_ENG_SE_SHA_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_SHA_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_SHA_0_INT_MASK_MSK (((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS) +#define SEC_ENG_SE_SHA_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS)) +#define SEC_ENG_SE_SHA_0_LINK_MODE SEC_ENG_SE_SHA_0_LINK_MODE +#define SEC_ENG_SE_SHA_0_LINK_MODE_POS (15U) +#define SEC_ENG_SE_SHA_0_LINK_MODE_LEN (1U) +#define SEC_ENG_SE_SHA_0_LINK_MODE_MSK (((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS) +#define SEC_ENG_SE_SHA_0_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS)) +#define SEC_ENG_SE_SHA_0_MSG_LEN SEC_ENG_SE_SHA_0_MSG_LEN +#define SEC_ENG_SE_SHA_0_MSG_LEN_POS (16U) +#define SEC_ENG_SE_SHA_0_MSG_LEN_LEN (16U) +#define SEC_ENG_SE_SHA_0_MSG_LEN_MSK (((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS) +#define SEC_ENG_SE_SHA_0_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS)) + +/* 0x4 : se_sha_0_msa */ +#define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4) +#define SEC_ENG_SE_SHA_0_MSA SEC_ENG_SE_SHA_0_MSA +#define SEC_ENG_SE_SHA_0_MSA_POS (0U) +#define SEC_ENG_SE_SHA_0_MSA_LEN (32U) +#define SEC_ENG_SE_SHA_0_MSA_MSK (((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS) +#define SEC_ENG_SE_SHA_0_MSA_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS)) + +/* 0x8 : se_sha_0_status */ +#define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8) +#define SEC_ENG_SE_SHA_0_STATUS SEC_ENG_SE_SHA_0_STATUS +#define SEC_ENG_SE_SHA_0_STATUS_POS (0U) +#define SEC_ENG_SE_SHA_0_STATUS_LEN (32U) +#define SEC_ENG_SE_SHA_0_STATUS_MSK (((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS) +#define SEC_ENG_SE_SHA_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS)) + +/* 0xC : se_sha_0_endian */ +#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET (0xC) +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN SEC_ENG_SE_SHA_0_DOUT_ENDIAN +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS (0U) +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN (1U) +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS) +#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS)) + +/* 0x10 : se_sha_0_hash_l_0 */ +#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10) +#define SEC_ENG_SE_SHA_0_HASH_L_0 SEC_ENG_SE_SHA_0_HASH_L_0 +#define SEC_ENG_SE_SHA_0_HASH_L_0_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_0_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_0_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_0_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS)) + +/* 0x14 : se_sha_0_hash_l_1 */ +#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14) +#define SEC_ENG_SE_SHA_0_HASH_L_1 SEC_ENG_SE_SHA_0_HASH_L_1 +#define SEC_ENG_SE_SHA_0_HASH_L_1_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_1_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_1_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_1_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS)) + +/* 0x18 : se_sha_0_hash_l_2 */ +#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18) +#define SEC_ENG_SE_SHA_0_HASH_L_2 SEC_ENG_SE_SHA_0_HASH_L_2 +#define SEC_ENG_SE_SHA_0_HASH_L_2_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_2_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_2_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_2_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS)) + +/* 0x1C : se_sha_0_hash_l_3 */ +#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C) +#define SEC_ENG_SE_SHA_0_HASH_L_3 SEC_ENG_SE_SHA_0_HASH_L_3 +#define SEC_ENG_SE_SHA_0_HASH_L_3_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_3_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_3_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_3_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS)) + +/* 0x20 : se_sha_0_hash_l_4 */ +#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20) +#define SEC_ENG_SE_SHA_0_HASH_L_4 SEC_ENG_SE_SHA_0_HASH_L_4 +#define SEC_ENG_SE_SHA_0_HASH_L_4_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_4_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_4_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_4_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS)) + +/* 0x24 : se_sha_0_hash_l_5 */ +#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24) +#define SEC_ENG_SE_SHA_0_HASH_L_5 SEC_ENG_SE_SHA_0_HASH_L_5 +#define SEC_ENG_SE_SHA_0_HASH_L_5_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_5_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_5_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_5_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS)) + +/* 0x28 : se_sha_0_hash_l_6 */ +#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28) +#define SEC_ENG_SE_SHA_0_HASH_L_6 SEC_ENG_SE_SHA_0_HASH_L_6 +#define SEC_ENG_SE_SHA_0_HASH_L_6_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_6_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_6_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_6_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS)) + +/* 0x2C : se_sha_0_hash_l_7 */ +#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C) +#define SEC_ENG_SE_SHA_0_HASH_L_7 SEC_ENG_SE_SHA_0_HASH_L_7 +#define SEC_ENG_SE_SHA_0_HASH_L_7_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_L_7_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_L_7_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS) +#define SEC_ENG_SE_SHA_0_HASH_L_7_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS)) + +/* 0x30 : se_sha_0_hash_h_0 */ +#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30) +#define SEC_ENG_SE_SHA_0_HASH_H_0 SEC_ENG_SE_SHA_0_HASH_H_0 +#define SEC_ENG_SE_SHA_0_HASH_H_0_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_0_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_0_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_0_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS)) + +/* 0x34 : se_sha_0_hash_h_1 */ +#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34) +#define SEC_ENG_SE_SHA_0_HASH_H_1 SEC_ENG_SE_SHA_0_HASH_H_1 +#define SEC_ENG_SE_SHA_0_HASH_H_1_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_1_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_1_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_1_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS)) + +/* 0x38 : se_sha_0_hash_h_2 */ +#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38) +#define SEC_ENG_SE_SHA_0_HASH_H_2 SEC_ENG_SE_SHA_0_HASH_H_2 +#define SEC_ENG_SE_SHA_0_HASH_H_2_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_2_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_2_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_2_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS)) + +/* 0x3C : se_sha_0_hash_h_3 */ +#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C) +#define SEC_ENG_SE_SHA_0_HASH_H_3 SEC_ENG_SE_SHA_0_HASH_H_3 +#define SEC_ENG_SE_SHA_0_HASH_H_3_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_3_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_3_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_3_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS)) + +/* 0x40 : se_sha_0_hash_h_4 */ +#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40) +#define SEC_ENG_SE_SHA_0_HASH_H_4 SEC_ENG_SE_SHA_0_HASH_H_4 +#define SEC_ENG_SE_SHA_0_HASH_H_4_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_4_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_4_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_4_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS)) + +/* 0x44 : se_sha_0_hash_h_5 */ +#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44) +#define SEC_ENG_SE_SHA_0_HASH_H_5 SEC_ENG_SE_SHA_0_HASH_H_5 +#define SEC_ENG_SE_SHA_0_HASH_H_5_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_5_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_5_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_5_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS)) + +/* 0x48 : se_sha_0_hash_h_6 */ +#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48) +#define SEC_ENG_SE_SHA_0_HASH_H_6 SEC_ENG_SE_SHA_0_HASH_H_6 +#define SEC_ENG_SE_SHA_0_HASH_H_6_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_6_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_6_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_6_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS)) + +/* 0x4C : se_sha_0_hash_h_7 */ +#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C) +#define SEC_ENG_SE_SHA_0_HASH_H_7 SEC_ENG_SE_SHA_0_HASH_H_7 +#define SEC_ENG_SE_SHA_0_HASH_H_7_POS (0U) +#define SEC_ENG_SE_SHA_0_HASH_H_7_LEN (32U) +#define SEC_ENG_SE_SHA_0_HASH_H_7_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS) +#define SEC_ENG_SE_SHA_0_HASH_H_7_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS)) + +/* 0x50 : se_sha_0_link */ +#define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50) +#define SEC_ENG_SE_SHA_0_LCA SEC_ENG_SE_SHA_0_LCA +#define SEC_ENG_SE_SHA_0_LCA_POS (0U) +#define SEC_ENG_SE_SHA_0_LCA_LEN (32U) +#define SEC_ENG_SE_SHA_0_LCA_MSK (((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS) +#define SEC_ENG_SE_SHA_0_LCA_UMSK (~(((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS)) + +/* 0xFC : se_sha_0_ctrl_prot */ +#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC) +#define SEC_ENG_SE_SHA_PROT_EN SEC_ENG_SE_SHA_PROT_EN +#define SEC_ENG_SE_SHA_PROT_EN_POS (0U) +#define SEC_ENG_SE_SHA_PROT_EN_LEN (1U) +#define SEC_ENG_SE_SHA_PROT_EN_MSK (((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS) +#define SEC_ENG_SE_SHA_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS)) +#define SEC_ENG_SE_SHA_ID0_EN SEC_ENG_SE_SHA_ID0_EN +#define SEC_ENG_SE_SHA_ID0_EN_POS (1U) +#define SEC_ENG_SE_SHA_ID0_EN_LEN (1U) +#define SEC_ENG_SE_SHA_ID0_EN_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS) +#define SEC_ENG_SE_SHA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)) +#define SEC_ENG_SE_SHA_ID1_EN SEC_ENG_SE_SHA_ID1_EN +#define SEC_ENG_SE_SHA_ID1_EN_POS (2U) +#define SEC_ENG_SE_SHA_ID1_EN_LEN (1U) +#define SEC_ENG_SE_SHA_ID1_EN_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS) +#define SEC_ENG_SE_SHA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)) + +/* 0x100 : se_aes_0_ctrl */ +#define SEC_ENG_SE_AES_0_CTRL_OFFSET (0x100) +#define SEC_ENG_SE_AES_0_BUSY SEC_ENG_SE_AES_0_BUSY +#define SEC_ENG_SE_AES_0_BUSY_POS (0U) +#define SEC_ENG_SE_AES_0_BUSY_LEN (1U) +#define SEC_ENG_SE_AES_0_BUSY_MSK (((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS) +#define SEC_ENG_SE_AES_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS)) +#define SEC_ENG_SE_AES_0_TRIG_1T SEC_ENG_SE_AES_0_TRIG_1T +#define SEC_ENG_SE_AES_0_TRIG_1T_POS (1U) +#define SEC_ENG_SE_AES_0_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_AES_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS) +#define SEC_ENG_SE_AES_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS)) +#define SEC_ENG_SE_AES_0_EN SEC_ENG_SE_AES_0_EN +#define SEC_ENG_SE_AES_0_EN_POS (2U) +#define SEC_ENG_SE_AES_0_EN_LEN (1U) +#define SEC_ENG_SE_AES_0_EN_MSK (((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS) +#define SEC_ENG_SE_AES_0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS)) +#define SEC_ENG_SE_AES_0_MODE SEC_ENG_SE_AES_0_MODE +#define SEC_ENG_SE_AES_0_MODE_POS (3U) +#define SEC_ENG_SE_AES_0_MODE_LEN (2U) +#define SEC_ENG_SE_AES_0_MODE_MSK (((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS) +#define SEC_ENG_SE_AES_0_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS)) +#define SEC_ENG_SE_AES_0_DEC_EN SEC_ENG_SE_AES_0_DEC_EN +#define SEC_ENG_SE_AES_0_DEC_EN_POS (5U) +#define SEC_ENG_SE_AES_0_DEC_EN_LEN (1U) +#define SEC_ENG_SE_AES_0_DEC_EN_MSK (((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS) +#define SEC_ENG_SE_AES_0_DEC_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS)) +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL SEC_ENG_SE_AES_0_DEC_KEY_SEL +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS (6U) +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN (1U) +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS) +#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS)) +#define SEC_ENG_SE_AES_0_HW_KEY_EN SEC_ENG_SE_AES_0_HW_KEY_EN +#define SEC_ENG_SE_AES_0_HW_KEY_EN_POS (7U) +#define SEC_ENG_SE_AES_0_HW_KEY_EN_LEN (1U) +#define SEC_ENG_SE_AES_0_HW_KEY_EN_MSK (((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS) +#define SEC_ENG_SE_AES_0_HW_KEY_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS)) +#define SEC_ENG_SE_AES_0_INT SEC_ENG_SE_AES_0_INT +#define SEC_ENG_SE_AES_0_INT_POS (8U) +#define SEC_ENG_SE_AES_0_INT_LEN (1U) +#define SEC_ENG_SE_AES_0_INT_MSK (((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS) +#define SEC_ENG_SE_AES_0_INT_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS)) +#define SEC_ENG_SE_AES_0_INT_CLR_1T SEC_ENG_SE_AES_0_INT_CLR_1T +#define SEC_ENG_SE_AES_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_AES_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_AES_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_AES_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_AES_0_INT_SET_1T SEC_ENG_SE_AES_0_INT_SET_1T +#define SEC_ENG_SE_AES_0_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_AES_0_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_AES_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS) +#define SEC_ENG_SE_AES_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS)) +#define SEC_ENG_SE_AES_0_INT_MASK SEC_ENG_SE_AES_0_INT_MASK +#define SEC_ENG_SE_AES_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_AES_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_AES_0_INT_MASK_MSK (((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS) +#define SEC_ENG_SE_AES_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS)) +#define SEC_ENG_SE_AES_0_BLOCK_MODE SEC_ENG_SE_AES_0_BLOCK_MODE +#define SEC_ENG_SE_AES_0_BLOCK_MODE_POS (12U) +#define SEC_ENG_SE_AES_0_BLOCK_MODE_LEN (2U) +#define SEC_ENG_SE_AES_0_BLOCK_MODE_MSK (((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS) +#define SEC_ENG_SE_AES_0_BLOCK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS)) +#define SEC_ENG_SE_AES_0_IV_SEL SEC_ENG_SE_AES_0_IV_SEL +#define SEC_ENG_SE_AES_0_IV_SEL_POS (14U) +#define SEC_ENG_SE_AES_0_IV_SEL_LEN (1U) +#define SEC_ENG_SE_AES_0_IV_SEL_MSK (((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS) +#define SEC_ENG_SE_AES_0_IV_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS)) +#define SEC_ENG_SE_AES_0_LINK_MODE SEC_ENG_SE_AES_0_LINK_MODE +#define SEC_ENG_SE_AES_0_LINK_MODE_POS (15U) +#define SEC_ENG_SE_AES_0_LINK_MODE_LEN (1U) +#define SEC_ENG_SE_AES_0_LINK_MODE_MSK (((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS) +#define SEC_ENG_SE_AES_0_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS)) +#define SEC_ENG_SE_AES_0_MSG_LEN SEC_ENG_SE_AES_0_MSG_LEN +#define SEC_ENG_SE_AES_0_MSG_LEN_POS (16U) +#define SEC_ENG_SE_AES_0_MSG_LEN_LEN (16U) +#define SEC_ENG_SE_AES_0_MSG_LEN_MSK (((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS) +#define SEC_ENG_SE_AES_0_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS)) + +/* 0x104 : se_aes_0_msa */ +#define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104) +#define SEC_ENG_SE_AES_0_MSA SEC_ENG_SE_AES_0_MSA +#define SEC_ENG_SE_AES_0_MSA_POS (0U) +#define SEC_ENG_SE_AES_0_MSA_LEN (32U) +#define SEC_ENG_SE_AES_0_MSA_MSK (((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS) +#define SEC_ENG_SE_AES_0_MSA_UMSK (~(((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS)) + +/* 0x108 : se_aes_0_mda */ +#define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108) +#define SEC_ENG_SE_AES_0_MDA SEC_ENG_SE_AES_0_MDA +#define SEC_ENG_SE_AES_0_MDA_POS (0U) +#define SEC_ENG_SE_AES_0_MDA_LEN (32U) +#define SEC_ENG_SE_AES_0_MDA_MSK (((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS) +#define SEC_ENG_SE_AES_0_MDA_UMSK (~(((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS)) + +/* 0x10C : se_aes_0_status */ +#define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C) +#define SEC_ENG_SE_AES_0_STATUS SEC_ENG_SE_AES_0_STATUS +#define SEC_ENG_SE_AES_0_STATUS_POS (0U) +#define SEC_ENG_SE_AES_0_STATUS_LEN (32U) +#define SEC_ENG_SE_AES_0_STATUS_MSK (((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS) +#define SEC_ENG_SE_AES_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS)) + +/* 0x110 : se_aes_0_iv_0 */ +#define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110) +#define SEC_ENG_SE_AES_0_IV_0 SEC_ENG_SE_AES_0_IV_0 +#define SEC_ENG_SE_AES_0_IV_0_POS (0U) +#define SEC_ENG_SE_AES_0_IV_0_LEN (32U) +#define SEC_ENG_SE_AES_0_IV_0_MSK (((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS) +#define SEC_ENG_SE_AES_0_IV_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS)) + +/* 0x114 : se_aes_0_iv_1 */ +#define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114) +#define SEC_ENG_SE_AES_0_IV_1 SEC_ENG_SE_AES_0_IV_1 +#define SEC_ENG_SE_AES_0_IV_1_POS (0U) +#define SEC_ENG_SE_AES_0_IV_1_LEN (32U) +#define SEC_ENG_SE_AES_0_IV_1_MSK (((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS) +#define SEC_ENG_SE_AES_0_IV_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS)) + +/* 0x118 : se_aes_0_iv_2 */ +#define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118) +#define SEC_ENG_SE_AES_0_IV_2 SEC_ENG_SE_AES_0_IV_2 +#define SEC_ENG_SE_AES_0_IV_2_POS (0U) +#define SEC_ENG_SE_AES_0_IV_2_LEN (32U) +#define SEC_ENG_SE_AES_0_IV_2_MSK (((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS) +#define SEC_ENG_SE_AES_0_IV_2_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS)) + +/* 0x11C : se_aes_0_iv_3 */ +#define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C) +#define SEC_ENG_SE_AES_0_IV_3 SEC_ENG_SE_AES_0_IV_3 +#define SEC_ENG_SE_AES_0_IV_3_POS (0U) +#define SEC_ENG_SE_AES_0_IV_3_LEN (32U) +#define SEC_ENG_SE_AES_0_IV_3_MSK (((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS) +#define SEC_ENG_SE_AES_0_IV_3_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS)) + +/* 0x120 : se_aes_0_key_0 */ +#define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120) +#define SEC_ENG_SE_AES_0_KEY_0 SEC_ENG_SE_AES_0_KEY_0 +#define SEC_ENG_SE_AES_0_KEY_0_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_0_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_0_MSK (((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS) +#define SEC_ENG_SE_AES_0_KEY_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS)) + +/* 0x124 : se_aes_0_key_1 */ +#define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124) +#define SEC_ENG_SE_AES_0_KEY_1 SEC_ENG_SE_AES_0_KEY_1 +#define SEC_ENG_SE_AES_0_KEY_1_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_1_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_1_MSK (((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS) +#define SEC_ENG_SE_AES_0_KEY_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS)) + +/* 0x128 : se_aes_0_key_2 */ +#define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128) +#define SEC_ENG_SE_AES_0_KEY_2 SEC_ENG_SE_AES_0_KEY_2 +#define SEC_ENG_SE_AES_0_KEY_2_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_2_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_2_MSK (((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS) +#define SEC_ENG_SE_AES_0_KEY_2_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS)) + +/* 0x12C : se_aes_0_key_3 */ +#define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C) +#define SEC_ENG_SE_AES_0_KEY_3 SEC_ENG_SE_AES_0_KEY_3 +#define SEC_ENG_SE_AES_0_KEY_3_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_3_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_3_MSK (((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS) +#define SEC_ENG_SE_AES_0_KEY_3_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS)) + +/* 0x130 : se_aes_0_key_4 */ +#define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130) +#define SEC_ENG_SE_AES_0_KEY_4 SEC_ENG_SE_AES_0_KEY_4 +#define SEC_ENG_SE_AES_0_KEY_4_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_4_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_4_MSK (((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS) +#define SEC_ENG_SE_AES_0_KEY_4_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS)) + +/* 0x134 : se_aes_0_key_5 */ +#define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134) +#define SEC_ENG_SE_AES_0_KEY_5 SEC_ENG_SE_AES_0_KEY_5 +#define SEC_ENG_SE_AES_0_KEY_5_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_5_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_5_MSK (((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS) +#define SEC_ENG_SE_AES_0_KEY_5_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS)) + +/* 0x138 : se_aes_0_key_6 */ +#define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138) +#define SEC_ENG_SE_AES_0_KEY_6 SEC_ENG_SE_AES_0_KEY_6 +#define SEC_ENG_SE_AES_0_KEY_6_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_6_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_6_MSK (((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS) +#define SEC_ENG_SE_AES_0_KEY_6_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS)) + +/* 0x13C : se_aes_0_key_7 */ +#define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C) +#define SEC_ENG_SE_AES_0_KEY_7 SEC_ENG_SE_AES_0_KEY_7 +#define SEC_ENG_SE_AES_0_KEY_7_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_7_LEN (32U) +#define SEC_ENG_SE_AES_0_KEY_7_MSK (((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS) +#define SEC_ENG_SE_AES_0_KEY_7_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS)) + +/* 0x140 : se_aes_0_key_sel_0 */ +#define SEC_ENG_SE_AES_0_KEY_SEL_0_OFFSET (0x140) +#define SEC_ENG_SE_AES_0_KEY_SEL_0 SEC_ENG_SE_AES_0_KEY_SEL_0 +#define SEC_ENG_SE_AES_0_KEY_SEL_0_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_SEL_0_LEN (2U) +#define SEC_ENG_SE_AES_0_KEY_SEL_0_MSK (((1U << SEC_ENG_SE_AES_0_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_0_POS) +#define SEC_ENG_SE_AES_0_KEY_SEL_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_0_POS)) + +/* 0x144 : se_aes_0_key_sel_1 */ +#define SEC_ENG_SE_AES_0_KEY_SEL_1_OFFSET (0x144) +#define SEC_ENG_SE_AES_0_KEY_SEL_1 SEC_ENG_SE_AES_0_KEY_SEL_1 +#define SEC_ENG_SE_AES_0_KEY_SEL_1_POS (0U) +#define SEC_ENG_SE_AES_0_KEY_SEL_1_LEN (2U) +#define SEC_ENG_SE_AES_0_KEY_SEL_1_MSK (((1U << SEC_ENG_SE_AES_0_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_1_POS) +#define SEC_ENG_SE_AES_0_KEY_SEL_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_1_POS)) + +/* 0x148 : se_aes_0_endian */ +#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET (0x148) +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN SEC_ENG_SE_AES_0_DOUT_ENDIAN +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS (0U) +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS) +#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS)) +#define SEC_ENG_SE_AES_0_DIN_ENDIAN SEC_ENG_SE_AES_0_DIN_ENDIAN +#define SEC_ENG_SE_AES_0_DIN_ENDIAN_POS (1U) +#define SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_0_DIN_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS) +#define SEC_ENG_SE_AES_0_DIN_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS)) +#define SEC_ENG_SE_AES_0_KEY_ENDIAN SEC_ENG_SE_AES_0_KEY_ENDIAN +#define SEC_ENG_SE_AES_0_KEY_ENDIAN_POS (2U) +#define SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_0_KEY_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS) +#define SEC_ENG_SE_AES_0_KEY_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS)) +#define SEC_ENG_SE_AES_0_IV_ENDIAN SEC_ENG_SE_AES_0_IV_ENDIAN +#define SEC_ENG_SE_AES_0_IV_ENDIAN_POS (3U) +#define SEC_ENG_SE_AES_0_IV_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_0_IV_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS) +#define SEC_ENG_SE_AES_0_IV_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS)) +#define SEC_ENG_SE_AES_0_CTR_LEN SEC_ENG_SE_AES_0_CTR_LEN +#define SEC_ENG_SE_AES_0_CTR_LEN_POS (30U) +#define SEC_ENG_SE_AES_0_CTR_LEN_LEN (2U) +#define SEC_ENG_SE_AES_0_CTR_LEN_MSK (((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS) +#define SEC_ENG_SE_AES_0_CTR_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS)) + +/* 0x14C : se_aes_0_sboot */ +#define SEC_ENG_SE_AES_0_SBOOT_OFFSET (0x14C) +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL SEC_ENG_SE_AES_0_SBOOT_KEY_SEL +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS (0U) +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN (1U) +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS) +#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS)) + +/* 0x150 : se_aes_0_link */ +#define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150) +#define SEC_ENG_SE_AES_0_LCA SEC_ENG_SE_AES_0_LCA +#define SEC_ENG_SE_AES_0_LCA_POS (0U) +#define SEC_ENG_SE_AES_0_LCA_LEN (32U) +#define SEC_ENG_SE_AES_0_LCA_MSK (((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS) +#define SEC_ENG_SE_AES_0_LCA_UMSK (~(((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS)) + +/* 0x1FC : se_aes_0_ctrl_prot */ +#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC) +#define SEC_ENG_SE_AES_PROT_EN SEC_ENG_SE_AES_PROT_EN +#define SEC_ENG_SE_AES_PROT_EN_POS (0U) +#define SEC_ENG_SE_AES_PROT_EN_LEN (1U) +#define SEC_ENG_SE_AES_PROT_EN_MSK (((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS) +#define SEC_ENG_SE_AES_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS)) +#define SEC_ENG_SE_AES_ID0_EN SEC_ENG_SE_AES_ID0_EN +#define SEC_ENG_SE_AES_ID0_EN_POS (1U) +#define SEC_ENG_SE_AES_ID0_EN_LEN (1U) +#define SEC_ENG_SE_AES_ID0_EN_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS) +#define SEC_ENG_SE_AES_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)) +#define SEC_ENG_SE_AES_ID1_EN SEC_ENG_SE_AES_ID1_EN +#define SEC_ENG_SE_AES_ID1_EN_POS (2U) +#define SEC_ENG_SE_AES_ID1_EN_LEN (1U) +#define SEC_ENG_SE_AES_ID1_EN_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS) +#define SEC_ENG_SE_AES_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)) + +/* 0x200 : se_trng_0_ctrl_0 */ +#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET (0x200) +#define SEC_ENG_SE_TRNG_0_BUSY SEC_ENG_SE_TRNG_0_BUSY +#define SEC_ENG_SE_TRNG_0_BUSY_POS (0U) +#define SEC_ENG_SE_TRNG_0_BUSY_LEN (1U) +#define SEC_ENG_SE_TRNG_0_BUSY_MSK (((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS) +#define SEC_ENG_SE_TRNG_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS)) +#define SEC_ENG_SE_TRNG_0_TRIG_1T SEC_ENG_SE_TRNG_0_TRIG_1T +#define SEC_ENG_SE_TRNG_0_TRIG_1T_POS (1U) +#define SEC_ENG_SE_TRNG_0_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS) +#define SEC_ENG_SE_TRNG_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS)) +#define SEC_ENG_SE_TRNG_0_EN SEC_ENG_SE_TRNG_0_EN +#define SEC_ENG_SE_TRNG_0_EN_POS (2U) +#define SEC_ENG_SE_TRNG_0_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS) +#define SEC_ENG_SE_TRNG_0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS)) +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T SEC_ENG_SE_TRNG_0_DOUT_CLR_1T +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS (3U) +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS)) +#define SEC_ENG_SE_TRNG_0_HT_ERROR SEC_ENG_SE_TRNG_0_HT_ERROR +#define SEC_ENG_SE_TRNG_0_HT_ERROR_POS (4U) +#define SEC_ENG_SE_TRNG_0_HT_ERROR_LEN (1U) +#define SEC_ENG_SE_TRNG_0_HT_ERROR_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS) +#define SEC_ENG_SE_TRNG_0_HT_ERROR_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS)) +#define SEC_ENG_SE_TRNG_0_INT SEC_ENG_SE_TRNG_0_INT +#define SEC_ENG_SE_TRNG_0_INT_POS (8U) +#define SEC_ENG_SE_TRNG_0_INT_LEN (1U) +#define SEC_ENG_SE_TRNG_0_INT_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS) +#define SEC_ENG_SE_TRNG_0_INT_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS)) +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T SEC_ENG_SE_TRNG_0_INT_CLR_1T +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_TRNG_0_INT_SET_1T SEC_ENG_SE_TRNG_0_INT_SET_1T +#define SEC_ENG_SE_TRNG_0_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS) +#define SEC_ENG_SE_TRNG_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS)) +#define SEC_ENG_SE_TRNG_0_INT_MASK SEC_ENG_SE_TRNG_0_INT_MASK +#define SEC_ENG_SE_TRNG_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_TRNG_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_TRNG_0_INT_MASK_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS) +#define SEC_ENG_SE_TRNG_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS)) +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS (13U) +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN (1U) +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS) +#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS)) +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED SEC_ENG_SE_TRNG_0_MANUAL_RESEED +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS (14U) +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN (1U) +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS) +#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS)) +#define SEC_ENG_SE_TRNG_0_MANUAL_EN SEC_ENG_SE_TRNG_0_MANUAL_EN +#define SEC_ENG_SE_TRNG_0_MANUAL_EN_POS (15U) +#define SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_MANUAL_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS) +#define SEC_ENG_SE_TRNG_0_MANUAL_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS)) + +/* 0x204 : se_trng_0_status */ +#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204) +#define SEC_ENG_SE_TRNG_0_STATUS SEC_ENG_SE_TRNG_0_STATUS +#define SEC_ENG_SE_TRNG_0_STATUS_POS (0U) +#define SEC_ENG_SE_TRNG_0_STATUS_LEN (32U) +#define SEC_ENG_SE_TRNG_0_STATUS_MSK (((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS) +#define SEC_ENG_SE_TRNG_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS)) + +/* 0x208 : se_trng_0_dout_0 */ +#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208) +#define SEC_ENG_SE_TRNG_0_DOUT_0 SEC_ENG_SE_TRNG_0_DOUT_0 +#define SEC_ENG_SE_TRNG_0_DOUT_0_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_0_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_0_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS)) + +/* 0x20C : se_trng_0_dout_1 */ +#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C) +#define SEC_ENG_SE_TRNG_0_DOUT_1 SEC_ENG_SE_TRNG_0_DOUT_1 +#define SEC_ENG_SE_TRNG_0_DOUT_1_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_1_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_1_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS)) + +/* 0x210 : se_trng_0_dout_2 */ +#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210) +#define SEC_ENG_SE_TRNG_0_DOUT_2 SEC_ENG_SE_TRNG_0_DOUT_2 +#define SEC_ENG_SE_TRNG_0_DOUT_2_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_2_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_2_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS)) + +/* 0x214 : se_trng_0_dout_3 */ +#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214) +#define SEC_ENG_SE_TRNG_0_DOUT_3 SEC_ENG_SE_TRNG_0_DOUT_3 +#define SEC_ENG_SE_TRNG_0_DOUT_3_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_3_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_3_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS)) + +/* 0x218 : se_trng_0_dout_4 */ +#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218) +#define SEC_ENG_SE_TRNG_0_DOUT_4 SEC_ENG_SE_TRNG_0_DOUT_4 +#define SEC_ENG_SE_TRNG_0_DOUT_4_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_4_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_4_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_4_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS)) + +/* 0x21C : se_trng_0_dout_5 */ +#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C) +#define SEC_ENG_SE_TRNG_0_DOUT_5 SEC_ENG_SE_TRNG_0_DOUT_5 +#define SEC_ENG_SE_TRNG_0_DOUT_5_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_5_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_5_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_5_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS)) + +/* 0x220 : se_trng_0_dout_6 */ +#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220) +#define SEC_ENG_SE_TRNG_0_DOUT_6 SEC_ENG_SE_TRNG_0_DOUT_6 +#define SEC_ENG_SE_TRNG_0_DOUT_6_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_6_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_6_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_6_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS)) + +/* 0x224 : se_trng_0_dout_7 */ +#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224) +#define SEC_ENG_SE_TRNG_0_DOUT_7 SEC_ENG_SE_TRNG_0_DOUT_7 +#define SEC_ENG_SE_TRNG_0_DOUT_7_POS (0U) +#define SEC_ENG_SE_TRNG_0_DOUT_7_LEN (32U) +#define SEC_ENG_SE_TRNG_0_DOUT_7_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS) +#define SEC_ENG_SE_TRNG_0_DOUT_7_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS)) + +/* 0x228 : se_trng_0_test */ +#define SEC_ENG_SE_TRNG_0_TEST_OFFSET (0x228) +#define SEC_ENG_SE_TRNG_0_TEST_EN SEC_ENG_SE_TRNG_0_TEST_EN +#define SEC_ENG_SE_TRNG_0_TEST_EN_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS) +#define SEC_ENG_SE_TRNG_0_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS)) +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN SEC_ENG_SE_TRNG_0_CP_TEST_EN +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS (1U) +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS) +#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS)) +#define SEC_ENG_SE_TRNG_0_CP_BYPASS SEC_ENG_SE_TRNG_0_CP_BYPASS +#define SEC_ENG_SE_TRNG_0_CP_BYPASS_POS (2U) +#define SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN (1U) +#define SEC_ENG_SE_TRNG_0_CP_BYPASS_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS) +#define SEC_ENG_SE_TRNG_0_CP_BYPASS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS)) +#define SEC_ENG_SE_TRNG_0_HT_DIS SEC_ENG_SE_TRNG_0_HT_DIS +#define SEC_ENG_SE_TRNG_0_HT_DIS_POS (3U) +#define SEC_ENG_SE_TRNG_0_HT_DIS_LEN (1U) +#define SEC_ENG_SE_TRNG_0_HT_DIS_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS) +#define SEC_ENG_SE_TRNG_0_HT_DIS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS)) +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N SEC_ENG_SE_TRNG_0_HT_ALARM_N +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS (4U) +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN (8U) +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS) +#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS)) + +/* 0x22C : se_trng_0_ctrl_1 */ +#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET (0x22C) +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB SEC_ENG_SE_TRNG_0_RESEED_N_LSB +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS (0U) +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN (32U) +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MSK (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS) +#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS)) + +/* 0x230 : se_trng_0_ctrl_2 */ +#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET (0x230) +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB SEC_ENG_SE_TRNG_0_RESEED_N_MSB +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS (0U) +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN (16U) +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MSK (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS) +#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS)) + +/* 0x234 : se_trng_0_ctrl_3 */ +#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234) +#define SEC_ENG_SE_TRNG_0_CP_RATIO SEC_ENG_SE_TRNG_0_CP_RATIO +#define SEC_ENG_SE_TRNG_0_CP_RATIO_POS (0U) +#define SEC_ENG_SE_TRNG_0_CP_RATIO_LEN (8U) +#define SEC_ENG_SE_TRNG_0_CP_RATIO_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS) +#define SEC_ENG_SE_TRNG_0_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS)) +#define SEC_ENG_SE_TRNG_0_HT_RCT_C SEC_ENG_SE_TRNG_0_HT_RCT_C +#define SEC_ENG_SE_TRNG_0_HT_RCT_C_POS (8U) +#define SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN (8U) +#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS) +#define SEC_ENG_SE_TRNG_0_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS)) +#define SEC_ENG_SE_TRNG_0_HT_APT_C SEC_ENG_SE_TRNG_0_HT_APT_C +#define SEC_ENG_SE_TRNG_0_HT_APT_C_POS (16U) +#define SEC_ENG_SE_TRNG_0_HT_APT_C_LEN (10U) +#define SEC_ENG_SE_TRNG_0_HT_APT_C_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS) +#define SEC_ENG_SE_TRNG_0_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS)) +#define SEC_ENG_SE_TRNG_0_HT_OD_EN SEC_ENG_SE_TRNG_0_HT_OD_EN +#define SEC_ENG_SE_TRNG_0_HT_OD_EN_POS (26U) +#define SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_HT_OD_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS) +#define SEC_ENG_SE_TRNG_0_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS)) +#define SEC_ENG_SE_TRNG_0_ROSC_EN SEC_ENG_SE_TRNG_0_ROSC_EN +#define SEC_ENG_SE_TRNG_0_ROSC_EN_POS (31U) +#define SEC_ENG_SE_TRNG_0_ROSC_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_0_ROSC_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS) +#define SEC_ENG_SE_TRNG_0_ROSC_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS)) + +/* 0x240 : se_trng_0_test_out_0 */ +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0 SEC_ENG_SE_TRNG_0_TEST_OUT_0 +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN (32U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS)) + +/* 0x244 : se_trng_0_test_out_1 */ +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1 SEC_ENG_SE_TRNG_0_TEST_OUT_1 +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN (32U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS)) + +/* 0x248 : se_trng_0_test_out_2 */ +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2 SEC_ENG_SE_TRNG_0_TEST_OUT_2 +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN (32U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS)) + +/* 0x24C : se_trng_0_test_out_3 */ +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3 SEC_ENG_SE_TRNG_0_TEST_OUT_3 +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS (0U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN (32U) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS) +#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS)) + +/* 0x2FC : se_trng_0_ctrl_prot */ +#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC) +#define SEC_ENG_SE_TRNG_PROT_EN SEC_ENG_SE_TRNG_PROT_EN +#define SEC_ENG_SE_TRNG_PROT_EN_POS (0U) +#define SEC_ENG_SE_TRNG_PROT_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_PROT_EN_MSK (((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS) +#define SEC_ENG_SE_TRNG_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS)) +#define SEC_ENG_SE_TRNG_ID0_EN SEC_ENG_SE_TRNG_ID0_EN +#define SEC_ENG_SE_TRNG_ID0_EN_POS (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS) +#define SEC_ENG_SE_TRNG_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)) +#define SEC_ENG_SE_TRNG_ID1_EN SEC_ENG_SE_TRNG_ID1_EN +#define SEC_ENG_SE_TRNG_ID1_EN_POS (2U) +#define SEC_ENG_SE_TRNG_ID1_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ID1_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS) +#define SEC_ENG_SE_TRNG_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)) + +/* 0x300 : se_pka_0_ctrl_0 */ +#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET (0x300) +#define SEC_ENG_SE_PKA_0_DONE SEC_ENG_SE_PKA_0_DONE +#define SEC_ENG_SE_PKA_0_DONE_POS (0U) +#define SEC_ENG_SE_PKA_0_DONE_LEN (1U) +#define SEC_ENG_SE_PKA_0_DONE_MSK (((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS) +#define SEC_ENG_SE_PKA_0_DONE_UMSK (~(((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS)) +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T SEC_ENG_SE_PKA_0_DONE_CLR_1T +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS (1U) +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN (1U) +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS) +#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS)) +#define SEC_ENG_SE_PKA_0_BUSY SEC_ENG_SE_PKA_0_BUSY +#define SEC_ENG_SE_PKA_0_BUSY_POS (2U) +#define SEC_ENG_SE_PKA_0_BUSY_LEN (1U) +#define SEC_ENG_SE_PKA_0_BUSY_MSK (((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS) +#define SEC_ENG_SE_PKA_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS)) +#define SEC_ENG_SE_PKA_0_EN SEC_ENG_SE_PKA_0_EN +#define SEC_ENG_SE_PKA_0_EN_POS (3U) +#define SEC_ENG_SE_PKA_0_EN_LEN (1U) +#define SEC_ENG_SE_PKA_0_EN_MSK (((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS) +#define SEC_ENG_SE_PKA_0_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS)) +#define SEC_ENG_SE_PKA_0_PROT_MD SEC_ENG_SE_PKA_0_PROT_MD +#define SEC_ENG_SE_PKA_0_PROT_MD_POS (4U) +#define SEC_ENG_SE_PKA_0_PROT_MD_LEN (4U) +#define SEC_ENG_SE_PKA_0_PROT_MD_MSK (((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS) +#define SEC_ENG_SE_PKA_0_PROT_MD_UMSK (~(((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS)) +#define SEC_ENG_SE_PKA_0_INT SEC_ENG_SE_PKA_0_INT +#define SEC_ENG_SE_PKA_0_INT_POS (8U) +#define SEC_ENG_SE_PKA_0_INT_LEN (1U) +#define SEC_ENG_SE_PKA_0_INT_MSK (((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS) +#define SEC_ENG_SE_PKA_0_INT_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS)) +#define SEC_ENG_SE_PKA_0_INT_CLR_1T SEC_ENG_SE_PKA_0_INT_CLR_1T +#define SEC_ENG_SE_PKA_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_PKA_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_PKA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_PKA_0_INT_SET SEC_ENG_SE_PKA_0_INT_SET +#define SEC_ENG_SE_PKA_0_INT_SET_POS (10U) +#define SEC_ENG_SE_PKA_0_INT_SET_LEN (1U) +#define SEC_ENG_SE_PKA_0_INT_SET_MSK (((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS) +#define SEC_ENG_SE_PKA_0_INT_SET_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS)) +#define SEC_ENG_SE_PKA_0_INT_MASK SEC_ENG_SE_PKA_0_INT_MASK +#define SEC_ENG_SE_PKA_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_PKA_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_PKA_0_INT_MASK_MSK (((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS) +#define SEC_ENG_SE_PKA_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS)) +#define SEC_ENG_SE_PKA_0_ENDIAN SEC_ENG_SE_PKA_0_ENDIAN +#define SEC_ENG_SE_PKA_0_ENDIAN_POS (12U) +#define SEC_ENG_SE_PKA_0_ENDIAN_LEN (1U) +#define SEC_ENG_SE_PKA_0_ENDIAN_MSK (((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS) +#define SEC_ENG_SE_PKA_0_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS)) +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD SEC_ENG_SE_PKA_0_RAM_CLR_MD +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS (13U) +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN (1U) +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_MSK (((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS) +#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_UMSK (~(((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS)) +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T SEC_ENG_SE_PKA_0_STATUS_CLR_1T +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS (15U) +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN (1U) +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS) +#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS)) +#define SEC_ENG_SE_PKA_0_STATUS SEC_ENG_SE_PKA_0_STATUS +#define SEC_ENG_SE_PKA_0_STATUS_POS (16U) +#define SEC_ENG_SE_PKA_0_STATUS_LEN (16U) +#define SEC_ENG_SE_PKA_0_STATUS_MSK (((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS) +#define SEC_ENG_SE_PKA_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS)) + +/* 0x30C : se_pka_0_seed */ +#define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C) +#define SEC_ENG_SE_PKA_0_SEED SEC_ENG_SE_PKA_0_SEED +#define SEC_ENG_SE_PKA_0_SEED_POS (0U) +#define SEC_ENG_SE_PKA_0_SEED_LEN (32U) +#define SEC_ENG_SE_PKA_0_SEED_MSK (((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS) +#define SEC_ENG_SE_PKA_0_SEED_UMSK (~(((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS)) + +/* 0x310 : se_pka_0_ctrl_1 */ +#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310) +#define SEC_ENG_SE_PKA_0_HBURST SEC_ENG_SE_PKA_0_HBURST +#define SEC_ENG_SE_PKA_0_HBURST_POS (0U) +#define SEC_ENG_SE_PKA_0_HBURST_LEN (3U) +#define SEC_ENG_SE_PKA_0_HBURST_MSK (((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS) +#define SEC_ENG_SE_PKA_0_HBURST_UMSK (~(((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS)) +#define SEC_ENG_SE_PKA_0_HBYPASS SEC_ENG_SE_PKA_0_HBYPASS +#define SEC_ENG_SE_PKA_0_HBYPASS_POS (3U) +#define SEC_ENG_SE_PKA_0_HBYPASS_LEN (1U) +#define SEC_ENG_SE_PKA_0_HBYPASS_MSK (((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS) +#define SEC_ENG_SE_PKA_0_HBYPASS_UMSK (~(((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS)) + +/* 0x340 : se_pka_0_rw */ +#define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340) + +/* 0x360 : se_pka_0_rw_burst */ +#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360) + +/* 0x3FC : se_pka_0_ctrl_prot */ +#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC) +#define SEC_ENG_SE_PKA_PROT_EN SEC_ENG_SE_PKA_PROT_EN +#define SEC_ENG_SE_PKA_PROT_EN_POS (0U) +#define SEC_ENG_SE_PKA_PROT_EN_LEN (1U) +#define SEC_ENG_SE_PKA_PROT_EN_MSK (((1U << SEC_ENG_SE_PKA_PROT_EN_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_POS) +#define SEC_ENG_SE_PKA_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_PROT_EN_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_POS)) +#define SEC_ENG_SE_PKA_ID0_EN SEC_ENG_SE_PKA_ID0_EN +#define SEC_ENG_SE_PKA_ID0_EN_POS (1U) +#define SEC_ENG_SE_PKA_ID0_EN_LEN (1U) +#define SEC_ENG_SE_PKA_ID0_EN_MSK (((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS) +#define SEC_ENG_SE_PKA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS)) +#define SEC_ENG_SE_PKA_ID1_EN SEC_ENG_SE_PKA_ID1_EN +#define SEC_ENG_SE_PKA_ID1_EN_POS (2U) +#define SEC_ENG_SE_PKA_ID1_EN_LEN (1U) +#define SEC_ENG_SE_PKA_ID1_EN_MSK (((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS) +#define SEC_ENG_SE_PKA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS)) + +/* 0x400 : se_cdet_0_ctrl_0 */ +#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET (0x400) +#define SEC_ENG_SE_CDET_0_EN SEC_ENG_SE_CDET_0_EN +#define SEC_ENG_SE_CDET_0_EN_POS (0U) +#define SEC_ENG_SE_CDET_0_EN_LEN (1U) +#define SEC_ENG_SE_CDET_0_EN_MSK (((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS) +#define SEC_ENG_SE_CDET_0_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS)) +#define SEC_ENG_SE_CDET_0_ERROR SEC_ENG_SE_CDET_0_ERROR +#define SEC_ENG_SE_CDET_0_ERROR_POS (1U) +#define SEC_ENG_SE_CDET_0_ERROR_LEN (1U) +#define SEC_ENG_SE_CDET_0_ERROR_MSK (((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS) +#define SEC_ENG_SE_CDET_0_ERROR_UMSK (~(((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS)) +#define SEC_ENG_SE_CDET_0_STATUS SEC_ENG_SE_CDET_0_STATUS +#define SEC_ENG_SE_CDET_0_STATUS_POS (2U) +#define SEC_ENG_SE_CDET_0_STATUS_LEN (14U) +#define SEC_ENG_SE_CDET_0_STATUS_MSK (((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS) +#define SEC_ENG_SE_CDET_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS)) +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX SEC_ENG_SE_CDET_0_G_LOOP_MAX +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS (16U) +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN (8U) +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MSK (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS) +#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS)) +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN SEC_ENG_SE_CDET_0_G_LOOP_MIN +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS (24U) +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN (8U) +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MSK (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS) +#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS)) + +/* 0x404 : se_cdet_0_ctrl_1 */ +#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404) +#define SEC_ENG_SE_CDET_0_T_LOOP_N SEC_ENG_SE_CDET_0_T_LOOP_N +#define SEC_ENG_SE_CDET_0_T_LOOP_N_POS (0U) +#define SEC_ENG_SE_CDET_0_T_LOOP_N_LEN (8U) +#define SEC_ENG_SE_CDET_0_T_LOOP_N_MSK (((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS) +#define SEC_ENG_SE_CDET_0_T_LOOP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS)) +#define SEC_ENG_SE_CDET_0_T_DLY_N SEC_ENG_SE_CDET_0_T_DLY_N +#define SEC_ENG_SE_CDET_0_T_DLY_N_POS (8U) +#define SEC_ENG_SE_CDET_0_T_DLY_N_LEN (8U) +#define SEC_ENG_SE_CDET_0_T_DLY_N_MSK (((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS) +#define SEC_ENG_SE_CDET_0_T_DLY_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS)) +#define SEC_ENG_SE_CDET_0_G_SLP_N SEC_ENG_SE_CDET_0_G_SLP_N +#define SEC_ENG_SE_CDET_0_G_SLP_N_POS (16U) +#define SEC_ENG_SE_CDET_0_G_SLP_N_LEN (8U) +#define SEC_ENG_SE_CDET_0_G_SLP_N_MSK (((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS) +#define SEC_ENG_SE_CDET_0_G_SLP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS)) + +/* 0x4FC : se_cdet_0_ctrl_prot */ +#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC) +#define SEC_ENG_SE_CDET_PROT_EN SEC_ENG_SE_CDET_PROT_EN +#define SEC_ENG_SE_CDET_PROT_EN_POS (0U) +#define SEC_ENG_SE_CDET_PROT_EN_LEN (1U) +#define SEC_ENG_SE_CDET_PROT_EN_MSK (((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS) +#define SEC_ENG_SE_CDET_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS)) +#define SEC_ENG_SE_CDET_ID0_EN SEC_ENG_SE_CDET_ID0_EN +#define SEC_ENG_SE_CDET_ID0_EN_POS (1U) +#define SEC_ENG_SE_CDET_ID0_EN_LEN (1U) +#define SEC_ENG_SE_CDET_ID0_EN_MSK (((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS) +#define SEC_ENG_SE_CDET_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS)) +#define SEC_ENG_SE_CDET_ID1_EN SEC_ENG_SE_CDET_ID1_EN +#define SEC_ENG_SE_CDET_ID1_EN_POS (2U) +#define SEC_ENG_SE_CDET_ID1_EN_LEN (1U) +#define SEC_ENG_SE_CDET_ID1_EN_MSK (((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS) +#define SEC_ENG_SE_CDET_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS)) + +/* 0x500 : se_gmac_0_ctrl_0 */ +#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET (0x500) +#define SEC_ENG_SE_GMAC_0_BUSY SEC_ENG_SE_GMAC_0_BUSY +#define SEC_ENG_SE_GMAC_0_BUSY_POS (0U) +#define SEC_ENG_SE_GMAC_0_BUSY_LEN (1U) +#define SEC_ENG_SE_GMAC_0_BUSY_MSK (((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS) +#define SEC_ENG_SE_GMAC_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS)) +#define SEC_ENG_SE_GMAC_0_TRIG_1T SEC_ENG_SE_GMAC_0_TRIG_1T +#define SEC_ENG_SE_GMAC_0_TRIG_1T_POS (1U) +#define SEC_ENG_SE_GMAC_0_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_GMAC_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS) +#define SEC_ENG_SE_GMAC_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS)) +#define SEC_ENG_SE_GMAC_0_EN SEC_ENG_SE_GMAC_0_EN +#define SEC_ENG_SE_GMAC_0_EN_POS (2U) +#define SEC_ENG_SE_GMAC_0_EN_LEN (1U) +#define SEC_ENG_SE_GMAC_0_EN_MSK (((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS) +#define SEC_ENG_SE_GMAC_0_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS)) +#define SEC_ENG_SE_GMAC_0_INT SEC_ENG_SE_GMAC_0_INT +#define SEC_ENG_SE_GMAC_0_INT_POS (8U) +#define SEC_ENG_SE_GMAC_0_INT_LEN (1U) +#define SEC_ENG_SE_GMAC_0_INT_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS) +#define SEC_ENG_SE_GMAC_0_INT_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS)) +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T SEC_ENG_SE_GMAC_0_INT_CLR_1T +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS) +#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS)) +#define SEC_ENG_SE_GMAC_0_INT_SET_1T SEC_ENG_SE_GMAC_0_INT_SET_1T +#define SEC_ENG_SE_GMAC_0_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_GMAC_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS) +#define SEC_ENG_SE_GMAC_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS)) +#define SEC_ENG_SE_GMAC_0_INT_MASK SEC_ENG_SE_GMAC_0_INT_MASK +#define SEC_ENG_SE_GMAC_0_INT_MASK_POS (11U) +#define SEC_ENG_SE_GMAC_0_INT_MASK_LEN (1U) +#define SEC_ENG_SE_GMAC_0_INT_MASK_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS) +#define SEC_ENG_SE_GMAC_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS)) +#define SEC_ENG_SE_GMAC_0_T_ENDIAN SEC_ENG_SE_GMAC_0_T_ENDIAN +#define SEC_ENG_SE_GMAC_0_T_ENDIAN_POS (12U) +#define SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN (1U) +#define SEC_ENG_SE_GMAC_0_T_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS) +#define SEC_ENG_SE_GMAC_0_T_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS)) +#define SEC_ENG_SE_GMAC_0_H_ENDIAN SEC_ENG_SE_GMAC_0_H_ENDIAN +#define SEC_ENG_SE_GMAC_0_H_ENDIAN_POS (13U) +#define SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN (1U) +#define SEC_ENG_SE_GMAC_0_H_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS) +#define SEC_ENG_SE_GMAC_0_H_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS)) +#define SEC_ENG_SE_GMAC_0_X_ENDIAN SEC_ENG_SE_GMAC_0_X_ENDIAN +#define SEC_ENG_SE_GMAC_0_X_ENDIAN_POS (14U) +#define SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN (1U) +#define SEC_ENG_SE_GMAC_0_X_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS) +#define SEC_ENG_SE_GMAC_0_X_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS)) + +/* 0x504 : se_gmac_0_lca */ +#define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504) +#define SEC_ENG_SE_GMAC_0_LCA SEC_ENG_SE_GMAC_0_LCA +#define SEC_ENG_SE_GMAC_0_LCA_POS (0U) +#define SEC_ENG_SE_GMAC_0_LCA_LEN (32U) +#define SEC_ENG_SE_GMAC_0_LCA_MSK (((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS) +#define SEC_ENG_SE_GMAC_0_LCA_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS)) + +/* 0x508 : se_gmac_0_status */ +#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508) +#define SEC_ENG_SE_GMAC_0_STATUS SEC_ENG_SE_GMAC_0_STATUS +#define SEC_ENG_SE_GMAC_0_STATUS_POS (0U) +#define SEC_ENG_SE_GMAC_0_STATUS_LEN (32U) +#define SEC_ENG_SE_GMAC_0_STATUS_MSK (((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS) +#define SEC_ENG_SE_GMAC_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS)) + +/* 0x5FC : se_gmac_0_ctrl_prot */ +#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC) +#define SEC_ENG_SE_GMAC_PROT_EN SEC_ENG_SE_GMAC_PROT_EN +#define SEC_ENG_SE_GMAC_PROT_EN_POS (0U) +#define SEC_ENG_SE_GMAC_PROT_EN_LEN (1U) +#define SEC_ENG_SE_GMAC_PROT_EN_MSK (((1U << SEC_ENG_SE_GMAC_PROT_EN_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_POS) +#define SEC_ENG_SE_GMAC_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_PROT_EN_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_POS)) +#define SEC_ENG_SE_GMAC_ID0_EN SEC_ENG_SE_GMAC_ID0_EN +#define SEC_ENG_SE_GMAC_ID0_EN_POS (1U) +#define SEC_ENG_SE_GMAC_ID0_EN_LEN (1U) +#define SEC_ENG_SE_GMAC_ID0_EN_MSK (((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS) +#define SEC_ENG_SE_GMAC_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS)) +#define SEC_ENG_SE_GMAC_ID1_EN SEC_ENG_SE_GMAC_ID1_EN +#define SEC_ENG_SE_GMAC_ID1_EN_POS (2U) +#define SEC_ENG_SE_GMAC_ID1_EN_LEN (1U) +#define SEC_ENG_SE_GMAC_ID1_EN_MSK (((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS) +#define SEC_ENG_SE_GMAC_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS)) + +/* 0xF00 : se_ctrl_prot_rd */ +#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET (0xF00) +#define SEC_ENG_SE_SHA_PROT_EN_RD SEC_ENG_SE_SHA_PROT_EN_RD +#define SEC_ENG_SE_SHA_PROT_EN_RD_POS (0U) +#define SEC_ENG_SE_SHA_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_SHA_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_RD_POS) +#define SEC_ENG_SE_SHA_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_RD_POS)) +#define SEC_ENG_SE_SHA_ID0_EN_RD SEC_ENG_SE_SHA_ID0_EN_RD +#define SEC_ENG_SE_SHA_ID0_EN_RD_POS (1U) +#define SEC_ENG_SE_SHA_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_SHA_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS) +#define SEC_ENG_SE_SHA_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS)) +#define SEC_ENG_SE_SHA_ID1_EN_RD SEC_ENG_SE_SHA_ID1_EN_RD +#define SEC_ENG_SE_SHA_ID1_EN_RD_POS (2U) +#define SEC_ENG_SE_SHA_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_SHA_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS) +#define SEC_ENG_SE_SHA_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS)) +#define SEC_ENG_SE_AES_PROT_EN_RD SEC_ENG_SE_AES_PROT_EN_RD +#define SEC_ENG_SE_AES_PROT_EN_RD_POS (4U) +#define SEC_ENG_SE_AES_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_AES_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_AES_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_RD_POS) +#define SEC_ENG_SE_AES_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_RD_POS)) +#define SEC_ENG_SE_AES_ID0_EN_RD SEC_ENG_SE_AES_ID0_EN_RD +#define SEC_ENG_SE_AES_ID0_EN_RD_POS (5U) +#define SEC_ENG_SE_AES_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_AES_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS) +#define SEC_ENG_SE_AES_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS)) +#define SEC_ENG_SE_AES_ID1_EN_RD SEC_ENG_SE_AES_ID1_EN_RD +#define SEC_ENG_SE_AES_ID1_EN_RD_POS (6U) +#define SEC_ENG_SE_AES_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_AES_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS) +#define SEC_ENG_SE_AES_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS)) +#define SEC_ENG_SE_TRNG_PROT_EN_RD SEC_ENG_SE_TRNG_PROT_EN_RD +#define SEC_ENG_SE_TRNG_PROT_EN_RD_POS (8U) +#define SEC_ENG_SE_TRNG_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_TRNG_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_RD_POS) +#define SEC_ENG_SE_TRNG_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_RD_POS)) +#define SEC_ENG_SE_TRNG_ID0_EN_RD SEC_ENG_SE_TRNG_ID0_EN_RD +#define SEC_ENG_SE_TRNG_ID0_EN_RD_POS (9U) +#define SEC_ENG_SE_TRNG_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS) +#define SEC_ENG_SE_TRNG_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS)) +#define SEC_ENG_SE_TRNG_ID1_EN_RD SEC_ENG_SE_TRNG_ID1_EN_RD +#define SEC_ENG_SE_TRNG_ID1_EN_RD_POS (10U) +#define SEC_ENG_SE_TRNG_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_TRNG_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS) +#define SEC_ENG_SE_TRNG_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS)) +#define SEC_ENG_SE_PKA_PROT_EN_RD SEC_ENG_SE_PKA_PROT_EN_RD +#define SEC_ENG_SE_PKA_PROT_EN_RD_POS (12U) +#define SEC_ENG_SE_PKA_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_PKA_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_RD_POS) +#define SEC_ENG_SE_PKA_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_RD_POS)) +#define SEC_ENG_SE_PKA_ID0_EN_RD SEC_ENG_SE_PKA_ID0_EN_RD +#define SEC_ENG_SE_PKA_ID0_EN_RD_POS (13U) +#define SEC_ENG_SE_PKA_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_PKA_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS) +#define SEC_ENG_SE_PKA_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS)) +#define SEC_ENG_SE_PKA_ID1_EN_RD SEC_ENG_SE_PKA_ID1_EN_RD +#define SEC_ENG_SE_PKA_ID1_EN_RD_POS (14U) +#define SEC_ENG_SE_PKA_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_PKA_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS) +#define SEC_ENG_SE_PKA_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS)) +#define SEC_ENG_SE_CDET_PROT_EN_RD SEC_ENG_SE_CDET_PROT_EN_RD +#define SEC_ENG_SE_CDET_PROT_EN_RD_POS (16U) +#define SEC_ENG_SE_CDET_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_CDET_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_RD_POS) +#define SEC_ENG_SE_CDET_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_RD_POS)) +#define SEC_ENG_SE_CDET_ID0_EN_RD SEC_ENG_SE_CDET_ID0_EN_RD +#define SEC_ENG_SE_CDET_ID0_EN_RD_POS (17U) +#define SEC_ENG_SE_CDET_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_CDET_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS) +#define SEC_ENG_SE_CDET_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS)) +#define SEC_ENG_SE_CDET_ID1_EN_RD SEC_ENG_SE_CDET_ID1_EN_RD +#define SEC_ENG_SE_CDET_ID1_EN_RD_POS (18U) +#define SEC_ENG_SE_CDET_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_CDET_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS) +#define SEC_ENG_SE_CDET_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS)) +#define SEC_ENG_SE_GMAC_PROT_EN_RD SEC_ENG_SE_GMAC_PROT_EN_RD +#define SEC_ENG_SE_GMAC_PROT_EN_RD_POS (20U) +#define SEC_ENG_SE_GMAC_PROT_EN_RD_LEN (1U) +#define SEC_ENG_SE_GMAC_PROT_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_RD_POS) +#define SEC_ENG_SE_GMAC_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_RD_POS)) +#define SEC_ENG_SE_GMAC_ID0_EN_RD SEC_ENG_SE_GMAC_ID0_EN_RD +#define SEC_ENG_SE_GMAC_ID0_EN_RD_POS (21U) +#define SEC_ENG_SE_GMAC_ID0_EN_RD_LEN (1U) +#define SEC_ENG_SE_GMAC_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS) +#define SEC_ENG_SE_GMAC_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS)) +#define SEC_ENG_SE_GMAC_ID1_EN_RD SEC_ENG_SE_GMAC_ID1_EN_RD +#define SEC_ENG_SE_GMAC_ID1_EN_RD_POS (22U) +#define SEC_ENG_SE_GMAC_ID1_EN_RD_LEN (1U) +#define SEC_ENG_SE_GMAC_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS) +#define SEC_ENG_SE_GMAC_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS)) +#define SEC_ENG_SE_DBG_DIS SEC_ENG_SE_DBG_DIS +#define SEC_ENG_SE_DBG_DIS_POS (31U) +#define SEC_ENG_SE_DBG_DIS_LEN (1U) +#define SEC_ENG_SE_DBG_DIS_MSK (((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS) +#define SEC_ENG_SE_DBG_DIS_UMSK (~(((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS)) + +/* 0xF04 : se_ctrl_reserved_0 */ +#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04) +#define SEC_ENG_SE_CTRL_RESERVED_0 SEC_ENG_SE_CTRL_RESERVED_0 +#define SEC_ENG_SE_CTRL_RESERVED_0_POS (0U) +#define SEC_ENG_SE_CTRL_RESERVED_0_LEN (32U) +#define SEC_ENG_SE_CTRL_RESERVED_0_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS) +#define SEC_ENG_SE_CTRL_RESERVED_0_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS)) + +/* 0xF08 : se_ctrl_reserved_1 */ +#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08) +#define SEC_ENG_SE_CTRL_RESERVED_1 SEC_ENG_SE_CTRL_RESERVED_1 +#define SEC_ENG_SE_CTRL_RESERVED_1_POS (0U) +#define SEC_ENG_SE_CTRL_RESERVED_1_LEN (32U) +#define SEC_ENG_SE_CTRL_RESERVED_1_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS) +#define SEC_ENG_SE_CTRL_RESERVED_1_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS)) + +/* 0xF0C : se_ctrl_reserved_2 */ +#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C) +#define SEC_ENG_SE_CTRL_RESERVED_2 SEC_ENG_SE_CTRL_RESERVED_2 +#define SEC_ENG_SE_CTRL_RESERVED_2_POS (0U) +#define SEC_ENG_SE_CTRL_RESERVED_2_LEN (32U) +#define SEC_ENG_SE_CTRL_RESERVED_2_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS) +#define SEC_ENG_SE_CTRL_RESERVED_2_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS)) + +struct sec_eng_reg { + /* 0x0 : se_sha_0_ctrl */ + union { + struct + { + uint32_t se_sha_0_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_sha_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_sha_0_mode : 3; /* [ 4: 2], r/w, 0x0 */ + uint32_t se_sha_0_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t se_sha_0_hash_sel : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t se_sha_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_sha_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_sha_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_sha_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_14 : 3; /* [14:12], rsvd, 0x0 */ + uint32_t se_sha_0_link_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t se_sha_0_msg_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_ctrl; + + /* 0x4 : se_sha_0_msa */ + union { + struct + { + uint32_t se_sha_0_msa : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_msa; + + /* 0x8 : se_sha_0_status */ + union { + struct + { + uint32_t se_sha_0_status : 32; /* [31: 0], r, 0x41 */ + } BF; + uint32_t WORD; + } se_sha_0_status; + + /* 0xC : se_sha_0_endian */ + union { + struct + { + uint32_t se_sha_0_dout_endian : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_endian; + + /* 0x10 : se_sha_0_hash_l_0 */ + union { + struct + { + uint32_t se_sha_0_hash_l_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_0; + + /* 0x14 : se_sha_0_hash_l_1 */ + union { + struct + { + uint32_t se_sha_0_hash_l_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_1; + + /* 0x18 : se_sha_0_hash_l_2 */ + union { + struct + { + uint32_t se_sha_0_hash_l_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_2; + + /* 0x1C : se_sha_0_hash_l_3 */ + union { + struct + { + uint32_t se_sha_0_hash_l_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_3; + + /* 0x20 : se_sha_0_hash_l_4 */ + union { + struct + { + uint32_t se_sha_0_hash_l_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_4; + + /* 0x24 : se_sha_0_hash_l_5 */ + union { + struct + { + uint32_t se_sha_0_hash_l_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_5; + + /* 0x28 : se_sha_0_hash_l_6 */ + union { + struct + { + uint32_t se_sha_0_hash_l_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_6; + + /* 0x2C : se_sha_0_hash_l_7 */ + union { + struct + { + uint32_t se_sha_0_hash_l_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_l_7; + + /* 0x30 : se_sha_0_hash_h_0 */ + union { + struct + { + uint32_t se_sha_0_hash_h_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_0; + + /* 0x34 : se_sha_0_hash_h_1 */ + union { + struct + { + uint32_t se_sha_0_hash_h_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_1; + + /* 0x38 : se_sha_0_hash_h_2 */ + union { + struct + { + uint32_t se_sha_0_hash_h_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_2; + + /* 0x3C : se_sha_0_hash_h_3 */ + union { + struct + { + uint32_t se_sha_0_hash_h_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_3; + + /* 0x40 : se_sha_0_hash_h_4 */ + union { + struct + { + uint32_t se_sha_0_hash_h_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_4; + + /* 0x44 : se_sha_0_hash_h_5 */ + union { + struct + { + uint32_t se_sha_0_hash_h_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_5; + + /* 0x48 : se_sha_0_hash_h_6 */ + union { + struct + { + uint32_t se_sha_0_hash_h_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_6; + + /* 0x4C : se_sha_0_hash_h_7 */ + union { + struct + { + uint32_t se_sha_0_hash_h_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_hash_h_7; + + /* 0x50 : se_sha_0_link */ + union { + struct + { + uint32_t se_sha_0_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_link; + + /* 0x54 reserved */ + uint8_t RESERVED0x54[168]; + + /* 0xFC : se_sha_0_ctrl_prot */ + union { + struct + { + uint32_t se_sha_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_sha_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_sha_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_0_ctrl_prot; + + /* 0x100 : se_aes_0_ctrl */ + union { + struct + { + uint32_t se_aes_0_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_aes_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_aes_0_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_aes_0_mode : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t se_aes_0_dec_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t se_aes_0_dec_key_sel : 1; /* [ 6], r/w, 0x0 */ + uint32_t se_aes_0_hw_key_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t se_aes_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_aes_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_aes_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_aes_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t se_aes_0_block_mode : 2; /* [13:12], r/w, 0x0 */ + uint32_t se_aes_0_iv_sel : 1; /* [ 14], r/w, 0x0 */ + uint32_t se_aes_0_link_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t se_aes_0_msg_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_ctrl; + + /* 0x104 : se_aes_0_msa */ + union { + struct + { + uint32_t se_aes_0_msa : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_msa; + + /* 0x108 : se_aes_0_mda */ + union { + struct + { + uint32_t se_aes_0_mda : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_mda; + + /* 0x10C : se_aes_0_status */ + union { + struct + { + uint32_t se_aes_0_status : 32; /* [31: 0], r, 0x100 */ + } BF; + uint32_t WORD; + } se_aes_0_status; + + /* 0x110 : se_aes_0_iv_0 */ + union { + struct + { + uint32_t se_aes_0_iv_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_iv_0; + + /* 0x114 : se_aes_0_iv_1 */ + union { + struct + { + uint32_t se_aes_0_iv_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_iv_1; + + /* 0x118 : se_aes_0_iv_2 */ + union { + struct + { + uint32_t se_aes_0_iv_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_iv_2; + + /* 0x11C : se_aes_0_iv_3 */ + union { + struct + { + uint32_t se_aes_0_iv_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_iv_3; + + /* 0x120 : se_aes_0_key_0 */ + union { + struct + { + uint32_t se_aes_0_key_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_0; + + /* 0x124 : se_aes_0_key_1 */ + union { + struct + { + uint32_t se_aes_0_key_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_1; + + /* 0x128 : se_aes_0_key_2 */ + union { + struct + { + uint32_t se_aes_0_key_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_2; + + /* 0x12C : se_aes_0_key_3 */ + union { + struct + { + uint32_t se_aes_0_key_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_3; + + /* 0x130 : se_aes_0_key_4 */ + union { + struct + { + uint32_t se_aes_0_key_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_4; + + /* 0x134 : se_aes_0_key_5 */ + union { + struct + { + uint32_t se_aes_0_key_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_5; + + /* 0x138 : se_aes_0_key_6 */ + union { + struct + { + uint32_t se_aes_0_key_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_6; + + /* 0x13C : se_aes_0_key_7 */ + union { + struct + { + uint32_t se_aes_0_key_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_7; + + /* 0x140 : se_aes_0_key_sel_0 */ + union { + struct + { + uint32_t se_aes_0_key_sel_0 : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_sel_0; + + /* 0x144 : se_aes_0_key_sel_1 */ + union { + struct + { + uint32_t se_aes_0_key_sel_1 : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_key_sel_1; + + /* 0x148 : se_aes_0_endian */ + union { + struct + { + uint32_t se_aes_0_dout_endian : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_aes_0_din_endian : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_aes_0_key_endian : 1; /* [ 2], r/w, 0x1 */ + uint32_t se_aes_0_iv_endian : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_29 : 26; /* [29: 4], rsvd, 0x0 */ + uint32_t se_aes_0_ctr_len : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_endian; + + /* 0x14C : se_aes_0_sboot */ + union { + struct + { + uint32_t se_aes_0_sboot_key_sel : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_sboot; + + /* 0x150 : se_aes_0_link */ + union { + struct + { + uint32_t se_aes_0_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_link; + + /* 0x154 reserved */ + uint8_t RESERVED0x154[168]; + + /* 0x1FC : se_aes_0_ctrl_prot */ + union { + struct + { + uint32_t se_aes_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_aes_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_aes_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_0_ctrl_prot; + + /* 0x200 : se_trng_0_ctrl_0 */ + union { + struct + { + uint32_t se_trng_0_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_trng_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_trng_0_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_trng_0_dout_clr_1t : 1; /* [ 3], w1p, 0x0 */ + uint32_t se_trng_0_ht_error : 1; /* [ 4], r, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t se_trng_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_trng_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_trng_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_trng_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ + uint32_t se_trng_0_manual_fun_sel : 1; /* [ 13], r/w, 0x0 */ + uint32_t se_trng_0_manual_reseed : 1; /* [ 14], r/w, 0x0 */ + uint32_t se_trng_0_manual_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_0; + + /* 0x204 : se_trng_0_status */ + union { + struct + { + uint32_t se_trng_0_status : 32; /* [31: 0], r, 0x100020 */ + } BF; + uint32_t WORD; + } se_trng_0_status; + + /* 0x208 : se_trng_0_dout_0 */ + union { + struct + { + uint32_t se_trng_0_dout_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_0; + + /* 0x20C : se_trng_0_dout_1 */ + union { + struct + { + uint32_t se_trng_0_dout_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_1; + + /* 0x210 : se_trng_0_dout_2 */ + union { + struct + { + uint32_t se_trng_0_dout_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_2; + + /* 0x214 : se_trng_0_dout_3 */ + union { + struct + { + uint32_t se_trng_0_dout_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_3; + + /* 0x218 : se_trng_0_dout_4 */ + union { + struct + { + uint32_t se_trng_0_dout_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_4; + + /* 0x21C : se_trng_0_dout_5 */ + union { + struct + { + uint32_t se_trng_0_dout_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_5; + + /* 0x220 : se_trng_0_dout_6 */ + union { + struct + { + uint32_t se_trng_0_dout_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_6; + + /* 0x224 : se_trng_0_dout_7 */ + union { + struct + { + uint32_t se_trng_0_dout_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_dout_7; + + /* 0x228 : se_trng_0_test */ + union { + struct + { + uint32_t se_trng_0_test_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t se_trng_0_cp_test_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t se_trng_0_cp_bypass : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_trng_0_ht_dis : 1; /* [ 3], r/w, 0x0 */ + uint32_t se_trng_0_ht_alarm_n : 8; /* [11: 4], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test; + + /* 0x22C : se_trng_0_ctrl_1 */ + union { + struct + { + uint32_t se_trng_0_reseed_n_lsb : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_1; + + /* 0x230 : se_trng_0_ctrl_2 */ + union { + struct + { + uint32_t se_trng_0_reseed_n_msb : 16; /* [15: 0], r/w, 0xff */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_2; + + /* 0x234 : se_trng_0_ctrl_3 */ + union { + struct + { + uint32_t se_trng_0_cp_ratio : 8; /* [ 7: 0], r/w, 0x3 */ + uint32_t se_trng_0_ht_rct_c : 8; /* [15: 8], r/w, 0x42 */ + uint32_t se_trng_0_ht_apt_c : 10; /* [25:16], r/w, 0x37a */ + uint32_t se_trng_0_ht_od_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */ + uint32_t se_trng_0_rosc_en : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_3; + + /* 0x238 reserved */ + uint8_t RESERVED0x238[8]; + + /* 0x240 : se_trng_0_test_out_0 */ + union { + struct + { + uint32_t se_trng_0_test_out_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test_out_0; + + /* 0x244 : se_trng_0_test_out_1 */ + union { + struct + { + uint32_t se_trng_0_test_out_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test_out_1; + + /* 0x248 : se_trng_0_test_out_2 */ + union { + struct + { + uint32_t se_trng_0_test_out_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test_out_2; + + /* 0x24C : se_trng_0_test_out_3 */ + union { + struct + { + uint32_t se_trng_0_test_out_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_test_out_3; + + /* 0x250 reserved */ + uint8_t RESERVED0x250[172]; + + /* 0x2FC : se_trng_0_ctrl_prot */ + union { + struct + { + uint32_t se_trng_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_trng_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_trng_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_0_ctrl_prot; + + /* 0x300 : se_pka_0_ctrl_0 */ + union { + struct + { + uint32_t se_pka_0_done : 1; /* [ 0], r, 0x0 */ + uint32_t se_pka_0_done_clr_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_pka_0_busy : 1; /* [ 2], r, 0x0 */ + uint32_t se_pka_0_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t se_pka_0_prot_md : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t se_pka_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_pka_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_pka_0_int_set : 1; /* [ 10], r/w, 0x0 */ + uint32_t se_pka_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t se_pka_0_endian : 1; /* [ 12], r/w, 0x0 */ + uint32_t se_pka_0_ram_clr_md : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ + uint32_t se_pka_0_status_clr_1t : 1; /* [ 15], w1p, 0x0 */ + uint32_t se_pka_0_status : 16; /* [31:16], r, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_ctrl_0; + + /* 0x304 reserved */ + uint8_t RESERVED0x304[8]; + + /* 0x30C : se_pka_0_seed */ + union { + struct + { + uint32_t se_pka_0_seed : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_seed; + + /* 0x310 : se_pka_0_ctrl_1 */ + union { + struct + { + uint32_t se_pka_0_hburst : 3; /* [ 2: 0], r/w, 0x5 */ + uint32_t se_pka_0_hbypass : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_ctrl_1; + + /* 0x314 reserved */ + uint8_t RESERVED0x314[44]; + + /* 0x340 : se_pka_0_rw */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_rw; + + /* 0x344 reserved */ + uint8_t RESERVED0x344[28]; + + /* 0x360 : se_pka_0_rw_burst */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_rw_burst; + + /* 0x364 reserved */ + uint8_t RESERVED0x364[152]; + + /* 0x3FC : se_pka_0_ctrl_prot */ + union { + struct + { + uint32_t se_pka_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_pka_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_pka_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_pka_0_ctrl_prot; + + /* 0x400 : se_cdet_0_ctrl_0 */ + union { + struct + { + uint32_t se_cdet_0_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t se_cdet_0_error : 1; /* [ 1], r, 0x0 */ + uint32_t se_cdet_0_status : 14; /* [15: 2], r, 0x1 */ + uint32_t se_cdet_0_g_loop_max : 8; /* [23:16], r/w, 0x64 */ + uint32_t se_cdet_0_g_loop_min : 8; /* [31:24], r/w, 0x21 */ + } BF; + uint32_t WORD; + } se_cdet_0_ctrl_0; + + /* 0x404 : se_cdet_0_ctrl_1 */ + union { + struct + { + uint32_t se_cdet_0_t_loop_n : 8; /* [ 7: 0], r/w, 0x32 */ + uint32_t se_cdet_0_t_dly_n : 8; /* [15: 8], r/w, 0x3 */ + uint32_t se_cdet_0_g_slp_n : 8; /* [23:16], r/w, 0xff */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_cdet_0_ctrl_1; + + /* 0x408 reserved */ + uint8_t RESERVED0x408[244]; + + /* 0x4FC : se_cdet_0_ctrl_prot */ + union { + struct + { + uint32_t se_cdet_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_cdet_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_cdet_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_cdet_0_ctrl_prot; + + /* 0x500 : se_gmac_0_ctrl_0 */ + union { + struct + { + uint32_t se_gmac_0_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_gmac_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_gmac_0_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ + uint32_t se_gmac_0_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_gmac_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_gmac_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_gmac_0_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t se_gmac_0_t_endian : 1; /* [ 12], r/w, 0x1 */ + uint32_t se_gmac_0_h_endian : 1; /* [ 13], r/w, 0x1 */ + uint32_t se_gmac_0_x_endian : 1; /* [ 14], r/w, 0x1 */ + uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_gmac_0_ctrl_0; + + /* 0x504 : se_gmac_0_lca */ + union { + struct + { + uint32_t se_gmac_0_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_gmac_0_lca; + + /* 0x508 : se_gmac_0_status */ + union { + struct + { + uint32_t se_gmac_0_status : 32; /* [31: 0], r, 0xf1000000L */ + } BF; + uint32_t WORD; + } se_gmac_0_status; + + /* 0x50c reserved */ + uint8_t RESERVED0x50c[240]; + + /* 0x5FC : se_gmac_0_ctrl_prot */ + union { + struct + { + uint32_t se_gmac_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_gmac_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_gmac_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_gmac_0_ctrl_prot; + + /* 0x600 reserved */ + uint8_t RESERVED0x600[2304]; + + /* 0xF00 : se_ctrl_prot_rd */ + union { + struct + { + uint32_t se_sha_prot_en_rd : 1; /* [ 0], r, 0x1 */ + uint32_t se_sha_id0_en_rd : 1; /* [ 1], r, 0x1 */ + uint32_t se_sha_id1_en_rd : 1; /* [ 2], r, 0x1 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t se_aes_prot_en_rd : 1; /* [ 4], r, 0x1 */ + uint32_t se_aes_id0_en_rd : 1; /* [ 5], r, 0x1 */ + uint32_t se_aes_id1_en_rd : 1; /* [ 6], r, 0x1 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t se_trng_prot_en_rd : 1; /* [ 8], r, 0x1 */ + uint32_t se_trng_id0_en_rd : 1; /* [ 9], r, 0x1 */ + uint32_t se_trng_id1_en_rd : 1; /* [ 10], r, 0x1 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t se_pka_prot_en_rd : 1; /* [ 12], r, 0x1 */ + uint32_t se_pka_id0_en_rd : 1; /* [ 13], r, 0x1 */ + uint32_t se_pka_id1_en_rd : 1; /* [ 14], r, 0x1 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t se_cdet_prot_en_rd : 1; /* [ 16], r, 0x1 */ + uint32_t se_cdet_id0_en_rd : 1; /* [ 17], r, 0x1 */ + uint32_t se_cdet_id1_en_rd : 1; /* [ 18], r, 0x1 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t se_gmac_prot_en_rd : 1; /* [ 20], r, 0x1 */ + uint32_t se_gmac_id0_en_rd : 1; /* [ 21], r, 0x1 */ + uint32_t se_gmac_id1_en_rd : 1; /* [ 22], r, 0x1 */ + uint32_t reserved_23_30 : 8; /* [30:23], rsvd, 0x0 */ + uint32_t se_dbg_dis : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } se_ctrl_prot_rd; + + /* 0xF04 : se_ctrl_reserved_0 */ + union { + struct + { + uint32_t se_ctrl_reserved_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_ctrl_reserved_0; + + /* 0xF08 : se_ctrl_reserved_1 */ + union { + struct + { + uint32_t se_ctrl_reserved_1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } se_ctrl_reserved_1; + + /* 0xF0C : se_ctrl_reserved_2 */ + union { + struct + { + uint32_t se_ctrl_reserved_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_ctrl_reserved_2; +}; + +typedef volatile struct sec_eng_reg sec_eng_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : se_sha_ctrl */ +#define SEC_ENG_SE_SHA_CTRL_OFFSET (0x0) +#define SEC_ENG_SE_SHA_BUSY SEC_ENG_SE_SHA_BUSY +#define SEC_ENG_SE_SHA_BUSY_POS (0U) +#define SEC_ENG_SE_SHA_BUSY_LEN (1U) +#define SEC_ENG_SE_SHA_BUSY_MSK (((1U << SEC_ENG_SE_SHA_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_BUSY_POS) +#define SEC_ENG_SE_SHA_BUSY_UMSK (~(((1U << SEC_ENG_SE_SHA_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_BUSY_POS)) +#define SEC_ENG_SE_SHA_TRIG_1T SEC_ENG_SE_SHA_TRIG_1T +#define SEC_ENG_SE_SHA_TRIG_1T_POS (1U) +#define SEC_ENG_SE_SHA_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_SHA_TRIG_1T_MSK (((1U << SEC_ENG_SE_SHA_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_TRIG_1T_POS) +#define SEC_ENG_SE_SHA_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_TRIG_1T_POS)) +#define SEC_ENG_SE_SHA_MODE SEC_ENG_SE_SHA_MODE +#define SEC_ENG_SE_SHA_MODE_POS (2U) +#define SEC_ENG_SE_SHA_MODE_LEN (3U) +#define SEC_ENG_SE_SHA_MODE_MSK (((1U << SEC_ENG_SE_SHA_MODE_LEN) - 1) << SEC_ENG_SE_SHA_MODE_POS) +#define SEC_ENG_SE_SHA_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_MODE_LEN) - 1) << SEC_ENG_SE_SHA_MODE_POS)) +#define SEC_ENG_SE_SHA_EN SEC_ENG_SE_SHA_EN +#define SEC_ENG_SE_SHA_EN_POS (5U) +#define SEC_ENG_SE_SHA_EN_LEN (1U) +#define SEC_ENG_SE_SHA_EN_MSK (((1U << SEC_ENG_SE_SHA_EN_LEN) - 1) << SEC_ENG_SE_SHA_EN_POS) +#define SEC_ENG_SE_SHA_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_EN_LEN) - 1) << SEC_ENG_SE_SHA_EN_POS)) +#define SEC_ENG_SE_SHA_HASH_SEL SEC_ENG_SE_SHA_HASH_SEL +#define SEC_ENG_SE_SHA_HASH_SEL_POS (6U) +#define SEC_ENG_SE_SHA_HASH_SEL_LEN (1U) +#define SEC_ENG_SE_SHA_HASH_SEL_MSK (((1U << SEC_ENG_SE_SHA_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_HASH_SEL_POS) +#define SEC_ENG_SE_SHA_HASH_SEL_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_HASH_SEL_POS)) +#define SEC_ENG_SE_SHA_INT SEC_ENG_SE_SHA_INT +#define SEC_ENG_SE_SHA_INT_POS (8U) +#define SEC_ENG_SE_SHA_INT_LEN (1U) +#define SEC_ENG_SE_SHA_INT_MSK (((1U << SEC_ENG_SE_SHA_INT_LEN) - 1) << SEC_ENG_SE_SHA_INT_POS) +#define SEC_ENG_SE_SHA_INT_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_LEN) - 1) << SEC_ENG_SE_SHA_INT_POS)) +#define SEC_ENG_SE_SHA_INT_CLR_1T SEC_ENG_SE_SHA_INT_CLR_1T +#define SEC_ENG_SE_SHA_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_SHA_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_SHA_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_SHA_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_CLR_1T_POS) +#define SEC_ENG_SE_SHA_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_CLR_1T_POS)) +#define SEC_ENG_SE_SHA_INT_SET_1T SEC_ENG_SE_SHA_INT_SET_1T +#define SEC_ENG_SE_SHA_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_SHA_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_SHA_INT_SET_1T_MSK (((1U << SEC_ENG_SE_SHA_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_SET_1T_POS) +#define SEC_ENG_SE_SHA_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_SET_1T_POS)) +#define SEC_ENG_SE_SHA_INT_MASK SEC_ENG_SE_SHA_INT_MASK +#define SEC_ENG_SE_SHA_INT_MASK_POS (11U) +#define SEC_ENG_SE_SHA_INT_MASK_LEN (1U) +#define SEC_ENG_SE_SHA_INT_MASK_MSK (((1U << SEC_ENG_SE_SHA_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_INT_MASK_POS) +#define SEC_ENG_SE_SHA_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_INT_MASK_POS)) +#define SEC_ENG_SE_SHA_LINK_MODE SEC_ENG_SE_SHA_LINK_MODE +#define SEC_ENG_SE_SHA_LINK_MODE_POS (15U) +#define SEC_ENG_SE_SHA_LINK_MODE_LEN (1U) +#define SEC_ENG_SE_SHA_LINK_MODE_MSK (((1U << SEC_ENG_SE_SHA_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_LINK_MODE_POS) +#define SEC_ENG_SE_SHA_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_LINK_MODE_POS)) +#define SEC_ENG_SE_SHA_MSG_LEN SEC_ENG_SE_SHA_MSG_LEN +#define SEC_ENG_SE_SHA_MSG_LEN_POS (16U) +#define SEC_ENG_SE_SHA_MSG_LEN_LEN (16U) +#define SEC_ENG_SE_SHA_MSG_LEN_MSK (((1U << SEC_ENG_SE_SHA_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_MSG_LEN_POS) +#define SEC_ENG_SE_SHA_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_SHA_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_MSG_LEN_POS)) + +/* 0x4 : se_sha_msa */ +#define SEC_ENG_SE_SHA_MSA_OFFSET (0x4) +#define SEC_ENG_SE_SHA_MSA SEC_ENG_SE_SHA_MSA +#define SEC_ENG_SE_SHA_MSA_POS (0U) +#define SEC_ENG_SE_SHA_MSA_LEN (32U) +#define SEC_ENG_SE_SHA_MSA_MSK (((1U << SEC_ENG_SE_SHA_MSA_LEN) - 1) << SEC_ENG_SE_SHA_MSA_POS) +#define SEC_ENG_SE_SHA_MSA_UMSK (~(((1U << SEC_ENG_SE_SHA_MSA_LEN) - 1) << SEC_ENG_SE_SHA_MSA_POS)) + +/* 0x8 : se_sha_status */ +#define SEC_ENG_SE_SHA_STATUS_OFFSET (0x8) +#define SEC_ENG_SE_SHA_STATUS SEC_ENG_SE_SHA_STATUS +#define SEC_ENG_SE_SHA_STATUS_POS (0U) +#define SEC_ENG_SE_SHA_STATUS_LEN (32U) +#define SEC_ENG_SE_SHA_STATUS_MSK (((1U << SEC_ENG_SE_SHA_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_STATUS_POS) +#define SEC_ENG_SE_SHA_STATUS_UMSK (~(((1U << SEC_ENG_SE_SHA_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_STATUS_POS)) + +/* 0xc : se_sha_endian */ +#define SEC_ENG_SE_SHA_ENDIAN_OFFSET (0xc) +#define SEC_ENG_SE_SHA_DOUT_ENDIAN SEC_ENG_SE_SHA_DOUT_ENDIAN +#define SEC_ENG_SE_SHA_DOUT_ENDIAN_POS (0U) +#define SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN (1U) +#define SEC_ENG_SE_SHA_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_DOUT_ENDIAN_POS) +#define SEC_ENG_SE_SHA_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_DOUT_ENDIAN_POS)) + +/* 0x10 : se_sha_hash_l_0 */ +#define SEC_ENG_SE_SHA_HASH_L_0_OFFSET (0x10) +#define SEC_ENG_SE_SHA_HASH_L_0 SEC_ENG_SE_SHA_HASH_L_0 +#define SEC_ENG_SE_SHA_HASH_L_0_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_0_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_0_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_0_POS) +#define SEC_ENG_SE_SHA_HASH_L_0_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_0_POS)) + +/* 0x14 : se_sha_hash_l_1 */ +#define SEC_ENG_SE_SHA_HASH_L_1_OFFSET (0x14) +#define SEC_ENG_SE_SHA_HASH_L_1 SEC_ENG_SE_SHA_HASH_L_1 +#define SEC_ENG_SE_SHA_HASH_L_1_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_1_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_1_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_1_POS) +#define SEC_ENG_SE_SHA_HASH_L_1_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_1_POS)) + +/* 0x18 : se_sha_hash_l_2 */ +#define SEC_ENG_SE_SHA_HASH_L_2_OFFSET (0x18) +#define SEC_ENG_SE_SHA_HASH_L_2 SEC_ENG_SE_SHA_HASH_L_2 +#define SEC_ENG_SE_SHA_HASH_L_2_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_2_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_2_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_2_POS) +#define SEC_ENG_SE_SHA_HASH_L_2_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_2_POS)) + +/* 0x1c : se_sha_hash_l_3 */ +#define SEC_ENG_SE_SHA_HASH_L_3_OFFSET (0x1c) +#define SEC_ENG_SE_SHA_HASH_L_3 SEC_ENG_SE_SHA_HASH_L_3 +#define SEC_ENG_SE_SHA_HASH_L_3_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_3_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_3_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_3_POS) +#define SEC_ENG_SE_SHA_HASH_L_3_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_3_POS)) + +/* 0x20 : se_sha_hash_l_4 */ +#define SEC_ENG_SE_SHA_HASH_L_4_OFFSET (0x20) +#define SEC_ENG_SE_SHA_HASH_L_4 SEC_ENG_SE_SHA_HASH_L_4 +#define SEC_ENG_SE_SHA_HASH_L_4_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_4_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_4_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_4_POS) +#define SEC_ENG_SE_SHA_HASH_L_4_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_4_POS)) + +/* 0x24 : se_sha_hash_l_5 */ +#define SEC_ENG_SE_SHA_HASH_L_5_OFFSET (0x24) +#define SEC_ENG_SE_SHA_HASH_L_5 SEC_ENG_SE_SHA_HASH_L_5 +#define SEC_ENG_SE_SHA_HASH_L_5_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_5_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_5_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_5_POS) +#define SEC_ENG_SE_SHA_HASH_L_5_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_5_POS)) + +/* 0x28 : se_sha_hash_l_6 */ +#define SEC_ENG_SE_SHA_HASH_L_6_OFFSET (0x28) +#define SEC_ENG_SE_SHA_HASH_L_6 SEC_ENG_SE_SHA_HASH_L_6 +#define SEC_ENG_SE_SHA_HASH_L_6_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_6_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_6_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_6_POS) +#define SEC_ENG_SE_SHA_HASH_L_6_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_6_POS)) + +/* 0x2c : se_sha_hash_l_7 */ +#define SEC_ENG_SE_SHA_HASH_L_7_OFFSET (0x2c) +#define SEC_ENG_SE_SHA_HASH_L_7 SEC_ENG_SE_SHA_HASH_L_7 +#define SEC_ENG_SE_SHA_HASH_L_7_POS (0U) +#define SEC_ENG_SE_SHA_HASH_L_7_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_L_7_MSK (((1U << SEC_ENG_SE_SHA_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_7_POS) +#define SEC_ENG_SE_SHA_HASH_L_7_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_7_POS)) + +/* 0x30 : se_sha_hash_h_0 */ +#define SEC_ENG_SE_SHA_HASH_H_0_OFFSET (0x30) +#define SEC_ENG_SE_SHA_HASH_H_0 SEC_ENG_SE_SHA_HASH_H_0 +#define SEC_ENG_SE_SHA_HASH_H_0_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_0_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_0_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_0_POS) +#define SEC_ENG_SE_SHA_HASH_H_0_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_0_POS)) + +/* 0x34 : se_sha_hash_h_1 */ +#define SEC_ENG_SE_SHA_HASH_H_1_OFFSET (0x34) +#define SEC_ENG_SE_SHA_HASH_H_1 SEC_ENG_SE_SHA_HASH_H_1 +#define SEC_ENG_SE_SHA_HASH_H_1_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_1_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_1_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_1_POS) +#define SEC_ENG_SE_SHA_HASH_H_1_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_1_POS)) + +/* 0x38 : se_sha_hash_h_2 */ +#define SEC_ENG_SE_SHA_HASH_H_2_OFFSET (0x38) +#define SEC_ENG_SE_SHA_HASH_H_2 SEC_ENG_SE_SHA_HASH_H_2 +#define SEC_ENG_SE_SHA_HASH_H_2_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_2_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_2_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_2_POS) +#define SEC_ENG_SE_SHA_HASH_H_2_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_2_POS)) + +/* 0x3c : se_sha_hash_h_3 */ +#define SEC_ENG_SE_SHA_HASH_H_3_OFFSET (0x3c) +#define SEC_ENG_SE_SHA_HASH_H_3 SEC_ENG_SE_SHA_HASH_H_3 +#define SEC_ENG_SE_SHA_HASH_H_3_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_3_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_3_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_3_POS) +#define SEC_ENG_SE_SHA_HASH_H_3_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_3_POS)) + +/* 0x40 : se_sha_hash_h_4 */ +#define SEC_ENG_SE_SHA_HASH_H_4_OFFSET (0x40) +#define SEC_ENG_SE_SHA_HASH_H_4 SEC_ENG_SE_SHA_HASH_H_4 +#define SEC_ENG_SE_SHA_HASH_H_4_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_4_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_4_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_4_POS) +#define SEC_ENG_SE_SHA_HASH_H_4_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_4_POS)) + +/* 0x44 : se_sha_hash_h_5 */ +#define SEC_ENG_SE_SHA_HASH_H_5_OFFSET (0x44) +#define SEC_ENG_SE_SHA_HASH_H_5 SEC_ENG_SE_SHA_HASH_H_5 +#define SEC_ENG_SE_SHA_HASH_H_5_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_5_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_5_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_5_POS) +#define SEC_ENG_SE_SHA_HASH_H_5_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_5_POS)) + +/* 0x48 : se_sha_hash_h_6 */ +#define SEC_ENG_SE_SHA_HASH_H_6_OFFSET (0x48) +#define SEC_ENG_SE_SHA_HASH_H_6 SEC_ENG_SE_SHA_HASH_H_6 +#define SEC_ENG_SE_SHA_HASH_H_6_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_6_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_6_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_6_POS) +#define SEC_ENG_SE_SHA_HASH_H_6_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_6_POS)) + +/* 0x4c : se_sha_hash_h_7 */ +#define SEC_ENG_SE_SHA_HASH_H_7_OFFSET (0x4c) +#define SEC_ENG_SE_SHA_HASH_H_7 SEC_ENG_SE_SHA_HASH_H_7 +#define SEC_ENG_SE_SHA_HASH_H_7_POS (0U) +#define SEC_ENG_SE_SHA_HASH_H_7_LEN (32U) +#define SEC_ENG_SE_SHA_HASH_H_7_MSK (((1U << SEC_ENG_SE_SHA_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_7_POS) +#define SEC_ENG_SE_SHA_HASH_H_7_UMSK (~(((1U << SEC_ENG_SE_SHA_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_7_POS)) + +/* 0x50 : se_sha_link */ +#define SEC_ENG_SE_SHA_LINK_OFFSET (0x50) +#define SEC_ENG_SE_SHA_LCA SEC_ENG_SE_SHA_LCA +#define SEC_ENG_SE_SHA_LCA_POS (0U) +#define SEC_ENG_SE_SHA_LCA_LEN (32U) +#define SEC_ENG_SE_SHA_LCA_MSK (((1U << SEC_ENG_SE_SHA_LCA_LEN) - 1) << SEC_ENG_SE_SHA_LCA_POS) +#define SEC_ENG_SE_SHA_LCA_UMSK (~(((1U << SEC_ENG_SE_SHA_LCA_LEN) - 1) << SEC_ENG_SE_SHA_LCA_POS)) + +/* 0xfc : se_sha_ctrl_prot */ +#define SEC_ENG_SE_SHA_CTRL_PROT_OFFSET (0xfc) +#define SEC_ENG_SE_SHA_PROT_EN SEC_ENG_SE_SHA_PROT_EN +#define SEC_ENG_SE_SHA_PROT_EN_POS (0U) +#define SEC_ENG_SE_SHA_PROT_EN_LEN (1U) +#define SEC_ENG_SE_SHA_PROT_EN_MSK (((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS) +#define SEC_ENG_SE_SHA_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS)) +#define SEC_ENG_SE_SHA_ID0_EN SEC_ENG_SE_SHA_ID0_EN +#define SEC_ENG_SE_SHA_ID0_EN_POS (1U) +#define SEC_ENG_SE_SHA_ID0_EN_LEN (1U) +#define SEC_ENG_SE_SHA_ID0_EN_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS) +#define SEC_ENG_SE_SHA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)) +#define SEC_ENG_SE_SHA_ID1_EN SEC_ENG_SE_SHA_ID1_EN +#define SEC_ENG_SE_SHA_ID1_EN_POS (2U) +#define SEC_ENG_SE_SHA_ID1_EN_LEN (1U) +#define SEC_ENG_SE_SHA_ID1_EN_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS) +#define SEC_ENG_SE_SHA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)) + +struct sec_eng_sha_reg { + /* 0x0 : se_sha_ctrl */ + union { + struct + { + uint32_t se_sha_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_sha_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_sha_mode : 3; /* [ 4: 2], r/w, 0x0 */ + uint32_t se_sha_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t se_sha_hash_sel : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t se_sha_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_sha_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_sha_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_sha_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_14 : 3; /* [14:12], rsvd, 0x0 */ + uint32_t se_sha_link_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t se_sha_msg_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_ctrl; + + /* 0x4 : se_sha_msa */ + union { + struct + { + uint32_t se_sha_msa : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_msa; + + /* 0x8 : se_sha_status */ + union { + struct + { + uint32_t se_sha_status : 32; /* [31: 0], r, 0x41 */ + } BF; + uint32_t WORD; + } se_sha_status; + + /* 0xc : se_sha_endian */ + union { + struct + { + uint32_t se_sha_dout_endian : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_endian; + + /* 0x10 : se_sha_hash_l_0 */ + union { + struct + { + uint32_t se_sha_hash_l_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_0; + + /* 0x14 : se_sha_hash_l_1 */ + union { + struct + { + uint32_t se_sha_hash_l_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_1; + + /* 0x18 : se_sha_hash_l_2 */ + union { + struct + { + uint32_t se_sha_hash_l_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_2; + + /* 0x1c : se_sha_hash_l_3 */ + union { + struct + { + uint32_t se_sha_hash_l_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_3; + + /* 0x20 : se_sha_hash_l_4 */ + union { + struct + { + uint32_t se_sha_hash_l_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_4; + + /* 0x24 : se_sha_hash_l_5 */ + union { + struct + { + uint32_t se_sha_hash_l_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_5; + + /* 0x28 : se_sha_hash_l_6 */ + union { + struct + { + uint32_t se_sha_hash_l_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_6; + + /* 0x2c : se_sha_hash_l_7 */ + union { + struct + { + uint32_t se_sha_hash_l_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_l_7; + + /* 0x30 : se_sha_hash_h_0 */ + union { + struct + { + uint32_t se_sha_hash_h_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_0; + + /* 0x34 : se_sha_hash_h_1 */ + union { + struct + { + uint32_t se_sha_hash_h_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_1; + + /* 0x38 : se_sha_hash_h_2 */ + union { + struct + { + uint32_t se_sha_hash_h_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_2; + + /* 0x3c : se_sha_hash_h_3 */ + union { + struct + { + uint32_t se_sha_hash_h_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_3; + + /* 0x40 : se_sha_hash_h_4 */ + union { + struct + { + uint32_t se_sha_hash_h_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_4; + + /* 0x44 : se_sha_hash_h_5 */ + union { + struct + { + uint32_t se_sha_hash_h_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_5; + + /* 0x48 : se_sha_hash_h_6 */ + union { + struct + { + uint32_t se_sha_hash_h_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_6; + + /* 0x4c : se_sha_hash_h_7 */ + union { + struct + { + uint32_t se_sha_hash_h_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_hash_h_7; + + /* 0x50 : se_sha_link */ + union { + struct + { + uint32_t se_sha_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_link; + + /* 0x54 reserved */ + uint8_t RESERVED0x54[168]; + + /* 0xfc : se_sha_ctrl_prot */ + union { + struct + { + uint32_t se_sha_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_sha_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_sha_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_sha_ctrl_prot; +}; + +typedef volatile struct sec_eng_sha_reg sec_eng_sha_reg_t; + +#define SEC_ENG_SHA_OFFSET 0x000 + +/*Following is reg patch*/ + +/* 0x0 : se_aes_ctrl */ +#define SEC_ENG_SE_AES_CTRL_OFFSET (0x0) +#define SEC_ENG_SE_AES_BUSY SEC_ENG_SE_AES_BUSY +#define SEC_ENG_SE_AES_BUSY_POS (0U) +#define SEC_ENG_SE_AES_BUSY_LEN (1U) +#define SEC_ENG_SE_AES_BUSY_MSK (((1U << SEC_ENG_SE_AES_BUSY_LEN) - 1) << SEC_ENG_SE_AES_BUSY_POS) +#define SEC_ENG_SE_AES_BUSY_UMSK (~(((1U << SEC_ENG_SE_AES_BUSY_LEN) - 1) << SEC_ENG_SE_AES_BUSY_POS)) +#define SEC_ENG_SE_AES_TRIG_1T SEC_ENG_SE_AES_TRIG_1T +#define SEC_ENG_SE_AES_TRIG_1T_POS (1U) +#define SEC_ENG_SE_AES_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_AES_TRIG_1T_MSK (((1U << SEC_ENG_SE_AES_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_TRIG_1T_POS) +#define SEC_ENG_SE_AES_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_AES_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_TRIG_1T_POS)) +#define SEC_ENG_SE_AES_EN SEC_ENG_SE_AES_EN +#define SEC_ENG_SE_AES_EN_POS (2U) +#define SEC_ENG_SE_AES_EN_LEN (1U) +#define SEC_ENG_SE_AES_EN_MSK (((1U << SEC_ENG_SE_AES_EN_LEN) - 1) << SEC_ENG_SE_AES_EN_POS) +#define SEC_ENG_SE_AES_EN_UMSK (~(((1U << SEC_ENG_SE_AES_EN_LEN) - 1) << SEC_ENG_SE_AES_EN_POS)) +#define SEC_ENG_SE_AES_MODE SEC_ENG_SE_AES_MODE +#define SEC_ENG_SE_AES_MODE_POS (3U) +#define SEC_ENG_SE_AES_MODE_LEN (2U) +#define SEC_ENG_SE_AES_MODE_MSK (((1U << SEC_ENG_SE_AES_MODE_LEN) - 1) << SEC_ENG_SE_AES_MODE_POS) +#define SEC_ENG_SE_AES_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_MODE_LEN) - 1) << SEC_ENG_SE_AES_MODE_POS)) +#define SEC_ENG_SE_AES_DEC_EN SEC_ENG_SE_AES_DEC_EN +#define SEC_ENG_SE_AES_DEC_EN_POS (5U) +#define SEC_ENG_SE_AES_DEC_EN_LEN (1U) +#define SEC_ENG_SE_AES_DEC_EN_MSK (((1U << SEC_ENG_SE_AES_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_DEC_EN_POS) +#define SEC_ENG_SE_AES_DEC_EN_UMSK (~(((1U << SEC_ENG_SE_AES_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_DEC_EN_POS)) +#define SEC_ENG_SE_AES_DEC_KEY_SEL SEC_ENG_SE_AES_DEC_KEY_SEL +#define SEC_ENG_SE_AES_DEC_KEY_SEL_POS (6U) +#define SEC_ENG_SE_AES_DEC_KEY_SEL_LEN (1U) +#define SEC_ENG_SE_AES_DEC_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_DEC_KEY_SEL_POS) +#define SEC_ENG_SE_AES_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_DEC_KEY_SEL_POS)) +#define SEC_ENG_SE_AES_HW_KEY_EN SEC_ENG_SE_AES_HW_KEY_EN +#define SEC_ENG_SE_AES_HW_KEY_EN_POS (7U) +#define SEC_ENG_SE_AES_HW_KEY_EN_LEN (1U) +#define SEC_ENG_SE_AES_HW_KEY_EN_MSK (((1U << SEC_ENG_SE_AES_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_HW_KEY_EN_POS) +#define SEC_ENG_SE_AES_HW_KEY_EN_UMSK (~(((1U << SEC_ENG_SE_AES_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_HW_KEY_EN_POS)) +#define SEC_ENG_SE_AES_INT SEC_ENG_SE_AES_INT +#define SEC_ENG_SE_AES_INT_POS (8U) +#define SEC_ENG_SE_AES_INT_LEN (1U) +#define SEC_ENG_SE_AES_INT_MSK (((1U << SEC_ENG_SE_AES_INT_LEN) - 1) << SEC_ENG_SE_AES_INT_POS) +#define SEC_ENG_SE_AES_INT_UMSK (~(((1U << SEC_ENG_SE_AES_INT_LEN) - 1) << SEC_ENG_SE_AES_INT_POS)) +#define SEC_ENG_SE_AES_INT_CLR_1T SEC_ENG_SE_AES_INT_CLR_1T +#define SEC_ENG_SE_AES_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_AES_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_AES_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_AES_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_CLR_1T_POS) +#define SEC_ENG_SE_AES_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_AES_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_CLR_1T_POS)) +#define SEC_ENG_SE_AES_INT_SET_1T SEC_ENG_SE_AES_INT_SET_1T +#define SEC_ENG_SE_AES_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_AES_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_AES_INT_SET_1T_MSK (((1U << SEC_ENG_SE_AES_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_SET_1T_POS) +#define SEC_ENG_SE_AES_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_AES_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_SET_1T_POS)) +#define SEC_ENG_SE_AES_INT_MASK SEC_ENG_SE_AES_INT_MASK +#define SEC_ENG_SE_AES_INT_MASK_POS (11U) +#define SEC_ENG_SE_AES_INT_MASK_LEN (1U) +#define SEC_ENG_SE_AES_INT_MASK_MSK (((1U << SEC_ENG_SE_AES_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_INT_MASK_POS) +#define SEC_ENG_SE_AES_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_AES_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_INT_MASK_POS)) +#define SEC_ENG_SE_AES_BLOCK_MODE SEC_ENG_SE_AES_BLOCK_MODE +#define SEC_ENG_SE_AES_BLOCK_MODE_POS (12U) +#define SEC_ENG_SE_AES_BLOCK_MODE_LEN (2U) +#define SEC_ENG_SE_AES_BLOCK_MODE_MSK (((1U << SEC_ENG_SE_AES_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_BLOCK_MODE_POS) +#define SEC_ENG_SE_AES_BLOCK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_BLOCK_MODE_POS)) +#define SEC_ENG_SE_AES_IV_SEL SEC_ENG_SE_AES_IV_SEL +#define SEC_ENG_SE_AES_IV_SEL_POS (14U) +#define SEC_ENG_SE_AES_IV_SEL_LEN (1U) +#define SEC_ENG_SE_AES_IV_SEL_MSK (((1U << SEC_ENG_SE_AES_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_IV_SEL_POS) +#define SEC_ENG_SE_AES_IV_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_IV_SEL_POS)) +#define SEC_ENG_SE_AES_LINK_MODE SEC_ENG_SE_AES_LINK_MODE +#define SEC_ENG_SE_AES_LINK_MODE_POS (15U) +#define SEC_ENG_SE_AES_LINK_MODE_LEN (1U) +#define SEC_ENG_SE_AES_LINK_MODE_MSK (((1U << SEC_ENG_SE_AES_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_LINK_MODE_POS) +#define SEC_ENG_SE_AES_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_LINK_MODE_POS)) +#define SEC_ENG_SE_AES_MSG_LEN SEC_ENG_SE_AES_MSG_LEN +#define SEC_ENG_SE_AES_MSG_LEN_POS (16U) +#define SEC_ENG_SE_AES_MSG_LEN_LEN (16U) +#define SEC_ENG_SE_AES_MSG_LEN_MSK (((1U << SEC_ENG_SE_AES_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_MSG_LEN_POS) +#define SEC_ENG_SE_AES_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_MSG_LEN_POS)) + +/* 0x4 : se_aes_msa */ +#define SEC_ENG_SE_AES_MSA_OFFSET (0x4) +#define SEC_ENG_SE_AES_MSA SEC_ENG_SE_AES_MSA +#define SEC_ENG_SE_AES_MSA_POS (0U) +#define SEC_ENG_SE_AES_MSA_LEN (32U) +#define SEC_ENG_SE_AES_MSA_MSK (((1U << SEC_ENG_SE_AES_MSA_LEN) - 1) << SEC_ENG_SE_AES_MSA_POS) +#define SEC_ENG_SE_AES_MSA_UMSK (~(((1U << SEC_ENG_SE_AES_MSA_LEN) - 1) << SEC_ENG_SE_AES_MSA_POS)) + +/* 0x8 : se_aes_mda */ +#define SEC_ENG_SE_AES_MDA_OFFSET (0x8) +#define SEC_ENG_SE_AES_MDA SEC_ENG_SE_AES_MDA +#define SEC_ENG_SE_AES_MDA_POS (0U) +#define SEC_ENG_SE_AES_MDA_LEN (32U) +#define SEC_ENG_SE_AES_MDA_MSK (((1U << SEC_ENG_SE_AES_MDA_LEN) - 1) << SEC_ENG_SE_AES_MDA_POS) +#define SEC_ENG_SE_AES_MDA_UMSK (~(((1U << SEC_ENG_SE_AES_MDA_LEN) - 1) << SEC_ENG_SE_AES_MDA_POS)) + +/* 0xc : se_aes_status */ +#define SEC_ENG_SE_AES_STATUS_OFFSET (0xc) +#define SEC_ENG_SE_AES_STATUS SEC_ENG_SE_AES_STATUS +#define SEC_ENG_SE_AES_STATUS_POS (0U) +#define SEC_ENG_SE_AES_STATUS_LEN (32U) +#define SEC_ENG_SE_AES_STATUS_MSK (((1U << SEC_ENG_SE_AES_STATUS_LEN) - 1) << SEC_ENG_SE_AES_STATUS_POS) +#define SEC_ENG_SE_AES_STATUS_UMSK (~(((1U << SEC_ENG_SE_AES_STATUS_LEN) - 1) << SEC_ENG_SE_AES_STATUS_POS)) + +/* 0x10 : se_aes_iv_0 */ +#define SEC_ENG_SE_AES_IV_0_OFFSET (0x10) +#define SEC_ENG_SE_AES_IV_0 SEC_ENG_SE_AES_IV_0 +#define SEC_ENG_SE_AES_IV_0_POS (0U) +#define SEC_ENG_SE_AES_IV_0_LEN (32U) +#define SEC_ENG_SE_AES_IV_0_MSK (((1U << SEC_ENG_SE_AES_IV_0_LEN) - 1) << SEC_ENG_SE_AES_IV_0_POS) +#define SEC_ENG_SE_AES_IV_0_UMSK (~(((1U << SEC_ENG_SE_AES_IV_0_LEN) - 1) << SEC_ENG_SE_AES_IV_0_POS)) + +/* 0x14 : se_aes_iv_1 */ +#define SEC_ENG_SE_AES_IV_1_OFFSET (0x14) +#define SEC_ENG_SE_AES_IV_1 SEC_ENG_SE_AES_IV_1 +#define SEC_ENG_SE_AES_IV_1_POS (0U) +#define SEC_ENG_SE_AES_IV_1_LEN (32U) +#define SEC_ENG_SE_AES_IV_1_MSK (((1U << SEC_ENG_SE_AES_IV_1_LEN) - 1) << SEC_ENG_SE_AES_IV_1_POS) +#define SEC_ENG_SE_AES_IV_1_UMSK (~(((1U << SEC_ENG_SE_AES_IV_1_LEN) - 1) << SEC_ENG_SE_AES_IV_1_POS)) + +/* 0x18 : se_aes_iv_2 */ +#define SEC_ENG_SE_AES_IV_2_OFFSET (0x18) +#define SEC_ENG_SE_AES_IV_2 SEC_ENG_SE_AES_IV_2 +#define SEC_ENG_SE_AES_IV_2_POS (0U) +#define SEC_ENG_SE_AES_IV_2_LEN (32U) +#define SEC_ENG_SE_AES_IV_2_MSK (((1U << SEC_ENG_SE_AES_IV_2_LEN) - 1) << SEC_ENG_SE_AES_IV_2_POS) +#define SEC_ENG_SE_AES_IV_2_UMSK (~(((1U << SEC_ENG_SE_AES_IV_2_LEN) - 1) << SEC_ENG_SE_AES_IV_2_POS)) + +/* 0x1c : se_aes_iv_3 */ +#define SEC_ENG_SE_AES_IV_3_OFFSET (0x1c) +#define SEC_ENG_SE_AES_IV_3 SEC_ENG_SE_AES_IV_3 +#define SEC_ENG_SE_AES_IV_3_POS (0U) +#define SEC_ENG_SE_AES_IV_3_LEN (32U) +#define SEC_ENG_SE_AES_IV_3_MSK (((1U << SEC_ENG_SE_AES_IV_3_LEN) - 1) << SEC_ENG_SE_AES_IV_3_POS) +#define SEC_ENG_SE_AES_IV_3_UMSK (~(((1U << SEC_ENG_SE_AES_IV_3_LEN) - 1) << SEC_ENG_SE_AES_IV_3_POS)) + +/* 0x20 : se_aes_key_0 */ +#define SEC_ENG_SE_AES_KEY_0_OFFSET (0x20) +#define SEC_ENG_SE_AES_KEY_0 SEC_ENG_SE_AES_KEY_0 +#define SEC_ENG_SE_AES_KEY_0_POS (0U) +#define SEC_ENG_SE_AES_KEY_0_LEN (32U) +#define SEC_ENG_SE_AES_KEY_0_MSK (((1U << SEC_ENG_SE_AES_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_0_POS) +#define SEC_ENG_SE_AES_KEY_0_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_0_POS)) + +/* 0x24 : se_aes_key_1 */ +#define SEC_ENG_SE_AES_KEY_1_OFFSET (0x24) +#define SEC_ENG_SE_AES_KEY_1 SEC_ENG_SE_AES_KEY_1 +#define SEC_ENG_SE_AES_KEY_1_POS (0U) +#define SEC_ENG_SE_AES_KEY_1_LEN (32U) +#define SEC_ENG_SE_AES_KEY_1_MSK (((1U << SEC_ENG_SE_AES_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_1_POS) +#define SEC_ENG_SE_AES_KEY_1_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_1_POS)) + +/* 0x28 : se_aes_key_2 */ +#define SEC_ENG_SE_AES_KEY_2_OFFSET (0x28) +#define SEC_ENG_SE_AES_KEY_2 SEC_ENG_SE_AES_KEY_2 +#define SEC_ENG_SE_AES_KEY_2_POS (0U) +#define SEC_ENG_SE_AES_KEY_2_LEN (32U) +#define SEC_ENG_SE_AES_KEY_2_MSK (((1U << SEC_ENG_SE_AES_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_KEY_2_POS) +#define SEC_ENG_SE_AES_KEY_2_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_KEY_2_POS)) + +/* 0x2c : se_aes_key_3 */ +#define SEC_ENG_SE_AES_KEY_3_OFFSET (0x2c) +#define SEC_ENG_SE_AES_KEY_3 SEC_ENG_SE_AES_KEY_3 +#define SEC_ENG_SE_AES_KEY_3_POS (0U) +#define SEC_ENG_SE_AES_KEY_3_LEN (32U) +#define SEC_ENG_SE_AES_KEY_3_MSK (((1U << SEC_ENG_SE_AES_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_KEY_3_POS) +#define SEC_ENG_SE_AES_KEY_3_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_KEY_3_POS)) + +/* 0x30 : se_aes_key_4 */ +#define SEC_ENG_SE_AES_KEY_4_OFFSET (0x30) +#define SEC_ENG_SE_AES_KEY_4 SEC_ENG_SE_AES_KEY_4 +#define SEC_ENG_SE_AES_KEY_4_POS (0U) +#define SEC_ENG_SE_AES_KEY_4_LEN (32U) +#define SEC_ENG_SE_AES_KEY_4_MSK (((1U << SEC_ENG_SE_AES_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_KEY_4_POS) +#define SEC_ENG_SE_AES_KEY_4_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_KEY_4_POS)) + +/* 0x34 : se_aes_key_5 */ +#define SEC_ENG_SE_AES_KEY_5_OFFSET (0x34) +#define SEC_ENG_SE_AES_KEY_5 SEC_ENG_SE_AES_KEY_5 +#define SEC_ENG_SE_AES_KEY_5_POS (0U) +#define SEC_ENG_SE_AES_KEY_5_LEN (32U) +#define SEC_ENG_SE_AES_KEY_5_MSK (((1U << SEC_ENG_SE_AES_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_KEY_5_POS) +#define SEC_ENG_SE_AES_KEY_5_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_KEY_5_POS)) + +/* 0x38 : se_aes_key_6 */ +#define SEC_ENG_SE_AES_KEY_6_OFFSET (0x38) +#define SEC_ENG_SE_AES_KEY_6 SEC_ENG_SE_AES_KEY_6 +#define SEC_ENG_SE_AES_KEY_6_POS (0U) +#define SEC_ENG_SE_AES_KEY_6_LEN (32U) +#define SEC_ENG_SE_AES_KEY_6_MSK (((1U << SEC_ENG_SE_AES_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_KEY_6_POS) +#define SEC_ENG_SE_AES_KEY_6_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_KEY_6_POS)) + +/* 0x3c : se_aes_key_7 */ +#define SEC_ENG_SE_AES_KEY_7_OFFSET (0x3c) +#define SEC_ENG_SE_AES_KEY_7 SEC_ENG_SE_AES_KEY_7 +#define SEC_ENG_SE_AES_KEY_7_POS (0U) +#define SEC_ENG_SE_AES_KEY_7_LEN (32U) +#define SEC_ENG_SE_AES_KEY_7_MSK (((1U << SEC_ENG_SE_AES_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_KEY_7_POS) +#define SEC_ENG_SE_AES_KEY_7_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_KEY_7_POS)) + +/* 0x40 : se_aes_key_sel_0 */ +#define SEC_ENG_SE_AES_KEY_SEL_0_OFFSET (0x40) +#define SEC_ENG_SE_AES_KEY_SEL_0 SEC_ENG_SE_AES_KEY_SEL_0 +#define SEC_ENG_SE_AES_KEY_SEL_0_POS (0U) +#define SEC_ENG_SE_AES_KEY_SEL_0_LEN (2U) +#define SEC_ENG_SE_AES_KEY_SEL_0_MSK (((1U << SEC_ENG_SE_AES_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_0_POS) +#define SEC_ENG_SE_AES_KEY_SEL_0_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_0_POS)) + +/* 0x44 : se_aes_key_sel_1 */ +#define SEC_ENG_SE_AES_KEY_SEL_1_OFFSET (0x44) +#define SEC_ENG_SE_AES_KEY_SEL_1 SEC_ENG_SE_AES_KEY_SEL_1 +#define SEC_ENG_SE_AES_KEY_SEL_1_POS (0U) +#define SEC_ENG_SE_AES_KEY_SEL_1_LEN (2U) +#define SEC_ENG_SE_AES_KEY_SEL_1_MSK (((1U << SEC_ENG_SE_AES_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_1_POS) +#define SEC_ENG_SE_AES_KEY_SEL_1_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_1_POS)) + +/* 0x48 : se_aes_endian */ +#define SEC_ENG_SE_AES_ENDIAN_OFFSET (0x48) +#define SEC_ENG_SE_AES_DOUT_ENDIAN SEC_ENG_SE_AES_DOUT_ENDIAN +#define SEC_ENG_SE_AES_DOUT_ENDIAN_POS (0U) +#define SEC_ENG_SE_AES_DOUT_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DOUT_ENDIAN_POS) +#define SEC_ENG_SE_AES_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DOUT_ENDIAN_POS)) +#define SEC_ENG_SE_AES_DIN_ENDIAN SEC_ENG_SE_AES_DIN_ENDIAN +#define SEC_ENG_SE_AES_DIN_ENDIAN_POS (1U) +#define SEC_ENG_SE_AES_DIN_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_DIN_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DIN_ENDIAN_POS) +#define SEC_ENG_SE_AES_DIN_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DIN_ENDIAN_POS)) +#define SEC_ENG_SE_AES_KEY_ENDIAN SEC_ENG_SE_AES_KEY_ENDIAN +#define SEC_ENG_SE_AES_KEY_ENDIAN_POS (2U) +#define SEC_ENG_SE_AES_KEY_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_KEY_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_KEY_ENDIAN_POS) +#define SEC_ENG_SE_AES_KEY_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_KEY_ENDIAN_POS)) +#define SEC_ENG_SE_AES_IV_ENDIAN SEC_ENG_SE_AES_IV_ENDIAN +#define SEC_ENG_SE_AES_IV_ENDIAN_POS (3U) +#define SEC_ENG_SE_AES_IV_ENDIAN_LEN (1U) +#define SEC_ENG_SE_AES_IV_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_IV_ENDIAN_POS) +#define SEC_ENG_SE_AES_IV_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_IV_ENDIAN_POS)) +#define SEC_ENG_SE_AES_CTR_LEN SEC_ENG_SE_AES_CTR_LEN +#define SEC_ENG_SE_AES_CTR_LEN_POS (30U) +#define SEC_ENG_SE_AES_CTR_LEN_LEN (2U) +#define SEC_ENG_SE_AES_CTR_LEN_MSK (((1U << SEC_ENG_SE_AES_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_CTR_LEN_POS) +#define SEC_ENG_SE_AES_CTR_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_CTR_LEN_POS)) + +/* 0x4c : se_aes_sboot */ +#define SEC_ENG_SE_AES_SBOOT_OFFSET (0x4c) +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL SEC_ENG_SE_AES_SBOOT_KEY_SEL +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS (0U) +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN (1U) +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS) +#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS)) + +/* 0x50 : se_aes_link */ +#define SEC_ENG_SE_AES_LINK_OFFSET (0x50) +#define SEC_ENG_SE_AES_LCA SEC_ENG_SE_AES_LCA +#define SEC_ENG_SE_AES_LCA_POS (0U) +#define SEC_ENG_SE_AES_LCA_LEN (32U) +#define SEC_ENG_SE_AES_LCA_MSK (((1U << SEC_ENG_SE_AES_LCA_LEN) - 1) << SEC_ENG_SE_AES_LCA_POS) +#define SEC_ENG_SE_AES_LCA_UMSK (~(((1U << SEC_ENG_SE_AES_LCA_LEN) - 1) << SEC_ENG_SE_AES_LCA_POS)) + +/* 0xfc : se_aes_ctrl_prot */ +#define SEC_ENG_SE_AES_CTRL_PROT_OFFSET (0xfc) +#define SEC_ENG_SE_AES_PROT_EN SEC_ENG_SE_AES_PROT_EN +#define SEC_ENG_SE_AES_PROT_EN_POS (0U) +#define SEC_ENG_SE_AES_PROT_EN_LEN (1U) +#define SEC_ENG_SE_AES_PROT_EN_MSK (((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS) +#define SEC_ENG_SE_AES_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS)) +#define SEC_ENG_SE_AES_ID0_EN SEC_ENG_SE_AES_ID0_EN +#define SEC_ENG_SE_AES_ID0_EN_POS (1U) +#define SEC_ENG_SE_AES_ID0_EN_LEN (1U) +#define SEC_ENG_SE_AES_ID0_EN_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS) +#define SEC_ENG_SE_AES_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)) +#define SEC_ENG_SE_AES_ID1_EN SEC_ENG_SE_AES_ID1_EN +#define SEC_ENG_SE_AES_ID1_EN_POS (2U) +#define SEC_ENG_SE_AES_ID1_EN_LEN (1U) +#define SEC_ENG_SE_AES_ID1_EN_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS) +#define SEC_ENG_SE_AES_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)) + +struct sec_eng_aes_reg { + /* 0x0 : se_aes_ctrl */ + union { + struct + { + uint32_t se_aes_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_aes_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_aes_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_aes_mode : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t se_aes_dec_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t se_aes_dec_key_sel : 1; /* [ 6], r/w, 0x0 */ + uint32_t se_aes_hw_key_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t se_aes_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_aes_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_aes_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_aes_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t se_aes_block_mode : 2; /* [13:12], r/w, 0x0 */ + uint32_t se_aes_iv_sel : 1; /* [ 14], r/w, 0x0 */ + uint32_t se_aes_link_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t se_aes_msg_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_ctrl; + + /* 0x4 : se_aes_msa */ + union { + struct + { + uint32_t se_aes_msa : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_msa; + + /* 0x8 : se_aes_mda */ + union { + struct + { + uint32_t se_aes_mda : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_mda; + + /* 0xc : se_aes_status */ + union { + struct + { + uint32_t se_aes_status : 32; /* [31: 0], r, 0x100 */ + } BF; + uint32_t WORD; + } se_aes_status; + + /* 0x10 : se_aes_iv_0 */ + union { + struct + { + uint32_t se_aes_iv_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_iv_0; + + /* 0x14 : se_aes_iv_1 */ + union { + struct + { + uint32_t se_aes_iv_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_iv_1; + + /* 0x18 : se_aes_iv_2 */ + union { + struct + { + uint32_t se_aes_iv_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_iv_2; + + /* 0x1c : se_aes_iv_3 */ + union { + struct + { + uint32_t se_aes_iv_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_iv_3; + + /* 0x20 : se_aes_key_0 */ + union { + struct + { + uint32_t se_aes_key_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_0; + + /* 0x24 : se_aes_key_1 */ + union { + struct + { + uint32_t se_aes_key_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_1; + + /* 0x28 : se_aes_key_2 */ + union { + struct + { + uint32_t se_aes_key_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_2; + + /* 0x2c : se_aes_key_3 */ + union { + struct + { + uint32_t se_aes_key_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_3; + + /* 0x30 : se_aes_key_4 */ + union { + struct + { + uint32_t se_aes_key_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_4; + + /* 0x34 : se_aes_key_5 */ + union { + struct + { + uint32_t se_aes_key_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_5; + + /* 0x38 : se_aes_key_6 */ + union { + struct + { + uint32_t se_aes_key_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_6; + + /* 0x3c : se_aes_key_7 */ + union { + struct + { + uint32_t se_aes_key_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_7; + + /* 0x40 : se_aes_key_sel_0 */ + union { + struct + { + uint32_t se_aes_key_sel_0 : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_sel_0; + + /* 0x44 : se_aes_key_sel_1 */ + union { + struct + { + uint32_t se_aes_key_sel_1 : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_key_sel_1; + + /* 0x48 : se_aes_endian */ + union { + struct + { + uint32_t se_aes_dout_endian : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_aes_din_endian : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_aes_key_endian : 1; /* [ 2], r/w, 0x1 */ + uint32_t se_aes_iv_endian : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_29 : 26; /* [29: 4], rsvd, 0x0 */ + uint32_t se_aes_ctr_len : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_endian; + + /* 0x4c : se_aes_sboot */ + union { + struct + { + uint32_t se_aes_sboot_key_sel : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_sboot; + + /* 0x50 : se_aes_link */ + union { + struct + { + uint32_t se_aes_lca : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_link; + + /* 0x54 reserved */ + uint8_t RESERVED0x54[168]; + + /* 0xfc : se_aes_ctrl_prot */ + union { + struct + { + uint32_t se_aes_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_aes_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_aes_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_aes_ctrl_prot; +}; + +typedef volatile struct sec_eng_aes_reg sec_eng_aes_reg_t; + +#define SEC_ENG_AES_OFFSET 0x100 + +/*Following is reg patch*/ + +/* 0x0 : se_trng_ctrl_0 */ +#define SEC_ENG_SE_TRNG_CTRL_0_OFFSET (0x0) +#define SEC_ENG_SE_TRNG_BUSY SEC_ENG_SE_TRNG_BUSY +#define SEC_ENG_SE_TRNG_BUSY_POS (0U) +#define SEC_ENG_SE_TRNG_BUSY_LEN (1U) +#define SEC_ENG_SE_TRNG_BUSY_MSK (((1U << SEC_ENG_SE_TRNG_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_BUSY_POS) +#define SEC_ENG_SE_TRNG_BUSY_UMSK (~(((1U << SEC_ENG_SE_TRNG_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_BUSY_POS)) +#define SEC_ENG_SE_TRNG_TRIG_1T SEC_ENG_SE_TRNG_TRIG_1T +#define SEC_ENG_SE_TRNG_TRIG_1T_POS (1U) +#define SEC_ENG_SE_TRNG_TRIG_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_TRIG_1T_MSK (((1U << SEC_ENG_SE_TRNG_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_TRIG_1T_POS) +#define SEC_ENG_SE_TRNG_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_TRIG_1T_POS)) +#define SEC_ENG_SE_TRNG_EN SEC_ENG_SE_TRNG_EN +#define SEC_ENG_SE_TRNG_EN_POS (2U) +#define SEC_ENG_SE_TRNG_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_EN_MSK (((1U << SEC_ENG_SE_TRNG_EN_LEN) - 1) << SEC_ENG_SE_TRNG_EN_POS) +#define SEC_ENG_SE_TRNG_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_EN_LEN) - 1) << SEC_ENG_SE_TRNG_EN_POS)) +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T SEC_ENG_SE_TRNG_DOUT_CLR_1T +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS (3U) +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS) +#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS)) +#define SEC_ENG_SE_TRNG_HT_ERROR SEC_ENG_SE_TRNG_HT_ERROR +#define SEC_ENG_SE_TRNG_HT_ERROR_POS (4U) +#define SEC_ENG_SE_TRNG_HT_ERROR_LEN (1U) +#define SEC_ENG_SE_TRNG_HT_ERROR_MSK (((1U << SEC_ENG_SE_TRNG_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ERROR_POS) +#define SEC_ENG_SE_TRNG_HT_ERROR_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ERROR_POS)) +#define SEC_ENG_SE_TRNG_INT SEC_ENG_SE_TRNG_INT +#define SEC_ENG_SE_TRNG_INT_POS (8U) +#define SEC_ENG_SE_TRNG_INT_LEN (1U) +#define SEC_ENG_SE_TRNG_INT_MSK (((1U << SEC_ENG_SE_TRNG_INT_LEN) - 1) << SEC_ENG_SE_TRNG_INT_POS) +#define SEC_ENG_SE_TRNG_INT_UMSK (~(((1U << SEC_ENG_SE_TRNG_INT_LEN) - 1) << SEC_ENG_SE_TRNG_INT_POS)) +#define SEC_ENG_SE_TRNG_INT_CLR_1T SEC_ENG_SE_TRNG_INT_CLR_1T +#define SEC_ENG_SE_TRNG_INT_CLR_1T_POS (9U) +#define SEC_ENG_SE_TRNG_INT_CLR_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_CLR_1T_POS) +#define SEC_ENG_SE_TRNG_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_CLR_1T_POS)) +#define SEC_ENG_SE_TRNG_INT_SET_1T SEC_ENG_SE_TRNG_INT_SET_1T +#define SEC_ENG_SE_TRNG_INT_SET_1T_POS (10U) +#define SEC_ENG_SE_TRNG_INT_SET_1T_LEN (1U) +#define SEC_ENG_SE_TRNG_INT_SET_1T_MSK (((1U << SEC_ENG_SE_TRNG_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_SET_1T_POS) +#define SEC_ENG_SE_TRNG_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_SET_1T_POS)) +#define SEC_ENG_SE_TRNG_INT_MASK SEC_ENG_SE_TRNG_INT_MASK +#define SEC_ENG_SE_TRNG_INT_MASK_POS (11U) +#define SEC_ENG_SE_TRNG_INT_MASK_LEN (1U) +#define SEC_ENG_SE_TRNG_INT_MASK_MSK (((1U << SEC_ENG_SE_TRNG_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_INT_MASK_POS) +#define SEC_ENG_SE_TRNG_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_TRNG_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_INT_MASK_POS)) +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL SEC_ENG_SE_TRNG_MANUAL_FUN_SEL +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS (13U) +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN (1U) +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_MSK (((1U << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS) +#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS)) +#define SEC_ENG_SE_TRNG_MANUAL_RESEED SEC_ENG_SE_TRNG_MANUAL_RESEED +#define SEC_ENG_SE_TRNG_MANUAL_RESEED_POS (14U) +#define SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN (1U) +#define SEC_ENG_SE_TRNG_MANUAL_RESEED_MSK (((1U << SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_RESEED_POS) +#define SEC_ENG_SE_TRNG_MANUAL_RESEED_UMSK (~(((1U << SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_RESEED_POS)) +#define SEC_ENG_SE_TRNG_MANUAL_EN SEC_ENG_SE_TRNG_MANUAL_EN +#define SEC_ENG_SE_TRNG_MANUAL_EN_POS (15U) +#define SEC_ENG_SE_TRNG_MANUAL_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_MANUAL_EN_MSK (((1U << SEC_ENG_SE_TRNG_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_EN_POS) +#define SEC_ENG_SE_TRNG_MANUAL_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_EN_POS)) + +/* 0x4 : se_trng_status */ +#define SEC_ENG_SE_TRNG_STATUS_OFFSET (0x4) +#define SEC_ENG_SE_TRNG_STATUS SEC_ENG_SE_TRNG_STATUS +#define SEC_ENG_SE_TRNG_STATUS_POS (0U) +#define SEC_ENG_SE_TRNG_STATUS_LEN (32U) +#define SEC_ENG_SE_TRNG_STATUS_MSK (((1U << SEC_ENG_SE_TRNG_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_STATUS_POS) +#define SEC_ENG_SE_TRNG_STATUS_UMSK (~(((1U << SEC_ENG_SE_TRNG_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_STATUS_POS)) + +/* 0x8 : se_trng_dout_0 */ +#define SEC_ENG_SE_TRNG_DOUT_0_OFFSET (0x8) +#define SEC_ENG_SE_TRNG_DOUT_0 SEC_ENG_SE_TRNG_DOUT_0 +#define SEC_ENG_SE_TRNG_DOUT_0_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_0_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_0_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_0_POS) +#define SEC_ENG_SE_TRNG_DOUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_0_POS)) + +/* 0xc : se_trng_dout_1 */ +#define SEC_ENG_SE_TRNG_DOUT_1_OFFSET (0xc) +#define SEC_ENG_SE_TRNG_DOUT_1 SEC_ENG_SE_TRNG_DOUT_1 +#define SEC_ENG_SE_TRNG_DOUT_1_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_1_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_1_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_1_POS) +#define SEC_ENG_SE_TRNG_DOUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_1_POS)) + +/* 0x10 : se_trng_dout_2 */ +#define SEC_ENG_SE_TRNG_DOUT_2_OFFSET (0x10) +#define SEC_ENG_SE_TRNG_DOUT_2 SEC_ENG_SE_TRNG_DOUT_2 +#define SEC_ENG_SE_TRNG_DOUT_2_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_2_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_2_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_2_POS) +#define SEC_ENG_SE_TRNG_DOUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_2_POS)) + +/* 0x14 : se_trng_dout_3 */ +#define SEC_ENG_SE_TRNG_DOUT_3_OFFSET (0x14) +#define SEC_ENG_SE_TRNG_DOUT_3 SEC_ENG_SE_TRNG_DOUT_3 +#define SEC_ENG_SE_TRNG_DOUT_3_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_3_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_3_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_3_POS) +#define SEC_ENG_SE_TRNG_DOUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_3_POS)) + +/* 0x18 : se_trng_dout_4 */ +#define SEC_ENG_SE_TRNG_DOUT_4_OFFSET (0x18) +#define SEC_ENG_SE_TRNG_DOUT_4 SEC_ENG_SE_TRNG_DOUT_4 +#define SEC_ENG_SE_TRNG_DOUT_4_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_4_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_4_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_4_POS) +#define SEC_ENG_SE_TRNG_DOUT_4_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_4_POS)) + +/* 0x1c : se_trng_dout_5 */ +#define SEC_ENG_SE_TRNG_DOUT_5_OFFSET (0x1c) +#define SEC_ENG_SE_TRNG_DOUT_5 SEC_ENG_SE_TRNG_DOUT_5 +#define SEC_ENG_SE_TRNG_DOUT_5_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_5_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_5_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_5_POS) +#define SEC_ENG_SE_TRNG_DOUT_5_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_5_POS)) + +/* 0x20 : se_trng_dout_6 */ +#define SEC_ENG_SE_TRNG_DOUT_6_OFFSET (0x20) +#define SEC_ENG_SE_TRNG_DOUT_6 SEC_ENG_SE_TRNG_DOUT_6 +#define SEC_ENG_SE_TRNG_DOUT_6_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_6_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_6_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_6_POS) +#define SEC_ENG_SE_TRNG_DOUT_6_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_6_POS)) + +/* 0x24 : se_trng_dout_7 */ +#define SEC_ENG_SE_TRNG_DOUT_7_OFFSET (0x24) +#define SEC_ENG_SE_TRNG_DOUT_7 SEC_ENG_SE_TRNG_DOUT_7 +#define SEC_ENG_SE_TRNG_DOUT_7_POS (0U) +#define SEC_ENG_SE_TRNG_DOUT_7_LEN (32U) +#define SEC_ENG_SE_TRNG_DOUT_7_MSK (((1U << SEC_ENG_SE_TRNG_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_7_POS) +#define SEC_ENG_SE_TRNG_DOUT_7_UMSK (~(((1U << SEC_ENG_SE_TRNG_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_7_POS)) + +/* 0x28 : se_trng_test */ +#define SEC_ENG_SE_TRNG_TEST_OFFSET (0x28) +#define SEC_ENG_SE_TRNG_TEST_EN SEC_ENG_SE_TRNG_TEST_EN +#define SEC_ENG_SE_TRNG_TEST_EN_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_EN_POS) +#define SEC_ENG_SE_TRNG_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_EN_POS)) +#define SEC_ENG_SE_TRNG_CP_TEST_EN SEC_ENG_SE_TRNG_CP_TEST_EN +#define SEC_ENG_SE_TRNG_CP_TEST_EN_POS (1U) +#define SEC_ENG_SE_TRNG_CP_TEST_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_CP_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_CP_TEST_EN_POS) +#define SEC_ENG_SE_TRNG_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_CP_TEST_EN_POS)) +#define SEC_ENG_SE_TRNG_CP_BYPASS SEC_ENG_SE_TRNG_CP_BYPASS +#define SEC_ENG_SE_TRNG_CP_BYPASS_POS (2U) +#define SEC_ENG_SE_TRNG_CP_BYPASS_LEN (1U) +#define SEC_ENG_SE_TRNG_CP_BYPASS_MSK (((1U << SEC_ENG_SE_TRNG_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_CP_BYPASS_POS) +#define SEC_ENG_SE_TRNG_CP_BYPASS_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_CP_BYPASS_POS)) +#define SEC_ENG_SE_TRNG_HT_DIS SEC_ENG_SE_TRNG_HT_DIS +#define SEC_ENG_SE_TRNG_HT_DIS_POS (3U) +#define SEC_ENG_SE_TRNG_HT_DIS_LEN (1U) +#define SEC_ENG_SE_TRNG_HT_DIS_MSK (((1U << SEC_ENG_SE_TRNG_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_HT_DIS_POS) +#define SEC_ENG_SE_TRNG_HT_DIS_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_HT_DIS_POS)) +#define SEC_ENG_SE_TRNG_HT_ALARM_N SEC_ENG_SE_TRNG_HT_ALARM_N +#define SEC_ENG_SE_TRNG_HT_ALARM_N_POS (4U) +#define SEC_ENG_SE_TRNG_HT_ALARM_N_LEN (8U) +#define SEC_ENG_SE_TRNG_HT_ALARM_N_MSK (((1U << SEC_ENG_SE_TRNG_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ALARM_N_POS) +#define SEC_ENG_SE_TRNG_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ALARM_N_POS)) + +/* 0x2c : se_trng_ctrl_1 */ +#define SEC_ENG_SE_TRNG_CTRL_1_OFFSET (0x2c) +#define SEC_ENG_SE_TRNG_RESEED_N_LSB SEC_ENG_SE_TRNG_RESEED_N_LSB +#define SEC_ENG_SE_TRNG_RESEED_N_LSB_POS (0U) +#define SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN (32U) +#define SEC_ENG_SE_TRNG_RESEED_N_LSB_MSK (((1U << SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_LSB_POS) +#define SEC_ENG_SE_TRNG_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_LSB_POS)) + +/* 0x30 : se_trng_ctrl_2 */ +#define SEC_ENG_SE_TRNG_CTRL_2_OFFSET (0x30) +#define SEC_ENG_SE_TRNG_RESEED_N_MSB SEC_ENG_SE_TRNG_RESEED_N_MSB +#define SEC_ENG_SE_TRNG_RESEED_N_MSB_POS (0U) +#define SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN (16U) +#define SEC_ENG_SE_TRNG_RESEED_N_MSB_MSK (((1U << SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_MSB_POS) +#define SEC_ENG_SE_TRNG_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_MSB_POS)) + +/* 0x34 : se_trng_ctrl_3 */ +#define SEC_ENG_SE_TRNG_CTRL_3_OFFSET (0x34) +#define SEC_ENG_SE_TRNG_CP_RATIO SEC_ENG_SE_TRNG_CP_RATIO +#define SEC_ENG_SE_TRNG_CP_RATIO_POS (0U) +#define SEC_ENG_SE_TRNG_CP_RATIO_LEN (8U) +#define SEC_ENG_SE_TRNG_CP_RATIO_MSK (((1U << SEC_ENG_SE_TRNG_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_CP_RATIO_POS) +#define SEC_ENG_SE_TRNG_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_CP_RATIO_POS)) +#define SEC_ENG_SE_TRNG_HT_RCT_C SEC_ENG_SE_TRNG_HT_RCT_C +#define SEC_ENG_SE_TRNG_HT_RCT_C_POS (8U) +#define SEC_ENG_SE_TRNG_HT_RCT_C_LEN (8U) +#define SEC_ENG_SE_TRNG_HT_RCT_C_MSK (((1U << SEC_ENG_SE_TRNG_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_RCT_C_POS) +#define SEC_ENG_SE_TRNG_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_RCT_C_POS)) +#define SEC_ENG_SE_TRNG_HT_APT_C SEC_ENG_SE_TRNG_HT_APT_C +#define SEC_ENG_SE_TRNG_HT_APT_C_POS (16U) +#define SEC_ENG_SE_TRNG_HT_APT_C_LEN (10U) +#define SEC_ENG_SE_TRNG_HT_APT_C_MSK (((1U << SEC_ENG_SE_TRNG_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_APT_C_POS) +#define SEC_ENG_SE_TRNG_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_APT_C_POS)) +#define SEC_ENG_SE_TRNG_HT_OD_EN SEC_ENG_SE_TRNG_HT_OD_EN +#define SEC_ENG_SE_TRNG_HT_OD_EN_POS (26U) +#define SEC_ENG_SE_TRNG_HT_OD_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_HT_OD_EN_MSK (((1U << SEC_ENG_SE_TRNG_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_HT_OD_EN_POS) +#define SEC_ENG_SE_TRNG_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_HT_OD_EN_POS)) +#define SEC_ENG_SE_TRNG_ROSC_EN SEC_ENG_SE_TRNG_ROSC_EN +#define SEC_ENG_SE_TRNG_ROSC_EN_POS (31U) +#define SEC_ENG_SE_TRNG_ROSC_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ROSC_EN_MSK (((1U << SEC_ENG_SE_TRNG_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ROSC_EN_POS) +#define SEC_ENG_SE_TRNG_ROSC_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ROSC_EN_POS)) + +/* 0x40 : se_trng_test_out_0 */ +#define SEC_ENG_SE_TRNG_TEST_OUT_0_OFFSET (0x40) +#define SEC_ENG_SE_TRNG_TEST_OUT_0 SEC_ENG_SE_TRNG_TEST_OUT_0 +#define SEC_ENG_SE_TRNG_TEST_OUT_0_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_OUT_0_LEN (32U) +#define SEC_ENG_SE_TRNG_TEST_OUT_0_MSK (((1U << SEC_ENG_SE_TRNG_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_0_POS) +#define SEC_ENG_SE_TRNG_TEST_OUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_0_POS)) + +/* 0x44 : se_trng_test_out_1 */ +#define SEC_ENG_SE_TRNG_TEST_OUT_1_OFFSET (0x44) +#define SEC_ENG_SE_TRNG_TEST_OUT_1 SEC_ENG_SE_TRNG_TEST_OUT_1 +#define SEC_ENG_SE_TRNG_TEST_OUT_1_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_OUT_1_LEN (32U) +#define SEC_ENG_SE_TRNG_TEST_OUT_1_MSK (((1U << SEC_ENG_SE_TRNG_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_1_POS) +#define SEC_ENG_SE_TRNG_TEST_OUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_1_POS)) + +/* 0x48 : se_trng_test_out_2 */ +#define SEC_ENG_SE_TRNG_TEST_OUT_2_OFFSET (0x48) +#define SEC_ENG_SE_TRNG_TEST_OUT_2 SEC_ENG_SE_TRNG_TEST_OUT_2 +#define SEC_ENG_SE_TRNG_TEST_OUT_2_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_OUT_2_LEN (32U) +#define SEC_ENG_SE_TRNG_TEST_OUT_2_MSK (((1U << SEC_ENG_SE_TRNG_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_2_POS) +#define SEC_ENG_SE_TRNG_TEST_OUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_2_POS)) + +/* 0x4c : se_trng_test_out_3 */ +#define SEC_ENG_SE_TRNG_TEST_OUT_3_OFFSET (0x4c) +#define SEC_ENG_SE_TRNG_TEST_OUT_3 SEC_ENG_SE_TRNG_TEST_OUT_3 +#define SEC_ENG_SE_TRNG_TEST_OUT_3_POS (0U) +#define SEC_ENG_SE_TRNG_TEST_OUT_3_LEN (32U) +#define SEC_ENG_SE_TRNG_TEST_OUT_3_MSK (((1U << SEC_ENG_SE_TRNG_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_3_POS) +#define SEC_ENG_SE_TRNG_TEST_OUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_3_POS)) + +/* 0xfc : se_trng_ctrl_prot */ +#define SEC_ENG_SE_TRNG_CTRL_PROT_OFFSET (0xfc) +#define SEC_ENG_SE_TRNG_PROT_EN SEC_ENG_SE_TRNG_PROT_EN +#define SEC_ENG_SE_TRNG_PROT_EN_POS (0U) +#define SEC_ENG_SE_TRNG_PROT_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_PROT_EN_MSK (((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS) +#define SEC_ENG_SE_TRNG_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS)) +#define SEC_ENG_SE_TRNG_ID0_EN SEC_ENG_SE_TRNG_ID0_EN +#define SEC_ENG_SE_TRNG_ID0_EN_POS (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ID0_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS) +#define SEC_ENG_SE_TRNG_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)) +#define SEC_ENG_SE_TRNG_ID1_EN SEC_ENG_SE_TRNG_ID1_EN +#define SEC_ENG_SE_TRNG_ID1_EN_POS (2U) +#define SEC_ENG_SE_TRNG_ID1_EN_LEN (1U) +#define SEC_ENG_SE_TRNG_ID1_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS) +#define SEC_ENG_SE_TRNG_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)) + +struct sec_eng_trng_reg { + /* 0x0 : se_trng_ctrl_0 */ + union { + struct + { + uint32_t se_trng_busy : 1; /* [ 0], r, 0x0 */ + uint32_t se_trng_trig_1t : 1; /* [ 1], w1p, 0x0 */ + uint32_t se_trng_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_trng_dout_clr_1t : 1; /* [ 3], w1p, 0x0 */ + uint32_t se_trng_ht_error : 1; /* [ 4], r, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t se_trng_int : 1; /* [ 8], r, 0x0 */ + uint32_t se_trng_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ + uint32_t se_trng_int_set_1t : 1; /* [ 10], w1p, 0x0 */ + uint32_t se_trng_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ + uint32_t se_trng_manual_fun_sel : 1; /* [ 13], r/w, 0x0 */ + uint32_t se_trng_manual_reseed : 1; /* [ 14], r/w, 0x0 */ + uint32_t se_trng_manual_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_ctrl_0; + + /* 0x4 : se_trng_status */ + union { + struct + { + uint32_t se_trng_status : 32; /* [31: 0], r, 0x100020 */ + } BF; + uint32_t WORD; + } se_trng_status; + + /* 0x8 : se_trng_dout_0 */ + union { + struct + { + uint32_t se_trng_dout_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_0; + + /* 0xc : se_trng_dout_1 */ + union { + struct + { + uint32_t se_trng_dout_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_1; + + /* 0x10 : se_trng_dout_2 */ + union { + struct + { + uint32_t se_trng_dout_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_2; + + /* 0x14 : se_trng_dout_3 */ + union { + struct + { + uint32_t se_trng_dout_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_3; + + /* 0x18 : se_trng_dout_4 */ + union { + struct + { + uint32_t se_trng_dout_4 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_4; + + /* 0x1c : se_trng_dout_5 */ + union { + struct + { + uint32_t se_trng_dout_5 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_5; + + /* 0x20 : se_trng_dout_6 */ + union { + struct + { + uint32_t se_trng_dout_6 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_6; + + /* 0x24 : se_trng_dout_7 */ + union { + struct + { + uint32_t se_trng_dout_7 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_dout_7; + + /* 0x28 : se_trng_test */ + union { + struct + { + uint32_t se_trng_test_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t se_trng_cp_test_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t se_trng_cp_bypass : 1; /* [ 2], r/w, 0x0 */ + uint32_t se_trng_ht_dis : 1; /* [ 3], r/w, 0x0 */ + uint32_t se_trng_ht_alarm_n : 8; /* [11: 4], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test; + + /* 0x2c : se_trng_ctrl_1 */ + union { + struct + { + uint32_t se_trng_reseed_n_lsb : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } se_trng_ctrl_1; + + /* 0x30 : se_trng_ctrl_2 */ + union { + struct + { + uint32_t se_trng_reseed_n_msb : 16; /* [15: 0], r/w, 0xff */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_ctrl_2; + + /* 0x34 : se_trng_ctrl_3 */ + union { + struct + { + uint32_t se_trng_cp_ratio : 8; /* [ 7: 0], r/w, 0x3 */ + uint32_t se_trng_ht_rct_c : 8; /* [15: 8], r/w, 0x42 */ + uint32_t se_trng_ht_apt_c : 10; /* [25:16], r/w, 0x37a */ + uint32_t se_trng_ht_od_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */ + uint32_t se_trng_rosc_en : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_ctrl_3; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[8]; + + /* 0x40 : se_trng_test_out_0 */ + union { + struct + { + uint32_t se_trng_test_out_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test_out_0; + + /* 0x44 : se_trng_test_out_1 */ + union { + struct + { + uint32_t se_trng_test_out_1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test_out_1; + + /* 0x48 : se_trng_test_out_2 */ + union { + struct + { + uint32_t se_trng_test_out_2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test_out_2; + + /* 0x4c : se_trng_test_out_3 */ + union { + struct + { + uint32_t se_trng_test_out_3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_test_out_3; + + /* 0x50 reserved */ + uint8_t RESERVED0x50[172]; + + /* 0xfc : se_trng_ctrl_prot */ + union { + struct + { + uint32_t se_trng_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t se_trng_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t se_trng_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } se_trng_ctrl_prot; +}; + +typedef volatile struct sec_eng_trng_reg sec_eng_trng_reg_t; + +#define SEC_ENG_TRNG_OFFSET 0x200 + +#endif /* __SEC_ENG_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sf_ctrl_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sf_ctrl_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..45eda74109f41e260bd74bc0bfd3c5efae48141c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/sf_ctrl_reg.h @@ -0,0 +1,2735 @@ +/** + ****************************************************************************** + * @file sf_ctrl_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SF_CTRL_REG_H__ +#define __SF_CTRL_REG_H__ + +#include "bl702.h" + +/* 0x0 : sf_ctrl_0 */ +#define SF_CTRL_0_OFFSET (0x0) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL SF_CTRL_SF_CLK_SF_RX_INV_SEL +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS (2U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)) +#define SF_CTRL_SF_CLK_OUT_GATE_EN SF_CTRL_SF_CLK_OUT_GATE_EN +#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS (3U) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN (1U) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)) +#define SF_CTRL_SF_CLK_OUT_INV_SEL SF_CTRL_SF_CLK_OUT_INV_SEL +#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS (4U) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL SF_CTRL_SF_CLK_SAHB_SRAM_SEL +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS (5U) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_MSK (((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS)) +#define SF_CTRL_SF_IF_READ_DLY_N SF_CTRL_SF_IF_READ_DLY_N +#define SF_CTRL_SF_IF_READ_DLY_N_POS (8U) +#define SF_CTRL_SF_IF_READ_DLY_N_LEN (3U) +#define SF_CTRL_SF_IF_READ_DLY_N_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS) +#define SF_CTRL_SF_IF_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)) +#define SF_CTRL_SF_IF_READ_DLY_EN SF_CTRL_SF_IF_READ_DLY_EN +#define SF_CTRL_SF_IF_READ_DLY_EN_POS (11U) +#define SF_CTRL_SF_IF_READ_DLY_EN_LEN (1U) +#define SF_CTRL_SF_IF_READ_DLY_EN_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS) +#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)) +#define SF_CTRL_SF_IF_INT SF_CTRL_SF_IF_INT +#define SF_CTRL_SF_IF_INT_POS (16U) +#define SF_CTRL_SF_IF_INT_LEN (1U) +#define SF_CTRL_SF_IF_INT_MSK (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS) +#define SF_CTRL_SF_IF_INT_UMSK (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)) +#define SF_CTRL_SF_IF_INT_CLR SF_CTRL_SF_IF_INT_CLR +#define SF_CTRL_SF_IF_INT_CLR_POS (17U) +#define SF_CTRL_SF_IF_INT_CLR_LEN (1U) +#define SF_CTRL_SF_IF_INT_CLR_MSK (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS) +#define SF_CTRL_SF_IF_INT_CLR_UMSK (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)) +#define SF_CTRL_SF_IF_INT_SET SF_CTRL_SF_IF_INT_SET +#define SF_CTRL_SF_IF_INT_SET_POS (18U) +#define SF_CTRL_SF_IF_INT_SET_LEN (1U) +#define SF_CTRL_SF_IF_INT_SET_MSK (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS) +#define SF_CTRL_SF_IF_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)) +#define SF_CTRL_SF_AES_DLY_MODE SF_CTRL_SF_AES_DLY_MODE +#define SF_CTRL_SF_AES_DLY_MODE_POS (19U) +#define SF_CTRL_SF_AES_DLY_MODE_LEN (1U) +#define SF_CTRL_SF_AES_DLY_MODE_MSK (((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS) +#define SF_CTRL_SF_AES_DLY_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS)) +#define SF_CTRL_SF_AES_DOUT_ENDIAN SF_CTRL_SF_AES_DOUT_ENDIAN +#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS (20U) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)) +#define SF_CTRL_SF_AES_CTR_PLUS_EN SF_CTRL_SF_AES_CTR_PLUS_EN +#define SF_CTRL_SF_AES_CTR_PLUS_EN_POS (21U) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_LEN (1U) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_MSK (((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_UMSK (~(((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS)) +#define SF_CTRL_SF_AES_KEY_ENDIAN SF_CTRL_SF_AES_KEY_ENDIAN +#define SF_CTRL_SF_AES_KEY_ENDIAN_POS (22U) +#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS) +#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)) +#define SF_CTRL_SF_AES_IV_ENDIAN SF_CTRL_SF_AES_IV_ENDIAN +#define SF_CTRL_SF_AES_IV_ENDIAN_POS (23U) +#define SF_CTRL_SF_AES_IV_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_IV_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS) +#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)) +#define SF_CTRL_SF_ID SF_CTRL_SF_ID +#define SF_CTRL_SF_ID_POS (24U) +#define SF_CTRL_SF_ID_LEN (8U) +#define SF_CTRL_SF_ID_MSK (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS) +#define SF_CTRL_SF_ID_UMSK (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)) + +/* 0x4 : sf_ctrl_1 */ +#define SF_CTRL_1_OFFSET (0x4) +#define SF_CTRL_SF_IF_SR_PAT_MASK SF_CTRL_SF_IF_SR_PAT_MASK +#define SF_CTRL_SF_IF_SR_PAT_MASK_POS (0U) +#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN (8U) +#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS) +#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)) +#define SF_CTRL_SF_IF_SR_PAT SF_CTRL_SF_IF_SR_PAT +#define SF_CTRL_SF_IF_SR_PAT_POS (8U) +#define SF_CTRL_SF_IF_SR_PAT_LEN (8U) +#define SF_CTRL_SF_IF_SR_PAT_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS) +#define SF_CTRL_SF_IF_SR_PAT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)) +#define SF_CTRL_SF_IF_SR_INT SF_CTRL_SF_IF_SR_INT +#define SF_CTRL_SF_IF_SR_INT_POS (16U) +#define SF_CTRL_SF_IF_SR_INT_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_MSK (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS) +#define SF_CTRL_SF_IF_SR_INT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)) +#define SF_CTRL_SF_IF_SR_INT_EN SF_CTRL_SF_IF_SR_INT_EN +#define SF_CTRL_SF_IF_SR_INT_EN_POS (17U) +#define SF_CTRL_SF_IF_SR_INT_EN_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_EN_MSK (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS) +#define SF_CTRL_SF_IF_SR_INT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)) +#define SF_CTRL_SF_IF_SR_INT_SET SF_CTRL_SF_IF_SR_INT_SET +#define SF_CTRL_SF_IF_SR_INT_SET_POS (18U) +#define SF_CTRL_SF_IF_SR_INT_SET_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_SET_MSK (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS) +#define SF_CTRL_SF_IF_SR_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)) +#define SF_CTRL_SF_IF_0_ACK_LAT SF_CTRL_SF_IF_0_ACK_LAT +#define SF_CTRL_SF_IF_0_ACK_LAT_POS (20U) +#define SF_CTRL_SF_IF_0_ACK_LAT_LEN (3U) +#define SF_CTRL_SF_IF_0_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS) +#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)) +#define SF_CTRL_SF_IF_REG_HOLD SF_CTRL_SF_IF_REG_HOLD +#define SF_CTRL_SF_IF_REG_HOLD_POS (24U) +#define SF_CTRL_SF_IF_REG_HOLD_LEN (1U) +#define SF_CTRL_SF_IF_REG_HOLD_MSK (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS) +#define SF_CTRL_SF_IF_REG_HOLD_UMSK (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)) +#define SF_CTRL_SF_IF_REG_WP SF_CTRL_SF_IF_REG_WP +#define SF_CTRL_SF_IF_REG_WP_POS (25U) +#define SF_CTRL_SF_IF_REG_WP_LEN (1U) +#define SF_CTRL_SF_IF_REG_WP_MSK (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS) +#define SF_CTRL_SF_IF_REG_WP_UMSK (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)) +#define SF_CTRL_SF_AHB2SIF_STOPPED SF_CTRL_SF_AHB2SIF_STOPPED +#define SF_CTRL_SF_AHB2SIF_STOPPED_POS (26U) +#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS) +#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)) +#define SF_CTRL_SF_AHB2SIF_STOP SF_CTRL_SF_AHB2SIF_STOP +#define SF_CTRL_SF_AHB2SIF_STOP_POS (27U) +#define SF_CTRL_SF_AHB2SIF_STOP_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_STOP_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS) +#define SF_CTRL_SF_AHB2SIF_STOP_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)) +#define SF_CTRL_SF_IF_FN_SEL SF_CTRL_SF_IF_FN_SEL +#define SF_CTRL_SF_IF_FN_SEL_POS (28U) +#define SF_CTRL_SF_IF_FN_SEL_LEN (1U) +#define SF_CTRL_SF_IF_FN_SEL_MSK (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS) +#define SF_CTRL_SF_IF_FN_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)) +#define SF_CTRL_SF_IF_EN SF_CTRL_SF_IF_EN +#define SF_CTRL_SF_IF_EN_POS (29U) +#define SF_CTRL_SF_IF_EN_LEN (1U) +#define SF_CTRL_SF_IF_EN_MSK (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS) +#define SF_CTRL_SF_IF_EN_UMSK (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)) +#define SF_CTRL_SF_AHB2SIF_EN SF_CTRL_SF_AHB2SIF_EN +#define SF_CTRL_SF_AHB2SIF_EN_POS (30U) +#define SF_CTRL_SF_AHB2SIF_EN_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_EN_MSK (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS) +#define SF_CTRL_SF_AHB2SIF_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)) +#define SF_CTRL_SF_AHB2SRAM_EN SF_CTRL_SF_AHB2SRAM_EN +#define SF_CTRL_SF_AHB2SRAM_EN_POS (31U) +#define SF_CTRL_SF_AHB2SRAM_EN_LEN (1U) +#define SF_CTRL_SF_AHB2SRAM_EN_MSK (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS) +#define SF_CTRL_SF_AHB2SRAM_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)) + +/* 0x8 : sf_if_sahb_0 */ +#define SF_CTRL_SF_IF_SAHB_0_OFFSET (0x8) +#define SF_CTRL_SF_IF_BUSY SF_CTRL_SF_IF_BUSY +#define SF_CTRL_SF_IF_BUSY_POS (0U) +#define SF_CTRL_SF_IF_BUSY_LEN (1U) +#define SF_CTRL_SF_IF_BUSY_MSK (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS) +#define SF_CTRL_SF_IF_BUSY_UMSK (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)) +#define SF_CTRL_SF_IF_0_TRIG SF_CTRL_SF_IF_0_TRIG +#define SF_CTRL_SF_IF_0_TRIG_POS (1U) +#define SF_CTRL_SF_IF_0_TRIG_LEN (1U) +#define SF_CTRL_SF_IF_0_TRIG_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS) +#define SF_CTRL_SF_IF_0_TRIG_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)) +#define SF_CTRL_SF_IF_0_DAT_BYTE SF_CTRL_SF_IF_0_DAT_BYTE +#define SF_CTRL_SF_IF_0_DAT_BYTE_POS (2U) +#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN (10U) +#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS) +#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)) +#define SF_CTRL_SF_IF_0_DMY_BYTE SF_CTRL_SF_IF_0_DMY_BYTE +#define SF_CTRL_SF_IF_0_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_0_ADR_BYTE SF_CTRL_SF_IF_0_ADR_BYTE +#define SF_CTRL_SF_IF_0_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_0_CMD_BYTE SF_CTRL_SF_IF_0_CMD_BYTE +#define SF_CTRL_SF_IF_0_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_0_DAT_RW SF_CTRL_SF_IF_0_DAT_RW +#define SF_CTRL_SF_IF_0_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_0_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_0_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS) +#define SF_CTRL_SF_IF_0_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)) +#define SF_CTRL_SF_IF_0_DAT_EN SF_CTRL_SF_IF_0_DAT_EN +#define SF_CTRL_SF_IF_0_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_0_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS) +#define SF_CTRL_SF_IF_0_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)) +#define SF_CTRL_SF_IF_0_DMY_EN SF_CTRL_SF_IF_0_DMY_EN +#define SF_CTRL_SF_IF_0_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_0_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS) +#define SF_CTRL_SF_IF_0_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)) +#define SF_CTRL_SF_IF_0_ADR_EN SF_CTRL_SF_IF_0_ADR_EN +#define SF_CTRL_SF_IF_0_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_0_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS) +#define SF_CTRL_SF_IF_0_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)) +#define SF_CTRL_SF_IF_0_CMD_EN SF_CTRL_SF_IF_0_CMD_EN +#define SF_CTRL_SF_IF_0_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_0_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS) +#define SF_CTRL_SF_IF_0_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)) +#define SF_CTRL_SF_IF_0_SPI_MODE SF_CTRL_SF_IF_0_SPI_MODE +#define SF_CTRL_SF_IF_0_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_0_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_0_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS) +#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN SF_CTRL_SF_IF_0_QPI_MODE_EN +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)) + +/* 0xC : sf_if_sahb_1 */ +#define SF_CTRL_SF_IF_SAHB_1_OFFSET (0xC) +#define SF_CTRL_SF_IF_0_CMD_BUF_0 SF_CTRL_SF_IF_0_CMD_BUF_0 +#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)) + +/* 0x10 : sf_if_sahb_2 */ +#define SF_CTRL_SF_IF_SAHB_2_OFFSET (0x10) +#define SF_CTRL_SF_IF_0_CMD_BUF_1 SF_CTRL_SF_IF_0_CMD_BUF_1 +#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)) + +/* 0x14 : sf_if_iahb_0 */ +#define SF_CTRL_SF_IF_IAHB_0_OFFSET (0x14) +#define SF_CTRL_SF_IF_1_DMY_BYTE SF_CTRL_SF_IF_1_DMY_BYTE +#define SF_CTRL_SF_IF_1_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_1_ADR_BYTE SF_CTRL_SF_IF_1_ADR_BYTE +#define SF_CTRL_SF_IF_1_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_1_CMD_BYTE SF_CTRL_SF_IF_1_CMD_BYTE +#define SF_CTRL_SF_IF_1_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_1_DAT_RW SF_CTRL_SF_IF_1_DAT_RW +#define SF_CTRL_SF_IF_1_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_1_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_1_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS) +#define SF_CTRL_SF_IF_1_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)) +#define SF_CTRL_SF_IF_1_DAT_EN SF_CTRL_SF_IF_1_DAT_EN +#define SF_CTRL_SF_IF_1_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_1_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS) +#define SF_CTRL_SF_IF_1_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)) +#define SF_CTRL_SF_IF_1_DMY_EN SF_CTRL_SF_IF_1_DMY_EN +#define SF_CTRL_SF_IF_1_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_1_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS) +#define SF_CTRL_SF_IF_1_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)) +#define SF_CTRL_SF_IF_1_ADR_EN SF_CTRL_SF_IF_1_ADR_EN +#define SF_CTRL_SF_IF_1_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_1_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS) +#define SF_CTRL_SF_IF_1_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)) +#define SF_CTRL_SF_IF_1_CMD_EN SF_CTRL_SF_IF_1_CMD_EN +#define SF_CTRL_SF_IF_1_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_1_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS) +#define SF_CTRL_SF_IF_1_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)) +#define SF_CTRL_SF_IF_1_SPI_MODE SF_CTRL_SF_IF_1_SPI_MODE +#define SF_CTRL_SF_IF_1_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_1_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_1_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS) +#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN SF_CTRL_SF_IF_1_QPI_MODE_EN +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)) + +/* 0x18 : sf_if_iahb_1 */ +#define SF_CTRL_SF_IF_IAHB_1_OFFSET (0x18) +#define SF_CTRL_SF_IF_1_CMD_BUF_0 SF_CTRL_SF_IF_1_CMD_BUF_0 +#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)) + +/* 0x1C : sf_if_iahb_2 */ +#define SF_CTRL_SF_IF_IAHB_2_OFFSET (0x1C) +#define SF_CTRL_SF_IF_1_CMD_BUF_1 SF_CTRL_SF_IF_1_CMD_BUF_1 +#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)) + +/* 0x20 : sf_if_status_0 */ +#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20) +#define SF_CTRL_SF_IF_STATUS_0 SF_CTRL_SF_IF_STATUS_0 +#define SF_CTRL_SF_IF_STATUS_0_POS (0U) +#define SF_CTRL_SF_IF_STATUS_0_LEN (32U) +#define SF_CTRL_SF_IF_STATUS_0_MSK (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS) +#define SF_CTRL_SF_IF_STATUS_0_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)) + +/* 0x24 : sf_if_status_1 */ +#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24) +#define SF_CTRL_SF_IF_STATUS_1 SF_CTRL_SF_IF_STATUS_1 +#define SF_CTRL_SF_IF_STATUS_1_POS (0U) +#define SF_CTRL_SF_IF_STATUS_1_LEN (32U) +#define SF_CTRL_SF_IF_STATUS_1_MSK (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS) +#define SF_CTRL_SF_IF_STATUS_1_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)) + +/* 0x28 : sf_aes */ +#define SF_CTRL_SF_AES_OFFSET (0x28) +#define SF_CTRL_SF_AES_EN SF_CTRL_SF_AES_EN +#define SF_CTRL_SF_AES_EN_POS (0U) +#define SF_CTRL_SF_AES_EN_LEN (1U) +#define SF_CTRL_SF_AES_EN_MSK (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS) +#define SF_CTRL_SF_AES_EN_UMSK (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)) +#define SF_CTRL_SF_AES_MODE SF_CTRL_SF_AES_MODE +#define SF_CTRL_SF_AES_MODE_POS (1U) +#define SF_CTRL_SF_AES_MODE_LEN (2U) +#define SF_CTRL_SF_AES_MODE_MSK (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS) +#define SF_CTRL_SF_AES_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)) +#define SF_CTRL_SF_AES_PREF_TRIG SF_CTRL_SF_AES_PREF_TRIG +#define SF_CTRL_SF_AES_PREF_TRIG_POS (3U) +#define SF_CTRL_SF_AES_PREF_TRIG_LEN (1U) +#define SF_CTRL_SF_AES_PREF_TRIG_MSK (((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS) +#define SF_CTRL_SF_AES_PREF_TRIG_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS)) +#define SF_CTRL_SF_AES_PREF_BUSY SF_CTRL_SF_AES_PREF_BUSY +#define SF_CTRL_SF_AES_PREF_BUSY_POS (4U) +#define SF_CTRL_SF_AES_PREF_BUSY_LEN (1U) +#define SF_CTRL_SF_AES_PREF_BUSY_MSK (((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS) +#define SF_CTRL_SF_AES_PREF_BUSY_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS)) +#define SF_CTRL_SF_AES_STATUS SF_CTRL_SF_AES_STATUS +#define SF_CTRL_SF_AES_STATUS_POS (5U) +#define SF_CTRL_SF_AES_STATUS_LEN (27U) +#define SF_CTRL_SF_AES_STATUS_MSK (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS) +#define SF_CTRL_SF_AES_STATUS_UMSK (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)) + +/* 0x2C : sf_ahb2sif_status */ +#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C) +#define SF_CTRL_SF_AHB2SIF_STATUS SF_CTRL_SF_AHB2SIF_STATUS +#define SF_CTRL_SF_AHB2SIF_STATUS_POS (0U) +#define SF_CTRL_SF_AHB2SIF_STATUS_LEN (32U) +#define SF_CTRL_SF_AHB2SIF_STATUS_MSK (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS) +#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)) + +/* 0x30 : sf_if_io_dly_0 */ +#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET (0x30) +#define SF_CTRL_SF_CS_DLY_SEL SF_CTRL_SF_CS_DLY_SEL +#define SF_CTRL_SF_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS) +#define SF_CTRL_SF_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)) +#define SF_CTRL_SF_CS2_DLY_SEL SF_CTRL_SF_CS2_DLY_SEL +#define SF_CTRL_SF_CS2_DLY_SEL_POS (2U) +#define SF_CTRL_SF_CS2_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS) +#define SF_CTRL_SF_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS)) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL SF_CTRL_SF_CLK_OUT_DLY_SEL +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_OE_DLY_SEL SF_CTRL_SF_DQS_OE_DLY_SEL +#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_DI_DLY_SEL SF_CTRL_SF_DQS_DI_DLY_SEL +#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_DO_DLY_SEL SF_CTRL_SF_DQS_DO_DLY_SEL +#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)) + +/* 0x34 : sf_if_io_dly_1 */ +#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET (0x34) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL SF_CTRL_SF_IO_0_OE_DLY_SEL +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL SF_CTRL_SF_IO_0_DI_DLY_SEL +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL SF_CTRL_SF_IO_0_DO_DLY_SEL +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)) + +/* 0x38 : sf_if_io_dly_2 */ +#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET (0x38) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL SF_CTRL_SF_IO_1_OE_DLY_SEL +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL SF_CTRL_SF_IO_1_DI_DLY_SEL +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL SF_CTRL_SF_IO_1_DO_DLY_SEL +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)) + +/* 0x3C : sf_if_io_dly_3 */ +#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET (0x3C) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL SF_CTRL_SF_IO_2_OE_DLY_SEL +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL SF_CTRL_SF_IO_2_DI_DLY_SEL +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL SF_CTRL_SF_IO_2_DO_DLY_SEL +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)) + +/* 0x40 : sf_if_io_dly_4 */ +#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET (0x40) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL SF_CTRL_SF_IO_3_OE_DLY_SEL +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL SF_CTRL_SF_IO_3_DI_DLY_SEL +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL SF_CTRL_SF_IO_3_DO_DLY_SEL +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)) + +/* 0x44 : sf_reserved */ +#define SF_CTRL_SF_RESERVED_OFFSET (0x44) +#define SF_CTRL_SF_RESERVED SF_CTRL_SF_RESERVED +#define SF_CTRL_SF_RESERVED_POS (0U) +#define SF_CTRL_SF_RESERVED_LEN (32U) +#define SF_CTRL_SF_RESERVED_MSK (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS) +#define SF_CTRL_SF_RESERVED_UMSK (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)) + +/* 0x48 : sf2_if_io_dly_0 */ +#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET (0x48) +#define SF_CTRL_SF2_CS_DLY_SEL SF_CTRL_SF2_CS_DLY_SEL +#define SF_CTRL_SF2_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS) +#define SF_CTRL_SF2_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)) +#define SF_CTRL_SF2_CS2_DLY_SEL SF_CTRL_SF2_CS2_DLY_SEL +#define SF_CTRL_SF2_CS2_DLY_SEL_POS (2U) +#define SF_CTRL_SF2_CS2_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS) +#define SF_CTRL_SF2_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS)) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL SF_CTRL_SF2_CLK_OUT_DLY_SEL +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL SF_CTRL_SF2_DQS_OE_DLY_SEL +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL SF_CTRL_SF2_DQS_DI_DLY_SEL +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL SF_CTRL_SF2_DQS_DO_DLY_SEL +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)) + +/* 0x4C : sf2_if_io_dly_1 */ +#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET (0x4C) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL SF_CTRL_SF2_IO_0_OE_DLY_SEL +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL SF_CTRL_SF2_IO_0_DI_DLY_SEL +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL SF_CTRL_SF2_IO_0_DO_DLY_SEL +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)) + +/* 0x50 : sf2_if_io_dly_2 */ +#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET (0x50) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL SF_CTRL_SF2_IO_1_OE_DLY_SEL +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL SF_CTRL_SF2_IO_1_DI_DLY_SEL +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL SF_CTRL_SF2_IO_1_DO_DLY_SEL +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)) + +/* 0x54 : sf2_if_io_dly_3 */ +#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET (0x54) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL SF_CTRL_SF2_IO_2_OE_DLY_SEL +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL SF_CTRL_SF2_IO_2_DI_DLY_SEL +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL SF_CTRL_SF2_IO_2_DO_DLY_SEL +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)) + +/* 0x58 : sf2_if_io_dly_4 */ +#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET (0x58) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL SF_CTRL_SF2_IO_3_OE_DLY_SEL +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL SF_CTRL_SF2_IO_3_DI_DLY_SEL +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL SF_CTRL_SF2_IO_3_DO_DLY_SEL +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)) + +/* 0x5C : sf3_if_io_dly_0 */ +#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET (0x5C) +#define SF_CTRL_SF3_CS_DLY_SEL SF_CTRL_SF3_CS_DLY_SEL +#define SF_CTRL_SF3_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS) +#define SF_CTRL_SF3_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)) +#define SF_CTRL_SF3_CS2_DLY_SEL SF_CTRL_SF3_CS2_DLY_SEL +#define SF_CTRL_SF3_CS2_DLY_SEL_POS (2U) +#define SF_CTRL_SF3_CS2_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS) +#define SF_CTRL_SF3_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS)) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL SF_CTRL_SF3_CLK_OUT_DLY_SEL +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL SF_CTRL_SF3_DQS_OE_DLY_SEL +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL SF_CTRL_SF3_DQS_DI_DLY_SEL +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL SF_CTRL_SF3_DQS_DO_DLY_SEL +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)) + +/* 0x60 : sf3_if_io_dly_1 */ +#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET (0x60) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL SF_CTRL_SF3_IO_0_OE_DLY_SEL +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL SF_CTRL_SF3_IO_0_DI_DLY_SEL +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL SF_CTRL_SF3_IO_0_DO_DLY_SEL +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)) + +/* 0x64 : sf3_if_io_dly_2 */ +#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET (0x64) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL SF_CTRL_SF3_IO_1_OE_DLY_SEL +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL SF_CTRL_SF3_IO_1_DI_DLY_SEL +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL SF_CTRL_SF3_IO_1_DO_DLY_SEL +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)) + +/* 0x68 : sf3_if_io_dly_3 */ +#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET (0x68) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL SF_CTRL_SF3_IO_2_OE_DLY_SEL +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL SF_CTRL_SF3_IO_2_DI_DLY_SEL +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL SF_CTRL_SF3_IO_2_DO_DLY_SEL +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)) + +/* 0x6C : sf3_if_io_dly_4 */ +#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET (0x6C) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL SF_CTRL_SF3_IO_3_OE_DLY_SEL +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL SF_CTRL_SF3_IO_3_DI_DLY_SEL +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL SF_CTRL_SF3_IO_3_DO_DLY_SEL +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)) + +/* 0x70 : sf_ctrl_2 */ +#define SF_CTRL_2_OFFSET (0x70) +#define SF_CTRL_SF_IF_PAD_SEL SF_CTRL_SF_IF_PAD_SEL +#define SF_CTRL_SF_IF_PAD_SEL_POS (0U) +#define SF_CTRL_SF_IF_PAD_SEL_LEN (2U) +#define SF_CTRL_SF_IF_PAD_SEL_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS) +#define SF_CTRL_SF_IF_PAD_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK SF_CTRL_SF_IF_PAD_SEL_LOCK +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS (3U) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN (1U) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)) +#define SF_CTRL_SF_IF_DTR_EN SF_CTRL_SF_IF_DTR_EN +#define SF_CTRL_SF_IF_DTR_EN_POS (4U) +#define SF_CTRL_SF_IF_DTR_EN_LEN (1U) +#define SF_CTRL_SF_IF_DTR_EN_MSK (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS) +#define SF_CTRL_SF_IF_DTR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)) +#define SF_CTRL_SF_IF_DQS_EN SF_CTRL_SF_IF_DQS_EN +#define SF_CTRL_SF_IF_DQS_EN_POS (5U) +#define SF_CTRL_SF_IF_DQS_EN_LEN (1U) +#define SF_CTRL_SF_IF_DQS_EN_MSK (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS) +#define SF_CTRL_SF_IF_DQS_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)) +#define SF_CTRL_SF_IF_BK_SWAP SF_CTRL_SF_IF_BK_SWAP +#define SF_CTRL_SF_IF_BK_SWAP_POS (28U) +#define SF_CTRL_SF_IF_BK_SWAP_LEN (1U) +#define SF_CTRL_SF_IF_BK_SWAP_MSK (((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS) +#define SF_CTRL_SF_IF_BK_SWAP_UMSK (~(((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS)) +#define SF_CTRL_SF_IF_BK2_MODE SF_CTRL_SF_IF_BK2_MODE +#define SF_CTRL_SF_IF_BK2_MODE_POS (29U) +#define SF_CTRL_SF_IF_BK2_MODE_LEN (1U) +#define SF_CTRL_SF_IF_BK2_MODE_MSK (((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS) +#define SF_CTRL_SF_IF_BK2_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS)) +#define SF_CTRL_SF_IF_BK2_EN SF_CTRL_SF_IF_BK2_EN +#define SF_CTRL_SF_IF_BK2_EN_POS (30U) +#define SF_CTRL_SF_IF_BK2_EN_LEN (1U) +#define SF_CTRL_SF_IF_BK2_EN_MSK (((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS) +#define SF_CTRL_SF_IF_BK2_EN_UMSK (~(((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS)) +#define SF_CTRL_SF_IF_0_BK_SEL SF_CTRL_SF_IF_0_BK_SEL +#define SF_CTRL_SF_IF_0_BK_SEL_POS (31U) +#define SF_CTRL_SF_IF_0_BK_SEL_LEN (1U) +#define SF_CTRL_SF_IF_0_BK_SEL_MSK (((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS) +#define SF_CTRL_SF_IF_0_BK_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS)) + +/* 0x74 : sf_ctrl_3 */ +#define SF_CTRL_3_OFFSET (0x74) +#define SF_CTRL_SF_CMDS_WRAP_LEN SF_CTRL_SF_CMDS_WRAP_LEN +#define SF_CTRL_SF_CMDS_WRAP_LEN_POS (0U) +#define SF_CTRL_SF_CMDS_WRAP_LEN_LEN (4U) +#define SF_CTRL_SF_CMDS_WRAP_LEN_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS) +#define SF_CTRL_SF_CMDS_WRAP_LEN_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS)) +#define SF_CTRL_SF_CMDS_EN SF_CTRL_SF_CMDS_EN +#define SF_CTRL_SF_CMDS_EN_POS (4U) +#define SF_CTRL_SF_CMDS_EN_LEN (1U) +#define SF_CTRL_SF_CMDS_EN_MSK (((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS) +#define SF_CTRL_SF_CMDS_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS)) +#define SF_CTRL_SF_CMDS_BT_DLY SF_CTRL_SF_CMDS_BT_DLY +#define SF_CTRL_SF_CMDS_BT_DLY_POS (5U) +#define SF_CTRL_SF_CMDS_BT_DLY_LEN (3U) +#define SF_CTRL_SF_CMDS_BT_DLY_MSK (((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS) +#define SF_CTRL_SF_CMDS_BT_DLY_UMSK (~(((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS)) +#define SF_CTRL_SF_CMDS_BT_EN SF_CTRL_SF_CMDS_BT_EN +#define SF_CTRL_SF_CMDS_BT_EN_POS (8U) +#define SF_CTRL_SF_CMDS_BT_EN_LEN (1U) +#define SF_CTRL_SF_CMDS_BT_EN_MSK (((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS) +#define SF_CTRL_SF_CMDS_BT_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS)) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI SF_CTRL_SF_CMDS_WRAP_Q_INI +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_POS (9U) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN (1U) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS)) +#define SF_CTRL_SF_CMDS_WRAP_MODE SF_CTRL_SF_CMDS_WRAP_MODE +#define SF_CTRL_SF_CMDS_WRAP_MODE_POS (10U) +#define SF_CTRL_SF_CMDS_WRAP_MODE_LEN (1U) +#define SF_CTRL_SF_CMDS_WRAP_MODE_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS) +#define SF_CTRL_SF_CMDS_WRAP_MODE_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS)) +#define SF_CTRL_SF_CMDS_WRAP_Q SF_CTRL_SF_CMDS_WRAP_Q +#define SF_CTRL_SF_CMDS_WRAP_Q_POS (11U) +#define SF_CTRL_SF_CMDS_WRAP_Q_LEN (1U) +#define SF_CTRL_SF_CMDS_WRAP_Q_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS) +#define SF_CTRL_SF_CMDS_WRAP_Q_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS)) +#define SF_CTRL_SF_IF_1_ACK_LAT SF_CTRL_SF_IF_1_ACK_LAT +#define SF_CTRL_SF_IF_1_ACK_LAT_POS (29U) +#define SF_CTRL_SF_IF_1_ACK_LAT_LEN (3U) +#define SF_CTRL_SF_IF_1_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS) +#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)) + +/* 0x78 : sf_if_iahb_3 */ +#define SF_CTRL_SF_IF_IAHB_3_OFFSET (0x78) +#define SF_CTRL_SF_IF_2_DMY_BYTE SF_CTRL_SF_IF_2_DMY_BYTE +#define SF_CTRL_SF_IF_2_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_2_ADR_BYTE SF_CTRL_SF_IF_2_ADR_BYTE +#define SF_CTRL_SF_IF_2_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_2_CMD_BYTE SF_CTRL_SF_IF_2_CMD_BYTE +#define SF_CTRL_SF_IF_2_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_2_DAT_RW SF_CTRL_SF_IF_2_DAT_RW +#define SF_CTRL_SF_IF_2_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_2_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_2_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS) +#define SF_CTRL_SF_IF_2_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)) +#define SF_CTRL_SF_IF_2_DAT_EN SF_CTRL_SF_IF_2_DAT_EN +#define SF_CTRL_SF_IF_2_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_2_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS) +#define SF_CTRL_SF_IF_2_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)) +#define SF_CTRL_SF_IF_2_DMY_EN SF_CTRL_SF_IF_2_DMY_EN +#define SF_CTRL_SF_IF_2_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_2_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS) +#define SF_CTRL_SF_IF_2_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)) +#define SF_CTRL_SF_IF_2_ADR_EN SF_CTRL_SF_IF_2_ADR_EN +#define SF_CTRL_SF_IF_2_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_2_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS) +#define SF_CTRL_SF_IF_2_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)) +#define SF_CTRL_SF_IF_2_CMD_EN SF_CTRL_SF_IF_2_CMD_EN +#define SF_CTRL_SF_IF_2_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_2_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS) +#define SF_CTRL_SF_IF_2_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)) +#define SF_CTRL_SF_IF_2_SPI_MODE SF_CTRL_SF_IF_2_SPI_MODE +#define SF_CTRL_SF_IF_2_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_2_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_2_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS) +#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN SF_CTRL_SF_IF_2_QPI_MODE_EN +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)) + +/* 0x7C : sf_if_iahb_4 */ +#define SF_CTRL_SF_IF_IAHB_4_OFFSET (0x7C) +#define SF_CTRL_SF_IF_2_CMD_BUF_0 SF_CTRL_SF_IF_2_CMD_BUF_0 +#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)) + +/* 0x80 : sf_if_iahb_5 */ +#define SF_CTRL_SF_IF_IAHB_5_OFFSET (0x80) +#define SF_CTRL_SF_IF_2_CMD_BUF_1 SF_CTRL_SF_IF_2_CMD_BUF_1 +#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)) + +/* 0x84 : sf_if_iahb_6 */ +#define SF_CTRL_SF_IF_IAHB_6_OFFSET (0x84) +#define SF_CTRL_SF_IF_3_ADR_BYTE SF_CTRL_SF_IF_3_ADR_BYTE +#define SF_CTRL_SF_IF_3_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_3_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_3_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_3_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_3_CMD_BYTE SF_CTRL_SF_IF_3_CMD_BYTE +#define SF_CTRL_SF_IF_3_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_3_ADR_EN SF_CTRL_SF_IF_3_ADR_EN +#define SF_CTRL_SF_IF_3_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_3_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_3_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS) +#define SF_CTRL_SF_IF_3_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS)) +#define SF_CTRL_SF_IF_3_CMD_EN SF_CTRL_SF_IF_3_CMD_EN +#define SF_CTRL_SF_IF_3_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_3_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_3_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS) +#define SF_CTRL_SF_IF_3_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS)) +#define SF_CTRL_SF_IF_3_SPI_MODE SF_CTRL_SF_IF_3_SPI_MODE +#define SF_CTRL_SF_IF_3_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_3_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_3_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS) +#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN SF_CTRL_SF_IF_3_QPI_MODE_EN +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)) + +/* 0x88 : sf_if_iahb_7 */ +#define SF_CTRL_SF_IF_IAHB_7_OFFSET (0x88) +#define SF_CTRL_SF_IF_3_CMD_BUF_0 SF_CTRL_SF_IF_3_CMD_BUF_0 +#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)) + +/* 0x8C : sf_if_iahb_8 */ +#define SF_CTRL_SF_IF_IAHB_8_OFFSET (0x8C) +#define SF_CTRL_SF_IF_3_CMD_BUF_1 SF_CTRL_SF_IF_3_CMD_BUF_1 +#define SF_CTRL_SF_IF_3_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_3_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_3_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_3_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS)) + +/* 0x90 : sf_if_iahb_9 */ +#define SF_CTRL_SF_IF_IAHB_9_OFFSET (0x90) +#define SF_CTRL_SF_IF_4_DMY_BYTE SF_CTRL_SF_IF_4_DMY_BYTE +#define SF_CTRL_SF_IF_4_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_4_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_4_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_4_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_4_ADR_BYTE SF_CTRL_SF_IF_4_ADR_BYTE +#define SF_CTRL_SF_IF_4_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_4_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_4_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_4_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_4_CMD_BYTE SF_CTRL_SF_IF_4_CMD_BYTE +#define SF_CTRL_SF_IF_4_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_4_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_4_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_4_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_4_DAT_RW SF_CTRL_SF_IF_4_DAT_RW +#define SF_CTRL_SF_IF_4_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_4_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_4_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS) +#define SF_CTRL_SF_IF_4_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS)) +#define SF_CTRL_SF_IF_4_DAT_EN SF_CTRL_SF_IF_4_DAT_EN +#define SF_CTRL_SF_IF_4_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_4_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_4_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS) +#define SF_CTRL_SF_IF_4_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS)) +#define SF_CTRL_SF_IF_4_DMY_EN SF_CTRL_SF_IF_4_DMY_EN +#define SF_CTRL_SF_IF_4_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_4_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_4_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS) +#define SF_CTRL_SF_IF_4_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS)) +#define SF_CTRL_SF_IF_4_ADR_EN SF_CTRL_SF_IF_4_ADR_EN +#define SF_CTRL_SF_IF_4_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_4_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_4_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS) +#define SF_CTRL_SF_IF_4_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS)) +#define SF_CTRL_SF_IF_4_CMD_EN SF_CTRL_SF_IF_4_CMD_EN +#define SF_CTRL_SF_IF_4_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_4_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_4_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS) +#define SF_CTRL_SF_IF_4_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS)) +#define SF_CTRL_SF_IF_4_SPI_MODE SF_CTRL_SF_IF_4_SPI_MODE +#define SF_CTRL_SF_IF_4_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_4_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_4_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS) +#define SF_CTRL_SF_IF_4_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_4_QPI_MODE_EN SF_CTRL_SF_IF_4_QPI_MODE_EN +#define SF_CTRL_SF_IF_4_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_4_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_4_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS)) + +/* 0x94 : sf_if_iahb_10 */ +#define SF_CTRL_SF_IF_IAHB_10_OFFSET (0x94) +#define SF_CTRL_SF_IF_4_CMD_BUF_0 SF_CTRL_SF_IF_4_CMD_BUF_0 +#define SF_CTRL_SF_IF_4_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_4_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_4_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_4_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS)) + +/* 0x98 : sf_if_iahb_11 */ +#define SF_CTRL_SF_IF_IAHB_11_OFFSET (0x98) +#define SF_CTRL_SF_IF_4_CMD_BUF_1 SF_CTRL_SF_IF_4_CMD_BUF_1 +#define SF_CTRL_SF_IF_4_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_4_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_4_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_4_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS)) + +/* 0x9C : sf_if_iahb_12 */ +#define SF_CTRL_SF_IF_IAHB_12_OFFSET (0x9C) +#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL SF_CTRL_SF2_CLK_SF_RX_INV_SEL +#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS (2U) +#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN (1U) +#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_MSK (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS) +#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS)) +#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC SF_CTRL_SF2_CLK_SF_RX_INV_SRC +#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS (3U) +#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN (1U) +#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_MSK (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS) +#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS)) +#define SF_CTRL_SF2_CLK_OUT_INV_SEL SF_CTRL_SF2_CLK_OUT_INV_SEL +#define SF_CTRL_SF2_CLK_OUT_INV_SEL_POS (4U) +#define SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN (1U) +#define SF_CTRL_SF2_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS) +#define SF_CTRL_SF2_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS)) +#define SF_CTRL_SF3_CLK_OUT_INV_SEL SF_CTRL_SF3_CLK_OUT_INV_SEL +#define SF_CTRL_SF3_CLK_OUT_INV_SEL_POS (5U) +#define SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN (1U) +#define SF_CTRL_SF3_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS) +#define SF_CTRL_SF3_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS)) +#define SF_CTRL_SF2_IF_READ_DLY_N SF_CTRL_SF2_IF_READ_DLY_N +#define SF_CTRL_SF2_IF_READ_DLY_N_POS (8U) +#define SF_CTRL_SF2_IF_READ_DLY_N_LEN (3U) +#define SF_CTRL_SF2_IF_READ_DLY_N_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS) +#define SF_CTRL_SF2_IF_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS)) +#define SF_CTRL_SF2_IF_READ_DLY_EN SF_CTRL_SF2_IF_READ_DLY_EN +#define SF_CTRL_SF2_IF_READ_DLY_EN_POS (11U) +#define SF_CTRL_SF2_IF_READ_DLY_EN_LEN (1U) +#define SF_CTRL_SF2_IF_READ_DLY_EN_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS) +#define SF_CTRL_SF2_IF_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS)) +#define SF_CTRL_SF2_IF_READ_DLY_SRC SF_CTRL_SF2_IF_READ_DLY_SRC +#define SF_CTRL_SF2_IF_READ_DLY_SRC_POS (12U) +#define SF_CTRL_SF2_IF_READ_DLY_SRC_LEN (1U) +#define SF_CTRL_SF2_IF_READ_DLY_SRC_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS) +#define SF_CTRL_SF2_IF_READ_DLY_SRC_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS)) + +/* 0x100 : sf_ctrl_prot_en_rd */ +#define SF_CTRL_PROT_EN_RD_OFFSET (0x100) +#define SF_CTRL_PROT_EN_RD SF_CTRL_PROT_EN_RD +#define SF_CTRL_PROT_EN_RD_POS (0U) +#define SF_CTRL_PROT_EN_RD_LEN (1U) +#define SF_CTRL_PROT_EN_RD_MSK (((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS) +#define SF_CTRL_PROT_EN_RD_UMSK (~(((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS)) +#define SF_CTRL_ID0_EN_RD SF_CTRL_ID0_EN_RD +#define SF_CTRL_ID0_EN_RD_POS (1U) +#define SF_CTRL_ID0_EN_RD_LEN (1U) +#define SF_CTRL_ID0_EN_RD_MSK (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS) +#define SF_CTRL_ID0_EN_RD_UMSK (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)) +#define SF_CTRL_ID1_EN_RD SF_CTRL_ID1_EN_RD +#define SF_CTRL_ID1_EN_RD_POS (2U) +#define SF_CTRL_ID1_EN_RD_LEN (1U) +#define SF_CTRL_ID1_EN_RD_MSK (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS) +#define SF_CTRL_ID1_EN_RD_UMSK (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK SF_CTRL_SF_IF_0_TRIG_WR_LOCK +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS (30U) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN (1U) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)) +#define SF_CTRL_SF_DBG_DIS SF_CTRL_SF_DBG_DIS +#define SF_CTRL_SF_DBG_DIS_POS (31U) +#define SF_CTRL_SF_DBG_DIS_LEN (1U) +#define SF_CTRL_SF_DBG_DIS_MSK (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS) +#define SF_CTRL_SF_DBG_DIS_UMSK (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)) + +/* 0x104 : sf_ctrl_prot_en */ +#define SF_CTRL_PROT_EN_OFFSET (0x104) +#define SF_CTRL_PROT_EN SF_CTRL_PROT_EN +#define SF_CTRL_PROT_EN_POS (0U) +#define SF_CTRL_PROT_EN_LEN (1U) +#define SF_CTRL_PROT_EN_MSK (((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS) +#define SF_CTRL_PROT_EN_UMSK (~(((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS)) +#define SF_CTRL_ID0_EN SF_CTRL_ID0_EN +#define SF_CTRL_ID0_EN_POS (1U) +#define SF_CTRL_ID0_EN_LEN (1U) +#define SF_CTRL_ID0_EN_MSK (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS) +#define SF_CTRL_ID0_EN_UMSK (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)) +#define SF_CTRL_ID1_EN SF_CTRL_ID1_EN +#define SF_CTRL_ID1_EN_POS (2U) +#define SF_CTRL_ID1_EN_LEN (1U) +#define SF_CTRL_ID1_EN_MSK (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS) +#define SF_CTRL_ID1_EN_UMSK (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)) + +/* 0x200 : sf_aes_key_r0_0 */ +#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200) +#define SF_CTRL_SF_AES_KEY_R0_0 SF_CTRL_SF_AES_KEY_R0_0 +#define SF_CTRL_SF_AES_KEY_R0_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS) +#define SF_CTRL_SF_AES_KEY_R0_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)) + +/* 0x204 : sf_aes_key_r0_1 */ +#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204) +#define SF_CTRL_SF_AES_KEY_R0_1 SF_CTRL_SF_AES_KEY_R0_1 +#define SF_CTRL_SF_AES_KEY_R0_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS) +#define SF_CTRL_SF_AES_KEY_R0_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)) + +/* 0x208 : sf_aes_key_r0_2 */ +#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208) +#define SF_CTRL_SF_AES_KEY_R0_2 SF_CTRL_SF_AES_KEY_R0_2 +#define SF_CTRL_SF_AES_KEY_R0_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS) +#define SF_CTRL_SF_AES_KEY_R0_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)) + +/* 0x20C : sf_aes_key_r0_3 */ +#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C) +#define SF_CTRL_SF_AES_KEY_R0_3 SF_CTRL_SF_AES_KEY_R0_3 +#define SF_CTRL_SF_AES_KEY_R0_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS) +#define SF_CTRL_SF_AES_KEY_R0_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)) + +/* 0x210 : sf_aes_key_r0_4 */ +#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210) +#define SF_CTRL_SF_AES_KEY_R0_4 SF_CTRL_SF_AES_KEY_R0_4 +#define SF_CTRL_SF_AES_KEY_R0_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS) +#define SF_CTRL_SF_AES_KEY_R0_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)) + +/* 0x214 : sf_aes_key_r0_5 */ +#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214) +#define SF_CTRL_SF_AES_KEY_R0_5 SF_CTRL_SF_AES_KEY_R0_5 +#define SF_CTRL_SF_AES_KEY_R0_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS) +#define SF_CTRL_SF_AES_KEY_R0_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)) + +/* 0x218 : sf_aes_key_r0_6 */ +#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218) +#define SF_CTRL_SF_AES_KEY_R0_6 SF_CTRL_SF_AES_KEY_R0_6 +#define SF_CTRL_SF_AES_KEY_R0_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS) +#define SF_CTRL_SF_AES_KEY_R0_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)) + +/* 0x21C : sf_aes_key_r0_7 */ +#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C) +#define SF_CTRL_SF_AES_KEY_R0_7 SF_CTRL_SF_AES_KEY_R0_7 +#define SF_CTRL_SF_AES_KEY_R0_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS) +#define SF_CTRL_SF_AES_KEY_R0_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)) + +/* 0x220 : sf_aes_iv_r0_w0 */ +#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220) +#define SF_CTRL_SF_AES_IV_R0_W0 SF_CTRL_SF_AES_IV_R0_W0 +#define SF_CTRL_SF_AES_IV_R0_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS) +#define SF_CTRL_SF_AES_IV_R0_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)) + +/* 0x224 : sf_aes_iv_r0_w1 */ +#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224) +#define SF_CTRL_SF_AES_IV_R0_W1 SF_CTRL_SF_AES_IV_R0_W1 +#define SF_CTRL_SF_AES_IV_R0_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS) +#define SF_CTRL_SF_AES_IV_R0_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)) + +/* 0x228 : sf_aes_iv_r0_w2 */ +#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228) +#define SF_CTRL_SF_AES_IV_R0_W2 SF_CTRL_SF_AES_IV_R0_W2 +#define SF_CTRL_SF_AES_IV_R0_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS) +#define SF_CTRL_SF_AES_IV_R0_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)) + +/* 0x22C : sf_aes_iv_r0_w3 */ +#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C) +#define SF_CTRL_SF_AES_IV_R0_W3 SF_CTRL_SF_AES_IV_R0_W3 +#define SF_CTRL_SF_AES_IV_R0_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS) +#define SF_CTRL_SF_AES_IV_R0_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)) + +/* 0x230 : sf_aes_cfg_r0 */ +#define SF_CTRL_SF_AES_CFG_R0_OFFSET (0x230) +#define SF_CTRL_SF_AES_REGION_R0_END SF_CTRL_SF_AES_REGION_R0_END +#define SF_CTRL_SF_AES_REGION_R0_END_POS (0U) +#define SF_CTRL_SF_AES_REGION_R0_END_LEN (14U) +#define SF_CTRL_SF_AES_REGION_R0_END_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS) +#define SF_CTRL_SF_AES_REGION_R0_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)) +#define SF_CTRL_SF_AES_REGION_R0_START SF_CTRL_SF_AES_REGION_R0_START +#define SF_CTRL_SF_AES_REGION_R0_START_POS (14U) +#define SF_CTRL_SF_AES_REGION_R0_START_LEN (14U) +#define SF_CTRL_SF_AES_REGION_R0_START_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS) +#define SF_CTRL_SF_AES_REGION_R0_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_REGION_R0_EN SF_CTRL_SF_AES_REGION_R0_EN +#define SF_CTRL_SF_AES_REGION_R0_EN_POS (30U) +#define SF_CTRL_SF_AES_REGION_R0_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS) +#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)) +#define SF_CTRL_SF_AES_REGION_R0_LOCK SF_CTRL_SF_AES_REGION_R0_LOCK +#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS (31U) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)) + +/* 0x300 : sf_aes_key_r1_0 */ +#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x300) +#define SF_CTRL_SF_AES_KEY_R1_0 SF_CTRL_SF_AES_KEY_R1_0 +#define SF_CTRL_SF_AES_KEY_R1_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS) +#define SF_CTRL_SF_AES_KEY_R1_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)) + +/* 0x304 : sf_aes_key_r1_1 */ +#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x304) +#define SF_CTRL_SF_AES_KEY_R1_1 SF_CTRL_SF_AES_KEY_R1_1 +#define SF_CTRL_SF_AES_KEY_R1_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS) +#define SF_CTRL_SF_AES_KEY_R1_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)) + +/* 0x308 : sf_aes_key_r1_2 */ +#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x308) +#define SF_CTRL_SF_AES_KEY_R1_2 SF_CTRL_SF_AES_KEY_R1_2 +#define SF_CTRL_SF_AES_KEY_R1_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS) +#define SF_CTRL_SF_AES_KEY_R1_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)) + +/* 0x30C : sf_aes_key_r1_3 */ +#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x30C) +#define SF_CTRL_SF_AES_KEY_R1_3 SF_CTRL_SF_AES_KEY_R1_3 +#define SF_CTRL_SF_AES_KEY_R1_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS) +#define SF_CTRL_SF_AES_KEY_R1_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)) + +/* 0x310 : sf_aes_key_r1_4 */ +#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x310) +#define SF_CTRL_SF_AES_KEY_R1_4 SF_CTRL_SF_AES_KEY_R1_4 +#define SF_CTRL_SF_AES_KEY_R1_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS) +#define SF_CTRL_SF_AES_KEY_R1_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)) + +/* 0x314 : sf_aes_key_r1_5 */ +#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x314) +#define SF_CTRL_SF_AES_KEY_R1_5 SF_CTRL_SF_AES_KEY_R1_5 +#define SF_CTRL_SF_AES_KEY_R1_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS) +#define SF_CTRL_SF_AES_KEY_R1_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)) + +/* 0x318 : sf_aes_key_r1_6 */ +#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x318) +#define SF_CTRL_SF_AES_KEY_R1_6 SF_CTRL_SF_AES_KEY_R1_6 +#define SF_CTRL_SF_AES_KEY_R1_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS) +#define SF_CTRL_SF_AES_KEY_R1_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)) + +/* 0x31C : sf_aes_key_r1_7 */ +#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x31C) +#define SF_CTRL_SF_AES_KEY_R1_7 SF_CTRL_SF_AES_KEY_R1_7 +#define SF_CTRL_SF_AES_KEY_R1_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS) +#define SF_CTRL_SF_AES_KEY_R1_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)) + +/* 0x320 : sf_aes_iv_r1_w0 */ +#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x320) +#define SF_CTRL_SF_AES_IV_R1_W0 SF_CTRL_SF_AES_IV_R1_W0 +#define SF_CTRL_SF_AES_IV_R1_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS) +#define SF_CTRL_SF_AES_IV_R1_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)) + +/* 0x324 : sf_aes_iv_r1_w1 */ +#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x324) +#define SF_CTRL_SF_AES_IV_R1_W1 SF_CTRL_SF_AES_IV_R1_W1 +#define SF_CTRL_SF_AES_IV_R1_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS) +#define SF_CTRL_SF_AES_IV_R1_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)) + +/* 0x328 : sf_aes_iv_r1_w2 */ +#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x328) +#define SF_CTRL_SF_AES_IV_R1_W2 SF_CTRL_SF_AES_IV_R1_W2 +#define SF_CTRL_SF_AES_IV_R1_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS) +#define SF_CTRL_SF_AES_IV_R1_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)) + +/* 0x32C : sf_aes_iv_r1_w3 */ +#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x32C) +#define SF_CTRL_SF_AES_IV_R1_W3 SF_CTRL_SF_AES_IV_R1_W3 +#define SF_CTRL_SF_AES_IV_R1_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS) +#define SF_CTRL_SF_AES_IV_R1_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)) + +/* 0x330 : sf_aes_r1 */ +#define SF_CTRL_SF_AES_R1_OFFSET (0x330) +#define SF_CTRL_SF_AES_R1_END SF_CTRL_SF_AES_R1_END +#define SF_CTRL_SF_AES_R1_END_POS (0U) +#define SF_CTRL_SF_AES_R1_END_LEN (14U) +#define SF_CTRL_SF_AES_R1_END_MSK (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS) +#define SF_CTRL_SF_AES_R1_END_UMSK (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)) +#define SF_CTRL_SF_AES_R1_START SF_CTRL_SF_AES_R1_START +#define SF_CTRL_SF_AES_R1_START_POS (14U) +#define SF_CTRL_SF_AES_R1_START_LEN (14U) +#define SF_CTRL_SF_AES_R1_START_MSK (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS) +#define SF_CTRL_SF_AES_R1_START_UMSK (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN SF_CTRL_SF_AES_R1_HW_KEY_EN +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_R1_EN SF_CTRL_SF_AES_R1_EN +#define SF_CTRL_SF_AES_R1_EN_POS (30U) +#define SF_CTRL_SF_AES_R1_EN_LEN (1U) +#define SF_CTRL_SF_AES_R1_EN_MSK (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS) +#define SF_CTRL_SF_AES_R1_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)) +#define SF_CTRL_SF_AES_R1_LOCK SF_CTRL_SF_AES_R1_LOCK +#define SF_CTRL_SF_AES_R1_LOCK_POS (31U) +#define SF_CTRL_SF_AES_R1_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_R1_LOCK_MSK (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS) +#define SF_CTRL_SF_AES_R1_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)) + +/* 0x400 : sf_aes_key_r2_0 */ +#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x400) +#define SF_CTRL_SF_AES_KEY_R2_0 SF_CTRL_SF_AES_KEY_R2_0 +#define SF_CTRL_SF_AES_KEY_R2_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS) +#define SF_CTRL_SF_AES_KEY_R2_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)) + +/* 0x404 : sf_aes_key_r2_1 */ +#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x404) +#define SF_CTRL_SF_AES_KEY_R2_1 SF_CTRL_SF_AES_KEY_R2_1 +#define SF_CTRL_SF_AES_KEY_R2_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS) +#define SF_CTRL_SF_AES_KEY_R2_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)) + +/* 0x408 : sf_aes_key_r2_2 */ +#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x408) +#define SF_CTRL_SF_AES_KEY_R2_2 SF_CTRL_SF_AES_KEY_R2_2 +#define SF_CTRL_SF_AES_KEY_R2_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS) +#define SF_CTRL_SF_AES_KEY_R2_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)) + +/* 0x40C : sf_aes_key_r2_3 */ +#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x40C) +#define SF_CTRL_SF_AES_KEY_R2_3 SF_CTRL_SF_AES_KEY_R2_3 +#define SF_CTRL_SF_AES_KEY_R2_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS) +#define SF_CTRL_SF_AES_KEY_R2_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)) + +/* 0x410 : sf_aes_key_r2_4 */ +#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x410) +#define SF_CTRL_SF_AES_KEY_R2_4 SF_CTRL_SF_AES_KEY_R2_4 +#define SF_CTRL_SF_AES_KEY_R2_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS) +#define SF_CTRL_SF_AES_KEY_R2_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)) + +/* 0x414 : sf_aes_key_r2_5 */ +#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x414) +#define SF_CTRL_SF_AES_KEY_R2_5 SF_CTRL_SF_AES_KEY_R2_5 +#define SF_CTRL_SF_AES_KEY_R2_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS) +#define SF_CTRL_SF_AES_KEY_R2_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)) + +/* 0x418 : sf_aes_key_r2_6 */ +#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x418) +#define SF_CTRL_SF_AES_KEY_R2_6 SF_CTRL_SF_AES_KEY_R2_6 +#define SF_CTRL_SF_AES_KEY_R2_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS) +#define SF_CTRL_SF_AES_KEY_R2_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)) + +/* 0x41C : sf_aes_key_r2_7 */ +#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x41C) +#define SF_CTRL_SF_AES_KEY_R2_7 SF_CTRL_SF_AES_KEY_R2_7 +#define SF_CTRL_SF_AES_KEY_R2_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS) +#define SF_CTRL_SF_AES_KEY_R2_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)) + +/* 0x420 : sf_aes_iv_r2_w0 */ +#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x420) +#define SF_CTRL_SF_AES_IV_R2_W0 SF_CTRL_SF_AES_IV_R2_W0 +#define SF_CTRL_SF_AES_IV_R2_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS) +#define SF_CTRL_SF_AES_IV_R2_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)) + +/* 0x424 : sf_aes_iv_r2_w1 */ +#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x424) +#define SF_CTRL_SF_AES_IV_R2_W1 SF_CTRL_SF_AES_IV_R2_W1 +#define SF_CTRL_SF_AES_IV_R2_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS) +#define SF_CTRL_SF_AES_IV_R2_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)) + +/* 0x428 : sf_aes_iv_r2_w2 */ +#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x428) +#define SF_CTRL_SF_AES_IV_R2_W2 SF_CTRL_SF_AES_IV_R2_W2 +#define SF_CTRL_SF_AES_IV_R2_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS) +#define SF_CTRL_SF_AES_IV_R2_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)) + +/* 0x42C : sf_aes_iv_r2_w3 */ +#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x42C) +#define SF_CTRL_SF_AES_IV_R2_W3 SF_CTRL_SF_AES_IV_R2_W3 +#define SF_CTRL_SF_AES_IV_R2_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS) +#define SF_CTRL_SF_AES_IV_R2_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)) + +/* 0x430 : sf_aes_r2 */ +#define SF_CTRL_SF_AES_R2_OFFSET (0x430) +#define SF_CTRL_SF_AES_R2_END SF_CTRL_SF_AES_R2_END +#define SF_CTRL_SF_AES_R2_END_POS (0U) +#define SF_CTRL_SF_AES_R2_END_LEN (14U) +#define SF_CTRL_SF_AES_R2_END_MSK (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS) +#define SF_CTRL_SF_AES_R2_END_UMSK (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)) +#define SF_CTRL_SF_AES_R2_START SF_CTRL_SF_AES_R2_START +#define SF_CTRL_SF_AES_R2_START_POS (14U) +#define SF_CTRL_SF_AES_R2_START_LEN (14U) +#define SF_CTRL_SF_AES_R2_START_MSK (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS) +#define SF_CTRL_SF_AES_R2_START_UMSK (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN SF_CTRL_SF_AES_R2_HW_KEY_EN +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_R2_EN SF_CTRL_SF_AES_R2_EN +#define SF_CTRL_SF_AES_R2_EN_POS (30U) +#define SF_CTRL_SF_AES_R2_EN_LEN (1U) +#define SF_CTRL_SF_AES_R2_EN_MSK (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS) +#define SF_CTRL_SF_AES_R2_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)) +#define SF_CTRL_SF_AES_R2_LOCK SF_CTRL_SF_AES_R2_LOCK +#define SF_CTRL_SF_AES_R2_LOCK_POS (31U) +#define SF_CTRL_SF_AES_R2_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_R2_LOCK_MSK (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS) +#define SF_CTRL_SF_AES_R2_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)) + +/* 0x434 : sf_id0_offset */ +#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0x434) +#define SF_CTRL_SF_ID0_OFFSET SF_CTRL_SF_ID0_OFFSET +#define SF_CTRL_SF_ID0_OFFSET_POS (0U) +#define SF_CTRL_SF_ID0_OFFSET_LEN (24U) +#define SF_CTRL_SF_ID0_OFFSET_MSK (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS) +#define SF_CTRL_SF_ID0_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)) + +/* 0x438 : sf_id1_offset */ +#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0x438) +#define SF_CTRL_SF_ID1_OFFSET SF_CTRL_SF_ID1_OFFSET +#define SF_CTRL_SF_ID1_OFFSET_POS (0U) +#define SF_CTRL_SF_ID1_OFFSET_LEN (24U) +#define SF_CTRL_SF_ID1_OFFSET_MSK (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS) +#define SF_CTRL_SF_ID1_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)) + +/* 0x43C : sf_bk2_id0_offset */ +#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0x43C) +#define SF_CTRL_SF_BK2_ID0_OFFSET SF_CTRL_SF_BK2_ID0_OFFSET +#define SF_CTRL_SF_BK2_ID0_OFFSET_POS (0U) +#define SF_CTRL_SF_BK2_ID0_OFFSET_LEN (24U) +#define SF_CTRL_SF_BK2_ID0_OFFSET_MSK (((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS) +#define SF_CTRL_SF_BK2_ID0_OFFSET_UMSK (~(((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS)) + +/* 0x440 : sf_bk2_id1_offset */ +#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0x440) +#define SF_CTRL_SF_BK2_ID1_OFFSET SF_CTRL_SF_BK2_ID1_OFFSET +#define SF_CTRL_SF_BK2_ID1_OFFSET_POS (0U) +#define SF_CTRL_SF_BK2_ID1_OFFSET_LEN (24U) +#define SF_CTRL_SF_BK2_ID1_OFFSET_MSK (((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS) +#define SF_CTRL_SF_BK2_ID1_OFFSET_UMSK (~(((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS)) + +struct sf_ctrl_reg { + /* 0x0 : sf_ctrl_0 */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t sf_clk_sf_rx_inv_sel : 1; /* [ 2], r/w, 0x1 */ + uint32_t sf_clk_out_gate_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t sf_clk_out_inv_sel : 1; /* [ 4], r/w, 0x1 */ + uint32_t sf_clk_sahb_sram_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t sf_if_read_dly_n : 3; /* [10: 8], r/w, 0x0 */ + uint32_t sf_if_read_dly_en : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t sf_if_int : 1; /* [ 16], r, 0x0 */ + uint32_t sf_if_int_clr : 1; /* [ 17], r/w, 0x1 */ + uint32_t sf_if_int_set : 1; /* [ 18], r/w, 0x0 */ + uint32_t sf_aes_dly_mode : 1; /* [ 19], r/w, 0x0 */ + uint32_t sf_aes_dout_endian : 1; /* [ 20], r/w, 0x1 */ + uint32_t sf_aes_ctr_plus_en : 1; /* [ 21], r/w, 0x0 */ + uint32_t sf_aes_key_endian : 1; /* [ 22], r/w, 0x1 */ + uint32_t sf_aes_iv_endian : 1; /* [ 23], r/w, 0x1 */ + uint32_t sf_id : 8; /* [31:24], r/w, 0x1a */ + } BF; + uint32_t WORD; + } sf_ctrl_0; + + /* 0x4 : sf_ctrl_1 */ + union { + struct + { + uint32_t sf_if_sr_pat_mask : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t sf_if_sr_pat : 8; /* [15: 8], r/w, 0x0 */ + uint32_t sf_if_sr_int : 1; /* [ 16], r, 0x0 */ + uint32_t sf_if_sr_int_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t sf_if_sr_int_set : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t sf_if_0_ack_lat : 3; /* [22:20], r/w, 0x6 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t sf_if_reg_hold : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_reg_wp : 1; /* [ 25], r/w, 0x1 */ + uint32_t sf_ahb2sif_stopped : 1; /* [ 26], r, 0x0 */ + uint32_t sf_ahb2sif_stop : 1; /* [ 27], r/w, 0x0 */ + uint32_t sf_if_fn_sel : 1; /* [ 28], r/w, 0x1 */ + uint32_t sf_if_en : 1; /* [ 29], r/w, 0x1 */ + uint32_t sf_ahb2sif_en : 1; /* [ 30], r/w, 0x1 */ + uint32_t sf_ahb2sram_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_ctrl_1; + + /* 0x8 : sf_if_sahb_0 */ + union { + struct + { + uint32_t sf_if_busy : 1; /* [ 0], r, 0x0 */ + uint32_t sf_if_0_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t sf_if_0_dat_byte : 10; /* [11: 2], r/w, 0x0 */ + uint32_t sf_if_0_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_0_adr_byte : 3; /* [19:17], r/w, 0x0 */ + uint32_t sf_if_0_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_0_dat_rw : 1; /* [ 23], r/w, 0x0 */ + uint32_t sf_if_0_dat_en : 1; /* [ 24], r/w, 0x0 */ + uint32_t sf_if_0_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_0_adr_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t sf_if_0_cmd_en : 1; /* [ 27], r/w, 0x0 */ + uint32_t sf_if_0_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_0_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_0; + + /* 0xC : sf_if_sahb_1 */ + union { + struct + { + uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_1; + + /* 0x10 : sf_if_sahb_2 */ + union { + struct + { + uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_2; + + /* 0x14 : sf_if_iahb_0 */ + union { + struct + { + uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ + uint32_t sf_if_1_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_1_adr_byte : 3; /* [19:17], r/w, 0x2 */ + uint32_t sf_if_1_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_1_dat_rw : 1; /* [ 23], r/w, 0x0 */ + uint32_t sf_if_1_dat_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_1_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_1_adr_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t sf_if_1_cmd_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t sf_if_1_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_1_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_0; + + /* 0x18 : sf_if_iahb_1 */ + union { + struct + { + uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0], r/w, 0x3000000 */ + } BF; + uint32_t WORD; + } sf_if_iahb_1; + + /* 0x1C : sf_if_iahb_2 */ + union { + struct + { + uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_2; + + /* 0x20 : sf_if_status_0 */ + union { + struct + { + uint32_t sf_if_status_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_status_0; + + /* 0x24 : sf_if_status_1 */ + union { + struct + { + uint32_t sf_if_status_1 : 32; /* [31: 0], r, 0x20000000 */ + } BF; + uint32_t WORD; + } sf_if_status_1; + + /* 0x28 : sf_aes */ + union { + struct + { + uint32_t sf_aes_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t sf_aes_mode : 2; /* [ 2: 1], r/w, 0x0 */ + uint32_t sf_aes_pref_trig : 1; /* [ 3], r/w, 0x0 */ + uint32_t sf_aes_pref_busy : 1; /* [ 4], r, 0x0 */ + uint32_t sf_aes_status : 27; /* [31: 5], r, 0x2 */ + } BF; + uint32_t WORD; + } sf_aes; + + /* 0x2C : sf_ahb2sif_status */ + union { + struct + { + uint32_t sf_ahb2sif_status : 32; /* [31: 0], r, 0x10000003 */ + } BF; + uint32_t WORD; + } sf_ahb2sif_status; + + /* 0x30 : sf_if_io_dly_0 */ + union { + struct + { + uint32_t sf_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t sf_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t sf_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_0; + + /* 0x34 : sf_if_io_dly_1 */ + union { + struct + { + uint32_t sf_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_1; + + /* 0x38 : sf_if_io_dly_2 */ + union { + struct + { + uint32_t sf_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_2; + + /* 0x3C : sf_if_io_dly_3 */ + union { + struct + { + uint32_t sf_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_3; + + /* 0x40 : sf_if_io_dly_4 */ + union { + struct + { + uint32_t sf_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_4; + + /* 0x44 : sf_reserved */ + union { + struct + { + uint32_t sf_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } sf_reserved; + + /* 0x48 : sf2_if_io_dly_0 */ + union { + struct + { + uint32_t sf2_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t sf2_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t sf2_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf2_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf2_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf2_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_0; + + /* 0x4C : sf2_if_io_dly_1 */ + union { + struct + { + uint32_t sf2_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_1; + + /* 0x50 : sf2_if_io_dly_2 */ + union { + struct + { + uint32_t sf2_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_2; + + /* 0x54 : sf2_if_io_dly_3 */ + union { + struct + { + uint32_t sf2_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_3; + + /* 0x58 : sf2_if_io_dly_4 */ + union { + struct + { + uint32_t sf2_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_4; + + /* 0x5C : sf3_if_io_dly_0 */ + union { + struct + { + uint32_t sf3_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t sf3_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t sf3_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf3_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf3_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf3_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_0; + + /* 0x60 : sf3_if_io_dly_1 */ + union { + struct + { + uint32_t sf3_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_1; + + /* 0x64 : sf3_if_io_dly_2 */ + union { + struct + { + uint32_t sf3_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_2; + + /* 0x68 : sf3_if_io_dly_3 */ + union { + struct + { + uint32_t sf3_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_3; + + /* 0x6C : sf3_if_io_dly_4 */ + union { + struct + { + uint32_t sf3_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_4; + + /* 0x70 : sf_ctrl_2 */ + union { + struct + { + uint32_t sf_if_pad_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */ + uint32_t sf_if_pad_sel_lock : 1; /* [ 3], r/w, 0x0 */ + uint32_t sf_if_dtr_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t sf_if_dqs_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_27 : 22; /* [27: 6], rsvd, 0x0 */ + uint32_t sf_if_bk_swap : 1; /* [ 28], r/w, 0x0 */ + uint32_t sf_if_bk2_mode : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_if_bk2_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_if_0_bk_sel : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_2; + + /* 0x74 : sf_ctrl_3 */ + union { + struct + { + uint32_t sf_cmds_wrap_len : 4; /* [ 3: 0], r/w, 0x6 */ + uint32_t sf_cmds_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t sf_cmds_bt_dly : 3; /* [ 7: 5], r/w, 0x2 */ + uint32_t sf_cmds_bt_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t sf_cmds_wrap_q_ini : 1; /* [ 9], r/w, 0x0 */ + uint32_t sf_cmds_wrap_mode : 1; /* [ 10], r/w, 0x0 */ + uint32_t sf_cmds_wrap_q : 1; /* [ 11], r, 0x0 */ + uint32_t reserved_12_28 : 17; /* [28:12], rsvd, 0x0 */ + uint32_t sf_if_1_ack_lat : 3; /* [31:29], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_ctrl_3; + + /* 0x78 : sf_if_iahb_3 */ + union { + struct + { + uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ + uint32_t sf_if_2_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_2_adr_byte : 3; /* [19:17], r/w, 0x2 */ + uint32_t sf_if_2_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_2_dat_rw : 1; /* [ 23], r/w, 0x1 */ + uint32_t sf_if_2_dat_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_2_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_2_adr_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t sf_if_2_cmd_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t sf_if_2_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_2_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_if_iahb_3; + + /* 0x7C : sf_if_iahb_4 */ + union { + struct + { + uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0], r/w, 0x38000000 */ + } BF; + uint32_t WORD; + } sf_if_iahb_4; + + /* 0x80 : sf_if_iahb_5 */ + union { + struct + { + uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_5; + + /* 0x84 : sf_if_iahb_6 */ + union { + struct + { + uint32_t reserved_0_16 : 17; /* [16: 0], rsvd, 0x0 */ + uint32_t sf_if_3_adr_byte : 3; /* [19:17], r/w, 0x0 */ + uint32_t sf_if_3_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_25 : 3; /* [25:23], rsvd, 0x0 */ + uint32_t sf_if_3_adr_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t sf_if_3_cmd_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t sf_if_3_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_3_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_if_iahb_6; + + /* 0x88 : sf_if_iahb_7 */ + union { + struct + { + uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0], r/w, 0xc0000000L */ + } BF; + uint32_t WORD; + } sf_if_iahb_7; + + /* 0x8C : sf_if_iahb_8 */ + union { + struct + { + uint32_t sf_if_3_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_8; + + /* 0x90 : sf_if_iahb_9 */ + union { + struct + { + uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ + uint32_t sf_if_4_dmy_byte : 5; /* [16:12], r/w, 0x2 */ + uint32_t sf_if_4_adr_byte : 3; /* [19:17], r/w, 0x2 */ + uint32_t sf_if_4_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_4_dat_rw : 1; /* [ 23], r/w, 0x0 */ + uint32_t sf_if_4_dat_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_4_dmy_en : 1; /* [ 25], r/w, 0x1 */ + uint32_t sf_if_4_adr_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t sf_if_4_cmd_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t sf_if_4_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_4_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_if_iahb_9; + + /* 0x94 : sf_if_iahb_10 */ + union { + struct + { + uint32_t sf_if_4_cmd_buf_0 : 32; /* [31: 0], r/w, 0xeb000000L */ + } BF; + uint32_t WORD; + } sf_if_iahb_10; + + /* 0x98 : sf_if_iahb_11 */ + union { + struct + { + uint32_t sf_if_4_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_11; + + /* 0x9C : sf_if_iahb_12 */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t sf2_clk_sf_rx_inv_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t sf2_clk_sf_rx_inv_src : 1; /* [ 3], r/w, 0x0 */ + uint32_t sf2_clk_out_inv_sel : 1; /* [ 4], r/w, 0x1 */ + uint32_t sf3_clk_out_inv_sel : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t sf2_if_read_dly_n : 3; /* [10: 8], r/w, 0x0 */ + uint32_t sf2_if_read_dly_en : 1; /* [ 11], r/w, 0x0 */ + uint32_t sf2_if_read_dly_src : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_12; + + /* 0xa0 reserved */ + uint8_t RESERVED0xa0[96]; + + /* 0x100 : sf_ctrl_prot_en_rd */ + union { + struct + { + uint32_t sf_ctrl_prot_en_rd : 1; /* [ 0], r, 0x1 */ + uint32_t sf_ctrl_id0_en_rd : 1; /* [ 1], r, 0x1 */ + uint32_t sf_ctrl_id1_en_rd : 1; /* [ 2], r, 0x1 */ + uint32_t reserved_3_29 : 27; /* [29: 3], rsvd, 0x0 */ + uint32_t sf_if_0_trig_wr_lock : 1; /* [ 30], r, 0x0 */ + uint32_t sf_dbg_dis : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_prot_en_rd; + + /* 0x104 : sf_ctrl_prot_en */ + union { + struct + { + uint32_t sf_ctrl_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t sf_ctrl_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t sf_ctrl_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_prot_en; + + /* 0x108 reserved */ + uint8_t RESERVED0x108[248]; + + /* 0x200 : sf_aes_key_r0_0 */ + union { + struct + { + uint32_t sf_aes_key_r0_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_0; + + /* 0x204 : sf_aes_key_r0_1 */ + union { + struct + { + uint32_t sf_aes_key_r0_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_1; + + /* 0x208 : sf_aes_key_r0_2 */ + union { + struct + { + uint32_t sf_aes_key_r0_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_2; + + /* 0x20C : sf_aes_key_r0_3 */ + union { + struct + { + uint32_t sf_aes_key_r0_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_3; + + /* 0x210 : sf_aes_key_r0_4 */ + union { + struct + { + uint32_t sf_aes_key_r0_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_4; + + /* 0x214 : sf_aes_key_r0_5 */ + union { + struct + { + uint32_t sf_aes_key_r0_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_5; + + /* 0x218 : sf_aes_key_r0_6 */ + union { + struct + { + uint32_t sf_aes_key_r0_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_6; + + /* 0x21C : sf_aes_key_r0_7 */ + union { + struct + { + uint32_t sf_aes_key_r0_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_7; + + /* 0x220 : sf_aes_iv_r0_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w0; + + /* 0x224 : sf_aes_iv_r0_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w1; + + /* 0x228 : sf_aes_iv_r0_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w2; + + /* 0x22C : sf_aes_iv_r0_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w3; + + /* 0x230 : sf_aes_cfg_r0 */ + union { + struct + { + uint32_t sf_aes_region_r0_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_region_r0_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_region_r0_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_region_r0_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_region_r0_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_cfg_r0; + + /* 0x234 reserved */ + uint8_t RESERVED0x234[204]; + + /* 0x300 : sf_aes_key_r1_0 */ + union { + struct + { + uint32_t sf_aes_key_r1_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_0; + + /* 0x304 : sf_aes_key_r1_1 */ + union { + struct + { + uint32_t sf_aes_key_r1_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_1; + + /* 0x308 : sf_aes_key_r1_2 */ + union { + struct + { + uint32_t sf_aes_key_r1_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_2; + + /* 0x30C : sf_aes_key_r1_3 */ + union { + struct + { + uint32_t sf_aes_key_r1_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_3; + + /* 0x310 : sf_aes_key_r1_4 */ + union { + struct + { + uint32_t sf_aes_key_r1_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_4; + + /* 0x314 : sf_aes_key_r1_5 */ + union { + struct + { + uint32_t sf_aes_key_r1_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_5; + + /* 0x318 : sf_aes_key_r1_6 */ + union { + struct + { + uint32_t sf_aes_key_r1_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_6; + + /* 0x31C : sf_aes_key_r1_7 */ + union { + struct + { + uint32_t sf_aes_key_r1_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_7; + + /* 0x320 : sf_aes_iv_r1_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w0; + + /* 0x324 : sf_aes_iv_r1_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w1; + + /* 0x328 : sf_aes_iv_r1_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w2; + + /* 0x32C : sf_aes_iv_r1_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w3; + + /* 0x330 : sf_aes_r1 */ + union { + struct + { + uint32_t sf_aes_r1_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_r1_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_r1_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_r1_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_r1_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_r1; + + /* 0x334 reserved */ + uint8_t RESERVED0x334[204]; + + /* 0x400 : sf_aes_key_r2_0 */ + union { + struct + { + uint32_t sf_aes_key_r2_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_0; + + /* 0x404 : sf_aes_key_r2_1 */ + union { + struct + { + uint32_t sf_aes_key_r2_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_1; + + /* 0x408 : sf_aes_key_r2_2 */ + union { + struct + { + uint32_t sf_aes_key_r2_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_2; + + /* 0x40C : sf_aes_key_r2_3 */ + union { + struct + { + uint32_t sf_aes_key_r2_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_3; + + /* 0x410 : sf_aes_key_r2_4 */ + union { + struct + { + uint32_t sf_aes_key_r2_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_4; + + /* 0x414 : sf_aes_key_r2_5 */ + union { + struct + { + uint32_t sf_aes_key_r2_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_5; + + /* 0x418 : sf_aes_key_r2_6 */ + union { + struct + { + uint32_t sf_aes_key_r2_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_6; + + /* 0x41C : sf_aes_key_r2_7 */ + union { + struct + { + uint32_t sf_aes_key_r2_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_7; + + /* 0x420 : sf_aes_iv_r2_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w0; + + /* 0x424 : sf_aes_iv_r2_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w1; + + /* 0x428 : sf_aes_iv_r2_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w2; + + /* 0x42C : sf_aes_iv_r2_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w3; + + /* 0x430 : sf_aes_r2 */ + union { + struct + { + uint32_t sf_aes_r2_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_r2_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_r2_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_r2_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_r2_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_r2; + + /* 0x434 : sf_id0_offset */ + union { + struct + { + uint32_t sf_id0_offset : 24; /* [23: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_id0_offset; + + /* 0x438 : sf_id1_offset */ + union { + struct + { + uint32_t sf_id1_offset : 24; /* [23: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_id1_offset; + + /* 0x43C : sf_bk2_id0_offset */ + union { + struct + { + uint32_t sf_bk2_id0_offset : 24; /* [23: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_bk2_id0_offset; + + /* 0x440 : sf_bk2_id1_offset */ + union { + struct + { + uint32_t sf_bk2_id1_offset : 24; /* [23: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_bk2_id1_offset; +}; + +typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : sf_aes_key_0 */ +#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0) +#define SF_CTRL_SF_AES_KEY_0 SF_CTRL_SF_AES_KEY_0 +#define SF_CTRL_SF_AES_KEY_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_0_MSK (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS) +#define SF_CTRL_SF_AES_KEY_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)) + +/* 0x4 : sf_aes_key_1 */ +#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4) +#define SF_CTRL_SF_AES_KEY_1 SF_CTRL_SF_AES_KEY_1 +#define SF_CTRL_SF_AES_KEY_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_1_MSK (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS) +#define SF_CTRL_SF_AES_KEY_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)) + +/* 0x8 : sf_aes_key_2 */ +#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8) +#define SF_CTRL_SF_AES_KEY_2 SF_CTRL_SF_AES_KEY_2 +#define SF_CTRL_SF_AES_KEY_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_2_MSK (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS) +#define SF_CTRL_SF_AES_KEY_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)) + +/* 0xc : sf_aes_key_3 */ +#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc) +#define SF_CTRL_SF_AES_KEY_3 SF_CTRL_SF_AES_KEY_3 +#define SF_CTRL_SF_AES_KEY_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_3_MSK (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS) +#define SF_CTRL_SF_AES_KEY_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)) + +/* 0x10 : sf_aes_key_4 */ +#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10) +#define SF_CTRL_SF_AES_KEY_4 SF_CTRL_SF_AES_KEY_4 +#define SF_CTRL_SF_AES_KEY_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_4_MSK (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS) +#define SF_CTRL_SF_AES_KEY_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)) + +/* 0x14 : sf_aes_key_5 */ +#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14) +#define SF_CTRL_SF_AES_KEY_5 SF_CTRL_SF_AES_KEY_5 +#define SF_CTRL_SF_AES_KEY_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_5_MSK (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS) +#define SF_CTRL_SF_AES_KEY_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)) + +/* 0x18 : sf_aes_key_6 */ +#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18) +#define SF_CTRL_SF_AES_KEY_6 SF_CTRL_SF_AES_KEY_6 +#define SF_CTRL_SF_AES_KEY_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_6_MSK (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS) +#define SF_CTRL_SF_AES_KEY_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)) + +/* 0x1c : sf_aes_key_7 */ +#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c) +#define SF_CTRL_SF_AES_KEY_7 SF_CTRL_SF_AES_KEY_7 +#define SF_CTRL_SF_AES_KEY_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_7_MSK (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS) +#define SF_CTRL_SF_AES_KEY_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)) + +/* 0x20 : sf_aes_iv_w0 */ +#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20) +#define SF_CTRL_SF_AES_IV_W0 SF_CTRL_SF_AES_IV_W0 +#define SF_CTRL_SF_AES_IV_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_W0_MSK (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS) +#define SF_CTRL_SF_AES_IV_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)) + +/* 0x24 : sf_aes_iv_w1 */ +#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24) +#define SF_CTRL_SF_AES_IV_W1 SF_CTRL_SF_AES_IV_W1 +#define SF_CTRL_SF_AES_IV_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_W1_MSK (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS) +#define SF_CTRL_SF_AES_IV_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)) + +/* 0x28 : sf_aes_iv_w2 */ +#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28) +#define SF_CTRL_SF_AES_IV_W2 SF_CTRL_SF_AES_IV_W2 +#define SF_CTRL_SF_AES_IV_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_W2_MSK (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS) +#define SF_CTRL_SF_AES_IV_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)) + +/* 0x2c : sf_aes_iv_w3 */ +#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c) +#define SF_CTRL_SF_AES_IV_W3 SF_CTRL_SF_AES_IV_W3 +#define SF_CTRL_SF_AES_IV_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_W3_MSK (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS) +#define SF_CTRL_SF_AES_IV_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)) + +/* 0x30 : sf_aes_cfg */ +#define SF_CTRL_SF_AES_CFG_OFFSET (0x30) +#define SF_CTRL_SF_AES_REGION_END SF_CTRL_SF_AES_REGION_END +#define SF_CTRL_SF_AES_REGION_END_POS (0U) +#define SF_CTRL_SF_AES_REGION_END_LEN (14U) +#define SF_CTRL_SF_AES_REGION_END_MSK (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS) +#define SF_CTRL_SF_AES_REGION_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)) +#define SF_CTRL_SF_AES_REGION_START SF_CTRL_SF_AES_REGION_START +#define SF_CTRL_SF_AES_REGION_START_POS (14U) +#define SF_CTRL_SF_AES_REGION_START_LEN (14U) +#define SF_CTRL_SF_AES_REGION_START_MSK (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS) +#define SF_CTRL_SF_AES_REGION_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN SF_CTRL_SF_AES_REGION_HW_KEY_EN +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_REGION_EN SF_CTRL_SF_AES_REGION_EN +#define SF_CTRL_SF_AES_REGION_EN_POS (30U) +#define SF_CTRL_SF_AES_REGION_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS) +#define SF_CTRL_SF_AES_REGION_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)) +#define SF_CTRL_SF_AES_REGION_LOCK SF_CTRL_SF_AES_REGION_LOCK +#define SF_CTRL_SF_AES_REGION_LOCK_POS (31U) +#define SF_CTRL_SF_AES_REGION_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_REGION_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS) +#define SF_CTRL_SF_AES_REGION_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)) + +struct sf_ctrl_aes_region_reg { + /* 0x0 : sf_aes_key_0 */ + union { + struct + { + uint32_t sf_aes_key_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_0; + + /* 0x4 : sf_aes_key_1 */ + union { + struct + { + uint32_t sf_aes_key_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_1; + + /* 0x8 : sf_aes_key_2 */ + union { + struct + { + uint32_t sf_aes_key_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_2; + + /* 0xc : sf_aes_key_3 */ + union { + struct + { + uint32_t sf_aes_key_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_3; + + /* 0x10 : sf_aes_key_4 */ + union { + struct + { + uint32_t sf_aes_key_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_4; + + /* 0x14 : sf_aes_key_5 */ + union { + struct + { + uint32_t sf_aes_key_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_5; + + /* 0x18 : sf_aes_key_6 */ + union { + struct + { + uint32_t sf_aes_key_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_6; + + /* 0x1c : sf_aes_key_7 */ + union { + struct + { + uint32_t sf_aes_key_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_7; + + /* 0x20 : sf_aes_iv_w0 */ + union { + struct + { + uint32_t sf_aes_iv_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w0; + + /* 0x24 : sf_aes_iv_w1 */ + union { + struct + { + uint32_t sf_aes_iv_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w1; + + /* 0x28 : sf_aes_iv_w2 */ + union { + struct + { + uint32_t sf_aes_iv_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w2; + + /* 0x2c : sf_aes_iv_w3 */ + union { + struct + { + uint32_t sf_aes_iv_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w3; + + /* 0x30 : sf_aes_cfg */ + union { + struct + { + uint32_t sf_aes_region_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_region_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_region_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_region_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_region_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_cfg; +}; + +typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t; + +#define SF_CTRL_AES_REGION_OFFSET 0x200 + +#endif /* __SF_CTRL_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/soc702_reg.svd b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/soc702_reg.svd new file mode 100644 index 0000000000000000000000000000000000000000..939bb8ed006842d88a7c36b25ec7901d35dd3377 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/soc702_reg.svd @@ -0,0 +1,22548 @@ + + + bouffalolab + bouffalolab + 702 + WiFi BT + high-performance, 32-bit RV32IMAFC core + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + 702 + little + + + + glb + glb. + 0x40000000 + glb + 32 + read-write + + 0 + 0x1000 + registers + + + + clk_cfg0 + clk_cfg0. + 0x0 + + + glb_id + 28 + 31 + + + chip_rdy + 27 + 27 + + + fclk_sw_state + 24 + 26 + + + reg_bclk_div + 16 + 23 + + + reg_hclk_div + 8 + 15 + + + hbn_root_clk_sel + 6 + 7 + + + reg_pll_sel + 4 + 5 + + + reg_bclk_en + 3 + 3 + + + reg_hclk_en + 2 + 2 + + + reg_fclk_en + 1 + 1 + + + reg_pll_en + 0 + 0 + + + + + clk_cfg1 + clk_cfg1. + 0x4 + + + reg_cam_ref_clk_div + 30 + 31 + + + reg_cam_ref_clk_src_sel + 29 + 29 + + + reg_cam_ref_clk_en + 28 + 28 + + + m154_zbEn + 25 + 25 + + + ble_en + 24 + 24 + + + ble_clk_sel + 16 + 21 + + + reg_i2s_0_ref_clk_oe + 14 + 14 + + + reg_i2s0_clk_en + 13 + 13 + + + reg_i2s_clk_sel + 12 + 12 + + + dll_48m_div_en + 9 + 9 + + + usb_clk_en + 8 + 8 + + + qdec_clk_sel + 7 + 7 + + + qdec_clk_div + 0 + 4 + + + + + clk_cfg2 + clk_cfg2. + 0x8 + + + dma_clk_en + 24 + 31 + + + ir_clk_en + 23 + 23 + + + ir_clk_div + 16 + 21 + + + sf_clk_sel2 + 14 + 15 + + + sf_clk_sel + 12 + 13 + + + sf_clk_en + 11 + 11 + + + sf_clk_div + 8 + 10 + + + hbn_uart_clk_sel + 7 + 7 + + + uart_clk_en + 4 + 4 + + + uart_clk_div + 0 + 2 + + + + + clk_cfg3 + clk_cfg3. + 0xC + + + chip_clk_out_1_sel + 30 + 31 + + + chip_clk_out_0_sel + 28 + 29 + + + i2c_clk_en + 24 + 24 + + + i2c_clk_div + 16 + 23 + + + cfg_inv_eth_rx_clk + 10 + 10 + + + cfg_inv_rf_test_clk_o + 9 + 9 + + + spi_clk_en + 8 + 8 + + + cfg_inv_eth_tx_clk + 7 + 7 + + + cfg_inv_eth_ref_clk_o + 6 + 6 + + + cfg_sel_eth_ref_clk_o + 5 + 5 + + + spi_clk_div + 0 + 4 + + + + + swrst_cfg0 + swrst_cfg0. + 0x10 + + + swrst_s30 + 8 + 8 + + + swrst_s20 + 4 + 4 + + + swrst_s01 + 1 + 1 + + + swrst_s00 + 0 + 0 + + + + + swrst_cfg1 + swrst_cfg1. + 0x14 + + + swrst_s1ae + 30 + 30 + + + swrst_s1ad + 29 + 29 + + + swrst_s1ac + 28 + 28 + + + swrst_s1ab + 27 + 27 + + + swrst_s1aa + 26 + 26 + + + swrst_s1a9 + 25 + 25 + + + swrst_s1a8 + 24 + 24 + + + swrst_s1a7 + 23 + 23 + + + swrst_s1a6 + 22 + 22 + + + swrst_s1a5 + 21 + 21 + + + swrst_s1a4 + 20 + 20 + + + swrst_s1a3 + 19 + 19 + + + swrst_s1a2 + 18 + 18 + + + swrst_s1a1 + 17 + 17 + + + swrst_s1a0 + 16 + 16 + + + swrst_s1f + 15 + 15 + + + swrst_s1e + 14 + 14 + + + swrst_s1d + 13 + 13 + + + swrst_s1c + 12 + 12 + + + swrst_s1b + 11 + 11 + + + swrst_s1a + 10 + 10 + + + swrst_s19 + 9 + 9 + + + swrst_s18 + 8 + 8 + + + swrst_s17 + 7 + 7 + + + swrst_s16 + 6 + 6 + + + swrst_s15 + 5 + 5 + + + swrst_s14 + 4 + 4 + + + swrst_s13 + 3 + 3 + + + swrst_s12 + 2 + 2 + + + swrst_s11 + 1 + 1 + + + swrst_s10 + 0 + 0 + + + + + swrst_cfg2 + swrst_cfg2. + 0x18 + + + pka_clk_sel + 24 + 24 + + + reg_ctrl_reset_dummy + 4 + 7 + + + reg_ctrl_sys_reset + 2 + 2 + + + reg_ctrl_cpu_reset + 1 + 1 + + + reg_ctrl_pwron_rst + 0 + 0 + + + + + swrst_cfg3 + swrst_cfg3. + 0x1C + + + + cgen_cfg0 + cgen_cfg0. + 0x20 + + + cgen_m + 0 + 7 + + + + + cgen_cfg1 + cgen_cfg1. + 0x24 + + + cgen_s1a + 16 + 31 + + + cgen_s1 + 0 + 15 + + + + + cgen_cfg2 + cgen_cfg2. + 0x28 + + + cgen_s3 + 4 + 4 + + + cgen_s2 + 0 + 0 + + + + + cgen_cfg3 + cgen_cfg3. + 0x2C + + + + MBIST_CTL + MBIST_CTL. + 0x30 + + + reg_mbist_rst_n + 31 + 31 + + + em_ram_mbist_mode + 5 + 5 + + + ocram_mbist_mode + 4 + 4 + + + tag_mbist_mode + 3 + 3 + + + hsram_cache_mbist_mode + 2 + 2 + + + hsram_mem_mbist_mode + 1 + 1 + + + irom_mbist_mode + 0 + 0 + + + + + MBIST_STAT + MBIST_STAT. + 0x34 + + + em_ram_mbist_fail + 21 + 21 + + + ocram_mbist_fail + 20 + 20 + + + tag_mbist_fail + 19 + 19 + + + hsram_cache_mbist_fail + 18 + 18 + + + hsram_mem_mbist_fail + 17 + 17 + + + irom_mbist_fail + 16 + 16 + + + em_ram_mbist_done + 5 + 5 + + + ocram_mbist_done + 4 + 4 + + + tag_mbist_done + 3 + 3 + + + hsram_cache_mbist_done + 2 + 2 + + + hsram_mem_mbist_done + 1 + 1 + + + irom_mbist_done + 0 + 0 + + + + + bmx_cfg1 + bmx_cfg1. + 0x50 + + + hbn_apb_cfg + 24 + 31 + + + pds_apb_cfg + 16 + 23 + + + hsel_option + 12 + 15 + + + bmx_gating_dis + 10 + 10 + + + bmx_busy_option_dis + 9 + 9 + + + bmx_err_en + 8 + 8 + + + bmx_arb_mode + 4 + 5 + + + bmx_timeout_en + 0 + 3 + + + + + bmx_cfg2 + bmx_cfg2. + 0x54 + + + bmx_dbg_sel + 28 + 31 + + + reg_w_thre_l1c + 10 + 11 + + + reg_w_thre_bmx + 8 + 9 + + + bmx_err_tz + 5 + 5 + + + bmx_err_dec + 4 + 4 + + + bmx_err_addr_dis + 0 + 0 + + + + + bmx_err_addr + bmx_err_addr. + 0x58 + + + bmx_err_addr + 0 + 31 + + + + + bmx_dbg_out + bmx_dbg_out. + 0x5C + + + bmx_dbg_out + 0 + 31 + + + + + rsv0 + rsv0. + 0x60 + + + rsvd_31_0 + 0 + 31 + + + + + rsv1 + rsv1. + 0x64 + + + rsvd_31_0 + 0 + 31 + + + + + rsv2 + rsv2. + 0x68 + + + rsvd_31_0 + 0 + 31 + + + + + rsv3 + rsv3. + 0x6C + + + rsvd_31_0 + 0 + 31 + + + + + sram_ret + sram_ret. + 0x70 + + + reg_sram_ret + 0 + 31 + + + + + sram_slp + sram_slp. + 0x74 + + + reg_sram_slp + 0 + 31 + + + + + sram_parm + sram_parm. + 0x78 + + + reg_sram_parm + 0 + 31 + + + + + seam_misc + seam_misc. + 0x7C + + + em_sel + 0 + 3 + + + + + glb_parm + glb_parm. + 0x80 + + + pin_sel_emac_cam + 31 + 31 + + + reg_ext_rst_smt + 30 + 30 + + + reg_kys_drv_val + 29 + 29 + + + uart_swap_set + 24 + 27 + + + p6_jtag_use_io_0_2_7 + 23 + 23 + + + p5_dac_test_with_jtag + 21 + 21 + + + p4_adc_test_with_jtag + 20 + 20 + + + p3_cci_use_io_0_2_7 + 19 + 19 + + + p2_dac_test_with_cci + 18 + 18 + + + p1_adc_test_with_cci + 17 + 17 + + + reg_cci_use_jtag_pin + 16 + 16 + + + reg_spi_0_swap + 13 + 13 + + + reg_spi_0_master_mode + 12 + 12 + + + cfg_flash_scenario + 10 + 11 + + + cfg_sflash2_swap_cs_io2 + 9 + 9 + + + cfg_sflash2_swap_io0_io3 + 8 + 8 + + + jtag_swap_set + 0 + 7 + + + + + PDM_CLK_CTRL + PDM_CLK_CTRL. + 0x84 + + + reg_pdm0_clk_en + 7 + 7 + + + reg_pdm0_clk_div + 0 + 5 + + + + + GPIO_USE_PSRAM__IO + GPIO_USE_PSRAM__IO. + 0x88 + + + cfg_gpio_use_psram_io + 0 + 5 + + + + + CPU_CLK_CFG + CPU_CLK_CFG. + 0x90 + + + debug_ndreset_gate + 20 + 20 + + + cpu_rtc_sel + 19 + 19 + + + cpu_rtc_en + 18 + 18 + + + cpu_rtc_div + 0 + 16 + + + + + GPADC_32M_SRC_CTRL + GPADC_32M_SRC_CTRL. + 0xA4 + + + gpadc_32m_div_en + 8 + 8 + + + gpadc_32m_clk_sel + 7 + 7 + + + gpadc_32m_clk_div + 0 + 5 + + + + + DIG32K_WAKEUP_CTRL + DIG32K_WAKEUP_CTRL. + 0xA8 + + + reg_en_platform_wakeup + 31 + 31 + + + dig_clk_src_sel + 28 + 29 + + + dig_512k_comp + 25 + 25 + + + dig_512k_en + 24 + 24 + + + dig_512k_div + 16 + 22 + + + dig_32k_comp + 13 + 13 + + + dig_32k_en + 12 + 12 + + + dig_32k_div + 0 + 10 + + + + + WIFI_BT_COEX_CTRL + WIFI_BT_COEX_CTRL. + 0xAC + + + en_gpio_bt_coex + 12 + 12 + + + coex_bt_bw + 11 + 11 + + + coex_bt_pti + 7 + 10 + + + coex_bt_channel + 0 + 6 + + + + + BZ_COEX_CTRL + BZ_COEX_CTRL. + 0xB0 + + + coex_arb + 28 + 31 + + + ble_tx_abort_dis + 27 + 27 + + + ble_rx_abort_dis + 26 + 26 + + + m154_tx_abort_dis + 25 + 25 + + + m154_rx_abort_dis + 24 + 24 + + + coex_force_ch + 16 + 22 + + + coex_option + 15 + 15 + + + force_ble_win + 14 + 14 + + + force_m154_win + 13 + 13 + + + coex_pri + 12 + 12 + + + bz_abort_pol + 11 + 11 + + + bz_active_pol + 10 + 10 + + + bz_pri_pol + 9 + 9 + + + bz_pri_en + 8 + 8 + + + bz_pri_thr + 4 + 7 + + + m154_rx_ignore + 3 + 3 + + + ble_rx_ignore + 2 + 2 + + + wlan_en + 1 + 1 + + + coex_en + 0 + 0 + + + + + UART_SIG_SEL_0 + UART_SIG_SEL_0. + 0xC0 + + + uart_sig_7_sel + 28 + 31 + + + uart_sig_6_sel + 24 + 27 + + + uart_sig_5_sel + 20 + 23 + + + uart_sig_4_sel + 16 + 19 + + + uart_sig_3_sel + 12 + 15 + + + uart_sig_2_sel + 8 + 11 + + + uart_sig_1_sel + 4 + 7 + + + uart_sig_0_sel + 0 + 3 + + + + + DBG_SEL_LL + DBG_SEL_LL. + 0xD0 + + + reg_dbg_ll_ctrl + 0 + 31 + + + + + DBG_SEL_LH + DBG_SEL_LH. + 0xD4 + + + reg_dbg_lh_ctrl + 0 + 31 + + + + + DBG_SEL_HL + DBG_SEL_HL. + 0xD8 + + + reg_dbg_hl_ctrl + 0 + 31 + + + + + DBG_SEL_HH + DBG_SEL_HH. + 0xDC + + + reg_dbg_hh_ctrl + 0 + 31 + + + + + debug + debug. + 0xE0 + + + debug_i + 1 + 31 + + + debug_oe + 0 + 0 + + + + + GPIO_CFGCTL0 + GPIO_CFGCTL0. + 0x100 + + + reg_gpio_1_func_sel + 24 + 28 + + + reg_gpio_1_pd + 21 + 21 + + + reg_gpio_1_pu + 20 + 20 + + + reg_gpio_1_drv + 18 + 19 + + + reg_gpio_1_smt + 17 + 17 + + + reg_gpio_1_ie + 16 + 16 + + + reg_gpio_0_func_sel + 8 + 12 + + + reg_gpio_0_pd + 5 + 5 + + + reg_gpio_0_pu + 4 + 4 + + + reg_gpio_0_drv + 2 + 3 + + + reg_gpio_0_smt + 1 + 1 + + + reg_gpio_0_ie + 0 + 0 + + + + + GPIO_CFGCTL1 + GPIO_CFGCTL1. + 0x104 + + + reg_gpio_3_func_sel + 24 + 28 + + + reg_gpio_3_pd + 21 + 21 + + + reg_gpio_3_pu + 20 + 20 + + + reg_gpio_3_drv + 18 + 19 + + + reg_gpio_3_smt + 17 + 17 + + + reg_gpio_3_ie + 16 + 16 + + + reg_gpio_2_func_sel + 8 + 12 + + + reg_gpio_2_pd + 5 + 5 + + + reg_gpio_2_pu + 4 + 4 + + + reg_gpio_2_drv + 2 + 3 + + + reg_gpio_2_smt + 1 + 1 + + + reg_gpio_2_ie + 0 + 0 + + + + + GPIO_CFGCTL2 + GPIO_CFGCTL2. + 0x108 + + + reg_gpio_5_func_sel + 24 + 28 + + + reg_gpio_5_pd + 21 + 21 + + + reg_gpio_5_pu + 20 + 20 + + + reg_gpio_5_drv + 18 + 19 + + + reg_gpio_5_smt + 17 + 17 + + + reg_gpio_5_ie + 16 + 16 + + + reg_gpio_4_func_sel + 8 + 12 + + + reg_gpio_4_pd + 5 + 5 + + + reg_gpio_4_pu + 4 + 4 + + + reg_gpio_4_drv + 2 + 3 + + + reg_gpio_4_smt + 1 + 1 + + + reg_gpio_4_ie + 0 + 0 + + + + + GPIO_CFGCTL3 + GPIO_CFGCTL3. + 0x10C + + + reg_gpio_7_func_sel + 24 + 28 + + + reg_gpio_7_pd + 21 + 21 + + + reg_gpio_7_pu + 20 + 20 + + + reg_gpio_7_drv + 18 + 19 + + + reg_gpio_7_smt + 17 + 17 + + + reg_gpio_7_ie + 16 + 16 + + + reg_gpio_6_func_sel + 8 + 12 + + + reg_gpio_6_pd + 5 + 5 + + + reg_gpio_6_pu + 4 + 4 + + + reg_gpio_6_drv + 2 + 3 + + + reg_gpio_6_smt + 1 + 1 + + + reg_gpio_6_ie + 0 + 0 + + + + + GPIO_CFGCTL4 + GPIO_CFGCTL4. + 0x110 + + + reg_gpio_9_func_sel + 24 + 28 + + + reg_gpio_9_pd + 21 + 21 + + + reg_gpio_9_pu + 20 + 20 + + + reg_gpio_9_drv + 18 + 19 + + + reg_gpio_9_smt + 17 + 17 + + + reg_gpio_9_ie + 16 + 16 + + + reg_gpio_8_func_sel + 8 + 12 + + + reg_gpio_8_pd + 5 + 5 + + + reg_gpio_8_pu + 4 + 4 + + + reg_gpio_8_drv + 2 + 3 + + + reg_gpio_8_smt + 1 + 1 + + + reg_gpio_8_ie + 0 + 0 + + + + + GPIO_CFGCTL5 + GPIO_CFGCTL5. + 0x114 + + + reg_gpio_11_func_sel + 24 + 28 + + + reg_gpio_11_pd + 21 + 21 + + + reg_gpio_11_pu + 20 + 20 + + + reg_gpio_11_drv + 18 + 19 + + + reg_gpio_11_smt + 17 + 17 + + + reg_gpio_11_ie + 16 + 16 + + + reg_gpio_10_func_sel + 8 + 12 + + + reg_gpio_10_pd + 5 + 5 + + + reg_gpio_10_pu + 4 + 4 + + + reg_gpio_10_drv + 2 + 3 + + + reg_gpio_10_smt + 1 + 1 + + + reg_gpio_10_ie + 0 + 0 + + + + + GPIO_CFGCTL6 + GPIO_CFGCTL6. + 0x118 + + + reg_gpio_13_func_sel + 24 + 28 + + + reg_gpio_13_pd + 21 + 21 + + + reg_gpio_13_pu + 20 + 20 + + + reg_gpio_13_drv + 18 + 19 + + + reg_gpio_13_smt + 17 + 17 + + + reg_gpio_13_ie + 16 + 16 + + + reg_gpio_12_func_sel + 8 + 12 + + + reg_gpio_12_pd + 5 + 5 + + + reg_gpio_12_pu + 4 + 4 + + + reg_gpio_12_drv + 2 + 3 + + + reg_gpio_12_smt + 1 + 1 + + + reg_gpio_12_ie + 0 + 0 + + + + + GPIO_CFGCTL7 + GPIO_CFGCTL7. + 0x11C + + + reg_gpio_15_func_sel + 24 + 28 + + + reg_gpio_15_pd + 21 + 21 + + + reg_gpio_15_pu + 20 + 20 + + + reg_gpio_15_drv + 18 + 19 + + + reg_gpio_15_smt + 17 + 17 + + + reg_gpio_15_ie + 16 + 16 + + + reg_gpio_14_func_sel + 8 + 12 + + + reg_gpio_14_pd + 5 + 5 + + + reg_gpio_14_pu + 4 + 4 + + + reg_gpio_14_drv + 2 + 3 + + + reg_gpio_14_smt + 1 + 1 + + + reg_gpio_14_ie + 0 + 0 + + + + + GPIO_CFGCTL8 + GPIO_CFGCTL8. + 0x120 + + + reg_gpio_17_func_sel + 24 + 28 + + + reg_gpio_17_pd + 21 + 21 + + + reg_gpio_17_pu + 20 + 20 + + + reg_gpio_17_drv + 18 + 19 + + + reg_gpio_17_smt + 17 + 17 + + + reg_gpio_17_ie + 16 + 16 + + + reg_gpio_16_func_sel + 8 + 12 + + + reg_gpio_16_pd + 5 + 5 + + + reg_gpio_16_pu + 4 + 4 + + + reg_gpio_16_drv + 2 + 3 + + + reg_gpio_16_smt + 1 + 1 + + + reg_gpio_16_ie + 0 + 0 + + + + + GPIO_CFGCTL9 + GPIO_CFGCTL9. + 0x124 + + + reg_gpio_19_func_sel + 24 + 28 + + + reg_gpio_19_pd + 21 + 21 + + + reg_gpio_19_pu + 20 + 20 + + + reg_gpio_19_drv + 18 + 19 + + + reg_gpio_19_smt + 17 + 17 + + + reg_gpio_19_ie + 16 + 16 + + + reg_gpio_18_func_sel + 8 + 12 + + + reg_gpio_18_pd + 5 + 5 + + + reg_gpio_18_pu + 4 + 4 + + + reg_gpio_18_drv + 2 + 3 + + + reg_gpio_18_smt + 1 + 1 + + + reg_gpio_18_ie + 0 + 0 + + + + + GPIO_CFGCTL10 + GPIO_CFGCTL10. + 0x128 + + + reg_gpio_21_func_sel + 24 + 28 + + + reg_gpio_21_pd + 21 + 21 + + + reg_gpio_21_pu + 20 + 20 + + + reg_gpio_21_drv + 18 + 19 + + + reg_gpio_21_smt + 17 + 17 + + + reg_gpio_21_ie + 16 + 16 + + + reg_gpio_20_func_sel + 8 + 12 + + + reg_gpio_20_pd + 5 + 5 + + + reg_gpio_20_pu + 4 + 4 + + + reg_gpio_20_drv + 2 + 3 + + + reg_gpio_20_smt + 1 + 1 + + + reg_gpio_20_ie + 0 + 0 + + + + + GPIO_CFGCTL11 + GPIO_CFGCTL11. + 0x12C + + + reg_gpio_23_func_sel + 24 + 28 + + + reg_gpio_23_pd + 21 + 21 + + + reg_gpio_23_pu + 20 + 20 + + + reg_gpio_23_drv + 18 + 19 + + + reg_gpio_23_smt + 17 + 17 + + + reg_gpio_23_ie + 16 + 16 + + + reg_gpio_22_func_sel + 8 + 12 + + + reg_gpio_22_pd + 5 + 5 + + + reg_gpio_22_pu + 4 + 4 + + + reg_gpio_22_drv + 2 + 3 + + + reg_gpio_22_smt + 1 + 1 + + + reg_gpio_22_ie + 0 + 0 + + + + + GPIO_CFGCTL12 + GPIO_CFGCTL12. + 0x130 + + + reg_gpio_25_func_sel + 24 + 28 + + + reg_gpio_25_pd + 21 + 21 + + + reg_gpio_25_pu + 20 + 20 + + + reg_gpio_25_drv + 18 + 19 + + + reg_gpio_25_smt + 17 + 17 + + + reg_gpio_25_ie + 16 + 16 + + + reg_gpio_24_func_sel + 8 + 12 + + + reg_gpio_24_pd + 5 + 5 + + + reg_gpio_24_pu + 4 + 4 + + + reg_gpio_24_drv + 2 + 3 + + + reg_gpio_24_smt + 1 + 1 + + + reg_gpio_24_ie + 0 + 0 + + + + + GPIO_CFGCTL13 + GPIO_CFGCTL13. + 0x134 + + + reg_gpio_27_func_sel + 24 + 28 + + + reg_gpio_27_pd + 21 + 21 + + + reg_gpio_27_pu + 20 + 20 + + + reg_gpio_27_drv + 18 + 19 + + + reg_gpio_27_smt + 17 + 17 + + + reg_gpio_27_ie + 16 + 16 + + + reg_gpio_26_func_sel + 8 + 12 + + + reg_gpio_26_pd + 5 + 5 + + + reg_gpio_26_pu + 4 + 4 + + + reg_gpio_26_drv + 2 + 3 + + + reg_gpio_26_smt + 1 + 1 + + + reg_gpio_26_ie + 0 + 0 + + + + + GPIO_CFGCTL14 + GPIO_CFGCTL14. + 0x138 + + + reg_gpio_29_func_sel + 24 + 28 + + + reg_gpio_29_pd + 21 + 21 + + + reg_gpio_29_pu + 20 + 20 + + + reg_gpio_29_drv + 18 + 19 + + + reg_gpio_29_smt + 17 + 17 + + + reg_gpio_29_ie + 16 + 16 + + + reg_gpio_28_func_sel + 8 + 12 + + + reg_gpio_28_pd + 5 + 5 + + + reg_gpio_28_pu + 4 + 4 + + + reg_gpio_28_drv + 2 + 3 + + + reg_gpio_28_smt + 1 + 1 + + + reg_gpio_28_ie + 0 + 0 + + + + + GPIO_CFGCTL15 + GPIO_CFGCTL15. + 0x13C + + + reg_gpio_31_func_sel + 24 + 28 + + + reg_gpio_31_pd + 21 + 21 + + + reg_gpio_31_pu + 20 + 20 + + + reg_gpio_31_drv + 18 + 19 + + + reg_gpio_31_smt + 17 + 17 + + + reg_gpio_31_ie + 16 + 16 + + + reg_gpio_30_func_sel + 8 + 12 + + + reg_gpio_30_pd + 5 + 5 + + + reg_gpio_30_pu + 4 + 4 + + + reg_gpio_30_drv + 2 + 3 + + + reg_gpio_30_smt + 1 + 1 + + + reg_gpio_30_ie + 0 + 0 + + + + + GPIO_CFGCTL16 + GPIO_CFGCTL16. + 0x140 + + + reg_gpio_33_pd + 21 + 21 + + + reg_gpio_33_pu + 20 + 20 + + + reg_gpio_33_drv + 18 + 19 + + + reg_gpio_33_smt + 17 + 17 + + + reg_gpio_33_ie + 16 + 16 + + + reg_gpio_32_pd + 5 + 5 + + + reg_gpio_32_pu + 4 + 4 + + + reg_gpio_32_drv + 2 + 3 + + + reg_gpio_32_smt + 1 + 1 + + + reg_gpio_32_ie + 0 + 0 + + + + + GPIO_CFGCTL17 + GPIO_CFGCTL17. + 0x144 + + + reg_gpio_35_pd + 21 + 21 + + + reg_gpio_35_pu + 20 + 20 + + + reg_gpio_35_drv + 18 + 19 + + + reg_gpio_35_smt + 17 + 17 + + + reg_gpio_35_ie + 16 + 16 + + + reg_gpio_34_pd + 5 + 5 + + + reg_gpio_34_pu + 4 + 4 + + + reg_gpio_34_drv + 2 + 3 + + + reg_gpio_34_smt + 1 + 1 + + + reg_gpio_34_ie + 0 + 0 + + + + + GPIO_CFGCTL18 + GPIO_CFGCTL18. + 0x148 + + + reg_gpio_37_pd + 21 + 21 + + + reg_gpio_37_pu + 20 + 20 + + + reg_gpio_37_drv + 18 + 19 + + + reg_gpio_37_smt + 17 + 17 + + + reg_gpio_37_ie + 16 + 16 + + + reg_gpio_36_pd + 5 + 5 + + + reg_gpio_36_pu + 4 + 4 + + + reg_gpio_36_drv + 2 + 3 + + + reg_gpio_36_smt + 1 + 1 + + + reg_gpio_36_ie + 0 + 0 + + + + + GPIO_CFGCTL30 + GPIO_CFGCTL30. + 0x180 + + + reg_gpio_31_i + 31 + 31 + + + reg_gpio_30_i + 30 + 30 + + + reg_gpio_29_i + 29 + 29 + + + reg_gpio_28_i + 28 + 28 + + + reg_gpio_27_i + 27 + 27 + + + reg_gpio_26_i + 26 + 26 + + + reg_gpio_25_i + 25 + 25 + + + reg_gpio_24_i + 24 + 24 + + + reg_gpio_23_i + 23 + 23 + + + reg_gpio_22_i + 22 + 22 + + + reg_gpio_21_i + 21 + 21 + + + reg_gpio_20_i + 20 + 20 + + + reg_gpio_19_i + 19 + 19 + + + reg_gpio_18_i + 18 + 18 + + + reg_gpio_17_i + 17 + 17 + + + reg_gpio_16_i + 16 + 16 + + + reg_gpio_15_i + 15 + 15 + + + reg_gpio_14_i + 14 + 14 + + + reg_gpio_13_i + 13 + 13 + + + reg_gpio_12_i + 12 + 12 + + + reg_gpio_11_i + 11 + 11 + + + reg_gpio_10_i + 10 + 10 + + + reg_gpio_9_i + 9 + 9 + + + reg_gpio_8_i + 8 + 8 + + + reg_gpio_7_i + 7 + 7 + + + reg_gpio_6_i + 6 + 6 + + + reg_gpio_5_i + 5 + 5 + + + reg_gpio_4_i + 4 + 4 + + + reg_gpio_3_i + 3 + 3 + + + reg_gpio_2_i + 2 + 2 + + + reg_gpio_1_i + 1 + 1 + + + reg_gpio_0_i + 0 + 0 + + + + + GPIO_CFGCTL31 + GPIO_CFGCTL31. + 0x184 + + + + GPIO_CFGCTL32 + GPIO_CFGCTL32. + 0x188 + + + reg_gpio_31_o + 31 + 31 + + + reg_gpio_30_o + 30 + 30 + + + reg_gpio_29_o + 29 + 29 + + + reg_gpio_28_o + 28 + 28 + + + reg_gpio_27_o + 27 + 27 + + + reg_gpio_26_o + 26 + 26 + + + reg_gpio_25_o + 25 + 25 + + + reg_gpio_24_o + 24 + 24 + + + reg_gpio_23_o + 23 + 23 + + + reg_gpio_22_o + 22 + 22 + + + reg_gpio_21_o + 21 + 21 + + + reg_gpio_20_o + 20 + 20 + + + reg_gpio_19_o + 19 + 19 + + + reg_gpio_18_o + 18 + 18 + + + reg_gpio_17_o + 17 + 17 + + + reg_gpio_16_o + 16 + 16 + + + reg_gpio_15_o + 15 + 15 + + + reg_gpio_14_o + 14 + 14 + + + reg_gpio_13_o + 13 + 13 + + + reg_gpio_12_o + 12 + 12 + + + reg_gpio_11_o + 11 + 11 + + + reg_gpio_10_o + 10 + 10 + + + reg_gpio_9_o + 9 + 9 + + + reg_gpio_8_o + 8 + 8 + + + reg_gpio_7_o + 7 + 7 + + + reg_gpio_6_o + 6 + 6 + + + reg_gpio_5_o + 5 + 5 + + + reg_gpio_4_o + 4 + 4 + + + reg_gpio_3_o + 3 + 3 + + + reg_gpio_2_o + 2 + 2 + + + reg_gpio_1_o + 1 + 1 + + + reg_gpio_0_o + 0 + 0 + + + + + GPIO_CFGCTL33 + GPIO_CFGCTL33. + 0x18C + + + + GPIO_CFGCTL34 + GPIO_CFGCTL34. + 0x190 + + + reg_gpio_31_oe + 31 + 31 + + + reg_gpio_30_oe + 30 + 30 + + + reg_gpio_29_oe + 29 + 29 + + + reg_gpio_28_oe + 28 + 28 + + + reg_gpio_27_oe + 27 + 27 + + + reg_gpio_26_oe + 26 + 26 + + + reg_gpio_25_oe + 25 + 25 + + + reg_gpio_24_oe + 24 + 24 + + + reg_gpio_23_oe + 23 + 23 + + + reg_gpio_22_oe + 22 + 22 + + + reg_gpio_21_oe + 21 + 21 + + + reg_gpio_20_oe + 20 + 20 + + + reg_gpio_19_oe + 19 + 19 + + + reg_gpio_18_oe + 18 + 18 + + + reg_gpio_17_oe + 17 + 17 + + + reg_gpio_16_oe + 16 + 16 + + + reg_gpio_15_oe + 15 + 15 + + + reg_gpio_14_oe + 14 + 14 + + + reg_gpio_13_oe + 13 + 13 + + + reg_gpio_12_oe + 12 + 12 + + + reg_gpio_11_oe + 11 + 11 + + + reg_gpio_10_oe + 10 + 10 + + + reg_gpio_9_oe + 9 + 9 + + + reg_gpio_8_oe + 8 + 8 + + + reg_gpio_7_oe + 7 + 7 + + + reg_gpio_6_oe + 6 + 6 + + + reg_gpio_5_oe + 5 + 5 + + + reg_gpio_4_oe + 4 + 4 + + + reg_gpio_3_oe + 3 + 3 + + + reg_gpio_2_oe + 2 + 2 + + + reg_gpio_1_oe + 1 + 1 + + + reg_gpio_0_oe + 0 + 0 + + + + + GPIO_CFGCTL35 + GPIO_CFGCTL35. + 0x194 + + + + GPIO_INT_MASK1 + GPIO_INT_MASK1. + 0x1A0 + + + reg_gpio_int_mask1 + 0 + 31 + + + + + GPIO_INT_STAT1 + GPIO_INT_STAT1. + 0x1A8 + + + gpio_int_stat1 + 0 + 31 + + + + + GPIO_INT_CLR1 + GPIO_INT_CLR1. + 0x1B0 + + + reg_gpio_int_clr1 + 0 + 31 + + + + + GPIO_INT_MODE_SET1 + GPIO_INT_MODE_SET1. + 0x1C0 + + + reg_gpio_int_mode_set1 + 0 + 29 + + + + + GPIO_INT_MODE_SET2 + GPIO_INT_MODE_SET2. + 0x1C4 + + + reg_gpio_int_mode_set2 + 0 + 29 + + + + + GPIO_INT_MODE_SET3 + GPIO_INT_MODE_SET3. + 0x1C8 + + + reg_gpio_int_mode_set3 + 0 + 29 + + + + + GPIO_INT_MODE_SET4 + GPIO_INT_MODE_SET4. + 0x1CC + + + reg_gpio_int_mode_set4 + 0 + 5 + + + + + GPIO_INT2_MASK1 + GPIO_INT2_MASK1. + 0x1D0 + + + reg_gpio_int2_mask1 + 0 + 31 + + + + + GPIO_INT2_STAT1 + GPIO_INT2_STAT1. + 0x1D4 + + + gpio_int2_stat1 + 0 + 31 + + + + + GPIO_INT2_CLR1 + GPIO_INT2_CLR1. + 0x1D8 + + + reg_gpio_int2_clr1 + 0 + 31 + + + + + GPIO_INT2_MODE_SET1 + GPIO_INT2_MODE_SET1. + 0x1DC + + + reg_gpio_int2_mode_set1 + 0 + 29 + + + + + GPIO_INT2_MODE_SET2 + GPIO_INT2_MODE_SET2. + 0x1E0 + + + reg_gpio_int2_mode_set2 + 0 + 29 + + + + + GPIO_INT2_MODE_SET3 + GPIO_INT2_MODE_SET3. + 0x1E4 + + + reg_gpio_int2_mode_set3 + 0 + 29 + + + + + GPIO_INT2_MODE_SET4 + GPIO_INT2_MODE_SET4. + 0x1E8 + + + reg_gpio_int2_mode_set4 + 0 + 5 + + + + + dll + dll. + 0x200 + + + ppu_dll + 31 + 31 + + + pu_dll + 30 + 30 + + + dll_reset + 29 + 29 + + + dll_refclk_sel + 28 + 28 + + + dll_cp_hiz + 23 + 23 + + + dll_cp_op_en + 22 + 22 + + + dll_delay_sel + 20 + 21 + + + dll_post_div + 16 + 19 + + + dll_vctrl_force_en + 15 + 15 + + + dll_prechg_en + 14 + 14 + + + dll_prechg_reg + 13 + 13 + + + dll_prechg_sel + 12 + 12 + + + dll_vctrl_sel + 8 + 10 + + + dll_clk_57p6M_en + 7 + 7 + + + dll_clk_96M_en + 6 + 6 + + + dll_clk_144M_en + 5 + 5 + + + dll_clk_288M_en + 4 + 4 + + + dll_clk_mmdiv_en + 3 + 3 + + + ten_dll + 2 + 2 + + + dtest_en_dll_outclk + 1 + 1 + + + dtest_en_dll_refclk + 0 + 0 + + + + + led_driver + led_driver. + 0x224 + + + pu_leddrv + 31 + 31 + + + leddrv_out_en + 28 + 29 + + + ir_rx_gpio_sel + 8 + 11 + + + leddrv_ibias + 4 + 7 + + + led_din_polarity_sel + 2 + 2 + + + led_din_sel + 1 + 1 + + + led_din_reg + 0 + 0 + + + + + usb_xcvr + usb_xcvr. + 0x228 + + + usb_rcv + 27 + 27 + + + usb_vip + 26 + 26 + + + usb_vim + 25 + 25 + + + usb_bd + 24 + 24 + + + pu_usb + 23 + 23 + + + usb_sus + 22 + 22 + + + usb_spd + 21 + 21 + + + usb_enum + 20 + 20 + + + usb_data_convert + 16 + 16 + + + usb_oeb + 14 + 14 + + + usb_oeb_reg + 13 + 13 + + + usb_oeb_sel + 12 + 12 + + + usb_rout_pmos + 8 + 10 + + + usb_rout_nmos + 4 + 6 + + + pu_usb_ldo + 3 + 3 + + + usb_ldo_vfb + 0 + 2 + + + + + usb_xcvr_config + usb_xcvr_config. + 0x22C + + + usb_slewrate_p_rise + 28 + 30 + + + usb_slewrate_p_fall + 24 + 26 + + + usb_slewrate_m_rise + 20 + 22 + + + usb_slewrate_m_fall + 16 + 18 + + + usb_res_pullup_tune + 12 + 14 + + + reg_usb_use_ctrl + 11 + 11 + + + usb_str_drv + 8 + 10 + + + reg_usb_use_xcvr + 7 + 7 + + + usb_bd_vth + 4 + 6 + + + usb_v_hys_p + 2 + 3 + + + usb_v_hys_m + 0 + 1 + + + + + gpdac_ctrl + gpdac_ctrl. + 0x308 + + + gpdac_reserved + 24 + 31 + + + gpdac_test_sel + 9 + 11 + + + gpdac_ref_sel + 8 + 8 + + + gpdac_test_en + 7 + 7 + + + gpdacb_rstn_ana + 1 + 1 + + + gpdaca_rstn_ana + 0 + 0 + + + + + gpdac_actrl + gpdac_actrl. + 0x30C + + + gpdac_a_outmux + 20 + 22 + + + gpdac_a_rng + 18 + 19 + + + gpdac_ioa_en + 1 + 1 + + + gpdac_a_en + 0 + 0 + + + + + gpdac_bctrl + gpdac_bctrl. + 0x310 + + + gpdac_b_outmux + 20 + 22 + + + gpdac_b_rng + 18 + 19 + + + gpdac_iob_en + 1 + 1 + + + gpdac_b_en + 0 + 0 + + + + + gpdac_data + gpdac_data. + 0x314 + + + gpdac_a_data + 16 + 25 + + + gpdac_b_data + 0 + 9 + + + + + chip_revision + chip_revision. + 0xE00 + + + chip_rev + 0 + 3 + + + + + tzc_glb_ctrl_0 + tzc_glb_ctrl_0. + 0xF00 + + + tzc_glb_clk_lock + 31 + 31 + + + tzc_glb_mbist_lock + 30 + 30 + + + tzc_glb_dbg_lock + 29 + 29 + + + tzc_glb_bmx_lock + 28 + 28 + + + tzc_glb_l2c_lock + 27 + 27 + + + tzc_glb_sram_lock + 26 + 26 + + + tzc_glb_misc_lock + 25 + 25 + + + tzc_glb_ctrl_ungated_ap_lock + 15 + 15 + + + tzc_glb_ctrl_sys_reset_lock + 14 + 14 + + + tzc_glb_ctrl_cpu_reset_lock + 13 + 13 + + + tzc_glb_ctrl_pwron_rst_lock + 12 + 12 + + + tzc_glb_swrst_s30_lock + 8 + 8 + + + tzc_glb_swrst_s01_lock + 1 + 1 + + + tzc_glb_swrst_s00_lock + 0 + 0 + + + + + tzc_glb_ctrl_1 + tzc_glb_ctrl_1. + 0xF04 + + + tzc_glb_swrst_s1f_lock + 31 + 31 + + + tzc_glb_swrst_s1e_lock + 30 + 30 + + + tzc_glb_swrst_s1d_lock + 29 + 29 + + + tzc_glb_swrst_s1c_lock + 28 + 28 + + + tzc_glb_swrst_s1b_lock + 27 + 27 + + + tzc_glb_swrst_s1a_lock + 26 + 26 + + + tzc_glb_swrst_s19_lock + 25 + 25 + + + tzc_glb_swrst_s18_lock + 24 + 24 + + + tzc_glb_swrst_s17_lock + 23 + 23 + + + tzc_glb_swrst_s16_lock + 22 + 22 + + + tzc_glb_swrst_s15_lock + 21 + 21 + + + tzc_glb_swrst_s14_lock + 20 + 20 + + + tzc_glb_swrst_s13_lock + 19 + 19 + + + tzc_glb_swrst_s12_lock + 18 + 18 + + + tzc_glb_swrst_s11_lock + 17 + 17 + + + tzc_glb_swrst_s10_lock + 16 + 16 + + + tzc_glb_swrst_s2f_lock + 15 + 15 + + + tzc_glb_swrst_s2e_lock + 14 + 14 + + + tzc_glb_swrst_s2d_lock + 13 + 13 + + + tzc_glb_swrst_s2c_lock + 12 + 12 + + + tzc_glb_swrst_s2b_lock + 11 + 11 + + + tzc_glb_swrst_s2a_lock + 10 + 10 + + + tzc_glb_swrst_s29_lock + 9 + 9 + + + tzc_glb_swrst_s28_lock + 8 + 8 + + + tzc_glb_swrst_s27_lock + 7 + 7 + + + tzc_glb_swrst_s26_lock + 6 + 6 + + + tzc_glb_swrst_s25_lock + 5 + 5 + + + tzc_glb_swrst_s24_lock + 4 + 4 + + + tzc_glb_swrst_s23_lock + 3 + 3 + + + tzc_glb_swrst_s22_lock + 2 + 2 + + + tzc_glb_swrst_s21_lock + 1 + 1 + + + tzc_glb_swrst_s20_lock + 0 + 0 + + + + + tzc_glb_ctrl_2 + tzc_glb_ctrl_2. + 0xF08 + + + tzc_glb_gpio_31_lock + 31 + 31 + + + tzc_glb_gpio_30_lock + 30 + 30 + + + tzc_glb_gpio_29_lock + 29 + 29 + + + tzc_glb_gpio_28_lock + 28 + 28 + + + tzc_glb_gpio_27_lock + 27 + 27 + + + tzc_glb_gpio_26_lock + 26 + 26 + + + tzc_glb_gpio_25_lock + 25 + 25 + + + tzc_glb_gpio_24_lock + 24 + 24 + + + tzc_glb_gpio_23_lock + 23 + 23 + + + tzc_glb_gpio_22_lock + 22 + 22 + + + tzc_glb_gpio_21_lock + 21 + 21 + + + tzc_glb_gpio_20_lock + 20 + 20 + + + tzc_glb_gpio_19_lock + 19 + 19 + + + tzc_glb_gpio_18_lock + 18 + 18 + + + tzc_glb_gpio_17_lock + 17 + 17 + + + tzc_glb_gpio_16_lock + 16 + 16 + + + tzc_glb_gpio_15_lock + 15 + 15 + + + tzc_glb_gpio_14_lock + 14 + 14 + + + tzc_glb_gpio_13_lock + 13 + 13 + + + tzc_glb_gpio_12_lock + 12 + 12 + + + tzc_glb_gpio_11_lock + 11 + 11 + + + tzc_glb_gpio_10_lock + 10 + 10 + + + tzc_glb_gpio_9_lock + 9 + 9 + + + tzc_glb_gpio_8_lock + 8 + 8 + + + tzc_glb_gpio_7_lock + 7 + 7 + + + tzc_glb_gpio_6_lock + 6 + 6 + + + tzc_glb_gpio_5_lock + 5 + 5 + + + tzc_glb_gpio_4_lock + 4 + 4 + + + tzc_glb_gpio_3_lock + 3 + 3 + + + tzc_glb_gpio_2_lock + 2 + 2 + + + tzc_glb_gpio_1_lock + 1 + 1 + + + tzc_glb_gpio_0_lock + 0 + 0 + + + + + tzc_glb_ctrl_3 + tzc_glb_ctrl_3. + 0xF0C + + + tzc_glb_gpio_37_lock + 5 + 5 + + + tzc_glb_gpio_36_lock + 4 + 4 + + + tzc_glb_gpio_35_lock + 3 + 3 + + + tzc_glb_gpio_34_lock + 2 + 2 + + + tzc_glb_gpio_33_lock + 1 + 1 + + + tzc_glb_gpio_32_lock + 0 + 0 + + + + + + + gpip + gpip. + 0x40002000 + gpip + 32 + read-write + + 0 + 0x1000 + registers + + + + gpadc_config + gpadc_config. + 0x0 + + + rsvd_31_24 + 24 + 31 + + + gpadc_fifo_thl + 22 + 23 + + + gpadc_fifo_data_count + 16 + 21 + + + gpadc_fifo_rdy_mask + 15 + 15 + + + gpadc_fifo_underrun_mask + 14 + 14 + + + gpadc_fifo_overrun_mask + 13 + 13 + + + gpadc_rdy_mask + 12 + 12 + + + gpadc_fifo_underrun_clr + 10 + 10 + + + gpadc_fifo_overrun_clr + 9 + 9 + + + gpadc_rdy_clr + 8 + 8 + + + gpadc_fifo_rdy + 7 + 7 + + + gpadc_fifo_underrun + 6 + 6 + + + gpadc_fifo_overrun + 5 + 5 + + + gpadc_rdy + 4 + 4 + + + gpadc_fifo_full + 3 + 3 + + + gpadc_fifo_ne + 2 + 2 + + + gpadc_fifo_clr + 1 + 1 + + + gpadc_dma_en + 0 + 0 + + + + + gpadc_dma_rdata + gpadc_dma_rdata. + 0x4 + + + rsvd_31_26 + 26 + 31 + + + gpadc_dma_rdata + 0 + 25 + + + + + gpdac_config + gpdac_config. + 0x40 + + + rsvd_31_24 + 24 + 31 + + + gpdac_ch_b_sel + 20 + 23 + + + gpdac_ch_a_sel + 16 + 19 + + + gpdac_mode + 8 + 10 + + + dsm_mode + 4 + 5 + + + gpdac_en2 + 1 + 1 + + + gpdac_en + 0 + 0 + + + + + gpdac_dma_config + gpdac_dma_config. + 0x44 + + + gpdac_dma_format + 4 + 5 + + + gpdac_dma_tx_en + 0 + 0 + + + + + gpdac_dma_wdata + gpdac_dma_wdata. + 0x48 + + + gpdac_dma_wdata + 0 + 31 + + + + + gpdac_tx_fifo_status + gpdac_tx_fifo_status. + 0x4C + + + TxFifoWrPtr + 8 + 9 + + + TxFifoRdPtr + 4 + 6 + + + tx_cs + 2 + 3 + + + tx_fifo_full + 1 + 1 + + + tx_fifo_empty + 0 + 0 + + + + + + + sec_dbg + sec_dbg. + 0x40003000 + sec_dbg + 32 + read-write + + 0 + 0x1000 + registers + + + + sd_chip_id_low + sd_chip_id_low. + 0x0 + + + sd_chip_id_low + 0 + 31 + + + + + sd_chip_id_high + sd_chip_id_high. + 0x4 + + + sd_chip_id_high + 0 + 31 + + + + + sd_wifi_mac_low + sd_wifi_mac_low. + 0x8 + + + sd_wifi_mac_low + 0 + 31 + + + + + sd_wifi_mac_high + sd_wifi_mac_high. + 0xC + + + sd_wifi_mac_high + 0 + 31 + + + + + sd_dbg_pwd_low + sd_dbg_pwd_low. + 0x10 + + + sd_dbg_pwd_low + 0 + 31 + + + + + sd_dbg_pwd_high + sd_dbg_pwd_high. + 0x14 + + + sd_dbg_pwd_high + 0 + 31 + + + + + sd_status + sd_status. + 0x18 + + + sd_dbg_ena + 28 + 31 + + + sd_dbg_mode + 24 + 27 + + + sd_dbg_pwd_cnt + 4 + 23 + + + sd_dbg_cci_clk_sel + 3 + 3 + + + sd_dbg_cci_read_en + 2 + 2 + + + sd_dbg_pwd_trig + 1 + 1 + + + sd_dbg_pwd_busy + 0 + 0 + + + + + sd_dbg_reserved + sd_dbg_reserved. + 0x1C + + + sd_dbg_reserved + 0 + 31 + + + + + + + sec_eng + sec_eng. + 0x40004000 + sec_eng + 32 + read-write + + 0 + 0x1000 + registers + + + + se_sha_0_ctrl + se_sha_0_ctrl. + 0x0 + + + se_sha_0_msg_len + 16 + 31 + + + se_sha_0_link_mode + 15 + 15 + + + se_sha_0_int_mask + 11 + 11 + + + se_sha_0_int_set_1t + 10 + 10 + + + se_sha_0_int_clr_1t + 9 + 9 + + + se_sha_0_int + 8 + 8 + + + se_sha_0_hash_sel + 6 + 6 + + + se_sha_0_en + 5 + 5 + + + se_sha_0_mode + 2 + 4 + + + se_sha_0_trig_1t + 1 + 1 + + + se_sha_0_busy + 0 + 0 + + + + + se_sha_0_msa + se_sha_0_msa. + 0x4 + + + se_sha_0_msa + 0 + 31 + + + + + se_sha_0_status + se_sha_0_status. + 0x8 + + + se_sha_0_status + 0 + 31 + + + + + se_sha_0_endian + se_sha_0_endian. + 0xC + + + se_sha_0_dout_endian + 0 + 0 + + + + + se_sha_0_hash_l_0 + se_sha_0_hash_l_0. + 0x10 + + + se_sha_0_hash_l_0 + 0 + 31 + + + + + se_sha_0_hash_l_1 + se_sha_0_hash_l_1. + 0x14 + + + se_sha_0_hash_l_1 + 0 + 31 + + + + + se_sha_0_hash_l_2 + se_sha_0_hash_l_2. + 0x18 + + + se_sha_0_hash_l_2 + 0 + 31 + + + + + se_sha_0_hash_l_3 + se_sha_0_hash_l_3. + 0x1C + + + se_sha_0_hash_l_3 + 0 + 31 + + + + + se_sha_0_hash_l_4 + se_sha_0_hash_l_4. + 0x20 + + + se_sha_0_hash_l_4 + 0 + 31 + + + + + se_sha_0_hash_l_5 + se_sha_0_hash_l_5. + 0x24 + + + se_sha_0_hash_l_5 + 0 + 31 + + + + + se_sha_0_hash_l_6 + se_sha_0_hash_l_6. + 0x28 + + + se_sha_0_hash_l_6 + 0 + 31 + + + + + se_sha_0_hash_l_7 + se_sha_0_hash_l_7. + 0x2C + + + se_sha_0_hash_l_7 + 0 + 31 + + + + + se_sha_0_hash_h_0 + se_sha_0_hash_h_0. + 0x30 + + + se_sha_0_hash_h_0 + 0 + 31 + + + + + se_sha_0_hash_h_1 + se_sha_0_hash_h_1. + 0x34 + + + se_sha_0_hash_h_1 + 0 + 31 + + + + + se_sha_0_hash_h_2 + se_sha_0_hash_h_2. + 0x38 + + + se_sha_0_hash_h_2 + 0 + 31 + + + + + se_sha_0_hash_h_3 + se_sha_0_hash_h_3. + 0x3C + + + se_sha_0_hash_h_3 + 0 + 31 + + + + + se_sha_0_hash_h_4 + se_sha_0_hash_h_4. + 0x40 + + + se_sha_0_hash_h_4 + 0 + 31 + + + + + se_sha_0_hash_h_5 + se_sha_0_hash_h_5. + 0x44 + + + se_sha_0_hash_h_5 + 0 + 31 + + + + + se_sha_0_hash_h_6 + se_sha_0_hash_h_6. + 0x48 + + + se_sha_0_hash_h_6 + 0 + 31 + + + + + se_sha_0_hash_h_7 + se_sha_0_hash_h_7. + 0x4C + + + se_sha_0_hash_h_7 + 0 + 31 + + + + + se_sha_0_link + se_sha_0_link. + 0x50 + + + se_sha_0_lca + 0 + 31 + + + + + se_sha_0_ctrl_prot + se_sha_0_ctrl_prot. + 0xFC + + + se_sha_id1_en + 2 + 2 + + + se_sha_id0_en + 1 + 1 + + + se_sha_prot_en + 0 + 0 + + + + + se_aes_0_ctrl + se_aes_0_ctrl. + 0x100 + + + se_aes_0_msg_len + 16 + 31 + + + se_aes_0_link_mode + 15 + 15 + + + se_aes_0_iv_sel + 14 + 14 + + + se_aes_0_block_mode + 12 + 13 + + + se_aes_0_int_mask + 11 + 11 + + + se_aes_0_int_set_1t + 10 + 10 + + + se_aes_0_int_clr_1t + 9 + 9 + + + se_aes_0_int + 8 + 8 + + + se_aes_0_hw_key_en + 7 + 7 + + + se_aes_0_dec_key_sel + 6 + 6 + + + se_aes_0_dec_en + 5 + 5 + + + se_aes_0_mode + 3 + 4 + + + se_aes_0_en + 2 + 2 + + + se_aes_0_trig_1t + 1 + 1 + + + se_aes_0_busy + 0 + 0 + + + + + se_aes_0_msa + se_aes_0_msa. + 0x104 + + + se_aes_0_msa + 0 + 31 + + + + + se_aes_0_mda + se_aes_0_mda. + 0x108 + + + se_aes_0_mda + 0 + 31 + + + + + se_aes_0_status + se_aes_0_status. + 0x10C + + + se_aes_0_status + 0 + 31 + + + + + se_aes_0_iv_0 + se_aes_0_iv_0. + 0x110 + + + se_aes_0_iv_0 + 0 + 31 + + + + + se_aes_0_iv_1 + se_aes_0_iv_1. + 0x114 + + + se_aes_0_iv_1 + 0 + 31 + + + + + se_aes_0_iv_2 + se_aes_0_iv_2. + 0x118 + + + se_aes_0_iv_2 + 0 + 31 + + + + + se_aes_0_iv_3 + se_aes_0_iv_3. + 0x11C + + + se_aes_0_iv_3 + 0 + 31 + + + + + se_aes_0_key_0 + se_aes_0_key_0. + 0x120 + + + se_aes_0_key_0 + 0 + 31 + + + + + se_aes_0_key_1 + se_aes_0_key_1. + 0x124 + + + se_aes_0_key_1 + 0 + 31 + + + + + se_aes_0_key_2 + se_aes_0_key_2. + 0x128 + + + se_aes_0_key_2 + 0 + 31 + + + + + se_aes_0_key_3 + se_aes_0_key_3. + 0x12C + + + se_aes_0_key_3 + 0 + 31 + + + + + se_aes_0_key_4 + se_aes_0_key_4. + 0x130 + + + se_aes_0_key_4 + 0 + 31 + + + + + se_aes_0_key_5 + se_aes_0_key_5. + 0x134 + + + se_aes_0_key_5 + 0 + 31 + + + + + se_aes_0_key_6 + se_aes_0_key_6. + 0x138 + + + se_aes_0_key_6 + 0 + 31 + + + + + se_aes_0_key_7 + se_aes_0_key_7. + 0x13C + + + se_aes_0_key_7 + 0 + 31 + + + + + se_aes_0_key_sel_0 + se_aes_0_key_sel_0. + 0x140 + + + se_aes_0_key_sel_0 + 0 + 1 + + + + + se_aes_0_key_sel_1 + se_aes_0_key_sel_1. + 0x144 + + + se_aes_0_key_sel_1 + 0 + 1 + + + + + se_aes_0_endian + se_aes_0_endian. + 0x148 + + + se_aes_0_ctr_len + 30 + 31 + + + se_aes_0_iv_endian + 3 + 3 + + + se_aes_0_key_endian + 2 + 2 + + + se_aes_0_din_endian + 1 + 1 + + + se_aes_0_dout_endian + 0 + 0 + + + + + se_aes_0_sboot + se_aes_0_sboot. + 0x14C + + + se_aes_0_sboot_key_sel + 0 + 0 + + + + + se_aes_0_link + se_aes_0_link. + 0x150 + + + se_aes_0_lca + 0 + 31 + + + + + se_aes_0_ctrl_prot + se_aes_0_ctrl_prot. + 0x1FC + + + se_aes_id1_en + 2 + 2 + + + se_aes_id0_en + 1 + 1 + + + se_aes_prot_en + 0 + 0 + + + + + se_trng_0_ctrl_0 + se_trng_0_ctrl_0. + 0x200 + + + se_trng_0_manual_en + 15 + 15 + + + se_trng_0_manual_reseed + 14 + 14 + + + se_trng_0_manual_fun_sel + 13 + 13 + + + se_trng_0_int_mask + 11 + 11 + + + se_trng_0_int_set_1t + 10 + 10 + + + se_trng_0_int_clr_1t + 9 + 9 + + + se_trng_0_int + 8 + 8 + + + se_trng_0_ht_error + 4 + 4 + + + se_trng_0_dout_clr_1t + 3 + 3 + + + se_trng_0_en + 2 + 2 + + + se_trng_0_trig_1t + 1 + 1 + + + se_trng_0_busy + 0 + 0 + + + + + se_trng_0_status + se_trng_0_status. + 0x204 + + + se_trng_0_status + 0 + 31 + + + + + se_trng_0_dout_0 + se_trng_0_dout_0. + 0x208 + + + se_trng_0_dout_0 + 0 + 31 + + + + + se_trng_0_dout_1 + se_trng_0_dout_1. + 0x20C + + + se_trng_0_dout_1 + 0 + 31 + + + + + se_trng_0_dout_2 + se_trng_0_dout_2. + 0x210 + + + se_trng_0_dout_2 + 0 + 31 + + + + + se_trng_0_dout_3 + se_trng_0_dout_3. + 0x214 + + + se_trng_0_dout_3 + 0 + 31 + + + + + se_trng_0_dout_4 + se_trng_0_dout_4. + 0x218 + + + se_trng_0_dout_4 + 0 + 31 + + + + + se_trng_0_dout_5 + se_trng_0_dout_5. + 0x21C + + + se_trng_0_dout_5 + 0 + 31 + + + + + se_trng_0_dout_6 + se_trng_0_dout_6. + 0x220 + + + se_trng_0_dout_6 + 0 + 31 + + + + + se_trng_0_dout_7 + se_trng_0_dout_7. + 0x224 + + + se_trng_0_dout_7 + 0 + 31 + + + + + se_trng_0_test + se_trng_0_test. + 0x228 + + + se_trng_0_ht_alarm_n + 4 + 11 + + + se_trng_0_ht_dis + 3 + 3 + + + se_trng_0_cp_bypass + 2 + 2 + + + se_trng_0_cp_test_en + 1 + 1 + + + se_trng_0_test_en + 0 + 0 + + + + + se_trng_0_ctrl_1 + se_trng_0_ctrl_1. + 0x22C + + + se_trng_0_reseed_n_lsb + 0 + 31 + + + + + se_trng_0_ctrl_2 + se_trng_0_ctrl_2. + 0x230 + + + se_trng_0_reseed_n_msb + 0 + 15 + + + + + se_trng_0_ctrl_3 + se_trng_0_ctrl_3. + 0x234 + + + se_trng_0_rosc_en + 31 + 31 + + + se_trng_0_ht_od_en + 26 + 26 + + + se_trng_0_ht_apt_c + 16 + 25 + + + se_trng_0_ht_rct_c + 8 + 15 + + + se_trng_0_cp_ratio + 0 + 7 + + + + + se_trng_0_test_out_0 + se_trng_0_test_out_0. + 0x240 + + + se_trng_0_test_out_0 + 0 + 31 + + + + + se_trng_0_test_out_1 + se_trng_0_test_out_1. + 0x244 + + + se_trng_0_test_out_1 + 0 + 31 + + + + + se_trng_0_test_out_2 + se_trng_0_test_out_2. + 0x248 + + + se_trng_0_test_out_2 + 0 + 31 + + + + + se_trng_0_test_out_3 + se_trng_0_test_out_3. + 0x24C + + + se_trng_0_test_out_3 + 0 + 31 + + + + + se_trng_0_ctrl_prot + se_trng_0_ctrl_prot. + 0x2FC + + + se_trng_id1_en + 2 + 2 + + + se_trng_id0_en + 1 + 1 + + + se_trng_prot_en + 0 + 0 + + + + + se_pka_0_ctrl_0 + se_pka_0_ctrl_0. + 0x300 + + + se_pka_0_status + 16 + 31 + + + se_pka_0_status_clr_1t + 15 + 15 + + + se_pka_0_ram_clr_md + 13 + 13 + + + se_pka_0_endian + 12 + 12 + + + se_pka_0_int_mask + 11 + 11 + + + se_pka_0_int_set + 10 + 10 + + + se_pka_0_int_clr_1t + 9 + 9 + + + se_pka_0_int + 8 + 8 + + + se_pka_0_prot_md + 4 + 7 + + + se_pka_0_en + 3 + 3 + + + se_pka_0_busy + 2 + 2 + + + se_pka_0_done_clr_1t + 1 + 1 + + + se_pka_0_done + 0 + 0 + + + + + se_pka_0_seed + se_pka_0_seed. + 0x30C + + + se_pka_0_seed + 0 + 31 + + + + + se_pka_0_ctrl_1 + se_pka_0_ctrl_1. + 0x310 + + + se_pka_0_hbypass + 3 + 3 + + + se_pka_0_hburst + 0 + 2 + + + + + se_pka_0_rw + se_pka_0_rw. + 0x340 + + + + se_pka_0_rw_burst + se_pka_0_rw_burst. + 0x360 + + + + se_pka_0_ctrl_prot + se_pka_0_ctrl_prot. + 0x3FC + + + se_pka_id1_en + 2 + 2 + + + se_pka_id0_en + 1 + 1 + + + se_pka_prot_en + 0 + 0 + + + + + se_cdet_0_ctrl_0 + se_cdet_0_ctrl_0. + 0x400 + + + se_cdet_0_g_loop_min + 24 + 31 + + + se_cdet_0_g_loop_max + 16 + 23 + + + se_cdet_0_status + 2 + 15 + + + se_cdet_0_error + 1 + 1 + + + se_cdet_0_en + 0 + 0 + + + + + se_cdet_0_ctrl_1 + se_cdet_0_ctrl_1. + 0x404 + + + se_cdet_0_g_slp_n + 16 + 23 + + + se_cdet_0_t_dly_n + 8 + 15 + + + se_cdet_0_t_loop_n + 0 + 7 + + + + + se_cdet_0_ctrl_prot + se_cdet_0_ctrl_prot. + 0x4FC + + + se_cdet_id1_en + 2 + 2 + + + se_cdet_id0_en + 1 + 1 + + + se_cdet_prot_en + 0 + 0 + + + + + se_gmac_0_ctrl_0 + se_gmac_0_ctrl_0. + 0x500 + + + se_gmac_0_x_endian + 14 + 14 + + + se_gmac_0_h_endian + 13 + 13 + + + se_gmac_0_t_endian + 12 + 12 + + + se_gmac_0_int_mask + 11 + 11 + + + se_gmac_0_int_set_1t + 10 + 10 + + + se_gmac_0_int_clr_1t + 9 + 9 + + + se_gmac_0_int + 8 + 8 + + + se_gmac_0_en + 2 + 2 + + + se_gmac_0_trig_1t + 1 + 1 + + + se_gmac_0_busy + 0 + 0 + + + + + se_gmac_0_lca + se_gmac_0_lca. + 0x504 + + + se_gmac_0_lca + 0 + 31 + + + + + se_gmac_0_status + se_gmac_0_status. + 0x508 + + + se_gmac_0_status + 0 + 31 + + + + + se_gmac_0_ctrl_prot + se_gmac_0_ctrl_prot. + 0x5FC + + + se_gmac_id1_en + 2 + 2 + + + se_gmac_id0_en + 1 + 1 + + + se_gmac_prot_en + 0 + 0 + + + + + se_ctrl_prot_rd + se_ctrl_prot_rd. + 0xF00 + + + se_dbg_dis + 31 + 31 + + + se_gmac_id1_en_rd + 22 + 22 + + + se_gmac_id0_en_rd + 21 + 21 + + + se_gmac_prot_en_rd + 20 + 20 + + + se_cdet_id1_en_rd + 18 + 18 + + + se_cdet_id0_en_rd + 17 + 17 + + + se_cdet_prot_en_rd + 16 + 16 + + + se_pka_id1_en_rd + 14 + 14 + + + se_pka_id0_en_rd + 13 + 13 + + + se_pka_prot_en_rd + 12 + 12 + + + se_trng_id1_en_rd + 10 + 10 + + + se_trng_id0_en_rd + 9 + 9 + + + se_trng_prot_en_rd + 8 + 8 + + + se_aes_id1_en_rd + 6 + 6 + + + se_aes_id0_en_rd + 5 + 5 + + + se_aes_prot_en_rd + 4 + 4 + + + se_sha_id1_en_rd + 2 + 2 + + + se_sha_id0_en_rd + 1 + 1 + + + se_sha_prot_en_rd + 0 + 0 + + + + + se_ctrl_reserved_0 + se_ctrl_reserved_0. + 0xF04 + + + se_ctrl_reserved_0 + 0 + 31 + + + + + se_ctrl_reserved_1 + se_ctrl_reserved_1. + 0xF08 + + + se_ctrl_reserved_1 + 0 + 31 + + + + + se_ctrl_reserved_2 + se_ctrl_reserved_2. + 0xF0C + + + se_ctrl_reserved_2 + 0 + 31 + + + + + + + tzc_sec + tzc_sec. + 0x40005000 + tzc_sec + 32 + read-write + + 0 + 0x1000 + registers + + + + tzc_rom_ctrl + tzc_rom_ctrl. + 0x40 + + + tzc_sboot_done + 28 + 31 + + + tzc_rom1_r1_lock + 27 + 27 + + + tzc_rom1_r0_lock + 26 + 26 + + + tzc_rom0_r1_lock + 25 + 25 + + + tzc_rom0_r0_lock + 24 + 24 + + + tzc_rom1_r1_en + 19 + 19 + + + tzc_rom1_r0_en + 18 + 18 + + + tzc_rom0_r1_en + 17 + 17 + + + tzc_rom0_r0_en + 16 + 16 + + + tzc_rom1_r1_id1_en + 11 + 11 + + + tzc_rom1_r0_id1_en + 10 + 10 + + + tzc_rom0_r1_id1_en + 9 + 9 + + + tzc_rom0_r0_id1_en + 8 + 8 + + + tzc_rom1_r1_id0_en + 3 + 3 + + + tzc_rom1_r0_id0_en + 2 + 2 + + + tzc_rom0_r1_id0_en + 1 + 1 + + + tzc_rom0_r0_id0_en + 0 + 0 + + + + + tzc_rom0_r0 + tzc_rom0_r0. + 0x44 + + + tzc_rom0_r0_start + 16 + 31 + + + tzc_rom0_r0_end + 0 + 15 + + + + + tzc_rom0_r1 + tzc_rom0_r1. + 0x48 + + + tzc_rom0_r1_start + 16 + 31 + + + tzc_rom0_r1_end + 0 + 15 + + + + + tzc_rom1_r0 + tzc_rom1_r0. + 0x4C + + + tzc_rom1_r0_start + 16 + 31 + + + tzc_rom1_r0_end + 0 + 15 + + + + + tzc_rom1_r1 + tzc_rom1_r1. + 0x50 + + + tzc_rom1_r1_start + 16 + 31 + + + tzc_rom1_r1_end + 0 + 15 + + + + + + + tzc_nsec + tzc_nsec. + 0x40006000 + tzc_nsec + 32 + read-write + + 0 + 0x1000 + registers + + + + tzc_rom_ctrl + tzc_rom_ctrl. + 0x40 + + + tzc_sboot_done + 28 + 31 + + + tzc_rom1_r1_lock + 27 + 27 + + + tzc_rom1_r0_lock + 26 + 26 + + + tzc_rom0_r1_lock + 25 + 25 + + + tzc_rom0_r0_lock + 24 + 24 + + + tzc_rom1_r1_en + 19 + 19 + + + tzc_rom1_r0_en + 18 + 18 + + + tzc_rom0_r1_en + 17 + 17 + + + tzc_rom0_r0_en + 16 + 16 + + + tzc_rom1_r1_id1_en + 11 + 11 + + + tzc_rom1_r0_id1_en + 10 + 10 + + + tzc_rom0_r1_id1_en + 9 + 9 + + + tzc_rom0_r0_id1_en + 8 + 8 + + + tzc_rom1_r1_id0_en + 3 + 3 + + + tzc_rom1_r0_id0_en + 2 + 2 + + + tzc_rom0_r1_id0_en + 1 + 1 + + + tzc_rom0_r0_id0_en + 0 + 0 + + + + + tzc_rom0_r0 + tzc_rom0_r0. + 0x44 + + + tzc_rom0_r0_start + 16 + 31 + + + tzc_rom0_r0_end + 0 + 15 + + + + + tzc_rom0_r1 + tzc_rom0_r1. + 0x48 + + + tzc_rom0_r1_start + 16 + 31 + + + tzc_rom0_r1_end + 0 + 15 + + + + + tzc_rom1_r0 + tzc_rom1_r0. + 0x4C + + + tzc_rom1_r0_start + 16 + 31 + + + tzc_rom1_r0_end + 0 + 15 + + + + + tzc_rom1_r1 + tzc_rom1_r1. + 0x50 + + + tzc_rom1_r1_start + 16 + 31 + + + tzc_rom1_r1_end + 0 + 15 + + + + + + + ef_data_0 + ef_data_0. + 0x40007000 + ef_data_0 + 32 + read-write + + 0 + 0x1000 + registers + + + + ef_cfg_0 + ef_cfg_0. + 0x0 + + + ef_dbg_mode + 28 + 31 + + + ef_dbg_jtag_0_dis + 26 + 27 + + + ef_dbg_jtag_1_dis + 24 + 25 + + + ef_efuse_dbg_dis + 23 + 23 + + + ef_se_dbg_dis + 22 + 22 + + + ef_cpu_rst_dbg_dis + 21 + 21 + + + ef_cpu1_dis + 20 + 20 + + + ef_sf_dis + 19 + 19 + + + ef_cam_dis + 18 + 18 + + + ef_0_key_enc_en + 17 + 17 + + + ef_wifi_dis + 16 + 16 + + + ef_ble_dis + 15 + 15 + + + ef_sdu_dis + 14 + 14 + + + ef_sf_key_0_sel + 12 + 13 + + + ef_boot_sel + 8 + 11 + + + ef_cpu0_enc_en + 7 + 7 + + + ef_cpu1_enc_en + 6 + 6 + + + ef_sboot_en + 4 + 5 + + + ef_sboot_sign_mode + 2 + 3 + + + ef_sf_aes_mode + 0 + 1 + + + + + ef_dbg_pwd_low + ef_dbg_pwd_low. + 0x4 + + + ef_dbg_pwd_low + 0 + 31 + + + + + ef_dbg_pwd_high + ef_dbg_pwd_high. + 0x8 + + + ef_dbg_pwd_high + 0 + 31 + + + + + ef_ana_trim_0 + ef_ana_trim_0. + 0xC + + + ef_ana_trim_0 + 0 + 31 + + + + + ef_sw_usage_0 + ef_sw_usage_0. + 0x10 + + + ef_sw_usage_0 + 0 + 31 + + + + + ef_wifi_mac_low + ef_wifi_mac_low. + 0x14 + + + ef_wifi_mac_low + 0 + 31 + + + + + ef_wifi_mac_high + ef_wifi_mac_high. + 0x18 + + + ef_wifi_mac_high + 0 + 31 + + + + + ef_key_slot_0_w0 + ef_key_slot_0_w0. + 0x1C + + + ef_key_slot_0_w0 + 0 + 31 + + + + + ef_key_slot_0_w1 + ef_key_slot_0_w1. + 0x20 + + + ef_key_slot_0_w1 + 0 + 31 + + + + + ef_key_slot_0_w2 + ef_key_slot_0_w2. + 0x24 + + + ef_key_slot_0_w2 + 0 + 31 + + + + + ef_key_slot_0_w3 + ef_key_slot_0_w3. + 0x28 + + + ef_key_slot_0_w3 + 0 + 31 + + + + + ef_key_slot_1_w0 + ef_key_slot_1_w0. + 0x2C + + + ef_key_slot_1_w0 + 0 + 31 + + + + + ef_key_slot_1_w1 + ef_key_slot_1_w1. + 0x30 + + + ef_key_slot_1_w1 + 0 + 31 + + + + + ef_key_slot_1_w2 + ef_key_slot_1_w2. + 0x34 + + + ef_key_slot_1_w2 + 0 + 31 + + + + + ef_key_slot_1_w3 + ef_key_slot_1_w3. + 0x38 + + + ef_key_slot_1_w3 + 0 + 31 + + + + + ef_key_slot_2_w0 + ef_key_slot_2_w0. + 0x3C + + + ef_key_slot_2_w0 + 0 + 31 + + + + + ef_key_slot_2_w1 + ef_key_slot_2_w1. + 0x40 + + + ef_key_slot_2_w1 + 0 + 31 + + + + + ef_key_slot_2_w2 + ef_key_slot_2_w2. + 0x44 + + + ef_key_slot_2_w2 + 0 + 31 + + + + + ef_key_slot_2_w3 + ef_key_slot_2_w3. + 0x48 + + + ef_key_slot_2_w3 + 0 + 31 + + + + + ef_key_slot_3_w0 + ef_key_slot_3_w0. + 0x4C + + + ef_key_slot_3_w0 + 0 + 31 + + + + + ef_key_slot_3_w1 + ef_key_slot_3_w1. + 0x50 + + + ef_key_slot_3_w1 + 0 + 31 + + + + + ef_key_slot_3_w2 + ef_key_slot_3_w2. + 0x54 + + + ef_key_slot_3_w2 + 0 + 31 + + + + + ef_key_slot_3_w3 + ef_key_slot_3_w3. + 0x58 + + + ef_key_slot_3_w3 + 0 + 31 + + + + + ef_key_slot_4_w0 + ef_key_slot_4_w0. + 0x5C + + + ef_key_slot_4_w0 + 0 + 31 + + + + + ef_key_slot_4_w1 + ef_key_slot_4_w1. + 0x60 + + + ef_key_slot_4_w1 + 0 + 31 + + + + + ef_key_slot_4_w2 + ef_key_slot_4_w2. + 0x64 + + + ef_key_slot_4_w2 + 0 + 31 + + + + + ef_key_slot_4_w3 + ef_key_slot_4_w3. + 0x68 + + + ef_key_slot_4_w3 + 0 + 31 + + + + + ef_key_slot_5_w0 + ef_key_slot_5_w0. + 0x6C + + + ef_key_slot_5_w0 + 0 + 31 + + + + + ef_key_slot_5_w1 + ef_key_slot_5_w1. + 0x70 + + + ef_key_slot_5_w1 + 0 + 31 + + + + + ef_key_slot_5_w2 + ef_key_slot_5_w2. + 0x74 + + + ef_key_slot_5_w2 + 0 + 31 + + + + + ef_key_slot_5_w3 + ef_key_slot_5_w3. + 0x78 + + + ef_key_slot_5_w3 + 0 + 31 + + + + + ef_data_0_lock + ef_data_0_lock. + 0x7C + + + rd_lock_key_slot_5 + 31 + 31 + + + rd_lock_key_slot_4 + 30 + 30 + + + rd_lock_key_slot_3 + 29 + 29 + + + rd_lock_key_slot_2 + 28 + 28 + + + rd_lock_key_slot_1 + 27 + 27 + + + rd_lock_key_slot_0 + 26 + 26 + + + rd_lock_dbg_pwd + 25 + 25 + + + wr_lock_key_slot_5_h + 24 + 24 + + + wr_lock_key_slot_4_h + 23 + 23 + + + wr_lock_key_slot_3 + 22 + 22 + + + wr_lock_key_slot_2 + 21 + 21 + + + wr_lock_key_slot_1 + 20 + 20 + + + wr_lock_key_slot_0 + 19 + 19 + + + wr_lock_wifi_mac + 18 + 18 + + + wr_lock_sw_usage_0 + 17 + 17 + + + wr_lock_dbg_pwd + 16 + 16 + + + wr_lock_boot_mode + 15 + 15 + + + wr_lock_key_slot_5_l + 14 + 14 + + + wr_lock_key_slot_4_l + 13 + 13 + + + ef_ana_trim_1 + 0 + 12 + + + + + + + ef_data_1 + ef_data_1. + 0x40007000 + ef_data_1 + 32 + read-write + + 0 + 0x1000 + registers + + + + reg_key_slot_6_w0 + reg_key_slot_6_w0. + 0x80 + + + reg_key_slot_6_w0 + 0 + 31 + + + + + reg_key_slot_6_w1 + reg_key_slot_6_w1. + 0x84 + + + reg_key_slot_6_w1 + 0 + 31 + + + + + reg_key_slot_6_w2 + reg_key_slot_6_w2. + 0x88 + + + reg_key_slot_6_w2 + 0 + 31 + + + + + reg_key_slot_6_w3 + reg_key_slot_6_w3. + 0x8C + + + reg_key_slot_6_w3 + 0 + 31 + + + + + reg_key_slot_7_w0 + reg_key_slot_7_w0. + 0x90 + + + reg_key_slot_7_w0 + 0 + 31 + + + + + reg_key_slot_7_w1 + reg_key_slot_7_w1. + 0x94 + + + reg_key_slot_7_w1 + 0 + 31 + + + + + reg_key_slot_7_w2 + reg_key_slot_7_w2. + 0x98 + + + reg_key_slot_7_w2 + 0 + 31 + + + + + reg_key_slot_7_w3 + reg_key_slot_7_w3. + 0x9C + + + reg_key_slot_7_w3 + 0 + 31 + + + + + reg_key_slot_8_w0 + reg_key_slot_8_w0. + 0xA0 + + + reg_key_slot_8_w0 + 0 + 31 + + + + + reg_key_slot_8_w1 + reg_key_slot_8_w1. + 0xA4 + + + reg_key_slot_8_w1 + 0 + 31 + + + + + reg_key_slot_8_w2 + reg_key_slot_8_w2. + 0xA8 + + + reg_key_slot_8_w2 + 0 + 31 + + + + + reg_key_slot_8_w3 + reg_key_slot_8_w3. + 0xAC + + + reg_key_slot_8_w3 + 0 + 31 + + + + + reg_key_slot_9_w0 + reg_key_slot_9_w0. + 0xB0 + + + reg_key_slot_9_w0 + 0 + 31 + + + + + reg_key_slot_9_w1 + reg_key_slot_9_w1. + 0xB4 + + + reg_key_slot_9_w1 + 0 + 31 + + + + + reg_key_slot_9_w2 + reg_key_slot_9_w2. + 0xB8 + + + reg_key_slot_9_w2 + 0 + 31 + + + + + reg_key_slot_9_w3 + reg_key_slot_9_w3. + 0xBC + + + reg_key_slot_9_w3 + 0 + 31 + + + + + reg_key_slot_10_w0 + reg_key_slot_10_w0. + 0xC0 + + + + reg_key_slot_10_w1 + reg_key_slot_10_w1. + 0xC4 + + + + reg_key_slot_10_w2 + reg_key_slot_10_w2. + 0xC8 + + + + reg_key_slot_10_w3 + reg_key_slot_10_w3. + 0xCC + + + + reg_key_slot_11_w0 + reg_key_slot_11_w0. + 0xD0 + + + + reg_key_slot_11_w1 + reg_key_slot_11_w1. + 0xD4 + + + + reg_key_slot_11_w2 + reg_key_slot_11_w2. + 0xD8 + + + + reg_key_slot_11_w3 + reg_key_slot_11_w3. + 0xDC + + + + reg_data_1_lock + reg_data_1_lock. + 0xE0 + + + rd_lock_key_slot_9 + 29 + 29 + + + rd_lock_key_slot_8 + 28 + 28 + + + rd_lock_key_slot_7 + 27 + 27 + + + rd_lock_key_slot_6 + 26 + 26 + + + RESERVED_25_16 + 16 + 25 + + + wr_lock_key_slot_9 + 13 + 13 + + + wr_lock_key_slot_8 + 12 + 12 + + + wr_lock_key_slot_7 + 11 + 11 + + + wr_lock_key_slot_6 + 10 + 10 + + + RESERVED_9_0 + 0 + 9 + + + + + + + ef_ctrl + ef_ctrl. + 0x40007000 + ef_ctrl + 32 + read-write + + 0 + 0x1000 + registers + + + + ef_if_ctrl_0 + ef_if_ctrl_0. + 0x800 + + + ef_if_prot_code_cyc + 24 + 31 + + + ef_if_0_int_set + 22 + 22 + + + ef_if_0_int_clr + 21 + 21 + + + ef_if_0_int + 20 + 20 + + + ef_if_cyc_modify_lock + 19 + 19 + + + ef_if_auto_rd_en + 18 + 18 + + + ef_clk_sahb_data_gate + 17 + 17 + + + ef_if_por_dig + 16 + 16 + + + ef_if_prot_code_ctrl + 8 + 15 + + + ef_clk_sahb_data_sel + 7 + 7 + + + ef_if_0_cyc_modify + 6 + 6 + + + ef_if_0_manual_en + 5 + 5 + + + ef_if_0_trig + 4 + 4 + + + ef_if_0_rw + 3 + 3 + + + ef_if_0_busy + 2 + 2 + + + ef_if_0_autoload_done + 1 + 1 + + + ef_if_0_autoload_p1_done + 0 + 0 + + + + + ef_if_cyc_0 + ef_if_cyc_0. + 0x804 + + + ef_if_cyc_pd_cs_s + 24 + 31 + + + ef_if_cyc_cs + 18 + 23 + + + ef_if_cyc_rd_adr + 12 + 17 + + + ef_if_cyc_rd_dat + 6 + 11 + + + ef_if_cyc_rd_dmy + 0 + 5 + + + + + ef_if_cyc_1 + ef_if_cyc_1. + 0x808 + + + ef_if_cyc_pd_cs_h + 26 + 31 + + + ef_if_cyc_ps_cs + 20 + 25 + + + ef_if_cyc_wr_adr + 14 + 19 + + + ef_if_cyc_pp + 6 + 13 + + + ef_if_cyc_pi + 0 + 5 + + + + + ef_if_0_manual + ef_if_0_manual. + 0x80C + + + ef_if_prot_code_manual + 24 + 31 + + + ef_if_0_q + 16 + 23 + + + ef_if_csb + 15 + 15 + + + ef_if_load + 14 + 14 + + + ef_if_pgenb + 13 + 13 + + + ef_if_strobe + 12 + 12 + + + ef_if_ps + 11 + 11 + + + ef_if_pd + 10 + 10 + + + ef_if_a + 0 + 9 + + + + + ef_if_0_status + ef_if_0_status. + 0x810 + + + ef_if_0_status + 0 + 31 + + + + + ef_if_cfg_0 + ef_if_cfg_0. + 0x814 + + + ef_if_dbg_mode + 28 + 31 + + + ef_if_dbg_jtag_0_dis + 26 + 27 + + + ef_if_dbg_jtag_1_dis + 24 + 25 + + + ef_if_efuse_dbg_dis + 23 + 23 + + + ef_if_se_dbg_dis + 22 + 22 + + + ef_if_cpu_rst_dbg_dis + 21 + 21 + + + ef_if_cpu1_dis + 20 + 20 + + + ef_if_sf_dis + 19 + 19 + + + ef_if_cam_dis + 18 + 18 + + + ef_if_0_key_enc_en + 17 + 17 + + + ef_if_wifi_dis + 16 + 16 + + + ef_if_ble_dis + 15 + 15 + + + ef_if_sdu_dis + 14 + 14 + + + ef_if_sf_key_0_sel + 12 + 13 + + + ef_if_boot_sel + 8 + 11 + + + ef_if_cpu0_enc_en + 7 + 7 + + + ef_if_cpu1_enc_en + 6 + 6 + + + ef_if_sboot_en + 4 + 5 + + + ef_if_sboot_sign_mode + 2 + 3 + + + ef_if_sf_aes_mode + 0 + 1 + + + + + ef_sw_cfg_0 + ef_sw_cfg_0. + 0x818 + + + ef_sw_dbg_mode + 28 + 31 + + + ef_sw_dbg_jtag_0_dis + 26 + 27 + + + ef_sw_dbg_jtag_1_dis + 24 + 25 + + + ef_sw_efuse_dbg_dis + 23 + 23 + + + ef_sw_se_dbg_dis + 22 + 22 + + + ef_sw_cpu_rst_dbg_dis + 21 + 21 + + + ef_sw_cpu1_dis + 20 + 20 + + + ef_sw_sf_dis + 19 + 19 + + + ef_sw_cam_dis + 18 + 18 + + + ef_sw_0_key_enc_en + 17 + 17 + + + ef_sw_wifi_dis + 16 + 16 + + + ef_sw_ble_dis + 15 + 15 + + + ef_sw_sdu_dis + 14 + 14 + + + ef_sw_sf_key_0_sel + 12 + 13 + + + ef_sw_cpu0_enc_en + 7 + 7 + + + ef_sw_cpu1_enc_en + 6 + 6 + + + ef_sw_sboot_en + 4 + 5 + + + ef_sw_sboot_sign_mode + 2 + 3 + + + ef_sw_sf_aes_mode + 0 + 1 + + + + + ef_reserved + ef_reserved. + 0x81C + + + ef_reserved + 0 + 31 + + + + + ef_if_ana_trim_0 + ef_if_ana_trim_0. + 0x820 + + + ef_if_ana_trim_0 + 0 + 31 + + + + + ef_if_sw_usage_0 + ef_if_sw_usage_0. + 0x824 + + + ef_if_sw_usage_0 + 0 + 31 + + + + + ef_crc_ctrl_0 + ef_crc_ctrl_0. + 0xA00 + + + ef_crc_slp_n + 16 + 31 + + + ef_crc_lock + 11 + 11 + + + ef_crc_int_set + 10 + 10 + + + ef_crc_int_clr + 9 + 9 + + + ef_crc_int + 8 + 8 + + + ef_crc_din_endian + 7 + 7 + + + ef_crc_dout_endian + 6 + 6 + + + ef_crc_dout_inv_en + 5 + 5 + + + ef_crc_error + 4 + 4 + + + ef_crc_mode + 3 + 3 + + + ef_crc_en + 2 + 2 + + + ef_crc_trig + 1 + 1 + + + ef_crc_busy + 0 + 0 + + + + + ef_crc_ctrl_1 + ef_crc_ctrl_1. + 0xA04 + + + ef_crc_data_0_en + 0 + 31 + + + + + ef_crc_ctrl_2 + ef_crc_ctrl_2. + 0xA08 + + + ef_crc_data_1_en + 0 + 31 + + + + + ef_crc_ctrl_3 + ef_crc_ctrl_3. + 0xA0C + + + ef_crc_iv + 0 + 31 + + + + + ef_crc_ctrl_4 + ef_crc_ctrl_4. + 0xA10 + + + ef_crc_golden + 0 + 31 + + + + + ef_crc_ctrl_5 + ef_crc_ctrl_5. + 0xA14 + + + ef_crc_dout + 0 + 31 + + + + + + + cci + cci. + 0x40008000 + cci + 32 + read-write + + 0 + 0x1000 + registers + + + + cci_cfg + cci_cfg. + 0x0 + + + reg_mcci_clk_inv + 9 + 9 + + + reg_scci_clk_inv + 8 + 8 + + + cfg_cci1_pre_read + 7 + 7 + + + reg_div_m_cci_sclk + 5 + 6 + + + reg_m_cci_sclk_en + 4 + 4 + + + cci_mas_hw_mode + 3 + 3 + + + cci_mas_sel_cci2 + 2 + 2 + + + cci_slv_sel_cci2 + 1 + 1 + + + cci_en + 0 + 0 + + + + + cci_addr + cci_addr. + 0x4 + + + apb_cci_addr + 0 + 31 + + + + + cci_wdata + cci_wdata. + 0x8 + + + apb_cci_wdata + 0 + 31 + + + + + cci_rdata + cci_rdata. + 0xC + + + apb_cci_rdata + 0 + 31 + + + + + cci_ctl + cci_ctl. + 0x10 + + + ahb_state + 2 + 3 + + + cci_read_flag + 1 + 1 + + + cci_write_flag + 0 + 0 + + + + + + + l1c + l1c. + 0x40009000 + l1c + 32 + read-write + + 0 + 0x1000 + registers + + + + l1c_config + l1c_config. + 0x0 + + + reserved_31_30 + 30 + 31 + + + l1c_flush_done + 29 + 29 + + + l1c_flush_en + 28 + 28 + + + wrap_dis + 26 + 26 + + + early_resp_dis + 25 + 25 + + + l1c_bmx_busy_option_dis + 24 + 24 + + + l1c_bmx_timeout_en + 20 + 23 + + + l1c_bmx_arb_mode + 16 + 17 + + + l1c_bmx_err_en + 15 + 15 + + + l1c_bypass + 14 + 14 + + + irom_2t_access + 12 + 12 + + + l1c_way_dis + 8 + 11 + + + l1c_wa_en + 6 + 6 + + + l1c_wb_en + 5 + 5 + + + l1c_wt_en + 4 + 4 + + + l1c_invalid_done + 3 + 3 + + + l1c_invalid_en + 2 + 2 + + + l1c_cnt_en + 1 + 1 + + + l1c_cacheable + 0 + 0 + + + + + hit_cnt_lsb + hit_cnt_lsb. + 0x4 + + + hit_cnt_lsb + 0 + 31 + + + + + hit_cnt_msb + hit_cnt_msb. + 0x8 + + + hit_cnt_msb + 0 + 31 + + + + + miss_cnt + miss_cnt. + 0xC + + + miss_cnt + 0 + 31 + + + + + l1c_misc + l1c_misc. + 0x10 + + + l1c_fsm + 28 + 30 + + + + + l1c_bmx_err_addr_en + l1c_bmx_err_addr_en. + 0x200 + + + l1c_hsel_option + 16 + 19 + + + l1c_bmx_err_tz + 5 + 5 + + + l1c_bmx_err_dec + 4 + 4 + + + l1c_bmx_err_addr_dis + 0 + 0 + + + + + l1c_bmx_err_addr + l1c_bmx_err_addr. + 0x204 + + + l1c_bmx_err_addr + 0 + 31 + + + + + irom1_misr_dataout_0 + irom1_misr_dataout_0. + 0x208 + + + irom1_misr_dataout_0 + 0 + 31 + + + + + irom1_misr_dataout_1 + irom1_misr_dataout_1. + 0x20C + + + irom1_misr_dataout_1 + 0 + 31 + + + + + cpu_clk_gate + cpu_clk_gate. + 0x210 + + + force_e21_clock_on_2 + 2 + 2 + + + force_e21_clock_on_1 + 1 + 1 + + + force_e21_clock_on_0 + 0 + 0 + + + + + + + uart + uart. + 0x4000A000 + uart + 32 + read-write + + 0 + 0x1000 + registers + + + + utx_config + utx_config. + 0x0 + + + cr_utx_len + 16 + 31 + + + cr_utx_bit_cnt_b + 13 + 15 + + + cr_utx_bit_cnt_p + 11 + 12 + + + cr_utx_bit_cnt_d + 8 + 10 + + + cr_utx_ir_inv + 7 + 7 + + + cr_utx_ir_en + 6 + 6 + + + cr_utx_prt_sel + 5 + 5 + + + cr_utx_prt_en + 4 + 4 + + + cr_utx_lin_en + 3 + 3 + + + cr_utx_frm_en + 2 + 2 + + + cr_utx_cts_en + 1 + 1 + + + cr_utx_en + 0 + 0 + + + + + urx_config + urx_config. + 0x4 + + + cr_urx_len + 16 + 31 + + + cr_urx_deg_cnt + 12 + 15 + + + cr_urx_deg_en + 11 + 11 + + + cr_urx_bit_cnt_d + 8 + 10 + + + cr_urx_ir_inv + 7 + 7 + + + cr_urx_ir_en + 6 + 6 + + + cr_urx_prt_sel + 5 + 5 + + + cr_urx_prt_en + 4 + 4 + + + cr_urx_lin_en + 3 + 3 + + + cr_urx_abr_en + 1 + 1 + + + cr_urx_en + 0 + 0 + + + + + uart_bit_prd + uart_bit_prd. + 0x8 + + + cr_urx_bit_prd + 16 + 31 + + + cr_utx_bit_prd + 0 + 15 + + + + + data_config + data_config. + 0xC + + + cr_uart_bit_inv + 0 + 0 + + + + + utx_ir_position + utx_ir_position. + 0x10 + + + cr_utx_ir_pos_p + 16 + 31 + + + cr_utx_ir_pos_s + 0 + 15 + + + + + urx_ir_position + urx_ir_position. + 0x14 + + + cr_urx_ir_pos_s + 0 + 15 + + + + + urx_rto_timer + urx_rto_timer. + 0x18 + + + cr_urx_rto_value + 0 + 7 + + + + + uart_sw_mode + uart_sw_mode. + 0x1C + + + cr_urx_rts_sw_val + 3 + 3 + + + cr_urx_rts_sw_mode + 2 + 2 + + + cr_utx_txd_sw_val + 1 + 1 + + + cr_utx_txd_sw_mode + 0 + 0 + + + + + uart_int_sts + UART interrupt status + 0x20 + + + urx_lse_int + 8 + 8 + + + urx_fer_int + 7 + 7 + + + utx_fer_int + 6 + 6 + + + urx_pce_int + 5 + 5 + + + urx_rto_int + 4 + 4 + + + urx_fifo_int + 3 + 3 + + + utx_fifo_int + 2 + 2 + + + urx_end_int + 1 + 1 + + + utx_end_int + 0 + 0 + + + + + uart_int_mask + UART interrupt mask + 0x24 + + + cr_urx_lse_mask + 8 + 8 + + + cr_urx_fer_mask + 7 + 7 + + + cr_utx_fer_mask + 6 + 6 + + + cr_urx_pce_mask + 5 + 5 + + + cr_urx_rto_mask + 4 + 4 + + + cr_urx_fifo_mask + 3 + 3 + + + cr_utx_fifo_mask + 2 + 2 + + + cr_urx_end_mask + 1 + 1 + + + cr_utx_end_mask + 0 + 0 + + + + + uart_int_clear + UART interrupt clear + 0x28 + + + cr_urx_lse_clr + 8 + 8 + + + rsvd_7 + 7 + 7 + + + rsvd_6 + 6 + 6 + + + cr_urx_pce_clr + 5 + 5 + + + cr_urx_rto_clr + 4 + 4 + + + rsvd_3 + 3 + 3 + + + rsvd_2 + 2 + 2 + + + cr_urx_end_clr + 1 + 1 + + + cr_utx_end_clr + 0 + 0 + + + + + uart_int_en + UART interrupt enable + 0x2C + + + cr_urx_lse_en + 8 + 8 + + + cr_urx_fer_en + 7 + 7 + + + cr_utx_fer_en + 6 + 6 + + + cr_urx_pce_en + 5 + 5 + + + cr_urx_rto_en + 4 + 4 + + + cr_urx_fifo_en + 3 + 3 + + + cr_utx_fifo_en + 2 + 2 + + + cr_urx_end_en + 1 + 1 + + + cr_utx_end_en + 0 + 0 + + + + + uart_status + uart_status. + 0x30 + + + sts_urx_bus_busy + 1 + 1 + + + sts_utx_bus_busy + 0 + 0 + + + + + sts_urx_abr_prd + sts_urx_abr_prd. + 0x34 + + + sts_urx_abr_prd_0x55 + 16 + 31 + + + sts_urx_abr_prd_start + 0 + 15 + + + + + uart_fifo_config_0 + uart_fifo_config_0. + 0x80 + + + rx_fifo_underflow + 7 + 7 + + + rx_fifo_overflow + 6 + 6 + + + tx_fifo_underflow + 5 + 5 + + + tx_fifo_overflow + 4 + 4 + + + rx_fifo_clr + 3 + 3 + + + tx_fifo_clr + 2 + 2 + + + uart_dma_rx_en + 1 + 1 + + + uart_dma_tx_en + 0 + 0 + + + + + uart_fifo_config_1 + uart_fifo_config_1. + 0x84 + + + rx_fifo_th + 24 + 30 + + + tx_fifo_th + 16 + 22 + + + rx_fifo_cnt + 8 + 15 + + + tx_fifo_cnt + 0 + 7 + + + + + uart_fifo_wdata + uart_fifo_wdata. + 0x88 + + + uart_fifo_wdata + 0 + 7 + + + + + uart_fifo_rdata + uart_fifo_rdata. + 0x8C + + + uart_fifo_rdata + 0 + 7 + + + + + + + spi + spi. + 0x4000A200 + spi + 32 + read-write + + 0 + 0x1000 + registers + + + + spi_config + spi_config. + 0x0 + + + cr_spi_deg_cnt + 12 + 15 + + + cr_spi_deg_en + 11 + 11 + + + cr_spi_m_cont_en + 9 + 9 + + + cr_spi_rxd_ignr_en + 8 + 8 + + + cr_spi_byte_inv + 7 + 7 + + + cr_spi_bit_inv + 6 + 6 + + + cr_spi_sclk_ph + 5 + 5 + + + cr_spi_sclk_pol + 4 + 4 + + + cr_spi_frame_size + 2 + 3 + + + cr_spi_s_en + 1 + 1 + + + cr_spi_m_en + 0 + 0 + + + + + spi_int_sts + spi_int_sts. + 0x4 + + + cr_spi_fer_en + 29 + 29 + + + cr_spi_txu_en + 28 + 28 + + + cr_spi_sto_en + 27 + 27 + + + cr_spi_rxf_en + 26 + 26 + + + cr_spi_txf_en + 25 + 25 + + + cr_spi_end_en + 24 + 24 + + + rsvd_21 + 21 + 21 + + + cr_spi_txu_clr + 20 + 20 + + + cr_spi_sto_clr + 19 + 19 + + + rsvd_18 + 18 + 18 + + + rsvd_17 + 17 + 17 + + + cr_spi_end_clr + 16 + 16 + + + cr_spi_fer_mask + 13 + 13 + + + cr_spi_txu_mask + 12 + 12 + + + cr_spi_sto_mask + 11 + 11 + + + cr_spi_rxf_mask + 10 + 10 + + + cr_spi_txf_mask + 9 + 9 + + + cr_spi_end_mask + 8 + 8 + + + spi_fer_int + 5 + 5 + + + spi_txu_int + 4 + 4 + + + spi_sto_int + 3 + 3 + + + spi_rxf_int + 2 + 2 + + + spi_txf_int + 1 + 1 + + + spi_end_int + 0 + 0 + + + + + spi_bus_busy + spi_bus_busy. + 0x8 + + + sts_spi_bus_busy + 0 + 0 + + + + + spi_prd_0 + spi_prd_0. + 0x10 + + + cr_spi_prd_d_ph_1 + 24 + 31 + + + cr_spi_prd_d_ph_0 + 16 + 23 + + + cr_spi_prd_p + 8 + 15 + + + cr_spi_prd_s + 0 + 7 + + + + + spi_prd_1 + spi_prd_1. + 0x14 + + + cr_spi_prd_i + 0 + 7 + + + + + spi_rxd_ignr + spi_rxd_ignr. + 0x18 + + + cr_spi_rxd_ignr_s + 16 + 20 + + + cr_spi_rxd_ignr_p + 0 + 4 + + + + + spi_sto_value + spi_sto_value. + 0x1C + + + cr_spi_sto_value + 0 + 11 + + + + + spi_fifo_config_0 + spi_fifo_config_0. + 0x80 + + + rx_fifo_underflow + 7 + 7 + + + rx_fifo_overflow + 6 + 6 + + + tx_fifo_underflow + 5 + 5 + + + tx_fifo_overflow + 4 + 4 + + + rx_fifo_clr + 3 + 3 + + + tx_fifo_clr + 2 + 2 + + + spi_dma_rx_en + 1 + 1 + + + spi_dma_tx_en + 0 + 0 + + + + + spi_fifo_config_1 + spi_fifo_config_1. + 0x84 + + + rx_fifo_th + 24 + 25 + + + tx_fifo_th + 16 + 17 + + + rx_fifo_cnt + 8 + 10 + + + tx_fifo_cnt + 0 + 2 + + + + + spi_fifo_wdata + spi_fifo_wdata. + 0x88 + + + spi_fifo_wdata + 0 + 31 + + + + + spi_fifo_rdata + spi_fifo_rdata. + 0x8C + + + spi_fifo_rdata + 0 + 31 + + + + + + + i2c + i2c. + 0x4000A300 + i2c + 32 + read-write + + 0 + 0x1000 + registers + + + + i2c_config + i2c_config. + 0x0 + + + cr_i2c_deg_cnt + 28 + 31 + + + cr_i2c_pkt_len + 16 + 23 + + + cr_i2c_slv_addr + 8 + 14 + + + cr_i2c_sub_addr_bc + 5 + 6 + + + cr_i2c_sub_addr_en + 4 + 4 + + + cr_i2c_scl_sync_en + 3 + 3 + + + cr_i2c_deg_en + 2 + 2 + + + cr_i2c_pkt_dir + 1 + 1 + + + cr_i2c_m_en + 0 + 0 + + + + + i2c_int_sts + i2c_int_sts. + 0x4 + + + cr_i2c_fer_en + 29 + 29 + + + cr_i2c_arb_en + 28 + 28 + + + cr_i2c_nak_en + 27 + 27 + + + cr_i2c_rxf_en + 26 + 26 + + + cr_i2c_txf_en + 25 + 25 + + + cr_i2c_end_en + 24 + 24 + + + rsvd_21 + 21 + 21 + + + cr_i2c_arb_clr + 20 + 20 + + + cr_i2c_nak_clr + 19 + 19 + + + rsvd_18 + 18 + 18 + + + rsvd_17 + 17 + 17 + + + cr_i2c_end_clr + 16 + 16 + + + cr_i2c_fer_mask + 13 + 13 + + + cr_i2c_arb_mask + 12 + 12 + + + cr_i2c_nak_mask + 11 + 11 + + + cr_i2c_rxf_mask + 10 + 10 + + + cr_i2c_txf_mask + 9 + 9 + + + cr_i2c_end_mask + 8 + 8 + + + i2c_fer_int + 5 + 5 + + + i2c_arb_int + 4 + 4 + + + i2c_nak_int + 3 + 3 + + + i2c_rxf_int + 2 + 2 + + + i2c_txf_int + 1 + 1 + + + i2c_end_int + 0 + 0 + + + + + i2c_sub_addr + i2c_sub_addr. + 0x8 + + + cr_i2c_sub_addr_b3 + 24 + 31 + + + cr_i2c_sub_addr_b2 + 16 + 23 + + + cr_i2c_sub_addr_b1 + 8 + 15 + + + cr_i2c_sub_addr_b0 + 0 + 7 + + + + + i2c_bus_busy + i2c_bus_busy. + 0xC + + + cr_i2c_bus_busy_clr + 1 + 1 + + + sts_i2c_bus_busy + 0 + 0 + + + + + i2c_prd_start + i2c_prd_start. + 0x10 + + + cr_i2c_prd_s_ph_3 + 24 + 31 + + + cr_i2c_prd_s_ph_2 + 16 + 23 + + + cr_i2c_prd_s_ph_1 + 8 + 15 + + + cr_i2c_prd_s_ph_0 + 0 + 7 + + + + + i2c_prd_stop + i2c_prd_stop. + 0x14 + + + cr_i2c_prd_p_ph_3 + 24 + 31 + + + cr_i2c_prd_p_ph_2 + 16 + 23 + + + cr_i2c_prd_p_ph_1 + 8 + 15 + + + cr_i2c_prd_p_ph_0 + 0 + 7 + + + + + i2c_prd_data + i2c_prd_data. + 0x18 + + + cr_i2c_prd_d_ph_3 + 24 + 31 + + + cr_i2c_prd_d_ph_2 + 16 + 23 + + + cr_i2c_prd_d_ph_1 + 8 + 15 + + + cr_i2c_prd_d_ph_0 + 0 + 7 + + + + + i2c_fifo_config_0 + i2c_fifo_config_0. + 0x80 + + + rx_fifo_underflow + 7 + 7 + + + rx_fifo_overflow + 6 + 6 + + + tx_fifo_underflow + 5 + 5 + + + tx_fifo_overflow + 4 + 4 + + + rx_fifo_clr + 3 + 3 + + + tx_fifo_clr + 2 + 2 + + + i2c_dma_rx_en + 1 + 1 + + + i2c_dma_tx_en + 0 + 0 + + + + + i2c_fifo_config_1 + i2c_fifo_config_1. + 0x84 + + + rx_fifo_th + 24 + 24 + + + tx_fifo_th + 16 + 16 + + + rx_fifo_cnt + 8 + 9 + + + tx_fifo_cnt + 0 + 1 + + + + + i2c_fifo_wdata + i2c_fifo_wdata. + 0x88 + + + i2c_fifo_wdata + 0 + 31 + + + + + i2c_fifo_rdata + i2c_fifo_rdata. + 0x8C + + + i2c_fifo_rdata + 0 + 31 + + + + + + + pwm + pwm. + 0x4000A400 + pwm + 32 + read-write + + 0 + 0x1000 + registers + + + + pwm_int_config + pwm_int_config. + 0x0 + + + pwm_int_clear + 8 + 13 + + + pwm_interrupt_sts + 0 + 5 + + + + + pwm0_clkdiv + pwm0_clkdiv. + 0x20 + + + pwm_clk_div + 0 + 15 + + + + + pwm0_thre1 + pwm0_thre1. + 0x24 + + + pwm_thre1 + 0 + 15 + + + + + pwm0_thre2 + pwm0_thre2. + 0x28 + + + pwm_thre2 + 0 + 15 + + + + + pwm0_period + pwm0_period. + 0x2C + + + pwm_period + 0 + 15 + + + + + pwm0_config + pwm0_config. + 0x30 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm0_interrupt + pwm0_interrupt. + 0x34 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + pwm1_clkdiv + pwm1_clkdiv. + 0x40 + + + pwm_clk_div + 0 + 15 + + + + + pwm1_thre1 + pwm1_thre1. + 0x44 + + + pwm_thre1 + 0 + 15 + + + + + pwm1_thre2 + pwm1_thre2. + 0x48 + + + pwm_thre2 + 0 + 15 + + + + + pwm1_period + pwm1_period. + 0x4C + + + pwm_period + 0 + 15 + + + + + pwm1_config + pwm1_config. + 0x50 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm1_interrupt + pwm1_interrupt. + 0x54 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + pwm2_clkdiv + pwm2_clkdiv. + 0x60 + + + pwm_clk_div + 0 + 15 + + + + + pwm2_thre1 + pwm2_thre1. + 0x64 + + + pwm_thre1 + 0 + 15 + + + + + pwm2_thre2 + pwm2_thre2. + 0x68 + + + pwm_thre2 + 0 + 15 + + + + + pwm2_period + pwm2_period. + 0x6C + + + pwm_period + 0 + 15 + + + + + pwm2_config + pwm2_config. + 0x70 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm2_interrupt + pwm2_interrupt. + 0x74 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + pwm3_clkdiv + pwm3_clkdiv. + 0x80 + + + pwm_clk_div + 0 + 15 + + + + + pwm3_thre1 + pwm3_thre1. + 0x84 + + + pwm_thre1 + 0 + 15 + + + + + pwm3_thre2 + pwm3_thre2. + 0x88 + + + pwm_thre2 + 0 + 15 + + + + + pwm3_period + pwm3_period. + 0x8C + + + pwm_period + 0 + 15 + + + + + pwm3_config + pwm3_config. + 0x90 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm3_interrupt + pwm3_interrupt. + 0x94 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + pwm4_clkdiv + pwm4_clkdiv. + 0xA0 + + + pwm_clk_div + 0 + 15 + + + + + pwm4_thre1 + pwm4_thre1. + 0xA4 + + + pwm_thre1 + 0 + 15 + + + + + pwm4_thre2 + pwm4_thre2. + 0xA8 + + + pwm_thre2 + 0 + 15 + + + + + pwm4_period + pwm4_period. + 0xAC + + + pwm_period + 0 + 15 + + + + + pwm4_config + pwm4_config. + 0xB0 + + + pwm_sts_top + 7 + 7 + + + pwm_stop_en + 6 + 6 + + + pwm_sw_mode + 5 + 5 + + + pwm_sw_force_val + 4 + 4 + + + pwm_stop_mode + 3 + 3 + + + pwm_out_inv + 2 + 2 + + + reg_clk_sel + 0 + 1 + + + + + pwm4_interrupt + pwm4_interrupt. + 0xB4 + + + pwm_int_enable + 16 + 16 + + + pwm_int_period_cnt + 0 + 15 + + + + + + + timer + timer. + 0x4000A500 + timer + 32 + read-write + + 0 + 0x1000 + registers + + + + TCCR + TCCR. + 0x0 + + + cs_wdt + 8 + 9 + + + RESERVED_7 + 7 + 7 + + + cs_2 + 5 + 6 + + + RESERVED_4 + 4 + 4 + + + cs_1 + 2 + 3 + + + + + TMR2_0 + TMR2_0. + 0x10 + + + tmr + 0 + 31 + + + + + TMR2_1 + TMR2_1. + 0x14 + + + tmr + 0 + 31 + + + + + TMR2_2 + TMR2_2. + 0x18 + + + tmr + 0 + 31 + + + + + TMR3_0 + TMR3_0. + 0x1C + + + tmr + 0 + 31 + + + + + TMR3_1 + TMR3_1. + 0x20 + + + tmr + 0 + 31 + + + + + TMR3_2 + TMR3_2. + 0x24 + + + tmr + 0 + 31 + + + + + TCR2 + TCR2. + 0x2C + + + tcr + 0 + 31 + + + + + TCR3 + TCR3. + 0x30 + + + tcr + 0 + 31 + + + + + TMSR2 + TMSR2. + 0x38 + + + tmsr_2 + 2 + 2 + + + tmsr_1 + 1 + 1 + + + tmsr_0 + 0 + 0 + + + + + TMSR3 + TMSR3. + 0x3C + + + tmsr_2 + 2 + 2 + + + tmsr_1 + 1 + 1 + + + tmsr_0 + 0 + 0 + + + + + TIER2 + TIER2. + 0x44 + + + tier_2 + 2 + 2 + + + tier_1 + 1 + 1 + + + tier_0 + 0 + 0 + + + + + TIER3 + TIER3. + 0x48 + + + tier_2 + 2 + 2 + + + tier_1 + 1 + 1 + + + tier_0 + 0 + 0 + + + + + TPLVR2 + TPLVR2. + 0x50 + + + tplvr + 0 + 31 + + + + + TPLVR3 + TPLVR3. + 0x54 + + + tplvr + 0 + 31 + + + + + TPLCR2 + TPLCR2. + 0x5C + + + tplcr + 0 + 1 + + + + + TPLCR3 + TPLCR3. + 0x60 + + + tplcr + 0 + 1 + + + + + WMER + WMER. + 0x64 + + + wrie + 1 + 1 + + + we + 0 + 0 + + + + + WMR + WMR. + 0x68 + + + wmr + 0 + 15 + + + + + WVR + WVR. + 0x6C + + + wvr + 0 + 15 + + + + + WSR + WSR. + 0x70 + + + wts + 0 + 0 + + + + + TICR2 + TICR2. + 0x78 + + + tclr_2 + 2 + 2 + + + tclr_1 + 1 + 1 + + + tclr_0 + 0 + 0 + + + + + TICR3 + TICR3. + 0x7C + + + tclr_2 + 2 + 2 + + + tclr_1 + 1 + 1 + + + tclr_0 + 0 + 0 + + + + + WICR + WICR. + 0x80 + + + wiclr + 0 + 0 + + + + + TCER + TCER. + 0x84 + + + timer3_en + 2 + 2 + + + timer2_en + 1 + 1 + + + + + TCMR + TCMR. + 0x88 + + + timer3_mode + 2 + 2 + + + timer2_mode + 1 + 1 + + + + + TILR2 + TILR2. + 0x90 + + + tilr_2 + 2 + 2 + + + tilr_1 + 1 + 1 + + + tilr_0 + 0 + 0 + + + + + TILR3 + TILR3. + 0x94 + + + tilr_2 + 2 + 2 + + + tilr_1 + 1 + 1 + + + tilr_0 + 0 + 0 + + + + + WCR + WCR. + 0x98 + + + wcr + 0 + 0 + + + + + WFAR + WFAR. + 0x9C + + + wfar + 0 + 15 + + + + + WSAR + WSAR. + 0xA0 + + + wsar + 0 + 15 + + + + + TCVWR2 + TCVWR2. + 0xA8 + + + tcvwr + 0 + 31 + + + + + TCVWR3 + TCVWR3. + 0xAC + + + tcvwr + 0 + 31 + + + + + TCVSYN2 + TCVSYN2. + 0xB4 + + + tcvsyn2 + 0 + 31 + + + + + TCVSYN3 + TCVSYN3. + 0xB8 + + + tcvsyn3 + 0 + 31 + + + + + TCDR + TCDR. + 0xBC + + + wcdr + 24 + 31 + + + tcdr3 + 16 + 23 + + + tcdr2 + 8 + 15 + + + + + + + ir + ir. + 0x4000A600 + ir + 32 + read-write + + 0 + 0x1000 + registers + + + + irtx_config + irtx_config. + 0x0 + + + cr_irtx_data_num + 12 + 17 + + + cr_irtx_tail_hl_inv + 11 + 11 + + + cr_irtx_tail_en + 10 + 10 + + + cr_irtx_head_hl_inv + 9 + 9 + + + cr_irtx_head_en + 8 + 8 + + + cr_irtx_logic1_hl_inv + 6 + 6 + + + cr_irtx_logic0_hl_inv + 5 + 5 + + + cr_irtx_data_en + 4 + 4 + + + cr_irtx_swm_en + 3 + 3 + + + cr_irtx_mod_en + 2 + 2 + + + cr_irtx_out_inv + 1 + 1 + + + cr_irtx_en + 0 + 0 + + + + + irtx_int_sts + irtx_int_sts. + 0x4 + + + cr_irtx_end_en + 24 + 24 + + + cr_irtx_end_clr + 16 + 16 + + + cr_irtx_end_mask + 8 + 8 + + + irtx_end_int + 0 + 0 + + + + + irtx_data_word0 + irtx_data_word0. + 0x8 + + + cr_irtx_data_word0 + 0 + 31 + + + + + irtx_data_word1 + irtx_data_word1. + 0xC + + + cr_irtx_data_word1 + 0 + 31 + + + + + irtx_pulse_width + irtx_pulse_width. + 0x10 + + + cr_irtx_mod_ph1_w + 24 + 31 + + + cr_irtx_mod_ph0_w + 16 + 23 + + + cr_irtx_pw_unit + 0 + 11 + + + + + irtx_pw + irtx_pw. + 0x14 + + + cr_irtx_tail_ph1_w + 28 + 31 + + + cr_irtx_tail_ph0_w + 24 + 27 + + + cr_irtx_head_ph1_w + 20 + 23 + + + cr_irtx_head_ph0_w + 16 + 19 + + + cr_irtx_logic1_ph1_w + 12 + 15 + + + cr_irtx_logic1_ph0_w + 8 + 11 + + + cr_irtx_logic0_ph1_w + 4 + 7 + + + cr_irtx_logic0_ph0_w + 0 + 3 + + + + + irtx_swm_pw_0 + irtx_swm_pw_0. + 0x40 + + + cr_irtx_swm_pw_0 + 0 + 31 + + + + + irtx_swm_pw_1 + irtx_swm_pw_1. + 0x44 + + + cr_irtx_swm_pw_1 + 0 + 31 + + + + + irtx_swm_pw_2 + irtx_swm_pw_2. + 0x48 + + + cr_irtx_swm_pw_2 + 0 + 31 + + + + + irtx_swm_pw_3 + irtx_swm_pw_3. + 0x4C + + + cr_irtx_swm_pw_3 + 0 + 31 + + + + + irtx_swm_pw_4 + irtx_swm_pw_4. + 0x50 + + + cr_irtx_swm_pw_4 + 0 + 31 + + + + + irtx_swm_pw_5 + irtx_swm_pw_5. + 0x54 + + + cr_irtx_swm_pw_5 + 0 + 31 + + + + + irtx_swm_pw_6 + irtx_swm_pw_6. + 0x58 + + + cr_irtx_swm_pw_6 + 0 + 31 + + + + + irtx_swm_pw_7 + irtx_swm_pw_7. + 0x5C + + + cr_irtx_swm_pw_7 + 0 + 31 + + + + + irrx_config + irrx_config. + 0x80 + + + cr_irrx_deg_cnt + 8 + 11 + + + cr_irrx_deg_en + 4 + 4 + + + cr_irrx_mode + 2 + 3 + + + cr_irrx_in_inv + 1 + 1 + + + cr_irrx_en + 0 + 0 + + + + + irrx_int_sts + irrx_int_sts. + 0x84 + + + cr_irrx_end_en + 24 + 24 + + + cr_irrx_end_clr + 16 + 16 + + + cr_irrx_end_mask + 8 + 8 + + + irrx_end_int + 0 + 0 + + + + + irrx_pw_config + irrx_pw_config. + 0x88 + + + cr_irrx_end_th + 16 + 31 + + + cr_irrx_data_th + 0 + 15 + + + + + irrx_data_count + irrx_data_count. + 0x90 + + + sts_irrx_data_cnt + 0 + 6 + + + + + irrx_data_word0 + irrx_data_word0. + 0x94 + + + sts_irrx_data_word0 + 0 + 31 + + + + + irrx_data_word1 + irrx_data_word1. + 0x98 + + + sts_irrx_data_word1 + 0 + 31 + + + + + irrx_swm_fifo_config_0 + irrx_swm_fifo_config_0. + 0xC0 + + + rx_fifo_cnt + 4 + 10 + + + rx_fifo_underflow + 3 + 3 + + + rx_fifo_overflow + 2 + 2 + + + rx_fifo_clr + 0 + 0 + + + + + irrx_swm_fifo_rdata + irrx_swm_fifo_rdata. + 0xC4 + + + rx_fifo_rdata + 0 + 15 + + + + + + + cks + cks. + 0x4000A700 + cks + 32 + read-write + + 0 + 0x1000 + registers + + + + cks_config + cks_config. + 0x0 + + + cr_cks_byte_swap + 1 + 1 + + + cr_cks_clr + 0 + 0 + + + + + data_in + data_in. + 0x4 + + + data_in + 0 + 7 + + + + + cks_out + cks_out. + 0x8 + + + cks_out + 0 + 15 + + + + + + + qdec + qdec. + 0x4000A800 + qdec + 32 + read-write + + 0 + 0x1000 + registers + + + + qdec_ctrl + qdec_ctrl. + 0x0 + + + input_swap + 31 + 31 + + + rpt_mode + 30 + 30 + + + spl_mode + 29 + 29 + + + led_period + 20 + 28 + + + rpt_period + 12 + 19 + + + spl_period + 8 + 11 + + + deg_cnt + 4 + 7 + + + deg_en + 3 + 3 + + + led_pol + 2 + 2 + + + led_en + 1 + 1 + + + qdec_en + 0 + 0 + + + + + qdec_value + qdec_value. + 0x4 + + + spl_val + 28 + 29 + + + acc2_val + 16 + 19 + + + acc1_val + 0 + 10 + + + + + qdec_int_en + qdec_int_en. + 0x10 + + + overflow_en + 3 + 3 + + + dbl_rdy_en + 2 + 2 + + + spl_rdy_en + 1 + 1 + + + rpt_rdy_en + 0 + 0 + + + + + qdec_int_sts + qdec_int_sts. + 0x14 + + + overflow_sts + 3 + 3 + + + dbl_rdy_sts + 2 + 2 + + + spl_rdy_sts + 1 + 1 + + + rpt_rdy_sts + 0 + 0 + + + + + qdec_int_clr + qdec_int_clr. + 0x18 + + + overflow_clr + 3 + 3 + + + dbl_rdy_clr + 2 + 2 + + + spl_rdy_clr + 1 + 1 + + + rpt_rdy_clr + 0 + 0 + + + + + + + kys + kys. + 0x4000AB00 + kys + 32 + read-write + + 0 + 0x1000 + registers + + + + ks_ctrl + ks_ctrl. + 0x0 + + + col_num + 20 + 24 + + + row_num + 16 + 18 + + + rc_ext + 8 + 9 + + + deg_cnt + 4 + 7 + + + deg_en + 3 + 3 + + + ghost_en + 2 + 2 + + + ks_en + 0 + 0 + + + + + ks_int_en + ks_int_en. + 0x10 + + + ks_int_en + 0 + 0 + + + + + ks_int_sts + ks_int_sts. + 0x14 + + + keycode_valid + 0 + 3 + + + + + keycode_clr + keycode_clr. + 0x18 + + + keycode_clr + 0 + 3 + + + + + keycode_value + keycode_value. + 0x1C + + + keycode3 + 24 + 31 + + + keycode2 + 16 + 23 + + + keycode1 + 8 + 15 + + + keycode0 + 0 + 7 + + + + + + + i2s + i2s. + 0x4000AA00 + i2s + 32 + read-write + + 0 + 0x1000 + registers + + + + i2s_config + i2s_config. + 0x0 + + + cr_ofs_en + 25 + 25 + + + cr_ofs_cnt + 20 + 24 + + + cr_mono_rx_ch + 19 + 19 + + + cr_endian + 18 + 18 + + + cr_i2s_mode + 16 + 17 + + + cr_data_size + 14 + 15 + + + cr_frame_size + 12 + 13 + + + cr_fs_3ch_mode + 8 + 8 + + + cr_fs_4ch_mode + 7 + 7 + + + cr_fs_1t_mode + 6 + 6 + + + cr_mute_mode + 5 + 5 + + + cr_mono_mode + 4 + 4 + + + cr_i2s_rxd_en + 3 + 3 + + + cr_i2s_txd_en + 2 + 2 + + + cr_i2s_s_en + 1 + 1 + + + cr_i2s_m_en + 0 + 0 + + + + + i2s_int_sts + i2s_int_sts. + 0x4 + + + cr_i2s_fer_en + 26 + 26 + + + cr_i2s_rxf_en + 25 + 25 + + + cr_i2s_txf_en + 24 + 24 + + + cr_i2s_fer_mask + 10 + 10 + + + cr_i2s_rxf_mask + 9 + 9 + + + cr_i2s_txf_mask + 8 + 8 + + + i2s_fer_int + 2 + 2 + + + i2s_rxf_int + 1 + 1 + + + i2s_txf_int + 0 + 0 + + + + + i2s_bclk_config + i2s_bclk_config. + 0x10 + + + cr_bclk_div_h + 16 + 27 + + + cr_bclk_div_l + 0 + 11 + + + + + i2s_fifo_config_0 + i2s_fifo_config_0. + 0x80 + + + cr_fifo_24b_lj + 10 + 10 + + + cr_fifo_lr_exchg + 9 + 9 + + + cr_fifo_lr_merge + 8 + 8 + + + rx_fifo_underflow + 7 + 7 + + + rx_fifo_overflow + 6 + 6 + + + tx_fifo_underflow + 5 + 5 + + + tx_fifo_overflow + 4 + 4 + + + rx_fifo_clr + 3 + 3 + + + tx_fifo_clr + 2 + 2 + + + i2s_dma_rx_en + 1 + 1 + + + i2s_dma_tx_en + 0 + 0 + + + + + i2s_fifo_config_1 + i2s_fifo_config_1. + 0x84 + + + rx_fifo_th + 24 + 27 + + + tx_fifo_th + 16 + 19 + + + rx_fifo_cnt + 8 + 12 + + + tx_fifo_cnt + 0 + 4 + + + + + i2s_fifo_wdata + i2s_fifo_wdata. + 0x88 + + + i2s_fifo_wdata + 0 + 31 + + + + + i2s_fifo_rdata + i2s_fifo_rdata. + 0x8C + + + i2s_fifo_rdata + 0 + 31 + + + + + i2s_io_config + i2s_io_config. + 0xFC + + + cr_deg_en + 7 + 7 + + + cr_deg_cnt + 4 + 6 + + + cr_i2s_bclk_inv + 3 + 3 + + + cr_i2s_fs_inv + 2 + 2 + + + cr_i2s_rxd_inv + 1 + 1 + + + cr_i2s_txd_inv + 0 + 0 + + + + + + + cam + cam. + 0x4000AD00 + cam + 32 + read-write + + 0 + 0x1000 + registers + + + + dvp2axi_configue + dvp2axi_configue. + 0x0 + + + reg_dvp_wait_cycle + 24 + 31 + + + reg_dvp_pix_clk_cg + 20 + 20 + + + reg_interlv_mode + 16 + 16 + + + reg_subsample_even + 15 + 15 + + + reg_subsample_en + 14 + 14 + + + reg_drop_even + 13 + 13 + + + reg_drop_en + 12 + 12 + + + reg_hw_mode_fwrap + 11 + 11 + + + reg_dvp_mode + 8 + 10 + + + reg_hburst + 4 + 5 + + + reg_line_vld_pol + 3 + 3 + + + reg_fram_vld_pol + 2 + 2 + + + reg_sw_mode + 1 + 1 + + + reg_dvp_enable + 0 + 0 + + + + + dvp2ahb_addr_start_0 + dvp2ahb_addr_start_0. + 0x4 + + + reg_addr_start_0 + 0 + 31 + + + + + dvp2ahb_mem_bcnt_0 + dvp2ahb_mem_bcnt_0. + 0x8 + + + reg_mem_burst_cnt_0 + 0 + 31 + + + + + dvp2ahb_frame_bcnt_0 + dvp2ahb_frame_bcnt_0. + 0xC + + + reg_frame_burst_cnt_0 + 0 + 31 + + + + + dvp2ahb_addr_start_1 + dvp2ahb_addr_start_1. + 0x10 + + + reg_addr_start_1 + 0 + 31 + + + + + dvp2ahb_mem_bcnt_1 + dvp2ahb_mem_bcnt_1. + 0x14 + + + reg_mem_burst_cnt_1 + 0 + 31 + + + + + dvp2ahb_frame_bcnt_1 + dvp2ahb_frame_bcnt_1. + 0x18 + + + reg_frame_burst_cnt_1 + 0 + 31 + + + + + dvp_status_and_error + dvp_status_and_error. + 0x1C + + + st_bus_flsh + 31 + 31 + + + st_bus_wait + 30 + 30 + + + st_bus_func + 29 + 29 + + + st_bus_idle + 28 + 28 + + + frame_valid_cnt_1 + 24 + 27 + + + frame_valid_cnt_0 + 20 + 23 + + + st_dvp_idle + 19 + 19 + + + ahb_idle_1 + 17 + 17 + + + ahb_idle_0 + 16 + 16 + + + sts_vcnt_int + 9 + 9 + + + sts_hcnt_int + 8 + 8 + + + sts_fifo_int_1 + 7 + 7 + + + sts_fifo_int_0 + 6 + 6 + + + sts_frame_int_1 + 5 + 5 + + + sts_frame_int_0 + 4 + 4 + + + sts_mem_int_1 + 3 + 3 + + + sts_mem_int_0 + 2 + 2 + + + sts_normal_int_1 + 1 + 1 + + + sts_normal_int_0 + 0 + 0 + + + + + dvp_frame_fifo_pop + dvp_frame_fifo_pop. + 0x20 + + + reg_int_fifo_clr_1 + 19 + 19 + + + reg_int_frame_clr_1 + 18 + 18 + + + reg_int_mem_clr_1 + 17 + 17 + + + reg_int_normal_clr_1 + 16 + 16 + + + reg_int_vcnt_clr_0 + 9 + 9 + + + reg_int_hcnt_clr_0 + 8 + 8 + + + reg_int_fifo_clr_0 + 7 + 7 + + + reg_int_frame_clr_0 + 6 + 6 + + + reg_int_mem_clr_0 + 5 + 5 + + + reg_int_normal_clr_0 + 4 + 4 + + + rfifo_pop_1 + 1 + 1 + + + rfifo_pop_0 + 0 + 0 + + + + + snsr_control + snsr_control. + 0x24 + + + reg_cam_pwdn + 1 + 1 + + + reg_cam_rst + 0 + 0 + + + + + int_control + int_control. + 0x28 + + + reg_frame_cnt_trgr_int + 28 + 31 + + + reg_int_vcnt_en + 6 + 6 + + + reg_int_hcnt_en + 5 + 5 + + + reg_int_fifo_en + 4 + 4 + + + reg_int_frame_en + 3 + 3 + + + reg_int_mem_en + 2 + 2 + + + reg_int_normal_1_en + 1 + 1 + + + reg_int_normal_0_en + 0 + 0 + + + + + hsync_control + hsync_control. + 0x30 + + + reg_hsync_act_start + 16 + 31 + + + reg_hsync_act_end + 0 + 15 + + + + + vsync_control + vsync_control. + 0x34 + + + reg_vsync_act_start + 16 + 31 + + + reg_vsync_act_end + 0 + 15 + + + + + frame_size_control + frame_size_control. + 0x38 + + + reg_total_vcnt + 16 + 31 + + + reg_total_hcnt + 0 + 15 + + + + + frame_start_addr0_0 + frame_start_addr0_0. + 0x40 + + + frame_start_addr_0_0 + 0 + 31 + + + + + frame_byte_cnt0_0 + frame_byte_cnt0_0. + 0x44 + + + frame_byte_cnt_0_0 + 0 + 31 + + + + + frame_start_addr0_1 + frame_start_addr0_1. + 0x48 + + + frame_start_addr_0_1 + 0 + 31 + + + + + frame_byte_cnt0_1 + frame_byte_cnt0_1. + 0x4C + + + frame_byte_cnt_0_1 + 0 + 31 + + + + + frame_start_addr0_2 + frame_start_addr0_2. + 0x50 + + + frame_start_addr_0_2 + 0 + 31 + + + + + frame_byte_cnt0_2 + frame_byte_cnt0_2. + 0x54 + + + frame_byte_cnt_0_2 + 0 + 31 + + + + + frame_start_addr0_3 + frame_start_addr0_3. + 0x58 + + + frame_start_addr_0_3 + 0 + 31 + + + + + frame_byte_cnt0_3 + frame_byte_cnt0_3. + 0x5C + + + frame_byte_cnt_0_3 + 0 + 31 + + + + + frame_start_addr0_4 + frame_start_addr0_4. + 0x60 + + + frame_start_addr_0_4 + 0 + 31 + + + + + frame_byte_cnt0_4 + frame_byte_cnt0_4. + 0x64 + + + frame_byte_cnt_0_4 + 0 + 31 + + + + + frame_start_addr0_5 + frame_start_addr0_5. + 0x68 + + + frame_start_addr_0_5 + 0 + 31 + + + + + frame_byte_cnt0_5 + frame_byte_cnt0_5. + 0x6C + + + frame_byte_cnt_0_5 + 0 + 31 + + + + + frame_start_addr0_6 + frame_start_addr0_6. + 0x70 + + + frame_start_addr_0_6 + 0 + 31 + + + + + frame_byte_cnt0_6 + frame_byte_cnt0_6. + 0x74 + + + frame_byte_cnt_0_6 + 0 + 31 + + + + + frame_start_addr0_7 + frame_start_addr0_7. + 0x78 + + + frame_start_addr_0_7 + 0 + 31 + + + + + frame_byte_cnt0_7 + frame_byte_cnt0_7. + 0x7C + + + frame_byte_cnt_0_7 + 0 + 31 + + + + + frame_start_addr1_0 + frame_start_addr1_0. + 0x80 + + + frame_start_addr_1_0 + 0 + 31 + + + + + frame_byte_cnt1_0 + frame_byte_cnt1_0. + 0x84 + + + frame_byte_cnt_1_0 + 0 + 31 + + + + + frame_start_addr1_1 + frame_start_addr1_1. + 0x88 + + + frame_start_addr_1_1 + 0 + 31 + + + + + frame_byte_cnt1_1 + frame_byte_cnt1_1. + 0x8C + + + frame_byte_cnt_1_1 + 0 + 31 + + + + + frame_start_addr1_2 + frame_start_addr1_2. + 0x90 + + + frame_start_addr_1_2 + 0 + 31 + + + + + frame_byte_cnt1_2 + frame_byte_cnt1_2. + 0x94 + + + frame_byte_cnt_1_2 + 0 + 31 + + + + + frame_start_addr1_3 + frame_start_addr1_3. + 0x98 + + + frame_start_addr_1_3 + 0 + 31 + + + + + frame_byte_cnt1_3 + frame_byte_cnt1_3. + 0x9C + + + frame_byte_cnt_1_3 + 0 + 31 + + + + + frame_start_addr1_4 + frame_start_addr1_4. + 0xA0 + + + frame_start_addr_1_4 + 0 + 31 + + + + + frame_byte_cnt1_4 + frame_byte_cnt1_4. + 0xA4 + + + frame_byte_cnt_1_4 + 0 + 31 + + + + + frame_start_addr1_5 + frame_start_addr1_5. + 0xA8 + + + frame_start_addr_1_5 + 0 + 31 + + + + + frame_byte_cnt1_5 + frame_byte_cnt1_5. + 0xAC + + + frame_byte_cnt_1_5 + 0 + 31 + + + + + frame_start_addr1_6 + frame_start_addr1_6. + 0xB0 + + + frame_start_addr_1_6 + 0 + 31 + + + + + frame_byte_cnt1_6 + frame_byte_cnt1_6. + 0xB4 + + + frame_byte_cnt_1_6 + 0 + 31 + + + + + frame_start_addr1_7 + frame_start_addr1_7. + 0xB8 + + + frame_start_addr_1_7 + 0 + 31 + + + + + frame_byte_cnt1_7 + frame_byte_cnt1_7. + 0xBC + + + frame_byte_cnt_1_7 + 0 + 31 + + + + + dvp_debug + dvp_debug. + 0xFF0 + + + reg_dvp_dbg_sel + 1 + 3 + + + reg_dvp_dbg_en + 0 + 0 + + + + + dvp_dummy_reg + dvp_dummy_reg. + 0xFFC + + + RESERVED_31_0 + 0 + 31 + + + + + + + mjpeg + mjpeg. + 0x4000AE00 + mjpeg + 32 + read-write + + 0 + 0x1000 + registers + + + + mjpeg_control_1 + mjpeg_control_1. + 0x0 + + + reg_v0_order + 30 + 31 + + + reg_y1_order + 28 + 29 + + + reg_u0_order + 26 + 27 + + + reg_y0_order + 24 + 25 + + + reg_q_mode + 16 + 22 + + + reg_yuv_mode + 12 + 13 + + + reg_h_bust + 8 + 9 + + + reg_reflect_dmy + 6 + 6 + + + reg_last_hf_hblk_dmy + 5 + 5 + + + reg_last_hf_wblk_dmy + 4 + 4 + + + reg_wr_over_stop + 3 + 3 + + + reg_order_u_even + 2 + 2 + + + reg_mjpeg_bit_order + 1 + 1 + + + reg_mjpeg_enable + 0 + 0 + + + + + mjpeg_control_2 + mjpeg_control_2. + 0x4 + + + reg_mjpeg_wait_cycle + 16 + 31 + + + reg_uv_dvp2ahb_fsel + 15 + 15 + + + reg_uv_dvp2ahb_lsel + 14 + 14 + + + reg_yy_dvp2ahb_fsel + 13 + 13 + + + reg_yy_dvp2ahb_lsel + 12 + 12 + + + reg_mjpeg_sw_run + 9 + 9 + + + reg_mjpeg_sw_mode + 8 + 8 + + + reg_sw_frame + 0 + 4 + + + + + mjpeg_yy_frame_addr + mjpeg_yy_frame_addr. + 0x08 + + + reg_yy_addr_start + 0 + 31 + + + + + mjpeg_uv_frame_addr + mjpeg_uv_frame_addr. + 0x0C + + + reg_uv_addr_start + 0 + 31 + + + + + mjpeg_yuv_mem + mjpeg_yuv_mem. + 0x10 + + + reg_uv_mem_hblk + 16 + 28 + + + reg_yy_mem_hblk + 0 + 12 + + + + + jpeg_frame_addr + jpeg_frame_addr. + 0x14 + + + reg_w_addr_start + 0 + 31 + + + + + jpeg_store_memory + jpeg_store_memory. + 0x18 + + + reg_w_burst_cnt + 0 + 31 + + + + + mjpeg_control_3 + mjpeg_control_3. + 0x1C + + + sts_swap_int + 30 + 30 + + + reg_int_swap_en + 29 + 29 + + + frame_valid_cnt + 24 + 28 + + + sts_idle_int + 22 + 22 + + + reg_int_idle_en + 21 + 21 + + + reg_frame_cnt_trgr_int + 16 + 20 + + + ahb_idle + 14 + 14 + + + mjpeg_manf + 13 + 13 + + + mjpeg_mans + 12 + 12 + + + mjpeg_flsh + 11 + 11 + + + mjpeg_wait + 10 + 10 + + + mjpeg_func + 9 + 9 + + + mjpeg_idle + 8 + 8 + + + sts_frame_int + 7 + 7 + + + sts_mem_int + 6 + 6 + + + sts_cam_int + 5 + 5 + + + sts_normal_int + 4 + 4 + + + reg_int_frame_en + 3 + 3 + + + reg_int_mem_en + 2 + 2 + + + reg_int_cam_en + 1 + 1 + + + reg_int_normal_en + 0 + 0 + + + + + mjpeg_frame_fifo_pop + mjpeg_frame_fifo_pop. + 0x20 + + + reg_int_swap_clr + 13 + 13 + + + reg_int_idle_clr + 12 + 12 + + + reg_int_frame_clr + 11 + 11 + + + reg_int_mem_clr + 10 + 10 + + + reg_int_cam_clr + 9 + 9 + + + reg_int_normal_clr + 8 + 8 + + + reg_w_swap_clr + 1 + 1 + + + rfifo_pop + 0 + 0 + + + + + mjpeg_frame_size + mjpeg_frame_size. + 0x24 + + + reg_frame_hblk + 16 + 27 + + + reg_frame_wblk + 0 + 11 + + + + + mjpeg_header_byte + mjpeg_header_byte. + 0x28 + + + reg_tail_exp + 16 + 16 + + + reg_head_byte + 0 + 11 + + + + + mjpeg_swap_mode + mjpeg_swap_mode. + 0x30 + + + sts_swap_fend + 12 + 12 + + + sts_swap_fstart + 11 + 11 + + + sts_read_swap_idx + 10 + 10 + + + sts_swap1_full + 9 + 9 + + + sts_swap0_full + 8 + 8 + + + reg_w_swap_mode + 0 + 0 + + + + + mjpeg_swap_bit_cnt + mjpeg_swap_bit_cnt. + 0x34 + + + frame_swap_end_bit_cnt + 0 + 31 + + + + + mjpeg_paket_ctrl + mjpeg_paket_ctrl. + 0x38 + + + reg_pket_body_byte + 16 + 31 + + + reg_jend_to_pend + 1 + 1 + + + reg_pket_en + 0 + 0 + + + + + mjpeg_paket_head_tail + mjpeg_paket_head_tail. + 0x3C + + + reg_pket_tail_byte + 16 + 27 + + + reg_pket_head_byte + 0 + 11 + + + + + mjpeg_Y_frame_read_status_1 + mjpeg_Y_frame_read_status_1. + 0x40 + + + yy_frm_hblk_r + 16 + 28 + + + yy_mem_hblk_r + 0 + 12 + + + + + mjpeg_Y_frame_read_status_2 + mjpeg_Y_frame_read_status_2. + 0x44 + + + yy_frm_cnt_r + 24 + 31 + + + yy_mem_rnd_r + 16 + 23 + + + yy_wblk_r + 0 + 12 + + + + + mjpeg_Y_frame_write_status + mjpeg_Y_frame_write_status. + 0x48 + + + yy_frm_cnt_w + 24 + 31 + + + yy_mem_rnd_w + 16 + 23 + + + yy_mem_hblk_w + 0 + 12 + + + + + mjpeg_UV_frame_read_status_1 + mjpeg_UV_frame_read_status_1. + 0x4C + + + uv_frm_hblk_r + 16 + 28 + + + uv_mem_hblk_r + 0 + 12 + + + + + mjpeg_UV_frame_read_status_2 + mjpeg_UV_frame_read_status_2. + 0x50 + + + uv_frm_cnt_r + 24 + 31 + + + uv_mem_rnd_r + 16 + 23 + + + uv_wblk_r + 0 + 12 + + + + + mjpeg_UV_frame_write_status + mjpeg_UV_frame_write_status. + 0x54 + + + uv_frm_cnt_w + 24 + 31 + + + uv_mem_rnd_w + 16 + 23 + + + uv_mem_hblk_w + 0 + 12 + + + + + mjpeg_start_addr0 + mjpeg_start_addr0. + 0x80 + + + frame_start_addr_0 + 0 + 31 + + + + + mjpeg_bit_cnt0 + mjpeg_bit_cnt0. + 0x84 + + + frame_bit_cnt_0 + 0 + 31 + + + + + mjpeg_start_addr1 + mjpeg_start_addr1. + 0x88 + + + frame_start_addr_1 + 0 + 31 + + + + + mjpeg_bit_cnt1 + mjpeg_bit_cnt1. + 0x8C + + + frame_bit_cnt_1 + 0 + 31 + + + + + mjpeg_start_addr2 + mjpeg_start_addr2. + 0x90 + + + frame_start_addr_2 + 0 + 31 + + + + + mjpeg_bit_cnt2 + mjpeg_bit_cnt2. + 0x94 + + + frame_bit_cnt_2 + 0 + 31 + + + + + mjpeg_start_addr3 + mjpeg_start_addr3. + 0x98 + + + frame_start_addr_3 + 0 + 31 + + + + + mjpeg_bit_cnt3 + mjpeg_bit_cnt3. + 0x9C + + + frame_bit_cnt_3 + 0 + 31 + + + + + mjpeg_start_addr4 + mjpeg_start_addr4. + 0xA0 + + + frame_start_addr_4 + 0 + 31 + + + + + mjpeg_bit_cnt4 + mjpeg_bit_cnt4. + 0xA4 + + + frame_bit_cnt_4 + 0 + 31 + + + + + mjpeg_start_addr5 + mjpeg_start_addr5. + 0xA8 + + + frame_start_addr_5 + 0 + 31 + + + + + mjpeg_bit_cnt5 + mjpeg_bit_cnt5. + 0xAC + + + frame_bit_cnt_5 + 0 + 31 + + + + + mjpeg_start_addr6 + mjpeg_start_addr6. + 0xB0 + + + frame_start_addr_6 + 0 + 31 + + + + + mjpeg_bit_cnt6 + mjpeg_bit_cnt6. + 0xB4 + + + frame_bit_cnt_6 + 0 + 31 + + + + + mjpeg_start_addr7 + mjpeg_start_addr7. + 0xB8 + + + frame_start_addr_7 + 0 + 31 + + + + + mjpeg_bit_cnt7 + mjpeg_bit_cnt7. + 0xBC + + + frame_bit_cnt_7 + 0 + 31 + + + + + mjpeg_start_addr_8 + mjpeg_start_addr_8. + 0xC0 + + + frame_start_addr_8 + 0 + 31 + + + + + mjpeg_bit_cnt_8 + mjpeg_bit_cnt_8. + 0xC4 + + + frame_bit_cnt_8 + 0 + 31 + + + + + mjpeg_start_addr_9 + mjpeg_start_addr_9. + 0xC8 + + + frame_start_addr_9 + 0 + 31 + + + + + mjpeg_bit_cnt_9 + mjpeg_bit_cnt_9. + 0xCC + + + frame_bit_cnt_9 + 0 + 31 + + + + + mjpeg_start_addr_a + mjpeg_start_addr_a. + 0xD0 + + + frame_start_addr_a + 0 + 31 + + + + + mjpeg_bit_cnt_a + mjpeg_bit_cnt_a. + 0xD4 + + + frame_bit_cnt_a + 0 + 31 + + + + + mjpeg_start_addr_b + mjpeg_start_addr_b. + 0xD8 + + + frame_start_addr_b + 0 + 31 + + + + + mjpeg_bit_cnt_b + mjpeg_bit_cnt_b. + 0xDC + + + frame_bit_cnt_b + 0 + 31 + + + + + mjpeg_start_addr_c + mjpeg_start_addr_c. + 0xE0 + + + frame_start_addr_c + 0 + 31 + + + + + mjpeg_bit_cnt_c + mjpeg_bit_cnt_c. + 0xE4 + + + frame_bit_cnt_c + 0 + 31 + + + + + mjpeg_start_addr_d + mjpeg_start_addr_d. + 0xE8 + + + frame_start_addr_d + 0 + 31 + + + + + mjpeg_bit_cnt_d + mjpeg_bit_cnt_d. + 0xEC + + + frame_bit_cnt_d + 0 + 31 + + + + + mjpeg_start_addr_e + mjpeg_start_addr_e. + 0xF0 + + + frame_start_addr_e + 0 + 31 + + + + + mjpeg_bit_cnt_e + mjpeg_bit_cnt_e. + 0xF4 + + + frame_bit_cnt_e + 0 + 31 + + + + + mjpeg_start_addr_f + mjpeg_start_addr_f. + 0xF8 + + + frame_start_addr_f + 0 + 31 + + + + + mjpeg_bit_cnt_f + mjpeg_bit_cnt_f. + 0xFC + + + frame_bit_cnt_f + 0 + 31 + + + + + mjpeg_q_mode0 + mjpeg_q_mode0. + 0x100 + + + frame_q_mode_0 + 0 + 6 + + + + + mjpeg_q_mode1 + mjpeg_q_mode1. + 0x104 + + + frame_q_mode_1 + 0 + 6 + + + + + mjpeg_q_mode2 + mjpeg_q_mode2. + 0x108 + + + frame_q_mode_2 + 0 + 6 + + + + + mjpeg_q_mode3 + mjpeg_q_mode3. + 0x10C + + + frame_q_mode_3 + 0 + 6 + + + + + mjpeg_q_mode4 + mjpeg_q_mode4. + 0x110 + + + frame_q_mode_4 + 0 + 6 + + + + + mjpeg_q_mode5 + mjpeg_q_mode5. + 0x114 + + + frame_q_mode_5 + 0 + 6 + + + + + mjpeg_q_mode6 + mjpeg_q_mode6. + 0x118 + + + frame_q_mode_6 + 0 + 6 + + + + + mjpeg_q_mode7 + mjpeg_q_mode7. + 0x11C + + + frame_q_mode_7 + 0 + 6 + + + + + mjpeg_q_mode_8 + mjpeg_q_mode_8. + 0x120 + + + frame_q_mode_8 + 0 + 6 + + + + + mjpeg_q_mode_9 + mjpeg_q_mode_9. + 0x124 + + + frame_q_mode_9 + 0 + 6 + + + + + mjpeg_q_mode_a + mjpeg_q_mode_a. + 0x128 + + + frame_q_mode_a + 0 + 6 + + + + + mjpeg_q_mode_b + mjpeg_q_mode_b. + 0x12C + + + frame_q_mode_b + 0 + 6 + + + + + mjpeg_q_mode_c + mjpeg_q_mode_c. + 0x130 + + + frame_q_mode_c + 0 + 6 + + + + + mjpeg_q_mode_d + mjpeg_q_mode_d. + 0x134 + + + frame_q_mode_d + 0 + 6 + + + + + mjpeg_q_mode_e + mjpeg_q_mode_e. + 0x138 + + + frame_q_mode_e + 0 + 6 + + + + + mjpeg_q_mode_f + mjpeg_q_mode_f. + 0x13C + + + frame_q_mode_f + 0 + 6 + + + + + mjpeg_debug + mjpeg_debug. + 0x1F0 + + + reg_mjpeg_dbg_sel + 4 + 7 + + + reg_mjpeg_dbg_en + 0 + 0 + + + + + mjpeg_dummy_reg + mjpeg_dummy_reg. + 0x1FC + + + mjpeg_dummy_reg + 0 + 31 + + + + + + + sf_ctrl + sf_ctrl. + 0x4000B000 + sf_ctrl + 32 + read-write + + 0 + 0x1000 + registers + + + + sf_ctrl_0 + sf_ctrl_0. + 0x0 + + + sf_id + 24 + 31 + + + sf_aes_iv_endian + 23 + 23 + + + sf_aes_key_endian + 22 + 22 + + + sf_aes_ctr_plus_en + 21 + 21 + + + sf_aes_dout_endian + 20 + 20 + + + sf_aes_dly_mode + 19 + 19 + + + sf_if_int_set + 18 + 18 + + + sf_if_int_clr + 17 + 17 + + + sf_if_int + 16 + 16 + + + sf_if_read_dly_en + 11 + 11 + + + sf_if_read_dly_n + 8 + 10 + + + sf_clk_sahb_sram_sel + 5 + 5 + + + sf_clk_out_inv_sel + 4 + 4 + + + sf_clk_out_gate_en + 3 + 3 + + + sf_clk_sf_rx_inv_sel + 2 + 2 + + + + + sf_ctrl_1 + sf_ctrl_1. + 0x4 + + + sf_ahb2sram_en + 31 + 31 + + + sf_ahb2sif_en + 30 + 30 + + + sf_if_en + 29 + 29 + + + sf_if_fn_sel + 28 + 28 + + + sf_ahb2sif_stop + 27 + 27 + + + sf_ahb2sif_stopped + 26 + 26 + + + sf_if_reg_wp + 25 + 25 + + + sf_if_reg_hold + 24 + 24 + + + sf_if_0_ack_lat + 20 + 22 + + + sf_if_sr_int_set + 18 + 18 + + + sf_if_sr_int_en + 17 + 17 + + + sf_if_sr_int + 16 + 16 + + + sf_if_sr_pat + 8 + 15 + + + sf_if_sr_pat_mask + 0 + 7 + + + + + sf_if_sahb_0 + sf_if_sahb_0. + 0x8 + + + sf_if_0_qpi_mode_en + 31 + 31 + + + sf_if_0_spi_mode + 28 + 30 + + + sf_if_0_cmd_en + 27 + 27 + + + sf_if_0_adr_en + 26 + 26 + + + sf_if_0_dmy_en + 25 + 25 + + + sf_if_0_dat_en + 24 + 24 + + + sf_if_0_dat_rw + 23 + 23 + + + sf_if_0_cmd_byte + 20 + 22 + + + sf_if_0_adr_byte + 17 + 19 + + + sf_if_0_dmy_byte + 12 + 16 + + + sf_if_0_dat_byte + 2 + 11 + + + sf_if_0_trig + 1 + 1 + + + sf_if_busy + 0 + 0 + + + + + sf_if_sahb_1 + sf_if_sahb_1. + 0xC + + + sf_if_0_cmd_buf_0 + 0 + 31 + + + + + sf_if_sahb_2 + sf_if_sahb_2. + 0x10 + + + sf_if_0_cmd_buf_1 + 0 + 31 + + + + + sf_if_iahb_0 + sf_if_iahb_0. + 0x14 + + + sf_if_1_qpi_mode_en + 31 + 31 + + + sf_if_1_spi_mode + 28 + 30 + + + sf_if_1_cmd_en + 27 + 27 + + + sf_if_1_adr_en + 26 + 26 + + + sf_if_1_dmy_en + 25 + 25 + + + sf_if_1_dat_en + 24 + 24 + + + sf_if_1_dat_rw + 23 + 23 + + + sf_if_1_cmd_byte + 20 + 22 + + + sf_if_1_adr_byte + 17 + 19 + + + sf_if_1_dmy_byte + 12 + 16 + + + + + sf_if_iahb_1 + sf_if_iahb_1. + 0x18 + + + sf_if_1_cmd_buf_0 + 0 + 31 + + + + + sf_if_iahb_2 + sf_if_iahb_2. + 0x1C + + + sf_if_1_cmd_buf_1 + 0 + 31 + + + + + sf_if_status_0 + sf_if_status_0. + 0x20 + + + sf_if_status_0 + 0 + 31 + + + + + sf_if_status_1 + sf_if_status_1. + 0x24 + + + sf_if_status_1 + 0 + 31 + + + + + sf_aes + sf_aes. + 0x28 + + + sf_aes_status + 5 + 31 + + + sf_aes_pref_busy + 4 + 4 + + + sf_aes_pref_trig + 3 + 3 + + + sf_aes_mode + 1 + 2 + + + sf_aes_en + 0 + 0 + + + + + sf_ahb2sif_status + sf_ahb2sif_status. + 0x2C + + + sf_ahb2sif_status + 0 + 31 + + + + + sf_if_io_dly_0 + sf_if_io_dly_0. + 0x30 + + + sf_dqs_do_dly_sel + 30 + 31 + + + sf_dqs_di_dly_sel + 28 + 29 + + + sf_dqs_oe_dly_sel + 26 + 27 + + + sf_clk_out_dly_sel + 8 + 9 + + + sf_cs2_dly_sel + 2 + 3 + + + sf_cs_dly_sel + 0 + 1 + + + + + sf_if_io_dly_1 + sf_if_io_dly_1. + 0x34 + + + sf_io_0_do_dly_sel + 16 + 17 + + + sf_io_0_di_dly_sel + 8 + 9 + + + sf_io_0_oe_dly_sel + 0 + 1 + + + + + sf_if_io_dly_2 + sf_if_io_dly_2. + 0x38 + + + sf_io_1_do_dly_sel + 16 + 17 + + + sf_io_1_di_dly_sel + 8 + 9 + + + sf_io_1_oe_dly_sel + 0 + 1 + + + + + sf_if_io_dly_3 + sf_if_io_dly_3. + 0x3C + + + sf_io_2_do_dly_sel + 16 + 17 + + + sf_io_2_di_dly_sel + 8 + 9 + + + sf_io_2_oe_dly_sel + 0 + 1 + + + + + sf_if_io_dly_4 + sf_if_io_dly_4. + 0x40 + + + sf_io_3_do_dly_sel + 16 + 17 + + + sf_io_3_di_dly_sel + 8 + 9 + + + sf_io_3_oe_dly_sel + 0 + 1 + + + + + sf_reserved + sf_reserved. + 0x44 + + + sf_reserved + 0 + 31 + + + + + sf2_if_io_dly_0 + sf2_if_io_dly_0. + 0x48 + + + sf2_dqs_do_dly_sel + 30 + 31 + + + sf2_dqs_di_dly_sel + 28 + 29 + + + sf2_dqs_oe_dly_sel + 26 + 27 + + + sf2_clk_out_dly_sel + 8 + 9 + + + sf2_cs2_dly_sel + 2 + 3 + + + sf2_cs_dly_sel + 0 + 1 + + + + + sf2_if_io_dly_1 + sf2_if_io_dly_1. + 0x4C + + + sf2_io_0_do_dly_sel + 16 + 17 + + + sf2_io_0_di_dly_sel + 8 + 9 + + + sf2_io_0_oe_dly_sel + 0 + 1 + + + + + sf2_if_io_dly_2 + sf2_if_io_dly_2. + 0x50 + + + sf2_io_1_do_dly_sel + 16 + 17 + + + sf2_io_1_di_dly_sel + 8 + 9 + + + sf2_io_1_oe_dly_sel + 0 + 1 + + + + + sf2_if_io_dly_3 + sf2_if_io_dly_3. + 0x54 + + + sf2_io_2_do_dly_sel + 16 + 17 + + + sf2_io_2_di_dly_sel + 8 + 9 + + + sf2_io_2_oe_dly_sel + 0 + 1 + + + + + sf2_if_io_dly_4 + sf2_if_io_dly_4. + 0x58 + + + sf2_io_3_do_dly_sel + 16 + 17 + + + sf2_io_3_di_dly_sel + 8 + 9 + + + sf2_io_3_oe_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_0 + sf3_if_io_dly_0. + 0x5C + + + sf3_dqs_do_dly_sel + 30 + 31 + + + sf3_dqs_di_dly_sel + 28 + 29 + + + sf3_dqs_oe_dly_sel + 26 + 27 + + + sf3_clk_out_dly_sel + 8 + 9 + + + sf3_cs2_dly_sel + 2 + 3 + + + sf3_cs_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_1 + sf3_if_io_dly_1. + 0x60 + + + sf3_io_0_do_dly_sel + 16 + 17 + + + sf3_io_0_di_dly_sel + 8 + 9 + + + sf3_io_0_oe_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_2 + sf3_if_io_dly_2. + 0x64 + + + sf3_io_1_do_dly_sel + 16 + 17 + + + sf3_io_1_di_dly_sel + 8 + 9 + + + sf3_io_1_oe_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_3 + sf3_if_io_dly_3. + 0x68 + + + sf3_io_2_do_dly_sel + 16 + 17 + + + sf3_io_2_di_dly_sel + 8 + 9 + + + sf3_io_2_oe_dly_sel + 0 + 1 + + + + + sf3_if_io_dly_4 + sf3_if_io_dly_4. + 0x6C + + + sf3_io_3_do_dly_sel + 16 + 17 + + + sf3_io_3_di_dly_sel + 8 + 9 + + + sf3_io_3_oe_dly_sel + 0 + 1 + + + + + sf_ctrl_2 + sf_ctrl_2. + 0x70 + + + sf_if_0_bk_sel + 31 + 31 + + + sf_if_bk2_en + 30 + 30 + + + sf_if_bk2_mode + 29 + 29 + + + sf_if_bk_swap + 28 + 28 + + + sf_if_dqs_en + 5 + 5 + + + sf_if_dtr_en + 4 + 4 + + + sf_if_pad_sel_lock + 3 + 3 + + + sf_if_pad_sel + 0 + 1 + + + + + sf_ctrl_3 + sf_ctrl_3. + 0x74 + + + sf_if_1_ack_lat + 29 + 31 + + + sf_cmds_wrap_q + 11 + 11 + + + sf_cmds_wrap_mode + 10 + 10 + + + sf_cmds_wrap_q_ini + 9 + 9 + + + sf_cmds_bt_en + 8 + 8 + + + sf_cmds_bt_dly + 5 + 7 + + + sf_cmds_en + 4 + 4 + + + sf_cmds_wrap_len + 0 + 3 + + + + + sf_if_iahb_3 + sf_if_iahb_3. + 0x78 + + + sf_if_2_qpi_mode_en + 31 + 31 + + + sf_if_2_spi_mode + 28 + 30 + + + sf_if_2_cmd_en + 27 + 27 + + + sf_if_2_adr_en + 26 + 26 + + + sf_if_2_dmy_en + 25 + 25 + + + sf_if_2_dat_en + 24 + 24 + + + sf_if_2_dat_rw + 23 + 23 + + + sf_if_2_cmd_byte + 20 + 22 + + + sf_if_2_adr_byte + 17 + 19 + + + sf_if_2_dmy_byte + 12 + 16 + + + + + sf_if_iahb_4 + sf_if_iahb_4. + 0x7C + + + sf_if_2_cmd_buf_0 + 0 + 31 + + + + + sf_if_iahb_5 + sf_if_iahb_5. + 0x80 + + + sf_if_2_cmd_buf_1 + 0 + 31 + + + + + sf_if_iahb_6 + sf_if_iahb_6. + 0x84 + + + sf_if_3_qpi_mode_en + 31 + 31 + + + sf_if_3_spi_mode + 28 + 30 + + + sf_if_3_cmd_en + 27 + 27 + + + sf_if_3_adr_en + 26 + 26 + + + sf_if_3_cmd_byte + 20 + 22 + + + sf_if_3_adr_byte + 17 + 19 + + + + + sf_if_iahb_7 + sf_if_iahb_7. + 0x88 + + + sf_if_3_cmd_buf_0 + 0 + 31 + + + + + sf_if_iahb_8 + sf_if_iahb_8. + 0x8C + + + sf_if_3_cmd_buf_1 + 0 + 31 + + + + + sf_if_iahb_9 + sf_if_iahb_9. + 0x90 + + + sf_if_4_qpi_mode_en + 31 + 31 + + + sf_if_4_spi_mode + 28 + 30 + + + sf_if_4_cmd_en + 27 + 27 + + + sf_if_4_adr_en + 26 + 26 + + + sf_if_4_dmy_en + 25 + 25 + + + sf_if_4_dat_en + 24 + 24 + + + sf_if_4_dat_rw + 23 + 23 + + + sf_if_4_cmd_byte + 20 + 22 + + + sf_if_4_adr_byte + 17 + 19 + + + sf_if_4_dmy_byte + 12 + 16 + + + + + sf_if_iahb_10 + sf_if_iahb_10. + 0x94 + + + sf_if_4_cmd_buf_0 + 0 + 31 + + + + + sf_if_iahb_11 + sf_if_iahb_11. + 0x98 + + + sf_if_4_cmd_buf_1 + 0 + 31 + + + + + sf_if_iahb_12 + sf_if_iahb_12. + 0x9C + + + sf2_if_read_dly_src + 12 + 12 + + + sf2_if_read_dly_en + 11 + 11 + + + sf2_if_read_dly_n + 8 + 10 + + + sf3_clk_out_inv_sel + 5 + 5 + + + sf2_clk_out_inv_sel + 4 + 4 + + + sf2_clk_sf_rx_inv_src + 3 + 3 + + + sf2_clk_sf_rx_inv_sel + 2 + 2 + + + + + sf_ctrl_prot_en_rd + sf_ctrl_prot_en_rd. + 0x100 + + + sf_dbg_dis + 31 + 31 + + + sf_if_0_trig_wr_lock + 30 + 30 + + + sf_ctrl_id1_en_rd + 2 + 2 + + + sf_ctrl_id0_en_rd + 1 + 1 + + + sf_ctrl_prot_en_rd + 0 + 0 + + + + + sf_ctrl_prot_en + sf_ctrl_prot_en. + 0x104 + + + sf_ctrl_id1_en + 2 + 2 + + + sf_ctrl_id0_en + 1 + 1 + + + sf_ctrl_prot_en + 0 + 0 + + + + + sf_aes_key_r0_0 + sf_aes_key_r0_0. + 0x200 + + + sf_aes_key_r0_0 + 0 + 31 + + + + + sf_aes_key_r0_1 + sf_aes_key_r0_1. + 0x204 + + + sf_aes_key_r0_1 + 0 + 31 + + + + + sf_aes_key_r0_2 + sf_aes_key_r0_2. + 0x208 + + + sf_aes_key_r0_2 + 0 + 31 + + + + + sf_aes_key_r0_3 + sf_aes_key_r0_3. + 0x20C + + + sf_aes_key_r0_3 + 0 + 31 + + + + + sf_aes_key_r0_4 + sf_aes_key_r0_4. + 0x210 + + + sf_aes_key_r0_4 + 0 + 31 + + + + + sf_aes_key_r0_5 + sf_aes_key_r0_5. + 0x214 + + + sf_aes_key_r0_5 + 0 + 31 + + + + + sf_aes_key_r0_6 + sf_aes_key_r0_6. + 0x218 + + + sf_aes_key_r0_6 + 0 + 31 + + + + + sf_aes_key_r0_7 + sf_aes_key_r0_7. + 0x21C + + + sf_aes_key_r0_7 + 0 + 31 + + + + + sf_aes_iv_r0_w0 + sf_aes_iv_r0_w0. + 0x220 + + + sf_aes_iv_r0_w0 + 0 + 31 + + + + + sf_aes_iv_r0_w1 + sf_aes_iv_r0_w1. + 0x224 + + + sf_aes_iv_r0_w1 + 0 + 31 + + + + + sf_aes_iv_r0_w2 + sf_aes_iv_r0_w2. + 0x228 + + + sf_aes_iv_r0_w2 + 0 + 31 + + + + + sf_aes_iv_r0_w3 + sf_aes_iv_r0_w3. + 0x22C + + + sf_aes_iv_r0_w3 + 0 + 31 + + + + + sf_aes_cfg_r0 + sf_aes_cfg_r0. + 0x230 + + + sf_aes_region_r0_lock + 31 + 31 + + + sf_aes_region_r0_en + 30 + 30 + + + sf_aes_region_r0_hw_key_en + 29 + 29 + + + sf_aes_region_r0_start + 14 + 27 + + + sf_aes_region_r0_end + 0 + 13 + + + + + sf_aes_key_r1_0 + sf_aes_key_r1_0. + 0x300 + + + sf_aes_key_r1_0 + 0 + 31 + + + + + sf_aes_key_r1_1 + sf_aes_key_r1_1. + 0x304 + + + sf_aes_key_r1_1 + 0 + 31 + + + + + sf_aes_key_r1_2 + sf_aes_key_r1_2. + 0x308 + + + sf_aes_key_r1_2 + 0 + 31 + + + + + sf_aes_key_r1_3 + sf_aes_key_r1_3. + 0x30C + + + sf_aes_key_r1_3 + 0 + 31 + + + + + sf_aes_key_r1_4 + sf_aes_key_r1_4. + 0x310 + + + sf_aes_key_r1_4 + 0 + 31 + + + + + sf_aes_key_r1_5 + sf_aes_key_r1_5. + 0x314 + + + sf_aes_key_r1_5 + 0 + 31 + + + + + sf_aes_key_r1_6 + sf_aes_key_r1_6. + 0x318 + + + sf_aes_key_r1_6 + 0 + 31 + + + + + sf_aes_key_r1_7 + sf_aes_key_r1_7. + 0x31C + + + sf_aes_key_r1_7 + 0 + 31 + + + + + sf_aes_iv_r1_w0 + sf_aes_iv_r1_w0. + 0x320 + + + sf_aes_iv_r1_w0 + 0 + 31 + + + + + sf_aes_iv_r1_w1 + sf_aes_iv_r1_w1. + 0x324 + + + sf_aes_iv_r1_w1 + 0 + 31 + + + + + sf_aes_iv_r1_w2 + sf_aes_iv_r1_w2. + 0x328 + + + sf_aes_iv_r1_w2 + 0 + 31 + + + + + sf_aes_iv_r1_w3 + sf_aes_iv_r1_w3. + 0x32C + + + sf_aes_iv_r1_w3 + 0 + 31 + + + + + sf_aes_r1 + sf_aes_r1. + 0x330 + + + sf_aes_r1_lock + 31 + 31 + + + sf_aes_r1_en + 30 + 30 + + + sf_aes_r1_hw_key_en + 29 + 29 + + + sf_aes_r1_start + 14 + 27 + + + sf_aes_r1_end + 0 + 13 + + + + + sf_aes_key_r2_0 + sf_aes_key_r2_0. + 0x400 + + + sf_aes_key_r2_0 + 0 + 31 + + + + + sf_aes_key_r2_1 + sf_aes_key_r2_1. + 0x404 + + + sf_aes_key_r2_1 + 0 + 31 + + + + + sf_aes_key_r2_2 + sf_aes_key_r2_2. + 0x408 + + + sf_aes_key_r2_2 + 0 + 31 + + + + + sf_aes_key_r2_3 + sf_aes_key_r2_3. + 0x40C + + + sf_aes_key_r2_3 + 0 + 31 + + + + + sf_aes_key_r2_4 + sf_aes_key_r2_4. + 0x410 + + + sf_aes_key_r2_4 + 0 + 31 + + + + + sf_aes_key_r2_5 + sf_aes_key_r2_5. + 0x414 + + + sf_aes_key_r2_5 + 0 + 31 + + + + + sf_aes_key_r2_6 + sf_aes_key_r2_6. + 0x418 + + + sf_aes_key_r2_6 + 0 + 31 + + + + + sf_aes_key_r2_7 + sf_aes_key_r2_7. + 0x41C + + + sf_aes_key_r2_7 + 0 + 31 + + + + + sf_aes_iv_r2_w0 + sf_aes_iv_r2_w0. + 0x420 + + + sf_aes_iv_r2_w0 + 0 + 31 + + + + + sf_aes_iv_r2_w1 + sf_aes_iv_r2_w1. + 0x424 + + + sf_aes_iv_r2_w1 + 0 + 31 + + + + + sf_aes_iv_r2_w2 + sf_aes_iv_r2_w2. + 0x428 + + + sf_aes_iv_r2_w2 + 0 + 31 + + + + + sf_aes_iv_r2_w3 + sf_aes_iv_r2_w3. + 0x42C + + + sf_aes_iv_r2_w3 + 0 + 31 + + + + + sf_aes_r2 + sf_aes_r2. + 0x430 + + + sf_aes_r2_lock + 31 + 31 + + + sf_aes_r2_en + 30 + 30 + + + sf_aes_r2_hw_key_en + 29 + 29 + + + sf_aes_r2_start + 14 + 27 + + + sf_aes_r2_end + 0 + 13 + + + + + sf_id0_offset + sf_id0_offset. + 0x434 + + + sf_id0_offset + 0 + 23 + + + + + sf_id1_offset + sf_id1_offset. + 0x438 + + + sf_id1_offset + 0 + 23 + + + + + sf_bk2_id0_offset + sf_bk2_id0_offset. + 0x43C + + + sf_bk2_id0_offset + 0 + 23 + + + + + sf_bk2_id1_offset + sf_bk2_id1_offset. + 0x440 + + + sf_bk2_id1_offset + 0 + 23 + + + + + + + dma + dma. + 0x40007000 + dma + 32 + read-write + + 0 + 0x1000 + registers + + + + DMA_IntStatus + DMA_IntStatus. + 0x0 + + + IntStatus + 0 + 7 + + + + + DMA_IntTCStatus + DMA_IntTCStatus. + 0x4 + + + IntTCStatus + 0 + 7 + + + + + DMA_IntTCClear + DMA_IntTCClear. + 0x8 + + + IntTCClear + 0 + 7 + + + + + DMA_IntErrorStatus + DMA_IntErrorStatus. + 0xC + + + IntErrorStatus + 0 + 7 + + + + + DMA_IntErrClr + DMA_IntErrClr. + 0x10 + + + IntErrClr + 0 + 7 + + + + + DMA_RawIntTCStatus + DMA_RawIntTCStatus. + 0x14 + + + RawIntTCStatus + 0 + 7 + + + + + DMA_RawIntErrorStatus + DMA_RawIntErrorStatus. + 0x18 + + + RawIntErrorStatus + 0 + 7 + + + + + DMA_EnbldChns + DMA_EnbldChns. + 0x1C + + + EnabledChannels + 0 + 7 + + + + + DMA_SoftBReq + DMA_SoftBReq. + 0x20 + + + SoftBReq + 0 + 31 + + + + + DMA_SoftSReq + DMA_SoftSReq. + 0x24 + + + SoftSReq + 0 + 31 + + + + + DMA_SoftLBReq + DMA_SoftLBReq. + 0x28 + + + SoftLBReq + 0 + 31 + + + + + DMA_SoftLSReq + DMA_SoftLSReq. + 0x2C + + + SoftLSReq + 0 + 31 + + + + + DMA_Top_Config + DMA_Top_Config. + 0x30 + + + M + 1 + 1 + + + E + 0 + 0 + + + + + DMA_Sync + DMA_Sync. + 0x34 + + + DMA_Sync + 0 + 31 + + + + + DMA_C0SrcAddr + DMA_C0SrcAddr. + 0x100 + + + SrcAddr + 0 + 31 + + + + + DMA_C0DstAddr + DMA_C0DstAddr. + 0x104 + + + DstAddr + 0 + 31 + + + + + DMA_C0LLI + DMA_C0LLI. + 0x108 + + + LLI + 0 + 31 + + + + + DMA_C0Control + DMA_C0Control. + 0x10C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + SLargerD + 25 + 25 + + + fix_cnt + 23 + 24 + + + DWidth + 21 + 22 + + + SWidth + 18 + 19 + + + dst_add_mode + 17 + 17 + + + DBSize + 15 + 16 + + + dst_min_mode + 14 + 14 + + + SBSize + 12 + 13 + + + TransferSize + 0 + 11 + + + + + DMA_C0Config + DMA_C0Config. + 0x110 + + + LLICounter + 20 + 29 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C1SrcAddr + DMA_C1SrcAddr. + 0x200 + + + SrcAddr + 0 + 31 + + + + + DMA_C1DstAddr + DMA_C1DstAddr. + 0x204 + + + DstAddr + 0 + 31 + + + + + DMA_C1LLI + DMA_C1LLI. + 0x208 + + + LLI + 2 + 31 + + + + + DMA_C1Control + DMA_C1Control. + 0x20C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + fix_cnt + 23 + 24 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + dst_add_mode + 17 + 17 + + + DBSize + 15 + 16 + + + dst_min_mode + 14 + 14 + + + SBSize + 12 + 13 + + + TransferSize + 0 + 11 + + + + + DMA_C1Config + DMA_C1Config. + 0x210 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C2SrcAddr + DMA_C2SrcAddr. + 0x300 + + + SrcAddr + 0 + 31 + + + + + DMA_C2DstAddr + DMA_C2DstAddr. + 0x304 + + + DstAddr + 0 + 31 + + + + + DMA_C2LLI + DMA_C2LLI. + 0x308 + + + LLI + 2 + 31 + + + + + DMA_C2Control + DMA_C2Control. + 0x30C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + fix_cnt + 23 + 24 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + dst_add_mode + 17 + 17 + + + DBSize + 15 + 16 + + + dst_min_mode + 14 + 14 + + + SBSize + 12 + 13 + + + TransferSize + 0 + 11 + + + + + DMA_C2Config + DMA_C2Config. + 0x310 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C3SrcAddr + DMA_C3SrcAddr. + 0x400 + + + SrcAddr + 0 + 31 + + + + + DMA_C3DstAddr + DMA_C3DstAddr. + 0x404 + + + DstAddr + 0 + 31 + + + + + DMA_C3LLI + DMA_C3LLI. + 0x408 + + + LLI + 2 + 31 + + + + + DMA_C3Control + DMA_C3Control. + 0x40C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + fix_cnt + 23 + 24 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + dst_add_mode + 17 + 17 + + + DBSize + 15 + 16 + + + dst_min_mode + 14 + 14 + + + SBSize + 12 + 13 + + + TransferSize + 0 + 11 + + + + + DMA_C3Config + DMA_C3Config. + 0x410 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C4SrcAddr + DMA_C4SrcAddr. + 0x500 + + + SrcAddr + 0 + 31 + + + + + DMA_C4DstAddr + DMA_C4DstAddr. + 0x504 + + + DstAddr + 0 + 31 + + + + + DMA_C4LLI + DMA_C4LLI. + 0x508 + + + LLI + 2 + 31 + + + + + DMA_C4Control + DMA_C4Control. + 0x50C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + fix_cnt + 23 + 24 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + dst_add_mode + 17 + 17 + + + DBSize + 15 + 16 + + + dst_min_mode + 14 + 14 + + + SBSize + 12 + 13 + + + TransferSize + 0 + 11 + + + + + DMA_C4Config + DMA_C4Config. + 0x510 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C5SrcAddr + DMA_C5SrcAddr. + 0x600 + + + SrcAddr + 0 + 31 + + + + + DMA_C5DstAddr + DMA_C5DstAddr. + 0x604 + + + DstAddr + 0 + 31 + + + + + DMA_C5LLI + DMA_C5LLI. + 0x608 + + + LLI + 2 + 31 + + + + + DMA_C5Control + DMA_C5Control. + 0x60C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + fix_cnt + 23 + 24 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + dst_add_mode + 17 + 17 + + + DBSize + 15 + 16 + + + dst_min_mode + 14 + 14 + + + SBSize + 12 + 13 + + + TransferSize + 0 + 11 + + + + + DMA_C5Config + DMA_C5Config. + 0x610 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C6SrcAddr + DMA_C6SrcAddr. + 0x700 + + + SrcAddr + 0 + 31 + + + + + DMA_C6DstAddr + DMA_C6DstAddr. + 0x704 + + + DstAddr + 0 + 31 + + + + + DMA_C6LLI + DMA_C6LLI. + 0x708 + + + LLI + 2 + 31 + + + + + DMA_C6Control + DMA_C6Control. + 0x70C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + fix_cnt + 23 + 24 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + dst_add_mode + 17 + 17 + + + DBSize + 15 + 16 + + + dst_min_mode + 14 + 14 + + + SBSize + 12 + 13 + + + TransferSize + 0 + 11 + + + + + DMA_C6Config + DMA_C6Config. + 0x710 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + DMA_C7SrcAddr + DMA_C7SrcAddr. + 0x800 + + + SrcAddr + 0 + 31 + + + + + DMA_C7DstAddr + DMA_C7DstAddr. + 0x804 + + + DstAddr + 0 + 31 + + + + + DMA_C7LLI + DMA_C7LLI. + 0x808 + + + LLI + 2 + 31 + + + + + DMA_C7Control + DMA_C7Control. + 0x80C + + + I + 31 + 31 + + + Prot + 28 + 30 + + + DI + 27 + 27 + + + SI + 26 + 26 + + + fix_cnt + 23 + 24 + + + DWidth + 21 + 23 + + + SWidth + 18 + 20 + + + dst_add_mode + 17 + 17 + + + DBSize + 15 + 16 + + + dst_min_mode + 14 + 14 + + + SBSize + 12 + 13 + + + TransferSize + 0 + 11 + + + + + DMA_C7Config + DMA_C7Config. + 0x810 + + + H + 18 + 18 + + + A + 17 + 17 + + + L + 16 + 16 + + + ITC + 15 + 15 + + + IE + 14 + 14 + + + FlowCntrl + 11 + 13 + + + DstPeripheral + 6 + 10 + + + SrcPeripheral + 1 + 5 + + + E + 0 + 0 + + + + + + + emac + emac. + 0x4000D000 + emac + 32 + read-write + + 0 + 0x1000 + registers + + + + MODE + MODE. + 0x0 + + + rsvd_23_18 + 18 + 23 + + + RMII_EN + 17 + 17 + + + RECSMALL + 16 + 16 + + + PAD + 15 + 15 + + + HUGEN + 14 + 14 + + + CRCEN + 13 + 13 + + + rsvd_12_11 + 11 + 12 + + + FULLD + 10 + 10 + + + rsvd_9_7 + 7 + 9 + + + IFG + 6 + 6 + + + PRO + 5 + 5 + + + rsvd_4 + 4 + 4 + + + BRO + 3 + 3 + + + NOPRE + 2 + 2 + + + TXEN + 1 + 1 + + + RXEN + 0 + 0 + + + + + INT_SOURCE + INT_SOURCE. + 0x4 + + + RXC + 6 + 6 + + + TXC + 5 + 5 + + + BUSY + 4 + 4 + + + RXE + 3 + 3 + + + RXB + 2 + 2 + + + TXE + 1 + 1 + + + TXB + 0 + 0 + + + + + INT_MASK + INT_MASK. + 0x8 + + + RXC_M + 6 + 6 + + + TXC_M + 5 + 5 + + + BUSY_M + 4 + 4 + + + RXE_M + 3 + 3 + + + RXB_M + 2 + 2 + + + TXE_M + 1 + 1 + + + TXB_M + 0 + 0 + + + + + IPGT + IPGT. + 0xC + + + IPGT + 0 + 6 + + + + + PACKETLEN + PACKETLEN. + 0x18 + + + MINFL + 16 + 31 + + + MAXFL + 0 + 15 + + + + + COLLCONFIG + COLLCONFIG. + 0x1C + + + MAXRET + 16 + 19 + + + COLLVALID + 0 + 5 + + + + + TX_BD_NUM + TX_BD_NUM. + 0x20 + + + RXBDPTR + 24 + 30 + + + TXBDPTR + 16 + 22 + + + TXBDNUM + 0 + 7 + + + + + MIIMODE + MIIMODE. + 0x28 + + + MIINOPRE + 8 + 8 + + + CLKDIV + 0 + 7 + + + + + MIICOMMAND + MIICOMMAND. + 0x2C + + + WCTRLDATA + 2 + 2 + + + RSTAT + 1 + 1 + + + SCANSTAT + 0 + 0 + + + + + MIIADDRESS + MIIADDRESS. + 0x30 + + + RGAD + 8 + 12 + + + FIAD + 0 + 4 + + + + + MIITX_DATA + MIITX_DATA. + 0x34 + + + CTRLDATA + 0 + 15 + + + + + MIIRX_DATA + MIIRX_DATA. + 0x38 + + + PRSD + 0 + 15 + + + + + MIISTATUS + MIISTATUS. + 0x3C + + + MIIM_BUSY + 1 + 1 + + + MIIM_LINKFAIL + 0 + 0 + + + + + MAC_ADDR0 + MAC_ADDR0. + 0x40 + + + MAC_B2 + 24 + 31 + + + MAC_B3 + 16 + 23 + + + MAC_B4 + 8 + 15 + + + MAC_B5 + 0 + 7 + + + + + MAC_ADDR1 + MAC_ADDR1. + 0x44 + + + MAC_B0 + 8 + 15 + + + MAC_B1 + 0 + 7 + + + + + HASH0_ADDR + HASH0_ADDR. + 0x48 + + + HASH0 + 0 + 31 + + + + + HASH1_ADDR + HASH1_ADDR. + 0x4C + + + HASH1 + 0 + 31 + + + + + TXCTRL + TXCTRL. + 0x50 + + + TXPAUSERQ + 16 + 16 + + + TXPAUSETV + 0 + 15 + + + + + + + usb + usb. + 0x4000D800 + usb + 32 + read-write + + 0 + 0x1000 + registers + + + + usb_config + usb_config. + 0x0 + + + sts_usb_ep0_sw_rdy + 28 + 28 + + + cr_usb_ep0_sw_rdy + 27 + 27 + + + cr_usb_ep0_sw_nack_out + 26 + 26 + + + cr_usb_ep0_sw_nack_in + 25 + 25 + + + cr_usb_ep0_sw_stall + 24 + 24 + + + cr_usb_ep0_sw_size + 16 + 23 + + + cr_usb_ep0_sw_addr + 9 + 15 + + + cr_usb_ep0_sw_ctrl + 8 + 8 + + + cr_usb_rom_dct_en + 4 + 4 + + + cr_usb_en + 0 + 0 + + + + + usb_lpm_config + usb_lpm_config. + 0x4 + + + sts_lpm + 31 + 31 + + + sts_lpm_attr + 20 + 30 + + + cr_lpm_resp + 2 + 3 + + + cr_lpm_resp_upd + 1 + 1 + + + cr_lpm_en + 0 + 0 + + + + + usb_resume_config + usb_resume_config. + 0x8 + + + cr_res_force + 31 + 31 + + + cr_res_trig + 12 + 12 + + + cr_res_width + 0 + 10 + + + + + usb_setup_data_0 + usb_setup_data_0. + 0x10 + + + sts_setup_data_b3 + 24 + 31 + + + sts_setup_data_b2 + 16 + 23 + + + sts_setup_data_b1 + 8 + 15 + + + sts_setup_data_b0 + 0 + 7 + + + + + usb_setup_data_1 + usb_setup_data_1. + 0x14 + + + sts_setup_data_b7 + 24 + 31 + + + sts_setup_data_b6 + 16 + 23 + + + sts_setup_data_b5 + 8 + 15 + + + sts_setup_data_b4 + 0 + 7 + + + + + usb_frame_no + usb_frame_no. + 0x18 + + + sts_ep_no + 16 + 19 + + + sts_pid + 12 + 15 + + + sts_frame_no + 0 + 10 + + + + + usb_error + usb_error. + 0x1C + + + crc16_err + 6 + 6 + + + crc5_err + 5 + 5 + + + pid_cks_err + 4 + 4 + + + pid_seq_err + 3 + 3 + + + ivld_ep_err + 2 + 2 + + + xfer_to_err + 1 + 1 + + + utmi_rx_err + 0 + 0 + + + + + usb_int_en + USB interrupt enable + 0x20 + + + cr_usb_err_en + 31 + 31 + + + cr_sof_3ms_en + 30 + 30 + + + cr_lpm_pkt_en + 29 + 29 + + + cr_lpm_wkup_en + 28 + 28 + + + rsvd_27_24 + 24 + 27 + + + cr_ep7_done_en + 23 + 23 + + + cr_ep7_cmd_en + 22 + 22 + + + cr_ep6_done_en + 21 + 21 + + + cr_ep6_cmd_en + 20 + 20 + + + cr_ep5_done_en + 19 + 19 + + + cr_ep5_cmd_en + 18 + 18 + + + cr_ep4_done_en + 17 + 17 + + + cr_ep4_cmd_en + 16 + 16 + + + cr_ep3_done_en + 15 + 15 + + + cr_ep3_cmd_en + 14 + 14 + + + cr_ep2_done_en + 13 + 13 + + + cr_ep2_cmd_en + 12 + 12 + + + cr_ep1_done_en + 11 + 11 + + + cr_ep1_cmd_en + 10 + 10 + + + cr_ep0_out_done_en + 9 + 9 + + + cr_ep0_out_cmd_en + 8 + 8 + + + cr_ep0_in_done_en + 7 + 7 + + + cr_ep0_in_cmd_en + 6 + 6 + + + cr_ep0_setup_done_en + 5 + 5 + + + cr_ep0_setup_cmd_en + 4 + 4 + + + cr_get_dct_cmd_en + 3 + 3 + + + cr_vbus_tgl_en + 2 + 2 + + + cr_usb_reset_en + 1 + 1 + + + cr_sof_en + 0 + 0 + + + + + usb_int_sts + USB interrupt status + 0x24 + + + usb_err_int + 31 + 31 + + + sof_3ms_int + 30 + 30 + + + lpm_pkt_int + 29 + 29 + + + lpm_wkup_int + 28 + 28 + + + rsvd_27_24 + 24 + 27 + + + ep7_done_int + 23 + 23 + + + ep7_cmd_int + 22 + 22 + + + ep6_done_int + 21 + 21 + + + ep6_cmd_int + 20 + 20 + + + ep5_done_int + 19 + 19 + + + ep5_cmd_int + 18 + 18 + + + ep4_done_int + 17 + 17 + + + ep4_cmd_int + 16 + 16 + + + ep3_done_int + 15 + 15 + + + ep3_cmd_int + 14 + 14 + + + ep2_done_int + 13 + 13 + + + ep2_cmd_int + 12 + 12 + + + ep1_done_int + 11 + 11 + + + ep1_cmd_int + 10 + 10 + + + ep0_out_done_int + 9 + 9 + + + ep0_out_cmd_int + 8 + 8 + + + ep0_in_done_int + 7 + 7 + + + ep0_in_cmd_int + 6 + 6 + + + ep0_setup_done_int + 5 + 5 + + + ep0_setup_cmd_int + 4 + 4 + + + get_dct_cmd_int + 3 + 3 + + + vbus_tgl_int + 2 + 2 + + + usb_reset_int + 1 + 1 + + + sof_int + 0 + 0 + + + + + usb_int_mask + USB interrupt mask + 0x28 + + + cr_usb_err_mask + 31 + 31 + + + cr_sof_3ms_mask + 30 + 30 + + + cr_lpm_pkt_mask + 29 + 29 + + + cr_lpm_wkup_mask + 28 + 28 + + + rsvd_27_24 + 24 + 27 + + + cr_ep7_done_mask + 23 + 23 + + + cr_ep7_cmd_mask + 22 + 22 + + + cr_ep6_done_mask + 21 + 21 + + + cr_ep6_cmd_mask + 20 + 20 + + + cr_ep5_done_mask + 19 + 19 + + + cr_ep5_cmd_mask + 18 + 18 + + + cr_ep4_done_mask + 17 + 17 + + + cr_ep4_cmd_mask + 16 + 16 + + + cr_ep3_done_mask + 15 + 15 + + + cr_ep3_cmd_mask + 14 + 14 + + + cr_ep2_done_mask + 13 + 13 + + + cr_ep2_cmd_mask + 12 + 12 + + + cr_ep1_done_mask + 11 + 11 + + + cr_ep1_cmd_mask + 10 + 10 + + + cr_ep0_out_done_mask + 9 + 9 + + + cr_ep0_out_cmd_mask + 8 + 8 + + + cr_ep0_in_done_mask + 7 + 7 + + + cr_ep0_in_cmd_mask + 6 + 6 + + + cr_ep0_setup_done_mask + 5 + 5 + + + cr_ep0_setup_cmd_mask + 4 + 4 + + + cr_get_dct_cmd_mask + 3 + 3 + + + cr_vbus_tgl_mask + 2 + 2 + + + cr_usb_reset_mask + 1 + 1 + + + cr_sof_mask + 0 + 0 + + + + + usb_int_clear + USB interrupt clear + 0x2C + + + cr_usb_err_clr + 31 + 31 + + + cr_sof_3ms_clr + 30 + 30 + + + cr_lpm_pkt_clr + 29 + 29 + + + cr_lpm_wkup_clr + 28 + 28 + + + rsvd_27_24 + 24 + 27 + + + cr_ep7_done_clr + 23 + 23 + + + cr_ep7_cmd_clr + 22 + 22 + + + cr_ep6_done_clr + 21 + 21 + + + cr_ep6_cmd_clr + 20 + 20 + + + cr_ep5_done_clr + 19 + 19 + + + cr_ep5_cmd_clr + 18 + 18 + + + cr_ep4_done_clr + 17 + 17 + + + cr_ep4_cmd_clr + 16 + 16 + + + cr_ep3_done_clr + 15 + 15 + + + cr_ep3_cmd_clr + 14 + 14 + + + cr_ep2_done_clr + 13 + 13 + + + cr_ep2_cmd_clr + 12 + 12 + + + cr_ep1_done_clr + 11 + 11 + + + cr_ep1_cmd_clr + 10 + 10 + + + cr_ep0_out_done_clr + 9 + 9 + + + cr_ep0_out_cmd_clr + 8 + 8 + + + cr_ep0_in_done_clr + 7 + 7 + + + cr_ep0_in_cmd_clr + 6 + 6 + + + cr_ep0_setup_done_clr + 5 + 5 + + + cr_ep0_setup_cmd_clr + 4 + 4 + + + cr_get_dct_cmd_clr + 3 + 3 + + + cr_vbus_tgl_clr + 2 + 2 + + + cr_usb_reset_clr + 1 + 1 + + + cr_sof_clr + 0 + 0 + + + + + ep1_config + ep1_config. + 0x40 + + + sts_ep1_rdy + 19 + 19 + + + cr_ep1_rdy + 18 + 18 + + + cr_ep1_nack + 17 + 17 + + + cr_ep1_stall + 16 + 16 + + + cr_ep1_type + 13 + 15 + + + cr_ep1_dir + 11 + 12 + + + cr_ep1_size + 0 + 10 + + + + + ep2_config + ep2_config. + 0x44 + + + sts_ep2_rdy + 19 + 19 + + + cr_ep2_rdy + 18 + 18 + + + cr_ep2_nack + 17 + 17 + + + cr_ep2_stall + 16 + 16 + + + cr_ep2_type + 13 + 15 + + + cr_ep2_dir + 11 + 12 + + + cr_ep2_size + 0 + 10 + + + + + ep3_config + ep3_config. + 0x48 + + + sts_ep3_rdy + 19 + 19 + + + cr_ep3_rdy + 18 + 18 + + + cr_ep3_nack + 17 + 17 + + + cr_ep3_stall + 16 + 16 + + + cr_ep3_type + 13 + 15 + + + cr_ep3_dir + 11 + 12 + + + cr_ep3_size + 0 + 10 + + + + + ep4_config + ep4_config. + 0x4C + + + sts_ep4_rdy + 19 + 19 + + + cr_ep4_rdy + 18 + 18 + + + cr_ep4_nack + 17 + 17 + + + cr_ep4_stall + 16 + 16 + + + cr_ep4_type + 13 + 15 + + + cr_ep4_dir + 11 + 12 + + + cr_ep4_size + 0 + 10 + + + + + ep5_config + ep5_config. + 0x50 + + + sts_ep5_rdy + 19 + 19 + + + cr_ep5_rdy + 18 + 18 + + + cr_ep5_nack + 17 + 17 + + + cr_ep5_stall + 16 + 16 + + + cr_ep5_type + 13 + 15 + + + cr_ep5_dir + 11 + 12 + + + cr_ep5_size + 0 + 10 + + + + + ep6_config + ep6_config. + 0x54 + + + sts_ep6_rdy + 19 + 19 + + + cr_ep6_rdy + 18 + 18 + + + cr_ep6_nack + 17 + 17 + + + cr_ep6_stall + 16 + 16 + + + cr_ep6_type + 13 + 15 + + + cr_ep6_dir + 11 + 12 + + + cr_ep6_size + 0 + 10 + + + + + ep7_config + ep7_config. + 0x58 + + + sts_ep7_rdy + 19 + 19 + + + cr_ep7_rdy + 18 + 18 + + + cr_ep7_nack + 17 + 17 + + + cr_ep7_stall + 16 + 16 + + + cr_ep7_type + 13 + 15 + + + cr_ep7_dir + 11 + 12 + + + cr_ep7_size + 0 + 10 + + + + + ep0_fifo_config + ep0_fifo_config. + 0x100 + + + ep0_rx_fifo_underflow + 7 + 7 + + + ep0_rx_fifo_overflow + 6 + 6 + + + ep0_tx_fifo_underflow + 5 + 5 + + + ep0_tx_fifo_overflow + 4 + 4 + + + ep0_rx_fifo_clr + 3 + 3 + + + ep0_tx_fifo_clr + 2 + 2 + + + ep0_dma_rx_en + 1 + 1 + + + ep0_dma_tx_en + 0 + 0 + + + + + ep0_fifo_status + ep0_fifo_status. + 0x104 + + + ep0_rx_fifo_full + 31 + 31 + + + ep0_rx_fifo_empty + 30 + 30 + + + ep0_rx_fifo_cnt + 16 + 22 + + + ep0_tx_fifo_full + 15 + 15 + + + ep0_tx_fifo_empty + 14 + 14 + + + ep0_tx_fifo_cnt + 0 + 6 + + + + + ep0_tx_fifo_wdata + ep0_tx_fifo_wdata. + 0x108 + + + ep0_tx_fifo_wdata + 0 + 7 + + + + + ep0_rx_fifo_rdata + ep0_rx_fifo_rdata. + 0x10C + + + ep0_rx_fifo_rdata + 0 + 7 + + + + + ep1_fifo_config + ep1_fifo_config. + 0x110 + + + ep1_rx_fifo_underflow + 7 + 7 + + + ep1_rx_fifo_overflow + 6 + 6 + + + ep1_tx_fifo_underflow + 5 + 5 + + + ep1_tx_fifo_overflow + 4 + 4 + + + ep1_rx_fifo_clr + 3 + 3 + + + ep1_tx_fifo_clr + 2 + 2 + + + ep1_dma_rx_en + 1 + 1 + + + ep1_dma_tx_en + 0 + 0 + + + + + ep1_fifo_status + ep1_fifo_status. + 0x114 + + + ep1_rx_fifo_full + 31 + 31 + + + ep1_rx_fifo_empty + 30 + 30 + + + ep1_rx_fifo_cnt + 16 + 22 + + + ep1_tx_fifo_full + 15 + 15 + + + ep1_tx_fifo_empty + 14 + 14 + + + ep1_tx_fifo_cnt + 0 + 6 + + + + + ep1_tx_fifo_wdata + ep1_tx_fifo_wdata. + 0x118 + + + ep1_tx_fifo_wdata + 0 + 7 + + + + + ep1_rx_fifo_rdata + ep1_rx_fifo_rdata. + 0x11C + + + ep1_rx_fifo_rdata + 0 + 7 + + + + + ep2_fifo_config + ep2_fifo_config. + 0x120 + + + ep2_rx_fifo_underflow + 7 + 7 + + + ep2_rx_fifo_overflow + 6 + 6 + + + ep2_tx_fifo_underflow + 5 + 5 + + + ep2_tx_fifo_overflow + 4 + 4 + + + ep2_rx_fifo_clr + 3 + 3 + + + ep2_tx_fifo_clr + 2 + 2 + + + ep2_dma_rx_en + 1 + 1 + + + ep2_dma_tx_en + 0 + 0 + + + + + ep2_fifo_status + ep2_fifo_status. + 0x124 + + + ep2_rx_fifo_full + 31 + 31 + + + ep2_rx_fifo_empty + 30 + 30 + + + ep2_rx_fifo_cnt + 16 + 22 + + + ep2_tx_fifo_full + 15 + 15 + + + ep2_tx_fifo_empty + 14 + 14 + + + ep2_tx_fifo_cnt + 0 + 6 + + + + + ep2_tx_fifo_wdata + ep2_tx_fifo_wdata. + 0x128 + + + ep2_tx_fifo_wdata + 0 + 7 + + + + + ep2_rx_fifo_rdata + ep2_rx_fifo_rdata. + 0x12C + + + ep2_rx_fifo_rdata + 0 + 7 + + + + + ep3_fifo_config + ep3_fifo_config. + 0x130 + + + ep3_rx_fifo_underflow + 7 + 7 + + + ep3_rx_fifo_overflow + 6 + 6 + + + ep3_tx_fifo_underflow + 5 + 5 + + + ep3_tx_fifo_overflow + 4 + 4 + + + ep3_rx_fifo_clr + 3 + 3 + + + ep3_tx_fifo_clr + 2 + 2 + + + ep3_dma_rx_en + 1 + 1 + + + ep3_dma_tx_en + 0 + 0 + + + + + ep3_fifo_status + ep3_fifo_status. + 0x134 + + + ep3_rx_fifo_full + 31 + 31 + + + ep3_rx_fifo_empty + 30 + 30 + + + ep3_rx_fifo_cnt + 16 + 22 + + + ep3_tx_fifo_full + 15 + 15 + + + ep3_tx_fifo_empty + 14 + 14 + + + ep3_tx_fifo_cnt + 0 + 6 + + + + + ep3_tx_fifo_wdata + ep3_tx_fifo_wdata. + 0x138 + + + ep3_tx_fifo_wdata + 0 + 7 + + + + + ep3_rx_fifo_rdata + ep3_rx_fifo_rdata. + 0x13C + + + ep3_rx_fifo_rdata + 0 + 7 + + + + + ep4_fifo_config + ep4_fifo_config. + 0x140 + + + ep4_rx_fifo_underflow + 7 + 7 + + + ep4_rx_fifo_overflow + 6 + 6 + + + ep4_tx_fifo_underflow + 5 + 5 + + + ep4_tx_fifo_overflow + 4 + 4 + + + ep4_rx_fifo_clr + 3 + 3 + + + ep4_tx_fifo_clr + 2 + 2 + + + ep4_dma_rx_en + 1 + 1 + + + ep4_dma_tx_en + 0 + 0 + + + + + ep4_fifo_status + ep4_fifo_status. + 0x144 + + + ep4_rx_fifo_full + 31 + 31 + + + ep4_rx_fifo_empty + 30 + 30 + + + ep4_rx_fifo_cnt + 16 + 22 + + + ep4_tx_fifo_full + 15 + 15 + + + ep4_tx_fifo_empty + 14 + 14 + + + ep4_tx_fifo_cnt + 0 + 6 + + + + + ep4_tx_fifo_wdata + ep4_tx_fifo_wdata. + 0x148 + + + ep4_tx_fifo_wdata + 0 + 7 + + + + + ep4_rx_fifo_rdata + ep4_rx_fifo_rdata. + 0x14C + + + ep4_rx_fifo_rdata + 0 + 7 + + + + + ep5_fifo_config + ep5_fifo_config. + 0x150 + + + ep5_rx_fifo_underflow + 7 + 7 + + + ep5_rx_fifo_overflow + 6 + 6 + + + ep5_tx_fifo_underflow + 5 + 5 + + + ep5_tx_fifo_overflow + 4 + 4 + + + ep5_rx_fifo_clr + 3 + 3 + + + ep5_tx_fifo_clr + 2 + 2 + + + ep5_dma_rx_en + 1 + 1 + + + ep5_dma_tx_en + 0 + 0 + + + + + ep5_fifo_status + ep5_fifo_status. + 0x154 + + + ep5_rx_fifo_full + 31 + 31 + + + ep5_rx_fifo_empty + 30 + 30 + + + ep5_rx_fifo_cnt + 16 + 22 + + + ep5_tx_fifo_full + 15 + 15 + + + ep5_tx_fifo_empty + 14 + 14 + + + ep5_tx_fifo_cnt + 0 + 6 + + + + + ep5_tx_fifo_wdata + ep5_tx_fifo_wdata. + 0x158 + + + ep5_tx_fifo_wdata + 0 + 7 + + + + + ep5_rx_fifo_rdata + ep5_rx_fifo_rdata. + 0x15C + + + ep5_rx_fifo_rdata + 0 + 7 + + + + + ep6_fifo_config + ep6_fifo_config. + 0x160 + + + ep6_rx_fifo_underflow + 7 + 7 + + + ep6_rx_fifo_overflow + 6 + 6 + + + ep6_tx_fifo_underflow + 5 + 5 + + + ep6_tx_fifo_overflow + 4 + 4 + + + ep6_rx_fifo_clr + 3 + 3 + + + ep6_tx_fifo_clr + 2 + 2 + + + ep6_dma_rx_en + 1 + 1 + + + ep6_dma_tx_en + 0 + 0 + + + + + ep6_fifo_status + ep6_fifo_status. + 0x164 + + + ep6_rx_fifo_full + 31 + 31 + + + ep6_rx_fifo_empty + 30 + 30 + + + ep6_rx_fifo_cnt + 16 + 22 + + + ep6_tx_fifo_full + 15 + 15 + + + ep6_tx_fifo_empty + 14 + 14 + + + ep6_tx_fifo_cnt + 0 + 6 + + + + + ep6_tx_fifo_wdata + ep6_tx_fifo_wdata. + 0x168 + + + ep6_tx_fifo_wdata + 0 + 7 + + + + + ep6_rx_fifo_rdata + ep6_rx_fifo_rdata. + 0x16C + + + ep6_rx_fifo_rdata + 0 + 7 + + + + + ep7_fifo_config + ep7_fifo_config. + 0x170 + + + ep7_rx_fifo_underflow + 7 + 7 + + + ep7_rx_fifo_overflow + 6 + 6 + + + ep7_tx_fifo_underflow + 5 + 5 + + + ep7_tx_fifo_overflow + 4 + 4 + + + ep7_rx_fifo_clr + 3 + 3 + + + ep7_tx_fifo_clr + 2 + 2 + + + ep7_dma_rx_en + 1 + 1 + + + ep7_dma_tx_en + 0 + 0 + + + + + ep7_fifo_status + ep7_fifo_status. + 0x174 + + + ep7_rx_fifo_full + 31 + 31 + + + ep7_rx_fifo_empty + 30 + 30 + + + ep7_rx_fifo_cnt + 16 + 22 + + + ep7_tx_fifo_full + 15 + 15 + + + ep7_tx_fifo_empty + 14 + 14 + + + ep7_tx_fifo_cnt + 0 + 6 + + + + + ep7_tx_fifo_wdata + ep7_tx_fifo_wdata. + 0x178 + + + ep7_tx_fifo_wdata + 0 + 7 + + + + + ep7_rx_fifo_rdata + ep7_rx_fifo_rdata. + 0x17C + + + ep7_rx_fifo_rdata + 0 + 7 + + + + + rsvd_0 + rsvd_0. + 0x1F0 + + + rsvd_0 + 0 + 31 + + + + + rsvd_1 + rsvd_1. + 0x1F4 + + + rsvd_1 + 0 + 31 + + + + + xcvr_if_config + xcvr_if_config. + 0x1FC + + + sts_vbus_det + 31 + 31 + + + cr_xcvr_om_rx_dn + 11 + 11 + + + cr_xcvr_om_rx_dp + 10 + 10 + + + cr_xcvr_om_rx_d + 9 + 9 + + + cr_xcvr_om_rx_sel + 8 + 8 + + + cr_xcvr_force_rx_dn + 7 + 7 + + + cr_xcvr_force_rx_dp + 6 + 6 + + + cr_xcvr_force_rx_d + 5 + 5 + + + cr_xcvr_force_rx_en + 4 + 4 + + + cr_xcvr_force_tx_dn + 3 + 3 + + + cr_xcvr_force_tx_dp + 2 + 2 + + + cr_xcvr_force_tx_oe + 1 + 1 + + + cr_xcvr_force_tx_en + 0 + 0 + + + + + + + pds + pds. + 0x4000E000 + pds + 32 + read-write + + 0 + 0x1000 + registers + + + + PDS_CTL + PDS_CTL. + 0x0 + + + cr_pds_ctrl_pll + 30 + 31 + + + cr_pds_ctrl_rf + 28 + 29 + + + cr_pds_ldo_vol + 24 + 27 + + + cr_pds_force_ram_clk_en + 23 + 23 + + + cr_pds_pd_ldo11 + 22 + 22 + + + cr_np_wfi_mask + 21 + 21 + + + cr_pds_ram_lp_with_clk_en + 19 + 19 + + + cr_pds_ldo_vsel_en + 18 + 18 + + + cr_pds_rc32m_off_dis + 17 + 17 + + + cr_pds_rst_soc_en + 16 + 16 + + + cr_pds_soc_enb_force_on + 15 + 15 + + + cr_pds_pd_xtal + 14 + 14 + + + cr_pds_pwr_off + 13 + 13 + + + cr_pds_wait_xtal_rdy + 12 + 12 + + + cr_pds_iso_en + 11 + 11 + + + cr_sw_pu_flash + 10 + 10 + + + cr_pds_mem_stby + 9 + 9 + + + cr_pds_gate_clk + 8 + 8 + + + cr_pds_ctrl_pu_flash + 7 + 7 + + + cr_pds_ctrl_gpio_ie_pu_pd + 6 + 6 + + + cr_pds_pd_bg_sys + 5 + 5 + + + cr_pds_pd_dcdc18 + 4 + 4 + + + cr_wifi_pds_save_state + 3 + 3 + + + cr_xtal_force_off + 2 + 2 + + + cr_sleep_forever + 1 + 1 + + + pds_start_ps + 0 + 0 + + + + + PDS_TIME1 + PDS_TIME1. + 0x4 + + + cr_sleep_duration + 0 + 31 + + + + + PDS_INT + PDS_INT. + 0xC + + + ro_pds_wakeup_event + 24 + 31 + + + cr_pds_wakeup_src_en + 16 + 23 + + + cr_pds_int_clr + 15 + 15 + + + cr_pds_pll_done_int_mask + 11 + 11 + + + cr_pds_rf_done_int_mask + 10 + 10 + + + cr_pds_wake_int_mask + 8 + 8 + + + pds_clr_reset_event + 7 + 7 + + + pds_reset_event + 4 + 6 + + + ro_pds_pll_done_int + 3 + 3 + + + ro_pds_rf_done_int + 2 + 2 + + + ro_pds_wake_int + 0 + 0 + + + + + PDS_CTL2 + PDS_CTL2. + 0x10 + + + cr_pds_force_usb_gate_clk + 19 + 19 + + + cr_pds_force_bz_gate_clk + 18 + 18 + + + cr_pds_force_np_gate_clk + 16 + 16 + + + cr_pds_force_usb_mem_stby + 15 + 15 + + + cr_pds_force_bz_mem_stby + 14 + 14 + + + cr_pds_force_np_mem_stby + 12 + 12 + + + cr_pds_force_usb_pds_rst + 11 + 11 + + + cr_pds_force_bz_pds_rst + 10 + 10 + + + cr_pds_force_np_pds_rst + 8 + 8 + + + cr_pds_force_usb_iso_en + 7 + 7 + + + cr_pds_force_bz_iso_en + 6 + 6 + + + cr_pds_force_np_iso_en + 4 + 4 + + + cr_pds_force_usb_pwr_off + 3 + 3 + + + cr_pds_force_bz_pwr_off + 2 + 2 + + + cr_pds_force_np_pwr_off + 0 + 0 + + + + + PDS_CTL3 + PDS_CTL3. + 0x14 + + + cr_pds_misc_iso_en + 30 + 30 + + + cr_pds_usb_iso_en + 29 + 29 + + + cr_pds_ble_iso_en + 28 + 28 + + + cr_pds_bz_iso_en + 27 + 27 + + + cr_pds_np_iso_en + 24 + 24 + + + cr_pds_force_ble_gate_clk + 14 + 14 + + + cr_pds_force_misc_gate_clk + 13 + 13 + + + cr_pds_force_ble_mem_stby + 11 + 11 + + + cr_pds_force_misc_mem_stby + 10 + 10 + + + cr_pds_force_ble_pds_rst + 8 + 8 + + + cr_pds_force_misc_pds_rst + 7 + 7 + + + cr_pds_force_ble_iso_en + 5 + 5 + + + cr_pds_force_ble_pwr_off + 2 + 2 + + + cr_pds_force_misc_pwr_off + 1 + 1 + + + + + PDS_CTL4 + PDS_CTL4. + 0x18 + + + cr_pds_misc_dig_pwr_off + 31 + 31 + + + cr_pds_misc_ana_pwr_off + 30 + 30 + + + cr_pds_misc_gate_clk + 27 + 27 + + + cr_pds_misc_mem_stby + 26 + 26 + + + cr_pds_misc_reset + 25 + 25 + + + cr_pds_misc_pwr_off + 24 + 24 + + + cr_pds_usb_gate_clk + 23 + 23 + + + cr_pds_usb_mem_stby + 22 + 22 + + + cr_pds_usb_reset + 21 + 21 + + + cr_pds_usb_pwr_off + 20 + 20 + + + cr_pds_ble_gate_clk + 19 + 19 + + + cr_pds_ble_mem_stby + 18 + 18 + + + cr_pds_ble_reset + 17 + 17 + + + cr_pds_ble_pwr_off + 16 + 16 + + + cr_pds_bz_gate_clk + 15 + 15 + + + cr_pds_bz_mem_stby + 14 + 14 + + + cr_pds_bz_reset + 13 + 13 + + + cr_pds_bz_pwr_off + 12 + 12 + + + cr_pds_np_gate_clk + 3 + 3 + + + cr_pds_np_mem_stby + 2 + 2 + + + cr_pds_np_reset + 1 + 1 + + + cr_pds_np_pwr_off + 0 + 0 + + + + + pds_stat + pds_stat. + 0x1C + + + ro_pds_pll_state + 16 + 17 + + + ro_pds_rf_state + 8 + 11 + + + ro_pds_state + 0 + 3 + + + + + pds_ram1 + pds_ram1. + 0x20 + + + cr_pds_ram_pgen + 8 + 11 + + + cr_pds_ram_ret2n + 4 + 7 + + + cr_pds_ram_ret1n + 0 + 3 + + + + + pds_gpio_set_pu_pd + pds_gpio_set_pu_pd. + 0x30 + + + cr_pds_gpio_28_23_pu + 24 + 29 + + + cr_pds_gpio_28_23_pd + 16 + 21 + + + cr_pds_gpio_22_17_pu + 8 + 13 + + + cr_pds_gpio_22_17_pd + 0 + 5 + + + + + pds_gpio_int + pds_gpio_int. + 0x40 + + + pds_gpio_int_select + 8 + 10 + + + pds_gpio_int_mode + 4 + 6 + + + pds_gpio_int_clr + 2 + 2 + + + pds_gpio_int_stat + 1 + 1 + + + pds_gpio_int_mask + 0 + 0 + + + + + rc32m_ctrl0 + rc32m_ctrl0. + 0x300 + + + rc32m_code_fr_ext + 22 + 29 + + + rc32m_pd + 21 + 21 + + + rc32m_cal_en + 20 + 20 + + + rc32m_ext_code_en + 19 + 19 + + + rc32m_refclk_half + 18 + 18 + + + rc32m_allow_cal + 17 + 17 + + + rc32m_dig_code_fr_cal + 6 + 13 + + + rc32m_cal_precharge + 5 + 5 + + + rc32m_cal_div + 3 + 4 + + + rc32m_cal_inprogress + 2 + 2 + + + rc32m_rdy + 1 + 1 + + + rc32m_cal_done + 0 + 0 + + + + + rc32m_ctrl1 + rc32m_ctrl1. + 0x304 + + + rc32m_reserved + 24 + 31 + + + rc32m_clk_force_on + 4 + 4 + + + rc32m_clk_inv + 3 + 3 + + + rc32m_clk_soft_rst + 2 + 2 + + + rc32m_soft_rst + 1 + 1 + + + rc32m_test_en + 0 + 0 + + + + + pu_rst_clkpll + pu_rst_clkpll. + 0x400 + + + pu_clkpll + 10 + 10 + + + pu_clkpll_sfreg + 9 + 9 + + + clkpll_pu_cp + 8 + 8 + + + clkpll_pu_pfd + 7 + 7 + + + clkpll_pu_clamp_op + 6 + 6 + + + clkpll_pu_fbdv + 5 + 5 + + + clkpll_pu_postdiv + 4 + 4 + + + clkpll_reset_refdiv + 3 + 3 + + + clkpll_reset_fbdv + 2 + 2 + + + clkpll_reset_postdiv + 1 + 1 + + + clkpll_sdm_reset + 0 + 0 + + + + + clkpll_top_ctrl + clkpll_top_ctrl. + 0x404 + + + clkpll_resv + 24 + 25 + + + clkpll_vg11_sel + 20 + 21 + + + clkpll_refclk_sel + 16 + 16 + + + clkpll_xtal_rc32m_sel + 12 + 12 + + + clkpll_refdiv_ratio + 8 + 11 + + + clkpll_postdiv + 0 + 6 + + + + + clkpll_cp + clkpll_cp. + 0x408 + + + clkpll_cp_opamp_en + 10 + 10 + + + clkpll_cp_startup_en + 9 + 9 + + + clkpll_int_frac_sw + 8 + 8 + + + clkpll_icp_1u + 6 + 7 + + + clkpll_icp_5u + 4 + 5 + + + clkpll_sel_cp_bias + 0 + 0 + + + + + clkpll_rz + clkpll_rz. + 0x40C + + + clkpll_rz + 16 + 18 + + + clkpll_cz + 14 + 15 + + + clkpll_c3 + 12 + 13 + + + clkpll_r4_short + 8 + 8 + + + clkpll_r4 + 4 + 5 + + + clkpll_c4_en + 0 + 0 + + + + + clkpll_fbdv + clkpll_fbdv. + 0x410 + + + clkpll_sel_fb_clk + 2 + 3 + + + clkpll_sel_sample_clk + 0 + 1 + + + + + clkpll_vco + clkpll_vco. + 0x414 + + + clkpll_shrtr + 3 + 3 + + + clkpll_vco_speed + 0 + 2 + + + + + clkpll_sdm + clkpll_sdm. + 0x418 + + + clkpll_sdm_bypass + 29 + 29 + + + clkpll_sdm_flag + 28 + 28 + + + clkpll_dither_sel + 24 + 25 + + + clkpll_sdmin + 0 + 23 + + + + + clkpll_output_en + clkpll_output_en. + 0x41C + + + clkpll_en_div2_480m + 9 + 9 + + + clkpll_en_32m + 8 + 8 + + + clkpll_en_48m + 7 + 7 + + + clkpll_en_80m + 6 + 6 + + + clkpll_en_96m + 5 + 5 + + + clkpll_en_120m + 4 + 4 + + + clkpll_en_160m + 3 + 3 + + + clkpll_en_192m + 2 + 2 + + + clkpll_en_240m + 1 + 1 + + + clkpll_en_480m + 0 + 0 + + + + + clkpll_test_enable + clkpll_test_enable. + 0x420 + + + clkpll_dc_tp_out_en + 8 + 8 + + + ten_clkpll + 7 + 7 + + + ten_clkpll_sfreg + 6 + 6 + + + dten_clkpll_fin + 5 + 5 + + + dten_clkpll_fref + 4 + 4 + + + dten_clkpll_fsdm + 3 + 3 + + + dten_clk32M + 2 + 2 + + + dten_clk96M + 1 + 1 + + + dten_clkpll_postdiv_clk + 0 + 0 + + + + + + + HBN + HBN. + 0x4000F000 + HBN + 32 + read-write + + 0 + 0x1000 + registers + + + + HBN_CTL + HBN_CTL. + 0x0 + + + hbn_state + 28 + 31 + + + sram_slp + 27 + 27 + + + sram_slp_option + 26 + 26 + + + pwr_on_option + 25 + 25 + + + rtc_dly_option + 24 + 24 + + + pu_dcdc18_aon + 23 + 23 + + + hbn_ldo11_aon_vout_sel + 19 + 22 + + + hbn_ldo11_rt_vout_sel + 15 + 18 + + + hbn_dis_pwr_off_ldo11_rt + 14 + 14 + + + hbn_dis_pwr_off_ldo11 + 13 + 13 + + + sw_rst + 12 + 12 + + + pwrdn_hbn_rtc + 11 + 11 + + + pwrdn_hbn_core + 9 + 9 + + + trap_mode + 8 + 8 + + + hbn_mode + 7 + 7 + + + rtc_ctl + 0 + 6 + + + + + HBN_TIME_L + HBN_TIME_L. + 0x4 + + + hbn_time_l + 0 + 31 + + + + + HBN_TIME_H + HBN_TIME_H. + 0x8 + + + hbn_time_h + 0 + 7 + + + + + RTC_TIME_L + RTC_TIME_L. + 0xC + + + rtc_time_latch_l + 0 + 31 + + + + + RTC_TIME_H + RTC_TIME_H. + 0x10 + + + rtc_time_latch + 31 + 31 + + + rtc_time_latch_h + 0 + 7 + + + + + HBN_IRQ_MODE + HBN_IRQ_MODE. + 0x14 + + + pin_wakeup_en + 27 + 27 + + + pin_wakeup_sel + 24 + 26 + + + irq_acomp1_en + 22 + 23 + + + irq_acomp0_en + 20 + 21 + + + irq_bor_en + 18 + 18 + + + reg_en_hw_pu_pd + 16 + 16 + + + reg_aon_pad_ie_smt + 8 + 12 + + + hbn_pin_wakeup_mask + 3 + 7 + + + hbn_pin_wakeup_mode + 0 + 2 + + + + + HBN_IRQ_STAT + HBN_IRQ_STAT. + 0x18 + + + irq_stat + 0 + 31 + + + + + HBN_IRQ_CLR + HBN_IRQ_CLR. + 0x1C + + + irq_clr + 0 + 31 + + + + + HBN_PIR_CFG + HBN_PIR_CFG. + 0x20 + + + gpadc_nosync + 9 + 9 + + + gpadc_cgen + 8 + 8 + + + pir_en + 7 + 7 + + + pir_dis + 4 + 5 + + + pir_lpf_sel + 2 + 2 + + + pir_hpf_sel + 0 + 1 + + + + + HBN_PIR_VTH + HBN_PIR_VTH. + 0x24 + + + pir_vth + 0 + 13 + + + + + HBN_PIR_INTERVAL + HBN_PIR_INTERVAL. + 0x28 + + + pir_interval + 0 + 11 + + + + + HBN_MISC + HBN_MISC. + 0x2C + + + hbn_flash_pulldown_aon + 24 + 29 + + + hbn_flash_pullup_aon + 16 + 21 + + + r_bor_out + 3 + 3 + + + pu_bor + 2 + 2 + + + bor_vth + 1 + 1 + + + bor_sel + 0 + 0 + + + + + HBN_GLB + HBN_GLB. + 0x30 + + + sw_ldo11_aon_vout_sel + 28 + 31 + + + sw_ldo11_rt_vout_sel + 24 + 27 + + + sw_ldo11soc_vout_sel_aon + 16 + 19 + + + hbn_clear_reset_event + 13 + 13 + + + hbn_reset_event + 8 + 12 + + + ldo11_rt_iload_sel + 6 + 7 + + + hbn_pu_rc32k + 5 + 5 + + + hbn_f32k_sel + 3 + 4 + + + hbn_uart_clk_sel + 2 + 2 + + + hbn_root_clk_sel + 0 + 1 + + + + + HBN_SRAM + HBN_SRAM. + 0x34 + + + retram_slp + 7 + 7 + + + retram_ret + 6 + 6 + + + retram_emaw + 3 + 4 + + + retram_ema + 0 + 2 + + + + + HBN_RSV0 + HBN_RSV0. + 0x100 + + + HBN_RSV0 + 0 + 31 + + + + + HBN_RSV1 + HBN_RSV1. + 0x104 + + + HBN_RSV1 + 0 + 31 + + + + + HBN_RSV2 + HBN_RSV2. + 0x108 + + + HBN_RSV2 + 0 + 31 + + + + + HBN_RSV3 + HBN_RSV3. + 0x10C + + + HBN_RSV3 + 0 + 31 + + + + + rc32k_ctrl0 + rc32k_ctrl0. + 0x200 + + + rc32k_code_fr_ext + 22 + 31 + + + rc32k_cal_en + 20 + 20 + + + rc32k_ext_code_en + 19 + 19 + + + rc32k_allow_cal + 18 + 18 + + + rc32k_vref_dly + 16 + 17 + + + rc32k_dig_code_fr_cal + 6 + 15 + + + rc32k_cal_precharge + 5 + 5 + + + rc32k_cal_div + 3 + 4 + + + rc32k_cal_inprogress + 2 + 2 + + + rc32k_rdy + 1 + 1 + + + rc32k_cal_done + 0 + 0 + + + + + xtal32k + xtal32k. + 0x204 + + + pu_xtal32k + 19 + 19 + + + pu_xtal32k_buf + 18 + 18 + + + xtal32k_ac_cap_short + 17 + 17 + + + xtal32k_capbank + 11 + 16 + + + xtal32k_inv_stre + 9 + 10 + + + xtal32k_otf_short + 8 + 8 + + + xtal32k_outbuf_stre + 7 + 7 + + + xtal32k_reg + 5 + 6 + + + xtal32k_amp_ctrl + 3 + 4 + + + xtal32k_ext_sel + 2 + 2 + + + xtal32k_lowv_en + 1 + 1 + + + xtal32k_hiz_en + 0 + 0 + + + + + + + AON + AON. + + AON + 32 + read-write + + 0 + 0x1000 + registers + + + + aon + aon. + 0x800 + + + sw_pu_ldo11_rt + 22 + 22 + + + ldo11_rt_pulldown_sel + 21 + 21 + + + ldo11_rt_pulldown + 20 + 20 + + + pu_aon_dc_tbuf + 12 + 12 + + + aon_resv + 0 + 7 + + + + + aon_common + aon_common. + 0x804 + + + ten_cip_misc_aon + 20 + 20 + + + ten_mbg_aon + 19 + 19 + + + dten_xtal_aon + 18 + 18 + + + ten_xtal_aon + 17 + 17 + + + ten_ldo15rf_aon + 16 + 16 + + + ten_bg_sys_aon + 12 + 12 + + + ten_dcdc18_1_aon + 11 + 11 + + + ten_dcdc18_0_aon + 10 + 10 + + + ten_ldo11soc_aon + 9 + 9 + + + ten_vddcore_aon + 8 + 8 + + + ten_xtal32k + 6 + 6 + + + dten_xtal32k + 5 + 5 + + + ten_aon + 4 + 4 + + + tmux_aon + 0 + 2 + + + + + aon_misc + aon_misc. + 0x808 + + + sw_bz_en_aon + 1 + 1 + + + sw_soc_en_aon + 0 + 0 + + + + + bg_sys_top + bg_sys_top. + 0x810 + + + bg_sys_start_ctrl_aon + 12 + 12 + + + pu_bg_sys_aon + 8 + 8 + + + pmip_resv + 0 + 7 + + + + + dcdc18_top_0 + dcdc18_top_0. + 0x814 + + + dcdc18_rdy_aon + 31 + 31 + + + dcdc18_sstart_time_aon + 28 + 29 + + + dcdc18_osc_inhibit_t2_aon + 27 + 27 + + + dcdc18_slow_osc_aon + 26 + 26 + + + dcdc18_stop_osc_aon + 25 + 25 + + + dcdc18_slope_curr_sel_aon + 20 + 24 + + + dcdc18_osc_freq_trim_aon + 16 + 19 + + + dcdc18_osc_2m_mode_aon + 12 + 12 + + + dcdc18_vpfm_aon + 8 + 11 + + + dcdc18_vout_sel_aon + 1 + 5 + + + + + dcdc18_top_1 + dcdc18_top_1. + 0x818 + + + dcdc18_pulldown_aon + 29 + 29 + + + dcdc18_en_antiring_aon + 28 + 28 + + + dcdc18_cfb_sel_aon + 24 + 27 + + + dcdc18_chf_sel_aon + 20 + 23 + + + dcdc18_rc_sel_aon + 16 + 19 + + + dcdc18_nonoverlap_td_aon + 8 + 12 + + + dcdc18_zvs_td_opt_aon + 4 + 6 + + + dcdc18_cs_delay_aon + 1 + 3 + + + dcdc18_force_cs_zvs_aon + 0 + 0 + + + + + ldo11soc_and_dctest + ldo11soc_and_dctest. + 0x81C + + + pmip_dc_tp_out_en_aon + 31 + 31 + + + pu_vddcore_misc_aon + 30 + 30 + + + ldo11soc_power_good_aon + 29 + 29 + + + ldo11soc_rdy_aon + 28 + 28 + + + ldo11soc_cc_aon + 24 + 25 + + + ldo11soc_vth_sel_aon + 12 + 13 + + + ldo11soc_pulldown_sel_aon + 11 + 11 + + + ldo11soc_pulldown_aon + 10 + 10 + + + ldo11soc_sstart_delay_aon + 8 + 9 + + + ldo11soc_sstart_sel_aon + 4 + 4 + + + pu_ldo11soc_aon + 0 + 0 + + + + + psw_irrcv + psw_irrcv. + 0x820 + + + pu_ir_psw_aon + 0 + 0 + + + + + rf_top_aon + rf_top_aon. + 0x880 + + + ldo15rf_bypass_aon + 28 + 28 + + + ldo15rf_cc_aon + 24 + 25 + + + ldo15rf_vout_sel_aon + 16 + 18 + + + ldo15rf_pulldown_sel_aon + 13 + 13 + + + ldo15rf_pulldown_aon + 12 + 12 + + + ldo15rf_sstart_delay_aon + 9 + 10 + + + ldo15rf_sstart_sel_aon + 8 + 8 + + + pu_xtal_aon + 5 + 5 + + + pu_xtal_buf_aon + 4 + 4 + + + pu_sfreg_aon + 2 + 2 + + + pu_ldo15rf_aon + 1 + 1 + + + pu_mbg_aon + 0 + 0 + + + + + xtal_cfg + xtal_cfg. + 0x884 + + + xtal_rdy_sel_aon + 30 + 31 + + + xtal_gm_boost_aon + 28 + 29 + + + xtal_capcode_in_aon + 22 + 27 + + + xtal_capcode_out_aon + 16 + 21 + + + xtal_amp_ctrl_aon + 14 + 15 + + + xtal_sleep_aon + 13 + 13 + + + xtal_fast_startup_aon + 12 + 12 + + + xtal_buf_hp_aon + 8 + 11 + + + xtal_buf_en_aon + 4 + 7 + + + xtal_ext_sel_aon + 3 + 3 + + + xtal_capcode_extra_aon + 2 + 2 + + + xtal_bk_aon + 0 + 1 + + + + + tsen + tsen. + 0x888 + + + xtal_rdy_int_sel_aon + 30 + 31 + + + xtal_inn_cfg_en_aon + 29 + 29 + + + xtal_rdy + 28 + 28 + + + tsen_refcode_rfcal + 16 + 27 + + + tsen_refcode_corner + 0 + 11 + + + + + acomp0_ctrl + acomp0_ctrl. + 0x900 + + + acomp0_muxen + 26 + 26 + + + acomp0_pos_sel + 22 + 25 + + + acomp0_neg_sel + 18 + 21 + + + acomp0_level_sel + 12 + 17 + + + acomp0_bias_prog + 10 + 11 + + + acomp0_hyst_selp + 7 + 9 + + + acomp0_hyst_seln + 4 + 6 + + + acomp0_en + 0 + 0 + + + + + acomp1_ctrl + acomp1_ctrl. + 0x904 + + + acomp1_muxen + 26 + 26 + + + acomp1_pos_sel + 22 + 25 + + + acomp1_neg_sel + 18 + 21 + + + acomp1_level_sel + 12 + 17 + + + acomp1_bias_prog + 10 + 11 + + + acomp1_hyst_selp + 7 + 9 + + + acomp1_hyst_seln + 4 + 6 + + + acomp1_en + 0 + 0 + + + + + acomp_ctrl + acomp_ctrl. + 0x908 + + + acomp_reserved + 24 + 31 + + + acomp0_out_raw + 19 + 19 + + + acomp1_out_raw + 17 + 17 + + + acomp0_test_sel + 12 + 13 + + + acomp1_test_sel + 10 + 11 + + + acomp0_test_en + 9 + 9 + + + acomp1_test_en + 8 + 8 + + + acomp0_rstn_ana + 1 + 1 + + + acomp1_rstn_ana + 0 + 0 + + + + + gpadc_reg_cmd + gpadc_reg_cmd. + 0x90C + + + gpadc_sen_test_en + 30 + 30 + + + gpadc_sen_sel + 28 + 29 + + + gpadc_chip_sen_pu + 27 + 27 + + + gpadc_micboost_32db_en + 23 + 23 + + + gpadc_mic_pga2_gain + 21 + 22 + + + gpadc_mic1_diff + 20 + 20 + + + gpadc_mic2_diff + 19 + 19 + + + gpadc_dwa_en + 18 + 18 + + + gpadc_byp_micboost + 16 + 16 + + + gpadc_micpga_en + 15 + 15 + + + gpadc_micbias_en + 14 + 14 + + + gpadc_neg_gnd + 13 + 13 + + + gpadc_pos_sel + 8 + 12 + + + gpadc_neg_sel + 3 + 7 + + + gpadc_soft_rst + 2 + 2 + + + gpadc_conv_start + 1 + 1 + + + gpadc_global_en + 0 + 0 + + + + + gpadc_reg_config1 + gpadc_reg_config1. + 0x910 + + + gpadc_v18_sel + 29 + 30 + + + gpadc_v11_sel + 27 + 28 + + + gpadc_dither_en + 26 + 26 + + + gpadc_scan_en + 25 + 25 + + + gpadc_scan_length + 21 + 24 + + + gpadc_clk_div_ratio + 18 + 20 + + + gpadc_clk_ana_inv + 17 + 17 + + + gpadc_lowv_det_en + 10 + 10 + + + gpadc_vcm_hyst_sel + 9 + 9 + + + gpadc_vcm_sel_en + 8 + 8 + + + gpadc_res_sel + 2 + 4 + + + gpadc_cont_conv_en + 1 + 1 + + + gpadc_cal_os_en + 0 + 0 + + + + + gpadc_reg_config2 + gpadc_reg_config2. + 0x914 + + + gpadc_tsvbe_low + 31 + 31 + + + gpadc_dly_sel + 28 + 30 + + + gpadc_pga1_gain + 25 + 27 + + + gpadc_pga2_gain + 22 + 24 + + + gpadc_test_sel + 19 + 21 + + + gpadc_test_en + 18 + 18 + + + gpadc_bias_sel + 17 + 17 + + + gpadc_chop_mode + 15 + 16 + + + gpadc_pga_vcmi_en + 14 + 14 + + + gpadc_pga_en + 13 + 13 + + + gpadc_pga_os_cal + 9 + 12 + + + gpadc_pga_vcm + 7 + 8 + + + gpadc_ts_en + 6 + 6 + + + gpadc_tsext_sel + 5 + 5 + + + gpadc_vbat_en + 4 + 4 + + + gpadc_vref_sel + 3 + 3 + + + gpadc_diff_mode + 2 + 2 + + + + + gpadc_reg_scn_pos1 + adc converation sequence 1 + 0x918 + + + gpadc_scan_pos_5 + 25 + 29 + + + gpadc_scan_pos_4 + 20 + 24 + + + gpadc_scan_pos_3 + 15 + 19 + + + gpadc_scan_pos_2 + 10 + 14 + + + gpadc_scan_pos_1 + 5 + 9 + + + gpadc_scan_pos_0 + 0 + 4 + + + + + gpadc_reg_scn_pos2 + adc converation sequence 2 + 0x91C + + + gpadc_scan_pos_11 + 25 + 29 + + + gpadc_scan_pos_10 + 20 + 24 + + + gpadc_scan_pos_9 + 15 + 19 + + + gpadc_scan_pos_8 + 10 + 14 + + + gpadc_scan_pos_7 + 5 + 9 + + + gpadc_scan_pos_6 + 0 + 4 + + + + + gpadc_reg_scn_neg1 + adc converation sequence 3 + 0x920 + + + gpadc_scan_neg_5 + 25 + 29 + + + gpadc_scan_neg_4 + 20 + 24 + + + gpadc_scan_neg_3 + 15 + 19 + + + gpadc_scan_neg_2 + 10 + 14 + + + gpadc_scan_neg_1 + 5 + 9 + + + gpadc_scan_neg_0 + 0 + 4 + + + + + gpadc_reg_scn_neg2 + adc converation sequence 4 + 0x924 + + + gpadc_scan_neg_11 + 25 + 29 + + + gpadc_scan_neg_10 + 20 + 24 + + + gpadc_scan_neg_9 + 15 + 19 + + + gpadc_scan_neg_8 + 10 + 14 + + + gpadc_scan_neg_7 + 5 + 9 + + + gpadc_scan_neg_6 + 0 + 4 + + + + + gpadc_reg_status + gpadc_reg_status. + 0x928 + + + gpadc_reserved + 16 + 31 + + + gpadc_data_rdy + 0 + 0 + + + + + gpadc_reg_isr + gpadc_reg_isr. + 0x92C + + + gpadc_pos_satur_mask + 9 + 9 + + + gpadc_neg_satur_mask + 8 + 8 + + + gpadc_pos_satur_clr + 5 + 5 + + + gpadc_neg_satur_clr + 4 + 4 + + + gpadc_pos_satur + 1 + 1 + + + gpadc_neg_satur + 0 + 0 + + + + + gpadc_reg_result + gpadc_reg_result. + 0x930 + + + gpadc_data_out + 0 + 25 + + + + + gpadc_reg_raw_result + gpadc_reg_raw_result. + 0x934 + + + gpadc_raw_data + 0 + 11 + + + + + gpadc_reg_define + gpadc_reg_define. + 0x938 + + + gpadc_os_cal_data + 0 + 15 + + + + + hbncore_resv0 + hbncore_resv0. + 0x93C + + + hbncore_resv0_data + 0 + 31 + + + + + hbncore_resv1 + hbncore_resv1. + 0x940 + + + hbncore_resv1_data + 0 + 31 + + + + + + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/spi_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/spi_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..0ad7b7d9b23d9b55108c2cb974a9b9005c0466e8 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/spi_reg.h @@ -0,0 +1,521 @@ +/** + ****************************************************************************** + * @file spi_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +#include "bl702.h" + +/* 0x0 : spi_config */ +#define SPI_CONFIG_OFFSET (0x0) +#define SPI_CR_SPI_M_EN SPI_CR_SPI_M_EN +#define SPI_CR_SPI_M_EN_POS (0U) +#define SPI_CR_SPI_M_EN_LEN (1U) +#define SPI_CR_SPI_M_EN_MSK (((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS) +#define SPI_CR_SPI_M_EN_UMSK (~(((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS)) +#define SPI_CR_SPI_S_EN SPI_CR_SPI_S_EN +#define SPI_CR_SPI_S_EN_POS (1U) +#define SPI_CR_SPI_S_EN_LEN (1U) +#define SPI_CR_SPI_S_EN_MSK (((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS) +#define SPI_CR_SPI_S_EN_UMSK (~(((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS)) +#define SPI_CR_SPI_FRAME_SIZE SPI_CR_SPI_FRAME_SIZE +#define SPI_CR_SPI_FRAME_SIZE_POS (2U) +#define SPI_CR_SPI_FRAME_SIZE_LEN (2U) +#define SPI_CR_SPI_FRAME_SIZE_MSK (((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS) +#define SPI_CR_SPI_FRAME_SIZE_UMSK (~(((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS)) +#define SPI_CR_SPI_SCLK_POL SPI_CR_SPI_SCLK_POL +#define SPI_CR_SPI_SCLK_POL_POS (4U) +#define SPI_CR_SPI_SCLK_POL_LEN (1U) +#define SPI_CR_SPI_SCLK_POL_MSK (((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS) +#define SPI_CR_SPI_SCLK_POL_UMSK (~(((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS)) +#define SPI_CR_SPI_SCLK_PH SPI_CR_SPI_SCLK_PH +#define SPI_CR_SPI_SCLK_PH_POS (5U) +#define SPI_CR_SPI_SCLK_PH_LEN (1U) +#define SPI_CR_SPI_SCLK_PH_MSK (((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS) +#define SPI_CR_SPI_SCLK_PH_UMSK (~(((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS)) +#define SPI_CR_SPI_BIT_INV SPI_CR_SPI_BIT_INV +#define SPI_CR_SPI_BIT_INV_POS (6U) +#define SPI_CR_SPI_BIT_INV_LEN (1U) +#define SPI_CR_SPI_BIT_INV_MSK (((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS) +#define SPI_CR_SPI_BIT_INV_UMSK (~(((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS)) +#define SPI_CR_SPI_BYTE_INV SPI_CR_SPI_BYTE_INV +#define SPI_CR_SPI_BYTE_INV_POS (7U) +#define SPI_CR_SPI_BYTE_INV_LEN (1U) +#define SPI_CR_SPI_BYTE_INV_MSK (((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS) +#define SPI_CR_SPI_BYTE_INV_UMSK (~(((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS)) +#define SPI_CR_SPI_RXD_IGNR_EN SPI_CR_SPI_RXD_IGNR_EN +#define SPI_CR_SPI_RXD_IGNR_EN_POS (8U) +#define SPI_CR_SPI_RXD_IGNR_EN_LEN (1U) +#define SPI_CR_SPI_RXD_IGNR_EN_MSK (((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS) +#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS)) +#define SPI_CR_SPI_M_CONT_EN SPI_CR_SPI_M_CONT_EN +#define SPI_CR_SPI_M_CONT_EN_POS (9U) +#define SPI_CR_SPI_M_CONT_EN_LEN (1U) +#define SPI_CR_SPI_M_CONT_EN_MSK (((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS) +#define SPI_CR_SPI_M_CONT_EN_UMSK (~(((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS)) +#define SPI_CR_SPI_DEG_EN SPI_CR_SPI_DEG_EN +#define SPI_CR_SPI_DEG_EN_POS (11U) +#define SPI_CR_SPI_DEG_EN_LEN (1U) +#define SPI_CR_SPI_DEG_EN_MSK (((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS) +#define SPI_CR_SPI_DEG_EN_UMSK (~(((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS)) +#define SPI_CR_SPI_DEG_CNT SPI_CR_SPI_DEG_CNT +#define SPI_CR_SPI_DEG_CNT_POS (12U) +#define SPI_CR_SPI_DEG_CNT_LEN (4U) +#define SPI_CR_SPI_DEG_CNT_MSK (((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS) +#define SPI_CR_SPI_DEG_CNT_UMSK (~(((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS)) + +/* 0x4 : spi_int_sts */ +#define SPI_INT_STS_OFFSET (0x4) +#define SPI_END_INT SPI_END_INT +#define SPI_END_INT_POS (0U) +#define SPI_END_INT_LEN (1U) +#define SPI_END_INT_MSK (((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS) +#define SPI_END_INT_UMSK (~(((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS)) +#define SPI_TXF_INT SPI_TXF_INT +#define SPI_TXF_INT_POS (1U) +#define SPI_TXF_INT_LEN (1U) +#define SPI_TXF_INT_MSK (((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS) +#define SPI_TXF_INT_UMSK (~(((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS)) +#define SPI_RXF_INT SPI_RXF_INT +#define SPI_RXF_INT_POS (2U) +#define SPI_RXF_INT_LEN (1U) +#define SPI_RXF_INT_MSK (((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS) +#define SPI_RXF_INT_UMSK (~(((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS)) +#define SPI_STO_INT SPI_STO_INT +#define SPI_STO_INT_POS (3U) +#define SPI_STO_INT_LEN (1U) +#define SPI_STO_INT_MSK (((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS) +#define SPI_STO_INT_UMSK (~(((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS)) +#define SPI_TXU_INT SPI_TXU_INT +#define SPI_TXU_INT_POS (4U) +#define SPI_TXU_INT_LEN (1U) +#define SPI_TXU_INT_MSK (((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS) +#define SPI_TXU_INT_UMSK (~(((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS)) +#define SPI_FER_INT SPI_FER_INT +#define SPI_FER_INT_POS (5U) +#define SPI_FER_INT_LEN (1U) +#define SPI_FER_INT_MSK (((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS) +#define SPI_FER_INT_UMSK (~(((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS)) +#define SPI_CR_SPI_END_MASK SPI_CR_SPI_END_MASK +#define SPI_CR_SPI_END_MASK_POS (8U) +#define SPI_CR_SPI_END_MASK_LEN (1U) +#define SPI_CR_SPI_END_MASK_MSK (((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS) +#define SPI_CR_SPI_END_MASK_UMSK (~(((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS)) +#define SPI_CR_SPI_TXF_MASK SPI_CR_SPI_TXF_MASK +#define SPI_CR_SPI_TXF_MASK_POS (9U) +#define SPI_CR_SPI_TXF_MASK_LEN (1U) +#define SPI_CR_SPI_TXF_MASK_MSK (((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS) +#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS)) +#define SPI_CR_SPI_RXF_MASK SPI_CR_SPI_RXF_MASK +#define SPI_CR_SPI_RXF_MASK_POS (10U) +#define SPI_CR_SPI_RXF_MASK_LEN (1U) +#define SPI_CR_SPI_RXF_MASK_MSK (((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS) +#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS)) +#define SPI_CR_SPI_STO_MASK SPI_CR_SPI_STO_MASK +#define SPI_CR_SPI_STO_MASK_POS (11U) +#define SPI_CR_SPI_STO_MASK_LEN (1U) +#define SPI_CR_SPI_STO_MASK_MSK (((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS) +#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS)) +#define SPI_CR_SPI_TXU_MASK SPI_CR_SPI_TXU_MASK +#define SPI_CR_SPI_TXU_MASK_POS (12U) +#define SPI_CR_SPI_TXU_MASK_LEN (1U) +#define SPI_CR_SPI_TXU_MASK_MSK (((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS) +#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS)) +#define SPI_CR_SPI_FER_MASK SPI_CR_SPI_FER_MASK +#define SPI_CR_SPI_FER_MASK_POS (13U) +#define SPI_CR_SPI_FER_MASK_LEN (1U) +#define SPI_CR_SPI_FER_MASK_MSK (((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS) +#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS)) +#define SPI_CR_SPI_END_CLR SPI_CR_SPI_END_CLR +#define SPI_CR_SPI_END_CLR_POS (16U) +#define SPI_CR_SPI_END_CLR_LEN (1U) +#define SPI_CR_SPI_END_CLR_MSK (((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS) +#define SPI_CR_SPI_END_CLR_UMSK (~(((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS)) +#define SPI_CR_SPI_STO_CLR SPI_CR_SPI_STO_CLR +#define SPI_CR_SPI_STO_CLR_POS (19U) +#define SPI_CR_SPI_STO_CLR_LEN (1U) +#define SPI_CR_SPI_STO_CLR_MSK (((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS) +#define SPI_CR_SPI_STO_CLR_UMSK (~(((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS)) +#define SPI_CR_SPI_TXU_CLR SPI_CR_SPI_TXU_CLR +#define SPI_CR_SPI_TXU_CLR_POS (20U) +#define SPI_CR_SPI_TXU_CLR_LEN (1U) +#define SPI_CR_SPI_TXU_CLR_MSK (((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS) +#define SPI_CR_SPI_TXU_CLR_UMSK (~(((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS)) +#define SPI_CR_SPI_END_EN SPI_CR_SPI_END_EN +#define SPI_CR_SPI_END_EN_POS (24U) +#define SPI_CR_SPI_END_EN_LEN (1U) +#define SPI_CR_SPI_END_EN_MSK (((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS) +#define SPI_CR_SPI_END_EN_UMSK (~(((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS)) +#define SPI_CR_SPI_TXF_EN SPI_CR_SPI_TXF_EN +#define SPI_CR_SPI_TXF_EN_POS (25U) +#define SPI_CR_SPI_TXF_EN_LEN (1U) +#define SPI_CR_SPI_TXF_EN_MSK (((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS) +#define SPI_CR_SPI_TXF_EN_UMSK (~(((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS)) +#define SPI_CR_SPI_RXF_EN SPI_CR_SPI_RXF_EN +#define SPI_CR_SPI_RXF_EN_POS (26U) +#define SPI_CR_SPI_RXF_EN_LEN (1U) +#define SPI_CR_SPI_RXF_EN_MSK (((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS) +#define SPI_CR_SPI_RXF_EN_UMSK (~(((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS)) +#define SPI_CR_SPI_STO_EN SPI_CR_SPI_STO_EN +#define SPI_CR_SPI_STO_EN_POS (27U) +#define SPI_CR_SPI_STO_EN_LEN (1U) +#define SPI_CR_SPI_STO_EN_MSK (((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS) +#define SPI_CR_SPI_STO_EN_UMSK (~(((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS)) +#define SPI_CR_SPI_TXU_EN SPI_CR_SPI_TXU_EN +#define SPI_CR_SPI_TXU_EN_POS (28U) +#define SPI_CR_SPI_TXU_EN_LEN (1U) +#define SPI_CR_SPI_TXU_EN_MSK (((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS) +#define SPI_CR_SPI_TXU_EN_UMSK (~(((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS)) +#define SPI_CR_SPI_FER_EN SPI_CR_SPI_FER_EN +#define SPI_CR_SPI_FER_EN_POS (29U) +#define SPI_CR_SPI_FER_EN_LEN (1U) +#define SPI_CR_SPI_FER_EN_MSK (((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS) +#define SPI_CR_SPI_FER_EN_UMSK (~(((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS)) + +/* 0x8 : spi_bus_busy */ +#define SPI_BUS_BUSY_OFFSET (0x8) +#define SPI_STS_SPI_BUS_BUSY SPI_STS_SPI_BUS_BUSY +#define SPI_STS_SPI_BUS_BUSY_POS (0U) +#define SPI_STS_SPI_BUS_BUSY_LEN (1U) +#define SPI_STS_SPI_BUS_BUSY_MSK (((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS) +#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS)) + +/* 0x10 : spi_prd_0 */ +#define SPI_PRD_0_OFFSET (0x10) +#define SPI_CR_SPI_PRD_S SPI_CR_SPI_PRD_S +#define SPI_CR_SPI_PRD_S_POS (0U) +#define SPI_CR_SPI_PRD_S_LEN (8U) +#define SPI_CR_SPI_PRD_S_MSK (((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS) +#define SPI_CR_SPI_PRD_S_UMSK (~(((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS)) +#define SPI_CR_SPI_PRD_P SPI_CR_SPI_PRD_P +#define SPI_CR_SPI_PRD_P_POS (8U) +#define SPI_CR_SPI_PRD_P_LEN (8U) +#define SPI_CR_SPI_PRD_P_MSK (((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS) +#define SPI_CR_SPI_PRD_P_UMSK (~(((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS)) +#define SPI_CR_SPI_PRD_D_PH_0 SPI_CR_SPI_PRD_D_PH_0 +#define SPI_CR_SPI_PRD_D_PH_0_POS (16U) +#define SPI_CR_SPI_PRD_D_PH_0_LEN (8U) +#define SPI_CR_SPI_PRD_D_PH_0_MSK (((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS) +#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS)) +#define SPI_CR_SPI_PRD_D_PH_1 SPI_CR_SPI_PRD_D_PH_1 +#define SPI_CR_SPI_PRD_D_PH_1_POS (24U) +#define SPI_CR_SPI_PRD_D_PH_1_LEN (8U) +#define SPI_CR_SPI_PRD_D_PH_1_MSK (((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS) +#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS)) + +/* 0x14 : spi_prd_1 */ +#define SPI_PRD_1_OFFSET (0x14) +#define SPI_CR_SPI_PRD_I SPI_CR_SPI_PRD_I +#define SPI_CR_SPI_PRD_I_POS (0U) +#define SPI_CR_SPI_PRD_I_LEN (8U) +#define SPI_CR_SPI_PRD_I_MSK (((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS) +#define SPI_CR_SPI_PRD_I_UMSK (~(((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS)) + +/* 0x18 : spi_rxd_ignr */ +#define SPI_RXD_IGNR_OFFSET (0x18) +#define SPI_CR_SPI_RXD_IGNR_P SPI_CR_SPI_RXD_IGNR_P +#define SPI_CR_SPI_RXD_IGNR_P_POS (0U) +#define SPI_CR_SPI_RXD_IGNR_P_LEN (5U) +#define SPI_CR_SPI_RXD_IGNR_P_MSK (((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS) +#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS)) +#define SPI_CR_SPI_RXD_IGNR_S SPI_CR_SPI_RXD_IGNR_S +#define SPI_CR_SPI_RXD_IGNR_S_POS (16U) +#define SPI_CR_SPI_RXD_IGNR_S_LEN (5U) +#define SPI_CR_SPI_RXD_IGNR_S_MSK (((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS) +#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS)) + +/* 0x1C : spi_sto_value */ +#define SPI_STO_VALUE_OFFSET (0x1C) +#define SPI_CR_SPI_STO_VALUE SPI_CR_SPI_STO_VALUE +#define SPI_CR_SPI_STO_VALUE_POS (0U) +#define SPI_CR_SPI_STO_VALUE_LEN (12U) +#define SPI_CR_SPI_STO_VALUE_MSK (((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS) +#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS)) + +/* 0x80 : spi_fifo_config_0 */ +#define SPI_FIFO_CONFIG_0_OFFSET (0x80) +#define SPI_DMA_TX_EN SPI_DMA_TX_EN +#define SPI_DMA_TX_EN_POS (0U) +#define SPI_DMA_TX_EN_LEN (1U) +#define SPI_DMA_TX_EN_MSK (((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS) +#define SPI_DMA_TX_EN_UMSK (~(((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS)) +#define SPI_DMA_RX_EN SPI_DMA_RX_EN +#define SPI_DMA_RX_EN_POS (1U) +#define SPI_DMA_RX_EN_LEN (1U) +#define SPI_DMA_RX_EN_MSK (((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS) +#define SPI_DMA_RX_EN_UMSK (~(((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS)) +#define SPI_TX_FIFO_CLR SPI_TX_FIFO_CLR +#define SPI_TX_FIFO_CLR_POS (2U) +#define SPI_TX_FIFO_CLR_LEN (1U) +#define SPI_TX_FIFO_CLR_MSK (((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS) +#define SPI_TX_FIFO_CLR_UMSK (~(((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS)) +#define SPI_RX_FIFO_CLR SPI_RX_FIFO_CLR +#define SPI_RX_FIFO_CLR_POS (3U) +#define SPI_RX_FIFO_CLR_LEN (1U) +#define SPI_RX_FIFO_CLR_MSK (((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS) +#define SPI_RX_FIFO_CLR_UMSK (~(((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS)) +#define SPI_TX_FIFO_OVERFLOW SPI_TX_FIFO_OVERFLOW +#define SPI_TX_FIFO_OVERFLOW_POS (4U) +#define SPI_TX_FIFO_OVERFLOW_LEN (1U) +#define SPI_TX_FIFO_OVERFLOW_MSK (((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS) +#define SPI_TX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS)) +#define SPI_TX_FIFO_UNDERFLOW SPI_TX_FIFO_UNDERFLOW +#define SPI_TX_FIFO_UNDERFLOW_POS (5U) +#define SPI_TX_FIFO_UNDERFLOW_LEN (1U) +#define SPI_TX_FIFO_UNDERFLOW_MSK (((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS) +#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS)) +#define SPI_RX_FIFO_OVERFLOW SPI_RX_FIFO_OVERFLOW +#define SPI_RX_FIFO_OVERFLOW_POS (6U) +#define SPI_RX_FIFO_OVERFLOW_LEN (1U) +#define SPI_RX_FIFO_OVERFLOW_MSK (((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS) +#define SPI_RX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS)) +#define SPI_RX_FIFO_UNDERFLOW SPI_RX_FIFO_UNDERFLOW +#define SPI_RX_FIFO_UNDERFLOW_POS (7U) +#define SPI_RX_FIFO_UNDERFLOW_LEN (1U) +#define SPI_RX_FIFO_UNDERFLOW_MSK (((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS) +#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS)) + +/* 0x84 : spi_fifo_config_1 */ +#define SPI_FIFO_CONFIG_1_OFFSET (0x84) +#define SPI_TX_FIFO_CNT SPI_TX_FIFO_CNT +#define SPI_TX_FIFO_CNT_POS (0U) +#define SPI_TX_FIFO_CNT_LEN (3U) +#define SPI_TX_FIFO_CNT_MSK (((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS) +#define SPI_TX_FIFO_CNT_UMSK (~(((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS)) +#define SPI_RX_FIFO_CNT SPI_RX_FIFO_CNT +#define SPI_RX_FIFO_CNT_POS (8U) +#define SPI_RX_FIFO_CNT_LEN (3U) +#define SPI_RX_FIFO_CNT_MSK (((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS) +#define SPI_RX_FIFO_CNT_UMSK (~(((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS)) +#define SPI_TX_FIFO_TH SPI_TX_FIFO_TH +#define SPI_TX_FIFO_TH_POS (16U) +#define SPI_TX_FIFO_TH_LEN (2U) +#define SPI_TX_FIFO_TH_MSK (((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS) +#define SPI_TX_FIFO_TH_UMSK (~(((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS)) +#define SPI_RX_FIFO_TH SPI_RX_FIFO_TH +#define SPI_RX_FIFO_TH_POS (24U) +#define SPI_RX_FIFO_TH_LEN (2U) +#define SPI_RX_FIFO_TH_MSK (((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS) +#define SPI_RX_FIFO_TH_UMSK (~(((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS)) + +/* 0x88 : spi_fifo_wdata */ +#define SPI_FIFO_WDATA_OFFSET (0x88) +#define SPI_FIFO_WDATA SPI_FIFO_WDATA +#define SPI_FIFO_WDATA_POS (0U) +#define SPI_FIFO_WDATA_LEN (32U) +#define SPI_FIFO_WDATA_MSK (((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS) +#define SPI_FIFO_WDATA_UMSK (~(((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS)) + +/* 0x8C : spi_fifo_rdata */ +#define SPI_FIFO_RDATA_OFFSET (0x8C) +#define SPI_FIFO_RDATA SPI_FIFO_RDATA +#define SPI_FIFO_RDATA_POS (0U) +#define SPI_FIFO_RDATA_LEN (32U) +#define SPI_FIFO_RDATA_MSK (((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS) +#define SPI_FIFO_RDATA_UMSK (~(((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS)) + +struct spi_reg { + /* 0x0 : spi_config */ + union { + struct + { + uint32_t cr_spi_m_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_spi_s_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_spi_frame_size : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t cr_spi_sclk_pol : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_spi_sclk_ph : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_spi_bit_inv : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_spi_byte_inv : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_spi_rxd_ignr_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t cr_spi_m_cont_en : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ + uint32_t cr_spi_deg_en : 1; /* [ 11], r/w, 0x0 */ + uint32_t cr_spi_deg_cnt : 4; /* [15:12], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_config; + + /* 0x4 : spi_int_sts */ + union { + struct + { + uint32_t spi_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t spi_txf_int : 1; /* [ 1], r, 0x0 */ + uint32_t spi_rxf_int : 1; /* [ 2], r, 0x0 */ + uint32_t spi_sto_int : 1; /* [ 3], r, 0x0 */ + uint32_t spi_txu_int : 1; /* [ 4], r, 0x0 */ + uint32_t spi_fer_int : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t cr_spi_end_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_spi_txf_mask : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_spi_rxf_mask : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_spi_sto_mask : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_spi_txu_mask : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_spi_fer_mask : 1; /* [ 13], r/w, 0x1 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t cr_spi_end_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t cr_spi_sto_clr : 1; /* [ 19], w1c, 0x0 */ + uint32_t cr_spi_txu_clr : 1; /* [ 20], w1c, 0x0 */ + uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t cr_spi_end_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t cr_spi_txf_en : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_spi_rxf_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t cr_spi_sto_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t cr_spi_txu_en : 1; /* [ 28], r/w, 0x1 */ + uint32_t cr_spi_fer_en : 1; /* [ 29], r/w, 0x1 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_int_sts; + + /* 0x8 : spi_bus_busy */ + union { + struct + { + uint32_t sts_spi_bus_busy : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_bus_busy; + + /* 0xc reserved */ + uint8_t RESERVED0xc[4]; + + /* 0x10 : spi_prd_0 */ + union { + struct + { + uint32_t cr_spi_prd_s : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t cr_spi_prd_p : 8; /* [15: 8], r/w, 0xf */ + uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */ + uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } spi_prd_0; + + /* 0x14 : spi_prd_1 */ + union { + struct + { + uint32_t cr_spi_prd_i : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_prd_1; + + /* 0x18 : spi_rxd_ignr */ + union { + struct + { + uint32_t cr_spi_rxd_ignr_p : 5; /* [ 4: 0], r/w, 0x0 */ + uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ + uint32_t cr_spi_rxd_ignr_s : 5; /* [20:16], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_rxd_ignr; + + /* 0x1C : spi_sto_value */ + union { + struct + { + uint32_t cr_spi_sto_value : 12; /* [11: 0], r/w, 0xfff */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_sto_value; + + /* 0x20 reserved */ + uint8_t RESERVED0x20[96]; + + /* 0x80 : spi_fifo_config_0 */ + union { + struct + { + uint32_t spi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t spi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_fifo_config_0; + + /* 0x84 : spi_fifo_config_1 */ + union { + struct + { + uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */ + uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ + uint32_t rx_fifo_cnt : 3; /* [10: 8], r, 0x0 */ + uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ + uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */ + uint32_t rx_fifo_th : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } spi_fifo_config_1; + + /* 0x88 : spi_fifo_wdata */ + union { + struct + { + uint32_t spi_fifo_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } spi_fifo_wdata; + + /* 0x8C : spi_fifo_rdata */ + union { + struct + { + uint32_t spi_fifo_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } spi_fifo_rdata; +}; + +typedef volatile struct spi_reg spi_reg_t; + +#endif /* __SPI_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/timer_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/timer_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..49870bbaead687bb7df9553d4466e3aa371e5d33 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/timer_reg.h @@ -0,0 +1,852 @@ +/** + ****************************************************************************** + * @file timer_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#include "bl702.h" + +/* 0x0 : TCCR */ +#define TIMER_TCCR_OFFSET (0x0) +#define TIMER_CS_1 TIMER_CS_1 +#define TIMER_CS_1_POS (2U) +#define TIMER_CS_1_LEN (2U) +#define TIMER_CS_1_MSK (((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS) +#define TIMER_CS_1_UMSK (~(((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS)) +#define TIMER_CS_2 TIMER_CS_2 +#define TIMER_CS_2_POS (5U) +#define TIMER_CS_2_LEN (2U) +#define TIMER_CS_2_MSK (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS) +#define TIMER_CS_2_UMSK (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)) +#define TIMER_CS_WDT TIMER_CS_WDT +#define TIMER_CS_WDT_POS (8U) +#define TIMER_CS_WDT_LEN (2U) +#define TIMER_CS_WDT_MSK (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS) +#define TIMER_CS_WDT_UMSK (~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)) + +/* 0x10 : TMR2_0 */ +#define TIMER_TMR2_0_OFFSET (0x10) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x14 : TMR2_1 */ +#define TIMER_TMR2_1_OFFSET (0x14) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x18 : TMR2_2 */ +#define TIMER_TMR2_2_OFFSET (0x18) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x1C : TMR3_0 */ +#define TIMER_TMR3_0_OFFSET (0x1C) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x20 : TMR3_1 */ +#define TIMER_TMR3_1_OFFSET (0x20) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x24 : TMR3_2 */ +#define TIMER_TMR3_2_OFFSET (0x24) +#define TIMER_TMR TIMER_TMR +#define TIMER_TMR_POS (0U) +#define TIMER_TMR_LEN (32U) +#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS) +#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)) + +/* 0x2C : TCR2 */ +#define TIMER_TCR2_OFFSET (0x2C) +#define TIMER_TCR TIMER_TCR +#define TIMER_TCR_POS (0U) +#define TIMER_TCR_LEN (32U) +#define TIMER_TCR_MSK (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS) +#define TIMER_TCR_UMSK (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)) + +/* 0x30 : TCR3 */ +#define TIMER_TCR3_OFFSET (0x30) +#define TIMER_TCR TIMER_TCR +#define TIMER_TCR_POS (0U) +#define TIMER_TCR_LEN (32U) +#define TIMER_TCR_MSK (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS) +#define TIMER_TCR_UMSK (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)) + +/* 0x38 : TMSR2 */ +#define TIMER_TMSR2_OFFSET (0x38) +#define TIMER_TMSR_0 TIMER_TMSR_0 +#define TIMER_TMSR_0_POS (0U) +#define TIMER_TMSR_0_LEN (1U) +#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS) +#define TIMER_TMSR_0_UMSK (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)) +#define TIMER_TMSR_1 TIMER_TMSR_1 +#define TIMER_TMSR_1_POS (1U) +#define TIMER_TMSR_1_LEN (1U) +#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS) +#define TIMER_TMSR_1_UMSK (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)) +#define TIMER_TMSR_2 TIMER_TMSR_2 +#define TIMER_TMSR_2_POS (2U) +#define TIMER_TMSR_2_LEN (1U) +#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS) +#define TIMER_TMSR_2_UMSK (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)) + +/* 0x3C : TMSR3 */ +#define TIMER_TMSR3_OFFSET (0x3C) +#define TIMER_TMSR_0 TIMER_TMSR_0 +#define TIMER_TMSR_0_POS (0U) +#define TIMER_TMSR_0_LEN (1U) +#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS) +#define TIMER_TMSR_0_UMSK (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)) +#define TIMER_TMSR_1 TIMER_TMSR_1 +#define TIMER_TMSR_1_POS (1U) +#define TIMER_TMSR_1_LEN (1U) +#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS) +#define TIMER_TMSR_1_UMSK (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)) +#define TIMER_TMSR_2 TIMER_TMSR_2 +#define TIMER_TMSR_2_POS (2U) +#define TIMER_TMSR_2_LEN (1U) +#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS) +#define TIMER_TMSR_2_UMSK (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)) + +/* 0x44 : TIER2 */ +#define TIMER_TIER2_OFFSET (0x44) +#define TIMER_TIER_0 TIMER_TIER_0 +#define TIMER_TIER_0_POS (0U) +#define TIMER_TIER_0_LEN (1U) +#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS) +#define TIMER_TIER_0_UMSK (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)) +#define TIMER_TIER_1 TIMER_TIER_1 +#define TIMER_TIER_1_POS (1U) +#define TIMER_TIER_1_LEN (1U) +#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS) +#define TIMER_TIER_1_UMSK (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)) +#define TIMER_TIER_2 TIMER_TIER_2 +#define TIMER_TIER_2_POS (2U) +#define TIMER_TIER_2_LEN (1U) +#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS) +#define TIMER_TIER_2_UMSK (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)) + +/* 0x48 : TIER3 */ +#define TIMER_TIER3_OFFSET (0x48) +#define TIMER_TIER_0 TIMER_TIER_0 +#define TIMER_TIER_0_POS (0U) +#define TIMER_TIER_0_LEN (1U) +#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS) +#define TIMER_TIER_0_UMSK (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)) +#define TIMER_TIER_1 TIMER_TIER_1 +#define TIMER_TIER_1_POS (1U) +#define TIMER_TIER_1_LEN (1U) +#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS) +#define TIMER_TIER_1_UMSK (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)) +#define TIMER_TIER_2 TIMER_TIER_2 +#define TIMER_TIER_2_POS (2U) +#define TIMER_TIER_2_LEN (1U) +#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS) +#define TIMER_TIER_2_UMSK (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)) + +/* 0x50 : TPLVR2 */ +#define TIMER_TPLVR2_OFFSET (0x50) +#define TIMER_TPLVR TIMER_TPLVR +#define TIMER_TPLVR_POS (0U) +#define TIMER_TPLVR_LEN (32U) +#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS) +#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)) + +/* 0x54 : TPLVR3 */ +#define TIMER_TPLVR3_OFFSET (0x54) +#define TIMER_TPLVR TIMER_TPLVR +#define TIMER_TPLVR_POS (0U) +#define TIMER_TPLVR_LEN (32U) +#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS) +#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)) + +/* 0x5C : TPLCR2 */ +#define TIMER_TPLCR2_OFFSET (0x5C) +#define TIMER_TPLCR TIMER_TPLCR +#define TIMER_TPLCR_POS (0U) +#define TIMER_TPLCR_LEN (2U) +#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS) +#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)) + +/* 0x60 : TPLCR3 */ +#define TIMER_TPLCR3_OFFSET (0x60) +#define TIMER_TPLCR TIMER_TPLCR +#define TIMER_TPLCR_POS (0U) +#define TIMER_TPLCR_LEN (2U) +#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS) +#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)) + +/* 0x64 : WMER */ +#define TIMER_WMER_OFFSET (0x64) +#define TIMER_WE TIMER_WE +#define TIMER_WE_POS (0U) +#define TIMER_WE_LEN (1U) +#define TIMER_WE_MSK (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS) +#define TIMER_WE_UMSK (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)) +#define TIMER_WRIE TIMER_WRIE +#define TIMER_WRIE_POS (1U) +#define TIMER_WRIE_LEN (1U) +#define TIMER_WRIE_MSK (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS) +#define TIMER_WRIE_UMSK (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)) + +/* 0x68 : WMR */ +#define TIMER_WMR_OFFSET (0x68) +#define TIMER_WMR TIMER_WMR +#define TIMER_WMR_POS (0U) +#define TIMER_WMR_LEN (16U) +#define TIMER_WMR_MSK (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS) +#define TIMER_WMR_UMSK (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)) + +/* 0x6C : WVR */ +#define TIMER_WVR_OFFSET (0x6C) +#define TIMER_WVR TIMER_WVR +#define TIMER_WVR_POS (0U) +#define TIMER_WVR_LEN (16U) +#define TIMER_WVR_MSK (((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS) +#define TIMER_WVR_UMSK (~(((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS)) + +/* 0x70 : WSR */ +#define TIMER_WSR_OFFSET (0x70) +#define TIMER_WTS TIMER_WTS +#define TIMER_WTS_POS (0U) +#define TIMER_WTS_LEN (1U) +#define TIMER_WTS_MSK (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS) +#define TIMER_WTS_UMSK (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)) + +/* 0x78 : TICR2 */ +#define TIMER_TICR2_OFFSET (0x78) +#define TIMER_TCLR_0 TIMER_TCLR_0 +#define TIMER_TCLR_0_POS (0U) +#define TIMER_TCLR_0_LEN (1U) +#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS) +#define TIMER_TCLR_0_UMSK (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)) +#define TIMER_TCLR_1 TIMER_TCLR_1 +#define TIMER_TCLR_1_POS (1U) +#define TIMER_TCLR_1_LEN (1U) +#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS) +#define TIMER_TCLR_1_UMSK (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)) +#define TIMER_TCLR_2 TIMER_TCLR_2 +#define TIMER_TCLR_2_POS (2U) +#define TIMER_TCLR_2_LEN (1U) +#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS) +#define TIMER_TCLR_2_UMSK (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)) + +/* 0x7C : TICR3 */ +#define TIMER_TICR3_OFFSET (0x7C) +#define TIMER_TCLR_0 TIMER_TCLR_0 +#define TIMER_TCLR_0_POS (0U) +#define TIMER_TCLR_0_LEN (1U) +#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS) +#define TIMER_TCLR_0_UMSK (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)) +#define TIMER_TCLR_1 TIMER_TCLR_1 +#define TIMER_TCLR_1_POS (1U) +#define TIMER_TCLR_1_LEN (1U) +#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS) +#define TIMER_TCLR_1_UMSK (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)) +#define TIMER_TCLR_2 TIMER_TCLR_2 +#define TIMER_TCLR_2_POS (2U) +#define TIMER_TCLR_2_LEN (1U) +#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS) +#define TIMER_TCLR_2_UMSK (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)) + +/* 0x80 : WICR */ +#define TIMER_WICR_OFFSET (0x80) +#define TIMER_WICLR TIMER_WICLR +#define TIMER_WICLR_POS (0U) +#define TIMER_WICLR_LEN (1U) +#define TIMER_WICLR_MSK (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS) +#define TIMER_WICLR_UMSK (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)) + +/* 0x84 : TCER */ +#define TIMER_TCER_OFFSET (0x84) +#define TIMER2_EN TIMER2_EN +#define TIMER2_EN_POS (1U) +#define TIMER2_EN_LEN (1U) +#define TIMER2_EN_MSK (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS) +#define TIMER2_EN_UMSK (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)) +#define TIMER3_EN TIMER3_EN +#define TIMER3_EN_POS (2U) +#define TIMER3_EN_LEN (1U) +#define TIMER3_EN_MSK (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS) +#define TIMER3_EN_UMSK (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)) + +/* 0x88 : TCMR */ +#define TIMER_TCMR_OFFSET (0x88) +#define TIMER2_MODE TIMER2_MODE +#define TIMER2_MODE_POS (1U) +#define TIMER2_MODE_LEN (1U) +#define TIMER2_MODE_MSK (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS) +#define TIMER2_MODE_UMSK (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)) +#define TIMER3_MODE TIMER3_MODE +#define TIMER3_MODE_POS (2U) +#define TIMER3_MODE_LEN (1U) +#define TIMER3_MODE_MSK (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS) +#define TIMER3_MODE_UMSK (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)) + +/* 0x90 : TILR2 */ +#define TIMER_TILR2_OFFSET (0x90) +#define TIMER_TILR_0 TIMER_TILR_0 +#define TIMER_TILR_0_POS (0U) +#define TIMER_TILR_0_LEN (1U) +#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS) +#define TIMER_TILR_0_UMSK (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)) +#define TIMER_TILR_1 TIMER_TILR_1 +#define TIMER_TILR_1_POS (1U) +#define TIMER_TILR_1_LEN (1U) +#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS) +#define TIMER_TILR_1_UMSK (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)) +#define TIMER_TILR_2 TIMER_TILR_2 +#define TIMER_TILR_2_POS (2U) +#define TIMER_TILR_2_LEN (1U) +#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS) +#define TIMER_TILR_2_UMSK (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)) + +/* 0x94 : TILR3 */ +#define TIMER_TILR3_OFFSET (0x94) +#define TIMER_TILR_0 TIMER_TILR_0 +#define TIMER_TILR_0_POS (0U) +#define TIMER_TILR_0_LEN (1U) +#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS) +#define TIMER_TILR_0_UMSK (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)) +#define TIMER_TILR_1 TIMER_TILR_1 +#define TIMER_TILR_1_POS (1U) +#define TIMER_TILR_1_LEN (1U) +#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS) +#define TIMER_TILR_1_UMSK (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)) +#define TIMER_TILR_2 TIMER_TILR_2 +#define TIMER_TILR_2_POS (2U) +#define TIMER_TILR_2_LEN (1U) +#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS) +#define TIMER_TILR_2_UMSK (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)) + +/* 0x98 : WCR */ +#define TIMER_WCR_OFFSET (0x98) +#define TIMER_WCR TIMER_WCR +#define TIMER_WCR_POS (0U) +#define TIMER_WCR_LEN (1U) +#define TIMER_WCR_MSK (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS) +#define TIMER_WCR_UMSK (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)) + +/* 0x9C : WFAR */ +#define TIMER_WFAR_OFFSET (0x9C) +#define TIMER_WFAR TIMER_WFAR +#define TIMER_WFAR_POS (0U) +#define TIMER_WFAR_LEN (16U) +#define TIMER_WFAR_MSK (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS) +#define TIMER_WFAR_UMSK (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)) + +/* 0xA0 : WSAR */ +#define TIMER_WSAR_OFFSET (0xA0) +#define TIMER_WSAR TIMER_WSAR +#define TIMER_WSAR_POS (0U) +#define TIMER_WSAR_LEN (16U) +#define TIMER_WSAR_MSK (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS) +#define TIMER_WSAR_UMSK (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)) + +/* 0xA8 : TCVWR2 */ +#define TIMER_TCVWR2_OFFSET (0xA8) +#define TIMER_TCVWR TIMER_TCVWR +#define TIMER_TCVWR_POS (0U) +#define TIMER_TCVWR_LEN (32U) +#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS) +#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)) + +/* 0xAC : TCVWR3 */ +#define TIMER_TCVWR3_OFFSET (0xAC) +#define TIMER_TCVWR TIMER_TCVWR +#define TIMER_TCVWR_POS (0U) +#define TIMER_TCVWR_LEN (32U) +#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS) +#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)) + +/* 0xB4 : TCVSYN2 */ +#define TIMER_TCVSYN2_OFFSET (0xB4) +#define TIMER_TCVSYN2 TIMER_TCVSYN2 +#define TIMER_TCVSYN2_POS (0U) +#define TIMER_TCVSYN2_LEN (32U) +#define TIMER_TCVSYN2_MSK (((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS) +#define TIMER_TCVSYN2_UMSK (~(((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS)) + +/* 0xB8 : TCVSYN3 */ +#define TIMER_TCVSYN3_OFFSET (0xB8) +#define TIMER_TCVSYN3 TIMER_TCVSYN3 +#define TIMER_TCVSYN3_POS (0U) +#define TIMER_TCVSYN3_LEN (32U) +#define TIMER_TCVSYN3_MSK (((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS) +#define TIMER_TCVSYN3_UMSK (~(((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS)) + +/* 0xBC : TCDR */ +#define TIMER_TCDR_OFFSET (0xBC) +#define TIMER_TCDR2 TIMER_TCDR2 +#define TIMER_TCDR2_POS (8U) +#define TIMER_TCDR2_LEN (8U) +#define TIMER_TCDR2_MSK (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS) +#define TIMER_TCDR2_UMSK (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)) +#define TIMER_TCDR3 TIMER_TCDR3 +#define TIMER_TCDR3_POS (16U) +#define TIMER_TCDR3_LEN (8U) +#define TIMER_TCDR3_MSK (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS) +#define TIMER_TCDR3_UMSK (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)) +#define TIMER_WCDR TIMER_WCDR +#define TIMER_WCDR_POS (24U) +#define TIMER_WCDR_LEN (8U) +#define TIMER_WCDR_MSK (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS) +#define TIMER_WCDR_UMSK (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)) + +struct timer_reg { + /* 0x0 : TCCR */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t cs_1 : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t RESERVED_4 : 1; /* [ 4], rsvd, 0x0 */ + uint32_t cs_2 : 2; /* [ 6: 5], r/w, 0x0 */ + uint32_t RESERVED_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cs_wdt : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TCCR; + + /* 0x4 reserved */ + uint8_t RESERVED0x4[12]; + + /* 0x10 : TMR2_0 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR2_0; + + /* 0x14 : TMR2_1 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR2_1; + + /* 0x18 : TMR2_2 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR2_2; + + /* 0x1C : TMR3_0 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR3_0; + + /* 0x20 : TMR3_1 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR3_1; + + /* 0x24 : TMR3_2 */ + union { + struct + { + uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } TMR3_2; + + /* 0x28 reserved */ + uint8_t RESERVED0x28[4]; + + /* 0x2C : TCR2 */ + union { + struct + { + uint32_t tcr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCR2; + + /* 0x30 : TCR3 */ + union { + struct + { + uint32_t tcr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCR3; + + /* 0x34 reserved */ + uint8_t RESERVED0x34[4]; + + /* 0x38 : TMSR2 */ + union { + struct + { + uint32_t tmsr_0 : 1; /* [ 0], r, 0x0 */ + uint32_t tmsr_1 : 1; /* [ 1], r, 0x0 */ + uint32_t tmsr_2 : 1; /* [ 2], r, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TMSR2; + + /* 0x3C : TMSR3 */ + union { + struct + { + uint32_t tmsr_0 : 1; /* [ 0], r, 0x0 */ + uint32_t tmsr_1 : 1; /* [ 1], r, 0x0 */ + uint32_t tmsr_2 : 1; /* [ 2], r, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TMSR3; + + /* 0x40 reserved */ + uint8_t RESERVED0x40[4]; + + /* 0x44 : TIER2 */ + union { + struct + { + uint32_t tier_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t tier_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t tier_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TIER2; + + /* 0x48 : TIER3 */ + union { + struct + { + uint32_t tier_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t tier_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t tier_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TIER3; + + /* 0x4c reserved */ + uint8_t RESERVED0x4c[4]; + + /* 0x50 : TPLVR2 */ + union { + struct + { + uint32_t tplvr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } TPLVR2; + + /* 0x54 : TPLVR3 */ + union { + struct + { + uint32_t tplvr : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } TPLVR3; + + /* 0x58 reserved */ + uint8_t RESERVED0x58[4]; + + /* 0x5C : TPLCR2 */ + union { + struct + { + uint32_t tplcr : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TPLCR2; + + /* 0x60 : TPLCR3 */ + union { + struct + { + uint32_t tplcr : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TPLCR3; + + /* 0x64 : WMER */ + union { + struct + { + uint32_t we : 1; /* [ 0], r/w, 0x0 */ + uint32_t wrie : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WMER; + + /* 0x68 : WMR */ + union { + struct + { + uint32_t wmr : 16; /* [15: 0], r/w, 0xffff */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WMR; + + /* 0x6C : WVR */ + union { + struct + { + uint32_t wvr : 16; /* [15: 0], r, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WVR; + + /* 0x70 : WSR */ + union { + struct + { + uint32_t wts : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WSR; + + /* 0x74 reserved */ + uint8_t RESERVED0x74[4]; + + /* 0x78 : TICR2 */ + union { + struct + { + uint32_t tclr_0 : 1; /* [ 0], w, 0x0 */ + uint32_t tclr_1 : 1; /* [ 1], w, 0x0 */ + uint32_t tclr_2 : 1; /* [ 2], w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TICR2; + + /* 0x7C : TICR3 */ + union { + struct + { + uint32_t tclr_0 : 1; /* [ 0], w, 0x0 */ + uint32_t tclr_1 : 1; /* [ 1], w, 0x0 */ + uint32_t tclr_2 : 1; /* [ 2], w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TICR3; + + /* 0x80 : WICR */ + union { + struct + { + uint32_t wiclr : 1; /* [ 0], w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WICR; + + /* 0x84 : TCER */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t timer2_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t timer3_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TCER; + + /* 0x88 : TCMR */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t timer2_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t timer3_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TCMR; + + /* 0x8c reserved */ + uint8_t RESERVED0x8c[4]; + + /* 0x90 : TILR2 */ + union { + struct + { + uint32_t tilr_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t tilr_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t tilr_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TILR2; + + /* 0x94 : TILR3 */ + union { + struct + { + uint32_t tilr_0 : 1; /* [ 0], r/w, 0x0 */ + uint32_t tilr_1 : 1; /* [ 1], r/w, 0x0 */ + uint32_t tilr_2 : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } TILR3; + + /* 0x98 : WCR */ + union { + struct + { + uint32_t wcr : 1; /* [ 0], w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WCR; + + /* 0x9C : WFAR */ + union { + struct + { + uint32_t wfar : 16; /* [15: 0], w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WFAR; + + /* 0xA0 : WSAR */ + union { + struct + { + uint32_t wsar : 16; /* [15: 0], w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WSAR; + + /* 0xa4 reserved */ + uint8_t RESERVED0xa4[4]; + + /* 0xA8 : TCVWR2 */ + union { + struct + { + uint32_t tcvwr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCVWR2; + + /* 0xAC : TCVWR3 */ + union { + struct + { + uint32_t tcvwr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCVWR3; + + /* 0xb0 reserved */ + uint8_t RESERVED0xb0[4]; + + /* 0xB4 : TCVSYN2 */ + union { + struct + { + uint32_t tcvsyn2 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCVSYN2; + + /* 0xB8 : TCVSYN3 */ + union { + struct + { + uint32_t tcvsyn3 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } TCVSYN3; + + /* 0xBC : TCDR */ + union { + struct + { + uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ + uint32_t tcdr2 : 8; /* [15: 8], r/w, 0x0 */ + uint32_t tcdr3 : 8; /* [23:16], r/w, 0x0 */ + uint32_t wcdr : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } TCDR; +}; + +typedef volatile struct timer_reg timer_reg_t; + +#endif /* __TIMER_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/tzc_sec_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/tzc_sec_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..e436b8c4c0bc29446f03cd72169e99fea0cd3a98 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/tzc_sec_reg.h @@ -0,0 +1,256 @@ +/** + ****************************************************************************** + * @file tzc_sec_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TZC_SEC_REG_H__ +#define __TZC_SEC_REG_H__ + +#include "bl702.h" + +/* 0x40 : tzc_rom_ctrl */ +#define TZC_SEC_TZC_ROM_CTRL_OFFSET (0x40) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN TZC_SEC_TZC_ROM0_R0_ID0_EN +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS (0U) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN TZC_SEC_TZC_ROM0_R1_ID0_EN +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS (1U) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN TZC_SEC_TZC_ROM1_R0_ID0_EN +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS (2U) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN TZC_SEC_TZC_ROM1_R1_ID0_EN +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS (3U) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN TZC_SEC_TZC_ROM0_R0_ID1_EN +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS (8U) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN TZC_SEC_TZC_ROM0_R1_ID1_EN +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS (9U) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN TZC_SEC_TZC_ROM1_R0_ID1_EN +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS (10U) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN TZC_SEC_TZC_ROM1_R1_ID1_EN +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS (11U) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_EN TZC_SEC_TZC_ROM0_R0_EN +#define TZC_SEC_TZC_ROM0_R0_EN_POS (16U) +#define TZC_SEC_TZC_ROM0_R0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_EN TZC_SEC_TZC_ROM0_R1_EN +#define TZC_SEC_TZC_ROM0_R1_EN_POS (17U) +#define TZC_SEC_TZC_ROM0_R1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_EN TZC_SEC_TZC_ROM1_R0_EN +#define TZC_SEC_TZC_ROM1_R0_EN_POS (18U) +#define TZC_SEC_TZC_ROM1_R0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_EN TZC_SEC_TZC_ROM1_R1_EN +#define TZC_SEC_TZC_ROM1_R1_EN_POS (19U) +#define TZC_SEC_TZC_ROM1_R1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_LOCK TZC_SEC_TZC_ROM0_R0_LOCK +#define TZC_SEC_TZC_ROM0_R0_LOCK_POS (24U) +#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS) +#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)) +#define TZC_SEC_TZC_ROM0_R1_LOCK TZC_SEC_TZC_ROM0_R1_LOCK +#define TZC_SEC_TZC_ROM0_R1_LOCK_POS (25U) +#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS) +#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)) +#define TZC_SEC_TZC_ROM1_R0_LOCK TZC_SEC_TZC_ROM1_R0_LOCK +#define TZC_SEC_TZC_ROM1_R0_LOCK_POS (26U) +#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS) +#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)) +#define TZC_SEC_TZC_ROM1_R1_LOCK TZC_SEC_TZC_ROM1_R1_LOCK +#define TZC_SEC_TZC_ROM1_R1_LOCK_POS (27U) +#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS) +#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)) +#define TZC_SEC_TZC_SBOOT_DONE TZC_SEC_TZC_SBOOT_DONE +#define TZC_SEC_TZC_SBOOT_DONE_POS (28U) +#define TZC_SEC_TZC_SBOOT_DONE_LEN (4U) +#define TZC_SEC_TZC_SBOOT_DONE_MSK (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS) +#define TZC_SEC_TZC_SBOOT_DONE_UMSK (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)) + +/* 0x44 : tzc_rom0_r0 */ +#define TZC_SEC_TZC_ROM0_R0_OFFSET (0x44) +#define TZC_SEC_TZC_ROM0_R0_END TZC_SEC_TZC_ROM0_R0_END +#define TZC_SEC_TZC_ROM0_R0_END_POS (0U) +#define TZC_SEC_TZC_ROM0_R0_END_LEN (16U) +#define TZC_SEC_TZC_ROM0_R0_END_MSK (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS) +#define TZC_SEC_TZC_ROM0_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)) +#define TZC_SEC_TZC_ROM0_R0_START TZC_SEC_TZC_ROM0_R0_START +#define TZC_SEC_TZC_ROM0_R0_START_POS (16U) +#define TZC_SEC_TZC_ROM0_R0_START_LEN (16U) +#define TZC_SEC_TZC_ROM0_R0_START_MSK (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS) +#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)) + +/* 0x48 : tzc_rom0_r1 */ +#define TZC_SEC_TZC_ROM0_R1_OFFSET (0x48) +#define TZC_SEC_TZC_ROM0_R1_END TZC_SEC_TZC_ROM0_R1_END +#define TZC_SEC_TZC_ROM0_R1_END_POS (0U) +#define TZC_SEC_TZC_ROM0_R1_END_LEN (16U) +#define TZC_SEC_TZC_ROM0_R1_END_MSK (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS) +#define TZC_SEC_TZC_ROM0_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)) +#define TZC_SEC_TZC_ROM0_R1_START TZC_SEC_TZC_ROM0_R1_START +#define TZC_SEC_TZC_ROM0_R1_START_POS (16U) +#define TZC_SEC_TZC_ROM0_R1_START_LEN (16U) +#define TZC_SEC_TZC_ROM0_R1_START_MSK (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS) +#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)) + +/* 0x4C : tzc_rom1_r0 */ +#define TZC_SEC_TZC_ROM1_R0_OFFSET (0x4C) +#define TZC_SEC_TZC_ROM1_R0_END TZC_SEC_TZC_ROM1_R0_END +#define TZC_SEC_TZC_ROM1_R0_END_POS (0U) +#define TZC_SEC_TZC_ROM1_R0_END_LEN (16U) +#define TZC_SEC_TZC_ROM1_R0_END_MSK (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS) +#define TZC_SEC_TZC_ROM1_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)) +#define TZC_SEC_TZC_ROM1_R0_START TZC_SEC_TZC_ROM1_R0_START +#define TZC_SEC_TZC_ROM1_R0_START_POS (16U) +#define TZC_SEC_TZC_ROM1_R0_START_LEN (16U) +#define TZC_SEC_TZC_ROM1_R0_START_MSK (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS) +#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)) + +/* 0x50 : tzc_rom1_r1 */ +#define TZC_SEC_TZC_ROM1_R1_OFFSET (0x50) +#define TZC_SEC_TZC_ROM1_R1_END TZC_SEC_TZC_ROM1_R1_END +#define TZC_SEC_TZC_ROM1_R1_END_POS (0U) +#define TZC_SEC_TZC_ROM1_R1_END_LEN (16U) +#define TZC_SEC_TZC_ROM1_R1_END_MSK (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS) +#define TZC_SEC_TZC_ROM1_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)) +#define TZC_SEC_TZC_ROM1_R1_START TZC_SEC_TZC_ROM1_R1_START +#define TZC_SEC_TZC_ROM1_R1_START_POS (16U) +#define TZC_SEC_TZC_ROM1_R1_START_LEN (16U) +#define TZC_SEC_TZC_ROM1_R1_START_MSK (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS) +#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)) + +struct tzc_sec_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[64]; + + /* 0x40 : tzc_rom_ctrl */ + union { + struct + { + uint32_t tzc_rom0_r0_id0_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t tzc_rom0_r1_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t tzc_rom1_r0_id0_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t tzc_rom1_r1_id0_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_id1_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t tzc_rom0_r1_id1_en : 1; /* [ 9], r/w, 0x1 */ + uint32_t tzc_rom1_r0_id1_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t tzc_rom1_r1_id1_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_en : 1; /* [ 16], r/w, 0x0 */ + uint32_t tzc_rom0_r1_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t tzc_rom1_r0_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t tzc_rom1_r1_en : 1; /* [ 19], r/w, 0x0 */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_lock : 1; /* [ 24], r/w, 0x0 */ + uint32_t tzc_rom0_r1_lock : 1; /* [ 25], r/w, 0x0 */ + uint32_t tzc_rom1_r0_lock : 1; /* [ 26], r/w, 0x0 */ + uint32_t tzc_rom1_r1_lock : 1; /* [ 27], r/w, 0x0 */ + uint32_t tzc_sboot_done : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom_ctrl; + + /* 0x44 : tzc_rom0_r0 */ + union { + struct + { + uint32_t tzc_rom0_r0_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom0_r0_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom0_r0; + + /* 0x48 : tzc_rom0_r1 */ + union { + struct + { + uint32_t tzc_rom0_r1_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom0_r1_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom0_r1; + + /* 0x4C : tzc_rom1_r0 */ + union { + struct + { + uint32_t tzc_rom1_r0_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom1_r0_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom1_r0; + + /* 0x50 : tzc_rom1_r1 */ + union { + struct + { + uint32_t tzc_rom1_r1_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom1_r1_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom1_r1; +}; + +typedef volatile struct tzc_sec_reg tzc_sec_reg_t; + +#endif /* __TZC_SEC_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/uart_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/uart_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..6a53957c9f81c7d2e5ee7c72e3e3c9bb40cdd532 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/uart_reg.h @@ -0,0 +1,769 @@ +/** + ****************************************************************************** + * @file uart_reg.h + * @version V1.2 + * @date 2020-03-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#include "bl702.h" + +/* 0x0 : utx_config */ +#define UART_UTX_CONFIG_OFFSET (0x0) +#define UART_CR_UTX_EN UART_CR_UTX_EN +#define UART_CR_UTX_EN_POS (0U) +#define UART_CR_UTX_EN_LEN (1U) +#define UART_CR_UTX_EN_MSK (((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS) +#define UART_CR_UTX_EN_UMSK (~(((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)) +#define UART_CR_UTX_CTS_EN UART_CR_UTX_CTS_EN +#define UART_CR_UTX_CTS_EN_POS (1U) +#define UART_CR_UTX_CTS_EN_LEN (1U) +#define UART_CR_UTX_CTS_EN_MSK (((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS) +#define UART_CR_UTX_CTS_EN_UMSK (~(((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)) +#define UART_CR_UTX_FRM_EN UART_CR_UTX_FRM_EN +#define UART_CR_UTX_FRM_EN_POS (2U) +#define UART_CR_UTX_FRM_EN_LEN (1U) +#define UART_CR_UTX_FRM_EN_MSK (((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS) +#define UART_CR_UTX_FRM_EN_UMSK (~(((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)) +#define UART_CR_UTX_LIN_EN UART_CR_UTX_LIN_EN +#define UART_CR_UTX_LIN_EN_POS (3U) +#define UART_CR_UTX_LIN_EN_LEN (1U) +#define UART_CR_UTX_LIN_EN_MSK (((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS) +#define UART_CR_UTX_LIN_EN_UMSK (~(((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS)) +#define UART_CR_UTX_PRT_EN UART_CR_UTX_PRT_EN +#define UART_CR_UTX_PRT_EN_POS (4U) +#define UART_CR_UTX_PRT_EN_LEN (1U) +#define UART_CR_UTX_PRT_EN_MSK (((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS) +#define UART_CR_UTX_PRT_EN_UMSK (~(((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)) +#define UART_CR_UTX_PRT_SEL UART_CR_UTX_PRT_SEL +#define UART_CR_UTX_PRT_SEL_POS (5U) +#define UART_CR_UTX_PRT_SEL_LEN (1U) +#define UART_CR_UTX_PRT_SEL_MSK (((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS) +#define UART_CR_UTX_PRT_SEL_UMSK (~(((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)) +#define UART_CR_UTX_IR_EN UART_CR_UTX_IR_EN +#define UART_CR_UTX_IR_EN_POS (6U) +#define UART_CR_UTX_IR_EN_LEN (1U) +#define UART_CR_UTX_IR_EN_MSK (((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS) +#define UART_CR_UTX_IR_EN_UMSK (~(((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)) +#define UART_CR_UTX_IR_INV UART_CR_UTX_IR_INV +#define UART_CR_UTX_IR_INV_POS (7U) +#define UART_CR_UTX_IR_INV_LEN (1U) +#define UART_CR_UTX_IR_INV_MSK (((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS) +#define UART_CR_UTX_IR_INV_UMSK (~(((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)) +#define UART_CR_UTX_BIT_CNT_D UART_CR_UTX_BIT_CNT_D +#define UART_CR_UTX_BIT_CNT_D_POS (8U) +#define UART_CR_UTX_BIT_CNT_D_LEN (3U) +#define UART_CR_UTX_BIT_CNT_D_MSK (((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS) +#define UART_CR_UTX_BIT_CNT_D_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)) +#define UART_CR_UTX_BIT_CNT_P UART_CR_UTX_BIT_CNT_P +#define UART_CR_UTX_BIT_CNT_P_POS (11U) +#define UART_CR_UTX_BIT_CNT_P_LEN (2U) +#define UART_CR_UTX_BIT_CNT_P_MSK (((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS) +#define UART_CR_UTX_BIT_CNT_P_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)) +#define UART_CR_UTX_BIT_CNT_B UART_CR_UTX_BIT_CNT_B +#define UART_CR_UTX_BIT_CNT_B_POS (13U) +#define UART_CR_UTX_BIT_CNT_B_LEN (3U) +#define UART_CR_UTX_BIT_CNT_B_MSK (((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS) +#define UART_CR_UTX_BIT_CNT_B_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS)) +#define UART_CR_UTX_LEN UART_CR_UTX_LEN +#define UART_CR_UTX_LEN_POS (16U) +#define UART_CR_UTX_LEN_LEN (16U) +#define UART_CR_UTX_LEN_MSK (((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS) +#define UART_CR_UTX_LEN_UMSK (~(((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)) + +/* 0x4 : urx_config */ +#define UART_URX_CONFIG_OFFSET (0x4) +#define UART_CR_URX_EN UART_CR_URX_EN +#define UART_CR_URX_EN_POS (0U) +#define UART_CR_URX_EN_LEN (1U) +#define UART_CR_URX_EN_MSK (((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS) +#define UART_CR_URX_EN_UMSK (~(((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)) +#define UART_CR_URX_ABR_EN UART_CR_URX_ABR_EN +#define UART_CR_URX_ABR_EN_POS (1U) +#define UART_CR_URX_ABR_EN_LEN (1U) +#define UART_CR_URX_ABR_EN_MSK (((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS) +#define UART_CR_URX_ABR_EN_UMSK (~(((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)) +#define UART_CR_URX_LIN_EN UART_CR_URX_LIN_EN +#define UART_CR_URX_LIN_EN_POS (3U) +#define UART_CR_URX_LIN_EN_LEN (1U) +#define UART_CR_URX_LIN_EN_MSK (((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS) +#define UART_CR_URX_LIN_EN_UMSK (~(((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS)) +#define UART_CR_URX_PRT_EN UART_CR_URX_PRT_EN +#define UART_CR_URX_PRT_EN_POS (4U) +#define UART_CR_URX_PRT_EN_LEN (1U) +#define UART_CR_URX_PRT_EN_MSK (((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS) +#define UART_CR_URX_PRT_EN_UMSK (~(((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)) +#define UART_CR_URX_PRT_SEL UART_CR_URX_PRT_SEL +#define UART_CR_URX_PRT_SEL_POS (5U) +#define UART_CR_URX_PRT_SEL_LEN (1U) +#define UART_CR_URX_PRT_SEL_MSK (((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS) +#define UART_CR_URX_PRT_SEL_UMSK (~(((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)) +#define UART_CR_URX_IR_EN UART_CR_URX_IR_EN +#define UART_CR_URX_IR_EN_POS (6U) +#define UART_CR_URX_IR_EN_LEN (1U) +#define UART_CR_URX_IR_EN_MSK (((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS) +#define UART_CR_URX_IR_EN_UMSK (~(((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)) +#define UART_CR_URX_IR_INV UART_CR_URX_IR_INV +#define UART_CR_URX_IR_INV_POS (7U) +#define UART_CR_URX_IR_INV_LEN (1U) +#define UART_CR_URX_IR_INV_MSK (((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS) +#define UART_CR_URX_IR_INV_UMSK (~(((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)) +#define UART_CR_URX_BIT_CNT_D UART_CR_URX_BIT_CNT_D +#define UART_CR_URX_BIT_CNT_D_POS (8U) +#define UART_CR_URX_BIT_CNT_D_LEN (3U) +#define UART_CR_URX_BIT_CNT_D_MSK (((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS) +#define UART_CR_URX_BIT_CNT_D_UMSK (~(((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)) +#define UART_CR_URX_DEG_EN UART_CR_URX_DEG_EN +#define UART_CR_URX_DEG_EN_POS (11U) +#define UART_CR_URX_DEG_EN_LEN (1U) +#define UART_CR_URX_DEG_EN_MSK (((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS) +#define UART_CR_URX_DEG_EN_UMSK (~(((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)) +#define UART_CR_URX_DEG_CNT UART_CR_URX_DEG_CNT +#define UART_CR_URX_DEG_CNT_POS (12U) +#define UART_CR_URX_DEG_CNT_LEN (4U) +#define UART_CR_URX_DEG_CNT_MSK (((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS) +#define UART_CR_URX_DEG_CNT_UMSK (~(((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)) +#define UART_CR_URX_LEN UART_CR_URX_LEN +#define UART_CR_URX_LEN_POS (16U) +#define UART_CR_URX_LEN_LEN (16U) +#define UART_CR_URX_LEN_MSK (((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS) +#define UART_CR_URX_LEN_UMSK (~(((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)) + +/* 0x8 : uart_bit_prd */ +#define UART_BIT_PRD_OFFSET (0x8) +#define UART_CR_UTX_BIT_PRD UART_CR_UTX_BIT_PRD +#define UART_CR_UTX_BIT_PRD_POS (0U) +#define UART_CR_UTX_BIT_PRD_LEN (16U) +#define UART_CR_UTX_BIT_PRD_MSK (((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS) +#define UART_CR_UTX_BIT_PRD_UMSK (~(((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)) +#define UART_CR_URX_BIT_PRD UART_CR_URX_BIT_PRD +#define UART_CR_URX_BIT_PRD_POS (16U) +#define UART_CR_URX_BIT_PRD_LEN (16U) +#define UART_CR_URX_BIT_PRD_MSK (((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS) +#define UART_CR_URX_BIT_PRD_UMSK (~(((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)) + +/* 0xC : data_config */ +#define UART_DATA_CONFIG_OFFSET (0xC) +#define UART_CR_UART_BIT_INV UART_CR_UART_BIT_INV +#define UART_CR_UART_BIT_INV_POS (0U) +#define UART_CR_UART_BIT_INV_LEN (1U) +#define UART_CR_UART_BIT_INV_MSK (((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS) +#define UART_CR_UART_BIT_INV_UMSK (~(((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)) + +/* 0x10 : utx_ir_position */ +#define UART_UTX_IR_POSITION_OFFSET (0x10) +#define UART_CR_UTX_IR_POS_S UART_CR_UTX_IR_POS_S +#define UART_CR_UTX_IR_POS_S_POS (0U) +#define UART_CR_UTX_IR_POS_S_LEN (16U) +#define UART_CR_UTX_IR_POS_S_MSK (((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS) +#define UART_CR_UTX_IR_POS_S_UMSK (~(((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)) +#define UART_CR_UTX_IR_POS_P UART_CR_UTX_IR_POS_P +#define UART_CR_UTX_IR_POS_P_POS (16U) +#define UART_CR_UTX_IR_POS_P_LEN (16U) +#define UART_CR_UTX_IR_POS_P_MSK (((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS) +#define UART_CR_UTX_IR_POS_P_UMSK (~(((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)) + +/* 0x14 : urx_ir_position */ +#define UART_URX_IR_POSITION_OFFSET (0x14) +#define UART_CR_URX_IR_POS_S UART_CR_URX_IR_POS_S +#define UART_CR_URX_IR_POS_S_POS (0U) +#define UART_CR_URX_IR_POS_S_LEN (16U) +#define UART_CR_URX_IR_POS_S_MSK (((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS) +#define UART_CR_URX_IR_POS_S_UMSK (~(((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)) + +/* 0x18 : urx_rto_timer */ +#define UART_URX_RTO_TIMER_OFFSET (0x18) +#define UART_CR_URX_RTO_VALUE UART_CR_URX_RTO_VALUE +#define UART_CR_URX_RTO_VALUE_POS (0U) +#define UART_CR_URX_RTO_VALUE_LEN (8U) +#define UART_CR_URX_RTO_VALUE_MSK (((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS) +#define UART_CR_URX_RTO_VALUE_UMSK (~(((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)) + +/* 0x1C : uart_sw_mode */ +#define UART_SW_MODE_OFFSET (0x1C) +#define UART_CR_UTX_TXD_SW_MODE UART_CR_UTX_TXD_SW_MODE +#define UART_CR_UTX_TXD_SW_MODE_POS (0U) +#define UART_CR_UTX_TXD_SW_MODE_LEN (1U) +#define UART_CR_UTX_TXD_SW_MODE_MSK (((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS) +#define UART_CR_UTX_TXD_SW_MODE_UMSK (~(((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS)) +#define UART_CR_UTX_TXD_SW_VAL UART_CR_UTX_TXD_SW_VAL +#define UART_CR_UTX_TXD_SW_VAL_POS (1U) +#define UART_CR_UTX_TXD_SW_VAL_LEN (1U) +#define UART_CR_UTX_TXD_SW_VAL_MSK (((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS) +#define UART_CR_UTX_TXD_SW_VAL_UMSK (~(((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS)) +#define UART_CR_URX_RTS_SW_MODE UART_CR_URX_RTS_SW_MODE +#define UART_CR_URX_RTS_SW_MODE_POS (2U) +#define UART_CR_URX_RTS_SW_MODE_LEN (1U) +#define UART_CR_URX_RTS_SW_MODE_MSK (((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS) +#define UART_CR_URX_RTS_SW_MODE_UMSK (~(((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS)) +#define UART_CR_URX_RTS_SW_VAL UART_CR_URX_RTS_SW_VAL +#define UART_CR_URX_RTS_SW_VAL_POS (3U) +#define UART_CR_URX_RTS_SW_VAL_LEN (1U) +#define UART_CR_URX_RTS_SW_VAL_MSK (((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS) +#define UART_CR_URX_RTS_SW_VAL_UMSK (~(((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)) + +/* 0x20 : UART interrupt status */ +#define UART_INT_STS_OFFSET (0x20) +#define UART_UTX_END_INT UART_UTX_END_INT +#define UART_UTX_END_INT_POS (0U) +#define UART_UTX_END_INT_LEN (1U) +#define UART_UTX_END_INT_MSK (((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS) +#define UART_UTX_END_INT_UMSK (~(((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)) +#define UART_URX_END_INT UART_URX_END_INT +#define UART_URX_END_INT_POS (1U) +#define UART_URX_END_INT_LEN (1U) +#define UART_URX_END_INT_MSK (((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS) +#define UART_URX_END_INT_UMSK (~(((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)) +#define UART_UTX_FIFO_INT UART_UTX_FIFO_INT +#define UART_UTX_FIFO_INT_POS (2U) +#define UART_UTX_FIFO_INT_LEN (1U) +#define UART_UTX_FIFO_INT_MSK (((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS) +#define UART_UTX_FIFO_INT_UMSK (~(((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS)) +#define UART_URX_FIFO_INT UART_URX_FIFO_INT +#define UART_URX_FIFO_INT_POS (3U) +#define UART_URX_FIFO_INT_LEN (1U) +#define UART_URX_FIFO_INT_MSK (((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS) +#define UART_URX_FIFO_INT_UMSK (~(((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS)) +#define UART_URX_RTO_INT UART_URX_RTO_INT +#define UART_URX_RTO_INT_POS (4U) +#define UART_URX_RTO_INT_LEN (1U) +#define UART_URX_RTO_INT_MSK (((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS) +#define UART_URX_RTO_INT_UMSK (~(((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)) +#define UART_URX_PCE_INT UART_URX_PCE_INT +#define UART_URX_PCE_INT_POS (5U) +#define UART_URX_PCE_INT_LEN (1U) +#define UART_URX_PCE_INT_MSK (((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS) +#define UART_URX_PCE_INT_UMSK (~(((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)) +#define UART_UTX_FER_INT UART_UTX_FER_INT +#define UART_UTX_FER_INT_POS (6U) +#define UART_UTX_FER_INT_LEN (1U) +#define UART_UTX_FER_INT_MSK (((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS) +#define UART_UTX_FER_INT_UMSK (~(((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)) +#define UART_URX_FER_INT UART_URX_FER_INT +#define UART_URX_FER_INT_POS (7U) +#define UART_URX_FER_INT_LEN (1U) +#define UART_URX_FER_INT_MSK (((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS) +#define UART_URX_FER_INT_UMSK (~(((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)) +#define UART_URX_LSE_INT UART_URX_LSE_INT +#define UART_URX_LSE_INT_POS (8U) +#define UART_URX_LSE_INT_LEN (1U) +#define UART_URX_LSE_INT_MSK (((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS) +#define UART_URX_LSE_INT_UMSK (~(((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS)) + +/* 0x24 : UART interrupt mask */ +#define UART_INT_MASK_OFFSET (0x24) +#define UART_CR_UTX_END_MASK UART_CR_UTX_END_MASK +#define UART_CR_UTX_END_MASK_POS (0U) +#define UART_CR_UTX_END_MASK_LEN (1U) +#define UART_CR_UTX_END_MASK_MSK (((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS) +#define UART_CR_UTX_END_MASK_UMSK (~(((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)) +#define UART_CR_URX_END_MASK UART_CR_URX_END_MASK +#define UART_CR_URX_END_MASK_POS (1U) +#define UART_CR_URX_END_MASK_LEN (1U) +#define UART_CR_URX_END_MASK_MSK (((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS) +#define UART_CR_URX_END_MASK_UMSK (~(((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)) +#define UART_CR_UTX_FIFO_MASK UART_CR_UTX_FIFO_MASK +#define UART_CR_UTX_FIFO_MASK_POS (2U) +#define UART_CR_UTX_FIFO_MASK_LEN (1U) +#define UART_CR_UTX_FIFO_MASK_MSK (((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS) +#define UART_CR_UTX_FIFO_MASK_UMSK (~(((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS)) +#define UART_CR_URX_FIFO_MASK UART_CR_URX_FIFO_MASK +#define UART_CR_URX_FIFO_MASK_POS (3U) +#define UART_CR_URX_FIFO_MASK_LEN (1U) +#define UART_CR_URX_FIFO_MASK_MSK (((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS) +#define UART_CR_URX_FIFO_MASK_UMSK (~(((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS)) +#define UART_CR_URX_RTO_MASK UART_CR_URX_RTO_MASK +#define UART_CR_URX_RTO_MASK_POS (4U) +#define UART_CR_URX_RTO_MASK_LEN (1U) +#define UART_CR_URX_RTO_MASK_MSK (((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS) +#define UART_CR_URX_RTO_MASK_UMSK (~(((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)) +#define UART_CR_URX_PCE_MASK UART_CR_URX_PCE_MASK +#define UART_CR_URX_PCE_MASK_POS (5U) +#define UART_CR_URX_PCE_MASK_LEN (1U) +#define UART_CR_URX_PCE_MASK_MSK (((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS) +#define UART_CR_URX_PCE_MASK_UMSK (~(((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)) +#define UART_CR_UTX_FER_MASK UART_CR_UTX_FER_MASK +#define UART_CR_UTX_FER_MASK_POS (6U) +#define UART_CR_UTX_FER_MASK_LEN (1U) +#define UART_CR_UTX_FER_MASK_MSK (((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS) +#define UART_CR_UTX_FER_MASK_UMSK (~(((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)) +#define UART_CR_URX_FER_MASK UART_CR_URX_FER_MASK +#define UART_CR_URX_FER_MASK_POS (7U) +#define UART_CR_URX_FER_MASK_LEN (1U) +#define UART_CR_URX_FER_MASK_MSK (((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS) +#define UART_CR_URX_FER_MASK_UMSK (~(((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)) +#define UART_CR_URX_LSE_MASK UART_CR_URX_LSE_MASK +#define UART_CR_URX_LSE_MASK_POS (8U) +#define UART_CR_URX_LSE_MASK_LEN (1U) +#define UART_CR_URX_LSE_MASK_MSK (((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS) +#define UART_CR_URX_LSE_MASK_UMSK (~(((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS)) + +/* 0x28 : UART interrupt clear */ +#define UART_INT_CLEAR_OFFSET (0x28) +#define UART_CR_UTX_END_CLR UART_CR_UTX_END_CLR +#define UART_CR_UTX_END_CLR_POS (0U) +#define UART_CR_UTX_END_CLR_LEN (1U) +#define UART_CR_UTX_END_CLR_MSK (((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS) +#define UART_CR_UTX_END_CLR_UMSK (~(((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)) +#define UART_CR_URX_END_CLR UART_CR_URX_END_CLR +#define UART_CR_URX_END_CLR_POS (1U) +#define UART_CR_URX_END_CLR_LEN (1U) +#define UART_CR_URX_END_CLR_MSK (((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS) +#define UART_CR_URX_END_CLR_UMSK (~(((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)) +#define UART_CR_URX_RTO_CLR UART_CR_URX_RTO_CLR +#define UART_CR_URX_RTO_CLR_POS (4U) +#define UART_CR_URX_RTO_CLR_LEN (1U) +#define UART_CR_URX_RTO_CLR_MSK (((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS) +#define UART_CR_URX_RTO_CLR_UMSK (~(((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)) +#define UART_CR_URX_PCE_CLR UART_CR_URX_PCE_CLR +#define UART_CR_URX_PCE_CLR_POS (5U) +#define UART_CR_URX_PCE_CLR_LEN (1U) +#define UART_CR_URX_PCE_CLR_MSK (((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS) +#define UART_CR_URX_PCE_CLR_UMSK (~(((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)) +#define UART_CR_URX_LSE_CLR UART_CR_URX_LSE_CLR +#define UART_CR_URX_LSE_CLR_POS (8U) +#define UART_CR_URX_LSE_CLR_LEN (1U) +#define UART_CR_URX_LSE_CLR_MSK (((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS) +#define UART_CR_URX_LSE_CLR_UMSK (~(((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS)) + +/* 0x2C : UART interrupt enable */ +#define UART_INT_EN_OFFSET (0x2C) +#define UART_CR_UTX_END_EN UART_CR_UTX_END_EN +#define UART_CR_UTX_END_EN_POS (0U) +#define UART_CR_UTX_END_EN_LEN (1U) +#define UART_CR_UTX_END_EN_MSK (((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS) +#define UART_CR_UTX_END_EN_UMSK (~(((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)) +#define UART_CR_URX_END_EN UART_CR_URX_END_EN +#define UART_CR_URX_END_EN_POS (1U) +#define UART_CR_URX_END_EN_LEN (1U) +#define UART_CR_URX_END_EN_MSK (((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS) +#define UART_CR_URX_END_EN_UMSK (~(((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)) +#define UART_CR_UTX_FIFO_EN UART_CR_UTX_FIFO_EN +#define UART_CR_UTX_FIFO_EN_POS (2U) +#define UART_CR_UTX_FIFO_EN_LEN (1U) +#define UART_CR_UTX_FIFO_EN_MSK (((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS) +#define UART_CR_UTX_FIFO_EN_UMSK (~(((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS)) +#define UART_CR_URX_FIFO_EN UART_CR_URX_FIFO_EN +#define UART_CR_URX_FIFO_EN_POS (3U) +#define UART_CR_URX_FIFO_EN_LEN (1U) +#define UART_CR_URX_FIFO_EN_MSK (((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS) +#define UART_CR_URX_FIFO_EN_UMSK (~(((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS)) +#define UART_CR_URX_RTO_EN UART_CR_URX_RTO_EN +#define UART_CR_URX_RTO_EN_POS (4U) +#define UART_CR_URX_RTO_EN_LEN (1U) +#define UART_CR_URX_RTO_EN_MSK (((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS) +#define UART_CR_URX_RTO_EN_UMSK (~(((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)) +#define UART_CR_URX_PCE_EN UART_CR_URX_PCE_EN +#define UART_CR_URX_PCE_EN_POS (5U) +#define UART_CR_URX_PCE_EN_LEN (1U) +#define UART_CR_URX_PCE_EN_MSK (((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS) +#define UART_CR_URX_PCE_EN_UMSK (~(((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)) +#define UART_CR_UTX_FER_EN UART_CR_UTX_FER_EN +#define UART_CR_UTX_FER_EN_POS (6U) +#define UART_CR_UTX_FER_EN_LEN (1U) +#define UART_CR_UTX_FER_EN_MSK (((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS) +#define UART_CR_UTX_FER_EN_UMSK (~(((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)) +#define UART_CR_URX_FER_EN UART_CR_URX_FER_EN +#define UART_CR_URX_FER_EN_POS (7U) +#define UART_CR_URX_FER_EN_LEN (1U) +#define UART_CR_URX_FER_EN_MSK (((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS) +#define UART_CR_URX_FER_EN_UMSK (~(((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)) +#define UART_CR_URX_LSE_EN UART_CR_URX_LSE_EN +#define UART_CR_URX_LSE_EN_POS (8U) +#define UART_CR_URX_LSE_EN_LEN (1U) +#define UART_CR_URX_LSE_EN_MSK (((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS) +#define UART_CR_URX_LSE_EN_UMSK (~(((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS)) + +/* 0x30 : uart_status */ +#define UART_STATUS_OFFSET (0x30) +#define UART_STS_UTX_BUS_BUSY UART_STS_UTX_BUS_BUSY +#define UART_STS_UTX_BUS_BUSY_POS (0U) +#define UART_STS_UTX_BUS_BUSY_LEN (1U) +#define UART_STS_UTX_BUS_BUSY_MSK (((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS) +#define UART_STS_UTX_BUS_BUSY_UMSK (~(((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)) +#define UART_STS_URX_BUS_BUSY UART_STS_URX_BUS_BUSY +#define UART_STS_URX_BUS_BUSY_POS (1U) +#define UART_STS_URX_BUS_BUSY_LEN (1U) +#define UART_STS_URX_BUS_BUSY_MSK (((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS) +#define UART_STS_URX_BUS_BUSY_UMSK (~(((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)) + +/* 0x34 : sts_urx_abr_prd */ +#define UART_STS_URX_ABR_PRD_OFFSET (0x34) +#define UART_STS_URX_ABR_PRD_START UART_STS_URX_ABR_PRD_START +#define UART_STS_URX_ABR_PRD_START_POS (0U) +#define UART_STS_URX_ABR_PRD_START_LEN (16U) +#define UART_STS_URX_ABR_PRD_START_MSK (((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS) +#define UART_STS_URX_ABR_PRD_START_UMSK (~(((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS)) +#define UART_STS_URX_ABR_PRD_0X55 UART_STS_URX_ABR_PRD_0X55 +#define UART_STS_URX_ABR_PRD_0X55_POS (16U) +#define UART_STS_URX_ABR_PRD_0X55_LEN (16U) +#define UART_STS_URX_ABR_PRD_0X55_MSK (((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS) +#define UART_STS_URX_ABR_PRD_0X55_UMSK (~(((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS)) + +/* 0x80 : uart_fifo_config_0 */ +#define UART_FIFO_CONFIG_0_OFFSET (0x80) +#define UART_DMA_TX_EN UART_DMA_TX_EN +#define UART_DMA_TX_EN_POS (0U) +#define UART_DMA_TX_EN_LEN (1U) +#define UART_DMA_TX_EN_MSK (((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS) +#define UART_DMA_TX_EN_UMSK (~(((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)) +#define UART_DMA_RX_EN UART_DMA_RX_EN +#define UART_DMA_RX_EN_POS (1U) +#define UART_DMA_RX_EN_LEN (1U) +#define UART_DMA_RX_EN_MSK (((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS) +#define UART_DMA_RX_EN_UMSK (~(((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)) +#define UART_TX_FIFO_CLR UART_TX_FIFO_CLR +#define UART_TX_FIFO_CLR_POS (2U) +#define UART_TX_FIFO_CLR_LEN (1U) +#define UART_TX_FIFO_CLR_MSK (((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS) +#define UART_TX_FIFO_CLR_UMSK (~(((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)) +#define UART_RX_FIFO_CLR UART_RX_FIFO_CLR +#define UART_RX_FIFO_CLR_POS (3U) +#define UART_RX_FIFO_CLR_LEN (1U) +#define UART_RX_FIFO_CLR_MSK (((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS) +#define UART_RX_FIFO_CLR_UMSK (~(((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)) +#define UART_TX_FIFO_OVERFLOW UART_TX_FIFO_OVERFLOW +#define UART_TX_FIFO_OVERFLOW_POS (4U) +#define UART_TX_FIFO_OVERFLOW_LEN (1U) +#define UART_TX_FIFO_OVERFLOW_MSK (((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS) +#define UART_TX_FIFO_OVERFLOW_UMSK (~(((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)) +#define UART_TX_FIFO_UNDERFLOW UART_TX_FIFO_UNDERFLOW +#define UART_TX_FIFO_UNDERFLOW_POS (5U) +#define UART_TX_FIFO_UNDERFLOW_LEN (1U) +#define UART_TX_FIFO_UNDERFLOW_MSK (((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS) +#define UART_TX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)) +#define UART_RX_FIFO_OVERFLOW UART_RX_FIFO_OVERFLOW +#define UART_RX_FIFO_OVERFLOW_POS (6U) +#define UART_RX_FIFO_OVERFLOW_LEN (1U) +#define UART_RX_FIFO_OVERFLOW_MSK (((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS) +#define UART_RX_FIFO_OVERFLOW_UMSK (~(((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)) +#define UART_RX_FIFO_UNDERFLOW UART_RX_FIFO_UNDERFLOW +#define UART_RX_FIFO_UNDERFLOW_POS (7U) +#define UART_RX_FIFO_UNDERFLOW_LEN (1U) +#define UART_RX_FIFO_UNDERFLOW_MSK (((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS) +#define UART_RX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)) + +/* 0x84 : uart_fifo_config_1 */ +#define UART_FIFO_CONFIG_1_OFFSET (0x84) +#define UART_TX_FIFO_CNT UART_TX_FIFO_CNT +#define UART_TX_FIFO_CNT_POS (0U) +#define UART_TX_FIFO_CNT_LEN (8U) +#define UART_TX_FIFO_CNT_MSK (((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS) +#define UART_TX_FIFO_CNT_UMSK (~(((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)) +#define UART_RX_FIFO_CNT UART_RX_FIFO_CNT +#define UART_RX_FIFO_CNT_POS (8U) +#define UART_RX_FIFO_CNT_LEN (8U) +#define UART_RX_FIFO_CNT_MSK (((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS) +#define UART_RX_FIFO_CNT_UMSK (~(((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)) +#define UART_TX_FIFO_TH UART_TX_FIFO_TH +#define UART_TX_FIFO_TH_POS (16U) +#define UART_TX_FIFO_TH_LEN (7U) +#define UART_TX_FIFO_TH_MSK (((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS) +#define UART_TX_FIFO_TH_UMSK (~(((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)) +#define UART_RX_FIFO_TH UART_RX_FIFO_TH +#define UART_RX_FIFO_TH_POS (24U) +#define UART_RX_FIFO_TH_LEN (7U) +#define UART_RX_FIFO_TH_MSK (((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS) +#define UART_RX_FIFO_TH_UMSK (~(((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)) + +/* 0x88 : uart_fifo_wdata */ +#define UART_FIFO_WDATA_OFFSET (0x88) +#define UART_FIFO_WDATA UART_FIFO_WDATA +#define UART_FIFO_WDATA_POS (0U) +#define UART_FIFO_WDATA_LEN (8U) +#define UART_FIFO_WDATA_MSK (((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS) +#define UART_FIFO_WDATA_UMSK (~(((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)) + +/* 0x8C : uart_fifo_rdata */ +#define UART_FIFO_RDATA_OFFSET (0x8C) +#define UART_FIFO_RDATA UART_FIFO_RDATA +#define UART_FIFO_RDATA_POS (0U) +#define UART_FIFO_RDATA_LEN (8U) +#define UART_FIFO_RDATA_MSK (((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS) +#define UART_FIFO_RDATA_UMSK (~(((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)) + +struct uart_reg { + /* 0x0 : utx_config */ + union { + struct + { + uint32_t cr_utx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_utx_cts_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_utx_frm_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_utx_lin_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_utx_prt_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_utx_prt_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_utx_ir_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_utx_ir_inv : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_utx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ + uint32_t cr_utx_bit_cnt_p : 2; /* [12:11], r/w, 0x1 */ + uint32_t cr_utx_bit_cnt_b : 3; /* [15:13], r/w, 0x4 */ + uint32_t cr_utx_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } utx_config; + + /* 0x4 : urx_config */ + union { + struct + { + uint32_t cr_urx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_urx_abr_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */ + uint32_t cr_urx_lin_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_urx_prt_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_urx_prt_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t cr_urx_ir_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t cr_urx_ir_inv : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_urx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ + uint32_t cr_urx_deg_en : 1; /* [ 11], r/w, 0x0 */ + uint32_t cr_urx_deg_cnt : 4; /* [15:12], r/w, 0x0 */ + uint32_t cr_urx_len : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } urx_config; + + /* 0x8 : uart_bit_prd */ + union { + struct + { + uint32_t cr_utx_bit_prd : 16; /* [15: 0], r/w, 0xff */ + uint32_t cr_urx_bit_prd : 16; /* [31:16], r/w, 0xff */ + } BF; + uint32_t WORD; + } uart_bit_prd; + + /* 0xC : data_config */ + union { + struct + { + uint32_t cr_uart_bit_inv : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } data_config; + + /* 0x10 : utx_ir_position */ + union { + struct + { + uint32_t cr_utx_ir_pos_s : 16; /* [15: 0], r/w, 0x70 */ + uint32_t cr_utx_ir_pos_p : 16; /* [31:16], r/w, 0x9f */ + } BF; + uint32_t WORD; + } utx_ir_position; + + /* 0x14 : urx_ir_position */ + union { + struct + { + uint32_t cr_urx_ir_pos_s : 16; /* [15: 0], r/w, 0x6f */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } urx_ir_position; + + /* 0x18 : urx_rto_timer */ + union { + struct + { + uint32_t cr_urx_rto_value : 8; /* [ 7: 0], r/w, 0xf */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } urx_rto_timer; + + /* 0x1C : uart_sw_mode */ + union { + struct + { + uint32_t cr_utx_txd_sw_mode : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_utx_txd_sw_val : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_urx_rts_sw_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_urx_rts_sw_val : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_sw_mode; + + /* 0x20 : UART interrupt status */ + union { + struct + { + uint32_t utx_end_int : 1; /* [ 0], r, 0x0 */ + uint32_t urx_end_int : 1; /* [ 1], r, 0x0 */ + uint32_t utx_fifo_int : 1; /* [ 2], r, 0x0 */ + uint32_t urx_fifo_int : 1; /* [ 3], r, 0x0 */ + uint32_t urx_rto_int : 1; /* [ 4], r, 0x0 */ + uint32_t urx_pce_int : 1; /* [ 5], r, 0x0 */ + uint32_t utx_fer_int : 1; /* [ 6], r, 0x0 */ + uint32_t urx_fer_int : 1; /* [ 7], r, 0x0 */ + uint32_t urx_lse_int : 1; /* [ 8], r, 0x0 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_int_sts; + + /* 0x24 : UART interrupt mask */ + union { + struct + { + uint32_t cr_utx_end_mask : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_urx_end_mask : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_utx_fifo_mask : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_urx_fifo_mask : 1; /* [ 3], r/w, 0x1 */ + uint32_t cr_urx_rto_mask : 1; /* [ 4], r/w, 0x1 */ + uint32_t cr_urx_pce_mask : 1; /* [ 5], r/w, 0x1 */ + uint32_t cr_utx_fer_mask : 1; /* [ 6], r/w, 0x1 */ + uint32_t cr_urx_fer_mask : 1; /* [ 7], r/w, 0x1 */ + uint32_t cr_urx_lse_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_int_mask; + + /* 0x28 : UART interrupt clear */ + union { + struct + { + uint32_t cr_utx_end_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t cr_urx_end_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */ + uint32_t rsvd_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t cr_urx_rto_clr : 1; /* [ 4], w1c, 0x0 */ + uint32_t cr_urx_pce_clr : 1; /* [ 5], w1c, 0x0 */ + uint32_t rsvd_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t rsvd_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cr_urx_lse_clr : 1; /* [ 8], w1c, 0x0 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_int_clear; + + /* 0x2C : UART interrupt enable */ + union { + struct + { + uint32_t cr_utx_end_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_urx_end_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_utx_fifo_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_urx_fifo_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t cr_urx_rto_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t cr_urx_pce_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t cr_utx_fer_en : 1; /* [ 6], r/w, 0x1 */ + uint32_t cr_urx_fer_en : 1; /* [ 7], r/w, 0x1 */ + uint32_t cr_urx_lse_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_int_en; + + /* 0x30 : uart_status */ + union { + struct + { + uint32_t sts_utx_bus_busy : 1; /* [ 0], r, 0x0 */ + uint32_t sts_urx_bus_busy : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_status; + + /* 0x34 : sts_urx_abr_prd */ + union { + struct + { + uint32_t sts_urx_abr_prd_start : 16; /* [15: 0], r, 0x0 */ + uint32_t sts_urx_abr_prd_0x55 : 16; /* [31:16], r, 0x0 */ + } BF; + uint32_t WORD; + } sts_urx_abr_prd; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[72]; + + /* 0x80 : uart_fifo_config_0 */ + union { + struct + { + uint32_t uart_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t uart_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_fifo_config_0; + + /* 0x84 : uart_fifo_config_1 */ + union { + struct + { + uint32_t tx_fifo_cnt : 8; /* [ 7: 0], r, 0x80 */ + uint32_t rx_fifo_cnt : 8; /* [15: 8], r, 0x0 */ + uint32_t tx_fifo_th : 7; /* [22:16], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t rx_fifo_th : 7; /* [30:24], r/w, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_fifo_config_1; + + /* 0x88 : uart_fifo_wdata */ + union { + struct + { + uint32_t uart_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_fifo_wdata; + + /* 0x8C : uart_fifo_rdata */ + union { + struct + { + uint32_t uart_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } uart_fifo_rdata; +}; + +typedef volatile struct uart_reg uart_reg_t; + +#endif /* __UART_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/usb_reg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/usb_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..941206649bb11883219c6f80dd01aa4dc06432f8 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/regs/usb_reg.h @@ -0,0 +1,2758 @@ +/** + ****************************************************************************** + * @file usb_reg.h + * @version V1.2 + * @date 2020-09-04 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __USB_REG_H__ +#define __USB_REG_H__ + +#include "bl702.h" + +/* 0x0 : usb_config */ +#define USB_CONFIG_OFFSET (0x0) +#define USB_CR_USB_EN USB_CR_USB_EN +#define USB_CR_USB_EN_POS (0U) +#define USB_CR_USB_EN_LEN (1U) +#define USB_CR_USB_EN_MSK (((1U << USB_CR_USB_EN_LEN) - 1) << USB_CR_USB_EN_POS) +#define USB_CR_USB_EN_UMSK (~(((1U << USB_CR_USB_EN_LEN) - 1) << USB_CR_USB_EN_POS)) +#define USB_CR_USB_ROM_DCT_EN USB_CR_USB_ROM_DCT_EN +#define USB_CR_USB_ROM_DCT_EN_POS (4U) +#define USB_CR_USB_ROM_DCT_EN_LEN (1U) +#define USB_CR_USB_ROM_DCT_EN_MSK (((1U << USB_CR_USB_ROM_DCT_EN_LEN) - 1) << USB_CR_USB_ROM_DCT_EN_POS) +#define USB_CR_USB_ROM_DCT_EN_UMSK (~(((1U << USB_CR_USB_ROM_DCT_EN_LEN) - 1) << USB_CR_USB_ROM_DCT_EN_POS)) +#define USB_CR_USB_EP0_SW_CTRL USB_CR_USB_EP0_SW_CTRL +#define USB_CR_USB_EP0_SW_CTRL_POS (8U) +#define USB_CR_USB_EP0_SW_CTRL_LEN (1U) +#define USB_CR_USB_EP0_SW_CTRL_MSK (((1U << USB_CR_USB_EP0_SW_CTRL_LEN) - 1) << USB_CR_USB_EP0_SW_CTRL_POS) +#define USB_CR_USB_EP0_SW_CTRL_UMSK (~(((1U << USB_CR_USB_EP0_SW_CTRL_LEN) - 1) << USB_CR_USB_EP0_SW_CTRL_POS)) +#define USB_CR_USB_EP0_SW_ADDR USB_CR_USB_EP0_SW_ADDR +#define USB_CR_USB_EP0_SW_ADDR_POS (9U) +#define USB_CR_USB_EP0_SW_ADDR_LEN (7U) +#define USB_CR_USB_EP0_SW_ADDR_MSK (((1U << USB_CR_USB_EP0_SW_ADDR_LEN) - 1) << USB_CR_USB_EP0_SW_ADDR_POS) +#define USB_CR_USB_EP0_SW_ADDR_UMSK (~(((1U << USB_CR_USB_EP0_SW_ADDR_LEN) - 1) << USB_CR_USB_EP0_SW_ADDR_POS)) +#define USB_CR_USB_EP0_SW_SIZE USB_CR_USB_EP0_SW_SIZE +#define USB_CR_USB_EP0_SW_SIZE_POS (16U) +#define USB_CR_USB_EP0_SW_SIZE_LEN (8U) +#define USB_CR_USB_EP0_SW_SIZE_MSK (((1U << USB_CR_USB_EP0_SW_SIZE_LEN) - 1) << USB_CR_USB_EP0_SW_SIZE_POS) +#define USB_CR_USB_EP0_SW_SIZE_UMSK (~(((1U << USB_CR_USB_EP0_SW_SIZE_LEN) - 1) << USB_CR_USB_EP0_SW_SIZE_POS)) +#define USB_CR_USB_EP0_SW_STALL USB_CR_USB_EP0_SW_STALL +#define USB_CR_USB_EP0_SW_STALL_POS (24U) +#define USB_CR_USB_EP0_SW_STALL_LEN (1U) +#define USB_CR_USB_EP0_SW_STALL_MSK (((1U << USB_CR_USB_EP0_SW_STALL_LEN) - 1) << USB_CR_USB_EP0_SW_STALL_POS) +#define USB_CR_USB_EP0_SW_STALL_UMSK (~(((1U << USB_CR_USB_EP0_SW_STALL_LEN) - 1) << USB_CR_USB_EP0_SW_STALL_POS)) +#define USB_CR_USB_EP0_SW_NACK_IN USB_CR_USB_EP0_SW_NACK_IN +#define USB_CR_USB_EP0_SW_NACK_IN_POS (25U) +#define USB_CR_USB_EP0_SW_NACK_IN_LEN (1U) +#define USB_CR_USB_EP0_SW_NACK_IN_MSK (((1U << USB_CR_USB_EP0_SW_NACK_IN_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_IN_POS) +#define USB_CR_USB_EP0_SW_NACK_IN_UMSK (~(((1U << USB_CR_USB_EP0_SW_NACK_IN_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_IN_POS)) +#define USB_CR_USB_EP0_SW_NACK_OUT USB_CR_USB_EP0_SW_NACK_OUT +#define USB_CR_USB_EP0_SW_NACK_OUT_POS (26U) +#define USB_CR_USB_EP0_SW_NACK_OUT_LEN (1U) +#define USB_CR_USB_EP0_SW_NACK_OUT_MSK (((1U << USB_CR_USB_EP0_SW_NACK_OUT_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_OUT_POS) +#define USB_CR_USB_EP0_SW_NACK_OUT_UMSK (~(((1U << USB_CR_USB_EP0_SW_NACK_OUT_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_OUT_POS)) +#define USB_CR_USB_EP0_SW_RDY USB_CR_USB_EP0_SW_RDY +#define USB_CR_USB_EP0_SW_RDY_POS (27U) +#define USB_CR_USB_EP0_SW_RDY_LEN (1U) +#define USB_CR_USB_EP0_SW_RDY_MSK (((1U << USB_CR_USB_EP0_SW_RDY_LEN) - 1) << USB_CR_USB_EP0_SW_RDY_POS) +#define USB_CR_USB_EP0_SW_RDY_UMSK (~(((1U << USB_CR_USB_EP0_SW_RDY_LEN) - 1) << USB_CR_USB_EP0_SW_RDY_POS)) +#define USB_STS_USB_EP0_SW_RDY USB_STS_USB_EP0_SW_RDY +#define USB_STS_USB_EP0_SW_RDY_POS (28U) +#define USB_STS_USB_EP0_SW_RDY_LEN (1U) +#define USB_STS_USB_EP0_SW_RDY_MSK (((1U << USB_STS_USB_EP0_SW_RDY_LEN) - 1) << USB_STS_USB_EP0_SW_RDY_POS) +#define USB_STS_USB_EP0_SW_RDY_UMSK (~(((1U << USB_STS_USB_EP0_SW_RDY_LEN) - 1) << USB_STS_USB_EP0_SW_RDY_POS)) + +/* 0x4 : usb_lpm_config */ +#define USB_LPM_CONFIG_OFFSET (0x4) +#define USB_CR_LPM_EN USB_CR_LPM_EN +#define USB_CR_LPM_EN_POS (0U) +#define USB_CR_LPM_EN_LEN (1U) +#define USB_CR_LPM_EN_MSK (((1U << USB_CR_LPM_EN_LEN) - 1) << USB_CR_LPM_EN_POS) +#define USB_CR_LPM_EN_UMSK (~(((1U << USB_CR_LPM_EN_LEN) - 1) << USB_CR_LPM_EN_POS)) +#define USB_CR_LPM_RESP_UPD USB_CR_LPM_RESP_UPD +#define USB_CR_LPM_RESP_UPD_POS (1U) +#define USB_CR_LPM_RESP_UPD_LEN (1U) +#define USB_CR_LPM_RESP_UPD_MSK (((1U << USB_CR_LPM_RESP_UPD_LEN) - 1) << USB_CR_LPM_RESP_UPD_POS) +#define USB_CR_LPM_RESP_UPD_UMSK (~(((1U << USB_CR_LPM_RESP_UPD_LEN) - 1) << USB_CR_LPM_RESP_UPD_POS)) +#define USB_CR_LPM_RESP USB_CR_LPM_RESP +#define USB_CR_LPM_RESP_POS (2U) +#define USB_CR_LPM_RESP_LEN (2U) +#define USB_CR_LPM_RESP_MSK (((1U << USB_CR_LPM_RESP_LEN) - 1) << USB_CR_LPM_RESP_POS) +#define USB_CR_LPM_RESP_UMSK (~(((1U << USB_CR_LPM_RESP_LEN) - 1) << USB_CR_LPM_RESP_POS)) +#define USB_STS_LPM_ATTR USB_STS_LPM_ATTR +#define USB_STS_LPM_ATTR_POS (20U) +#define USB_STS_LPM_ATTR_LEN (11U) +#define USB_STS_LPM_ATTR_MSK (((1U << USB_STS_LPM_ATTR_LEN) - 1) << USB_STS_LPM_ATTR_POS) +#define USB_STS_LPM_ATTR_UMSK (~(((1U << USB_STS_LPM_ATTR_LEN) - 1) << USB_STS_LPM_ATTR_POS)) +#define USB_STS_LPM USB_STS_LPM +#define USB_STS_LPM_POS (31U) +#define USB_STS_LPM_LEN (1U) +#define USB_STS_LPM_MSK (((1U << USB_STS_LPM_LEN) - 1) << USB_STS_LPM_POS) +#define USB_STS_LPM_UMSK (~(((1U << USB_STS_LPM_LEN) - 1) << USB_STS_LPM_POS)) + +/* 0x8 : usb_resume_config */ +#define USB_RESUME_CONFIG_OFFSET (0x8) +#define USB_CR_RES_WIDTH USB_CR_RES_WIDTH +#define USB_CR_RES_WIDTH_POS (0U) +#define USB_CR_RES_WIDTH_LEN (11U) +#define USB_CR_RES_WIDTH_MSK (((1U << USB_CR_RES_WIDTH_LEN) - 1) << USB_CR_RES_WIDTH_POS) +#define USB_CR_RES_WIDTH_UMSK (~(((1U << USB_CR_RES_WIDTH_LEN) - 1) << USB_CR_RES_WIDTH_POS)) +#define USB_CR_RES_TRIG USB_CR_RES_TRIG +#define USB_CR_RES_TRIG_POS (12U) +#define USB_CR_RES_TRIG_LEN (1U) +#define USB_CR_RES_TRIG_MSK (((1U << USB_CR_RES_TRIG_LEN) - 1) << USB_CR_RES_TRIG_POS) +#define USB_CR_RES_TRIG_UMSK (~(((1U << USB_CR_RES_TRIG_LEN) - 1) << USB_CR_RES_TRIG_POS)) +#define USB_CR_RES_FORCE USB_CR_RES_FORCE +#define USB_CR_RES_FORCE_POS (31U) +#define USB_CR_RES_FORCE_LEN (1U) +#define USB_CR_RES_FORCE_MSK (((1U << USB_CR_RES_FORCE_LEN) - 1) << USB_CR_RES_FORCE_POS) +#define USB_CR_RES_FORCE_UMSK (~(((1U << USB_CR_RES_FORCE_LEN) - 1) << USB_CR_RES_FORCE_POS)) + +/* 0x10 : usb_setup_data_0 */ +#define USB_SETUP_DATA_0_OFFSET (0x10) +#define USB_STS_SETUP_DATA_B0 USB_STS_SETUP_DATA_B0 +#define USB_STS_SETUP_DATA_B0_POS (0U) +#define USB_STS_SETUP_DATA_B0_LEN (8U) +#define USB_STS_SETUP_DATA_B0_MSK (((1U << USB_STS_SETUP_DATA_B0_LEN) - 1) << USB_STS_SETUP_DATA_B0_POS) +#define USB_STS_SETUP_DATA_B0_UMSK (~(((1U << USB_STS_SETUP_DATA_B0_LEN) - 1) << USB_STS_SETUP_DATA_B0_POS)) +#define USB_STS_SETUP_DATA_B1 USB_STS_SETUP_DATA_B1 +#define USB_STS_SETUP_DATA_B1_POS (8U) +#define USB_STS_SETUP_DATA_B1_LEN (8U) +#define USB_STS_SETUP_DATA_B1_MSK (((1U << USB_STS_SETUP_DATA_B1_LEN) - 1) << USB_STS_SETUP_DATA_B1_POS) +#define USB_STS_SETUP_DATA_B1_UMSK (~(((1U << USB_STS_SETUP_DATA_B1_LEN) - 1) << USB_STS_SETUP_DATA_B1_POS)) +#define USB_STS_SETUP_DATA_B2 USB_STS_SETUP_DATA_B2 +#define USB_STS_SETUP_DATA_B2_POS (16U) +#define USB_STS_SETUP_DATA_B2_LEN (8U) +#define USB_STS_SETUP_DATA_B2_MSK (((1U << USB_STS_SETUP_DATA_B2_LEN) - 1) << USB_STS_SETUP_DATA_B2_POS) +#define USB_STS_SETUP_DATA_B2_UMSK (~(((1U << USB_STS_SETUP_DATA_B2_LEN) - 1) << USB_STS_SETUP_DATA_B2_POS)) +#define USB_STS_SETUP_DATA_B3 USB_STS_SETUP_DATA_B3 +#define USB_STS_SETUP_DATA_B3_POS (24U) +#define USB_STS_SETUP_DATA_B3_LEN (8U) +#define USB_STS_SETUP_DATA_B3_MSK (((1U << USB_STS_SETUP_DATA_B3_LEN) - 1) << USB_STS_SETUP_DATA_B3_POS) +#define USB_STS_SETUP_DATA_B3_UMSK (~(((1U << USB_STS_SETUP_DATA_B3_LEN) - 1) << USB_STS_SETUP_DATA_B3_POS)) + +/* 0x14 : usb_setup_data_1 */ +#define USB_SETUP_DATA_1_OFFSET (0x14) +#define USB_STS_SETUP_DATA_B4 USB_STS_SETUP_DATA_B4 +#define USB_STS_SETUP_DATA_B4_POS (0U) +#define USB_STS_SETUP_DATA_B4_LEN (8U) +#define USB_STS_SETUP_DATA_B4_MSK (((1U << USB_STS_SETUP_DATA_B4_LEN) - 1) << USB_STS_SETUP_DATA_B4_POS) +#define USB_STS_SETUP_DATA_B4_UMSK (~(((1U << USB_STS_SETUP_DATA_B4_LEN) - 1) << USB_STS_SETUP_DATA_B4_POS)) +#define USB_STS_SETUP_DATA_B5 USB_STS_SETUP_DATA_B5 +#define USB_STS_SETUP_DATA_B5_POS (8U) +#define USB_STS_SETUP_DATA_B5_LEN (8U) +#define USB_STS_SETUP_DATA_B5_MSK (((1U << USB_STS_SETUP_DATA_B5_LEN) - 1) << USB_STS_SETUP_DATA_B5_POS) +#define USB_STS_SETUP_DATA_B5_UMSK (~(((1U << USB_STS_SETUP_DATA_B5_LEN) - 1) << USB_STS_SETUP_DATA_B5_POS)) +#define USB_STS_SETUP_DATA_B6 USB_STS_SETUP_DATA_B6 +#define USB_STS_SETUP_DATA_B6_POS (16U) +#define USB_STS_SETUP_DATA_B6_LEN (8U) +#define USB_STS_SETUP_DATA_B6_MSK (((1U << USB_STS_SETUP_DATA_B6_LEN) - 1) << USB_STS_SETUP_DATA_B6_POS) +#define USB_STS_SETUP_DATA_B6_UMSK (~(((1U << USB_STS_SETUP_DATA_B6_LEN) - 1) << USB_STS_SETUP_DATA_B6_POS)) +#define USB_STS_SETUP_DATA_B7 USB_STS_SETUP_DATA_B7 +#define USB_STS_SETUP_DATA_B7_POS (24U) +#define USB_STS_SETUP_DATA_B7_LEN (8U) +#define USB_STS_SETUP_DATA_B7_MSK (((1U << USB_STS_SETUP_DATA_B7_LEN) - 1) << USB_STS_SETUP_DATA_B7_POS) +#define USB_STS_SETUP_DATA_B7_UMSK (~(((1U << USB_STS_SETUP_DATA_B7_LEN) - 1) << USB_STS_SETUP_DATA_B7_POS)) + +/* 0x18 : usb_frame_no */ +#define USB_FRAME_NO_OFFSET (0x18) +#define USB_STS_FRAME_NO USB_STS_FRAME_NO +#define USB_STS_FRAME_NO_POS (0U) +#define USB_STS_FRAME_NO_LEN (11U) +#define USB_STS_FRAME_NO_MSK (((1U << USB_STS_FRAME_NO_LEN) - 1) << USB_STS_FRAME_NO_POS) +#define USB_STS_FRAME_NO_UMSK (~(((1U << USB_STS_FRAME_NO_LEN) - 1) << USB_STS_FRAME_NO_POS)) +#define USB_STS_PID USB_STS_PID +#define USB_STS_PID_POS (12U) +#define USB_STS_PID_LEN (4U) +#define USB_STS_PID_MSK (((1U << USB_STS_PID_LEN) - 1) << USB_STS_PID_POS) +#define USB_STS_PID_UMSK (~(((1U << USB_STS_PID_LEN) - 1) << USB_STS_PID_POS)) +#define USB_STS_EP_NO USB_STS_EP_NO +#define USB_STS_EP_NO_POS (16U) +#define USB_STS_EP_NO_LEN (4U) +#define USB_STS_EP_NO_MSK (((1U << USB_STS_EP_NO_LEN) - 1) << USB_STS_EP_NO_POS) +#define USB_STS_EP_NO_UMSK (~(((1U << USB_STS_EP_NO_LEN) - 1) << USB_STS_EP_NO_POS)) + +/* 0x1C : usb_error */ +#define USB_ERROR_OFFSET (0x1C) +#define USB_UTMI_RX_ERR USB_UTMI_RX_ERR +#define USB_UTMI_RX_ERR_POS (0U) +#define USB_UTMI_RX_ERR_LEN (1U) +#define USB_UTMI_RX_ERR_MSK (((1U << USB_UTMI_RX_ERR_LEN) - 1) << USB_UTMI_RX_ERR_POS) +#define USB_UTMI_RX_ERR_UMSK (~(((1U << USB_UTMI_RX_ERR_LEN) - 1) << USB_UTMI_RX_ERR_POS)) +#define USB_XFER_TO_ERR USB_XFER_TO_ERR +#define USB_XFER_TO_ERR_POS (1U) +#define USB_XFER_TO_ERR_LEN (1U) +#define USB_XFER_TO_ERR_MSK (((1U << USB_XFER_TO_ERR_LEN) - 1) << USB_XFER_TO_ERR_POS) +#define USB_XFER_TO_ERR_UMSK (~(((1U << USB_XFER_TO_ERR_LEN) - 1) << USB_XFER_TO_ERR_POS)) +#define USB_IVLD_EP_ERR USB_IVLD_EP_ERR +#define USB_IVLD_EP_ERR_POS (2U) +#define USB_IVLD_EP_ERR_LEN (1U) +#define USB_IVLD_EP_ERR_MSK (((1U << USB_IVLD_EP_ERR_LEN) - 1) << USB_IVLD_EP_ERR_POS) +#define USB_IVLD_EP_ERR_UMSK (~(((1U << USB_IVLD_EP_ERR_LEN) - 1) << USB_IVLD_EP_ERR_POS)) +#define USB_PID_SEQ_ERR USB_PID_SEQ_ERR +#define USB_PID_SEQ_ERR_POS (3U) +#define USB_PID_SEQ_ERR_LEN (1U) +#define USB_PID_SEQ_ERR_MSK (((1U << USB_PID_SEQ_ERR_LEN) - 1) << USB_PID_SEQ_ERR_POS) +#define USB_PID_SEQ_ERR_UMSK (~(((1U << USB_PID_SEQ_ERR_LEN) - 1) << USB_PID_SEQ_ERR_POS)) +#define USB_PID_CKS_ERR USB_PID_CKS_ERR +#define USB_PID_CKS_ERR_POS (4U) +#define USB_PID_CKS_ERR_LEN (1U) +#define USB_PID_CKS_ERR_MSK (((1U << USB_PID_CKS_ERR_LEN) - 1) << USB_PID_CKS_ERR_POS) +#define USB_PID_CKS_ERR_UMSK (~(((1U << USB_PID_CKS_ERR_LEN) - 1) << USB_PID_CKS_ERR_POS)) +#define USB_CRC5_ERR USB_CRC5_ERR +#define USB_CRC5_ERR_POS (5U) +#define USB_CRC5_ERR_LEN (1U) +#define USB_CRC5_ERR_MSK (((1U << USB_CRC5_ERR_LEN) - 1) << USB_CRC5_ERR_POS) +#define USB_CRC5_ERR_UMSK (~(((1U << USB_CRC5_ERR_LEN) - 1) << USB_CRC5_ERR_POS)) +#define USB_CRC16_ERR USB_CRC16_ERR +#define USB_CRC16_ERR_POS (6U) +#define USB_CRC16_ERR_LEN (1U) +#define USB_CRC16_ERR_MSK (((1U << USB_CRC16_ERR_LEN) - 1) << USB_CRC16_ERR_POS) +#define USB_CRC16_ERR_UMSK (~(((1U << USB_CRC16_ERR_LEN) - 1) << USB_CRC16_ERR_POS)) + +/* 0x20 : USB interrupt enable */ +#define USB_INT_EN_OFFSET (0x20) +#define USB_CR_SOF_EN USB_CR_SOF_EN +#define USB_CR_SOF_EN_POS (0U) +#define USB_CR_SOF_EN_LEN (1U) +#define USB_CR_SOF_EN_MSK (((1U << USB_CR_SOF_EN_LEN) - 1) << USB_CR_SOF_EN_POS) +#define USB_CR_SOF_EN_UMSK (~(((1U << USB_CR_SOF_EN_LEN) - 1) << USB_CR_SOF_EN_POS)) +#define USB_CR_USB_RESET_EN USB_CR_USB_RESET_EN +#define USB_CR_USB_RESET_EN_POS (1U) +#define USB_CR_USB_RESET_EN_LEN (1U) +#define USB_CR_USB_RESET_EN_MSK (((1U << USB_CR_USB_RESET_EN_LEN) - 1) << USB_CR_USB_RESET_EN_POS) +#define USB_CR_USB_RESET_EN_UMSK (~(((1U << USB_CR_USB_RESET_EN_LEN) - 1) << USB_CR_USB_RESET_EN_POS)) +#define USB_CR_VBUS_TGL_EN USB_CR_VBUS_TGL_EN +#define USB_CR_VBUS_TGL_EN_POS (2U) +#define USB_CR_VBUS_TGL_EN_LEN (1U) +#define USB_CR_VBUS_TGL_EN_MSK (((1U << USB_CR_VBUS_TGL_EN_LEN) - 1) << USB_CR_VBUS_TGL_EN_POS) +#define USB_CR_VBUS_TGL_EN_UMSK (~(((1U << USB_CR_VBUS_TGL_EN_LEN) - 1) << USB_CR_VBUS_TGL_EN_POS)) +#define USB_CR_GET_DCT_CMD_EN USB_CR_GET_DCT_CMD_EN +#define USB_CR_GET_DCT_CMD_EN_POS (3U) +#define USB_CR_GET_DCT_CMD_EN_LEN (1U) +#define USB_CR_GET_DCT_CMD_EN_MSK (((1U << USB_CR_GET_DCT_CMD_EN_LEN) - 1) << USB_CR_GET_DCT_CMD_EN_POS) +#define USB_CR_GET_DCT_CMD_EN_UMSK (~(((1U << USB_CR_GET_DCT_CMD_EN_LEN) - 1) << USB_CR_GET_DCT_CMD_EN_POS)) +#define USB_CR_EP0_SETUP_CMD_EN USB_CR_EP0_SETUP_CMD_EN +#define USB_CR_EP0_SETUP_CMD_EN_POS (4U) +#define USB_CR_EP0_SETUP_CMD_EN_LEN (1U) +#define USB_CR_EP0_SETUP_CMD_EN_MSK (((1U << USB_CR_EP0_SETUP_CMD_EN_LEN) - 1) << USB_CR_EP0_SETUP_CMD_EN_POS) +#define USB_CR_EP0_SETUP_CMD_EN_UMSK (~(((1U << USB_CR_EP0_SETUP_CMD_EN_LEN) - 1) << USB_CR_EP0_SETUP_CMD_EN_POS)) +#define USB_CR_EP0_SETUP_DONE_EN USB_CR_EP0_SETUP_DONE_EN +#define USB_CR_EP0_SETUP_DONE_EN_POS (5U) +#define USB_CR_EP0_SETUP_DONE_EN_LEN (1U) +#define USB_CR_EP0_SETUP_DONE_EN_MSK (((1U << USB_CR_EP0_SETUP_DONE_EN_LEN) - 1) << USB_CR_EP0_SETUP_DONE_EN_POS) +#define USB_CR_EP0_SETUP_DONE_EN_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_EN_LEN) - 1) << USB_CR_EP0_SETUP_DONE_EN_POS)) +#define USB_CR_EP0_IN_CMD_EN USB_CR_EP0_IN_CMD_EN +#define USB_CR_EP0_IN_CMD_EN_POS (6U) +#define USB_CR_EP0_IN_CMD_EN_LEN (1U) +#define USB_CR_EP0_IN_CMD_EN_MSK (((1U << USB_CR_EP0_IN_CMD_EN_LEN) - 1) << USB_CR_EP0_IN_CMD_EN_POS) +#define USB_CR_EP0_IN_CMD_EN_UMSK (~(((1U << USB_CR_EP0_IN_CMD_EN_LEN) - 1) << USB_CR_EP0_IN_CMD_EN_POS)) +#define USB_CR_EP0_IN_DONE_EN USB_CR_EP0_IN_DONE_EN +#define USB_CR_EP0_IN_DONE_EN_POS (7U) +#define USB_CR_EP0_IN_DONE_EN_LEN (1U) +#define USB_CR_EP0_IN_DONE_EN_MSK (((1U << USB_CR_EP0_IN_DONE_EN_LEN) - 1) << USB_CR_EP0_IN_DONE_EN_POS) +#define USB_CR_EP0_IN_DONE_EN_UMSK (~(((1U << USB_CR_EP0_IN_DONE_EN_LEN) - 1) << USB_CR_EP0_IN_DONE_EN_POS)) +#define USB_CR_EP0_OUT_CMD_EN USB_CR_EP0_OUT_CMD_EN +#define USB_CR_EP0_OUT_CMD_EN_POS (8U) +#define USB_CR_EP0_OUT_CMD_EN_LEN (1U) +#define USB_CR_EP0_OUT_CMD_EN_MSK (((1U << USB_CR_EP0_OUT_CMD_EN_LEN) - 1) << USB_CR_EP0_OUT_CMD_EN_POS) +#define USB_CR_EP0_OUT_CMD_EN_UMSK (~(((1U << USB_CR_EP0_OUT_CMD_EN_LEN) - 1) << USB_CR_EP0_OUT_CMD_EN_POS)) +#define USB_CR_EP0_OUT_DONE_EN USB_CR_EP0_OUT_DONE_EN +#define USB_CR_EP0_OUT_DONE_EN_POS (9U) +#define USB_CR_EP0_OUT_DONE_EN_LEN (1U) +#define USB_CR_EP0_OUT_DONE_EN_MSK (((1U << USB_CR_EP0_OUT_DONE_EN_LEN) - 1) << USB_CR_EP0_OUT_DONE_EN_POS) +#define USB_CR_EP0_OUT_DONE_EN_UMSK (~(((1U << USB_CR_EP0_OUT_DONE_EN_LEN) - 1) << USB_CR_EP0_OUT_DONE_EN_POS)) +#define USB_CR_EP1_CMD_EN USB_CR_EP1_CMD_EN +#define USB_CR_EP1_CMD_EN_POS (10U) +#define USB_CR_EP1_CMD_EN_LEN (1U) +#define USB_CR_EP1_CMD_EN_MSK (((1U << USB_CR_EP1_CMD_EN_LEN) - 1) << USB_CR_EP1_CMD_EN_POS) +#define USB_CR_EP1_CMD_EN_UMSK (~(((1U << USB_CR_EP1_CMD_EN_LEN) - 1) << USB_CR_EP1_CMD_EN_POS)) +#define USB_CR_EP1_DONE_EN USB_CR_EP1_DONE_EN +#define USB_CR_EP1_DONE_EN_POS (11U) +#define USB_CR_EP1_DONE_EN_LEN (1U) +#define USB_CR_EP1_DONE_EN_MSK (((1U << USB_CR_EP1_DONE_EN_LEN) - 1) << USB_CR_EP1_DONE_EN_POS) +#define USB_CR_EP1_DONE_EN_UMSK (~(((1U << USB_CR_EP1_DONE_EN_LEN) - 1) << USB_CR_EP1_DONE_EN_POS)) +#define USB_CR_EP2_CMD_EN USB_CR_EP2_CMD_EN +#define USB_CR_EP2_CMD_EN_POS (12U) +#define USB_CR_EP2_CMD_EN_LEN (1U) +#define USB_CR_EP2_CMD_EN_MSK (((1U << USB_CR_EP2_CMD_EN_LEN) - 1) << USB_CR_EP2_CMD_EN_POS) +#define USB_CR_EP2_CMD_EN_UMSK (~(((1U << USB_CR_EP2_CMD_EN_LEN) - 1) << USB_CR_EP2_CMD_EN_POS)) +#define USB_CR_EP2_DONE_EN USB_CR_EP2_DONE_EN +#define USB_CR_EP2_DONE_EN_POS (13U) +#define USB_CR_EP2_DONE_EN_LEN (1U) +#define USB_CR_EP2_DONE_EN_MSK (((1U << USB_CR_EP2_DONE_EN_LEN) - 1) << USB_CR_EP2_DONE_EN_POS) +#define USB_CR_EP2_DONE_EN_UMSK (~(((1U << USB_CR_EP2_DONE_EN_LEN) - 1) << USB_CR_EP2_DONE_EN_POS)) +#define USB_CR_EP3_CMD_EN USB_CR_EP3_CMD_EN +#define USB_CR_EP3_CMD_EN_POS (14U) +#define USB_CR_EP3_CMD_EN_LEN (1U) +#define USB_CR_EP3_CMD_EN_MSK (((1U << USB_CR_EP3_CMD_EN_LEN) - 1) << USB_CR_EP3_CMD_EN_POS) +#define USB_CR_EP3_CMD_EN_UMSK (~(((1U << USB_CR_EP3_CMD_EN_LEN) - 1) << USB_CR_EP3_CMD_EN_POS)) +#define USB_CR_EP3_DONE_EN USB_CR_EP3_DONE_EN +#define USB_CR_EP3_DONE_EN_POS (15U) +#define USB_CR_EP3_DONE_EN_LEN (1U) +#define USB_CR_EP3_DONE_EN_MSK (((1U << USB_CR_EP3_DONE_EN_LEN) - 1) << USB_CR_EP3_DONE_EN_POS) +#define USB_CR_EP3_DONE_EN_UMSK (~(((1U << USB_CR_EP3_DONE_EN_LEN) - 1) << USB_CR_EP3_DONE_EN_POS)) +#define USB_CR_EP4_CMD_EN USB_CR_EP4_CMD_EN +#define USB_CR_EP4_CMD_EN_POS (16U) +#define USB_CR_EP4_CMD_EN_LEN (1U) +#define USB_CR_EP4_CMD_EN_MSK (((1U << USB_CR_EP4_CMD_EN_LEN) - 1) << USB_CR_EP4_CMD_EN_POS) +#define USB_CR_EP4_CMD_EN_UMSK (~(((1U << USB_CR_EP4_CMD_EN_LEN) - 1) << USB_CR_EP4_CMD_EN_POS)) +#define USB_CR_EP4_DONE_EN USB_CR_EP4_DONE_EN +#define USB_CR_EP4_DONE_EN_POS (17U) +#define USB_CR_EP4_DONE_EN_LEN (1U) +#define USB_CR_EP4_DONE_EN_MSK (((1U << USB_CR_EP4_DONE_EN_LEN) - 1) << USB_CR_EP4_DONE_EN_POS) +#define USB_CR_EP4_DONE_EN_UMSK (~(((1U << USB_CR_EP4_DONE_EN_LEN) - 1) << USB_CR_EP4_DONE_EN_POS)) +#define USB_CR_EP5_CMD_EN USB_CR_EP5_CMD_EN +#define USB_CR_EP5_CMD_EN_POS (18U) +#define USB_CR_EP5_CMD_EN_LEN (1U) +#define USB_CR_EP5_CMD_EN_MSK (((1U << USB_CR_EP5_CMD_EN_LEN) - 1) << USB_CR_EP5_CMD_EN_POS) +#define USB_CR_EP5_CMD_EN_UMSK (~(((1U << USB_CR_EP5_CMD_EN_LEN) - 1) << USB_CR_EP5_CMD_EN_POS)) +#define USB_CR_EP5_DONE_EN USB_CR_EP5_DONE_EN +#define USB_CR_EP5_DONE_EN_POS (19U) +#define USB_CR_EP5_DONE_EN_LEN (1U) +#define USB_CR_EP5_DONE_EN_MSK (((1U << USB_CR_EP5_DONE_EN_LEN) - 1) << USB_CR_EP5_DONE_EN_POS) +#define USB_CR_EP5_DONE_EN_UMSK (~(((1U << USB_CR_EP5_DONE_EN_LEN) - 1) << USB_CR_EP5_DONE_EN_POS)) +#define USB_CR_EP6_CMD_EN USB_CR_EP6_CMD_EN +#define USB_CR_EP6_CMD_EN_POS (20U) +#define USB_CR_EP6_CMD_EN_LEN (1U) +#define USB_CR_EP6_CMD_EN_MSK (((1U << USB_CR_EP6_CMD_EN_LEN) - 1) << USB_CR_EP6_CMD_EN_POS) +#define USB_CR_EP6_CMD_EN_UMSK (~(((1U << USB_CR_EP6_CMD_EN_LEN) - 1) << USB_CR_EP6_CMD_EN_POS)) +#define USB_CR_EP6_DONE_EN USB_CR_EP6_DONE_EN +#define USB_CR_EP6_DONE_EN_POS (21U) +#define USB_CR_EP6_DONE_EN_LEN (1U) +#define USB_CR_EP6_DONE_EN_MSK (((1U << USB_CR_EP6_DONE_EN_LEN) - 1) << USB_CR_EP6_DONE_EN_POS) +#define USB_CR_EP6_DONE_EN_UMSK (~(((1U << USB_CR_EP6_DONE_EN_LEN) - 1) << USB_CR_EP6_DONE_EN_POS)) +#define USB_CR_EP7_CMD_EN USB_CR_EP7_CMD_EN +#define USB_CR_EP7_CMD_EN_POS (22U) +#define USB_CR_EP7_CMD_EN_LEN (1U) +#define USB_CR_EP7_CMD_EN_MSK (((1U << USB_CR_EP7_CMD_EN_LEN) - 1) << USB_CR_EP7_CMD_EN_POS) +#define USB_CR_EP7_CMD_EN_UMSK (~(((1U << USB_CR_EP7_CMD_EN_LEN) - 1) << USB_CR_EP7_CMD_EN_POS)) +#define USB_CR_EP7_DONE_EN USB_CR_EP7_DONE_EN +#define USB_CR_EP7_DONE_EN_POS (23U) +#define USB_CR_EP7_DONE_EN_LEN (1U) +#define USB_CR_EP7_DONE_EN_MSK (((1U << USB_CR_EP7_DONE_EN_LEN) - 1) << USB_CR_EP7_DONE_EN_POS) +#define USB_CR_EP7_DONE_EN_UMSK (~(((1U << USB_CR_EP7_DONE_EN_LEN) - 1) << USB_CR_EP7_DONE_EN_POS)) +#define USB_CR_USB_REND_EN USB_CR_USB_REND_EN +#define USB_CR_USB_REND_EN_POS (27U) +#define USB_CR_USB_REND_EN_LEN (1U) +#define USB_CR_USB_REND_EN_MSK (((1U << USB_CR_USB_REND_EN_LEN) - 1) << USB_CR_USB_REND_EN_POS) +#define USB_CR_USB_REND_EN_UMSK (~(((1U << USB_CR_USB_REND_EN_LEN) - 1) << USB_CR_USB_REND_EN_POS)) +#define USB_CR_LPM_WKUP_EN USB_CR_LPM_WKUP_EN +#define USB_CR_LPM_WKUP_EN_POS (28U) +#define USB_CR_LPM_WKUP_EN_LEN (1U) +#define USB_CR_LPM_WKUP_EN_MSK (((1U << USB_CR_LPM_WKUP_EN_LEN) - 1) << USB_CR_LPM_WKUP_EN_POS) +#define USB_CR_LPM_WKUP_EN_UMSK (~(((1U << USB_CR_LPM_WKUP_EN_LEN) - 1) << USB_CR_LPM_WKUP_EN_POS)) +#define USB_CR_LPM_PKT_EN USB_CR_LPM_PKT_EN +#define USB_CR_LPM_PKT_EN_POS (29U) +#define USB_CR_LPM_PKT_EN_LEN (1U) +#define USB_CR_LPM_PKT_EN_MSK (((1U << USB_CR_LPM_PKT_EN_LEN) - 1) << USB_CR_LPM_PKT_EN_POS) +#define USB_CR_LPM_PKT_EN_UMSK (~(((1U << USB_CR_LPM_PKT_EN_LEN) - 1) << USB_CR_LPM_PKT_EN_POS)) +#define USB_CR_SOF_3MS_EN USB_CR_SOF_3MS_EN +#define USB_CR_SOF_3MS_EN_POS (30U) +#define USB_CR_SOF_3MS_EN_LEN (1U) +#define USB_CR_SOF_3MS_EN_MSK (((1U << USB_CR_SOF_3MS_EN_LEN) - 1) << USB_CR_SOF_3MS_EN_POS) +#define USB_CR_SOF_3MS_EN_UMSK (~(((1U << USB_CR_SOF_3MS_EN_LEN) - 1) << USB_CR_SOF_3MS_EN_POS)) +#define USB_CR_USB_ERR_EN USB_CR_USB_ERR_EN +#define USB_CR_USB_ERR_EN_POS (31U) +#define USB_CR_USB_ERR_EN_LEN (1U) +#define USB_CR_USB_ERR_EN_MSK (((1U << USB_CR_USB_ERR_EN_LEN) - 1) << USB_CR_USB_ERR_EN_POS) +#define USB_CR_USB_ERR_EN_UMSK (~(((1U << USB_CR_USB_ERR_EN_LEN) - 1) << USB_CR_USB_ERR_EN_POS)) + +/* 0x24 : USB interrupt status */ +#define USB_INT_STS_OFFSET (0x24) +#define USB_SOF_INT USB_SOF_INT +#define USB_SOF_INT_POS (0U) +#define USB_SOF_INT_LEN (1U) +#define USB_SOF_INT_MSK (((1U << USB_SOF_INT_LEN) - 1) << USB_SOF_INT_POS) +#define USB_SOF_INT_UMSK (~(((1U << USB_SOF_INT_LEN) - 1) << USB_SOF_INT_POS)) +#define USB_RESET_INT USB_RESET_INT +#define USB_RESET_INT_POS (1U) +#define USB_RESET_INT_LEN (1U) +#define USB_RESET_INT_MSK (((1U << USB_RESET_INT_LEN) - 1) << USB_RESET_INT_POS) +#define USB_RESET_INT_UMSK (~(((1U << USB_RESET_INT_LEN) - 1) << USB_RESET_INT_POS)) +#define USB_VBUS_TGL_INT USB_VBUS_TGL_INT +#define USB_VBUS_TGL_INT_POS (2U) +#define USB_VBUS_TGL_INT_LEN (1U) +#define USB_VBUS_TGL_INT_MSK (((1U << USB_VBUS_TGL_INT_LEN) - 1) << USB_VBUS_TGL_INT_POS) +#define USB_VBUS_TGL_INT_UMSK (~(((1U << USB_VBUS_TGL_INT_LEN) - 1) << USB_VBUS_TGL_INT_POS)) +#define USB_GET_DCT_CMD_INT USB_GET_DCT_CMD_INT +#define USB_GET_DCT_CMD_INT_POS (3U) +#define USB_GET_DCT_CMD_INT_LEN (1U) +#define USB_GET_DCT_CMD_INT_MSK (((1U << USB_GET_DCT_CMD_INT_LEN) - 1) << USB_GET_DCT_CMD_INT_POS) +#define USB_GET_DCT_CMD_INT_UMSK (~(((1U << USB_GET_DCT_CMD_INT_LEN) - 1) << USB_GET_DCT_CMD_INT_POS)) +#define USB_EP0_SETUP_CMD_INT USB_EP0_SETUP_CMD_INT +#define USB_EP0_SETUP_CMD_INT_POS (4U) +#define USB_EP0_SETUP_CMD_INT_LEN (1U) +#define USB_EP0_SETUP_CMD_INT_MSK (((1U << USB_EP0_SETUP_CMD_INT_LEN) - 1) << USB_EP0_SETUP_CMD_INT_POS) +#define USB_EP0_SETUP_CMD_INT_UMSK (~(((1U << USB_EP0_SETUP_CMD_INT_LEN) - 1) << USB_EP0_SETUP_CMD_INT_POS)) +#define USB_EP0_SETUP_DONE_INT USB_EP0_SETUP_DONE_INT +#define USB_EP0_SETUP_DONE_INT_POS (5U) +#define USB_EP0_SETUP_DONE_INT_LEN (1U) +#define USB_EP0_SETUP_DONE_INT_MSK (((1U << USB_EP0_SETUP_DONE_INT_LEN) - 1) << USB_EP0_SETUP_DONE_INT_POS) +#define USB_EP0_SETUP_DONE_INT_UMSK (~(((1U << USB_EP0_SETUP_DONE_INT_LEN) - 1) << USB_EP0_SETUP_DONE_INT_POS)) +#define USB_EP0_IN_CMD_INT USB_EP0_IN_CMD_INT +#define USB_EP0_IN_CMD_INT_POS (6U) +#define USB_EP0_IN_CMD_INT_LEN (1U) +#define USB_EP0_IN_CMD_INT_MSK (((1U << USB_EP0_IN_CMD_INT_LEN) - 1) << USB_EP0_IN_CMD_INT_POS) +#define USB_EP0_IN_CMD_INT_UMSK (~(((1U << USB_EP0_IN_CMD_INT_LEN) - 1) << USB_EP0_IN_CMD_INT_POS)) +#define USB_EP0_IN_DONE_INT USB_EP0_IN_DONE_INT +#define USB_EP0_IN_DONE_INT_POS (7U) +#define USB_EP0_IN_DONE_INT_LEN (1U) +#define USB_EP0_IN_DONE_INT_MSK (((1U << USB_EP0_IN_DONE_INT_LEN) - 1) << USB_EP0_IN_DONE_INT_POS) +#define USB_EP0_IN_DONE_INT_UMSK (~(((1U << USB_EP0_IN_DONE_INT_LEN) - 1) << USB_EP0_IN_DONE_INT_POS)) +#define USB_EP0_OUT_CMD_INT USB_EP0_OUT_CMD_INT +#define USB_EP0_OUT_CMD_INT_POS (8U) +#define USB_EP0_OUT_CMD_INT_LEN (1U) +#define USB_EP0_OUT_CMD_INT_MSK (((1U << USB_EP0_OUT_CMD_INT_LEN) - 1) << USB_EP0_OUT_CMD_INT_POS) +#define USB_EP0_OUT_CMD_INT_UMSK (~(((1U << USB_EP0_OUT_CMD_INT_LEN) - 1) << USB_EP0_OUT_CMD_INT_POS)) +#define USB_EP0_OUT_DONE_INT USB_EP0_OUT_DONE_INT +#define USB_EP0_OUT_DONE_INT_POS (9U) +#define USB_EP0_OUT_DONE_INT_LEN (1U) +#define USB_EP0_OUT_DONE_INT_MSK (((1U << USB_EP0_OUT_DONE_INT_LEN) - 1) << USB_EP0_OUT_DONE_INT_POS) +#define USB_EP0_OUT_DONE_INT_UMSK (~(((1U << USB_EP0_OUT_DONE_INT_LEN) - 1) << USB_EP0_OUT_DONE_INT_POS)) +#define USB_EP1_CMD_INT USB_EP1_CMD_INT +#define USB_EP1_CMD_INT_POS (10U) +#define USB_EP1_CMD_INT_LEN (1U) +#define USB_EP1_CMD_INT_MSK (((1U << USB_EP1_CMD_INT_LEN) - 1) << USB_EP1_CMD_INT_POS) +#define USB_EP1_CMD_INT_UMSK (~(((1U << USB_EP1_CMD_INT_LEN) - 1) << USB_EP1_CMD_INT_POS)) +#define USB_EP1_DONE_INT USB_EP1_DONE_INT +#define USB_EP1_DONE_INT_POS (11U) +#define USB_EP1_DONE_INT_LEN (1U) +#define USB_EP1_DONE_INT_MSK (((1U << USB_EP1_DONE_INT_LEN) - 1) << USB_EP1_DONE_INT_POS) +#define USB_EP1_DONE_INT_UMSK (~(((1U << USB_EP1_DONE_INT_LEN) - 1) << USB_EP1_DONE_INT_POS)) +#define USB_EP2_CMD_INT USB_EP2_CMD_INT +#define USB_EP2_CMD_INT_POS (12U) +#define USB_EP2_CMD_INT_LEN (1U) +#define USB_EP2_CMD_INT_MSK (((1U << USB_EP2_CMD_INT_LEN) - 1) << USB_EP2_CMD_INT_POS) +#define USB_EP2_CMD_INT_UMSK (~(((1U << USB_EP2_CMD_INT_LEN) - 1) << USB_EP2_CMD_INT_POS)) +#define USB_EP2_DONE_INT USB_EP2_DONE_INT +#define USB_EP2_DONE_INT_POS (13U) +#define USB_EP2_DONE_INT_LEN (1U) +#define USB_EP2_DONE_INT_MSK (((1U << USB_EP2_DONE_INT_LEN) - 1) << USB_EP2_DONE_INT_POS) +#define USB_EP2_DONE_INT_UMSK (~(((1U << USB_EP2_DONE_INT_LEN) - 1) << USB_EP2_DONE_INT_POS)) +#define USB_EP3_CMD_INT USB_EP3_CMD_INT +#define USB_EP3_CMD_INT_POS (14U) +#define USB_EP3_CMD_INT_LEN (1U) +#define USB_EP3_CMD_INT_MSK (((1U << USB_EP3_CMD_INT_LEN) - 1) << USB_EP3_CMD_INT_POS) +#define USB_EP3_CMD_INT_UMSK (~(((1U << USB_EP3_CMD_INT_LEN) - 1) << USB_EP3_CMD_INT_POS)) +#define USB_EP3_DONE_INT USB_EP3_DONE_INT +#define USB_EP3_DONE_INT_POS (15U) +#define USB_EP3_DONE_INT_LEN (1U) +#define USB_EP3_DONE_INT_MSK (((1U << USB_EP3_DONE_INT_LEN) - 1) << USB_EP3_DONE_INT_POS) +#define USB_EP3_DONE_INT_UMSK (~(((1U << USB_EP3_DONE_INT_LEN) - 1) << USB_EP3_DONE_INT_POS)) +#define USB_EP4_CMD_INT USB_EP4_CMD_INT +#define USB_EP4_CMD_INT_POS (16U) +#define USB_EP4_CMD_INT_LEN (1U) +#define USB_EP4_CMD_INT_MSK (((1U << USB_EP4_CMD_INT_LEN) - 1) << USB_EP4_CMD_INT_POS) +#define USB_EP4_CMD_INT_UMSK (~(((1U << USB_EP4_CMD_INT_LEN) - 1) << USB_EP4_CMD_INT_POS)) +#define USB_EP4_DONE_INT USB_EP4_DONE_INT +#define USB_EP4_DONE_INT_POS (17U) +#define USB_EP4_DONE_INT_LEN (1U) +#define USB_EP4_DONE_INT_MSK (((1U << USB_EP4_DONE_INT_LEN) - 1) << USB_EP4_DONE_INT_POS) +#define USB_EP4_DONE_INT_UMSK (~(((1U << USB_EP4_DONE_INT_LEN) - 1) << USB_EP4_DONE_INT_POS)) +#define USB_EP5_CMD_INT USB_EP5_CMD_INT +#define USB_EP5_CMD_INT_POS (18U) +#define USB_EP5_CMD_INT_LEN (1U) +#define USB_EP5_CMD_INT_MSK (((1U << USB_EP5_CMD_INT_LEN) - 1) << USB_EP5_CMD_INT_POS) +#define USB_EP5_CMD_INT_UMSK (~(((1U << USB_EP5_CMD_INT_LEN) - 1) << USB_EP5_CMD_INT_POS)) +#define USB_EP5_DONE_INT USB_EP5_DONE_INT +#define USB_EP5_DONE_INT_POS (19U) +#define USB_EP5_DONE_INT_LEN (1U) +#define USB_EP5_DONE_INT_MSK (((1U << USB_EP5_DONE_INT_LEN) - 1) << USB_EP5_DONE_INT_POS) +#define USB_EP5_DONE_INT_UMSK (~(((1U << USB_EP5_DONE_INT_LEN) - 1) << USB_EP5_DONE_INT_POS)) +#define USB_EP6_CMD_INT USB_EP6_CMD_INT +#define USB_EP6_CMD_INT_POS (20U) +#define USB_EP6_CMD_INT_LEN (1U) +#define USB_EP6_CMD_INT_MSK (((1U << USB_EP6_CMD_INT_LEN) - 1) << USB_EP6_CMD_INT_POS) +#define USB_EP6_CMD_INT_UMSK (~(((1U << USB_EP6_CMD_INT_LEN) - 1) << USB_EP6_CMD_INT_POS)) +#define USB_EP6_DONE_INT USB_EP6_DONE_INT +#define USB_EP6_DONE_INT_POS (21U) +#define USB_EP6_DONE_INT_LEN (1U) +#define USB_EP6_DONE_INT_MSK (((1U << USB_EP6_DONE_INT_LEN) - 1) << USB_EP6_DONE_INT_POS) +#define USB_EP6_DONE_INT_UMSK (~(((1U << USB_EP6_DONE_INT_LEN) - 1) << USB_EP6_DONE_INT_POS)) +#define USB_EP7_CMD_INT USB_EP7_CMD_INT +#define USB_EP7_CMD_INT_POS (22U) +#define USB_EP7_CMD_INT_LEN (1U) +#define USB_EP7_CMD_INT_MSK (((1U << USB_EP7_CMD_INT_LEN) - 1) << USB_EP7_CMD_INT_POS) +#define USB_EP7_CMD_INT_UMSK (~(((1U << USB_EP7_CMD_INT_LEN) - 1) << USB_EP7_CMD_INT_POS)) +#define USB_EP7_DONE_INT USB_EP7_DONE_INT +#define USB_EP7_DONE_INT_POS (23U) +#define USB_EP7_DONE_INT_LEN (1U) +#define USB_EP7_DONE_INT_MSK (((1U << USB_EP7_DONE_INT_LEN) - 1) << USB_EP7_DONE_INT_POS) +#define USB_EP7_DONE_INT_UMSK (~(((1U << USB_EP7_DONE_INT_LEN) - 1) << USB_EP7_DONE_INT_POS)) +#define USB_REND_INT USB_REND_INT +#define USB_REND_INT_POS (27U) +#define USB_REND_INT_LEN (1U) +#define USB_REND_INT_MSK (((1U << USB_REND_INT_LEN) - 1) << USB_REND_INT_POS) +#define USB_REND_INT_UMSK (~(((1U << USB_REND_INT_LEN) - 1) << USB_REND_INT_POS)) +#define USB_LPM_WKUP_INT USB_LPM_WKUP_INT +#define USB_LPM_WKUP_INT_POS (28U) +#define USB_LPM_WKUP_INT_LEN (1U) +#define USB_LPM_WKUP_INT_MSK (((1U << USB_LPM_WKUP_INT_LEN) - 1) << USB_LPM_WKUP_INT_POS) +#define USB_LPM_WKUP_INT_UMSK (~(((1U << USB_LPM_WKUP_INT_LEN) - 1) << USB_LPM_WKUP_INT_POS)) +#define USB_LPM_PKT_INT USB_LPM_PKT_INT +#define USB_LPM_PKT_INT_POS (29U) +#define USB_LPM_PKT_INT_LEN (1U) +#define USB_LPM_PKT_INT_MSK (((1U << USB_LPM_PKT_INT_LEN) - 1) << USB_LPM_PKT_INT_POS) +#define USB_LPM_PKT_INT_UMSK (~(((1U << USB_LPM_PKT_INT_LEN) - 1) << USB_LPM_PKT_INT_POS)) +#define USB_SOF_3MS_INT USB_SOF_3MS_INT +#define USB_SOF_3MS_INT_POS (30U) +#define USB_SOF_3MS_INT_LEN (1U) +#define USB_SOF_3MS_INT_MSK (((1U << USB_SOF_3MS_INT_LEN) - 1) << USB_SOF_3MS_INT_POS) +#define USB_SOF_3MS_INT_UMSK (~(((1U << USB_SOF_3MS_INT_LEN) - 1) << USB_SOF_3MS_INT_POS)) +#define USB_ERR_INT USB_ERR_INT +#define USB_ERR_INT_POS (31U) +#define USB_ERR_INT_LEN (1U) +#define USB_ERR_INT_MSK (((1U << USB_ERR_INT_LEN) - 1) << USB_ERR_INT_POS) +#define USB_ERR_INT_UMSK (~(((1U << USB_ERR_INT_LEN) - 1) << USB_ERR_INT_POS)) + +/* 0x28 : USB interrupt mask */ +#define USB_INT_MASK_OFFSET (0x28) +#define USB_CR_SOF_MASK USB_CR_SOF_MASK +#define USB_CR_SOF_MASK_POS (0U) +#define USB_CR_SOF_MASK_LEN (1U) +#define USB_CR_SOF_MASK_MSK (((1U << USB_CR_SOF_MASK_LEN) - 1) << USB_CR_SOF_MASK_POS) +#define USB_CR_SOF_MASK_UMSK (~(((1U << USB_CR_SOF_MASK_LEN) - 1) << USB_CR_SOF_MASK_POS)) +#define USB_CR_USB_RESET_MASK USB_CR_USB_RESET_MASK +#define USB_CR_USB_RESET_MASK_POS (1U) +#define USB_CR_USB_RESET_MASK_LEN (1U) +#define USB_CR_USB_RESET_MASK_MSK (((1U << USB_CR_USB_RESET_MASK_LEN) - 1) << USB_CR_USB_RESET_MASK_POS) +#define USB_CR_USB_RESET_MASK_UMSK (~(((1U << USB_CR_USB_RESET_MASK_LEN) - 1) << USB_CR_USB_RESET_MASK_POS)) +#define USB_CR_VBUS_TGL_MASK USB_CR_VBUS_TGL_MASK +#define USB_CR_VBUS_TGL_MASK_POS (2U) +#define USB_CR_VBUS_TGL_MASK_LEN (1U) +#define USB_CR_VBUS_TGL_MASK_MSK (((1U << USB_CR_VBUS_TGL_MASK_LEN) - 1) << USB_CR_VBUS_TGL_MASK_POS) +#define USB_CR_VBUS_TGL_MASK_UMSK (~(((1U << USB_CR_VBUS_TGL_MASK_LEN) - 1) << USB_CR_VBUS_TGL_MASK_POS)) +#define USB_CR_GET_DCT_CMD_MASK USB_CR_GET_DCT_CMD_MASK +#define USB_CR_GET_DCT_CMD_MASK_POS (3U) +#define USB_CR_GET_DCT_CMD_MASK_LEN (1U) +#define USB_CR_GET_DCT_CMD_MASK_MSK (((1U << USB_CR_GET_DCT_CMD_MASK_LEN) - 1) << USB_CR_GET_DCT_CMD_MASK_POS) +#define USB_CR_GET_DCT_CMD_MASK_UMSK (~(((1U << USB_CR_GET_DCT_CMD_MASK_LEN) - 1) << USB_CR_GET_DCT_CMD_MASK_POS)) +#define USB_CR_EP0_SETUP_CMD_MASK USB_CR_EP0_SETUP_CMD_MASK +#define USB_CR_EP0_SETUP_CMD_MASK_POS (4U) +#define USB_CR_EP0_SETUP_CMD_MASK_LEN (1U) +#define USB_CR_EP0_SETUP_CMD_MASK_MSK (((1U << USB_CR_EP0_SETUP_CMD_MASK_LEN) - 1) << USB_CR_EP0_SETUP_CMD_MASK_POS) +#define USB_CR_EP0_SETUP_CMD_MASK_UMSK (~(((1U << USB_CR_EP0_SETUP_CMD_MASK_LEN) - 1) << USB_CR_EP0_SETUP_CMD_MASK_POS)) +#define USB_CR_EP0_SETUP_DONE_MASK USB_CR_EP0_SETUP_DONE_MASK +#define USB_CR_EP0_SETUP_DONE_MASK_POS (5U) +#define USB_CR_EP0_SETUP_DONE_MASK_LEN (1U) +#define USB_CR_EP0_SETUP_DONE_MASK_MSK (((1U << USB_CR_EP0_SETUP_DONE_MASK_LEN) - 1) << USB_CR_EP0_SETUP_DONE_MASK_POS) +#define USB_CR_EP0_SETUP_DONE_MASK_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_MASK_LEN) - 1) << USB_CR_EP0_SETUP_DONE_MASK_POS)) +#define USB_CR_EP0_IN_CMD_MASK USB_CR_EP0_IN_CMD_MASK +#define USB_CR_EP0_IN_CMD_MASK_POS (6U) +#define USB_CR_EP0_IN_CMD_MASK_LEN (1U) +#define USB_CR_EP0_IN_CMD_MASK_MSK (((1U << USB_CR_EP0_IN_CMD_MASK_LEN) - 1) << USB_CR_EP0_IN_CMD_MASK_POS) +#define USB_CR_EP0_IN_CMD_MASK_UMSK (~(((1U << USB_CR_EP0_IN_CMD_MASK_LEN) - 1) << USB_CR_EP0_IN_CMD_MASK_POS)) +#define USB_CR_EP0_IN_DONE_MASK USB_CR_EP0_IN_DONE_MASK +#define USB_CR_EP0_IN_DONE_MASK_POS (7U) +#define USB_CR_EP0_IN_DONE_MASK_LEN (1U) +#define USB_CR_EP0_IN_DONE_MASK_MSK (((1U << USB_CR_EP0_IN_DONE_MASK_LEN) - 1) << USB_CR_EP0_IN_DONE_MASK_POS) +#define USB_CR_EP0_IN_DONE_MASK_UMSK (~(((1U << USB_CR_EP0_IN_DONE_MASK_LEN) - 1) << USB_CR_EP0_IN_DONE_MASK_POS)) +#define USB_CR_EP0_OUT_CMD_MASK USB_CR_EP0_OUT_CMD_MASK +#define USB_CR_EP0_OUT_CMD_MASK_POS (8U) +#define USB_CR_EP0_OUT_CMD_MASK_LEN (1U) +#define USB_CR_EP0_OUT_CMD_MASK_MSK (((1U << USB_CR_EP0_OUT_CMD_MASK_LEN) - 1) << USB_CR_EP0_OUT_CMD_MASK_POS) +#define USB_CR_EP0_OUT_CMD_MASK_UMSK (~(((1U << USB_CR_EP0_OUT_CMD_MASK_LEN) - 1) << USB_CR_EP0_OUT_CMD_MASK_POS)) +#define USB_CR_EP0_OUT_DONE_MASK USB_CR_EP0_OUT_DONE_MASK +#define USB_CR_EP0_OUT_DONE_MASK_POS (9U) +#define USB_CR_EP0_OUT_DONE_MASK_LEN (1U) +#define USB_CR_EP0_OUT_DONE_MASK_MSK (((1U << USB_CR_EP0_OUT_DONE_MASK_LEN) - 1) << USB_CR_EP0_OUT_DONE_MASK_POS) +#define USB_CR_EP0_OUT_DONE_MASK_UMSK (~(((1U << USB_CR_EP0_OUT_DONE_MASK_LEN) - 1) << USB_CR_EP0_OUT_DONE_MASK_POS)) +#define USB_CR_EP1_CMD_MASK USB_CR_EP1_CMD_MASK +#define USB_CR_EP1_CMD_MASK_POS (10U) +#define USB_CR_EP1_CMD_MASK_LEN (1U) +#define USB_CR_EP1_CMD_MASK_MSK (((1U << USB_CR_EP1_CMD_MASK_LEN) - 1) << USB_CR_EP1_CMD_MASK_POS) +#define USB_CR_EP1_CMD_MASK_UMSK (~(((1U << USB_CR_EP1_CMD_MASK_LEN) - 1) << USB_CR_EP1_CMD_MASK_POS)) +#define USB_CR_EP1_DONE_MASK USB_CR_EP1_DONE_MASK +#define USB_CR_EP1_DONE_MASK_POS (11U) +#define USB_CR_EP1_DONE_MASK_LEN (1U) +#define USB_CR_EP1_DONE_MASK_MSK (((1U << USB_CR_EP1_DONE_MASK_LEN) - 1) << USB_CR_EP1_DONE_MASK_POS) +#define USB_CR_EP1_DONE_MASK_UMSK (~(((1U << USB_CR_EP1_DONE_MASK_LEN) - 1) << USB_CR_EP1_DONE_MASK_POS)) +#define USB_CR_EP2_CMD_MASK USB_CR_EP2_CMD_MASK +#define USB_CR_EP2_CMD_MASK_POS (12U) +#define USB_CR_EP2_CMD_MASK_LEN (1U) +#define USB_CR_EP2_CMD_MASK_MSK (((1U << USB_CR_EP2_CMD_MASK_LEN) - 1) << USB_CR_EP2_CMD_MASK_POS) +#define USB_CR_EP2_CMD_MASK_UMSK (~(((1U << USB_CR_EP2_CMD_MASK_LEN) - 1) << USB_CR_EP2_CMD_MASK_POS)) +#define USB_CR_EP2_DONE_MASK USB_CR_EP2_DONE_MASK +#define USB_CR_EP2_DONE_MASK_POS (13U) +#define USB_CR_EP2_DONE_MASK_LEN (1U) +#define USB_CR_EP2_DONE_MASK_MSK (((1U << USB_CR_EP2_DONE_MASK_LEN) - 1) << USB_CR_EP2_DONE_MASK_POS) +#define USB_CR_EP2_DONE_MASK_UMSK (~(((1U << USB_CR_EP2_DONE_MASK_LEN) - 1) << USB_CR_EP2_DONE_MASK_POS)) +#define USB_CR_EP3_CMD_MASK USB_CR_EP3_CMD_MASK +#define USB_CR_EP3_CMD_MASK_POS (14U) +#define USB_CR_EP3_CMD_MASK_LEN (1U) +#define USB_CR_EP3_CMD_MASK_MSK (((1U << USB_CR_EP3_CMD_MASK_LEN) - 1) << USB_CR_EP3_CMD_MASK_POS) +#define USB_CR_EP3_CMD_MASK_UMSK (~(((1U << USB_CR_EP3_CMD_MASK_LEN) - 1) << USB_CR_EP3_CMD_MASK_POS)) +#define USB_CR_EP3_DONE_MASK USB_CR_EP3_DONE_MASK +#define USB_CR_EP3_DONE_MASK_POS (15U) +#define USB_CR_EP3_DONE_MASK_LEN (1U) +#define USB_CR_EP3_DONE_MASK_MSK (((1U << USB_CR_EP3_DONE_MASK_LEN) - 1) << USB_CR_EP3_DONE_MASK_POS) +#define USB_CR_EP3_DONE_MASK_UMSK (~(((1U << USB_CR_EP3_DONE_MASK_LEN) - 1) << USB_CR_EP3_DONE_MASK_POS)) +#define USB_CR_EP4_CMD_MASK USB_CR_EP4_CMD_MASK +#define USB_CR_EP4_CMD_MASK_POS (16U) +#define USB_CR_EP4_CMD_MASK_LEN (1U) +#define USB_CR_EP4_CMD_MASK_MSK (((1U << USB_CR_EP4_CMD_MASK_LEN) - 1) << USB_CR_EP4_CMD_MASK_POS) +#define USB_CR_EP4_CMD_MASK_UMSK (~(((1U << USB_CR_EP4_CMD_MASK_LEN) - 1) << USB_CR_EP4_CMD_MASK_POS)) +#define USB_CR_EP4_DONE_MASK USB_CR_EP4_DONE_MASK +#define USB_CR_EP4_DONE_MASK_POS (17U) +#define USB_CR_EP4_DONE_MASK_LEN (1U) +#define USB_CR_EP4_DONE_MASK_MSK (((1U << USB_CR_EP4_DONE_MASK_LEN) - 1) << USB_CR_EP4_DONE_MASK_POS) +#define USB_CR_EP4_DONE_MASK_UMSK (~(((1U << USB_CR_EP4_DONE_MASK_LEN) - 1) << USB_CR_EP4_DONE_MASK_POS)) +#define USB_CR_EP5_CMD_MASK USB_CR_EP5_CMD_MASK +#define USB_CR_EP5_CMD_MASK_POS (18U) +#define USB_CR_EP5_CMD_MASK_LEN (1U) +#define USB_CR_EP5_CMD_MASK_MSK (((1U << USB_CR_EP5_CMD_MASK_LEN) - 1) << USB_CR_EP5_CMD_MASK_POS) +#define USB_CR_EP5_CMD_MASK_UMSK (~(((1U << USB_CR_EP5_CMD_MASK_LEN) - 1) << USB_CR_EP5_CMD_MASK_POS)) +#define USB_CR_EP5_DONE_MASK USB_CR_EP5_DONE_MASK +#define USB_CR_EP5_DONE_MASK_POS (19U) +#define USB_CR_EP5_DONE_MASK_LEN (1U) +#define USB_CR_EP5_DONE_MASK_MSK (((1U << USB_CR_EP5_DONE_MASK_LEN) - 1) << USB_CR_EP5_DONE_MASK_POS) +#define USB_CR_EP5_DONE_MASK_UMSK (~(((1U << USB_CR_EP5_DONE_MASK_LEN) - 1) << USB_CR_EP5_DONE_MASK_POS)) +#define USB_CR_EP6_CMD_MASK USB_CR_EP6_CMD_MASK +#define USB_CR_EP6_CMD_MASK_POS (20U) +#define USB_CR_EP6_CMD_MASK_LEN (1U) +#define USB_CR_EP6_CMD_MASK_MSK (((1U << USB_CR_EP6_CMD_MASK_LEN) - 1) << USB_CR_EP6_CMD_MASK_POS) +#define USB_CR_EP6_CMD_MASK_UMSK (~(((1U << USB_CR_EP6_CMD_MASK_LEN) - 1) << USB_CR_EP6_CMD_MASK_POS)) +#define USB_CR_EP6_DONE_MASK USB_CR_EP6_DONE_MASK +#define USB_CR_EP6_DONE_MASK_POS (21U) +#define USB_CR_EP6_DONE_MASK_LEN (1U) +#define USB_CR_EP6_DONE_MASK_MSK (((1U << USB_CR_EP6_DONE_MASK_LEN) - 1) << USB_CR_EP6_DONE_MASK_POS) +#define USB_CR_EP6_DONE_MASK_UMSK (~(((1U << USB_CR_EP6_DONE_MASK_LEN) - 1) << USB_CR_EP6_DONE_MASK_POS)) +#define USB_CR_EP7_CMD_MASK USB_CR_EP7_CMD_MASK +#define USB_CR_EP7_CMD_MASK_POS (22U) +#define USB_CR_EP7_CMD_MASK_LEN (1U) +#define USB_CR_EP7_CMD_MASK_MSK (((1U << USB_CR_EP7_CMD_MASK_LEN) - 1) << USB_CR_EP7_CMD_MASK_POS) +#define USB_CR_EP7_CMD_MASK_UMSK (~(((1U << USB_CR_EP7_CMD_MASK_LEN) - 1) << USB_CR_EP7_CMD_MASK_POS)) +#define USB_CR_EP7_DONE_MASK USB_CR_EP7_DONE_MASK +#define USB_CR_EP7_DONE_MASK_POS (23U) +#define USB_CR_EP7_DONE_MASK_LEN (1U) +#define USB_CR_EP7_DONE_MASK_MSK (((1U << USB_CR_EP7_DONE_MASK_LEN) - 1) << USB_CR_EP7_DONE_MASK_POS) +#define USB_CR_EP7_DONE_MASK_UMSK (~(((1U << USB_CR_EP7_DONE_MASK_LEN) - 1) << USB_CR_EP7_DONE_MASK_POS)) +#define USB_CR_USB_REND_MASK USB_CR_USB_REND_MASK +#define USB_CR_USB_REND_MASK_POS (27U) +#define USB_CR_USB_REND_MASK_LEN (1U) +#define USB_CR_USB_REND_MASK_MSK (((1U << USB_CR_USB_REND_MASK_LEN) - 1) << USB_CR_USB_REND_MASK_POS) +#define USB_CR_USB_REND_MASK_UMSK (~(((1U << USB_CR_USB_REND_MASK_LEN) - 1) << USB_CR_USB_REND_MASK_POS)) +#define USB_CR_LPM_WKUP_MASK USB_CR_LPM_WKUP_MASK +#define USB_CR_LPM_WKUP_MASK_POS (28U) +#define USB_CR_LPM_WKUP_MASK_LEN (1U) +#define USB_CR_LPM_WKUP_MASK_MSK (((1U << USB_CR_LPM_WKUP_MASK_LEN) - 1) << USB_CR_LPM_WKUP_MASK_POS) +#define USB_CR_LPM_WKUP_MASK_UMSK (~(((1U << USB_CR_LPM_WKUP_MASK_LEN) - 1) << USB_CR_LPM_WKUP_MASK_POS)) +#define USB_CR_LPM_PKT_MASK USB_CR_LPM_PKT_MASK +#define USB_CR_LPM_PKT_MASK_POS (29U) +#define USB_CR_LPM_PKT_MASK_LEN (1U) +#define USB_CR_LPM_PKT_MASK_MSK (((1U << USB_CR_LPM_PKT_MASK_LEN) - 1) << USB_CR_LPM_PKT_MASK_POS) +#define USB_CR_LPM_PKT_MASK_UMSK (~(((1U << USB_CR_LPM_PKT_MASK_LEN) - 1) << USB_CR_LPM_PKT_MASK_POS)) +#define USB_CR_SOF_3MS_MASK USB_CR_SOF_3MS_MASK +#define USB_CR_SOF_3MS_MASK_POS (30U) +#define USB_CR_SOF_3MS_MASK_LEN (1U) +#define USB_CR_SOF_3MS_MASK_MSK (((1U << USB_CR_SOF_3MS_MASK_LEN) - 1) << USB_CR_SOF_3MS_MASK_POS) +#define USB_CR_SOF_3MS_MASK_UMSK (~(((1U << USB_CR_SOF_3MS_MASK_LEN) - 1) << USB_CR_SOF_3MS_MASK_POS)) +#define USB_CR_USB_ERR_MASK USB_CR_USB_ERR_MASK +#define USB_CR_USB_ERR_MASK_POS (31U) +#define USB_CR_USB_ERR_MASK_LEN (1U) +#define USB_CR_USB_ERR_MASK_MSK (((1U << USB_CR_USB_ERR_MASK_LEN) - 1) << USB_CR_USB_ERR_MASK_POS) +#define USB_CR_USB_ERR_MASK_UMSK (~(((1U << USB_CR_USB_ERR_MASK_LEN) - 1) << USB_CR_USB_ERR_MASK_POS)) + +/* 0x2C : USB interrupt clear */ +#define USB_INT_CLEAR_OFFSET (0x2C) +#define USB_CR_SOF_CLR USB_CR_SOF_CLR +#define USB_CR_SOF_CLR_POS (0U) +#define USB_CR_SOF_CLR_LEN (1U) +#define USB_CR_SOF_CLR_MSK (((1U << USB_CR_SOF_CLR_LEN) - 1) << USB_CR_SOF_CLR_POS) +#define USB_CR_SOF_CLR_UMSK (~(((1U << USB_CR_SOF_CLR_LEN) - 1) << USB_CR_SOF_CLR_POS)) +#define USB_CR_USB_RESET_CLR USB_CR_USB_RESET_CLR +#define USB_CR_USB_RESET_CLR_POS (1U) +#define USB_CR_USB_RESET_CLR_LEN (1U) +#define USB_CR_USB_RESET_CLR_MSK (((1U << USB_CR_USB_RESET_CLR_LEN) - 1) << USB_CR_USB_RESET_CLR_POS) +#define USB_CR_USB_RESET_CLR_UMSK (~(((1U << USB_CR_USB_RESET_CLR_LEN) - 1) << USB_CR_USB_RESET_CLR_POS)) +#define USB_CR_VBUS_TGL_CLR USB_CR_VBUS_TGL_CLR +#define USB_CR_VBUS_TGL_CLR_POS (2U) +#define USB_CR_VBUS_TGL_CLR_LEN (1U) +#define USB_CR_VBUS_TGL_CLR_MSK (((1U << USB_CR_VBUS_TGL_CLR_LEN) - 1) << USB_CR_VBUS_TGL_CLR_POS) +#define USB_CR_VBUS_TGL_CLR_UMSK (~(((1U << USB_CR_VBUS_TGL_CLR_LEN) - 1) << USB_CR_VBUS_TGL_CLR_POS)) +#define USB_CR_GET_DCT_CMD_CLR USB_CR_GET_DCT_CMD_CLR +#define USB_CR_GET_DCT_CMD_CLR_POS (3U) +#define USB_CR_GET_DCT_CMD_CLR_LEN (1U) +#define USB_CR_GET_DCT_CMD_CLR_MSK (((1U << USB_CR_GET_DCT_CMD_CLR_LEN) - 1) << USB_CR_GET_DCT_CMD_CLR_POS) +#define USB_CR_GET_DCT_CMD_CLR_UMSK (~(((1U << USB_CR_GET_DCT_CMD_CLR_LEN) - 1) << USB_CR_GET_DCT_CMD_CLR_POS)) +#define USB_CR_EP0_SETUP_CMD_CLR USB_CR_EP0_SETUP_CMD_CLR +#define USB_CR_EP0_SETUP_CMD_CLR_POS (4U) +#define USB_CR_EP0_SETUP_CMD_CLR_LEN (1U) +#define USB_CR_EP0_SETUP_CMD_CLR_MSK (((1U << USB_CR_EP0_SETUP_CMD_CLR_LEN) - 1) << USB_CR_EP0_SETUP_CMD_CLR_POS) +#define USB_CR_EP0_SETUP_CMD_CLR_UMSK (~(((1U << USB_CR_EP0_SETUP_CMD_CLR_LEN) - 1) << USB_CR_EP0_SETUP_CMD_CLR_POS)) +#define USB_CR_EP0_SETUP_DONE_CLR USB_CR_EP0_SETUP_DONE_CLR +#define USB_CR_EP0_SETUP_DONE_CLR_POS (5U) +#define USB_CR_EP0_SETUP_DONE_CLR_LEN (1U) +#define USB_CR_EP0_SETUP_DONE_CLR_MSK (((1U << USB_CR_EP0_SETUP_DONE_CLR_LEN) - 1) << USB_CR_EP0_SETUP_DONE_CLR_POS) +#define USB_CR_EP0_SETUP_DONE_CLR_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_CLR_LEN) - 1) << USB_CR_EP0_SETUP_DONE_CLR_POS)) +#define USB_CR_EP0_IN_CMD_CLR USB_CR_EP0_IN_CMD_CLR +#define USB_CR_EP0_IN_CMD_CLR_POS (6U) +#define USB_CR_EP0_IN_CMD_CLR_LEN (1U) +#define USB_CR_EP0_IN_CMD_CLR_MSK (((1U << USB_CR_EP0_IN_CMD_CLR_LEN) - 1) << USB_CR_EP0_IN_CMD_CLR_POS) +#define USB_CR_EP0_IN_CMD_CLR_UMSK (~(((1U << USB_CR_EP0_IN_CMD_CLR_LEN) - 1) << USB_CR_EP0_IN_CMD_CLR_POS)) +#define USB_CR_EP0_IN_DONE_CLR USB_CR_EP0_IN_DONE_CLR +#define USB_CR_EP0_IN_DONE_CLR_POS (7U) +#define USB_CR_EP0_IN_DONE_CLR_LEN (1U) +#define USB_CR_EP0_IN_DONE_CLR_MSK (((1U << USB_CR_EP0_IN_DONE_CLR_LEN) - 1) << USB_CR_EP0_IN_DONE_CLR_POS) +#define USB_CR_EP0_IN_DONE_CLR_UMSK (~(((1U << USB_CR_EP0_IN_DONE_CLR_LEN) - 1) << USB_CR_EP0_IN_DONE_CLR_POS)) +#define USB_CR_EP0_OUT_CMD_CLR USB_CR_EP0_OUT_CMD_CLR +#define USB_CR_EP0_OUT_CMD_CLR_POS (8U) +#define USB_CR_EP0_OUT_CMD_CLR_LEN (1U) +#define USB_CR_EP0_OUT_CMD_CLR_MSK (((1U << USB_CR_EP0_OUT_CMD_CLR_LEN) - 1) << USB_CR_EP0_OUT_CMD_CLR_POS) +#define USB_CR_EP0_OUT_CMD_CLR_UMSK (~(((1U << USB_CR_EP0_OUT_CMD_CLR_LEN) - 1) << USB_CR_EP0_OUT_CMD_CLR_POS)) +#define USB_CR_EP0_OUT_DONE_CLR USB_CR_EP0_OUT_DONE_CLR +#define USB_CR_EP0_OUT_DONE_CLR_POS (9U) +#define USB_CR_EP0_OUT_DONE_CLR_LEN (1U) +#define USB_CR_EP0_OUT_DONE_CLR_MSK (((1U << USB_CR_EP0_OUT_DONE_CLR_LEN) - 1) << USB_CR_EP0_OUT_DONE_CLR_POS) +#define USB_CR_EP0_OUT_DONE_CLR_UMSK (~(((1U << USB_CR_EP0_OUT_DONE_CLR_LEN) - 1) << USB_CR_EP0_OUT_DONE_CLR_POS)) +#define USB_CR_EP1_CMD_CLR USB_CR_EP1_CMD_CLR +#define USB_CR_EP1_CMD_CLR_POS (10U) +#define USB_CR_EP1_CMD_CLR_LEN (1U) +#define USB_CR_EP1_CMD_CLR_MSK (((1U << USB_CR_EP1_CMD_CLR_LEN) - 1) << USB_CR_EP1_CMD_CLR_POS) +#define USB_CR_EP1_CMD_CLR_UMSK (~(((1U << USB_CR_EP1_CMD_CLR_LEN) - 1) << USB_CR_EP1_CMD_CLR_POS)) +#define USB_CR_EP1_DONE_CLR USB_CR_EP1_DONE_CLR +#define USB_CR_EP1_DONE_CLR_POS (11U) +#define USB_CR_EP1_DONE_CLR_LEN (1U) +#define USB_CR_EP1_DONE_CLR_MSK (((1U << USB_CR_EP1_DONE_CLR_LEN) - 1) << USB_CR_EP1_DONE_CLR_POS) +#define USB_CR_EP1_DONE_CLR_UMSK (~(((1U << USB_CR_EP1_DONE_CLR_LEN) - 1) << USB_CR_EP1_DONE_CLR_POS)) +#define USB_CR_EP2_CMD_CLR USB_CR_EP2_CMD_CLR +#define USB_CR_EP2_CMD_CLR_POS (12U) +#define USB_CR_EP2_CMD_CLR_LEN (1U) +#define USB_CR_EP2_CMD_CLR_MSK (((1U << USB_CR_EP2_CMD_CLR_LEN) - 1) << USB_CR_EP2_CMD_CLR_POS) +#define USB_CR_EP2_CMD_CLR_UMSK (~(((1U << USB_CR_EP2_CMD_CLR_LEN) - 1) << USB_CR_EP2_CMD_CLR_POS)) +#define USB_CR_EP2_DONE_CLR USB_CR_EP2_DONE_CLR +#define USB_CR_EP2_DONE_CLR_POS (13U) +#define USB_CR_EP2_DONE_CLR_LEN (1U) +#define USB_CR_EP2_DONE_CLR_MSK (((1U << USB_CR_EP2_DONE_CLR_LEN) - 1) << USB_CR_EP2_DONE_CLR_POS) +#define USB_CR_EP2_DONE_CLR_UMSK (~(((1U << USB_CR_EP2_DONE_CLR_LEN) - 1) << USB_CR_EP2_DONE_CLR_POS)) +#define USB_CR_EP3_CMD_CLR USB_CR_EP3_CMD_CLR +#define USB_CR_EP3_CMD_CLR_POS (14U) +#define USB_CR_EP3_CMD_CLR_LEN (1U) +#define USB_CR_EP3_CMD_CLR_MSK (((1U << USB_CR_EP3_CMD_CLR_LEN) - 1) << USB_CR_EP3_CMD_CLR_POS) +#define USB_CR_EP3_CMD_CLR_UMSK (~(((1U << USB_CR_EP3_CMD_CLR_LEN) - 1) << USB_CR_EP3_CMD_CLR_POS)) +#define USB_CR_EP3_DONE_CLR USB_CR_EP3_DONE_CLR +#define USB_CR_EP3_DONE_CLR_POS (15U) +#define USB_CR_EP3_DONE_CLR_LEN (1U) +#define USB_CR_EP3_DONE_CLR_MSK (((1U << USB_CR_EP3_DONE_CLR_LEN) - 1) << USB_CR_EP3_DONE_CLR_POS) +#define USB_CR_EP3_DONE_CLR_UMSK (~(((1U << USB_CR_EP3_DONE_CLR_LEN) - 1) << USB_CR_EP3_DONE_CLR_POS)) +#define USB_CR_EP4_CMD_CLR USB_CR_EP4_CMD_CLR +#define USB_CR_EP4_CMD_CLR_POS (16U) +#define USB_CR_EP4_CMD_CLR_LEN (1U) +#define USB_CR_EP4_CMD_CLR_MSK (((1U << USB_CR_EP4_CMD_CLR_LEN) - 1) << USB_CR_EP4_CMD_CLR_POS) +#define USB_CR_EP4_CMD_CLR_UMSK (~(((1U << USB_CR_EP4_CMD_CLR_LEN) - 1) << USB_CR_EP4_CMD_CLR_POS)) +#define USB_CR_EP4_DONE_CLR USB_CR_EP4_DONE_CLR +#define USB_CR_EP4_DONE_CLR_POS (17U) +#define USB_CR_EP4_DONE_CLR_LEN (1U) +#define USB_CR_EP4_DONE_CLR_MSK (((1U << USB_CR_EP4_DONE_CLR_LEN) - 1) << USB_CR_EP4_DONE_CLR_POS) +#define USB_CR_EP4_DONE_CLR_UMSK (~(((1U << USB_CR_EP4_DONE_CLR_LEN) - 1) << USB_CR_EP4_DONE_CLR_POS)) +#define USB_CR_EP5_CMD_CLR USB_CR_EP5_CMD_CLR +#define USB_CR_EP5_CMD_CLR_POS (18U) +#define USB_CR_EP5_CMD_CLR_LEN (1U) +#define USB_CR_EP5_CMD_CLR_MSK (((1U << USB_CR_EP5_CMD_CLR_LEN) - 1) << USB_CR_EP5_CMD_CLR_POS) +#define USB_CR_EP5_CMD_CLR_UMSK (~(((1U << USB_CR_EP5_CMD_CLR_LEN) - 1) << USB_CR_EP5_CMD_CLR_POS)) +#define USB_CR_EP5_DONE_CLR USB_CR_EP5_DONE_CLR +#define USB_CR_EP5_DONE_CLR_POS (19U) +#define USB_CR_EP5_DONE_CLR_LEN (1U) +#define USB_CR_EP5_DONE_CLR_MSK (((1U << USB_CR_EP5_DONE_CLR_LEN) - 1) << USB_CR_EP5_DONE_CLR_POS) +#define USB_CR_EP5_DONE_CLR_UMSK (~(((1U << USB_CR_EP5_DONE_CLR_LEN) - 1) << USB_CR_EP5_DONE_CLR_POS)) +#define USB_CR_EP6_CMD_CLR USB_CR_EP6_CMD_CLR +#define USB_CR_EP6_CMD_CLR_POS (20U) +#define USB_CR_EP6_CMD_CLR_LEN (1U) +#define USB_CR_EP6_CMD_CLR_MSK (((1U << USB_CR_EP6_CMD_CLR_LEN) - 1) << USB_CR_EP6_CMD_CLR_POS) +#define USB_CR_EP6_CMD_CLR_UMSK (~(((1U << USB_CR_EP6_CMD_CLR_LEN) - 1) << USB_CR_EP6_CMD_CLR_POS)) +#define USB_CR_EP6_DONE_CLR USB_CR_EP6_DONE_CLR +#define USB_CR_EP6_DONE_CLR_POS (21U) +#define USB_CR_EP6_DONE_CLR_LEN (1U) +#define USB_CR_EP6_DONE_CLR_MSK (((1U << USB_CR_EP6_DONE_CLR_LEN) - 1) << USB_CR_EP6_DONE_CLR_POS) +#define USB_CR_EP6_DONE_CLR_UMSK (~(((1U << USB_CR_EP6_DONE_CLR_LEN) - 1) << USB_CR_EP6_DONE_CLR_POS)) +#define USB_CR_EP7_CMD_CLR USB_CR_EP7_CMD_CLR +#define USB_CR_EP7_CMD_CLR_POS (22U) +#define USB_CR_EP7_CMD_CLR_LEN (1U) +#define USB_CR_EP7_CMD_CLR_MSK (((1U << USB_CR_EP7_CMD_CLR_LEN) - 1) << USB_CR_EP7_CMD_CLR_POS) +#define USB_CR_EP7_CMD_CLR_UMSK (~(((1U << USB_CR_EP7_CMD_CLR_LEN) - 1) << USB_CR_EP7_CMD_CLR_POS)) +#define USB_CR_EP7_DONE_CLR USB_CR_EP7_DONE_CLR +#define USB_CR_EP7_DONE_CLR_POS (23U) +#define USB_CR_EP7_DONE_CLR_LEN (1U) +#define USB_CR_EP7_DONE_CLR_MSK (((1U << USB_CR_EP7_DONE_CLR_LEN) - 1) << USB_CR_EP7_DONE_CLR_POS) +#define USB_CR_EP7_DONE_CLR_UMSK (~(((1U << USB_CR_EP7_DONE_CLR_LEN) - 1) << USB_CR_EP7_DONE_CLR_POS)) +#define USB_CR_USB_REND_CLR USB_CR_USB_REND_CLR +#define USB_CR_USB_REND_CLR_POS (27U) +#define USB_CR_USB_REND_CLR_LEN (1U) +#define USB_CR_USB_REND_CLR_MSK (((1U << USB_CR_USB_REND_CLR_LEN) - 1) << USB_CR_USB_REND_CLR_POS) +#define USB_CR_USB_REND_CLR_UMSK (~(((1U << USB_CR_USB_REND_CLR_LEN) - 1) << USB_CR_USB_REND_CLR_POS)) +#define USB_CR_LPM_WKUP_CLR USB_CR_LPM_WKUP_CLR +#define USB_CR_LPM_WKUP_CLR_POS (28U) +#define USB_CR_LPM_WKUP_CLR_LEN (1U) +#define USB_CR_LPM_WKUP_CLR_MSK (((1U << USB_CR_LPM_WKUP_CLR_LEN) - 1) << USB_CR_LPM_WKUP_CLR_POS) +#define USB_CR_LPM_WKUP_CLR_UMSK (~(((1U << USB_CR_LPM_WKUP_CLR_LEN) - 1) << USB_CR_LPM_WKUP_CLR_POS)) +#define USB_CR_LPM_PKT_CLR USB_CR_LPM_PKT_CLR +#define USB_CR_LPM_PKT_CLR_POS (29U) +#define USB_CR_LPM_PKT_CLR_LEN (1U) +#define USB_CR_LPM_PKT_CLR_MSK (((1U << USB_CR_LPM_PKT_CLR_LEN) - 1) << USB_CR_LPM_PKT_CLR_POS) +#define USB_CR_LPM_PKT_CLR_UMSK (~(((1U << USB_CR_LPM_PKT_CLR_LEN) - 1) << USB_CR_LPM_PKT_CLR_POS)) +#define USB_CR_SOF_3MS_CLR USB_CR_SOF_3MS_CLR +#define USB_CR_SOF_3MS_CLR_POS (30U) +#define USB_CR_SOF_3MS_CLR_LEN (1U) +#define USB_CR_SOF_3MS_CLR_MSK (((1U << USB_CR_SOF_3MS_CLR_LEN) - 1) << USB_CR_SOF_3MS_CLR_POS) +#define USB_CR_SOF_3MS_CLR_UMSK (~(((1U << USB_CR_SOF_3MS_CLR_LEN) - 1) << USB_CR_SOF_3MS_CLR_POS)) +#define USB_CR_USB_ERR_CLR USB_CR_USB_ERR_CLR +#define USB_CR_USB_ERR_CLR_POS (31U) +#define USB_CR_USB_ERR_CLR_LEN (1U) +#define USB_CR_USB_ERR_CLR_MSK (((1U << USB_CR_USB_ERR_CLR_LEN) - 1) << USB_CR_USB_ERR_CLR_POS) +#define USB_CR_USB_ERR_CLR_UMSK (~(((1U << USB_CR_USB_ERR_CLR_LEN) - 1) << USB_CR_USB_ERR_CLR_POS)) + +/* 0x40 : ep1_config */ +#define USB_EP1_CONFIG_OFFSET (0x40) +#define USB_CR_EP1_SIZE USB_CR_EP1_SIZE +#define USB_CR_EP1_SIZE_POS (0U) +#define USB_CR_EP1_SIZE_LEN (11U) +#define USB_CR_EP1_SIZE_MSK (((1U << USB_CR_EP1_SIZE_LEN) - 1) << USB_CR_EP1_SIZE_POS) +#define USB_CR_EP1_SIZE_UMSK (~(((1U << USB_CR_EP1_SIZE_LEN) - 1) << USB_CR_EP1_SIZE_POS)) +#define USB_CR_EP1_DIR USB_CR_EP1_DIR +#define USB_CR_EP1_DIR_POS (11U) +#define USB_CR_EP1_DIR_LEN (2U) +#define USB_CR_EP1_DIR_MSK (((1U << USB_CR_EP1_DIR_LEN) - 1) << USB_CR_EP1_DIR_POS) +#define USB_CR_EP1_DIR_UMSK (~(((1U << USB_CR_EP1_DIR_LEN) - 1) << USB_CR_EP1_DIR_POS)) +#define USB_CR_EP1_TYPE USB_CR_EP1_TYPE +#define USB_CR_EP1_TYPE_POS (13U) +#define USB_CR_EP1_TYPE_LEN (3U) +#define USB_CR_EP1_TYPE_MSK (((1U << USB_CR_EP1_TYPE_LEN) - 1) << USB_CR_EP1_TYPE_POS) +#define USB_CR_EP1_TYPE_UMSK (~(((1U << USB_CR_EP1_TYPE_LEN) - 1) << USB_CR_EP1_TYPE_POS)) +#define USB_CR_EP1_STALL USB_CR_EP1_STALL +#define USB_CR_EP1_STALL_POS (16U) +#define USB_CR_EP1_STALL_LEN (1U) +#define USB_CR_EP1_STALL_MSK (((1U << USB_CR_EP1_STALL_LEN) - 1) << USB_CR_EP1_STALL_POS) +#define USB_CR_EP1_STALL_UMSK (~(((1U << USB_CR_EP1_STALL_LEN) - 1) << USB_CR_EP1_STALL_POS)) +#define USB_CR_EP1_NACK USB_CR_EP1_NACK +#define USB_CR_EP1_NACK_POS (17U) +#define USB_CR_EP1_NACK_LEN (1U) +#define USB_CR_EP1_NACK_MSK (((1U << USB_CR_EP1_NACK_LEN) - 1) << USB_CR_EP1_NACK_POS) +#define USB_CR_EP1_NACK_UMSK (~(((1U << USB_CR_EP1_NACK_LEN) - 1) << USB_CR_EP1_NACK_POS)) +#define USB_CR_EP1_RDY USB_CR_EP1_RDY +#define USB_CR_EP1_RDY_POS (18U) +#define USB_CR_EP1_RDY_LEN (1U) +#define USB_CR_EP1_RDY_MSK (((1U << USB_CR_EP1_RDY_LEN) - 1) << USB_CR_EP1_RDY_POS) +#define USB_CR_EP1_RDY_UMSK (~(((1U << USB_CR_EP1_RDY_LEN) - 1) << USB_CR_EP1_RDY_POS)) +#define USB_STS_EP1_RDY USB_STS_EP1_RDY +#define USB_STS_EP1_RDY_POS (19U) +#define USB_STS_EP1_RDY_LEN (1U) +#define USB_STS_EP1_RDY_MSK (((1U << USB_STS_EP1_RDY_LEN) - 1) << USB_STS_EP1_RDY_POS) +#define USB_STS_EP1_RDY_UMSK (~(((1U << USB_STS_EP1_RDY_LEN) - 1) << USB_STS_EP1_RDY_POS)) + +/* 0x44 : ep2_config */ +#define USB_EP2_CONFIG_OFFSET (0x44) +#define USB_CR_EP2_SIZE USB_CR_EP2_SIZE +#define USB_CR_EP2_SIZE_POS (0U) +#define USB_CR_EP2_SIZE_LEN (11U) +#define USB_CR_EP2_SIZE_MSK (((1U << USB_CR_EP2_SIZE_LEN) - 1) << USB_CR_EP2_SIZE_POS) +#define USB_CR_EP2_SIZE_UMSK (~(((1U << USB_CR_EP2_SIZE_LEN) - 1) << USB_CR_EP2_SIZE_POS)) +#define USB_CR_EP2_DIR USB_CR_EP2_DIR +#define USB_CR_EP2_DIR_POS (11U) +#define USB_CR_EP2_DIR_LEN (2U) +#define USB_CR_EP2_DIR_MSK (((1U << USB_CR_EP2_DIR_LEN) - 1) << USB_CR_EP2_DIR_POS) +#define USB_CR_EP2_DIR_UMSK (~(((1U << USB_CR_EP2_DIR_LEN) - 1) << USB_CR_EP2_DIR_POS)) +#define USB_CR_EP2_TYPE USB_CR_EP2_TYPE +#define USB_CR_EP2_TYPE_POS (13U) +#define USB_CR_EP2_TYPE_LEN (3U) +#define USB_CR_EP2_TYPE_MSK (((1U << USB_CR_EP2_TYPE_LEN) - 1) << USB_CR_EP2_TYPE_POS) +#define USB_CR_EP2_TYPE_UMSK (~(((1U << USB_CR_EP2_TYPE_LEN) - 1) << USB_CR_EP2_TYPE_POS)) +#define USB_CR_EP2_STALL USB_CR_EP2_STALL +#define USB_CR_EP2_STALL_POS (16U) +#define USB_CR_EP2_STALL_LEN (1U) +#define USB_CR_EP2_STALL_MSK (((1U << USB_CR_EP2_STALL_LEN) - 1) << USB_CR_EP2_STALL_POS) +#define USB_CR_EP2_STALL_UMSK (~(((1U << USB_CR_EP2_STALL_LEN) - 1) << USB_CR_EP2_STALL_POS)) +#define USB_CR_EP2_NACK USB_CR_EP2_NACK +#define USB_CR_EP2_NACK_POS (17U) +#define USB_CR_EP2_NACK_LEN (1U) +#define USB_CR_EP2_NACK_MSK (((1U << USB_CR_EP2_NACK_LEN) - 1) << USB_CR_EP2_NACK_POS) +#define USB_CR_EP2_NACK_UMSK (~(((1U << USB_CR_EP2_NACK_LEN) - 1) << USB_CR_EP2_NACK_POS)) +#define USB_CR_EP2_RDY USB_CR_EP2_RDY +#define USB_CR_EP2_RDY_POS (18U) +#define USB_CR_EP2_RDY_LEN (1U) +#define USB_CR_EP2_RDY_MSK (((1U << USB_CR_EP2_RDY_LEN) - 1) << USB_CR_EP2_RDY_POS) +#define USB_CR_EP2_RDY_UMSK (~(((1U << USB_CR_EP2_RDY_LEN) - 1) << USB_CR_EP2_RDY_POS)) +#define USB_STS_EP2_RDY USB_STS_EP2_RDY +#define USB_STS_EP2_RDY_POS (19U) +#define USB_STS_EP2_RDY_LEN (1U) +#define USB_STS_EP2_RDY_MSK (((1U << USB_STS_EP2_RDY_LEN) - 1) << USB_STS_EP2_RDY_POS) +#define USB_STS_EP2_RDY_UMSK (~(((1U << USB_STS_EP2_RDY_LEN) - 1) << USB_STS_EP2_RDY_POS)) + +/* 0x48 : ep3_config */ +#define USB_EP3_CONFIG_OFFSET (0x48) +#define USB_CR_EP3_SIZE USB_CR_EP3_SIZE +#define USB_CR_EP3_SIZE_POS (0U) +#define USB_CR_EP3_SIZE_LEN (11U) +#define USB_CR_EP3_SIZE_MSK (((1U << USB_CR_EP3_SIZE_LEN) - 1) << USB_CR_EP3_SIZE_POS) +#define USB_CR_EP3_SIZE_UMSK (~(((1U << USB_CR_EP3_SIZE_LEN) - 1) << USB_CR_EP3_SIZE_POS)) +#define USB_CR_EP3_DIR USB_CR_EP3_DIR +#define USB_CR_EP3_DIR_POS (11U) +#define USB_CR_EP3_DIR_LEN (2U) +#define USB_CR_EP3_DIR_MSK (((1U << USB_CR_EP3_DIR_LEN) - 1) << USB_CR_EP3_DIR_POS) +#define USB_CR_EP3_DIR_UMSK (~(((1U << USB_CR_EP3_DIR_LEN) - 1) << USB_CR_EP3_DIR_POS)) +#define USB_CR_EP3_TYPE USB_CR_EP3_TYPE +#define USB_CR_EP3_TYPE_POS (13U) +#define USB_CR_EP3_TYPE_LEN (3U) +#define USB_CR_EP3_TYPE_MSK (((1U << USB_CR_EP3_TYPE_LEN) - 1) << USB_CR_EP3_TYPE_POS) +#define USB_CR_EP3_TYPE_UMSK (~(((1U << USB_CR_EP3_TYPE_LEN) - 1) << USB_CR_EP3_TYPE_POS)) +#define USB_CR_EP3_STALL USB_CR_EP3_STALL +#define USB_CR_EP3_STALL_POS (16U) +#define USB_CR_EP3_STALL_LEN (1U) +#define USB_CR_EP3_STALL_MSK (((1U << USB_CR_EP3_STALL_LEN) - 1) << USB_CR_EP3_STALL_POS) +#define USB_CR_EP3_STALL_UMSK (~(((1U << USB_CR_EP3_STALL_LEN) - 1) << USB_CR_EP3_STALL_POS)) +#define USB_CR_EP3_NACK USB_CR_EP3_NACK +#define USB_CR_EP3_NACK_POS (17U) +#define USB_CR_EP3_NACK_LEN (1U) +#define USB_CR_EP3_NACK_MSK (((1U << USB_CR_EP3_NACK_LEN) - 1) << USB_CR_EP3_NACK_POS) +#define USB_CR_EP3_NACK_UMSK (~(((1U << USB_CR_EP3_NACK_LEN) - 1) << USB_CR_EP3_NACK_POS)) +#define USB_CR_EP3_RDY USB_CR_EP3_RDY +#define USB_CR_EP3_RDY_POS (18U) +#define USB_CR_EP3_RDY_LEN (1U) +#define USB_CR_EP3_RDY_MSK (((1U << USB_CR_EP3_RDY_LEN) - 1) << USB_CR_EP3_RDY_POS) +#define USB_CR_EP3_RDY_UMSK (~(((1U << USB_CR_EP3_RDY_LEN) - 1) << USB_CR_EP3_RDY_POS)) +#define USB_STS_EP3_RDY USB_STS_EP3_RDY +#define USB_STS_EP3_RDY_POS (19U) +#define USB_STS_EP3_RDY_LEN (1U) +#define USB_STS_EP3_RDY_MSK (((1U << USB_STS_EP3_RDY_LEN) - 1) << USB_STS_EP3_RDY_POS) +#define USB_STS_EP3_RDY_UMSK (~(((1U << USB_STS_EP3_RDY_LEN) - 1) << USB_STS_EP3_RDY_POS)) + +/* 0x4C : ep4_config */ +#define USB_EP4_CONFIG_OFFSET (0x4C) +#define USB_CR_EP4_SIZE USB_CR_EP4_SIZE +#define USB_CR_EP4_SIZE_POS (0U) +#define USB_CR_EP4_SIZE_LEN (11U) +#define USB_CR_EP4_SIZE_MSK (((1U << USB_CR_EP4_SIZE_LEN) - 1) << USB_CR_EP4_SIZE_POS) +#define USB_CR_EP4_SIZE_UMSK (~(((1U << USB_CR_EP4_SIZE_LEN) - 1) << USB_CR_EP4_SIZE_POS)) +#define USB_CR_EP4_DIR USB_CR_EP4_DIR +#define USB_CR_EP4_DIR_POS (11U) +#define USB_CR_EP4_DIR_LEN (2U) +#define USB_CR_EP4_DIR_MSK (((1U << USB_CR_EP4_DIR_LEN) - 1) << USB_CR_EP4_DIR_POS) +#define USB_CR_EP4_DIR_UMSK (~(((1U << USB_CR_EP4_DIR_LEN) - 1) << USB_CR_EP4_DIR_POS)) +#define USB_CR_EP4_TYPE USB_CR_EP4_TYPE +#define USB_CR_EP4_TYPE_POS (13U) +#define USB_CR_EP4_TYPE_LEN (3U) +#define USB_CR_EP4_TYPE_MSK (((1U << USB_CR_EP4_TYPE_LEN) - 1) << USB_CR_EP4_TYPE_POS) +#define USB_CR_EP4_TYPE_UMSK (~(((1U << USB_CR_EP4_TYPE_LEN) - 1) << USB_CR_EP4_TYPE_POS)) +#define USB_CR_EP4_STALL USB_CR_EP4_STALL +#define USB_CR_EP4_STALL_POS (16U) +#define USB_CR_EP4_STALL_LEN (1U) +#define USB_CR_EP4_STALL_MSK (((1U << USB_CR_EP4_STALL_LEN) - 1) << USB_CR_EP4_STALL_POS) +#define USB_CR_EP4_STALL_UMSK (~(((1U << USB_CR_EP4_STALL_LEN) - 1) << USB_CR_EP4_STALL_POS)) +#define USB_CR_EP4_NACK USB_CR_EP4_NACK +#define USB_CR_EP4_NACK_POS (17U) +#define USB_CR_EP4_NACK_LEN (1U) +#define USB_CR_EP4_NACK_MSK (((1U << USB_CR_EP4_NACK_LEN) - 1) << USB_CR_EP4_NACK_POS) +#define USB_CR_EP4_NACK_UMSK (~(((1U << USB_CR_EP4_NACK_LEN) - 1) << USB_CR_EP4_NACK_POS)) +#define USB_CR_EP4_RDY USB_CR_EP4_RDY +#define USB_CR_EP4_RDY_POS (18U) +#define USB_CR_EP4_RDY_LEN (1U) +#define USB_CR_EP4_RDY_MSK (((1U << USB_CR_EP4_RDY_LEN) - 1) << USB_CR_EP4_RDY_POS) +#define USB_CR_EP4_RDY_UMSK (~(((1U << USB_CR_EP4_RDY_LEN) - 1) << USB_CR_EP4_RDY_POS)) +#define USB_STS_EP4_RDY USB_STS_EP4_RDY +#define USB_STS_EP4_RDY_POS (19U) +#define USB_STS_EP4_RDY_LEN (1U) +#define USB_STS_EP4_RDY_MSK (((1U << USB_STS_EP4_RDY_LEN) - 1) << USB_STS_EP4_RDY_POS) +#define USB_STS_EP4_RDY_UMSK (~(((1U << USB_STS_EP4_RDY_LEN) - 1) << USB_STS_EP4_RDY_POS)) + +/* 0x50 : ep5_config */ +#define USB_EP5_CONFIG_OFFSET (0x50) +#define USB_CR_EP5_SIZE USB_CR_EP5_SIZE +#define USB_CR_EP5_SIZE_POS (0U) +#define USB_CR_EP5_SIZE_LEN (11U) +#define USB_CR_EP5_SIZE_MSK (((1U << USB_CR_EP5_SIZE_LEN) - 1) << USB_CR_EP5_SIZE_POS) +#define USB_CR_EP5_SIZE_UMSK (~(((1U << USB_CR_EP5_SIZE_LEN) - 1) << USB_CR_EP5_SIZE_POS)) +#define USB_CR_EP5_DIR USB_CR_EP5_DIR +#define USB_CR_EP5_DIR_POS (11U) +#define USB_CR_EP5_DIR_LEN (2U) +#define USB_CR_EP5_DIR_MSK (((1U << USB_CR_EP5_DIR_LEN) - 1) << USB_CR_EP5_DIR_POS) +#define USB_CR_EP5_DIR_UMSK (~(((1U << USB_CR_EP5_DIR_LEN) - 1) << USB_CR_EP5_DIR_POS)) +#define USB_CR_EP5_TYPE USB_CR_EP5_TYPE +#define USB_CR_EP5_TYPE_POS (13U) +#define USB_CR_EP5_TYPE_LEN (3U) +#define USB_CR_EP5_TYPE_MSK (((1U << USB_CR_EP5_TYPE_LEN) - 1) << USB_CR_EP5_TYPE_POS) +#define USB_CR_EP5_TYPE_UMSK (~(((1U << USB_CR_EP5_TYPE_LEN) - 1) << USB_CR_EP5_TYPE_POS)) +#define USB_CR_EP5_STALL USB_CR_EP5_STALL +#define USB_CR_EP5_STALL_POS (16U) +#define USB_CR_EP5_STALL_LEN (1U) +#define USB_CR_EP5_STALL_MSK (((1U << USB_CR_EP5_STALL_LEN) - 1) << USB_CR_EP5_STALL_POS) +#define USB_CR_EP5_STALL_UMSK (~(((1U << USB_CR_EP5_STALL_LEN) - 1) << USB_CR_EP5_STALL_POS)) +#define USB_CR_EP5_NACK USB_CR_EP5_NACK +#define USB_CR_EP5_NACK_POS (17U) +#define USB_CR_EP5_NACK_LEN (1U) +#define USB_CR_EP5_NACK_MSK (((1U << USB_CR_EP5_NACK_LEN) - 1) << USB_CR_EP5_NACK_POS) +#define USB_CR_EP5_NACK_UMSK (~(((1U << USB_CR_EP5_NACK_LEN) - 1) << USB_CR_EP5_NACK_POS)) +#define USB_CR_EP5_RDY USB_CR_EP5_RDY +#define USB_CR_EP5_RDY_POS (18U) +#define USB_CR_EP5_RDY_LEN (1U) +#define USB_CR_EP5_RDY_MSK (((1U << USB_CR_EP5_RDY_LEN) - 1) << USB_CR_EP5_RDY_POS) +#define USB_CR_EP5_RDY_UMSK (~(((1U << USB_CR_EP5_RDY_LEN) - 1) << USB_CR_EP5_RDY_POS)) +#define USB_STS_EP5_RDY USB_STS_EP5_RDY +#define USB_STS_EP5_RDY_POS (19U) +#define USB_STS_EP5_RDY_LEN (1U) +#define USB_STS_EP5_RDY_MSK (((1U << USB_STS_EP5_RDY_LEN) - 1) << USB_STS_EP5_RDY_POS) +#define USB_STS_EP5_RDY_UMSK (~(((1U << USB_STS_EP5_RDY_LEN) - 1) << USB_STS_EP5_RDY_POS)) + +/* 0x54 : ep6_config */ +#define USB_EP6_CONFIG_OFFSET (0x54) +#define USB_CR_EP6_SIZE USB_CR_EP6_SIZE +#define USB_CR_EP6_SIZE_POS (0U) +#define USB_CR_EP6_SIZE_LEN (11U) +#define USB_CR_EP6_SIZE_MSK (((1U << USB_CR_EP6_SIZE_LEN) - 1) << USB_CR_EP6_SIZE_POS) +#define USB_CR_EP6_SIZE_UMSK (~(((1U << USB_CR_EP6_SIZE_LEN) - 1) << USB_CR_EP6_SIZE_POS)) +#define USB_CR_EP6_DIR USB_CR_EP6_DIR +#define USB_CR_EP6_DIR_POS (11U) +#define USB_CR_EP6_DIR_LEN (2U) +#define USB_CR_EP6_DIR_MSK (((1U << USB_CR_EP6_DIR_LEN) - 1) << USB_CR_EP6_DIR_POS) +#define USB_CR_EP6_DIR_UMSK (~(((1U << USB_CR_EP6_DIR_LEN) - 1) << USB_CR_EP6_DIR_POS)) +#define USB_CR_EP6_TYPE USB_CR_EP6_TYPE +#define USB_CR_EP6_TYPE_POS (13U) +#define USB_CR_EP6_TYPE_LEN (3U) +#define USB_CR_EP6_TYPE_MSK (((1U << USB_CR_EP6_TYPE_LEN) - 1) << USB_CR_EP6_TYPE_POS) +#define USB_CR_EP6_TYPE_UMSK (~(((1U << USB_CR_EP6_TYPE_LEN) - 1) << USB_CR_EP6_TYPE_POS)) +#define USB_CR_EP6_STALL USB_CR_EP6_STALL +#define USB_CR_EP6_STALL_POS (16U) +#define USB_CR_EP6_STALL_LEN (1U) +#define USB_CR_EP6_STALL_MSK (((1U << USB_CR_EP6_STALL_LEN) - 1) << USB_CR_EP6_STALL_POS) +#define USB_CR_EP6_STALL_UMSK (~(((1U << USB_CR_EP6_STALL_LEN) - 1) << USB_CR_EP6_STALL_POS)) +#define USB_CR_EP6_NACK USB_CR_EP6_NACK +#define USB_CR_EP6_NACK_POS (17U) +#define USB_CR_EP6_NACK_LEN (1U) +#define USB_CR_EP6_NACK_MSK (((1U << USB_CR_EP6_NACK_LEN) - 1) << USB_CR_EP6_NACK_POS) +#define USB_CR_EP6_NACK_UMSK (~(((1U << USB_CR_EP6_NACK_LEN) - 1) << USB_CR_EP6_NACK_POS)) +#define USB_CR_EP6_RDY USB_CR_EP6_RDY +#define USB_CR_EP6_RDY_POS (18U) +#define USB_CR_EP6_RDY_LEN (1U) +#define USB_CR_EP6_RDY_MSK (((1U << USB_CR_EP6_RDY_LEN) - 1) << USB_CR_EP6_RDY_POS) +#define USB_CR_EP6_RDY_UMSK (~(((1U << USB_CR_EP6_RDY_LEN) - 1) << USB_CR_EP6_RDY_POS)) +#define USB_STS_EP6_RDY USB_STS_EP6_RDY +#define USB_STS_EP6_RDY_POS (19U) +#define USB_STS_EP6_RDY_LEN (1U) +#define USB_STS_EP6_RDY_MSK (((1U << USB_STS_EP6_RDY_LEN) - 1) << USB_STS_EP6_RDY_POS) +#define USB_STS_EP6_RDY_UMSK (~(((1U << USB_STS_EP6_RDY_LEN) - 1) << USB_STS_EP6_RDY_POS)) + +/* 0x58 : ep7_config */ +#define USB_EP7_CONFIG_OFFSET (0x58) +#define USB_CR_EP7_SIZE USB_CR_EP7_SIZE +#define USB_CR_EP7_SIZE_POS (0U) +#define USB_CR_EP7_SIZE_LEN (11U) +#define USB_CR_EP7_SIZE_MSK (((1U << USB_CR_EP7_SIZE_LEN) - 1) << USB_CR_EP7_SIZE_POS) +#define USB_CR_EP7_SIZE_UMSK (~(((1U << USB_CR_EP7_SIZE_LEN) - 1) << USB_CR_EP7_SIZE_POS)) +#define USB_CR_EP7_DIR USB_CR_EP7_DIR +#define USB_CR_EP7_DIR_POS (11U) +#define USB_CR_EP7_DIR_LEN (2U) +#define USB_CR_EP7_DIR_MSK (((1U << USB_CR_EP7_DIR_LEN) - 1) << USB_CR_EP7_DIR_POS) +#define USB_CR_EP7_DIR_UMSK (~(((1U << USB_CR_EP7_DIR_LEN) - 1) << USB_CR_EP7_DIR_POS)) +#define USB_CR_EP7_TYPE USB_CR_EP7_TYPE +#define USB_CR_EP7_TYPE_POS (13U) +#define USB_CR_EP7_TYPE_LEN (3U) +#define USB_CR_EP7_TYPE_MSK (((1U << USB_CR_EP7_TYPE_LEN) - 1) << USB_CR_EP7_TYPE_POS) +#define USB_CR_EP7_TYPE_UMSK (~(((1U << USB_CR_EP7_TYPE_LEN) - 1) << USB_CR_EP7_TYPE_POS)) +#define USB_CR_EP7_STALL USB_CR_EP7_STALL +#define USB_CR_EP7_STALL_POS (16U) +#define USB_CR_EP7_STALL_LEN (1U) +#define USB_CR_EP7_STALL_MSK (((1U << USB_CR_EP7_STALL_LEN) - 1) << USB_CR_EP7_STALL_POS) +#define USB_CR_EP7_STALL_UMSK (~(((1U << USB_CR_EP7_STALL_LEN) - 1) << USB_CR_EP7_STALL_POS)) +#define USB_CR_EP7_NACK USB_CR_EP7_NACK +#define USB_CR_EP7_NACK_POS (17U) +#define USB_CR_EP7_NACK_LEN (1U) +#define USB_CR_EP7_NACK_MSK (((1U << USB_CR_EP7_NACK_LEN) - 1) << USB_CR_EP7_NACK_POS) +#define USB_CR_EP7_NACK_UMSK (~(((1U << USB_CR_EP7_NACK_LEN) - 1) << USB_CR_EP7_NACK_POS)) +#define USB_CR_EP7_RDY USB_CR_EP7_RDY +#define USB_CR_EP7_RDY_POS (18U) +#define USB_CR_EP7_RDY_LEN (1U) +#define USB_CR_EP7_RDY_MSK (((1U << USB_CR_EP7_RDY_LEN) - 1) << USB_CR_EP7_RDY_POS) +#define USB_CR_EP7_RDY_UMSK (~(((1U << USB_CR_EP7_RDY_LEN) - 1) << USB_CR_EP7_RDY_POS)) +#define USB_STS_EP7_RDY USB_STS_EP7_RDY +#define USB_STS_EP7_RDY_POS (19U) +#define USB_STS_EP7_RDY_LEN (1U) +#define USB_STS_EP7_RDY_MSK (((1U << USB_STS_EP7_RDY_LEN) - 1) << USB_STS_EP7_RDY_POS) +#define USB_STS_EP7_RDY_UMSK (~(((1U << USB_STS_EP7_RDY_LEN) - 1) << USB_STS_EP7_RDY_POS)) + +/* 0x100 : ep0_fifo_config */ +#define USB_EP0_FIFO_CONFIG_OFFSET (0x100) +#define USB_EP0_DMA_TX_EN USB_EP0_DMA_TX_EN +#define USB_EP0_DMA_TX_EN_POS (0U) +#define USB_EP0_DMA_TX_EN_LEN (1U) +#define USB_EP0_DMA_TX_EN_MSK (((1U << USB_EP0_DMA_TX_EN_LEN) - 1) << USB_EP0_DMA_TX_EN_POS) +#define USB_EP0_DMA_TX_EN_UMSK (~(((1U << USB_EP0_DMA_TX_EN_LEN) - 1) << USB_EP0_DMA_TX_EN_POS)) +#define USB_EP0_DMA_RX_EN USB_EP0_DMA_RX_EN +#define USB_EP0_DMA_RX_EN_POS (1U) +#define USB_EP0_DMA_RX_EN_LEN (1U) +#define USB_EP0_DMA_RX_EN_MSK (((1U << USB_EP0_DMA_RX_EN_LEN) - 1) << USB_EP0_DMA_RX_EN_POS) +#define USB_EP0_DMA_RX_EN_UMSK (~(((1U << USB_EP0_DMA_RX_EN_LEN) - 1) << USB_EP0_DMA_RX_EN_POS)) +#define USB_EP0_TX_FIFO_CLR USB_EP0_TX_FIFO_CLR +#define USB_EP0_TX_FIFO_CLR_POS (2U) +#define USB_EP0_TX_FIFO_CLR_LEN (1U) +#define USB_EP0_TX_FIFO_CLR_MSK (((1U << USB_EP0_TX_FIFO_CLR_LEN) - 1) << USB_EP0_TX_FIFO_CLR_POS) +#define USB_EP0_TX_FIFO_CLR_UMSK (~(((1U << USB_EP0_TX_FIFO_CLR_LEN) - 1) << USB_EP0_TX_FIFO_CLR_POS)) +#define USB_EP0_RX_FIFO_CLR USB_EP0_RX_FIFO_CLR +#define USB_EP0_RX_FIFO_CLR_POS (3U) +#define USB_EP0_RX_FIFO_CLR_LEN (1U) +#define USB_EP0_RX_FIFO_CLR_MSK (((1U << USB_EP0_RX_FIFO_CLR_LEN) - 1) << USB_EP0_RX_FIFO_CLR_POS) +#define USB_EP0_RX_FIFO_CLR_UMSK (~(((1U << USB_EP0_RX_FIFO_CLR_LEN) - 1) << USB_EP0_RX_FIFO_CLR_POS)) +#define USB_EP0_TX_FIFO_OVERFLOW USB_EP0_TX_FIFO_OVERFLOW +#define USB_EP0_TX_FIFO_OVERFLOW_POS (4U) +#define USB_EP0_TX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP0_TX_FIFO_OVERFLOW_MSK (((1U << USB_EP0_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_OVERFLOW_POS) +#define USB_EP0_TX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP0_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_OVERFLOW_POS)) +#define USB_EP0_TX_FIFO_UNDERFLOW USB_EP0_TX_FIFO_UNDERFLOW +#define USB_EP0_TX_FIFO_UNDERFLOW_POS (5U) +#define USB_EP0_TX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP0_TX_FIFO_UNDERFLOW_MSK (((1U << USB_EP0_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_UNDERFLOW_POS) +#define USB_EP0_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP0_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_UNDERFLOW_POS)) +#define USB_EP0_RX_FIFO_OVERFLOW USB_EP0_RX_FIFO_OVERFLOW +#define USB_EP0_RX_FIFO_OVERFLOW_POS (6U) +#define USB_EP0_RX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP0_RX_FIFO_OVERFLOW_MSK (((1U << USB_EP0_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_OVERFLOW_POS) +#define USB_EP0_RX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP0_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_OVERFLOW_POS)) +#define USB_EP0_RX_FIFO_UNDERFLOW USB_EP0_RX_FIFO_UNDERFLOW +#define USB_EP0_RX_FIFO_UNDERFLOW_POS (7U) +#define USB_EP0_RX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP0_RX_FIFO_UNDERFLOW_MSK (((1U << USB_EP0_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_UNDERFLOW_POS) +#define USB_EP0_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP0_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_UNDERFLOW_POS)) + +/* 0x104 : ep0_fifo_status */ +#define USB_EP0_FIFO_STATUS_OFFSET (0x104) +#define USB_EP0_TX_FIFO_CNT USB_EP0_TX_FIFO_CNT +#define USB_EP0_TX_FIFO_CNT_POS (0U) +#define USB_EP0_TX_FIFO_CNT_LEN (7U) +#define USB_EP0_TX_FIFO_CNT_MSK (((1U << USB_EP0_TX_FIFO_CNT_LEN) - 1) << USB_EP0_TX_FIFO_CNT_POS) +#define USB_EP0_TX_FIFO_CNT_UMSK (~(((1U << USB_EP0_TX_FIFO_CNT_LEN) - 1) << USB_EP0_TX_FIFO_CNT_POS)) +#define USB_EP0_TX_FIFO_EMPTY USB_EP0_TX_FIFO_EMPTY +#define USB_EP0_TX_FIFO_EMPTY_POS (14U) +#define USB_EP0_TX_FIFO_EMPTY_LEN (1U) +#define USB_EP0_TX_FIFO_EMPTY_MSK (((1U << USB_EP0_TX_FIFO_EMPTY_LEN) - 1) << USB_EP0_TX_FIFO_EMPTY_POS) +#define USB_EP0_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP0_TX_FIFO_EMPTY_LEN) - 1) << USB_EP0_TX_FIFO_EMPTY_POS)) +#define USB_EP0_TX_FIFO_FULL USB_EP0_TX_FIFO_FULL +#define USB_EP0_TX_FIFO_FULL_POS (15U) +#define USB_EP0_TX_FIFO_FULL_LEN (1U) +#define USB_EP0_TX_FIFO_FULL_MSK (((1U << USB_EP0_TX_FIFO_FULL_LEN) - 1) << USB_EP0_TX_FIFO_FULL_POS) +#define USB_EP0_TX_FIFO_FULL_UMSK (~(((1U << USB_EP0_TX_FIFO_FULL_LEN) - 1) << USB_EP0_TX_FIFO_FULL_POS)) +#define USB_EP0_RX_FIFO_CNT USB_EP0_RX_FIFO_CNT +#define USB_EP0_RX_FIFO_CNT_POS (16U) +#define USB_EP0_RX_FIFO_CNT_LEN (7U) +#define USB_EP0_RX_FIFO_CNT_MSK (((1U << USB_EP0_RX_FIFO_CNT_LEN) - 1) << USB_EP0_RX_FIFO_CNT_POS) +#define USB_EP0_RX_FIFO_CNT_UMSK (~(((1U << USB_EP0_RX_FIFO_CNT_LEN) - 1) << USB_EP0_RX_FIFO_CNT_POS)) +#define USB_EP0_RX_FIFO_EMPTY USB_EP0_RX_FIFO_EMPTY +#define USB_EP0_RX_FIFO_EMPTY_POS (30U) +#define USB_EP0_RX_FIFO_EMPTY_LEN (1U) +#define USB_EP0_RX_FIFO_EMPTY_MSK (((1U << USB_EP0_RX_FIFO_EMPTY_LEN) - 1) << USB_EP0_RX_FIFO_EMPTY_POS) +#define USB_EP0_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP0_RX_FIFO_EMPTY_LEN) - 1) << USB_EP0_RX_FIFO_EMPTY_POS)) +#define USB_EP0_RX_FIFO_FULL USB_EP0_RX_FIFO_FULL +#define USB_EP0_RX_FIFO_FULL_POS (31U) +#define USB_EP0_RX_FIFO_FULL_LEN (1U) +#define USB_EP0_RX_FIFO_FULL_MSK (((1U << USB_EP0_RX_FIFO_FULL_LEN) - 1) << USB_EP0_RX_FIFO_FULL_POS) +#define USB_EP0_RX_FIFO_FULL_UMSK (~(((1U << USB_EP0_RX_FIFO_FULL_LEN) - 1) << USB_EP0_RX_FIFO_FULL_POS)) + +/* 0x108 : ep0_tx_fifo_wdata */ +#define USB_EP0_TX_FIFO_WDATA_OFFSET (0x108) +#define USB_EP0_TX_FIFO_WDATA USB_EP0_TX_FIFO_WDATA +#define USB_EP0_TX_FIFO_WDATA_POS (0U) +#define USB_EP0_TX_FIFO_WDATA_LEN (8U) +#define USB_EP0_TX_FIFO_WDATA_MSK (((1U << USB_EP0_TX_FIFO_WDATA_LEN) - 1) << USB_EP0_TX_FIFO_WDATA_POS) +#define USB_EP0_TX_FIFO_WDATA_UMSK (~(((1U << USB_EP0_TX_FIFO_WDATA_LEN) - 1) << USB_EP0_TX_FIFO_WDATA_POS)) + +/* 0x10C : ep0_rx_fifo_rdata */ +#define USB_EP0_RX_FIFO_RDATA_OFFSET (0x10C) +#define USB_EP0_RX_FIFO_RDATA USB_EP0_RX_FIFO_RDATA +#define USB_EP0_RX_FIFO_RDATA_POS (0U) +#define USB_EP0_RX_FIFO_RDATA_LEN (8U) +#define USB_EP0_RX_FIFO_RDATA_MSK (((1U << USB_EP0_RX_FIFO_RDATA_LEN) - 1) << USB_EP0_RX_FIFO_RDATA_POS) +#define USB_EP0_RX_FIFO_RDATA_UMSK (~(((1U << USB_EP0_RX_FIFO_RDATA_LEN) - 1) << USB_EP0_RX_FIFO_RDATA_POS)) + +/* 0x110 : ep1_fifo_config */ +#define USB_EP1_FIFO_CONFIG_OFFSET (0x110) +#define USB_EP1_DMA_TX_EN USB_EP1_DMA_TX_EN +#define USB_EP1_DMA_TX_EN_POS (0U) +#define USB_EP1_DMA_TX_EN_LEN (1U) +#define USB_EP1_DMA_TX_EN_MSK (((1U << USB_EP1_DMA_TX_EN_LEN) - 1) << USB_EP1_DMA_TX_EN_POS) +#define USB_EP1_DMA_TX_EN_UMSK (~(((1U << USB_EP1_DMA_TX_EN_LEN) - 1) << USB_EP1_DMA_TX_EN_POS)) +#define USB_EP1_DMA_RX_EN USB_EP1_DMA_RX_EN +#define USB_EP1_DMA_RX_EN_POS (1U) +#define USB_EP1_DMA_RX_EN_LEN (1U) +#define USB_EP1_DMA_RX_EN_MSK (((1U << USB_EP1_DMA_RX_EN_LEN) - 1) << USB_EP1_DMA_RX_EN_POS) +#define USB_EP1_DMA_RX_EN_UMSK (~(((1U << USB_EP1_DMA_RX_EN_LEN) - 1) << USB_EP1_DMA_RX_EN_POS)) +#define USB_EP1_TX_FIFO_CLR USB_EP1_TX_FIFO_CLR +#define USB_EP1_TX_FIFO_CLR_POS (2U) +#define USB_EP1_TX_FIFO_CLR_LEN (1U) +#define USB_EP1_TX_FIFO_CLR_MSK (((1U << USB_EP1_TX_FIFO_CLR_LEN) - 1) << USB_EP1_TX_FIFO_CLR_POS) +#define USB_EP1_TX_FIFO_CLR_UMSK (~(((1U << USB_EP1_TX_FIFO_CLR_LEN) - 1) << USB_EP1_TX_FIFO_CLR_POS)) +#define USB_EP1_RX_FIFO_CLR USB_EP1_RX_FIFO_CLR +#define USB_EP1_RX_FIFO_CLR_POS (3U) +#define USB_EP1_RX_FIFO_CLR_LEN (1U) +#define USB_EP1_RX_FIFO_CLR_MSK (((1U << USB_EP1_RX_FIFO_CLR_LEN) - 1) << USB_EP1_RX_FIFO_CLR_POS) +#define USB_EP1_RX_FIFO_CLR_UMSK (~(((1U << USB_EP1_RX_FIFO_CLR_LEN) - 1) << USB_EP1_RX_FIFO_CLR_POS)) +#define USB_EP1_TX_FIFO_OVERFLOW USB_EP1_TX_FIFO_OVERFLOW +#define USB_EP1_TX_FIFO_OVERFLOW_POS (4U) +#define USB_EP1_TX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP1_TX_FIFO_OVERFLOW_MSK (((1U << USB_EP1_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_OVERFLOW_POS) +#define USB_EP1_TX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP1_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_OVERFLOW_POS)) +#define USB_EP1_TX_FIFO_UNDERFLOW USB_EP1_TX_FIFO_UNDERFLOW +#define USB_EP1_TX_FIFO_UNDERFLOW_POS (5U) +#define USB_EP1_TX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP1_TX_FIFO_UNDERFLOW_MSK (((1U << USB_EP1_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_UNDERFLOW_POS) +#define USB_EP1_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP1_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_UNDERFLOW_POS)) +#define USB_EP1_RX_FIFO_OVERFLOW USB_EP1_RX_FIFO_OVERFLOW +#define USB_EP1_RX_FIFO_OVERFLOW_POS (6U) +#define USB_EP1_RX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP1_RX_FIFO_OVERFLOW_MSK (((1U << USB_EP1_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_OVERFLOW_POS) +#define USB_EP1_RX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP1_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_OVERFLOW_POS)) +#define USB_EP1_RX_FIFO_UNDERFLOW USB_EP1_RX_FIFO_UNDERFLOW +#define USB_EP1_RX_FIFO_UNDERFLOW_POS (7U) +#define USB_EP1_RX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP1_RX_FIFO_UNDERFLOW_MSK (((1U << USB_EP1_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_UNDERFLOW_POS) +#define USB_EP1_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP1_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_UNDERFLOW_POS)) + +/* 0x114 : ep1_fifo_status */ +#define USB_EP1_FIFO_STATUS_OFFSET (0x114) +#define USB_EP1_TX_FIFO_CNT USB_EP1_TX_FIFO_CNT +#define USB_EP1_TX_FIFO_CNT_POS (0U) +#define USB_EP1_TX_FIFO_CNT_LEN (7U) +#define USB_EP1_TX_FIFO_CNT_MSK (((1U << USB_EP1_TX_FIFO_CNT_LEN) - 1) << USB_EP1_TX_FIFO_CNT_POS) +#define USB_EP1_TX_FIFO_CNT_UMSK (~(((1U << USB_EP1_TX_FIFO_CNT_LEN) - 1) << USB_EP1_TX_FIFO_CNT_POS)) +#define USB_EP1_TX_FIFO_EMPTY USB_EP1_TX_FIFO_EMPTY +#define USB_EP1_TX_FIFO_EMPTY_POS (14U) +#define USB_EP1_TX_FIFO_EMPTY_LEN (1U) +#define USB_EP1_TX_FIFO_EMPTY_MSK (((1U << USB_EP1_TX_FIFO_EMPTY_LEN) - 1) << USB_EP1_TX_FIFO_EMPTY_POS) +#define USB_EP1_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP1_TX_FIFO_EMPTY_LEN) - 1) << USB_EP1_TX_FIFO_EMPTY_POS)) +#define USB_EP1_TX_FIFO_FULL USB_EP1_TX_FIFO_FULL +#define USB_EP1_TX_FIFO_FULL_POS (15U) +#define USB_EP1_TX_FIFO_FULL_LEN (1U) +#define USB_EP1_TX_FIFO_FULL_MSK (((1U << USB_EP1_TX_FIFO_FULL_LEN) - 1) << USB_EP1_TX_FIFO_FULL_POS) +#define USB_EP1_TX_FIFO_FULL_UMSK (~(((1U << USB_EP1_TX_FIFO_FULL_LEN) - 1) << USB_EP1_TX_FIFO_FULL_POS)) +#define USB_EP1_RX_FIFO_CNT USB_EP1_RX_FIFO_CNT +#define USB_EP1_RX_FIFO_CNT_POS (16U) +#define USB_EP1_RX_FIFO_CNT_LEN (7U) +#define USB_EP1_RX_FIFO_CNT_MSK (((1U << USB_EP1_RX_FIFO_CNT_LEN) - 1) << USB_EP1_RX_FIFO_CNT_POS) +#define USB_EP1_RX_FIFO_CNT_UMSK (~(((1U << USB_EP1_RX_FIFO_CNT_LEN) - 1) << USB_EP1_RX_FIFO_CNT_POS)) +#define USB_EP1_RX_FIFO_EMPTY USB_EP1_RX_FIFO_EMPTY +#define USB_EP1_RX_FIFO_EMPTY_POS (30U) +#define USB_EP1_RX_FIFO_EMPTY_LEN (1U) +#define USB_EP1_RX_FIFO_EMPTY_MSK (((1U << USB_EP1_RX_FIFO_EMPTY_LEN) - 1) << USB_EP1_RX_FIFO_EMPTY_POS) +#define USB_EP1_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP1_RX_FIFO_EMPTY_LEN) - 1) << USB_EP1_RX_FIFO_EMPTY_POS)) +#define USB_EP1_RX_FIFO_FULL USB_EP1_RX_FIFO_FULL +#define USB_EP1_RX_FIFO_FULL_POS (31U) +#define USB_EP1_RX_FIFO_FULL_LEN (1U) +#define USB_EP1_RX_FIFO_FULL_MSK (((1U << USB_EP1_RX_FIFO_FULL_LEN) - 1) << USB_EP1_RX_FIFO_FULL_POS) +#define USB_EP1_RX_FIFO_FULL_UMSK (~(((1U << USB_EP1_RX_FIFO_FULL_LEN) - 1) << USB_EP1_RX_FIFO_FULL_POS)) + +/* 0x118 : ep1_tx_fifo_wdata */ +#define USB_EP1_TX_FIFO_WDATA_OFFSET (0x118) +#define USB_EP1_TX_FIFO_WDATA USB_EP1_TX_FIFO_WDATA +#define USB_EP1_TX_FIFO_WDATA_POS (0U) +#define USB_EP1_TX_FIFO_WDATA_LEN (8U) +#define USB_EP1_TX_FIFO_WDATA_MSK (((1U << USB_EP1_TX_FIFO_WDATA_LEN) - 1) << USB_EP1_TX_FIFO_WDATA_POS) +#define USB_EP1_TX_FIFO_WDATA_UMSK (~(((1U << USB_EP1_TX_FIFO_WDATA_LEN) - 1) << USB_EP1_TX_FIFO_WDATA_POS)) + +/* 0x11C : ep1_rx_fifo_rdata */ +#define USB_EP1_RX_FIFO_RDATA_OFFSET (0x11C) +#define USB_EP1_RX_FIFO_RDATA USB_EP1_RX_FIFO_RDATA +#define USB_EP1_RX_FIFO_RDATA_POS (0U) +#define USB_EP1_RX_FIFO_RDATA_LEN (8U) +#define USB_EP1_RX_FIFO_RDATA_MSK (((1U << USB_EP1_RX_FIFO_RDATA_LEN) - 1) << USB_EP1_RX_FIFO_RDATA_POS) +#define USB_EP1_RX_FIFO_RDATA_UMSK (~(((1U << USB_EP1_RX_FIFO_RDATA_LEN) - 1) << USB_EP1_RX_FIFO_RDATA_POS)) + +/* 0x120 : ep2_fifo_config */ +#define USB_EP2_FIFO_CONFIG_OFFSET (0x120) +#define USB_EP2_DMA_TX_EN USB_EP2_DMA_TX_EN +#define USB_EP2_DMA_TX_EN_POS (0U) +#define USB_EP2_DMA_TX_EN_LEN (1U) +#define USB_EP2_DMA_TX_EN_MSK (((1U << USB_EP2_DMA_TX_EN_LEN) - 1) << USB_EP2_DMA_TX_EN_POS) +#define USB_EP2_DMA_TX_EN_UMSK (~(((1U << USB_EP2_DMA_TX_EN_LEN) - 1) << USB_EP2_DMA_TX_EN_POS)) +#define USB_EP2_DMA_RX_EN USB_EP2_DMA_RX_EN +#define USB_EP2_DMA_RX_EN_POS (1U) +#define USB_EP2_DMA_RX_EN_LEN (1U) +#define USB_EP2_DMA_RX_EN_MSK (((1U << USB_EP2_DMA_RX_EN_LEN) - 1) << USB_EP2_DMA_RX_EN_POS) +#define USB_EP2_DMA_RX_EN_UMSK (~(((1U << USB_EP2_DMA_RX_EN_LEN) - 1) << USB_EP2_DMA_RX_EN_POS)) +#define USB_EP2_TX_FIFO_CLR USB_EP2_TX_FIFO_CLR +#define USB_EP2_TX_FIFO_CLR_POS (2U) +#define USB_EP2_TX_FIFO_CLR_LEN (1U) +#define USB_EP2_TX_FIFO_CLR_MSK (((1U << USB_EP2_TX_FIFO_CLR_LEN) - 1) << USB_EP2_TX_FIFO_CLR_POS) +#define USB_EP2_TX_FIFO_CLR_UMSK (~(((1U << USB_EP2_TX_FIFO_CLR_LEN) - 1) << USB_EP2_TX_FIFO_CLR_POS)) +#define USB_EP2_RX_FIFO_CLR USB_EP2_RX_FIFO_CLR +#define USB_EP2_RX_FIFO_CLR_POS (3U) +#define USB_EP2_RX_FIFO_CLR_LEN (1U) +#define USB_EP2_RX_FIFO_CLR_MSK (((1U << USB_EP2_RX_FIFO_CLR_LEN) - 1) << USB_EP2_RX_FIFO_CLR_POS) +#define USB_EP2_RX_FIFO_CLR_UMSK (~(((1U << USB_EP2_RX_FIFO_CLR_LEN) - 1) << USB_EP2_RX_FIFO_CLR_POS)) +#define USB_EP2_TX_FIFO_OVERFLOW USB_EP2_TX_FIFO_OVERFLOW +#define USB_EP2_TX_FIFO_OVERFLOW_POS (4U) +#define USB_EP2_TX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP2_TX_FIFO_OVERFLOW_MSK (((1U << USB_EP2_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_OVERFLOW_POS) +#define USB_EP2_TX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP2_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_OVERFLOW_POS)) +#define USB_EP2_TX_FIFO_UNDERFLOW USB_EP2_TX_FIFO_UNDERFLOW +#define USB_EP2_TX_FIFO_UNDERFLOW_POS (5U) +#define USB_EP2_TX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP2_TX_FIFO_UNDERFLOW_MSK (((1U << USB_EP2_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_UNDERFLOW_POS) +#define USB_EP2_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP2_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_UNDERFLOW_POS)) +#define USB_EP2_RX_FIFO_OVERFLOW USB_EP2_RX_FIFO_OVERFLOW +#define USB_EP2_RX_FIFO_OVERFLOW_POS (6U) +#define USB_EP2_RX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP2_RX_FIFO_OVERFLOW_MSK (((1U << USB_EP2_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_OVERFLOW_POS) +#define USB_EP2_RX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP2_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_OVERFLOW_POS)) +#define USB_EP2_RX_FIFO_UNDERFLOW USB_EP2_RX_FIFO_UNDERFLOW +#define USB_EP2_RX_FIFO_UNDERFLOW_POS (7U) +#define USB_EP2_RX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP2_RX_FIFO_UNDERFLOW_MSK (((1U << USB_EP2_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_UNDERFLOW_POS) +#define USB_EP2_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP2_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_UNDERFLOW_POS)) + +/* 0x124 : ep2_fifo_status */ +#define USB_EP2_FIFO_STATUS_OFFSET (0x124) +#define USB_EP2_TX_FIFO_CNT USB_EP2_TX_FIFO_CNT +#define USB_EP2_TX_FIFO_CNT_POS (0U) +#define USB_EP2_TX_FIFO_CNT_LEN (7U) +#define USB_EP2_TX_FIFO_CNT_MSK (((1U << USB_EP2_TX_FIFO_CNT_LEN) - 1) << USB_EP2_TX_FIFO_CNT_POS) +#define USB_EP2_TX_FIFO_CNT_UMSK (~(((1U << USB_EP2_TX_FIFO_CNT_LEN) - 1) << USB_EP2_TX_FIFO_CNT_POS)) +#define USB_EP2_TX_FIFO_EMPTY USB_EP2_TX_FIFO_EMPTY +#define USB_EP2_TX_FIFO_EMPTY_POS (14U) +#define USB_EP2_TX_FIFO_EMPTY_LEN (1U) +#define USB_EP2_TX_FIFO_EMPTY_MSK (((1U << USB_EP2_TX_FIFO_EMPTY_LEN) - 1) << USB_EP2_TX_FIFO_EMPTY_POS) +#define USB_EP2_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP2_TX_FIFO_EMPTY_LEN) - 1) << USB_EP2_TX_FIFO_EMPTY_POS)) +#define USB_EP2_TX_FIFO_FULL USB_EP2_TX_FIFO_FULL +#define USB_EP2_TX_FIFO_FULL_POS (15U) +#define USB_EP2_TX_FIFO_FULL_LEN (1U) +#define USB_EP2_TX_FIFO_FULL_MSK (((1U << USB_EP2_TX_FIFO_FULL_LEN) - 1) << USB_EP2_TX_FIFO_FULL_POS) +#define USB_EP2_TX_FIFO_FULL_UMSK (~(((1U << USB_EP2_TX_FIFO_FULL_LEN) - 1) << USB_EP2_TX_FIFO_FULL_POS)) +#define USB_EP2_RX_FIFO_CNT USB_EP2_RX_FIFO_CNT +#define USB_EP2_RX_FIFO_CNT_POS (16U) +#define USB_EP2_RX_FIFO_CNT_LEN (7U) +#define USB_EP2_RX_FIFO_CNT_MSK (((1U << USB_EP2_RX_FIFO_CNT_LEN) - 1) << USB_EP2_RX_FIFO_CNT_POS) +#define USB_EP2_RX_FIFO_CNT_UMSK (~(((1U << USB_EP2_RX_FIFO_CNT_LEN) - 1) << USB_EP2_RX_FIFO_CNT_POS)) +#define USB_EP2_RX_FIFO_EMPTY USB_EP2_RX_FIFO_EMPTY +#define USB_EP2_RX_FIFO_EMPTY_POS (30U) +#define USB_EP2_RX_FIFO_EMPTY_LEN (1U) +#define USB_EP2_RX_FIFO_EMPTY_MSK (((1U << USB_EP2_RX_FIFO_EMPTY_LEN) - 1) << USB_EP2_RX_FIFO_EMPTY_POS) +#define USB_EP2_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP2_RX_FIFO_EMPTY_LEN) - 1) << USB_EP2_RX_FIFO_EMPTY_POS)) +#define USB_EP2_RX_FIFO_FULL USB_EP2_RX_FIFO_FULL +#define USB_EP2_RX_FIFO_FULL_POS (31U) +#define USB_EP2_RX_FIFO_FULL_LEN (1U) +#define USB_EP2_RX_FIFO_FULL_MSK (((1U << USB_EP2_RX_FIFO_FULL_LEN) - 1) << USB_EP2_RX_FIFO_FULL_POS) +#define USB_EP2_RX_FIFO_FULL_UMSK (~(((1U << USB_EP2_RX_FIFO_FULL_LEN) - 1) << USB_EP2_RX_FIFO_FULL_POS)) + +/* 0x128 : ep2_tx_fifo_wdata */ +#define USB_EP2_TX_FIFO_WDATA_OFFSET (0x128) +#define USB_EP2_TX_FIFO_WDATA USB_EP2_TX_FIFO_WDATA +#define USB_EP2_TX_FIFO_WDATA_POS (0U) +#define USB_EP2_TX_FIFO_WDATA_LEN (8U) +#define USB_EP2_TX_FIFO_WDATA_MSK (((1U << USB_EP2_TX_FIFO_WDATA_LEN) - 1) << USB_EP2_TX_FIFO_WDATA_POS) +#define USB_EP2_TX_FIFO_WDATA_UMSK (~(((1U << USB_EP2_TX_FIFO_WDATA_LEN) - 1) << USB_EP2_TX_FIFO_WDATA_POS)) + +/* 0x12C : ep2_rx_fifo_rdata */ +#define USB_EP2_RX_FIFO_RDATA_OFFSET (0x12C) +#define USB_EP2_RX_FIFO_RDATA USB_EP2_RX_FIFO_RDATA +#define USB_EP2_RX_FIFO_RDATA_POS (0U) +#define USB_EP2_RX_FIFO_RDATA_LEN (8U) +#define USB_EP2_RX_FIFO_RDATA_MSK (((1U << USB_EP2_RX_FIFO_RDATA_LEN) - 1) << USB_EP2_RX_FIFO_RDATA_POS) +#define USB_EP2_RX_FIFO_RDATA_UMSK (~(((1U << USB_EP2_RX_FIFO_RDATA_LEN) - 1) << USB_EP2_RX_FIFO_RDATA_POS)) + +/* 0x130 : ep3_fifo_config */ +#define USB_EP3_FIFO_CONFIG_OFFSET (0x130) +#define USB_EP3_DMA_TX_EN USB_EP3_DMA_TX_EN +#define USB_EP3_DMA_TX_EN_POS (0U) +#define USB_EP3_DMA_TX_EN_LEN (1U) +#define USB_EP3_DMA_TX_EN_MSK (((1U << USB_EP3_DMA_TX_EN_LEN) - 1) << USB_EP3_DMA_TX_EN_POS) +#define USB_EP3_DMA_TX_EN_UMSK (~(((1U << USB_EP3_DMA_TX_EN_LEN) - 1) << USB_EP3_DMA_TX_EN_POS)) +#define USB_EP3_DMA_RX_EN USB_EP3_DMA_RX_EN +#define USB_EP3_DMA_RX_EN_POS (1U) +#define USB_EP3_DMA_RX_EN_LEN (1U) +#define USB_EP3_DMA_RX_EN_MSK (((1U << USB_EP3_DMA_RX_EN_LEN) - 1) << USB_EP3_DMA_RX_EN_POS) +#define USB_EP3_DMA_RX_EN_UMSK (~(((1U << USB_EP3_DMA_RX_EN_LEN) - 1) << USB_EP3_DMA_RX_EN_POS)) +#define USB_EP3_TX_FIFO_CLR USB_EP3_TX_FIFO_CLR +#define USB_EP3_TX_FIFO_CLR_POS (2U) +#define USB_EP3_TX_FIFO_CLR_LEN (1U) +#define USB_EP3_TX_FIFO_CLR_MSK (((1U << USB_EP3_TX_FIFO_CLR_LEN) - 1) << USB_EP3_TX_FIFO_CLR_POS) +#define USB_EP3_TX_FIFO_CLR_UMSK (~(((1U << USB_EP3_TX_FIFO_CLR_LEN) - 1) << USB_EP3_TX_FIFO_CLR_POS)) +#define USB_EP3_RX_FIFO_CLR USB_EP3_RX_FIFO_CLR +#define USB_EP3_RX_FIFO_CLR_POS (3U) +#define USB_EP3_RX_FIFO_CLR_LEN (1U) +#define USB_EP3_RX_FIFO_CLR_MSK (((1U << USB_EP3_RX_FIFO_CLR_LEN) - 1) << USB_EP3_RX_FIFO_CLR_POS) +#define USB_EP3_RX_FIFO_CLR_UMSK (~(((1U << USB_EP3_RX_FIFO_CLR_LEN) - 1) << USB_EP3_RX_FIFO_CLR_POS)) +#define USB_EP3_TX_FIFO_OVERFLOW USB_EP3_TX_FIFO_OVERFLOW +#define USB_EP3_TX_FIFO_OVERFLOW_POS (4U) +#define USB_EP3_TX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP3_TX_FIFO_OVERFLOW_MSK (((1U << USB_EP3_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_OVERFLOW_POS) +#define USB_EP3_TX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP3_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_OVERFLOW_POS)) +#define USB_EP3_TX_FIFO_UNDERFLOW USB_EP3_TX_FIFO_UNDERFLOW +#define USB_EP3_TX_FIFO_UNDERFLOW_POS (5U) +#define USB_EP3_TX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP3_TX_FIFO_UNDERFLOW_MSK (((1U << USB_EP3_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_UNDERFLOW_POS) +#define USB_EP3_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP3_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_UNDERFLOW_POS)) +#define USB_EP3_RX_FIFO_OVERFLOW USB_EP3_RX_FIFO_OVERFLOW +#define USB_EP3_RX_FIFO_OVERFLOW_POS (6U) +#define USB_EP3_RX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP3_RX_FIFO_OVERFLOW_MSK (((1U << USB_EP3_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_OVERFLOW_POS) +#define USB_EP3_RX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP3_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_OVERFLOW_POS)) +#define USB_EP3_RX_FIFO_UNDERFLOW USB_EP3_RX_FIFO_UNDERFLOW +#define USB_EP3_RX_FIFO_UNDERFLOW_POS (7U) +#define USB_EP3_RX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP3_RX_FIFO_UNDERFLOW_MSK (((1U << USB_EP3_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_UNDERFLOW_POS) +#define USB_EP3_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP3_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_UNDERFLOW_POS)) + +/* 0x134 : ep3_fifo_status */ +#define USB_EP3_FIFO_STATUS_OFFSET (0x134) +#define USB_EP3_TX_FIFO_CNT USB_EP3_TX_FIFO_CNT +#define USB_EP3_TX_FIFO_CNT_POS (0U) +#define USB_EP3_TX_FIFO_CNT_LEN (7U) +#define USB_EP3_TX_FIFO_CNT_MSK (((1U << USB_EP3_TX_FIFO_CNT_LEN) - 1) << USB_EP3_TX_FIFO_CNT_POS) +#define USB_EP3_TX_FIFO_CNT_UMSK (~(((1U << USB_EP3_TX_FIFO_CNT_LEN) - 1) << USB_EP3_TX_FIFO_CNT_POS)) +#define USB_EP3_TX_FIFO_EMPTY USB_EP3_TX_FIFO_EMPTY +#define USB_EP3_TX_FIFO_EMPTY_POS (14U) +#define USB_EP3_TX_FIFO_EMPTY_LEN (1U) +#define USB_EP3_TX_FIFO_EMPTY_MSK (((1U << USB_EP3_TX_FIFO_EMPTY_LEN) - 1) << USB_EP3_TX_FIFO_EMPTY_POS) +#define USB_EP3_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP3_TX_FIFO_EMPTY_LEN) - 1) << USB_EP3_TX_FIFO_EMPTY_POS)) +#define USB_EP3_TX_FIFO_FULL USB_EP3_TX_FIFO_FULL +#define USB_EP3_TX_FIFO_FULL_POS (15U) +#define USB_EP3_TX_FIFO_FULL_LEN (1U) +#define USB_EP3_TX_FIFO_FULL_MSK (((1U << USB_EP3_TX_FIFO_FULL_LEN) - 1) << USB_EP3_TX_FIFO_FULL_POS) +#define USB_EP3_TX_FIFO_FULL_UMSK (~(((1U << USB_EP3_TX_FIFO_FULL_LEN) - 1) << USB_EP3_TX_FIFO_FULL_POS)) +#define USB_EP3_RX_FIFO_CNT USB_EP3_RX_FIFO_CNT +#define USB_EP3_RX_FIFO_CNT_POS (16U) +#define USB_EP3_RX_FIFO_CNT_LEN (7U) +#define USB_EP3_RX_FIFO_CNT_MSK (((1U << USB_EP3_RX_FIFO_CNT_LEN) - 1) << USB_EP3_RX_FIFO_CNT_POS) +#define USB_EP3_RX_FIFO_CNT_UMSK (~(((1U << USB_EP3_RX_FIFO_CNT_LEN) - 1) << USB_EP3_RX_FIFO_CNT_POS)) +#define USB_EP3_RX_FIFO_EMPTY USB_EP3_RX_FIFO_EMPTY +#define USB_EP3_RX_FIFO_EMPTY_POS (30U) +#define USB_EP3_RX_FIFO_EMPTY_LEN (1U) +#define USB_EP3_RX_FIFO_EMPTY_MSK (((1U << USB_EP3_RX_FIFO_EMPTY_LEN) - 1) << USB_EP3_RX_FIFO_EMPTY_POS) +#define USB_EP3_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP3_RX_FIFO_EMPTY_LEN) - 1) << USB_EP3_RX_FIFO_EMPTY_POS)) +#define USB_EP3_RX_FIFO_FULL USB_EP3_RX_FIFO_FULL +#define USB_EP3_RX_FIFO_FULL_POS (31U) +#define USB_EP3_RX_FIFO_FULL_LEN (1U) +#define USB_EP3_RX_FIFO_FULL_MSK (((1U << USB_EP3_RX_FIFO_FULL_LEN) - 1) << USB_EP3_RX_FIFO_FULL_POS) +#define USB_EP3_RX_FIFO_FULL_UMSK (~(((1U << USB_EP3_RX_FIFO_FULL_LEN) - 1) << USB_EP3_RX_FIFO_FULL_POS)) + +/* 0x138 : ep3_tx_fifo_wdata */ +#define USB_EP3_TX_FIFO_WDATA_OFFSET (0x138) +#define USB_EP3_TX_FIFO_WDATA USB_EP3_TX_FIFO_WDATA +#define USB_EP3_TX_FIFO_WDATA_POS (0U) +#define USB_EP3_TX_FIFO_WDATA_LEN (8U) +#define USB_EP3_TX_FIFO_WDATA_MSK (((1U << USB_EP3_TX_FIFO_WDATA_LEN) - 1) << USB_EP3_TX_FIFO_WDATA_POS) +#define USB_EP3_TX_FIFO_WDATA_UMSK (~(((1U << USB_EP3_TX_FIFO_WDATA_LEN) - 1) << USB_EP3_TX_FIFO_WDATA_POS)) + +/* 0x13C : ep3_rx_fifo_rdata */ +#define USB_EP3_RX_FIFO_RDATA_OFFSET (0x13C) +#define USB_EP3_RX_FIFO_RDATA USB_EP3_RX_FIFO_RDATA +#define USB_EP3_RX_FIFO_RDATA_POS (0U) +#define USB_EP3_RX_FIFO_RDATA_LEN (8U) +#define USB_EP3_RX_FIFO_RDATA_MSK (((1U << USB_EP3_RX_FIFO_RDATA_LEN) - 1) << USB_EP3_RX_FIFO_RDATA_POS) +#define USB_EP3_RX_FIFO_RDATA_UMSK (~(((1U << USB_EP3_RX_FIFO_RDATA_LEN) - 1) << USB_EP3_RX_FIFO_RDATA_POS)) + +/* 0x140 : ep4_fifo_config */ +#define USB_EP4_FIFO_CONFIG_OFFSET (0x140) +#define USB_EP4_DMA_TX_EN USB_EP4_DMA_TX_EN +#define USB_EP4_DMA_TX_EN_POS (0U) +#define USB_EP4_DMA_TX_EN_LEN (1U) +#define USB_EP4_DMA_TX_EN_MSK (((1U << USB_EP4_DMA_TX_EN_LEN) - 1) << USB_EP4_DMA_TX_EN_POS) +#define USB_EP4_DMA_TX_EN_UMSK (~(((1U << USB_EP4_DMA_TX_EN_LEN) - 1) << USB_EP4_DMA_TX_EN_POS)) +#define USB_EP4_DMA_RX_EN USB_EP4_DMA_RX_EN +#define USB_EP4_DMA_RX_EN_POS (1U) +#define USB_EP4_DMA_RX_EN_LEN (1U) +#define USB_EP4_DMA_RX_EN_MSK (((1U << USB_EP4_DMA_RX_EN_LEN) - 1) << USB_EP4_DMA_RX_EN_POS) +#define USB_EP4_DMA_RX_EN_UMSK (~(((1U << USB_EP4_DMA_RX_EN_LEN) - 1) << USB_EP4_DMA_RX_EN_POS)) +#define USB_EP4_TX_FIFO_CLR USB_EP4_TX_FIFO_CLR +#define USB_EP4_TX_FIFO_CLR_POS (2U) +#define USB_EP4_TX_FIFO_CLR_LEN (1U) +#define USB_EP4_TX_FIFO_CLR_MSK (((1U << USB_EP4_TX_FIFO_CLR_LEN) - 1) << USB_EP4_TX_FIFO_CLR_POS) +#define USB_EP4_TX_FIFO_CLR_UMSK (~(((1U << USB_EP4_TX_FIFO_CLR_LEN) - 1) << USB_EP4_TX_FIFO_CLR_POS)) +#define USB_EP4_RX_FIFO_CLR USB_EP4_RX_FIFO_CLR +#define USB_EP4_RX_FIFO_CLR_POS (3U) +#define USB_EP4_RX_FIFO_CLR_LEN (1U) +#define USB_EP4_RX_FIFO_CLR_MSK (((1U << USB_EP4_RX_FIFO_CLR_LEN) - 1) << USB_EP4_RX_FIFO_CLR_POS) +#define USB_EP4_RX_FIFO_CLR_UMSK (~(((1U << USB_EP4_RX_FIFO_CLR_LEN) - 1) << USB_EP4_RX_FIFO_CLR_POS)) +#define USB_EP4_TX_FIFO_OVERFLOW USB_EP4_TX_FIFO_OVERFLOW +#define USB_EP4_TX_FIFO_OVERFLOW_POS (4U) +#define USB_EP4_TX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP4_TX_FIFO_OVERFLOW_MSK (((1U << USB_EP4_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_OVERFLOW_POS) +#define USB_EP4_TX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP4_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_OVERFLOW_POS)) +#define USB_EP4_TX_FIFO_UNDERFLOW USB_EP4_TX_FIFO_UNDERFLOW +#define USB_EP4_TX_FIFO_UNDERFLOW_POS (5U) +#define USB_EP4_TX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP4_TX_FIFO_UNDERFLOW_MSK (((1U << USB_EP4_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_UNDERFLOW_POS) +#define USB_EP4_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP4_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_UNDERFLOW_POS)) +#define USB_EP4_RX_FIFO_OVERFLOW USB_EP4_RX_FIFO_OVERFLOW +#define USB_EP4_RX_FIFO_OVERFLOW_POS (6U) +#define USB_EP4_RX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP4_RX_FIFO_OVERFLOW_MSK (((1U << USB_EP4_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_OVERFLOW_POS) +#define USB_EP4_RX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP4_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_OVERFLOW_POS)) +#define USB_EP4_RX_FIFO_UNDERFLOW USB_EP4_RX_FIFO_UNDERFLOW +#define USB_EP4_RX_FIFO_UNDERFLOW_POS (7U) +#define USB_EP4_RX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP4_RX_FIFO_UNDERFLOW_MSK (((1U << USB_EP4_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_UNDERFLOW_POS) +#define USB_EP4_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP4_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_UNDERFLOW_POS)) + +/* 0x144 : ep4_fifo_status */ +#define USB_EP4_FIFO_STATUS_OFFSET (0x144) +#define USB_EP4_TX_FIFO_CNT USB_EP4_TX_FIFO_CNT +#define USB_EP4_TX_FIFO_CNT_POS (0U) +#define USB_EP4_TX_FIFO_CNT_LEN (7U) +#define USB_EP4_TX_FIFO_CNT_MSK (((1U << USB_EP4_TX_FIFO_CNT_LEN) - 1) << USB_EP4_TX_FIFO_CNT_POS) +#define USB_EP4_TX_FIFO_CNT_UMSK (~(((1U << USB_EP4_TX_FIFO_CNT_LEN) - 1) << USB_EP4_TX_FIFO_CNT_POS)) +#define USB_EP4_TX_FIFO_EMPTY USB_EP4_TX_FIFO_EMPTY +#define USB_EP4_TX_FIFO_EMPTY_POS (14U) +#define USB_EP4_TX_FIFO_EMPTY_LEN (1U) +#define USB_EP4_TX_FIFO_EMPTY_MSK (((1U << USB_EP4_TX_FIFO_EMPTY_LEN) - 1) << USB_EP4_TX_FIFO_EMPTY_POS) +#define USB_EP4_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP4_TX_FIFO_EMPTY_LEN) - 1) << USB_EP4_TX_FIFO_EMPTY_POS)) +#define USB_EP4_TX_FIFO_FULL USB_EP4_TX_FIFO_FULL +#define USB_EP4_TX_FIFO_FULL_POS (15U) +#define USB_EP4_TX_FIFO_FULL_LEN (1U) +#define USB_EP4_TX_FIFO_FULL_MSK (((1U << USB_EP4_TX_FIFO_FULL_LEN) - 1) << USB_EP4_TX_FIFO_FULL_POS) +#define USB_EP4_TX_FIFO_FULL_UMSK (~(((1U << USB_EP4_TX_FIFO_FULL_LEN) - 1) << USB_EP4_TX_FIFO_FULL_POS)) +#define USB_EP4_RX_FIFO_CNT USB_EP4_RX_FIFO_CNT +#define USB_EP4_RX_FIFO_CNT_POS (16U) +#define USB_EP4_RX_FIFO_CNT_LEN (7U) +#define USB_EP4_RX_FIFO_CNT_MSK (((1U << USB_EP4_RX_FIFO_CNT_LEN) - 1) << USB_EP4_RX_FIFO_CNT_POS) +#define USB_EP4_RX_FIFO_CNT_UMSK (~(((1U << USB_EP4_RX_FIFO_CNT_LEN) - 1) << USB_EP4_RX_FIFO_CNT_POS)) +#define USB_EP4_RX_FIFO_EMPTY USB_EP4_RX_FIFO_EMPTY +#define USB_EP4_RX_FIFO_EMPTY_POS (30U) +#define USB_EP4_RX_FIFO_EMPTY_LEN (1U) +#define USB_EP4_RX_FIFO_EMPTY_MSK (((1U << USB_EP4_RX_FIFO_EMPTY_LEN) - 1) << USB_EP4_RX_FIFO_EMPTY_POS) +#define USB_EP4_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP4_RX_FIFO_EMPTY_LEN) - 1) << USB_EP4_RX_FIFO_EMPTY_POS)) +#define USB_EP4_RX_FIFO_FULL USB_EP4_RX_FIFO_FULL +#define USB_EP4_RX_FIFO_FULL_POS (31U) +#define USB_EP4_RX_FIFO_FULL_LEN (1U) +#define USB_EP4_RX_FIFO_FULL_MSK (((1U << USB_EP4_RX_FIFO_FULL_LEN) - 1) << USB_EP4_RX_FIFO_FULL_POS) +#define USB_EP4_RX_FIFO_FULL_UMSK (~(((1U << USB_EP4_RX_FIFO_FULL_LEN) - 1) << USB_EP4_RX_FIFO_FULL_POS)) + +/* 0x148 : ep4_tx_fifo_wdata */ +#define USB_EP4_TX_FIFO_WDATA_OFFSET (0x148) +#define USB_EP4_TX_FIFO_WDATA USB_EP4_TX_FIFO_WDATA +#define USB_EP4_TX_FIFO_WDATA_POS (0U) +#define USB_EP4_TX_FIFO_WDATA_LEN (8U) +#define USB_EP4_TX_FIFO_WDATA_MSK (((1U << USB_EP4_TX_FIFO_WDATA_LEN) - 1) << USB_EP4_TX_FIFO_WDATA_POS) +#define USB_EP4_TX_FIFO_WDATA_UMSK (~(((1U << USB_EP4_TX_FIFO_WDATA_LEN) - 1) << USB_EP4_TX_FIFO_WDATA_POS)) + +/* 0x14C : ep4_rx_fifo_rdata */ +#define USB_EP4_RX_FIFO_RDATA_OFFSET (0x14C) +#define USB_EP4_RX_FIFO_RDATA USB_EP4_RX_FIFO_RDATA +#define USB_EP4_RX_FIFO_RDATA_POS (0U) +#define USB_EP4_RX_FIFO_RDATA_LEN (8U) +#define USB_EP4_RX_FIFO_RDATA_MSK (((1U << USB_EP4_RX_FIFO_RDATA_LEN) - 1) << USB_EP4_RX_FIFO_RDATA_POS) +#define USB_EP4_RX_FIFO_RDATA_UMSK (~(((1U << USB_EP4_RX_FIFO_RDATA_LEN) - 1) << USB_EP4_RX_FIFO_RDATA_POS)) + +/* 0x150 : ep5_fifo_config */ +#define USB_EP5_FIFO_CONFIG_OFFSET (0x150) +#define USB_EP5_DMA_TX_EN USB_EP5_DMA_TX_EN +#define USB_EP5_DMA_TX_EN_POS (0U) +#define USB_EP5_DMA_TX_EN_LEN (1U) +#define USB_EP5_DMA_TX_EN_MSK (((1U << USB_EP5_DMA_TX_EN_LEN) - 1) << USB_EP5_DMA_TX_EN_POS) +#define USB_EP5_DMA_TX_EN_UMSK (~(((1U << USB_EP5_DMA_TX_EN_LEN) - 1) << USB_EP5_DMA_TX_EN_POS)) +#define USB_EP5_DMA_RX_EN USB_EP5_DMA_RX_EN +#define USB_EP5_DMA_RX_EN_POS (1U) +#define USB_EP5_DMA_RX_EN_LEN (1U) +#define USB_EP5_DMA_RX_EN_MSK (((1U << USB_EP5_DMA_RX_EN_LEN) - 1) << USB_EP5_DMA_RX_EN_POS) +#define USB_EP5_DMA_RX_EN_UMSK (~(((1U << USB_EP5_DMA_RX_EN_LEN) - 1) << USB_EP5_DMA_RX_EN_POS)) +#define USB_EP5_TX_FIFO_CLR USB_EP5_TX_FIFO_CLR +#define USB_EP5_TX_FIFO_CLR_POS (2U) +#define USB_EP5_TX_FIFO_CLR_LEN (1U) +#define USB_EP5_TX_FIFO_CLR_MSK (((1U << USB_EP5_TX_FIFO_CLR_LEN) - 1) << USB_EP5_TX_FIFO_CLR_POS) +#define USB_EP5_TX_FIFO_CLR_UMSK (~(((1U << USB_EP5_TX_FIFO_CLR_LEN) - 1) << USB_EP5_TX_FIFO_CLR_POS)) +#define USB_EP5_RX_FIFO_CLR USB_EP5_RX_FIFO_CLR +#define USB_EP5_RX_FIFO_CLR_POS (3U) +#define USB_EP5_RX_FIFO_CLR_LEN (1U) +#define USB_EP5_RX_FIFO_CLR_MSK (((1U << USB_EP5_RX_FIFO_CLR_LEN) - 1) << USB_EP5_RX_FIFO_CLR_POS) +#define USB_EP5_RX_FIFO_CLR_UMSK (~(((1U << USB_EP5_RX_FIFO_CLR_LEN) - 1) << USB_EP5_RX_FIFO_CLR_POS)) +#define USB_EP5_TX_FIFO_OVERFLOW USB_EP5_TX_FIFO_OVERFLOW +#define USB_EP5_TX_FIFO_OVERFLOW_POS (4U) +#define USB_EP5_TX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP5_TX_FIFO_OVERFLOW_MSK (((1U << USB_EP5_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_OVERFLOW_POS) +#define USB_EP5_TX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP5_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_OVERFLOW_POS)) +#define USB_EP5_TX_FIFO_UNDERFLOW USB_EP5_TX_FIFO_UNDERFLOW +#define USB_EP5_TX_FIFO_UNDERFLOW_POS (5U) +#define USB_EP5_TX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP5_TX_FIFO_UNDERFLOW_MSK (((1U << USB_EP5_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_UNDERFLOW_POS) +#define USB_EP5_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP5_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_UNDERFLOW_POS)) +#define USB_EP5_RX_FIFO_OVERFLOW USB_EP5_RX_FIFO_OVERFLOW +#define USB_EP5_RX_FIFO_OVERFLOW_POS (6U) +#define USB_EP5_RX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP5_RX_FIFO_OVERFLOW_MSK (((1U << USB_EP5_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_OVERFLOW_POS) +#define USB_EP5_RX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP5_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_OVERFLOW_POS)) +#define USB_EP5_RX_FIFO_UNDERFLOW USB_EP5_RX_FIFO_UNDERFLOW +#define USB_EP5_RX_FIFO_UNDERFLOW_POS (7U) +#define USB_EP5_RX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP5_RX_FIFO_UNDERFLOW_MSK (((1U << USB_EP5_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_UNDERFLOW_POS) +#define USB_EP5_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP5_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_UNDERFLOW_POS)) + +/* 0x154 : ep5_fifo_status */ +#define USB_EP5_FIFO_STATUS_OFFSET (0x154) +#define USB_EP5_TX_FIFO_CNT USB_EP5_TX_FIFO_CNT +#define USB_EP5_TX_FIFO_CNT_POS (0U) +#define USB_EP5_TX_FIFO_CNT_LEN (7U) +#define USB_EP5_TX_FIFO_CNT_MSK (((1U << USB_EP5_TX_FIFO_CNT_LEN) - 1) << USB_EP5_TX_FIFO_CNT_POS) +#define USB_EP5_TX_FIFO_CNT_UMSK (~(((1U << USB_EP5_TX_FIFO_CNT_LEN) - 1) << USB_EP5_TX_FIFO_CNT_POS)) +#define USB_EP5_TX_FIFO_EMPTY USB_EP5_TX_FIFO_EMPTY +#define USB_EP5_TX_FIFO_EMPTY_POS (14U) +#define USB_EP5_TX_FIFO_EMPTY_LEN (1U) +#define USB_EP5_TX_FIFO_EMPTY_MSK (((1U << USB_EP5_TX_FIFO_EMPTY_LEN) - 1) << USB_EP5_TX_FIFO_EMPTY_POS) +#define USB_EP5_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP5_TX_FIFO_EMPTY_LEN) - 1) << USB_EP5_TX_FIFO_EMPTY_POS)) +#define USB_EP5_TX_FIFO_FULL USB_EP5_TX_FIFO_FULL +#define USB_EP5_TX_FIFO_FULL_POS (15U) +#define USB_EP5_TX_FIFO_FULL_LEN (1U) +#define USB_EP5_TX_FIFO_FULL_MSK (((1U << USB_EP5_TX_FIFO_FULL_LEN) - 1) << USB_EP5_TX_FIFO_FULL_POS) +#define USB_EP5_TX_FIFO_FULL_UMSK (~(((1U << USB_EP5_TX_FIFO_FULL_LEN) - 1) << USB_EP5_TX_FIFO_FULL_POS)) +#define USB_EP5_RX_FIFO_CNT USB_EP5_RX_FIFO_CNT +#define USB_EP5_RX_FIFO_CNT_POS (16U) +#define USB_EP5_RX_FIFO_CNT_LEN (7U) +#define USB_EP5_RX_FIFO_CNT_MSK (((1U << USB_EP5_RX_FIFO_CNT_LEN) - 1) << USB_EP5_RX_FIFO_CNT_POS) +#define USB_EP5_RX_FIFO_CNT_UMSK (~(((1U << USB_EP5_RX_FIFO_CNT_LEN) - 1) << USB_EP5_RX_FIFO_CNT_POS)) +#define USB_EP5_RX_FIFO_EMPTY USB_EP5_RX_FIFO_EMPTY +#define USB_EP5_RX_FIFO_EMPTY_POS (30U) +#define USB_EP5_RX_FIFO_EMPTY_LEN (1U) +#define USB_EP5_RX_FIFO_EMPTY_MSK (((1U << USB_EP5_RX_FIFO_EMPTY_LEN) - 1) << USB_EP5_RX_FIFO_EMPTY_POS) +#define USB_EP5_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP5_RX_FIFO_EMPTY_LEN) - 1) << USB_EP5_RX_FIFO_EMPTY_POS)) +#define USB_EP5_RX_FIFO_FULL USB_EP5_RX_FIFO_FULL +#define USB_EP5_RX_FIFO_FULL_POS (31U) +#define USB_EP5_RX_FIFO_FULL_LEN (1U) +#define USB_EP5_RX_FIFO_FULL_MSK (((1U << USB_EP5_RX_FIFO_FULL_LEN) - 1) << USB_EP5_RX_FIFO_FULL_POS) +#define USB_EP5_RX_FIFO_FULL_UMSK (~(((1U << USB_EP5_RX_FIFO_FULL_LEN) - 1) << USB_EP5_RX_FIFO_FULL_POS)) + +/* 0x158 : ep5_tx_fifo_wdata */ +#define USB_EP5_TX_FIFO_WDATA_OFFSET (0x158) +#define USB_EP5_TX_FIFO_WDATA USB_EP5_TX_FIFO_WDATA +#define USB_EP5_TX_FIFO_WDATA_POS (0U) +#define USB_EP5_TX_FIFO_WDATA_LEN (8U) +#define USB_EP5_TX_FIFO_WDATA_MSK (((1U << USB_EP5_TX_FIFO_WDATA_LEN) - 1) << USB_EP5_TX_FIFO_WDATA_POS) +#define USB_EP5_TX_FIFO_WDATA_UMSK (~(((1U << USB_EP5_TX_FIFO_WDATA_LEN) - 1) << USB_EP5_TX_FIFO_WDATA_POS)) + +/* 0x15C : ep5_rx_fifo_rdata */ +#define USB_EP5_RX_FIFO_RDATA_OFFSET (0x15C) +#define USB_EP5_RX_FIFO_RDATA USB_EP5_RX_FIFO_RDATA +#define USB_EP5_RX_FIFO_RDATA_POS (0U) +#define USB_EP5_RX_FIFO_RDATA_LEN (8U) +#define USB_EP5_RX_FIFO_RDATA_MSK (((1U << USB_EP5_RX_FIFO_RDATA_LEN) - 1) << USB_EP5_RX_FIFO_RDATA_POS) +#define USB_EP5_RX_FIFO_RDATA_UMSK (~(((1U << USB_EP5_RX_FIFO_RDATA_LEN) - 1) << USB_EP5_RX_FIFO_RDATA_POS)) + +/* 0x160 : ep6_fifo_config */ +#define USB_EP6_FIFO_CONFIG_OFFSET (0x160) +#define USB_EP6_DMA_TX_EN USB_EP6_DMA_TX_EN +#define USB_EP6_DMA_TX_EN_POS (0U) +#define USB_EP6_DMA_TX_EN_LEN (1U) +#define USB_EP6_DMA_TX_EN_MSK (((1U << USB_EP6_DMA_TX_EN_LEN) - 1) << USB_EP6_DMA_TX_EN_POS) +#define USB_EP6_DMA_TX_EN_UMSK (~(((1U << USB_EP6_DMA_TX_EN_LEN) - 1) << USB_EP6_DMA_TX_EN_POS)) +#define USB_EP6_DMA_RX_EN USB_EP6_DMA_RX_EN +#define USB_EP6_DMA_RX_EN_POS (1U) +#define USB_EP6_DMA_RX_EN_LEN (1U) +#define USB_EP6_DMA_RX_EN_MSK (((1U << USB_EP6_DMA_RX_EN_LEN) - 1) << USB_EP6_DMA_RX_EN_POS) +#define USB_EP6_DMA_RX_EN_UMSK (~(((1U << USB_EP6_DMA_RX_EN_LEN) - 1) << USB_EP6_DMA_RX_EN_POS)) +#define USB_EP6_TX_FIFO_CLR USB_EP6_TX_FIFO_CLR +#define USB_EP6_TX_FIFO_CLR_POS (2U) +#define USB_EP6_TX_FIFO_CLR_LEN (1U) +#define USB_EP6_TX_FIFO_CLR_MSK (((1U << USB_EP6_TX_FIFO_CLR_LEN) - 1) << USB_EP6_TX_FIFO_CLR_POS) +#define USB_EP6_TX_FIFO_CLR_UMSK (~(((1U << USB_EP6_TX_FIFO_CLR_LEN) - 1) << USB_EP6_TX_FIFO_CLR_POS)) +#define USB_EP6_RX_FIFO_CLR USB_EP6_RX_FIFO_CLR +#define USB_EP6_RX_FIFO_CLR_POS (3U) +#define USB_EP6_RX_FIFO_CLR_LEN (1U) +#define USB_EP6_RX_FIFO_CLR_MSK (((1U << USB_EP6_RX_FIFO_CLR_LEN) - 1) << USB_EP6_RX_FIFO_CLR_POS) +#define USB_EP6_RX_FIFO_CLR_UMSK (~(((1U << USB_EP6_RX_FIFO_CLR_LEN) - 1) << USB_EP6_RX_FIFO_CLR_POS)) +#define USB_EP6_TX_FIFO_OVERFLOW USB_EP6_TX_FIFO_OVERFLOW +#define USB_EP6_TX_FIFO_OVERFLOW_POS (4U) +#define USB_EP6_TX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP6_TX_FIFO_OVERFLOW_MSK (((1U << USB_EP6_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_OVERFLOW_POS) +#define USB_EP6_TX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP6_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_OVERFLOW_POS)) +#define USB_EP6_TX_FIFO_UNDERFLOW USB_EP6_TX_FIFO_UNDERFLOW +#define USB_EP6_TX_FIFO_UNDERFLOW_POS (5U) +#define USB_EP6_TX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP6_TX_FIFO_UNDERFLOW_MSK (((1U << USB_EP6_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_UNDERFLOW_POS) +#define USB_EP6_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP6_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_UNDERFLOW_POS)) +#define USB_EP6_RX_FIFO_OVERFLOW USB_EP6_RX_FIFO_OVERFLOW +#define USB_EP6_RX_FIFO_OVERFLOW_POS (6U) +#define USB_EP6_RX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP6_RX_FIFO_OVERFLOW_MSK (((1U << USB_EP6_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_OVERFLOW_POS) +#define USB_EP6_RX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP6_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_OVERFLOW_POS)) +#define USB_EP6_RX_FIFO_UNDERFLOW USB_EP6_RX_FIFO_UNDERFLOW +#define USB_EP6_RX_FIFO_UNDERFLOW_POS (7U) +#define USB_EP6_RX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP6_RX_FIFO_UNDERFLOW_MSK (((1U << USB_EP6_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_UNDERFLOW_POS) +#define USB_EP6_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP6_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_UNDERFLOW_POS)) + +/* 0x164 : ep6_fifo_status */ +#define USB_EP6_FIFO_STATUS_OFFSET (0x164) +#define USB_EP6_TX_FIFO_CNT USB_EP6_TX_FIFO_CNT +#define USB_EP6_TX_FIFO_CNT_POS (0U) +#define USB_EP6_TX_FIFO_CNT_LEN (7U) +#define USB_EP6_TX_FIFO_CNT_MSK (((1U << USB_EP6_TX_FIFO_CNT_LEN) - 1) << USB_EP6_TX_FIFO_CNT_POS) +#define USB_EP6_TX_FIFO_CNT_UMSK (~(((1U << USB_EP6_TX_FIFO_CNT_LEN) - 1) << USB_EP6_TX_FIFO_CNT_POS)) +#define USB_EP6_TX_FIFO_EMPTY USB_EP6_TX_FIFO_EMPTY +#define USB_EP6_TX_FIFO_EMPTY_POS (14U) +#define USB_EP6_TX_FIFO_EMPTY_LEN (1U) +#define USB_EP6_TX_FIFO_EMPTY_MSK (((1U << USB_EP6_TX_FIFO_EMPTY_LEN) - 1) << USB_EP6_TX_FIFO_EMPTY_POS) +#define USB_EP6_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP6_TX_FIFO_EMPTY_LEN) - 1) << USB_EP6_TX_FIFO_EMPTY_POS)) +#define USB_EP6_TX_FIFO_FULL USB_EP6_TX_FIFO_FULL +#define USB_EP6_TX_FIFO_FULL_POS (15U) +#define USB_EP6_TX_FIFO_FULL_LEN (1U) +#define USB_EP6_TX_FIFO_FULL_MSK (((1U << USB_EP6_TX_FIFO_FULL_LEN) - 1) << USB_EP6_TX_FIFO_FULL_POS) +#define USB_EP6_TX_FIFO_FULL_UMSK (~(((1U << USB_EP6_TX_FIFO_FULL_LEN) - 1) << USB_EP6_TX_FIFO_FULL_POS)) +#define USB_EP6_RX_FIFO_CNT USB_EP6_RX_FIFO_CNT +#define USB_EP6_RX_FIFO_CNT_POS (16U) +#define USB_EP6_RX_FIFO_CNT_LEN (7U) +#define USB_EP6_RX_FIFO_CNT_MSK (((1U << USB_EP6_RX_FIFO_CNT_LEN) - 1) << USB_EP6_RX_FIFO_CNT_POS) +#define USB_EP6_RX_FIFO_CNT_UMSK (~(((1U << USB_EP6_RX_FIFO_CNT_LEN) - 1) << USB_EP6_RX_FIFO_CNT_POS)) +#define USB_EP6_RX_FIFO_EMPTY USB_EP6_RX_FIFO_EMPTY +#define USB_EP6_RX_FIFO_EMPTY_POS (30U) +#define USB_EP6_RX_FIFO_EMPTY_LEN (1U) +#define USB_EP6_RX_FIFO_EMPTY_MSK (((1U << USB_EP6_RX_FIFO_EMPTY_LEN) - 1) << USB_EP6_RX_FIFO_EMPTY_POS) +#define USB_EP6_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP6_RX_FIFO_EMPTY_LEN) - 1) << USB_EP6_RX_FIFO_EMPTY_POS)) +#define USB_EP6_RX_FIFO_FULL USB_EP6_RX_FIFO_FULL +#define USB_EP6_RX_FIFO_FULL_POS (31U) +#define USB_EP6_RX_FIFO_FULL_LEN (1U) +#define USB_EP6_RX_FIFO_FULL_MSK (((1U << USB_EP6_RX_FIFO_FULL_LEN) - 1) << USB_EP6_RX_FIFO_FULL_POS) +#define USB_EP6_RX_FIFO_FULL_UMSK (~(((1U << USB_EP6_RX_FIFO_FULL_LEN) - 1) << USB_EP6_RX_FIFO_FULL_POS)) + +/* 0x168 : ep6_tx_fifo_wdata */ +#define USB_EP6_TX_FIFO_WDATA_OFFSET (0x168) +#define USB_EP6_TX_FIFO_WDATA USB_EP6_TX_FIFO_WDATA +#define USB_EP6_TX_FIFO_WDATA_POS (0U) +#define USB_EP6_TX_FIFO_WDATA_LEN (8U) +#define USB_EP6_TX_FIFO_WDATA_MSK (((1U << USB_EP6_TX_FIFO_WDATA_LEN) - 1) << USB_EP6_TX_FIFO_WDATA_POS) +#define USB_EP6_TX_FIFO_WDATA_UMSK (~(((1U << USB_EP6_TX_FIFO_WDATA_LEN) - 1) << USB_EP6_TX_FIFO_WDATA_POS)) + +/* 0x16C : ep6_rx_fifo_rdata */ +#define USB_EP6_RX_FIFO_RDATA_OFFSET (0x16C) +#define USB_EP6_RX_FIFO_RDATA USB_EP6_RX_FIFO_RDATA +#define USB_EP6_RX_FIFO_RDATA_POS (0U) +#define USB_EP6_RX_FIFO_RDATA_LEN (8U) +#define USB_EP6_RX_FIFO_RDATA_MSK (((1U << USB_EP6_RX_FIFO_RDATA_LEN) - 1) << USB_EP6_RX_FIFO_RDATA_POS) +#define USB_EP6_RX_FIFO_RDATA_UMSK (~(((1U << USB_EP6_RX_FIFO_RDATA_LEN) - 1) << USB_EP6_RX_FIFO_RDATA_POS)) + +/* 0x170 : ep7_fifo_config */ +#define USB_EP7_FIFO_CONFIG_OFFSET (0x170) +#define USB_EP7_DMA_TX_EN USB_EP7_DMA_TX_EN +#define USB_EP7_DMA_TX_EN_POS (0U) +#define USB_EP7_DMA_TX_EN_LEN (1U) +#define USB_EP7_DMA_TX_EN_MSK (((1U << USB_EP7_DMA_TX_EN_LEN) - 1) << USB_EP7_DMA_TX_EN_POS) +#define USB_EP7_DMA_TX_EN_UMSK (~(((1U << USB_EP7_DMA_TX_EN_LEN) - 1) << USB_EP7_DMA_TX_EN_POS)) +#define USB_EP7_DMA_RX_EN USB_EP7_DMA_RX_EN +#define USB_EP7_DMA_RX_EN_POS (1U) +#define USB_EP7_DMA_RX_EN_LEN (1U) +#define USB_EP7_DMA_RX_EN_MSK (((1U << USB_EP7_DMA_RX_EN_LEN) - 1) << USB_EP7_DMA_RX_EN_POS) +#define USB_EP7_DMA_RX_EN_UMSK (~(((1U << USB_EP7_DMA_RX_EN_LEN) - 1) << USB_EP7_DMA_RX_EN_POS)) +#define USB_EP7_TX_FIFO_CLR USB_EP7_TX_FIFO_CLR +#define USB_EP7_TX_FIFO_CLR_POS (2U) +#define USB_EP7_TX_FIFO_CLR_LEN (1U) +#define USB_EP7_TX_FIFO_CLR_MSK (((1U << USB_EP7_TX_FIFO_CLR_LEN) - 1) << USB_EP7_TX_FIFO_CLR_POS) +#define USB_EP7_TX_FIFO_CLR_UMSK (~(((1U << USB_EP7_TX_FIFO_CLR_LEN) - 1) << USB_EP7_TX_FIFO_CLR_POS)) +#define USB_EP7_RX_FIFO_CLR USB_EP7_RX_FIFO_CLR +#define USB_EP7_RX_FIFO_CLR_POS (3U) +#define USB_EP7_RX_FIFO_CLR_LEN (1U) +#define USB_EP7_RX_FIFO_CLR_MSK (((1U << USB_EP7_RX_FIFO_CLR_LEN) - 1) << USB_EP7_RX_FIFO_CLR_POS) +#define USB_EP7_RX_FIFO_CLR_UMSK (~(((1U << USB_EP7_RX_FIFO_CLR_LEN) - 1) << USB_EP7_RX_FIFO_CLR_POS)) +#define USB_EP7_TX_FIFO_OVERFLOW USB_EP7_TX_FIFO_OVERFLOW +#define USB_EP7_TX_FIFO_OVERFLOW_POS (4U) +#define USB_EP7_TX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP7_TX_FIFO_OVERFLOW_MSK (((1U << USB_EP7_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_OVERFLOW_POS) +#define USB_EP7_TX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP7_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_OVERFLOW_POS)) +#define USB_EP7_TX_FIFO_UNDERFLOW USB_EP7_TX_FIFO_UNDERFLOW +#define USB_EP7_TX_FIFO_UNDERFLOW_POS (5U) +#define USB_EP7_TX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP7_TX_FIFO_UNDERFLOW_MSK (((1U << USB_EP7_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_UNDERFLOW_POS) +#define USB_EP7_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP7_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_UNDERFLOW_POS)) +#define USB_EP7_RX_FIFO_OVERFLOW USB_EP7_RX_FIFO_OVERFLOW +#define USB_EP7_RX_FIFO_OVERFLOW_POS (6U) +#define USB_EP7_RX_FIFO_OVERFLOW_LEN (1U) +#define USB_EP7_RX_FIFO_OVERFLOW_MSK (((1U << USB_EP7_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_OVERFLOW_POS) +#define USB_EP7_RX_FIFO_OVERFLOW_UMSK (~(((1U << USB_EP7_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_OVERFLOW_POS)) +#define USB_EP7_RX_FIFO_UNDERFLOW USB_EP7_RX_FIFO_UNDERFLOW +#define USB_EP7_RX_FIFO_UNDERFLOW_POS (7U) +#define USB_EP7_RX_FIFO_UNDERFLOW_LEN (1U) +#define USB_EP7_RX_FIFO_UNDERFLOW_MSK (((1U << USB_EP7_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_UNDERFLOW_POS) +#define USB_EP7_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP7_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_UNDERFLOW_POS)) + +/* 0x174 : ep7_fifo_status */ +#define USB_EP7_FIFO_STATUS_OFFSET (0x174) +#define USB_EP7_TX_FIFO_CNT USB_EP7_TX_FIFO_CNT +#define USB_EP7_TX_FIFO_CNT_POS (0U) +#define USB_EP7_TX_FIFO_CNT_LEN (7U) +#define USB_EP7_TX_FIFO_CNT_MSK (((1U << USB_EP7_TX_FIFO_CNT_LEN) - 1) << USB_EP7_TX_FIFO_CNT_POS) +#define USB_EP7_TX_FIFO_CNT_UMSK (~(((1U << USB_EP7_TX_FIFO_CNT_LEN) - 1) << USB_EP7_TX_FIFO_CNT_POS)) +#define USB_EP7_TX_FIFO_EMPTY USB_EP7_TX_FIFO_EMPTY +#define USB_EP7_TX_FIFO_EMPTY_POS (14U) +#define USB_EP7_TX_FIFO_EMPTY_LEN (1U) +#define USB_EP7_TX_FIFO_EMPTY_MSK (((1U << USB_EP7_TX_FIFO_EMPTY_LEN) - 1) << USB_EP7_TX_FIFO_EMPTY_POS) +#define USB_EP7_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP7_TX_FIFO_EMPTY_LEN) - 1) << USB_EP7_TX_FIFO_EMPTY_POS)) +#define USB_EP7_TX_FIFO_FULL USB_EP7_TX_FIFO_FULL +#define USB_EP7_TX_FIFO_FULL_POS (15U) +#define USB_EP7_TX_FIFO_FULL_LEN (1U) +#define USB_EP7_TX_FIFO_FULL_MSK (((1U << USB_EP7_TX_FIFO_FULL_LEN) - 1) << USB_EP7_TX_FIFO_FULL_POS) +#define USB_EP7_TX_FIFO_FULL_UMSK (~(((1U << USB_EP7_TX_FIFO_FULL_LEN) - 1) << USB_EP7_TX_FIFO_FULL_POS)) +#define USB_EP7_RX_FIFO_CNT USB_EP7_RX_FIFO_CNT +#define USB_EP7_RX_FIFO_CNT_POS (16U) +#define USB_EP7_RX_FIFO_CNT_LEN (7U) +#define USB_EP7_RX_FIFO_CNT_MSK (((1U << USB_EP7_RX_FIFO_CNT_LEN) - 1) << USB_EP7_RX_FIFO_CNT_POS) +#define USB_EP7_RX_FIFO_CNT_UMSK (~(((1U << USB_EP7_RX_FIFO_CNT_LEN) - 1) << USB_EP7_RX_FIFO_CNT_POS)) +#define USB_EP7_RX_FIFO_EMPTY USB_EP7_RX_FIFO_EMPTY +#define USB_EP7_RX_FIFO_EMPTY_POS (30U) +#define USB_EP7_RX_FIFO_EMPTY_LEN (1U) +#define USB_EP7_RX_FIFO_EMPTY_MSK (((1U << USB_EP7_RX_FIFO_EMPTY_LEN) - 1) << USB_EP7_RX_FIFO_EMPTY_POS) +#define USB_EP7_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP7_RX_FIFO_EMPTY_LEN) - 1) << USB_EP7_RX_FIFO_EMPTY_POS)) +#define USB_EP7_RX_FIFO_FULL USB_EP7_RX_FIFO_FULL +#define USB_EP7_RX_FIFO_FULL_POS (31U) +#define USB_EP7_RX_FIFO_FULL_LEN (1U) +#define USB_EP7_RX_FIFO_FULL_MSK (((1U << USB_EP7_RX_FIFO_FULL_LEN) - 1) << USB_EP7_RX_FIFO_FULL_POS) +#define USB_EP7_RX_FIFO_FULL_UMSK (~(((1U << USB_EP7_RX_FIFO_FULL_LEN) - 1) << USB_EP7_RX_FIFO_FULL_POS)) + +/* 0x178 : ep7_tx_fifo_wdata */ +#define USB_EP7_TX_FIFO_WDATA_OFFSET (0x178) +#define USB_EP7_TX_FIFO_WDATA USB_EP7_TX_FIFO_WDATA +#define USB_EP7_TX_FIFO_WDATA_POS (0U) +#define USB_EP7_TX_FIFO_WDATA_LEN (8U) +#define USB_EP7_TX_FIFO_WDATA_MSK (((1U << USB_EP7_TX_FIFO_WDATA_LEN) - 1) << USB_EP7_TX_FIFO_WDATA_POS) +#define USB_EP7_TX_FIFO_WDATA_UMSK (~(((1U << USB_EP7_TX_FIFO_WDATA_LEN) - 1) << USB_EP7_TX_FIFO_WDATA_POS)) + +/* 0x17C : ep7_rx_fifo_rdata */ +#define USB_EP7_RX_FIFO_RDATA_OFFSET (0x17C) +#define USB_EP7_RX_FIFO_RDATA USB_EP7_RX_FIFO_RDATA +#define USB_EP7_RX_FIFO_RDATA_POS (0U) +#define USB_EP7_RX_FIFO_RDATA_LEN (8U) +#define USB_EP7_RX_FIFO_RDATA_MSK (((1U << USB_EP7_RX_FIFO_RDATA_LEN) - 1) << USB_EP7_RX_FIFO_RDATA_POS) +#define USB_EP7_RX_FIFO_RDATA_UMSK (~(((1U << USB_EP7_RX_FIFO_RDATA_LEN) - 1) << USB_EP7_RX_FIFO_RDATA_POS)) + +/* 0x1F0 : rsvd_0 */ +#define USB_RSVD_0_OFFSET (0x1F0) + +/* 0x1F4 : rsvd_1 */ +#define USB_RSVD_1_OFFSET (0x1F4) + +/* 0x1FC : xcvr_if_config */ +#define USB_XCVR_IF_CONFIG_OFFSET (0x1FC) +#define USB_CR_XCVR_FORCE_TX_EN USB_CR_XCVR_FORCE_TX_EN +#define USB_CR_XCVR_FORCE_TX_EN_POS (0U) +#define USB_CR_XCVR_FORCE_TX_EN_LEN (1U) +#define USB_CR_XCVR_FORCE_TX_EN_MSK (((1U << USB_CR_XCVR_FORCE_TX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_EN_POS) +#define USB_CR_XCVR_FORCE_TX_EN_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_EN_POS)) +#define USB_CR_XCVR_FORCE_TX_OE USB_CR_XCVR_FORCE_TX_OE +#define USB_CR_XCVR_FORCE_TX_OE_POS (1U) +#define USB_CR_XCVR_FORCE_TX_OE_LEN (1U) +#define USB_CR_XCVR_FORCE_TX_OE_MSK (((1U << USB_CR_XCVR_FORCE_TX_OE_LEN) - 1) << USB_CR_XCVR_FORCE_TX_OE_POS) +#define USB_CR_XCVR_FORCE_TX_OE_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_OE_LEN) - 1) << USB_CR_XCVR_FORCE_TX_OE_POS)) +#define USB_CR_XCVR_FORCE_TX_DP USB_CR_XCVR_FORCE_TX_DP +#define USB_CR_XCVR_FORCE_TX_DP_POS (2U) +#define USB_CR_XCVR_FORCE_TX_DP_LEN (1U) +#define USB_CR_XCVR_FORCE_TX_DP_MSK (((1U << USB_CR_XCVR_FORCE_TX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DP_POS) +#define USB_CR_XCVR_FORCE_TX_DP_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DP_POS)) +#define USB_CR_XCVR_FORCE_TX_DN USB_CR_XCVR_FORCE_TX_DN +#define USB_CR_XCVR_FORCE_TX_DN_POS (3U) +#define USB_CR_XCVR_FORCE_TX_DN_LEN (1U) +#define USB_CR_XCVR_FORCE_TX_DN_MSK (((1U << USB_CR_XCVR_FORCE_TX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DN_POS) +#define USB_CR_XCVR_FORCE_TX_DN_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DN_POS)) +#define USB_CR_XCVR_FORCE_RX_EN USB_CR_XCVR_FORCE_RX_EN +#define USB_CR_XCVR_FORCE_RX_EN_POS (4U) +#define USB_CR_XCVR_FORCE_RX_EN_LEN (1U) +#define USB_CR_XCVR_FORCE_RX_EN_MSK (((1U << USB_CR_XCVR_FORCE_RX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_EN_POS) +#define USB_CR_XCVR_FORCE_RX_EN_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_EN_POS)) +#define USB_CR_XCVR_FORCE_RX_D USB_CR_XCVR_FORCE_RX_D +#define USB_CR_XCVR_FORCE_RX_D_POS (5U) +#define USB_CR_XCVR_FORCE_RX_D_LEN (1U) +#define USB_CR_XCVR_FORCE_RX_D_MSK (((1U << USB_CR_XCVR_FORCE_RX_D_LEN) - 1) << USB_CR_XCVR_FORCE_RX_D_POS) +#define USB_CR_XCVR_FORCE_RX_D_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_D_LEN) - 1) << USB_CR_XCVR_FORCE_RX_D_POS)) +#define USB_CR_XCVR_FORCE_RX_DP USB_CR_XCVR_FORCE_RX_DP +#define USB_CR_XCVR_FORCE_RX_DP_POS (6U) +#define USB_CR_XCVR_FORCE_RX_DP_LEN (1U) +#define USB_CR_XCVR_FORCE_RX_DP_MSK (((1U << USB_CR_XCVR_FORCE_RX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DP_POS) +#define USB_CR_XCVR_FORCE_RX_DP_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DP_POS)) +#define USB_CR_XCVR_FORCE_RX_DN USB_CR_XCVR_FORCE_RX_DN +#define USB_CR_XCVR_FORCE_RX_DN_POS (7U) +#define USB_CR_XCVR_FORCE_RX_DN_LEN (1U) +#define USB_CR_XCVR_FORCE_RX_DN_MSK (((1U << USB_CR_XCVR_FORCE_RX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DN_POS) +#define USB_CR_XCVR_FORCE_RX_DN_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DN_POS)) +#define USB_CR_XCVR_OM_RX_SEL USB_CR_XCVR_OM_RX_SEL +#define USB_CR_XCVR_OM_RX_SEL_POS (8U) +#define USB_CR_XCVR_OM_RX_SEL_LEN (1U) +#define USB_CR_XCVR_OM_RX_SEL_MSK (((1U << USB_CR_XCVR_OM_RX_SEL_LEN) - 1) << USB_CR_XCVR_OM_RX_SEL_POS) +#define USB_CR_XCVR_OM_RX_SEL_UMSK (~(((1U << USB_CR_XCVR_OM_RX_SEL_LEN) - 1) << USB_CR_XCVR_OM_RX_SEL_POS)) +#define USB_CR_XCVR_OM_RX_D USB_CR_XCVR_OM_RX_D +#define USB_CR_XCVR_OM_RX_D_POS (9U) +#define USB_CR_XCVR_OM_RX_D_LEN (1U) +#define USB_CR_XCVR_OM_RX_D_MSK (((1U << USB_CR_XCVR_OM_RX_D_LEN) - 1) << USB_CR_XCVR_OM_RX_D_POS) +#define USB_CR_XCVR_OM_RX_D_UMSK (~(((1U << USB_CR_XCVR_OM_RX_D_LEN) - 1) << USB_CR_XCVR_OM_RX_D_POS)) +#define USB_CR_XCVR_OM_RX_DP USB_CR_XCVR_OM_RX_DP +#define USB_CR_XCVR_OM_RX_DP_POS (10U) +#define USB_CR_XCVR_OM_RX_DP_LEN (1U) +#define USB_CR_XCVR_OM_RX_DP_MSK (((1U << USB_CR_XCVR_OM_RX_DP_LEN) - 1) << USB_CR_XCVR_OM_RX_DP_POS) +#define USB_CR_XCVR_OM_RX_DP_UMSK (~(((1U << USB_CR_XCVR_OM_RX_DP_LEN) - 1) << USB_CR_XCVR_OM_RX_DP_POS)) +#define USB_CR_XCVR_OM_RX_DN USB_CR_XCVR_OM_RX_DN +#define USB_CR_XCVR_OM_RX_DN_POS (11U) +#define USB_CR_XCVR_OM_RX_DN_LEN (1U) +#define USB_CR_XCVR_OM_RX_DN_MSK (((1U << USB_CR_XCVR_OM_RX_DN_LEN) - 1) << USB_CR_XCVR_OM_RX_DN_POS) +#define USB_CR_XCVR_OM_RX_DN_UMSK (~(((1U << USB_CR_XCVR_OM_RX_DN_LEN) - 1) << USB_CR_XCVR_OM_RX_DN_POS)) +#define USB_STS_VBUS_DET USB_STS_VBUS_DET +#define USB_STS_VBUS_DET_POS (31U) +#define USB_STS_VBUS_DET_LEN (1U) +#define USB_STS_VBUS_DET_MSK (((1U << USB_STS_VBUS_DET_LEN) - 1) << USB_STS_VBUS_DET_POS) +#define USB_STS_VBUS_DET_UMSK (~(((1U << USB_STS_VBUS_DET_LEN) - 1) << USB_STS_VBUS_DET_POS)) + +struct usb_reg { + /* 0x0 : usb_config */ + union { + struct + { + uint32_t cr_usb_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t cr_usb_rom_dct_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t cr_usb_ep0_sw_ctrl : 1; /* [ 8], r/w, 0x0 */ + uint32_t cr_usb_ep0_sw_addr : 7; /* [15: 9], r/w, 0x0 */ + uint32_t cr_usb_ep0_sw_size : 8; /* [23:16], r/w, 0x0 */ + uint32_t cr_usb_ep0_sw_stall : 1; /* [ 24], w1c, 0x0 */ + uint32_t cr_usb_ep0_sw_nack_in : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_usb_ep0_sw_nack_out : 1; /* [ 26], r/w, 0x0 */ + uint32_t cr_usb_ep0_sw_rdy : 1; /* [ 27], w1c, 0x0 */ + uint32_t sts_usb_ep0_sw_rdy : 1; /* [ 28], r, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } usb_config; + + /* 0x4 : usb_lpm_config */ + union { + struct + { + uint32_t cr_lpm_en : 1; /* [ 0], w1c, 0x0 */ + uint32_t cr_lpm_resp_upd : 1; /* [ 1], w1c, 0x0 */ + uint32_t cr_lpm_resp : 2; /* [ 3: 2], r/w, 0x2 */ + uint32_t reserved_4_19 : 16; /* [19: 4], rsvd, 0x0 */ + uint32_t sts_lpm_attr : 11; /* [30:20], r, 0x0 */ + uint32_t sts_lpm : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } usb_lpm_config; + + /* 0x8 : usb_resume_config */ + union { + struct + { + uint32_t cr_res_width : 11; /* [10: 0], r/w, 0x1a */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t cr_res_trig : 1; /* [ 12], w1c, 0x0 */ + uint32_t reserved_13_30 : 18; /* [30:13], rsvd, 0x0 */ + uint32_t cr_res_force : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } usb_resume_config; + + /* 0xc reserved */ + uint8_t RESERVED0xc[4]; + + /* 0x10 : usb_setup_data_0 */ + union { + struct + { + uint32_t sts_setup_data_b0 : 8; /* [ 7: 0], r, 0x0 */ + uint32_t sts_setup_data_b1 : 8; /* [15: 8], r, 0x0 */ + uint32_t sts_setup_data_b2 : 8; /* [23:16], r, 0x0 */ + uint32_t sts_setup_data_b3 : 8; /* [31:24], r, 0x0 */ + } BF; + uint32_t WORD; + } usb_setup_data_0; + + /* 0x14 : usb_setup_data_1 */ + union { + struct + { + uint32_t sts_setup_data_b4 : 8; /* [ 7: 0], r, 0x0 */ + uint32_t sts_setup_data_b5 : 8; /* [15: 8], r, 0x0 */ + uint32_t sts_setup_data_b6 : 8; /* [23:16], r, 0x0 */ + uint32_t sts_setup_data_b7 : 8; /* [31:24], r, 0x0 */ + } BF; + uint32_t WORD; + } usb_setup_data_1; + + /* 0x18 : usb_frame_no */ + union { + struct + { + uint32_t sts_frame_no : 11; /* [10: 0], r, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t sts_pid : 4; /* [15:12], r, 0x0 */ + uint32_t sts_ep_no : 4; /* [19:16], r, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } usb_frame_no; + + /* 0x1C : usb_error */ + union { + struct + { + uint32_t utmi_rx_err : 1; /* [ 0], r, 0x0 */ + uint32_t xfer_to_err : 1; /* [ 1], r, 0x0 */ + uint32_t ivld_ep_err : 1; /* [ 2], r, 0x0 */ + uint32_t pid_seq_err : 1; /* [ 3], r, 0x0 */ + uint32_t pid_cks_err : 1; /* [ 4], r, 0x0 */ + uint32_t crc5_err : 1; /* [ 5], r, 0x0 */ + uint32_t crc16_err : 1; /* [ 6], r, 0x0 */ + uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } usb_error; + + /* 0x20 : USB interrupt enable */ + union { + struct + { + uint32_t cr_sof_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_usb_reset_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_vbus_tgl_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_get_dct_cmd_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t cr_ep0_setup_cmd_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t cr_ep0_setup_done_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t cr_ep0_in_cmd_en : 1; /* [ 6], r/w, 0x1 */ + uint32_t cr_ep0_in_done_en : 1; /* [ 7], r/w, 0x1 */ + uint32_t cr_ep0_out_cmd_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_ep0_out_done_en : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_ep1_cmd_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_ep1_done_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_ep2_cmd_en : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_ep2_done_en : 1; /* [ 13], r/w, 0x1 */ + uint32_t cr_ep3_cmd_en : 1; /* [ 14], r/w, 0x1 */ + uint32_t cr_ep3_done_en : 1; /* [ 15], r/w, 0x1 */ + uint32_t cr_ep4_cmd_en : 1; /* [ 16], r/w, 0x1 */ + uint32_t cr_ep4_done_en : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep5_cmd_en : 1; /* [ 18], r/w, 0x1 */ + uint32_t cr_ep5_done_en : 1; /* [ 19], r/w, 0x1 */ + uint32_t cr_ep6_cmd_en : 1; /* [ 20], r/w, 0x1 */ + uint32_t cr_ep6_done_en : 1; /* [ 21], r/w, 0x1 */ + uint32_t cr_ep7_cmd_en : 1; /* [ 22], r/w, 0x1 */ + uint32_t cr_ep7_done_en : 1; /* [ 23], r/w, 0x1 */ + uint32_t rsvd_26_24 : 3; /* [26:24], rsvd, 0x0 */ + uint32_t cr_usb_rend_en : 1; /* [ 27], r/w, 0x0 */ + uint32_t cr_lpm_wkup_en : 1; /* [ 28], r/w, 0x0 */ + uint32_t cr_lpm_pkt_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t cr_sof_3ms_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t cr_usb_err_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } usb_int_en; + + /* 0x24 : USB interrupt status */ + union { + struct + { + uint32_t sof_int : 1; /* [ 0], r, 0x0 */ + uint32_t usb_reset_int : 1; /* [ 1], r, 0x0 */ + uint32_t vbus_tgl_int : 1; /* [ 2], r, 0x0 */ + uint32_t get_dct_cmd_int : 1; /* [ 3], r, 0x0 */ + uint32_t ep0_setup_cmd_int : 1; /* [ 4], r, 0x0 */ + uint32_t ep0_setup_done_int : 1; /* [ 5], r, 0x0 */ + uint32_t ep0_in_cmd_int : 1; /* [ 6], r, 0x0 */ + uint32_t ep0_in_done_int : 1; /* [ 7], r, 0x0 */ + uint32_t ep0_out_cmd_int : 1; /* [ 8], r, 0x0 */ + uint32_t ep0_out_done_int : 1; /* [ 9], r, 0x0 */ + uint32_t ep1_cmd_int : 1; /* [ 10], r, 0x0 */ + uint32_t ep1_done_int : 1; /* [ 11], r, 0x0 */ + uint32_t ep2_cmd_int : 1; /* [ 12], r, 0x0 */ + uint32_t ep2_done_int : 1; /* [ 13], r, 0x0 */ + uint32_t ep3_cmd_int : 1; /* [ 14], r, 0x0 */ + uint32_t ep3_done_int : 1; /* [ 15], r, 0x0 */ + uint32_t ep4_cmd_int : 1; /* [ 16], r, 0x0 */ + uint32_t ep4_done_int : 1; /* [ 17], r, 0x0 */ + uint32_t ep5_cmd_int : 1; /* [ 18], r, 0x0 */ + uint32_t ep5_done_int : 1; /* [ 19], r, 0x0 */ + uint32_t ep6_cmd_int : 1; /* [ 20], r, 0x0 */ + uint32_t ep6_done_int : 1; /* [ 21], r, 0x0 */ + uint32_t ep7_cmd_int : 1; /* [ 22], r, 0x0 */ + uint32_t ep7_done_int : 1; /* [ 23], r, 0x0 */ + uint32_t rsvd_26_24 : 3; /* [26:24], rsvd, 0x0 */ + uint32_t usb_rend_int : 1; /* [ 27], r, 0x0 */ + uint32_t lpm_wkup_int : 1; /* [ 28], r, 0x0 */ + uint32_t lpm_pkt_int : 1; /* [ 29], r, 0x0 */ + uint32_t sof_3ms_int : 1; /* [ 30], r, 0x0 */ + uint32_t usb_err_int : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } usb_int_sts; + + /* 0x28 : USB interrupt mask */ + union { + struct + { + uint32_t cr_sof_mask : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_usb_reset_mask : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_vbus_tgl_mask : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_get_dct_cmd_mask : 1; /* [ 3], r/w, 0x1 */ + uint32_t cr_ep0_setup_cmd_mask : 1; /* [ 4], r/w, 0x1 */ + uint32_t cr_ep0_setup_done_mask : 1; /* [ 5], r/w, 0x1 */ + uint32_t cr_ep0_in_cmd_mask : 1; /* [ 6], r/w, 0x1 */ + uint32_t cr_ep0_in_done_mask : 1; /* [ 7], r/w, 0x1 */ + uint32_t cr_ep0_out_cmd_mask : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_ep0_out_done_mask : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_ep1_cmd_mask : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_ep1_done_mask : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_ep2_cmd_mask : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_ep2_done_mask : 1; /* [ 13], r/w, 0x1 */ + uint32_t cr_ep3_cmd_mask : 1; /* [ 14], r/w, 0x1 */ + uint32_t cr_ep3_done_mask : 1; /* [ 15], r/w, 0x1 */ + uint32_t cr_ep4_cmd_mask : 1; /* [ 16], r/w, 0x1 */ + uint32_t cr_ep4_done_mask : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep5_cmd_mask : 1; /* [ 18], r/w, 0x1 */ + uint32_t cr_ep5_done_mask : 1; /* [ 19], r/w, 0x1 */ + uint32_t cr_ep6_cmd_mask : 1; /* [ 20], r/w, 0x1 */ + uint32_t cr_ep6_done_mask : 1; /* [ 21], r/w, 0x1 */ + uint32_t cr_ep7_cmd_mask : 1; /* [ 22], r/w, 0x1 */ + uint32_t cr_ep7_done_mask : 1; /* [ 23], r/w, 0x1 */ + uint32_t rsvd_26_24 : 3; /* [26:24], rsvd, 0x0 */ + uint32_t cr_usb_rend_mask : 1; /* [ 27], r/w, 0x1 */ + uint32_t cr_lpm_wkup_mask : 1; /* [ 28], r/w, 0x1 */ + uint32_t cr_lpm_pkt_mask : 1; /* [ 29], r/w, 0x1 */ + uint32_t cr_sof_3ms_mask : 1; /* [ 30], r/w, 0x1 */ + uint32_t cr_usb_err_mask : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } usb_int_mask; + + /* 0x2C : USB interrupt clear */ + union { + struct + { + uint32_t cr_sof_clr : 1; /* [ 0], w1c, 0x0 */ + uint32_t cr_usb_reset_clr : 1; /* [ 1], w1c, 0x0 */ + uint32_t cr_vbus_tgl_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t cr_get_dct_cmd_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t cr_ep0_setup_cmd_clr : 1; /* [ 4], w1c, 0x0 */ + uint32_t cr_ep0_setup_done_clr : 1; /* [ 5], w1c, 0x0 */ + uint32_t cr_ep0_in_cmd_clr : 1; /* [ 6], w1c, 0x0 */ + uint32_t cr_ep0_in_done_clr : 1; /* [ 7], w1c, 0x0 */ + uint32_t cr_ep0_out_cmd_clr : 1; /* [ 8], w1c, 0x0 */ + uint32_t cr_ep0_out_done_clr : 1; /* [ 9], w1c, 0x0 */ + uint32_t cr_ep1_cmd_clr : 1; /* [ 10], w1c, 0x0 */ + uint32_t cr_ep1_done_clr : 1; /* [ 11], w1c, 0x0 */ + uint32_t cr_ep2_cmd_clr : 1; /* [ 12], w1c, 0x0 */ + uint32_t cr_ep2_done_clr : 1; /* [ 13], w1c, 0x0 */ + uint32_t cr_ep3_cmd_clr : 1; /* [ 14], w1c, 0x0 */ + uint32_t cr_ep3_done_clr : 1; /* [ 15], w1c, 0x0 */ + uint32_t cr_ep4_cmd_clr : 1; /* [ 16], w1c, 0x0 */ + uint32_t cr_ep4_done_clr : 1; /* [ 17], w1c, 0x0 */ + uint32_t cr_ep5_cmd_clr : 1; /* [ 18], w1c, 0x0 */ + uint32_t cr_ep5_done_clr : 1; /* [ 19], w1c, 0x0 */ + uint32_t cr_ep6_cmd_clr : 1; /* [ 20], w1c, 0x0 */ + uint32_t cr_ep6_done_clr : 1; /* [ 21], w1c, 0x0 */ + uint32_t cr_ep7_cmd_clr : 1; /* [ 22], w1c, 0x0 */ + uint32_t cr_ep7_done_clr : 1; /* [ 23], w1c, 0x0 */ + uint32_t rsvd_26_24 : 3; /* [26:24], rsvd, 0x0 */ + uint32_t cr_usb_rend_clr : 1; /* [ 27], w1c, 0x0 */ + uint32_t cr_lpm_wkup_clr : 1; /* [ 28], w1c, 0x0 */ + uint32_t cr_lpm_pkt_clr : 1; /* [ 29], w1c, 0x0 */ + uint32_t cr_sof_3ms_clr : 1; /* [ 30], w1c, 0x0 */ + uint32_t cr_usb_err_clr : 1; /* [ 31], w1c, 0x0 */ + } BF; + uint32_t WORD; + } usb_int_clear; + + /* 0x30 reserved */ + uint8_t RESERVED0x30[16]; + + /* 0x40 : ep1_config */ + union { + struct + { + uint32_t cr_ep1_size : 11; /* [10: 0], r/w, 0x40 */ + uint32_t cr_ep1_dir : 2; /* [12:11], r/w, 0x1 */ + uint32_t cr_ep1_type : 3; /* [15:13], r/w, 0x4 */ + uint32_t cr_ep1_stall : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_ep1_nack : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep1_rdy : 1; /* [ 18], w1c, 0x0 */ + uint32_t sts_ep1_rdy : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep1_config; + + /* 0x44 : ep2_config */ + union { + struct + { + uint32_t cr_ep2_size : 11; /* [10: 0], r/w, 0x40 */ + uint32_t cr_ep2_dir : 2; /* [12:11], r/w, 0x1 */ + uint32_t cr_ep2_type : 3; /* [15:13], r/w, 0x4 */ + uint32_t cr_ep2_stall : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_ep2_nack : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep2_rdy : 1; /* [ 18], w1c, 0x0 */ + uint32_t sts_ep2_rdy : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep2_config; + + /* 0x48 : ep3_config */ + union { + struct + { + uint32_t cr_ep3_size : 11; /* [10: 0], r/w, 0x40 */ + uint32_t cr_ep3_dir : 2; /* [12:11], r/w, 0x1 */ + uint32_t cr_ep3_type : 3; /* [15:13], r/w, 0x4 */ + uint32_t cr_ep3_stall : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_ep3_nack : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep3_rdy : 1; /* [ 18], w1c, 0x0 */ + uint32_t sts_ep3_rdy : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep3_config; + + /* 0x4C : ep4_config */ + union { + struct + { + uint32_t cr_ep4_size : 11; /* [10: 0], r/w, 0x40 */ + uint32_t cr_ep4_dir : 2; /* [12:11], r/w, 0x1 */ + uint32_t cr_ep4_type : 3; /* [15:13], r/w, 0x4 */ + uint32_t cr_ep4_stall : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_ep4_nack : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep4_rdy : 1; /* [ 18], w1c, 0x0 */ + uint32_t sts_ep4_rdy : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep4_config; + + /* 0x50 : ep5_config */ + union { + struct + { + uint32_t cr_ep5_size : 11; /* [10: 0], r/w, 0x40 */ + uint32_t cr_ep5_dir : 2; /* [12:11], r/w, 0x1 */ + uint32_t cr_ep5_type : 3; /* [15:13], r/w, 0x4 */ + uint32_t cr_ep5_stall : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_ep5_nack : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep5_rdy : 1; /* [ 18], w1c, 0x0 */ + uint32_t sts_ep5_rdy : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep5_config; + + /* 0x54 : ep6_config */ + union { + struct + { + uint32_t cr_ep6_size : 11; /* [10: 0], r/w, 0x40 */ + uint32_t cr_ep6_dir : 2; /* [12:11], r/w, 0x1 */ + uint32_t cr_ep6_type : 3; /* [15:13], r/w, 0x4 */ + uint32_t cr_ep6_stall : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_ep6_nack : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep6_rdy : 1; /* [ 18], w1c, 0x0 */ + uint32_t sts_ep6_rdy : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep6_config; + + /* 0x58 : ep7_config */ + union { + struct + { + uint32_t cr_ep7_size : 11; /* [10: 0], r/w, 0x40 */ + uint32_t cr_ep7_dir : 2; /* [12:11], r/w, 0x1 */ + uint32_t cr_ep7_type : 3; /* [15:13], r/w, 0x4 */ + uint32_t cr_ep7_stall : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_ep7_nack : 1; /* [ 17], r/w, 0x1 */ + uint32_t cr_ep7_rdy : 1; /* [ 18], w1c, 0x0 */ + uint32_t sts_ep7_rdy : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep7_config; + + /* 0x5c reserved */ + uint8_t RESERVED0x5c[164]; + + /* 0x100 : ep0_fifo_config */ + union { + struct + { + uint32_t ep0_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t ep0_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ep0_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t ep0_rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t ep0_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t ep0_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t ep0_rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t ep0_rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep0_fifo_config; + + /* 0x104 : ep0_fifo_status */ + union { + struct + { + uint32_t ep0_tx_fifo_cnt : 7; /* [ 6: 0], r, 0x40 */ + uint32_t reserved_7_13 : 7; /* [13: 7], rsvd, 0x0 */ + uint32_t ep0_tx_fifo_empty : 1; /* [ 14], r, 0x1 */ + uint32_t ep0_tx_fifo_full : 1; /* [ 15], r, 0x0 */ + uint32_t ep0_rx_fifo_cnt : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23_29 : 7; /* [29:23], rsvd, 0x0 */ + uint32_t ep0_rx_fifo_empty : 1; /* [ 30], r, 0x1 */ + uint32_t ep0_rx_fifo_full : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } ep0_fifo_status; + + /* 0x108 : ep0_tx_fifo_wdata */ + union { + struct + { + uint32_t ep0_tx_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep0_tx_fifo_wdata; + + /* 0x10C : ep0_rx_fifo_rdata */ + union { + struct + { + uint32_t ep0_rx_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep0_rx_fifo_rdata; + + /* 0x110 : ep1_fifo_config */ + union { + struct + { + uint32_t ep1_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t ep1_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ep1_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t ep1_rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t ep1_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t ep1_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t ep1_rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t ep1_rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep1_fifo_config; + + /* 0x114 : ep1_fifo_status */ + union { + struct + { + uint32_t ep1_tx_fifo_cnt : 7; /* [ 6: 0], r, 0x40 */ + uint32_t reserved_7_13 : 7; /* [13: 7], rsvd, 0x0 */ + uint32_t ep1_tx_fifo_empty : 1; /* [ 14], r, 0x1 */ + uint32_t ep1_tx_fifo_full : 1; /* [ 15], r, 0x0 */ + uint32_t ep1_rx_fifo_cnt : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23_29 : 7; /* [29:23], rsvd, 0x0 */ + uint32_t ep1_rx_fifo_empty : 1; /* [ 30], r, 0x1 */ + uint32_t ep1_rx_fifo_full : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } ep1_fifo_status; + + /* 0x118 : ep1_tx_fifo_wdata */ + union { + struct + { + uint32_t ep1_tx_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep1_tx_fifo_wdata; + + /* 0x11C : ep1_rx_fifo_rdata */ + union { + struct + { + uint32_t ep1_rx_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep1_rx_fifo_rdata; + + /* 0x120 : ep2_fifo_config */ + union { + struct + { + uint32_t ep2_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t ep2_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ep2_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t ep2_rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t ep2_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t ep2_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t ep2_rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t ep2_rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep2_fifo_config; + + /* 0x124 : ep2_fifo_status */ + union { + struct + { + uint32_t ep2_tx_fifo_cnt : 7; /* [ 6: 0], r, 0x40 */ + uint32_t reserved_7_13 : 7; /* [13: 7], rsvd, 0x0 */ + uint32_t ep2_tx_fifo_empty : 1; /* [ 14], r, 0x1 */ + uint32_t ep2_tx_fifo_full : 1; /* [ 15], r, 0x0 */ + uint32_t ep2_rx_fifo_cnt : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23_29 : 7; /* [29:23], rsvd, 0x0 */ + uint32_t ep2_rx_fifo_empty : 1; /* [ 30], r, 0x1 */ + uint32_t ep2_rx_fifo_full : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } ep2_fifo_status; + + /* 0x128 : ep2_tx_fifo_wdata */ + union { + struct + { + uint32_t ep2_tx_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep2_tx_fifo_wdata; + + /* 0x12C : ep2_rx_fifo_rdata */ + union { + struct + { + uint32_t ep2_rx_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep2_rx_fifo_rdata; + + /* 0x130 : ep3_fifo_config */ + union { + struct + { + uint32_t ep3_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t ep3_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ep3_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t ep3_rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t ep3_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t ep3_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t ep3_rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t ep3_rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep3_fifo_config; + + /* 0x134 : ep3_fifo_status */ + union { + struct + { + uint32_t ep3_tx_fifo_cnt : 7; /* [ 6: 0], r, 0x40 */ + uint32_t reserved_7_13 : 7; /* [13: 7], rsvd, 0x0 */ + uint32_t ep3_tx_fifo_empty : 1; /* [ 14], r, 0x1 */ + uint32_t ep3_tx_fifo_full : 1; /* [ 15], r, 0x0 */ + uint32_t ep3_rx_fifo_cnt : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23_29 : 7; /* [29:23], rsvd, 0x0 */ + uint32_t ep3_rx_fifo_empty : 1; /* [ 30], r, 0x1 */ + uint32_t ep3_rx_fifo_full : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } ep3_fifo_status; + + /* 0x138 : ep3_tx_fifo_wdata */ + union { + struct + { + uint32_t ep3_tx_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep3_tx_fifo_wdata; + + /* 0x13C : ep3_rx_fifo_rdata */ + union { + struct + { + uint32_t ep3_rx_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep3_rx_fifo_rdata; + + /* 0x140 : ep4_fifo_config */ + union { + struct + { + uint32_t ep4_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t ep4_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ep4_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t ep4_rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t ep4_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t ep4_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t ep4_rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t ep4_rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep4_fifo_config; + + /* 0x144 : ep4_fifo_status */ + union { + struct + { + uint32_t ep4_tx_fifo_cnt : 7; /* [ 6: 0], r, 0x40 */ + uint32_t reserved_7_13 : 7; /* [13: 7], rsvd, 0x0 */ + uint32_t ep4_tx_fifo_empty : 1; /* [ 14], r, 0x1 */ + uint32_t ep4_tx_fifo_full : 1; /* [ 15], r, 0x0 */ + uint32_t ep4_rx_fifo_cnt : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23_29 : 7; /* [29:23], rsvd, 0x0 */ + uint32_t ep4_rx_fifo_empty : 1; /* [ 30], r, 0x1 */ + uint32_t ep4_rx_fifo_full : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } ep4_fifo_status; + + /* 0x148 : ep4_tx_fifo_wdata */ + union { + struct + { + uint32_t ep4_tx_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep4_tx_fifo_wdata; + + /* 0x14C : ep4_rx_fifo_rdata */ + union { + struct + { + uint32_t ep4_rx_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep4_rx_fifo_rdata; + + /* 0x150 : ep5_fifo_config */ + union { + struct + { + uint32_t ep5_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t ep5_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ep5_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t ep5_rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t ep5_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t ep5_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t ep5_rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t ep5_rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep5_fifo_config; + + /* 0x154 : ep5_fifo_status */ + union { + struct + { + uint32_t ep5_tx_fifo_cnt : 7; /* [ 6: 0], r, 0x40 */ + uint32_t reserved_7_13 : 7; /* [13: 7], rsvd, 0x0 */ + uint32_t ep5_tx_fifo_empty : 1; /* [ 14], r, 0x1 */ + uint32_t ep5_tx_fifo_full : 1; /* [ 15], r, 0x0 */ + uint32_t ep5_rx_fifo_cnt : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23_29 : 7; /* [29:23], rsvd, 0x0 */ + uint32_t ep5_rx_fifo_empty : 1; /* [ 30], r, 0x1 */ + uint32_t ep5_rx_fifo_full : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } ep5_fifo_status; + + /* 0x158 : ep5_tx_fifo_wdata */ + union { + struct + { + uint32_t ep5_tx_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep5_tx_fifo_wdata; + + /* 0x15C : ep5_rx_fifo_rdata */ + union { + struct + { + uint32_t ep5_rx_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep5_rx_fifo_rdata; + + /* 0x160 : ep6_fifo_config */ + union { + struct + { + uint32_t ep6_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t ep6_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ep6_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t ep6_rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t ep6_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t ep6_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t ep6_rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t ep6_rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep6_fifo_config; + + /* 0x164 : ep6_fifo_status */ + union { + struct + { + uint32_t ep6_tx_fifo_cnt : 7; /* [ 6: 0], r, 0x40 */ + uint32_t reserved_7_13 : 7; /* [13: 7], rsvd, 0x0 */ + uint32_t ep6_tx_fifo_empty : 1; /* [ 14], r, 0x1 */ + uint32_t ep6_tx_fifo_full : 1; /* [ 15], r, 0x0 */ + uint32_t ep6_rx_fifo_cnt : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23_29 : 7; /* [29:23], rsvd, 0x0 */ + uint32_t ep6_rx_fifo_empty : 1; /* [ 30], r, 0x1 */ + uint32_t ep6_rx_fifo_full : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } ep6_fifo_status; + + /* 0x168 : ep6_tx_fifo_wdata */ + union { + struct + { + uint32_t ep6_tx_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep6_tx_fifo_wdata; + + /* 0x16C : ep6_rx_fifo_rdata */ + union { + struct + { + uint32_t ep6_rx_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep6_rx_fifo_rdata; + + /* 0x170 : ep7_fifo_config */ + union { + struct + { + uint32_t ep7_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t ep7_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t ep7_tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ + uint32_t ep7_rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ + uint32_t ep7_tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ + uint32_t ep7_tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ + uint32_t ep7_rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ + uint32_t ep7_rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep7_fifo_config; + + /* 0x174 : ep7_fifo_status */ + union { + struct + { + uint32_t ep7_tx_fifo_cnt : 7; /* [ 6: 0], r, 0x40 */ + uint32_t reserved_7_13 : 7; /* [13: 7], rsvd, 0x0 */ + uint32_t ep7_tx_fifo_empty : 1; /* [ 14], r, 0x1 */ + uint32_t ep7_tx_fifo_full : 1; /* [ 15], r, 0x0 */ + uint32_t ep7_rx_fifo_cnt : 7; /* [22:16], r, 0x0 */ + uint32_t reserved_23_29 : 7; /* [29:23], rsvd, 0x0 */ + uint32_t ep7_rx_fifo_empty : 1; /* [ 30], r, 0x1 */ + uint32_t ep7_rx_fifo_full : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } ep7_fifo_status; + + /* 0x178 : ep7_tx_fifo_wdata */ + union { + struct + { + uint32_t ep7_tx_fifo_wdata : 8; /* [ 7: 0], w, x */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep7_tx_fifo_wdata; + + /* 0x17C : ep7_rx_fifo_rdata */ + union { + struct + { + uint32_t ep7_rx_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ep7_rx_fifo_rdata; + + /* 0x180 reserved */ + uint8_t RESERVED0x180[112]; + + /* 0x1F0 : rsvd_0 */ + union { + struct + { + uint32_t rsvd_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsvd_0; + + /* 0x1F4 : rsvd_1 */ + union { + struct + { + uint32_t rsvd_1 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsvd_1; + + /* 0x1f8 reserved */ + uint8_t RESERVED0x1f8[4]; + + /* 0x1FC : xcvr_if_config */ + union { + struct + { + uint32_t cr_xcvr_force_tx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t cr_xcvr_force_tx_oe : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_xcvr_force_tx_dp : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_xcvr_force_tx_dn : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_xcvr_force_rx_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_xcvr_force_rx_d : 1; /* [ 5], r/w, 0x1 */ + uint32_t cr_xcvr_force_rx_dp : 1; /* [ 6], r/w, 0x1 */ + uint32_t cr_xcvr_force_rx_dn : 1; /* [ 7], r/w, 0x0 */ + uint32_t cr_xcvr_om_rx_sel : 1; /* [ 8], r/w, 0x0 */ + uint32_t cr_xcvr_om_rx_d : 1; /* [ 9], r/w, 0x1 */ + uint32_t cr_xcvr_om_rx_dp : 1; /* [ 10], r/w, 0x1 */ + uint32_t cr_xcvr_om_rx_dn : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_30 : 19; /* [30:12], rsvd, 0x0 */ + uint32_t sts_vbus_det : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } xcvr_if_config; +}; + +typedef volatile struct usb_reg usb_reg_t; + +#endif /* __USB_REG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/clic.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/clic.h new file mode 100644 index 0000000000000000000000000000000000000000..3ea51390b87ce351bd17dbcf794ba8294e8dae2d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/clic.h @@ -0,0 +1,21 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_CLIC_H +#define _SIFIVE_CLIC_H + +#define CLIC_CTRL_ADDR 0x02000000UL +#define CLIC_HART0_ADDR 0x02800000UL + +#define CLIC_MSIP 0x0000 +#define CLIC_MSIP_size 0x4 +#define CLIC_MTIMECMP 0x4000 +#define CLIC_MTIMECMP_size 0x8 +#define CLIC_MTIME 0xBFF8 +#define CLIC_MTIME_size 0x8 + +#define CLIC_INTIP 0x000 +#define CLIC_INTIE 0x400 +#define CLIC_INTCFG 0x800 +#define CLIC_CFG 0xc00 + +#endif /* _SIFIVE_CLIC_H */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/cmsis_compatible_gcc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/cmsis_compatible_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..88c7963f05f05812317b245ebd8f28e386671db5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/cmsis_compatible_gcc.h @@ -0,0 +1,132 @@ +#ifndef __CMSIS_COMPATIBLE_GCC_H +#define __CMSIS_COMPATIBLE_GCC_H + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __ALWAYS_INLINE +#define __ALWAYS_INLINE inline __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __IRQ +#define __IRQ __attribute__((interrupt)) +#endif +#ifndef __IRQ_ALIGN64 +#define __IRQ_ALIGN64 __attribute__((interrupt, aligned(64))) +#endif +#ifndef ALIGN4 +#define ALIGN4 __attribute((aligned(4))) +#endif +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */ + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */ + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */ + +static uint8_t nesting2 = 0; + +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + nesting2--; + if (nesting2 == 0) { + __ASM volatile("csrsi mstatus, 8"); + } +} + +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("csrci mstatus, 8"); + nesting2++; +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + //return __builtin_bswap32(value); + uint32_t res = 0; + + res = (value << 24) | (value >> 24); + res &= 0xFF0000FF; /* only for sure */ + res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000); + + return res; +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + return __builtin_bswap16(value); +} + +extern void clic_enable_interrupt(uint32_t source); +extern void clic_disable_interrupt(uint32_t source); +extern void clic_set_pending(uint32_t source); +extern void clic_clear_pending(uint32_t source); + +#define CPU_Interrupt_Enable clic_enable_interrupt + +#define CPU_Interrupt_Disable clic_disable_interrupt + +#define CPU_Interrupt_Pending_Clear clic_clear_pending + +//#define __set_MSP(val) __ASM volatile ("lw sp,0(%0)":: "r"(val)) +#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp)) + +#endif /* __CMSIS_COMPATIBLE_GCC_H */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_bits.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_bits.h new file mode 100644 index 0000000000000000000000000000000000000000..16b15bcddd5678feb76eae1241bce61d2674985a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) +#define ROUNDDOWN(a, b) ((a) / (b) * (b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +#define SLL32 sllw +#define STORE sd +#define LOAD ld +#define LWU lwu +#define LOG_REGBYTES 3 +#else +#define SLL32 sll +#define STORE sw +#define LOAD lw +#define LWU lw +#define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_const.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_const.h new file mode 100644 index 0000000000000000000000000000000000000000..109d1dff7649554b214619fce2272ce093af51eb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details. +/* Derived from */ + +#ifndef _RISCV_CONST_H +#define _RISCV_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X, Y) X +#define _AT(T, X) X +#else +#define _AC(X, Y) (X##Y) +#define _AT(T, X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1, UL) << (x)) +#define _BITULL(x) (_AC(1, ULL) << (x)) + +#endif /* _NUCLEI_CONST_H */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h new file mode 100644 index 0000000000000000000000000000000000000000..4987ac2653caa18e5ae639ae944f67bb4f72a842 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h @@ -0,0 +1,1360 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U << 30) +#define DCSR_NDRESET (1 << 29) +#define DCSR_FULLRESET (1 << 28) +#define DCSR_EBREAKM (1 << 15) +#define DCSR_EBREAKH (1 << 14) +#define DCSR_EBREAKS (1 << 13) +#define DCSR_EBREAKU (1 << 12) +#define DCSR_STOPCYCLE (1 << 10) +#define DCSR_STOPTIME (1 << 9) +#define DCSR_CAUSE (7 << 6) +#define DCSR_DEBUGINT (1 << 5) +#define DCSR_HALT (1 << 3) +#define DCSR_STEP (1 << 2) +#define DCSR_PRV (3 << 0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) + +#define MCONTROL_SELECT (1 << 19) +#define MCONTROL_TIMING (1 << 18) +#define MCONTROL_ACTION (0x3f << 12) +#define MCONTROL_CHAIN (1 << 11) +#define MCONTROL_MATCH (0xf << 7) +#define MCONTROL_M (1 << 6) +#define MCONTROL_H (1 << 5) +#define MCONTROL_S (1 << 4) +#define MCONTROL_U (1 << 3) +#define MCONTROL_EXECUTE (1 << 2) +#define MCONTROL_STORE (1 << 1) +#define MCONTROL_LOAD (1 << 0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define MIE_SSIE MIP_SSIP +#define MIE_HSIE MIP_HSIP +#define MIE_MSIE MIP_MSIP +#define MIE_STIE MIP_STIP +#define MIE_HTIE MIP_HTIP +#define MIE_MTIE MIP_MTIP +#define MIE_SEIE MIP_SEIP +#define MIE_HEIE MIP_HEIP +#define MIE_MEIE MIP_MEIP + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +#define MSTATUS_SD MSTATUS64_SD +#define SSTATUS_SD SSTATUS64_SD +#define RISCV_PGLEVEL_BITS 9 +#else +#define MSTATUS_SD MSTATUS32_SD +#define SSTATUS_SD SSTATUS32_SD +#define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define asm __asm + +#define read_fpu(reg) ({ unsigned long __tmp; \ + asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_fpu(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 + +#define CSR_MCOUNTINHIBIT 0x320 + +#define CSR_MNVEC 0x7C3 + +#define CSR_MTVT2 0x7EC +#define CSR_JALMNXTI 0x7ED +#define CSR_PUSHMCAUSE 0x7EE +#define CSR_PUSHMEPC 0x7EF +#define CSR_PUSHMSUBM 0x7EB + +#define CSR_WFE 0x810 +#define CSR_SLEEPVALUE 0x811 +#define CSR_TXEVT 0x812 + +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MSUBM 0x7c4 + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, + MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, + MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, + MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, + MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/entry.S b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/entry.S new file mode 100644 index 0000000000000000000000000000000000000000..b5bab3be07deb72ed461cb9da3fb2d6951c9c12b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/entry.S @@ -0,0 +1,120 @@ +/* Copyright 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +#include "riscv_encoding.h" + +/* This code executes before _start, which is contained inside the C library. + * In embedded systems we want to ensure that _enter, which contains the first + * code to be executed, can be loaded at a specific address. To enable this + * feature we provide the '.text.metal.init.enter' section, which is + * defined to have the first address being where execution should start. */ +.section .text.metal.init.enter +.global _enter +_enter: + .cfi_startproc + + /* Inform the debugger that there is nowhere to backtrace past _enter. */ + .cfi_undefined ra + + /* The absolute first thing that must happen is configuring the global + * pointer register, which must be done with relaxation disabled because + * it's not valid to obtain the address of any symbol without GP + * configured. The C environment might go ahead and do this again, but + * that's safe as it's a fixed register. */ +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + /* Disable global interrupt */ + /*clear_csr(mstatus, MSTATUS_MIE);*/ + csrci mstatus,8 + + /* If there is a clint then interrupts can branch directly to the + * trap handler. Otherwise the interrupt controller will need to be configured + * outside of this file. */ +#ifndef TRAP_ENRTY + la t0, Trap_Handler_Stub +#else + la t0, TRAP_ENRTY +#endif + ori t0, t0, 2 + csrw mtvec, t0 + + /* enable chicken bit if core is bullet series*/ + la t0, __metal_chicken_bit + beqz t0, 1f + csrwi 0x7C1, 0 +1: + + /* There may be pre-initialization routines inside the MBI code that run in + * C, so here we set up a C environment. First we set up a stack pointer, + * which is left as a weak reference in order to allow initialization + * routines that do not need a stack to be set up to transparently be + * called. */ + .weak __StackTop + la sp, __StackTop +#ifdef __riscv_float_abi_single + /* deal with FP */ + /* Is F extension present? */ + csrr t0, misa + andi t0, t0, (1 << ('F' - 'A')) + beqz t0, 1f + /* If so, enable it */ + li t0, MSTATUS_FS + csrs mstatus, t0 + fssr x0 +1: +#endif + + /* Check for an initialization routine and call it if one exists, otherwise + * just skip over the call entirely. Note that __metal_initialize isn't + * actually a full C function, as it doesn't end up with the .bss or .data + * segments having been initialized. This is done to avoid putting a + * burden on systems that can be initialized without having a C environment + * set up. */ + call SystemInit + + /* start load code to itcm like. */ + call start_load + + jal System_Post_Init + /* At this point we can enter the C runtime's startup file. The arguments + * to this function are designed to match those provided to the SEE, just + * so we don't have to write another ABI. */ + csrr a0, mhartid + li a1, 0 + li a2, 0 + call entry + + csrci mstatus, (1 << 3) + +__exit: + j __exit + + .cfi_endproc + +/* For sanity's sake we set up an early trap vector that just does nothing. If + * you end up here then there's a bug in the early boot code somewhere. */ +.weak Trap_Handler_Stub +.section .text.metal.init.trapvec +.align 2 +Trap_Handler_Stub: + .cfi_startproc + csrr t0, mcause + csrr t1, mepc + csrr t2, mtval + j Trap_Handler_Stub + .cfi_endproc + +/* The GCC port might not emit a __register_frame_info symbol, which eventually + * results in a weak undefined reference that eventually causes crash when it + * is dereference early in boot. We really shouldn't need to put this here, + * but to deal with what I think is probably a bug in the linker script I'm + * going to leave this in for now. At least it's fairly cheap :) */ +.weak __register_frame_info +.global __register_frame_info +.section .text.metal.init.__register_frame_info +__register_frame_info: + .cfi_startproc + ret + .cfi_endproc diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/start_load.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/start_load.c new file mode 100644 index 0000000000000000000000000000000000000000..ccdec3caea801ea10370d7cbad4933a7b004c15e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/start_load.c @@ -0,0 +1,115 @@ +/** + * @file start_load.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include +#include "bl702.h" + +#define __STARTUP_CLEAR_BSS 1 + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __itcm_load_addr; +extern uint32_t __dtcm_load_addr; +extern uint32_t __system_ram_load_addr; +extern uint32_t __ram_load_addr; + +extern uint32_t __text_code_start__; +extern uint32_t __text_code_end__; +extern uint32_t __tcm_code_start__; +extern uint32_t __tcm_code_end__; +extern uint32_t __tcm_data_start__; +extern uint32_t __tcm_data_end__; +extern uint32_t __system_ram_data_start__; +extern uint32_t __system_ram_data_end__; +extern uint32_t __ram_data_start__; +extern uint32_t __ram_data_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __noinit_data_start__; +extern uint32_t __noinit_data_end__; + +extern uint32_t __StackTop; +extern uint32_t __StackLimit; +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +//extern uint32_t __copy_table_start__; +//extern uint32_t __copy_table_end__; +//extern uint32_t __zero_table_start__; +//extern uint32_t __zero_table_end__; + +void start_load(void) +{ + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + + /* Copy ITCM code */ + pSrc = &__itcm_load_addr; + pDest = &__tcm_code_start__; + + for (; pDest < &__tcm_code_end__;) { + *pDest++ = *pSrc++; + } + + /* Copy DTCM code */ + pSrc = &__dtcm_load_addr; + pDest = &__tcm_data_start__; + + for (; pDest < &__tcm_data_end__;) { + *pDest++ = *pSrc++; + } + + /* BF Add system RAM data copy */ + pSrc = &__system_ram_load_addr; + pDest = &__system_ram_data_start__; + + for (; pDest < &__system_ram_data_end__;) { + *pDest++ = *pSrc++; + } + + /* BF Add OCARAM data copy */ + pSrc = &__ram_load_addr; + pDest = &__ram_data_start__; + + for (; pDest < &__ram_data_end__;) { + *pDest++ = *pSrc++; + } + +#ifdef __STARTUP_CLEAR_BSS + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for (; pDest < &__bss_end__;) { + *pDest++ = 0ul; + } + +#endif +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/interrupt.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..22980fb6f4c8c0af2521c0f6f6bbcf87ed5da51a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/interrupt.c @@ -0,0 +1,226 @@ +/** + * @file interrupt.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include + +#include "../risc-v/Core/Include/clic.h" +#include "../risc-v/Core/Include/cmsis_compatible_gcc.h" + +typedef void (*pFunc)(void); +extern void Interrupt_Handler(void); +extern void trap_handler(void); +void Interrupt_Handler_Stub(void); + +void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void clic_mtimer_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void clic_mext_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void clic_csoft_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void L1C_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void L1C_BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void RF_TOP_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void RF_TOP_INT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void DMA_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_GMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_CDET_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_PKA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_TRNG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SEC_SHA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void DMA_ALL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MJPEG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void CAM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void I2S_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void IRTX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void IRRX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void USB_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void EMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SF_CTRL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void GPADC_DMA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void EFUSE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void SPI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void UART0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void UART1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void I2C_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void PWM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_CH0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_CH1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_WDT_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void KYS_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void QDEC0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void QDEC1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void QDEC2_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void GPIO_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void TOUCH_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void M154_REQ_ENH_ACK_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void M154_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void M154_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void PDS_WAKEUP_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void HBN_OUT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void HBN_OUT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BOR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void WIFI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BZ_PHY_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void BLE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TXRX_TIMER_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TXRX_MISC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_RX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_GEN_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void MAC_PORT_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); +void WIFI_IPC_PUBLIC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub"))); + +const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = { + 0, /* */ + 0, /* */ + 0, /* */ + clic_msip_handler_Wrapper, /* 3 */ + 0, /* */ + 0, /* */ + 0, /* */ + clic_mtimer_handler_Wrapper, /* 7 */ + (pFunc)0x00000001, /* */ + 0, /* */ + (pFunc)0x00000102, /* */ //disable log as default + clic_mext_handler_Wrapper, /* 11 */ + clic_csoft_handler_Wrapper, /* 12 */ + 0, /* */ + 0, /* */ + 0, /* */ + BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */ + BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */ + L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */ + L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */ + SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */ + RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */ + RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */ + 0, /* 16 + 7 */ + DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */ + SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */ + SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */ + SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */ + SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */ + SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */ + SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */ + DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */ + MJPEG_IRQHandler_Wrapper, /* 16 + 16 */ + CAM_IRQHandler_Wrapper, /* 16 + 17 */ + I2S_IRQHandler_Wrapper, /* 16 + 18 */ + IRTX_IRQHandler_Wrapper, /* 16 + 19 */ + IRRX_IRQHandler_Wrapper, /* 16 + 20 */ + USB_IRQHandler_Wrapper, /* 16 + 21 */ + EMAC_IRQHandler_Wrapper, /* 16 + 22 */ + SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */ + 0, /* 16 + 24 */ + GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */ + EFUSE_IRQHandler_Wrapper, /* 16 + 26 */ + SPI_IRQHandler_Wrapper, /* 16 + 27 */ + 0, /* 16 + 28 */ + UART0_IRQHandler_Wrapper, /* 16 + 29 */ + UART1_IRQHandler_Wrapper, /* 16 + 30 */ + 0, /* 16 + 31 */ + I2C_IRQHandler_Wrapper, /* 16 + 32 */ + 0, /* 16 + 33 */ + PWM_IRQHandler_Wrapper, /* 16 + 34 */ + 0, /* 16 + 35 */ + TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */ + TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */ + TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */ + KYS_IRQHandler_Wrapper, /* 16 + 39 */ + QDEC0_IRQHandler_Wrapper, /* 16 + 40 */ + QDEC1_IRQHandler_Wrapper, /* 16 + 41 */ + QDEC2_IRQHandler_Wrapper, /* 16 + 42 */ + 0, /* 16 + 43 */ + GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */ + TOUCH_IRQHandler_Wrapper, /* 16 + 45 */ + 0, /* 16 + 46 */ + M154_REQ_ENH_ACK_IRQHandler_Wrapper, /* 16 + 47 */ + M154_IRQHandler_Wrapper, /* 16 + 48 */ + M154_AES_IRQHandler_Wrapper, /* 16 + 49 */ + PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */ + HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */ + HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */ + BOR_IRQHandler_Wrapper, /* 16 + 53 */ + WIFI_IRQHandler_Wrapper, /* 16 + 54 */ + BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */ + BLE_IRQHandler_Wrapper, /* 16 + 56 */ + MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */ + MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */ + MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */ + MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */ + MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */ + MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */ + WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */ +}; + +void __IRQ_ALIGN64 Trap_Handler_Stub(void) +{ + trap_handler(); +} + +void __IRQ Interrupt_Handler_Stub(void) +{ + Interrupt_Handler(); +} + +void clic_enable_interrupt(uint32_t source) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1; +} + +void clic_disable_interrupt(uint32_t source) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0; +} + +void clic_set_pending(uint32_t source) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1; +} + +void clic_clear_pending(uint32_t source) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0; +} + +void clic_set_intcfg(uint32_t source, uint32_t intcfg) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source) = intcfg; +} + +uint8_t clic_get_intcfg(uint32_t source) +{ + return *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source); +} + +void clic_set_cliccfg(uint32_t cfg) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_CFG) = cfg; +} + +uint8_t clic_get_cliccfg(void) +{ + return *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_CFG); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c new file mode 100644 index 0000000000000000000000000000000000000000..8ff840d92283ed6b03d8b6006d1968b5211d05d6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c @@ -0,0 +1,156 @@ +/** + * @file system_bl702.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "bl702.h" +#include "bl702_glb.h" +#include "bl702_hbn.h" +#include "system_bl702.h" + +#ifdef BFLB_EFLASH_LOADER +#include "bl702_usb.h" +void USB_DoNothing_IRQHandler(void) +{ + /* clear all USB int sts */ + USB_Clr_IntStatus(32); +} +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define SYSTEM_CLOCK (32000000UL) + +/*---------------------------------------------------------------------------- + Vector Table + *----------------------------------------------------------------------------*/ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ + +void system_bor_init(void) +{ + HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ }; + HBN_Set_BOR_Cfg(&borCfg); +} + +void SystemInit(void) +{ + uint32_t *p; + uint32_t i = 0; + uint32_t tmpVal = 0; + uint8_t flashCfg = 0; + uint8_t psramCfg = 0; + uint8_t isInternalFlash = 0; + uint8_t isInternalPsram = 0; + + /* global IRQ disable */ + __disable_irq(); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal |= (1 << 8); /*mask pds wakeup*/ + tmpVal |= (1 << 10); /*mask rf done*/ + tmpVal |= (1 << 11); /*mask pll done*/ + tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/ + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE); + BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); + + /* GLB_Set_EM_Sel(GLB_EM_0KB); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB); + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + /* Restore default setting*/ + /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + /* fix 57.6M */ + if (SystemCoreClockGet() == 57 * 6000 * 1000) { + SystemCoreClockSet(57.6 * 1000 * 1000) + } + + /* CLear all interrupt */ + p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + /* SF io select from efuse value */ + tmpVal = BL_RD_WORD(0x40007074); + flashCfg = ((tmpVal >> 26) & 7); + psramCfg = ((tmpVal >> 24) & 3); + if (flashCfg == 1 || flashCfg == 2) { + isInternalFlash = 1; + } else { + isInternalFlash = 0; + } + if (psramCfg == 1) { + isInternalPsram = 1; + } else { + isInternalPsram = 0; + } + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); + if (isInternalFlash == 1 && isInternalPsram == 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00); + } + BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal); + +#ifdef BFLB_EFLASH_LOADER + Interrupt_Handler_Register(USB_IRQn, USB_DoNothing_IRQHandler); +#endif + /* init bor for all platform */ + system_bor_init(); + /* global IRQ enable */ + __enable_irq(); +} +/*identify flash config automaticly*/ +extern BL_Err_Type flash_init(void); +extern void bflb_platform_print_set(uint8_t disable); +void System_Post_Init(void) +{ + PDS_Trim_RC32M(); + HBN_Trim_RC32K(); + bflb_platform_print_set(1); + flash_init(); + bflb_platform_print_set(0); +} + +void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.h new file mode 100644 index 0000000000000000000000000000000000000000..43f3ca55c15927510fdcee708d52568b6cf78c5b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.h @@ -0,0 +1,39 @@ +/** + * @file system_bl702.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __SYSTEM_BL702_H__ +#define __SYSTEM_BL702_H__ + +/** + * @brief PLL Clock type definition + */ + +extern uint32_t SystemCoreClock; + +extern void SystemCoreClockUpdate(void); +extern void SystemInit(void); +extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +extern void Systick_Stop(void); +extern void Systick_Start(void); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_acomp.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_acomp.h new file mode 100644 index 0000000000000000000000000000000000000000..cb812aaaccd61cad24a9db64d6764babc8f5252c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_acomp.h @@ -0,0 +1,213 @@ +/** + ****************************************************************************** + * @file bl702_acomp.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_ACOMP_H__ +#define __BL702_ACOMP_H__ + +#include "aon_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup ACOMP + * @{ + */ + +/** @defgroup ACOMP_Public_Types + * @{ + */ + +/** + * @brief Analog compare id type definition + */ +typedef enum { + AON_ACOMP0_ID, /*!< Analog compare 0 */ + AON_ACOMP1_ID, /*!< Analog compare 1 */ +} AON_ACOMP_ID_Type; + +/** + * @brief Analog compare level type definition + */ +typedef enum { + AON_ACOMP_LEVEL_FACTOR_0P25, /*!< Analog compare level scaling factor 0.25 */ + AON_ACOMP_LEVEL_FACTOR_0P5, /*!< Analog compare level scaling factor 0.5 */ + AON_ACOMP_LEVEL_FACTOR_0P75, /*!< Analog compare level scaling factor 0.75 */ + AON_ACOMP_LEVEL_FACTOR_1, /*!< Analog compare level scaling factor 1 */ +} AON_ACOMP_Level_Factor_Type; + +/** + * @brief Analog compare channel type definition + */ +typedef enum { + AON_ACOMP_CHAN_ADC0, /*!< Analog compare channel,ADC input channel 0 */ + AON_ACOMP_CHAN_ADC1, /*!< Analog compare channel,ADC input channel 1 */ + AON_ACOMP_CHAN_ADC2, /*!< Analog compare channel,ADC input channel 2 */ + AON_ACOMP_CHAN_ADC3, /*!< Analog compare channel,ADC input channel 3 */ + AON_ACOMP_CHAN_ADC4, /*!< Analog compare channel,ADC input channel 4 */ + AON_ACOMP_CHAN_ADC5, /*!< Analog compare channel,ADC input channel 5 */ + AON_ACOMP_CHAN_ADC6, /*!< Analog compare channel,ADC input channel 6 */ + AON_ACOMP_CHAN_ADC7, /*!< Analog compare channel,ADC input channel 7 */ + AON_ACOMP_CHAN_DACA, /*!< Analog compare channel,DAC output channel A */ + AON_ACOMP_CHAN_DACB, /*!< Analog compare channel,DAC output channel B */ + AON_ACOMP_CHAN_VREF_1P2V, /*!< Analog compare channel,1.2V ref voltage */ + AON_ACOMP_CHAN_0P375VBAT_NOT_IMP, /*!< Analog compare channel,6/16Vbat */ + AON_ACOMP_CHAN_0P25VBAT, /*!< Analog compare channel,4/16Vbat */ + AON_ACOMP_CHAN_0P1875VBAT, /*!< Analog compare channel,3/16Vbat */ + AON_ACOMP_CHAN_0P3125VBAT, /*!< Analog compare channel,5/16Vbat */ + AON_ACOMP_CHAN_VSS, /*!< Analog compare channel,vss */ +} AON_ACOMP_Chan_Type; + +/** + * @brief Analog compare bias current control type definition + */ +typedef enum { + AON_ACOMP_BIAS_POWER_MODE1, /*!< Analog compare power mode 1,slow response mode */ + AON_ACOMP_BIAS_POWER_MODE2, /*!< Analog compare power mode 2,medium response mode */ + AON_ACOMP_BIAS_POWER_MODE3, /*!< Analog compare power mode 3,fast response mode */ + AON_ACOMP_BIAS_POWER_NONE, /*!< Analog compare power mode none */ +} AON_ACOMP_Bias_Prog_Type; + +/** + * @brief Analog compare hysteresis voltage type definition + */ +typedef enum { + AON_ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */ + AON_ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */ + AON_ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */ + AON_ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */ + AON_ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */ + AON_ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */ + AON_ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */ + AON_ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */ +} AON_ACOMP_Hysteresis_Volt_Type; + +/** + * @brief AON ACOMP configuration type definition + */ +typedef struct +{ + BL_Fun_Type muxEn; /*!< ACOMP mux enable */ + uint8_t posChanSel; /*!< ACOMP positive channel select */ + uint8_t negChanSel; /*!< ACOMP negtive channel select */ + AON_ACOMP_Level_Factor_Type levelFactor; /*!< ACOMP level select factor */ + AON_ACOMP_Bias_Prog_Type biasProg; /*!< ACOMP bias current control */ + AON_ACOMP_Hysteresis_Volt_Type hysteresisPosVolt; /*!< ACOMP hysteresis voltage for positive */ + AON_ACOMP_Hysteresis_Volt_Type hysteresisNegVolt; /*!< ACOMP hysteresis voltage for negtive */ +} AON_ACOMP_CFG_Type; + +/*@} end of group ACOMP_Public_Types */ + +/** @defgroup ACOMP_Public_Constants + * @{ + */ + +/** @defgroup AON_ACOMP_ID_TYPE + * @{ + */ +#define IS_AON_ACOMP_ID_TYPE(type) (((type) == AON_ACOMP0_ID) || \ + ((type) == AON_ACOMP1_ID)) + +/** @defgroup AON_ACOMP_LEVEL_FACTOR_TYPE + * @{ + */ +#define IS_AON_ACOMP_LEVEL_FACTOR_TYPE(type) (((type) == AON_ACOMP_LEVEL_FACTOR_0P25) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_0P5) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_0P75) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_1)) + +/** @defgroup AON_ACOMP_CHAN_TYPE + * @{ + */ +#define IS_AON_ACOMP_CHAN_TYPE(type) (((type) == AON_ACOMP_CHAN_ADC0) || \ + ((type) == AON_ACOMP_CHAN_ADC1) || \ + ((type) == AON_ACOMP_CHAN_ADC2) || \ + ((type) == AON_ACOMP_CHAN_ADC3) || \ + ((type) == AON_ACOMP_CHAN_ADC4) || \ + ((type) == AON_ACOMP_CHAN_ADC5) || \ + ((type) == AON_ACOMP_CHAN_ADC6) || \ + ((type) == AON_ACOMP_CHAN_ADC7) || \ + ((type) == AON_ACOMP_CHAN_DACA) || \ + ((type) == AON_ACOMP_CHAN_DACB) || \ + ((type) == AON_ACOMP_CHAN_VREF_1P2V) || \ + ((type) == AON_ACOMP_CHAN_0P375VBAT_NOT_IMP) || \ + ((type) == AON_ACOMP_CHAN_0P25VBAT) || \ + ((type) == AON_ACOMP_CHAN_0P1875VBAT) || \ + ((type) == AON_ACOMP_CHAN_0P3125VBAT) || \ + ((type) == AON_ACOMP_CHAN_VSS)) + +/** @defgroup AON_ACOMP_BIAS_PROG_TYPE + * @{ + */ +#define IS_AON_ACOMP_BIAS_PROG_TYPE(type) (((type) == AON_ACOMP_BIAS_POWER_MODE1) || \ + ((type) == AON_ACOMP_BIAS_POWER_MODE2) || \ + ((type) == AON_ACOMP_BIAS_POWER_MODE3) || \ + ((type) == AON_ACOMP_BIAS_POWER_NONE)) + +/** @defgroup AON_ACOMP_HYSTERESIS_VOLT_TYPE + * @{ + */ +#define IS_AON_ACOMP_HYSTERESIS_VOLT_TYPE(type) (((type) == AON_ACOMP_HYSTERESIS_VOLT_NONE) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_10MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_20MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_30MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_40MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_50MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_60MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_70MV)) + +/*@} end of group ACOMP_Public_Constants */ + +/** @defgroup ACOMP_Public_Macros + * @{ + */ + +/*@} end of group ACOMP_Public_Macros */ + +/** @defgroup ACOMP_Public_Functions + * @{ + */ +void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg); +void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo); +BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo); + +/*@} end of group ACOMP_Public_Functions */ + +/*@} end of group ACOMP */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_ACOMP_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..c4becd3e20636da436bb0364bae34dbdb56e8a40 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h @@ -0,0 +1,552 @@ +/** + ****************************************************************************** + * @file bl702_adc.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_ADC_H__ +#define __BL702_ADC_H__ + +#include "aon_reg.h" +#include "gpip_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Public_Types + * @{ + */ + +/** + * @brief ADC channel type definition + */ +typedef enum { + ADC_CHAN0, /*!< ADC channel 0 */ + ADC_CHAN1, /*!< ADC channel 1 */ + ADC_CHAN2, /*!< ADC channel 2 */ + ADC_CHAN3, /*!< ADC channel 3 */ + ADC_CHAN4, /*!< ADC channel 4 */ + ADC_CHAN5, /*!< ADC channel 5 */ + ADC_CHAN6, /*!< ADC channel 6 */ + ADC_CHAN7, /*!< ADC channel 7 */ + ADC_CHAN8, /*!< ADC channel 8 */ + ADC_CHAN9, /*!< ADC channel 9 */ + ADC_CHAN10, /*!< ADC channel 10 */ + ADC_CHAN11, /*!< ADC channel 11 */ + ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */ + ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */ + ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */ + ADC_CHAN_TSEN_N, /*!< TSenn, ADC channel 15 */ + ADC_CHAN_VREF, /*!< Vref, ADC channel 16 */ + ADC_CHAN_DCTEST, /*!< DCTest, ADC channel 17 */ + ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */ + ADC_CHAN_SENP3, /*!< SenVP3, ADC channel 19 */ + ADC_CHAN_SENP2, /*!< SenVP2, ADC channel 20 */ + ADC_CHAN_SENP1, /*!< SenVP1, ADC channel 21 */ + ADC_CHAN_SENP0, /*!< SenVP0, ADC channel 22 */ + ADC_CHAN_GND, /*!< GND, ADC channel 23 */ +} ADC_Chan_Type; + +/** + * @brief ADC V18 selection type definition + */ +typedef enum { + ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */ + ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */ + ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */ + ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */ +} ADC_V18_SEL_Type; + +/** + * @brief ADC V11 selection type definition + */ +typedef enum { + ADC_V11_SEL_1P0V, /*!< V11 select 1.0V */ + ADC_V11_SEL_1P1V, /*!< V11 select 1.1V */ + ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */ + ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */ +} ADC_V11_SEL_Type; + +/** + * @brief ADC clock type definition + */ +typedef enum { + ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ + ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ + ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ + ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ + ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ + ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ + ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ + ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ +} ADC_CLK_Type; + +/** + * @brief ADC conversion speed type definition + */ +typedef enum { + ADC_DELAY_SEL_0, /*!< Select delay 0 */ + ADC_DELAY_SEL_1, /*!< Select delay 1 */ + ADC_DELAY_SEL_2, /*!< Select delay 2 */ + ADC_DELAY_SEL_3, /*!< Select delay 3 */ + ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */ + ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */ + ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */ + ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */ +} ADC_DELAY_SEL_Type; + +/** + * @brief ADC PGA gain type definition + */ +typedef enum { + ADC_PGA_GAIN_NONE, /*!< No PGA gain */ + ADC_PGA_GAIN_1, /*!< PGA gain 1 */ + ADC_PGA_GAIN_2, /*!< PGA gain 2 */ + ADC_PGA_GAIN_4, /*!< PGA gain 4 */ + ADC_PGA_GAIN_8, /*!< PGA gain 8 */ + ADC_PGA_GAIN_16, /*!< PGA gain 16 */ + ADC_PGA_GAIN_32, /*!< PGA gain 32 */ +} ADC_PGA_GAIN_Type; + +/** + * @brief ADC analog portion low power mode selection type definition + */ +typedef enum { + ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */ + ADC_BIAS_SEL_AON_BANDGAP, /*!< ADC current from aon bandgap for HBN mode */ +} ADC_BIAS_SEL_Type; + +/** + * @brief ADC chop mode type definition + */ +typedef enum { + ADC_CHOP_MOD_ALL_OFF, /*!< all off */ + ADC_CHOP_MOD_AZ_ON, /*!< Vref AZ on */ + ADC_CHOP_MOD_AZ_PGA_ON, /*!< Vref AZ and PGA chop on */ + ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */ +} ADC_CHOP_MOD_Type; + +/** + * @brief ADC audio PGA output common mode control type definition + */ +typedef enum { + ADC_PGA_VCM_1V, /*!< ADC VCM=1V */ + ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */ + ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */ + ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */ +} ADC_PGA_VCM_Type; + +/** + * @brief ADC tsen diode mode type definition + */ +typedef enum { + ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */ + ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */ +} ADC_TSEN_MOD_Type; + +/** + * @brief ADC voltage reference type definition + */ +typedef enum { + ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */ + ADC_VREF_2P0V, /*!< ADC select 2V as reference voltage */ +} ADC_VREF_Type; + +/** + * @brief ADC signal input type definition + */ +typedef enum { + ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */ + ADC_INPUT_DIFF, /*!< ADC signal is differential */ +} ADC_SIG_INPUT_Type; + +/** + * @brief ADC data width type definition + */ +typedef enum { + ADC_DATA_WIDTH_12, /*!< ADC 12 bits */ + ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ + ADC_DATA_WIDTH_16_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */ + ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ + ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ +} ADC_Data_Width_Type; + +/** + * @brief ADC micboost 32db type definition + */ +typedef enum { + ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */ + ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */ +} ADC_MICBOOST_DB_Type; + +/** + * @brief ADC pga2 gain type definition + */ +typedef enum { + ADC_PGA2_GAIN_0DB, /*!< MIC pga2 gain 0db */ + ADC_PGA2_GAIN_6DB, /*!< MIC pga2 gain 6db */ + ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */ + ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */ +} ADC_PGA2_GAIN_Type; + +/** + * @brief ADC mic mode type definition + */ +typedef enum { + ADC_MIC_MODE_SINGLE, /*!< MIC single mode */ + ADC_MIC_MODE_DIFF, /*!< MIC diff mode */ +} ADC_MIC_MODE_Type; + +/** + * @brief ADC mic type definition + */ +typedef struct +{ + ADC_MICBOOST_DB_Type micboostDb; /*!< MIC boost db */ + ADC_PGA2_GAIN_Type micPga2Gain; /*!< MIC pga2 gain */ + ADC_MIC_MODE_Type mic1Mode; /*!< MIC1 single or diff */ + ADC_MIC_MODE_Type mic2Mode; /*!< MIC2 single or diff */ + BL_Fun_Type dwaEn; /*!< Improve dynamic performance */ + BL_Fun_Type micboostBypassEn; /*!< MIC boost amp bypass enable or disable */ + BL_Fun_Type micPgaEn; /*!< MIC pga enable or disable */ + BL_Fun_Type micBiasEn; /*!< MIC bias enable or disable */ +} ADC_MIC_Type; + +/** + * @brief ADC configuration type definition + */ +typedef struct +{ + ADC_V18_SEL_Type v18Sel; /*!< ADC 1.8V select */ + ADC_V11_SEL_Type v11Sel; /*!< ADC 1.1V select */ + ADC_CLK_Type clkDiv; /*!< Clock divider */ + ADC_PGA_GAIN_Type gain1; /*!< PGA gain 1 */ + ADC_PGA_GAIN_Type gain2; /*!< PGA gain 2 */ + ADC_CHOP_MOD_Type chopMode; /*!< ADC chop mode select */ + ADC_BIAS_SEL_Type biasSel; /*!< ADC current form main bandgap or aon bandgap */ + ADC_PGA_VCM_Type vcm; /*!< ADC VCM value */ + ADC_VREF_Type vref; /*!< ADC voltage reference */ + ADC_SIG_INPUT_Type inputMode; /*!< ADC input signal type */ + ADC_Data_Width_Type resWidth; /*!< ADC resolution and oversample rate */ + BL_Fun_Type offsetCalibEn; /*!< Offset calibration enable */ + int16_t offsetCalibVal; /*!< Offset calibration value */ +} ADC_CFG_Type; + +/** + * @brief ADC configuration type definition + */ +typedef struct +{ + int8_t posChan; /*!< Positive channel */ + int8_t negChan; /*!< Negative channel */ + uint16_t value; /*!< ADC value */ + float volt; /*!< ADC voltage result */ +} ADC_Result_Type; + +/** + * @brief ADC FIFO threshold type definition + */ +typedef enum { + ADC_FIFO_THRESHOLD_1, /*!< ADC FIFO threshold is 1 */ + ADC_FIFO_THRESHOLD_4, /*!< ADC FIFO threshold is 4 */ + ADC_FIFO_THRESHOLD_8, /*!< ADC FIFO threshold is 8 */ + ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */ +} ADC_FIFO_Threshold_Type; + +/** + * @brief ADC interrupt type definition + */ +typedef enum { + ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */ + ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */ + ADC_INT_FIFO_UNDERRUN, /*!< ADC FIFO underrun interrupt */ + ADC_INT_FIFO_OVERRUN, /*!< ADC FIFO overrun interrupt */ + ADC_INT_ADC_READY, /*!< ADC data ready interrupt */ + ADC_INT_FIFO_READY, /*!< ADC FIFO count upper to threhold interrupt */ + ADC_INT_ALL, /*!< ADC all the interrupt */ +} ADC_INT_Type; + +/** + * @brief ADC FIFO configuration structure type definition + */ +typedef struct +{ + ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */ + BL_Fun_Type dmaEn; /*!< ADC DMA enable */ +} ADC_FIFO_Cfg_Type; + +/** + * @brief ADC REG GAIN CAL + */ +typedef struct +{ + BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */ + uint16_t adcgainCoeffVal; /*!< ADC_Gain_Coeff value */ + float coe; /*!< ADC_Gain_Coeff result */ +} ADC_Gain_Coeff_Type; + +/*@} end of group ADC_Public_Types */ + +/** @defgroup ADC_Public_Constants + * @{ + */ + +/** @defgroup ADC_CHAN_TYPE + * @{ + */ +#define IS_ADC_CHAN_TYPE(type) (((type) == ADC_CHAN0) || \ + ((type) == ADC_CHAN1) || \ + ((type) == ADC_CHAN2) || \ + ((type) == ADC_CHAN3) || \ + ((type) == ADC_CHAN4) || \ + ((type) == ADC_CHAN5) || \ + ((type) == ADC_CHAN6) || \ + ((type) == ADC_CHAN7) || \ + ((type) == ADC_CHAN8) || \ + ((type) == ADC_CHAN9) || \ + ((type) == ADC_CHAN10) || \ + ((type) == ADC_CHAN11) || \ + ((type) == ADC_CHAN_DAC_OUTA) || \ + ((type) == ADC_CHAN_DAC_OUTB) || \ + ((type) == ADC_CHAN_TSEN_P) || \ + ((type) == ADC_CHAN_TSEN_N) || \ + ((type) == ADC_CHAN_VREF) || \ + ((type) == ADC_CHAN_DCTEST) || \ + ((type) == ADC_CHAN_VABT_HALF) || \ + ((type) == ADC_CHAN_SENP3) || \ + ((type) == ADC_CHAN_SENP2) || \ + ((type) == ADC_CHAN_SENP1) || \ + ((type) == ADC_CHAN_SENP0) || \ + ((type) == ADC_CHAN_GND)) + +/** @defgroup ADC_V18_SEL_TYPE + * @{ + */ +#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || \ + ((type) == ADC_V18_SEL_1P72V) || \ + ((type) == ADC_V18_SEL_1P82V) || \ + ((type) == ADC_V18_SEL_1P92V)) + +/** @defgroup ADC_V11_SEL_TYPE + * @{ + */ +#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || \ + ((type) == ADC_V11_SEL_1P1V) || \ + ((type) == ADC_V11_SEL_1P18V) || \ + ((type) == ADC_V11_SEL_1P26V)) + +/** @defgroup ADC_CLK_TYPE + * @{ + */ +#define IS_ADC_CLK_TYPE(type) (((type) == ADC_CLK_DIV_1) || \ + ((type) == ADC_CLK_DIV_4) || \ + ((type) == ADC_CLK_DIV_8) || \ + ((type) == ADC_CLK_DIV_12) || \ + ((type) == ADC_CLK_DIV_16) || \ + ((type) == ADC_CLK_DIV_20) || \ + ((type) == ADC_CLK_DIV_24) || \ + ((type) == ADC_CLK_DIV_32)) + +/** @defgroup ADC_DELAY_SEL_TYPE + * @{ + */ +#define IS_ADC_DELAY_SEL_TYPE(type) (((type) == ADC_DELAY_SEL_0) || \ + ((type) == ADC_DELAY_SEL_1) || \ + ((type) == ADC_DELAY_SEL_2) || \ + ((type) == ADC_DELAY_SEL_3) || \ + ((type) == ADC_DELAY_SEL_4) || \ + ((type) == ADC_DELAY_SEL_5) || \ + ((type) == ADC_DELAY_SEL_6) || \ + ((type) == ADC_DELAY_SEL_7)) + +/** @defgroup ADC_PGA_GAIN_TYPE + * @{ + */ +#define IS_ADC_PGA_GAIN_TYPE(type) (((type) == ADC_PGA_GAIN_NONE) || \ + ((type) == ADC_PGA_GAIN_1) || \ + ((type) == ADC_PGA_GAIN_2) || \ + ((type) == ADC_PGA_GAIN_4) || \ + ((type) == ADC_PGA_GAIN_8) || \ + ((type) == ADC_PGA_GAIN_16) || \ + ((type) == ADC_PGA_GAIN_32)) + +/** @defgroup ADC_BIAS_SEL_TYPE + * @{ + */ +#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || \ + ((type) == ADC_BIAS_SEL_AON_BANDGAP)) + +/** @defgroup ADC_CHOP_MOD_TYPE + * @{ + */ +#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || \ + ((type) == ADC_CHOP_MOD_AZ_ON) || \ + ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || \ + ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON)) + +/** @defgroup ADC_PGA_VCM_TYPE + * @{ + */ +#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || \ + ((type) == ADC_PGA_VCM_1P2V) || \ + ((type) == ADC_PGA_VCM_1P4V) || \ + ((type) == ADC_PGA_VCM_1P6V)) + +/** @defgroup ADC_TSEN_MOD_TYPE + * @{ + */ +#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || \ + ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE)) + +/** @defgroup ADC_VREF_TYPE + * @{ + */ +#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P3V) || \ + ((type) == ADC_VREF_2V)) + +/** @defgroup ADC_SIG_INPUT_TYPE + * @{ + */ +#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || \ + ((type) == ADC_INPUT_DIFF)) + +/** @defgroup ADC_DATA_WIDTH_TYPE + * @{ + */ +#define IS_ADC_DATA_WIDTH_TYPE(type) (((type) == ADC_DATA_WIDTH_12) || \ + ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_64_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) + +/** @defgroup ADC_MICBOOST_DB_TYPE + * @{ + */ +#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || \ + ((type) == ADC_MICBOOST_DB_32DB)) + +/** @defgroup ADC_PGA2_GAIN_TYPE + * @{ + */ +#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || \ + ((type) == ADC_PGA2_GAIN_6DB) || \ + ((type) == ADC_PGA2_GAIN_N6DB) || \ + ((type) == ADC_PGA2_GAIN_12DB)) + +/** @defgroup ADC_MIC_MODE_TYPE + * @{ + */ +#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || \ + ((type) == ADC_MIC_MODE_DIFF)) + +/** @defgroup ADC_FIFO_THRESHOLD_TYPE + * @{ + */ +#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || \ + ((type) == ADC_FIFO_THRESHOLD_4) || \ + ((type) == ADC_FIFO_THRESHOLD_8) || \ + ((type) == ADC_FIFO_THRESHOLD_16)) + +/** @defgroup ADC_INT_TYPE + * @{ + */ +#define IS_ADC_INT_TYPE(type) (((type) == ADC_INT_POS_SATURATION) || \ + ((type) == ADC_INT_NEG_SATURATION) || \ + ((type) == ADC_INT_FIFO_UNDERRUN) || \ + ((type) == ADC_INT_FIFO_OVERRUN) || \ + ((type) == ADC_INT_ADC_READY) || \ + ((type) == ADC_INT_FIFO_READY) || \ + ((type) == ADC_INT_ALL)) + +/*@} end of group ADC_Public_Constants */ + +/** @defgroup ADC_Public_Macros + * @{ + */ + +/*@} end of group ADC_Public_Macros */ + +/** @defgroup ADC_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void GPADC_DMA_IRQHandler(void); +#endif +void ADC_Vbat_Enable(void); +void ADC_Vbat_Disable(void); +void ADC_Reset(void); +void ADC_Enable(void); +void ADC_Disable(void); +void ADC_Init(ADC_CFG_Type *cfg); +void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn); +void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn); +void ADC_Start(void); +void ADC_Stop(void); +void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg); +uint8_t ADC_Get_FIFO_Count(void); +BL_Sts_Type ADC_FIFO_Is_Empty(void); +BL_Sts_Type ADC_FIFO_Is_Full(void); +void ADC_FIFO_Clear(void); +uint32_t ADC_Read_FIFO(void); +void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result); +void ADC_IntClr(ADC_INT_Type intType); +BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType); +BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType); +void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun); +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); +void ADC_SET_TSVBE_LOW(void); +void ADC_SET_TSVBE_HIGH(void); +void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod); +void ADC_Tsen_Enable(void); +void ADC_Tsen_Disable(void); +void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal); +BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config); +void ADC_MIC_Bias_Disable(void); +void ADC_MIC_Bias_Enable(void); +BL_Err_Type ADC_Trim_TSEN(uint16_t *tsen_offset); +BL_Err_Type ADC_Gain_Trim(void); +uint32_t ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg); +float TSEN_Get_Temp(uint32_t tsen_offset); + +/*@} end of group ADC_Public_Functions */ + +/*@} end of group ADC */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_ADC_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_aon.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_aon.h new file mode 100644 index 0000000000000000000000000000000000000000..db92d5a99e5cda3ff4bb4e372c73ffa7110e3cc3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_aon.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file bl702_aon.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_AON_H__ +#define __BL702_AON_H__ + +#include "aon_reg.h" +#include "glb_reg.h" +#include "hbn_reg.h" +#include "pds_reg.h" +#include "bl702_ef_ctrl.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Public_Types + * @{ + */ + +/*@} end of group AON_Public_Types */ + +/** @defgroup AON_Public_Constants + * @{ + */ + +/*@} end of group AON_Public_Constants */ + +/** @defgroup AON_Public_Macros + * @{ + */ + +/*@} end of group AON_Public_Macros */ + +/** @defgroup AON_Public_Functions + * @{ + */ +/*----------*/ +BL_Err_Type AON_Power_On_MBG(void); +BL_Err_Type AON_Power_Off_MBG(void); +/*----------*/ +BL_Err_Type AON_Power_On_XTAL(void); +BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut); +uint8_t AON_Get_Xtal_CapCode(void); +BL_Err_Type AON_Power_Off_XTAL(void); +/*----------*/ +BL_Err_Type AON_Power_On_BG(void); +BL_Err_Type AON_Power_Off_BG(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO11_SOC(void); +BL_Err_Type AON_Power_Off_LDO11_SOC(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO15_RF(void); +BL_Err_Type AON_Power_Off_LDO15_RF(void); +/*----------*/ +BL_Err_Type AON_Power_On_SFReg(void); +BL_Err_Type AON_Power_Off_SFReg(void); +/*----------*/ +BL_Err_Type AON_LowPower_Enter_PDS0(void); +BL_Err_Type AON_LowPower_Exit_PDS0(void); +/*----------*/ +BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay); + +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_AON_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_cam.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_cam.h new file mode 100644 index 0000000000000000000000000000000000000000..fab888891f3585de9197dc01959406cbec684c12 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_cam.h @@ -0,0 +1,293 @@ +/** + ****************************************************************************** + * @file bl702_cam.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_CAM_H__ +#define __BL702_CAM_H__ + +#include "cam_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup CAM + * @{ + */ + +/** @defgroup CAM_Public_Types + * @{ + */ + +/** + * @brief CAM AHB burst type definition + */ +typedef enum { + CAM_BURST_TYPE_SINGLE, /*!< Camera AHB burst type:single */ + CAM_BURST_TYPE_INCR4, /*!< Camera AHB burst type:incrementing 4 */ + CAM_BURST_TYPE_INCR8, /*!< Camera AHB burst type:incrementing 8 */ + CAM_BURST_TYPE_INCR16, /*!< Camera AHB burst type:incrementing 16 */ +} CAM_Burst_Type; + +/** + * @brief CAM software mode type definition + */ +typedef enum { + CAM_SW_MODE_AUTO, /*!< CAM auto mode with mjpeg */ + CAM_SW_MODE_MANUAL, /*!< CAM manual mode(software mode) */ +} CAM_SW_Mode_Type; + +/** + * @brief CAM frame mode type definition + */ +typedef enum { + CAM_PLANAR_MODE, /*!< CAM planar mode(YYYY.../UVUV...) */ + CAM_INTERLEAVE_MODE, /*!< CAM interleave mode(YUYVYUYV...) */ +} CAM_Frame_Mode_Type; + +/** + * @brief CAM YUV mode type definition + */ +typedef enum { + CAM_YUV422, /*!< CAM YUV422 mode */ + CAM_YUV420_EVEN, /*!< CAM YUV420 mode(raw data:YUYV YUYV..., processed data:YUYV YY...) which dropped odd pix data in + odd rows */ + CAM_YUV420_ODD, /*!< CAM YUV420 mode(raw data:UYVY UYVY..., processed data:UYVY YY...) which dropped even pix data + in odd rows */ + CAM_YUV400_EVEN, /*!< CAM YUV400 mode(raw data:YUYV YUYV..., processed data:YY YY...) which dropped odd pix data */ + CAM_YUV400_ODD, /*!< CAM YUV400 mode(raw data:UYVY UYVY..., processed data:YY YY...) which dropped even pix data */ +} CAM_YUV_Mode_Type; + +/** + * @brief CAM line active polarity type definition + */ +typedef enum { + CAM_LINE_ACTIVE_POLARITY_LOW, /*!< CAM line active polarity low */ + CAM_LINE_ACTIVE_POLARITY_HIGH, /*!< CAM line active polarity high */ +} CAM_Line_Active_Pol; + +/** + * @brief CAM frame active polarity type definition + */ +typedef enum { + CAM_FRAME_ACTIVE_POLARITY_LOW, /*!< CAM frame active polarity low */ + CAM_FRAME_ACTIVE_POLARITY_HIGH, /*!< CAM frame active polarity high */ +} CAM_Frame_Active_Pol; + +/** + * @brief CAM sensor mode type definition + */ +typedef enum { + CAM_SENSOR_MODE_V_AND_H, /*!< CAM sensor type v and h */ + CAM_SENSOR_MODE_V_OR_H, /*!< CAM sensor type v or h */ + CAM_SENSOR_MODE_V, /*!< CAM sensor type v */ + CAM_SENSOR_MODE_H, /*!< CAM sensor type h */ +} CAM_Sensor_Mode_Type; + +/** + * @brief CAM interrupt type definition + */ +typedef enum { + CAM_INT_NORMAL_0, /*!< Interleave mode: normal write interrupt, planar mode:even byte normal write interrupt */ + CAM_INT_NORMAL_1, /*!< Interleave mode: no use, planar mode:odd byte normal write interrupt */ + CAM_INT_MEMORY_OVERWRITE_0, /*!< Interleave mode: memory overwrite interrupt, planar mode:even byte memory overwrite interrupt */ + CAM_INT_MEMORY_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte memory overwrite interrupt */ + CAM_INT_FRAME_OVERWRITE_0, /*!< Interleave mode: frame overwrite interrupt, planar mode:even byte frame overwrite interrupt */ + CAM_INT_FRAME_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte frame overwrite interrupt */ + CAM_INT_FIFO_OVERWRITE_0, /*!< Interleave mode: fifo overwrite interrupt, planar mode:even byte fifo overwrite interrupt */ + CAM_INT_FIFO_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte fifo overwrite interrupt */ + CAM_INT_VSYNC_CNT_ERROR, /*!< Vsync valid line count non-match interrupt */ + CAM_INT_HSYNC_CNT_ERROR, /*!< Hsync valid pixel count non-match interrupt */ + CAM_INT_ALL, /*!< All of interrupt */ +} CAM_INT_Type; + +/** + * @brief CAM configuration strcut definition + */ +typedef struct +{ + CAM_SW_Mode_Type swMode; /*!< Software mode */ + uint8_t swIntCnt; /*!< Set frame count to issue interrupt at software mode */ + CAM_Frame_Mode_Type frameMode; /*!< Frame mode */ + CAM_YUV_Mode_Type yuvMode; /*!< YUV mode */ + CAM_Frame_Active_Pol framePol; /*!< Frame polarity */ + CAM_Line_Active_Pol linePol; /*!< Line polarity */ + CAM_Burst_Type burstType; /*!< AHB burst type */ + CAM_Sensor_Mode_Type camSensorMode; /*!< CAM sensor mode */ + uint8_t waitCount; /*!< cycles in FSM wait mode, default value:0x40 */ + uint32_t memStart0; /*!< Interleave mode:data start address, planar mode:even byte start address */ + uint32_t memSize0; /*!< Interleave mode:memory size in burst, planar mode:even byte memory size in burst */ + uint32_t frameSize0; /*!< Interleave mode:frame size in burst, planar mode:even byte frame size in burst */ + uint32_t memStart1; /*!< Interleave mode:no use, planar mode:odd byte start address */ + uint32_t memSize1; /*!< Interleave mode:no use, planar mode:odd byte memory size in burst */ + uint32_t frameSize1; /*!< Interleave mode:no use, planar mode:odd byte frame size in burst */ +} CAM_CFG_Type; + +/** + * @brief CAM interleave mode frame information strcut definition + */ +typedef struct +{ + uint8_t validFrames; /*!< Valid frames */ + uint32_t curFrameAddr; /*!< Current frame address */ + uint32_t curFrameBytes; /*!< Current frame bytes */ + uint32_t status; /*!< CAM module status */ +} CAM_Interleave_Frame_Info; + +/** + * @brief CAM planar mode frame information strcut definition + */ +typedef struct +{ + uint8_t validFrames0; /*!< Even byte frame counts in memory */ + uint8_t validFrames1; /*!< Odd byte frame counts in memory */ + uint32_t curFrameAddr0; /*!< Current even frame address */ + uint32_t curFrameAddr1; /*!< Current odd frame address */ + uint32_t curFrameBytes0; /*!< Current even frame bytes */ + uint32_t curFrameBytes1; /*!< Current odd frame bytes */ + uint32_t status; /*!< CAM module status */ +} CAM_Planar_Frame_Info; + +/*@} end of group CAM_Public_Types */ + +/** @defgroup CAM_Public_Constants + * @{ + */ + +/** @defgroup CAM_BURST_TYPE + * @{ + */ +#define IS_CAM_BURST_TYPE(type) (((type) == CAM_BURST_TYPE_SINGLE) || \ + ((type) == CAM_BURST_TYPE_INCR4) || \ + ((type) == CAM_BURST_TYPE_INCR8) || \ + ((type) == CAM_BURST_TYPE_INCR16)) + +/** @defgroup CAM_SW_MODE_TYPE + * @{ + */ +#define IS_CAM_SW_MODE_TYPE(type) (((type) == CAM_SW_MODE_AUTO) || \ + ((type) == CAM_SW_MODE_MANUAL)) + +/** @defgroup CAM_FRAME_MODE_TYPE + * @{ + */ +#define IS_CAM_FRAME_MODE_TYPE(type) (((type) == CAM_PLANAR_MODE) || \ + ((type) == CAM_INTERLEAVE_MODE)) + +/** @defgroup CAM_YUV_MODE_TYPE + * @{ + */ +#define IS_CAM_YUV_MODE_TYPE(type) (((type) == CAM_YUV422) || \ + ((type) == CAM_YUV420_EVEN) || \ + ((type) == CAM_YUV420_ODD) || \ + ((type) == CAM_YUV400_EVEN) || \ + ((type) == CAM_YUV400_ODD)) + +/** @defgroup CAM_LINE_ACTIVE_POL + * @{ + */ +#define IS_CAM_LINE_ACTIVE_POL(type) (((type) == CAM_LINE_ACTIVE_POLARITY_LOW) || \ + ((type) == CAM_LINE_ACTIVE_POLARITY_HIGH)) + +/** @defgroup CAM_FRAME_ACTIVE_POL + * @{ + */ +#define IS_CAM_FRAME_ACTIVE_POL(type) (((type) == CAM_FRAME_ACTIVE_POLARITY_LOW) || \ + ((type) == CAM_FRAME_ACTIVE_POLARITY_HIGH)) + +/** @defgroup CAM_SENSOR_MODE_TYPE + * @{ + */ +#define IS_CAM_SENSOR_MODE_TYPE(type) (((type) == CAM_SENSOR_MODE_V_AND_H) || \ + ((type) == CAM_SENSOR_MODE_V_OR_H) || \ + ((type) == CAM_SENSOR_MODE_V) || \ + ((type) == CAM_SENSOR_MODE_H)) + +/** @defgroup CAM_INT_TYPE + * @{ + */ +#define IS_CAM_INT_TYPE(type) (((type) == CAM_INT_NORMAL_0) || \ + ((type) == CAM_INT_NORMAL_1) || \ + ((type) == CAM_INT_MEMORY_OVERWRITE_0) || \ + ((type) == CAM_INT_MEMORY_OVERWRITE_1) || \ + ((type) == CAM_INT_FRAME_OVERWRITE_0) || \ + ((type) == CAM_INT_FRAME_OVERWRITE_1) || \ + ((type) == CAM_INT_FIFO_OVERWRITE_0) || \ + ((type) == CAM_INT_FIFO_OVERWRITE_1) || \ + ((type) == CAM_INT_VSYNC_CNT_ERROR) || \ + ((type) == CAM_INT_HSYNC_CNT_ERROR) || \ + ((type) == CAM_INT_ALL)) + +/*@} end of group CAM_Public_Constants */ + +/** @defgroup CAM_Public_Macros + * @{ + */ + +/*@} end of group CAM_Public_Macros */ + +/** @defgroup CAM_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void CAM_IRQHandler(void); +#endif +void CAM_Init(CAM_CFG_Type *cfg); +void CAM_Deinit(void); +void CAM_Enable(void); +void CAM_Disable(void); +void CAM_Clock_Gate(BL_Fun_Type enable); +void CAM_Hsync_Crop(uint16_t start, uint16_t end); +void CAM_Vsync_Crop(uint16_t start, uint16_t end); +void CAM_Set_Hsync_Total_Count(uint16_t count); +void CAM_Set_Vsync_Total_Count(uint16_t count); +void CAM_Interleave_Get_Frame_Info(CAM_Interleave_Frame_Info *info); +void CAM_Planar_Get_Frame_Info(CAM_Planar_Frame_Info *info); +uint8_t CAM_Get_Frame_Count_0(void); +uint8_t CAM_Get_Frame_Count_1(void); +void CAM_Interleave_Pop_Frame(void); +void CAM_Planar_Pop_Frame(void); +void CAM_IntMask(CAM_INT_Type intType, BL_Mask_Type intMask); +void CAM_IntClr(CAM_INT_Type intType); +void CAM_Int_Callback_Install(CAM_INT_Type intType, intCallback_Type *cbFun); +void CAM_HW_Mode_Wrap(BL_Fun_Type enable); + +/*@} end of group CAM_Public_Functions */ + +/*@} end of group CAM */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_CAM_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_clock.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_clock.h new file mode 100644 index 0000000000000000000000000000000000000000..b11569f987208caa262b334ef48a6709ff3a1dbf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_clock.h @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * @file bl702_glb.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_GLB_H__ +#define __BL702_GLB_H__ + +#include "glb_reg.h" +#include "bl702_hbn.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Public_Types + * @{ + */ + +/** + * @brief System clock type definition + */ +typedef enum { + BL_SYSTEM_CLOCK_FCLK, /*!< Fast clock/CPU clock */ + BL_SYSTEM_CLOCK_BCLK, /*!< BUS clock */ + BL_SYSTEM_CLOCK_F32K, /*!< F32K clock */ + BL_SYSTEM_CLOCK_XCLK, /*!< XCLK:RC32M or XTAL */ + BL_SYSTEM_CLOCK_XTAL, /*!< XTAL clock */ + BL_SYSTEM_CLOCK_MAX, /*!< MAX type of system clock */ +} BL_System_Clock_Type; + +/** + * @brief SOC clock config type + */ +typedef struct +{ + uint16_t systemClock[BL_SYSTEM_CLOCK_MAX]; /*!< System lock value */ + uint16_t peripheralClock[BL_AHB_SLAVE1_MAX]; /*!< Pewripherals clock value */ + uint32_t i2sClock; /*!< I2S clock */ +} Clock_Cfg_Type; + +/*@} end of group GLB_Public_Types */ + +/** @defgroup GLB_Public_Constants + * @{ + */ + +/** @defgroup BL_SYSTEM_CLOCK_TYPE + * @{ + */ +#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_FCLK) || \ + ((type) == BL_SYSTEM_CLOCK_BCLK) || \ + ((type) == BL_SYSTEM_CLOCK_F32K) || \ + ((type) == BL_SYSTEM_CLOCK_XCLK) || \ + ((type) == BL_SYSTEM_CLOCK_XTAL) || \ + ((type) == BL_SYSTEM_CLOCK_MAX)) + +/*@} end of group GLB_Public_Constants */ + +/** @defgroup GLB_Public_Macros + * @{ + */ + +/*@} end of group GLB_Public_Macros */ + +/** @defgroup GLB_Public_Functions + * @{ + */ +void Clock_System_Clock_Set(BL_System_Clock_Type type, uint32_t clock); +void Clock_Peripheral_Clock_Set(BL_AHB_Slave1_Type type, uint32_t clock); +uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type); +uint32_t Clock_Peripheral_Clock_Get(BL_AHB_Slave1_Type type); + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_GLB_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_common.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_common.h new file mode 100644 index 0000000000000000000000000000000000000000..923ab3f78cfe32d8de2cc5758994624f0c0caa5a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_common.h @@ -0,0 +1,61 @@ +#ifndef __BL702_COMMON_H__ +#define __BL702_COMMON_H__ + +#include "bl702.h" +#include "bflb_platform.h" + +/** @addtogroup BL606_Peripheral_Driver + * @{ + */ + +/** @addtogroup COMMON + * @{ + */ + +/** @defgroup COMMON_Public_Types + * @{ + */ + +/*@} end of group COMMON_Public_Types */ + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** @defgroup DRIVER_INT_PERIPH + * @{ + */ +#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) + +/*@} end of group DRIVER_INT_PERIPH */ + +/** @defgroup DRIVER_INT_MASK + * @{ + */ +#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) + +/*@} end of group COMMON_Public_Constants */ + +/** @defgroup COMMON_Public_Macros + * @{ + */ + +/*@} end of group DRIVER_Public_Macro */ + +/** @defgroup DRIVER_Public_FunctionDeclaration + * @brief DRIVER functions declaration + * @{ + */ + +#define ARCH_Delay_US BL702_Delay_US +#define ARCH_Delay_MS BL702_Delay_MS +#define arch_delay_us BL702_Delay_US +#define arch_delay_ms BL702_Delay_MS + +void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); +void ASM_Delay_Us(uint32_t core, uint32_t cnt); +void BL702_Delay_US(uint32_t cnt); +void BL702_Delay_MS(uint32_t cnt); +/*@} end of group DRIVER_COMMON */ + +#endif /* __BL702_COMMON_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dac.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..df301db864f78f054255a6f496a3cbd3758e9dcc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dac.h @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file bl702_dac.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_DAC_H__ +#define __BL702_DAC_H__ + +#include "aon_reg.h" +#include "glb_reg.h" +#include "gpip_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Public_Types + * @{ + */ + +/** + * @brief DAC reference voltage definition + */ +typedef enum { + GLB_DAC_REF_SEL_INTERNAL, /*!< DAC reference select internal */ + GLB_DAC_REF_SEL_EXTERNAL, /*!< DAC reference select external */ +} GLB_DAC_Ref_Sel_Type; + +/** + * @brief DAC reference voltage definition + */ +typedef enum { + GLB_DAC_Output_Volt_0P2_1, /*!< DAC output voltage is 0.2-1V */ + GLB_DAC_Output_Volt_0P225_1P425, /*!< DAC output voltage is 0.225-1.425V */ + GLB_DAC_Output_Volt_RESEVED, /*!< DAC output voltage is 0.225-1.425V */ + GLB_DAC_Output_Volt_0P2_1P8, /*!< DAC output voltage is 0.2-1.8V */ +} GLB_DAC_Output_Volt_Range_Type; + +/** + * @brief DAC channel type definition + */ +typedef enum { + GLB_DAC_CHAN0, /*!< DAC channel 0 */ + GLB_DAC_CHAN1, /*!< DAC channel 1 */ + GLB_DAC_CHAN2, /*!< DAC channel 2 */ + GLB_DAC_CHAN3, /*!< DAC channel 3 */ + GLB_DAC_CHAN4, /*!< DAC channel 4 */ + GLB_DAC_CHAN5, /*!< DAC channel 5 */ + GLB_DAC_CHAN6, /*!< DAC channel 6 */ + GLB_DAC_CHAN7, /*!< DAC channel 7 */ + GLB_DAC_CHAN_ALL, /*!< DAC channel all */ +} GLB_DAC_Chan_Type; + +/** + * @brief DAC channel configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + GLB_DAC_Chan_Type outMux; /*!< DAC output mux,NOT implement yet,DAC use fixed GPIO9 and GPIO10 */ + GLB_DAC_Output_Volt_Range_Type outRange; /*!< DAC output voltage range */ +} GLB_DAC_Chan_Cfg_Type; + +/** + * @brief DAC configuration structure type definition + */ +typedef struct +{ + GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ + BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ + BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ +} GLB_DAC_Cfg_Type; + +/** + * @brief DAC channel B source selection type definition + */ +typedef enum { + GPIP_DAC_ChanB_SRC_REG, /*!< select Reg as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_DMA, /*!< select DMA as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_A, /*!< select channel A as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_INVERSE_A, /*!< select inverse of channel A as source of DAC channel B */ +} GPIP_DAC_ChanB_SRC_Type; + +/** + * @brief DAC channel A source selection type definition + */ +typedef enum { + GPIP_DAC_ChanA_SRC_REG, /*!< select Reg as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_DMA, /*!< select DMA as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel A */ +} GPIP_DAC_ChanA_SRC_Type; + +/** + * @brief DAC clock divider type definition + */ +typedef enum { + DAC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ + DAC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ + DAC_CLK_DIV_RESERVE, /*!< reserved */ + DAC_CLK_DIV_64, /*!< ADC clock:on 32M clock is 0.5M */ + DAC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ +} DAC_CLK_Type; + +/** + * @brief DAC DMA TX format selection type definition + */ +typedef enum { + GPIP_DAC_DMA_FORMAT_0, /*!< {A0},{A1},{A2},... */ + GPIP_DAC_DMA_FORMAT_1, /*!< {B0,A0},{B1,A1},{B2,A2},... */ + GPIP_DAC_DMA_FORMAT_2, /*!< {A1,A0},{A3,A2},{A5,A4},... */ +} GPIP_DAC_DMA_TX_FORMAT_Type; + +/** + * @brief AON and GPIP DAC configuration structure type definition + */ +typedef struct +{ + GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ + BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ + BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ + DAC_CLK_Type div; /*!< DAC clock div */ + BL_Fun_Type dmaEn; /*!< DAC DMA transfer enable */ + GPIP_DAC_DMA_TX_FORMAT_Type dmaFmt; /*!< DAC DMA TX format selection */ +} GLB_GPIP_DAC_Cfg_Type; + +/** + * @brief AON and GPIP DAC channel A configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + GPIP_DAC_ChanA_SRC_Type src; /*!< DAC channel A source */ +} GLB_GPIP_DAC_ChanA_Cfg_Type; + +/** + * @brief AON and GPIP DAC channel B configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + GPIP_DAC_ChanB_SRC_Type src; /*!< DAC channel B source */ +} GLB_GPIP_DAC_ChanB_Cfg_Type; + +/*@} end of group DAC_Public_Types */ + +/** @defgroup DAC_Public_Constants + * @{ + */ + +/** @defgroup GLB_DAC_REF_SEL_TYPE + * @{ + */ +#define IS_GLB_DAC_REF_SEL_TYPE(type) (((type) == GLB_DAC_REF_SEL_INTERNAL) || \ + ((type) == GLB_DAC_REF_SEL_EXTERNAL)) + +/** @defgroup GLB_DAC_OUTPUT_VOLT_RANGE_TYPE + * @{ + */ +#define IS_GLB_DAC_OUTPUT_VOLT_RANGE_TYPE(type) (((type) == GLB_DAC_Output_Volt_0P2_1) || \ + ((type) == GLB_DAC_Output_Volt_0P225_1P425) || \ + ((type) == GLB_DAC_Output_Volt_RESEVED) || \ + ((type) == GLB_DAC_Output_Volt_0P2_1P8)) + +/** @defgroup GLB_DAC_CHAN_TYPE + * @{ + */ +#define IS_GLB_DAC_CHAN_TYPE(type) (((type) == GLB_DAC_CHAN0) || \ + ((type) == GLB_DAC_CHAN1) || \ + ((type) == GLB_DAC_CHAN2) || \ + ((type) == GLB_DAC_CHAN3) || \ + ((type) == GLB_DAC_CHAN4) || \ + ((type) == GLB_DAC_CHAN5) || \ + ((type) == GLB_DAC_CHAN6) || \ + ((type) == GLB_DAC_CHAN7) || \ + ((type) == GLB_DAC_CHAN_ALL)) + +/** @defgroup GPIP_DAC_CHANB_SRC_TYPE + * @{ + */ +#define IS_GPIP_DAC_CHANB_SRC_TYPE(type) (((type) == GPIP_DAC_ChanB_SRC_REG) || \ + ((type) == GPIP_DAC_ChanB_SRC_DMA) || \ + ((type) == GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER) || \ + ((type) == GPIP_DAC_ChanB_SRC_SIN_GEN) || \ + ((type) == GPIP_DAC_ChanB_SRC_A) || \ + ((type) == GPIP_DAC_ChanB_SRC_INVERSE_A)) + +/** @defgroup GPIP_DAC_CHANA_SRC_TYPE + * @{ + */ +#define IS_GPIP_DAC_CHANA_SRC_TYPE(type) (((type) == GPIP_DAC_ChanA_SRC_REG) || \ + ((type) == GPIP_DAC_ChanA_SRC_DMA) || \ + ((type) == GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER) || \ + ((type) == GPIP_DAC_ChanA_SRC_SIN_GEN)) + +/** @defgroup DAC_CLK_TYPE + * @{ + */ +#define IS_DAC_CLK_TYPE(type) (((type) == DAC_CLK_DIV_16) || \ + ((type) == DAC_CLK_DIV_32) || \ + ((type) == DAC_CLK_DIV_RESERVE) || \ + ((type) == DAC_CLK_DIV_64) || \ + ((type) == DAC_CLK_DIV_1)) + +/** @defgroup GPIP_DAC_DMA_TX_FORMAT_TYPE + * @{ + */ +#define IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(type) (((type) == GPIP_DAC_DMA_FORMAT_0) || \ + ((type) == GPIP_DAC_DMA_FORMAT_1) || \ + ((type) == GPIP_DAC_DMA_FORMAT_2)) + +/*@} end of group DAC_Public_Constants */ + +/** @defgroup DAC_Public_Macros + * @{ + */ + +/*@} end of group DAC_Public_Macros */ + +/** @defgroup DAC_Public_Functions + * @{ + */ +void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg); +void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg); +void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg); +void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src); +void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src); +void GPIP_DAC_ChanB_Enable(void); +void GPIP_DAC_ChanB_Disable(void); +void GPIP_DAC_ChanA_Enable(void); +void GPIP_DAC_ChanA_Disable(void); +void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt); +void GPIP_Set_DAC_DMA_TX_Enable(void); +void GPIP_Set_DAC_DMA_TX_Disable(void); +void GPIP_DAC_DMA_WriteData(uint32_t data); +BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg); +void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg); +void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg); +void GLB_DAC_Set_ChanA_Value(uint16_t val); +void GLB_DAC_Set_ChanB_Value(uint16_t val); + +/*@} end of group DAC_Public_Functions */ + +/*@} end of group DAC */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_DAC_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..b7d12d0f04ff3723f6a662628e9e2ae4a059915d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file bl702_dma.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_DMA_H__ +#define __BL702_DMA_H__ + +#include "dma_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Public_Types + * @{ + */ + +/** + * @brief DMA endian type definition + */ +typedef enum { + DMA_LITTLE_ENDIAN = 0, /*!< DMA use little endian */ + DMA_BIG_ENDIAN, /*!< DMA use big endian */ +} DMA_Endian_Type; + +/** + * @brief DMA synchronization logic type definition + */ +typedef enum { + DMA_SYNC_LOGIC_ENABLE = 0, /*!< DMA synchronization logic enable */ + DMA_SYNC_LOGIC_DISABLE, /*!< DMA synchronization logic disable */ +} DMA_Sync_Logic_Type; + +/** + * @brief DMA transfer width type definition + */ +typedef enum { + DMA_TRNS_WIDTH_8BITS = 0, /*!< DMA transfer width:8 bits */ + DMA_TRNS_WIDTH_16BITS, /*!< DMA transfer width:16 bits */ + DMA_TRNS_WIDTH_32BITS, /*!< DMA transfer width:32 bits */ +} DMA_Trans_Width_Type; + +/** + * @brief DMA transfer direction type definition + */ +typedef enum { + DMA_TRNS_M2M = 0, /*!< DMA transfer tyep:memory to memory */ + DMA_TRNS_M2P, /*!< DMA transfer tyep:memory to peripheral */ + DMA_TRNS_P2M, /*!< DMA transfer tyep:peripheral to memory */ + DMA_TRNS_P2P, /*!< DMA transfer tyep:peripheral to peripheral */ +} DMA_Trans_Dir_Type; + +/** + * @brief DMA burst size type definition + */ +typedef enum { + DMA_BURST_SIZE_1 = 0, /*!< DMA transfer width:8 bits */ + DMA_BURST_SIZE_4, /*!< DMA transfer width:16 bits */ + DMA_BURST_SIZE_8, /*!< DMA transfer width:32 bits */ + DMA_BURST_SIZE_16, /*!< DMA transfer width:64 bits */ +} DMA_Burst_Size_Type; + +/** + * @brief DMA destination peripheral type definition + */ +typedef enum { + DMA_REQ_UART0_RX = 0, /*!< DMA request peripheral:UART0 RX */ + DMA_REQ_UART0_TX, /*!< DMA request peripheral:UART0 TX */ + DMA_REQ_UART1_RX, /*!< DMA request peripheral:UART1 RX */ + DMA_REQ_UART1_TX, /*!< DMA request peripheral:UART1 TX */ + DMA_REQ_I2C_RX = 6, /*!< DMA request peripheral:I2C RX */ + DMA_REQ_I2C_TX, /*!< DMA request peripheral:I2C TX */ + DMA_REQ_SPI_RX = 10, /*!< DMA request peripheral:SPI RX */ + DMA_REQ_SPI_TX, /*!< DMA request peripheral:SPI TX */ + DMA_REQ_I2S_RX = 20, /*!< DMA request peripheral:SPI RX */ + DMA_REQ_I2S_TX, /*!< DMA request peripheral:SPI TX */ + DMA_REQ_GPADC0 = 22, /*!< DMA request peripheral:GPADC0 */ + DMA_REQ_GPADC1, /*!< DMA request peripheral:GPADC1 */ + DMA_REQ_NONE = 0, /*!< DMA request peripheral:None */ +} DMA_Periph_Req_Type; + +/** + * @brief DMA channel type definition + */ +typedef enum { + DMA_CH0 = 0, /*!< DMA channel 0 */ + DMA_CH1, /*!< DMA channel 1 */ + DMA_CH2, /*!< DMA channel 2 */ + DMA_CH3, /*!< DMA channel 3 */ + DMA_CH4, /*!< DMA channel 4 */ + DMA_CH5, /*!< DMA channel 5 */ + DMA_CH6, /*!< DMA channel 6 */ + DMA_CH7, /*!< DMA channel 7 */ + DMA_CH_MAX, /*!< */ +} DMA_Chan_Type; + +/** + * @brief DMA LLI Structure PING-PONG + */ +typedef enum { + PING_INDEX = 0, /*!< PING INDEX */ + PONG_INDEX, /*!< PONG INDEX */ +} DMA_LLI_PP_Index_Type; + +/** + * @brief DMA interrupt type definition + */ +typedef enum { + DMA_INT_TCOMPLETED = 0, /*!< DMA completed interrupt */ + DMA_INT_ERR, /*!< DMA error interrupt */ + DMA_INT_ALL, /*!< All the interrupt */ +} DMA_INT_Type; + +/** + * @brief DMA Configuration Structure type definition + */ +typedef struct +{ + DMA_Endian_Type endian; /*!< DMA endian type */ + DMA_Sync_Logic_Type syncLogic; /*!< DMA synchronization logic */ +} DMA_Cfg_Type; + +/** + * @brief DMA channel Configuration Structure type definition + */ +typedef struct +{ + uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ + uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ + uint32_t transfLength; /*!< Transfer length, 0~4095, this is burst count */ + DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ + DMA_Chan_Type ch; /*!< Channel select 0-7 */ + DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */ + DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */ + DMA_Burst_Size_Type srcBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. + 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ + DMA_Burst_Size_Type dstBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. + 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ + BL_Fun_Type dstAddMode; /*!< */ + BL_Fun_Type dstMinMode; /*!< */ + uint8_t fixCnt; /*!< */ + uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */ + uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */ + DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ + DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ +} DMA_Channel_Cfg_Type; + +/** + * @brief DMA LLI control structure type definition + */ +typedef struct +{ + uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ + uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ + uint32_t nextLLI; /*!< Next LLI address */ + struct DMA_Control_Reg dmaCtrl; /*!< DMA transaction control */ +} DMA_LLI_Ctrl_Type; + +/** + * @brief DMA LLI configuration structure type definition + */ +typedef struct +{ + DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ + DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ + DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ +} DMA_LLI_Cfg_Type; + +/** + * @brief DMA LLI Ping-Pong Buf definition + */ +typedef struct +{ + uint8_t idleIndex; /*!< Index Idle lliListHeader */ + uint8_t dmaChan; /*!< DMA LLI Channel used */ + DMA_LLI_Ctrl_Type *lliListHeader[2]; /*!< Ping-Pong BUf List Header */ + void (*onTransCompleted)(DMA_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */ +} DMA_LLI_PP_Buf; + +/** + * @brief DMA LLI Ping-Pong Structure definition + */ +typedef struct +{ + uint8_t trans_index; /*!< Ping or Pong Trigger TC */ + uint8_t dmaChan; /*!< DMA LLI Channel used */ + struct DMA_Control_Reg dmaCtrlRegVal; /*!< DMA Basic Pararmeter */ + DMA_LLI_Cfg_Type *DMA_LLI_Cfg; /*!< LLI Config parameter */ + uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */ + uint32_t chache_buf_addr[2]; /*!< Ping-Pong structure chache */ + BL_Fun_Type is_single_mode; /*!< is Ping-pong running forever or single mode ,if is single mode ping-pong will run only once + after one start */ +} DMA_LLI_PP_Struct; + +/*@} end of group DMA_Public_Types */ + +/** @defgroup DMA_Public_Constants + * @{ + */ + +/** @defgroup DMA_ENDIAN_TYPE + * @{ + */ +#define IS_DMA_ENDIAN_TYPE(type) (((type) == DMA_LITTLE_ENDIAN) || \ + ((type) == DMA_BIG_ENDIAN)) + +/** @defgroup DMA_SYNC_LOGIC_TYPE + * @{ + */ +#define IS_DMA_SYNC_LOGIC_TYPE(type) (((type) == DMA_SYNC_LOGIC_ENABLE) || \ + ((type) == DMA_SYNC_LOGIC_DISABLE)) + +/** @defgroup DMA_TRANS_WIDTH_TYPE + * @{ + */ +#define IS_DMA_TRANS_WIDTH_TYPE(type) (((type) == DMA_TRNS_WIDTH_8BITS) || \ + ((type) == DMA_TRNS_WIDTH_16BITS) || \ + ((type) == DMA_TRNS_WIDTH_32BITS)) + +/** @defgroup DMA_TRANS_DIR_TYPE + * @{ + */ +#define IS_DMA_TRANS_DIR_TYPE(type) (((type) == DMA_TRNS_M2M) || \ + ((type) == DMA_TRNS_M2P) || \ + ((type) == DMA_TRNS_P2M) || \ + ((type) == DMA_TRNS_P2P)) + +/** @defgroup DMA_BURST_SIZE_TYPE + * @{ + */ +#define IS_DMA_BURST_SIZE_TYPE(type) (((type) == DMA_BURST_SIZE_1) || \ + ((type) == DMA_BURST_SIZE_4) || \ + ((type) == DMA_BURST_SIZE_8) || \ + ((type) == DMA_BURST_SIZE_16)) + +/** @defgroup DMA_PERIPH_REQ_TYPE + * @{ + */ +#define IS_DMA_PERIPH_REQ_TYPE(type) (((type) == DMA_REQ_UART0_RX) || \ + ((type) == DMA_REQ_UART0_TX) || \ + ((type) == DMA_REQ_UART1_RX) || \ + ((type) == DMA_REQ_UART1_TX) || \ + ((type) == DMA_REQ_I2C_RX) || \ + ((type) == DMA_REQ_I2C_TX) || \ + ((type) == DMA_REQ_SPI_RX) || \ + ((type) == DMA_REQ_SPI_TX) || \ + ((type) == DMA_REQ_I2S_RX) || \ + ((type) == DMA_REQ_I2S_TX) || \ + ((type) == DMA_REQ_GPADC0) || \ + ((type) == DMA_REQ_GPADC1) || \ + ((type) == DMA_REQ_NONE)) + +/** @defgroup DMA_CHAN_TYPE + * @{ + */ +#define IS_DMA_CHAN_TYPE(type) (((type) == DMA_CH0) || \ + ((type) == DMA_CH1) || \ + ((type) == DMA_CH2) || \ + ((type) == DMA_CH3) || \ + ((type) == DMA_CH4) || \ + ((type) == DMA_CH5) || \ + ((type) == DMA_CH6) || \ + ((type) == DMA_CH7) || \ + ((type) == DMA_CH_MAX)) + +/** @defgroup DMA_LLI_PP_INDEX_TYPE + * @{ + */ +#define IS_DMA_LLI_PP_INDEX_TYPE(type) (((type) == PING_INDEX) || \ + ((type) == PONG_INDEX)) + +/** @defgroup DMA_INT_TYPE + * @{ + */ +#define IS_DMA_INT_TYPE(type) (((type) == DMA_INT_TCOMPLETED) || \ + ((type) == DMA_INT_ERR) || \ + ((type) == DMA_INT_ALL)) + +/*@} end of group DMA_Public_Constants */ + +/** @defgroup DMA_Public_Macros + * @{ + */ +#define DMA_PINC_ENABLE 1 +#define DMA_PINC_DISABLE 0 +#define DMA_MINC_ENABLE 1 +#define DMA_MINC_DISABLE 0 + +/*@} end of group DMA_Public_Macros */ + +/** @defgroup DMA_Public_Functions + * @{ + */ + +/** + * @brief DMA Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void DMA_ALL_IRQHandler(void); +#endif +void DMA_Enable(void); +void DMA_Disable(void); +void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg); +void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len); +void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len); +uint32_t DMA_Channel_TranferSize(uint8_t ch); +BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch); +void DMA_Channel_Enable(uint8_t ch); +void DMA_Channel_Disable(uint8_t ch); +void DMA_LLI_Init(uint8_t ch, DMA_LLI_Cfg_Type *lliCfg); +void DMA_LLI_Update(uint8_t ch, uint32_t LLI); +void DMA_IntMask(uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask); +void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf); +DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf); +void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList); +void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf); +void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun); +void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct); +void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct); +BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct); +BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, + uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len); + +/*@} end of group DMA_Public_Functions */ + +/*@} end of group DMA */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_DMA_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ef_ctrl.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ef_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..3081cd499c03b7e08286dd6afe224b5686616696 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ef_ctrl.h @@ -0,0 +1,329 @@ +/** + ****************************************************************************** + * @file bl702_ef_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_EF_CTRL_H__ +#define __BL702_EF_CTRL_H__ + +#include "ef_ctrl_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup EF_CTRL + * @{ + */ + +/** @defgroup EF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Efuse Ctrl key slot type definition + */ +typedef enum { + EF_CTRL_KEY_SLOT0, /*!< key slot 0 */ + EF_CTRL_KEY_SLOT1, /*!< key slot 1 */ + EF_CTRL_KEY_SLOT2, /*!< key slot 2 */ + EF_CTRL_KEY_SLOT3, /*!< key slot 3 */ + EF_CTRL_KEY_SLOT4, /*!< key slot 4 */ + EF_CTRL_KEY_SLOT5, /*!< key slot 5 */ + EF_CTRL_KEY_MAX, /*!< */ +} EF_Ctrl_Key_Type; + +/** + * @brief Efuse Ctrl sign type definition + */ +typedef enum { + EF_CTRL_SIGN_NONE, /*!< no sign */ + EF_CTRL_SIGN_RSA, /*!< use RSA to sign */ + EF_CTRL_SIGN_ECC, /*!< use ECC to sign */ +} EF_Ctrl_Sign_Type; + +/** + * @brief Efuse Ctrl flash AES type definition + */ +typedef enum { + EF_CTRL_SF_AES_NONE, /*!< No AES */ + EF_CTRL_SF_AES_128, /*!< AES 128 */ + EF_CTRL_SF_AES_192, /*!< AES 192 */ + EF_CTRL_SF_AES_256, /*!< AES 256 */ +} EF_Ctrl_SF_AES_Type; + +/** + * @brief Efuse Ctrl Dbg type definition + */ +typedef enum { + EF_CTRL_DBG_OPEN = 0, /*!< Open debug */ + EF_CTRL_DBG_PASSWORD, /*!< Open debug with password */ + EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */ +} EF_Ctrl_Dbg_Mode_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_EF_CLK, /*!< Select efuse clock */ + EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */ +} EF_Ctrl_CLK_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_PARA_DFT, /*!< Select default cyc parameter */ + EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */ +} EF_Ctrl_CYC_PARA_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_OP_MODE_AUTO, /*!< Select efuse program auto mode */ + EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */ +} EF_Ctrl_OP_MODE_Type; + +/** + * @brief Efuse Ctrl secure configuration structure type definition + */ +typedef struct +{ + EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */ + uint8_t ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */ + uint8_t ef_sboot_en; /*!< Secure boot enable config value */ +} EF_Ctrl_Sec_Param_Type; + +/** + * @brief Efuse analog RC32M trim type definition + */ +typedef struct +{ + uint32_t trimRc32mCodeFrExt : 8; /*!< Efuse analog trim:trim_rc32m_code_fr_ext */ + uint32_t trimRc32mCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */ + uint32_t trimRc32mExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en */ + uint32_t reserved : 22; /*!< Efuse analog trim:reserved */ +} Efuse_Ana_RC32M_Trim_Type; + +/** + * @brief Efuse analog RC32K trim type definition + */ +typedef struct +{ + uint32_t trimRc32kCodeFrExt : 10; /*!< Efuse analog trim:trim_rc32k_code_fr_ext */ + uint32_t trimRc32kCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */ + uint32_t trimRc32kExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32k_ext_code_en */ + uint32_t reserved : 20; /*!< Efuse analog trim:reserved */ +} Efuse_Ana_RC32K_Trim_Type; + +/** + * @brief Efuse analog TSEN trim type definition + */ +typedef struct +{ + uint32_t tsenRefcodeCorner : 12; /*!< TSEN refcode */ + uint32_t tsenRefcodeCornerParity : 1; /*!< TSEN refcode parity */ + uint32_t tsenRefcodeCornerEn : 1; /*!< TSEN refcode enable */ + uint32_t tsenRefcodeCornerVersion : 1; /*!< TSEN ATE Version */ + uint32_t reserved : 18; /*!< TSEN analog trim:reserved */ +} Efuse_TSEN_Refcode_Corner_Type; + +/** + * @brief Efuse analog ADC Gain trim type definition + */ +typedef struct +{ + uint32_t adcGainCoeff : 12; /*!< ADC gain coeff */ + uint32_t adcGainCoeffParity : 1; /*!< ADC gain coeff parity */ + uint32_t adcGainCoeffEn : 1; /*!< ADC gain coeff enable */ + uint32_t reserved : 18; /*!< ADC gain coeff:reserved */ +} Efuse_ADC_Gain_Coeff_Type; + +/** + * @brief Efuse analog device info type definition + */ +typedef struct +{ + uint32_t rsvd_21_0 : 22; /*!< Reserved */ + uint32_t sf_swap_cfg : 2; /*!< 0:swap none, 1:swap SF2_CS & SF2_IO2, 2:swap SF2_IO0 & SF2_IO3, 3:swap both */ + uint32_t psram_cfg : 2; /*!< 0:no psram, 1:2MB psram, 2:external psram, 3:reserved */ + uint32_t flash_cfg : 3; /*!< 0:external flash SF2, 1:0.5MB flash, 2:1MB flash, 3:external flash SF1 */ + uint32_t rsvd_29 : 1; /*!< Reserved */ + uint32_t pkg_info : 2; /*!< 0:QFN32, 1:QFN40, 2:QFN48, 3:reserved */ +} Efuse_Device_Info_Type; + +/** + * @brief Efuse Capcode type definition + */ +typedef struct +{ + uint32_t capCode : 6; /*!< Cap code value */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 24; /*!< Reserved */ +} Efuse_Capcode_Info_Type; + +/*@} end of group EF_CTRL_Public_Types */ + +/** @defgroup EF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup EF_CTRL_KEY_TYPE + * @{ + */ +#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \ + ((type) == EF_CTRL_KEY_SLOT1) || \ + ((type) == EF_CTRL_KEY_SLOT2) || \ + ((type) == EF_CTRL_KEY_SLOT3) || \ + ((type) == EF_CTRL_KEY_SLOT4) || \ + ((type) == EF_CTRL_KEY_SLOT5) || \ + ((type) == EF_CTRL_KEY_MAX)) + +/** @defgroup EF_CTRL_SIGN_TYPE + * @{ + */ +#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \ + ((type) == EF_CTRL_SIGN_RSA) || \ + ((type) == EF_CTRL_SIGN_ECC)) + +/** @defgroup EF_CTRL_SF_AES_TYPE + * @{ + */ +#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \ + ((type) == EF_CTRL_SF_AES_128) || \ + ((type) == EF_CTRL_SF_AES_192) || \ + ((type) == EF_CTRL_SF_AES_256)) + +/** @defgroup EF_CTRL_DBG_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) || \ + ((type) == EF_CTRL_DBG_PASSWORD) || \ + ((type) == EF_CTRL_DBG_CLOSE)) + +/** @defgroup EF_CTRL_CLK_TYPE + * @{ + */ +#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \ + ((type) == EF_CTRL_SAHB_CLK)) + +/** @defgroup EF_CTRL_CYC_PARA_TYPE + * @{ + */ +#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || \ + ((type) == EF_CTRL_PARA_MANUAL)) + +/** @defgroup EF_CTRL_OP_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || \ + ((type) == EF_CTRL_OP_MODE_MANUAL)) + +/*@} end of group EF_CTRL_Public_Constants */ + +/** @defgroup EF_CTRL_Public_Macros + * @{ + */ +#define EF_CTRL_EFUSE_R0_SIZE 128 + +/*@} end of group EF_CTRL_Public_Macros */ + +/** @defgroup EF_CTRL_Public_Functions + * @{ + */ +void EF_Ctrl_Load_Efuse_R0(void); +BL_Sts_Type EF_Ctrl_Busy(void); +BL_Sts_Type EF_Ctrl_AutoLoad_Done(void); +void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program); +void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh); +void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program); +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg); +void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program); +void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]); +void EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled, uint8_t *npDisabled, uint8_t *npCpuType); +uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len); +void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program); +void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim); +void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim); +void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim); +void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim); +void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim); +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program); +void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage); +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program); +void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]); +BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]); +void EF_Ctrl_Writelock_MAC_Address(uint8_t program); +uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload); +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]); +/*----------*/ +BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]); +BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]); +/*----------*/ +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo); +uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t reload); +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t code, uint8_t program); +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t *code, uint8_t reload); +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program); +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload); +void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program); +void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len); +void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program); +void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program); +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Clear(uint32_t index, uint32_t len); +void EF_Ctrl_Crc_Enable(void); +BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void); +void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue); +BL_Err_Type EF_Ctrl_Crc_Result(void); +void EF_Ctrl_Sw_AHB_Clk_0(void); + +/*@} end of group EF_CTRL_Public_Functions */ + +/*@} end of group EF_CTRL */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_EF_CTRL_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_emac.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_emac.h new file mode 100644 index 0000000000000000000000000000000000000000..69d083ff10fe02039f3aeb5501b639e50f697e14 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_emac.h @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file bl702_emac.h + * @version V1.2 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2018 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_EMAC_H__ +#define __BL702_EMAC_H__ + +#include "emac_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup EMAC + * @{ + */ + +/** @defgroup EMAC_Public_Types + * @{ + */ + +/** + * @brief EMAC half/full-duplex type definition + */ +typedef enum { + EMAC_MODE_HALFDUPLEX, /*!< ETH half-duplex */ + EMAC_MODE_FULLDUPLEX, /*!< ETH full-duplex */ +} EMAC_Duplex_Type; + +/** + * @brief EMAC speed type definition + */ +typedef enum { + EMAC_SPEED_10M, /*!< ETH speed 10M */ + EMAC_SPEED_100M, /*!< ETH speed 100M */ +} EMAC_Speed_Type; + +/** + * @brief EMAC interrupt type definition + */ +typedef enum { + EMAC_INT_TX_DONE = 0x01, /*!< Transmit one frame done */ + EMAC_INT_TX_ERROR = 0x02, /*!< Transmit error occur */ + EMAC_INT_RX_DONE = 0x04, /*!< Receive one frame done */ + EMAC_INT_RX_ERROR = 0x08, /*!< Receive error occur */ + EMAC_INT_RX_BUSY = 0x10, /*!< Receive busy due to no free RX buffer Descripter */ + EMAC_INT_TX_CTRL = 0x20, /*!< Transmit control frame */ + EMAC_INT_RX_CTRL = 0x40, /*!< Receive control frame */ + EMAC_INT_ALL = 0x7F, /*!< */ +} EMAC_INT_Type; + +/** + * @brief EMAC interrupt Index + */ +typedef enum { + EMAC_INT_TX_DONE_IDX = 0x0, /*!< Transmit one frame done */ + EMAC_INT_TX_ERROR_IDX = 0x1, /*!< Transmit error occur */ + EMAC_INT_RX_DONE_IDX = 0x2, /*!< Receive one frame done */ + EMAC_INT_RX_ERROR_IDX = 0x3, /*!< Receive error occur */ + EMAC_INT_RX_BUSY_IDX = 0x4, /*!< Receive busy due to no free RX buffer Descripter */ + EMAC_INT_TX_CTRL_IDX = 0x5, /*!< Transmit control frame */ + EMAC_INT_RX_CTRL_IDX = 0x6, /*!< Receive control frame */ + EMAC_INT_CNT, /*!< EMAC INT source count */ +} EMAC_INT_Index; + +/** + * @brief EMAC configuration type definition + */ +typedef struct +{ + BL_Fun_Type recvSmallFrame; /*!< Receive small frmae or not */ + BL_Fun_Type recvHugeFrame; /*!< Receive huge frmae(>64K bytes) or not */ + BL_Fun_Type padEnable; /*!< Enable padding for frame which is less than MINFL or not */ + BL_Fun_Type crcEnable; /*!< Enable hardware CRC or not */ + BL_Fun_Type noPreamble; /*!< Enable preamble or not */ + BL_Fun_Type recvBroadCast; /*!< Receive broadcast frame or not */ + BL_Fun_Type interFrameGapCheck; /*!< Check inter frame gap or not */ + BL_Fun_Type miiNoPreamble; /*!< Enable MII interface preamble or not */ + uint8_t miiClkDiv; /*!< MII interface clock divider from bus clock */ + uint8_t maxTxRetry; /*!< Maximum tx retry count */ + uint16_t interFrameGapValue; /*!< Inter frame gap vaule in clock cycles(default 24),which equals 9.6 us for 10 Mbps and 0.96 us + for 100 Mbps mode */ + uint16_t minFrameLen; /*!< Minimum frame length */ + uint16_t maxFrameLen; /*!< Maximum frame length */ + uint16_t collisionValid; /*!< Collision valid value */ + uint8_t macAddr[6]; /*!< MAC Address */ +} EMAC_CFG_Type; + + +/** + * @brief EMAC TX DMA description type definition + */ +/** + * Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern. + */ +typedef struct +{ + uint32_t C_S_L; /*!< Buffer Descriptors(BD) control,status,length */ + uint32_t Buffer; /*!< BD buffer address */ +} EMAC_BD_Desc_Type; + +/** + * @brief EMAC Handle type definition + */ +typedef struct +{ + EMAC_BD_Desc_Type *bd; /*!< Tx descriptor header pointer */ + uint8_t txIndexEMAC; /*!< TX index: EMAC */ + uint8_t txIndexCPU; /*!< TX index: CPU/SW */ + uint8_t txBuffLimit; /*!< TX index max */ + uint8_t rsv0; + uint8_t rxIndexEMAC; /*!< RX index: EMAC */ + uint8_t rxIndexCPU; /*!< RX index: CPU/SW */ + uint8_t rxBuffLimit; /*!< RX index max */ + uint8_t rsv1; +} EMAC_Handle_Type; + +/*@} end of group EMAC_Public_Types */ + +/** @defgroup EMAC_Public_Constants + * @{ + */ + +/** @defgroup EMAC_DUPLEX_TYPE + * @{ + */ +#define IS_EMAC_DUPLEX_TYPE(type) (((type) == EMAC_MODE_HALFDUPLEX) || \ + ((type) == EMAC_MODE_FULLDUPLEX)) + +/** @defgroup EMAC_SPEED_TYPE + * @{ + */ +#define IS_EMAC_SPEED_TYPE(type) (((type) == EMAC_SPEED_10M) || \ + ((type) == EMAC_SPEED_100M)) + +/** @defgroup EMAC_INT_TYPE + * @{ + */ +#define IS_EMAC_INT_TYPE(type) (((type) == EMAC_INT_TX_DONE) || \ + ((type) == EMAC_INT_TX_ERROR) || \ + ((type) == EMAC_INT_RX_DONE) || \ + ((type) == EMAC_INT_RX_ERROR) || \ + ((type) == EMAC_INT_RX_BUSY) || \ + ((type) == EMAC_INT_TX_CTRL) || \ + ((type) == EMAC_INT_RX_CTRL) || \ + ((type) == EMAC_INT_ALL)) + +/** @defgroup EMAC_INT_INDEX + * @{ + */ +#define IS_EMAC_INT_INDEX(type) (((type) == EMAC_INT_TX_DONE_IDX) || \ + ((type) == EMAC_INT_TX_ERROR_IDX) || \ + ((type) == EMAC_INT_RX_DONE_IDX) || \ + ((type) == EMAC_INT_RX_ERROR_IDX) || \ + ((type) == EMAC_INT_RX_BUSY_IDX) || \ + ((type) == EMAC_INT_TX_CTRL_IDX) || \ + ((type) == EMAC_INT_RX_CTRL_IDX) || \ + ((type) == EMAC_INT_CNT)) + +/*@} end of group EMAC_Public_Constants */ + +/** @defgroup EMAC_Public_Macros + * @{ + */ +#define BD_TX_CS_POS (0) /*!< Carrier Sense Lost */ +#define BD_TX_CS_LEN (1) +#define BD_TX_DF_POS (1) /*!< Defer Indication */ +#define BD_TX_DF_LEN (1) +#define BD_TX_LC_POS (2) /*!< Late Collision */ +#define BD_TX_LC_LEN (1) +#define BD_TX_RL_POS (3) /*!< Retransmission Limit */ +#define BD_TX_RL_LEN (1) +#define BD_TX_RTRY_POS (4) /*!< Retry Count */ +#define BD_TX_RTRY_LEN (4) +#define BD_TX_UR_POS (8) /*!< Underrun */ +#define BD_TX_UR_LEN (1) +#define BD_TX_CRC_POS (11) /*!< CRC Enable */ +#define BD_TX_CRC_LEN (1) +#define BD_TX_PAD_POS (12) /*!< PAD enable */ +#define BD_TX_PAD_LEN (1) +#define BD_TX_WR_POS (13) /*!< Wrap */ +#define BD_TX_WR_LEN (1) +#define BD_TX_IRQ_POS (14) /*!< Interrupt Request Enable */ +#define BD_TX_IRQ_LEN (1) +#define BD_TX_RD_POS (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */ +#define BD_TX_RD_LEN (1) +#define BD_TX_LEN_POS (16) /*!< TX Data buffer length */ +#define BD_TX_LEN_LEN (16) + +#define BD_RX_LC_POS (0) /*!< Late Collision */ +#define BD_RX_LC_LEN (1) +#define BD_RX_CRC_POS (1) /*!< RX CRC Error */ +#define BD_RX_CRC_LEN (1) +#define BD_RX_SF_POS (2) /*!< Short Frame */ +#define BD_RX_SF_LEN (1) +#define BD_RX_TL_POS (3) /*!< Too Long */ +#define BD_RX_TL_LEN (1) +#define BD_RX_DN_POS (4) /*!< Dribble Nibble */ +#define BD_RX_DN_LEN (1) +#define BD_RX_RE_POS (5) /*!< Receive Error */ +#define BD_RX_RE_LEN (1) +#define BD_RX_OR_POS (6) /*!< Overrun */ +#define BD_RX_OR_LEN (1) +#define BD_RX_M_POS (7) /*!< Miss */ +#define BD_RX_M_LEN (1) +#define BD_RX_CF_POS (8) /*!< Control Frame Received */ +#define BD_RX_CF_LEN (1) +#define BD_RX_WR_POS (13) /*!< Wrap */ +#define BD_RX_WR_LEN (1) +#define BD_RX_IRQ_POS (14) /*!< Interrupt Request Enable */ +#define BD_RX_IRQ_LEN (1) +#define BD_RX_E_POS (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */ +#define BD_RX_E_LEN (1) +#define BD_RX_LEN_POS (16) /*!< RX Data buffer length */ +#define BD_RX_LEN_LEN (16) + +#define EMAC_BD_FIELD_MSK(field) (((1U << BD_##field##_LEN) - 1) << BD_##field##_POS) +#define EMAC_BD_FIELD_UMSK(field) (~(((1U << BD_##field##_LEN) - 1) << BD_##field##_POS)) +/* DMA Descriptor offset */ +#define EMAC_DMA_DESC_OFFSET 0x400 +/* ETH packet size */ +#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER_SZIE ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC_SIZE ((uint32_t)4U) /*!< Ethernet CRC */ +#define ETH_EXTRA_SIZE ((uint32_t)2U) /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG_SIZE ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD_SIZE ((uint32_t)46U) /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD_SIZE ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD_SIZE ((uint32_t)9000U) /*!< Jumbo frame payload size */ + +/*@} end of group EMAC_Public_Macros */ + +/** @defgroup EMAC_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void EMAC_IRQHandler(void); +#endif +BL_Err_Type EMAC_Init(EMAC_CFG_Type *cfg); +BL_Err_Type EMAC_DeInit(void); +BL_Err_Type EMAC_DMADescListInit(EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, + uint8_t *rxBuff, uint32_t rxBuffCount); +BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc); +BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len); +BL_Err_Type EMAC_Enable(void); +BL_Err_Type EMAC_Disable(void); +BL_Err_Type EMAC_IntMask(EMAC_INT_Type intType, BL_Mask_Type intMask); +BL_Sts_Type EMAC_GetIntStatus(EMAC_INT_Type intType); +BL_Err_Type EMAC_ClrIntStatus(EMAC_INT_Type intType); +BL_Err_Type EMAC_Int_Callback_Install(EMAC_INT_Index intIdx, intCallback_Type *cbFun); +BL_Err_Type EMAC_TxPauseReq(uint16_t timeCount); +BL_Err_Type EMAC_SetHash(uint32_t hash0, uint32_t hash1); +BL_Err_Type EMAC_Phy_Read(uint16_t phyReg, uint16_t *regValue); +BL_Err_Type EMAC_Phy_Write(uint16_t phyReg, uint16_t regValue); + +BL_Err_Type EMAC_Enable_TX(void); +BL_Err_Type EMAC_Disable_TX(void); + +void EMAC_Phy_SetAddress(uint16_t phyAddress); +void EMAC_Phy_Set_Full_Duplex(uint8_t fullDuplex); + +/*@} end of group EMAC_Public_Functions */ + +/*@} end of group EMAC */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_EMAC_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_glb.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_glb.h new file mode 100644 index 0000000000000000000000000000000000000000..1414477da89e0967815fd9c379af5b5e85bd21fc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_glb.h @@ -0,0 +1,822 @@ +/** + ****************************************************************************** + * @file bl702_glb.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_GLB_H__ +#define __BL702_GLB_H__ + +#include "glb_reg.h" +#include "pds_reg.h" +#include "bl702_gpio.h" +#include "bl702_l1c.h" +#include "bl702_hbn.h" +#include "bl702_sf_ctrl.h" +#include "bl702_sf_cfg.h" +#include "bl702_aon.h" +#include "bl702_ef_ctrl.h" +#include "bl702_pds.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Public_Types + * @{ + */ + +/** + * @brief GLB root clock type definition + */ +typedef enum { + GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */ + GLB_ROOT_CLK_XTAL, /*!< root clock select XTAL */ + GLB_ROOT_CLK_DLL, /*!< root clock select DLL others, PLL120M not recommend */ +} GLB_ROOT_CLK_Type; + +/** + * @brief GLB system clock type definition + */ +typedef enum { + GLB_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ + GLB_SYS_CLK_XTAL, /*!< use XTAL as system clock */ + GLB_SYS_CLK_DLL57P6M, /*!< use DLL output 57.6M as system clock */ + GLB_SYS_CLK_DLL96M, /*!< use DLL output 96M as system clock */ + GLB_SYS_CLK_DLL144M, /*!< use DLL output 144M as system clock, PLL120M not recommend */ +} GLB_SYS_CLK_Type; + +/** + * @brief GLB CAM clock type definition + */ +typedef enum { + GLB_CAM_CLK_XCLK, /*!< Select XCLK as CAM clock */ + GLB_CAM_CLK_DLL96M, /*!< Select DLL96M as CAM clock */ +} GLB_CAM_CLK_Type; + +/** + * @brief GLB I2S output ref clock type definition + */ +typedef enum { + GLB_I2S_OUT_REF_CLK_NONE, /*!< no output reference clock on I2S_0 ref_clock port */ + GLB_I2S_OUT_REF_CLK_SRC, /*!< output reference clock on I2S_0 ref_clock port */ +} GLB_I2S_OUT_REF_CLK_Type; + +/** + * @brief GLB qdec clock type definition + */ +typedef enum { + GLB_QDEC_CLK_XCLK, /*!< Select XCLK as QDEC clock */ + GLB_QDEC_CLK_F32K, /*!< Select f32k as QDEC clock (PDS mode) */ +} GLB_QDEC_CLK_Type; + +/** + * @brief GLB DMA clock ID type definition + */ +typedef enum { + GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */ + GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */ + GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */ + GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */ + GLB_DMA_CLK_DMA0_CH4, /*!< DMA clock ID:channel 4 */ + GLB_DMA_CLK_DMA0_CH5, /*!< DMA clock ID:channel 5 */ + GLB_DMA_CLK_DMA0_CH6, /*!< DMA clock ID:channel 6 */ + GLB_DMA_CLK_DMA0_CH7, /*!< DMA clock ID:channel 7 */ +} GLB_DMA_CLK_ID_Type; + +/** + * @brief GLB clock source type definition + */ +typedef enum { + GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */ +} GLB_IR_CLK_SRC_Type; + +/** + * @brief GLB flash clock type definition + */ +typedef enum { + GLB_SFLASH_CLK_144M, /*!< Select 144M as flash clock */ + GLB_SFLASH_CLK_XCLK, /*!< Select XCLK as flash clock */ + GLB_SFLASH_CLK_57P6M, /*!< Select 57.6M as flash clock */ + GLB_SFLASH_CLK_72M, /*!< Select 72M as flash clock */ + GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */ + GLB_SFLASH_CLK_96M, /*!< Select 96M as flash clock */ +} GLB_SFLASH_CLK_Type; + +/** + * @brief GLB chip clock out type definition + */ +typedef enum { + GLB_CHIP_CLK_OUT_NONE, /*!< no chip clock out */ + GLB_CHIP_CLK_OUT_I2S_REF_CLK, /*!< i2s_ref_clk out */ + GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK, /*!< audio_pll_clk out */ + GLB_CHIP_CLK_OUT_XTAL_SOC_32M, /*!< clk_xtal_soc_32M */ +} GLB_CHIP_CLK_OUT_Type; + +/** + * @brief GLB eth ref clock out type definition + */ +typedef enum { + GLB_ETH_REF_CLK_OUT_OUTSIDE_50M, /*!< select outside 50MHz RMII ref clock */ + GLB_ETH_REF_CLK_OUT_INSIDE_50M, /*!< select inside 50MHz RMII ref clock */ +} GLB_ETH_REF_CLK_OUT_Type; + +/** + * @brief GLB SPI pad action type definition + */ +typedef enum { + GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */ + GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */ +} GLB_SPI_PAD_ACT_AS_Type; + +/** + * @brief GLB PKA clock type definition + */ +typedef enum { + GLB_PKA_CLK_HCLK, /*!< Select HCLK as PKA clock */ + GLB_PKA_CLK_DLL96M, /*!< Select DLL 96M as PKA clock */ +} GLB_PKA_CLK_Type; + +/** + * @brief BMX arb mode type definition + */ +typedef enum { + BMX_ARB_FIX, /*!< 0->fix */ + BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + BMX_ARB_RANDOM, /*!< 3->random */ +} BMX_ARB_Type; + +/** + * @brief BMX configuration structure type definition + */ +typedef struct { + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +} BMX_Cfg_Type; + +/** + * @brief BMX bus err type definition + */ +typedef enum { + BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +} BMX_BUS_ERR_Type; + +/** + * @brief BMX bus err interrupt type definition + */ +typedef enum { + BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */ + BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */ +} BMX_ERR_INT_Type; + +/** + * @brief BMX time out interrupt type definition + */ +typedef enum { + BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */ + BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */ +} BMX_TO_INT_Type; + +/** + * @brief GLB EM type definition + */ +typedef enum { + GLB_EM_0KB = 0x0, /*!< 0x0 --> 0KB */ + GLB_EM_8KB = 0x3, /*!< 0x3 --> 8KB */ + GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */ +} GLB_EM_Type; + +/** + * @brief GLB EMAC and CAM pin type definition + */ +typedef enum { + GLB_EMAC_CAM_PIN_EMAC, /*!< select pin as emac */ + GLB_EMAC_CAM_PIN_CAM, /*!< select pin as cam */ +} GLB_EMAC_CAM_PIN_Type; + +/** + * @brief GLB RTC clock type definition + */ +typedef enum { + GLB_MTIMER_CLK_BCLK, /*!< BUS clock */ + GLB_MTIMER_CLK_32K, /*!< 32KHz */ +} GLB_MTIMER_CLK_Type; + +/** + * @brief GLB ADC clock type definition + */ +typedef enum { + GLB_ADC_CLK_AUDIO_PLL, /*!< use Audio PLL as ADC clock */ + GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */ +} GLB_ADC_CLK_Type; + +/** + * @brief GLB DAC clock type definition + */ +typedef enum { + GLB_DAC_CLK_PLL_32M, /*!< select PLL 32M as DAC clock source */ + GLB_DAC_CLK_XCLK, /*!< select XCLK as DAC clock source */ + GLB_DAC_CLK_AUDIO_PLL, /*!< select Audio PLL as DAC clock source */ +} GLB_DAC_CLK_Type; + +/** + * @brief GLB DIG clock source select type definition + */ +typedef enum { + GLB_DIG_CLK_PLL_32M, /*!< select PLL 32M as DIG clock source */ + GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */ + GLB_DIG_CLK_AUDIO_PLL, /*!< select Audio PLL as DIG clock source */ +} GLB_DIG_CLK_Type; + +/** + * @brief GLB BT bandwidth type definition + */ +typedef enum { + GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */ + GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */ +} GLB_BT_BANDWIDTH_Type; + +/** + * @brief GLB UART signal type definition + */ +typedef enum { + GLB_UART_SIG_0, /*!< UART signal 0 */ + GLB_UART_SIG_1, /*!< UART signal 1 */ + GLB_UART_SIG_2, /*!< UART signal 2 */ + GLB_UART_SIG_3, /*!< UART signal 3 */ + GLB_UART_SIG_4, /*!< UART signal 4 */ + GLB_UART_SIG_5, /*!< UART signal 5 */ + GLB_UART_SIG_6, /*!< UART signal 6 */ + GLB_UART_SIG_7, /*!< UART signal 7 */ +} GLB_UART_SIG_Type; + +/** + * @brief GLB UART signal function type definition + */ +typedef enum { + GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */ + GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */ + GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */ + GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */ + GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */ + GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */ + GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */ + GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */ +} GLB_UART_SIG_FUN_Type; + +/** + * @brief GLB DLL output clock type definition + */ +typedef enum { + GLB_DLL_CLK_57P6M, /*!< DLL output 57P6M clock */ + GLB_DLL_CLK_96M, /*!< DLL output 96M clock */ + GLB_DLL_CLK_144M, /*!< DLL output 144M clock */ + GLB_DLL_CLK_288M, /*!< DLL output 288M clock */ + GLB_DLL_CLK_MMDIV, /*!< DLL output mmdiv clock */ +} GLB_DLL_CLK_Type; + +/** + * @brief GLB GPIO interrupt trigger mode type definition + */ +typedef enum { + GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */ + GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */ + GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */ + GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */ +} GLB_GPIO_INT_TRIG_Type; + +/** + * @brief GLB GPIO interrupt control mode type definition + */ +typedef enum { + GLB_GPIO_INT_CONTROL_SYNC, /*!< GPIO interrupt sync mode */ + GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */ +} GLB_GPIO_INT_CONTROL_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + GLB_DLL_XTAL_NONE, /*!< XTAL is none */ + GLB_DLL_XTAL_32M, /*!< XTAL is 32M */ + GLB_DLL_XTAL_RC32M, /*!< XTAL is RC32M */ +} GLB_DLL_XTAL_Type; + +typedef enum { + GLB_AHB_CLOCK_IP_CPU, + GLB_AHB_CLOCK_IP_SDU, + GLB_AHB_CLOCK_IP_SEC, + GLB_AHB_CLOCK_IP_DMA_0, + GLB_AHB_CLOCK_IP_DMA_1, + GLB_AHB_CLOCK_IP_DMA_2, + GLB_AHB_CLOCK_IP_CCI, + GLB_AHB_CLOCK_IP_RF_TOP, + GLB_AHB_CLOCK_IP_GPIP, + GLB_AHB_CLOCK_IP_TZC, + GLB_AHB_CLOCK_IP_EF_CTRL, + GLB_AHB_CLOCK_IP_SF_CTRL, + GLB_AHB_CLOCK_IP_EMAC, + GLB_AHB_CLOCK_IP_UART0, + GLB_AHB_CLOCK_IP_UART1, + GLB_AHB_CLOCK_IP_UART2, + GLB_AHB_CLOCK_IP_UART3, + GLB_AHB_CLOCK_IP_UART4, + GLB_AHB_CLOCK_IP_SPI, + GLB_AHB_CLOCK_IP_I2C, + GLB_AHB_CLOCK_IP_PWM, + GLB_AHB_CLOCK_IP_TIMER, + GLB_AHB_CLOCK_IP_IR, + GLB_AHB_CLOCK_IP_CHECKSUM, + GLB_AHB_CLOCK_IP_QDEC, + GLB_AHB_CLOCK_IP_KYS, + GLB_AHB_CLOCK_IP_I2S, + GLB_AHB_CLOCK_IP_USB11, + GLB_AHB_CLOCK_IP_CAM, + GLB_AHB_CLOCK_IP_MJPEG, + GLB_AHB_CLOCK_IP_BT_BLE_NORMAL, + GLB_AHB_CLOCK_IP_BT_BLE_LP, + GLB_AHB_CLOCK_IP_ZB_NORMAL, + GLB_AHB_CLOCK_IP_ZB_LP, + GLB_AHB_CLOCK_IP_WIFI_NORMAL, + GLB_AHB_CLOCK_IP_WIFI_LP, + GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL, + GLB_AHB_CLOCK_IP_BT_BLE_2_LP, + GLB_AHB_CLOCK_IP_EMI_MISC, + GLB_AHB_CLOCK_IP_PSRAM0_CTRL, + GLB_AHB_CLOCK_IP_PSRAM1_CTRL, + GLB_AHB_CLOCK_IP_USB20, + GLB_AHB_CLOCK_IP_MIX2, + GLB_AHB_CLOCK_IP_AUDIO, + GLB_AHB_CLOCK_IP_SDH, +} GLB_AHB_CLOCK_IP_Type; + +/*@} end of group GLB_Public_Types */ + +/** @defgroup GLB_Public_Constants + * @{ + */ + +/** @defgroup GLB_ROOT_CLK_TYPE + * @{ + */ +#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \ + ((type) == GLB_ROOT_CLK_XTAL) || \ + ((type) == GLB_ROOT_CLK_DLL)) + +/** @defgroup GLB_SYS_CLK_TYPE + * @{ + */ +#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) || \ + ((type) == GLB_SYS_CLK_XTAL) || \ + ((type) == GLB_SYS_CLK_DLL57P6M) || \ + ((type) == GLB_SYS_CLK_DLL96M) || \ + ((type) == GLB_SYS_CLK_DLL144M)) + +/** @defgroup GLB_CAM_CLK_TYPE + * @{ + */ +#define IS_GLB_CAM_CLK_TYPE(type) (((type) == GLB_CAM_CLK_XCLK) || \ + ((type) == GLB_CAM_CLK_DLL96M)) + +/** @defgroup GLB_I2S_OUT_REF_CLK_TYPE + * @{ + */ +#define IS_GLB_I2S_OUT_REF_CLK_TYPE(type) (((type) == GLB_I2S_OUT_REF_CLK_NONE) || \ + ((type) == GLB_I2S_OUT_REF_CLK_SRC)) + +/** @defgroup GLB_QDEC_CLK_TYPE + * @{ + */ +#define IS_GLB_QDEC_CLK_TYPE(type) (((type) == GLB_QDEC_CLK_XCLK) || \ + ((type) == GLB_QDEC_CLK_F32K)) + +/** @defgroup GLB_DMA_CLK_ID_TYPE + * @{ + */ +#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \ + ((type) == GLB_DMA_CLK_DMA0_CH1) || \ + ((type) == GLB_DMA_CLK_DMA0_CH2) || \ + ((type) == GLB_DMA_CLK_DMA0_CH3) || \ + ((type) == GLB_DMA_CLK_DMA0_CH4) || \ + ((type) == GLB_DMA_CLK_DMA0_CH5) || \ + ((type) == GLB_DMA_CLK_DMA0_CH6) || \ + ((type) == GLB_DMA_CLK_DMA0_CH7)) + +/** @defgroup GLB_IR_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK)) + +/** @defgroup GLB_SFLASH_CLK_TYPE + * @{ + */ +#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_144M) || \ + ((type) == GLB_SFLASH_CLK_XCLK) || \ + ((type) == GLB_SFLASH_CLK_57P6M) || \ + ((type) == GLB_SFLASH_CLK_72M) || \ + ((type) == GLB_SFLASH_CLK_BCLK) || \ + ((type) == GLB_SFLASH_CLK_96M)) + +/** @defgroup GLB_CHIP_CLK_OUT_TYPE + * @{ + */ +#define IS_GLB_CHIP_CLK_OUT_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_NONE) || \ + ((type) == GLB_CHIP_CLK_OUT_I2S_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_XTAL_SOC_32M)) + +/** @defgroup GLB_ETH_REF_CLK_OUT_TYPE + * @{ + */ +#define IS_GLB_ETH_REF_CLK_OUT_TYPE(type) (((type) == GLB_ETH_REF_CLK_OUT_OUTSIDE_50M) || \ + ((type) == GLB_ETH_REF_CLK_OUT_INSIDE_50M)) + +/** @defgroup GLB_SPI_PAD_ACT_AS_TYPE + * @{ + */ +#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \ + ((type) == GLB_SPI_PAD_ACT_AS_MASTER)) + +/** @defgroup GLB_PKA_CLK_TYPE + * @{ + */ +#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \ + ((type) == GLB_PKA_CLK_DLL96M)) + +/** @defgroup BMX_ARB_TYPE + * @{ + */ +#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) || \ + ((type) == BMX_ARB_ROUND_ROBIN) || \ + ((type) == BMX_ARB_RANDOM)) + +/** @defgroup BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup BMX_ERR_INT_TYPE + * @{ + */ +#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \ + ((type) == BMX_ERR_INT_ALL)) + +/** @defgroup BMX_TO_INT_TYPE + * @{ + */ +#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \ + ((type) == BMX_TO_INT_ALL)) + +/** @defgroup GLB_EM_TYPE + * @{ + */ +#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \ + ((type) == GLB_EM_8KB) || \ + ((type) == GLB_EM_16KB)) + +/** @defgroup GLB_EMAC_CAM_PIN_TYPE + * @{ + */ +#define IS_GLB_EMAC_CAM_PIN_TYPE(type) (((type) == GLB_EMAC_CAM_PIN_EMAC) || \ + ((type) == GLB_EMAC_CAM_PIN_CAM)) + +/** @defgroup GLB_MTIMER_CLK_TYPE + * @{ + */ +#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \ + ((type) == GLB_MTIMER_CLK_32K)) + +/** @defgroup GLB_ADC_CLK_TYPE + * @{ + */ +#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_AUDIO_PLL) || \ + ((type) == GLB_ADC_CLK_XCLK)) + +/** @defgroup GLB_DAC_CLK_TYPE + * @{ + */ +#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_PLL_32M) || \ + ((type) == GLB_DAC_CLK_XCLK) || \ + ((type) == GLB_DAC_CLK_AUDIO_PLL)) + +/** @defgroup GLB_DIG_CLK_TYPE + * @{ + */ +#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \ + ((type) == GLB_DIG_CLK_XCLK) || \ + ((type) == GLB_DIG_CLK_AUDIO_PLL)) + +/** @defgroup GLB_BT_BANDWIDTH_TYPE + * @{ + */ +#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \ + ((type) == GLB_BT_BANDWIDTH_2M)) + +/** @defgroup GLB_UART_SIG_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \ + ((type) == GLB_UART_SIG_1) || \ + ((type) == GLB_UART_SIG_2) || \ + ((type) == GLB_UART_SIG_3) || \ + ((type) == GLB_UART_SIG_4) || \ + ((type) == GLB_UART_SIG_5) || \ + ((type) == GLB_UART_SIG_6) || \ + ((type) == GLB_UART_SIG_7)) + +/** @defgroup GLB_UART_SIG_FUN_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RXD)) + +/** @defgroup GLB_DLL_CLK_TYPE + * @{ + */ +#define IS_GLB_DLL_CLK_TYPE(type) (((type) == GLB_DLL_CLK_57P6M) || \ + ((type) == GLB_DLL_CLK_96M) || \ + ((type) == GLB_DLL_CLK_144M) || \ + ((type) == GLB_DLL_CLK_288M) || \ + ((type) == GLB_DLL_CLK_MMDIV)) + +/** @defgroup GLB_GPIO_INT_TRIG_TYPE + * @{ + */ +#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \ + ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \ + ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \ + ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL)) + +/** @defgroup GLB_GPIO_INT_CONTROL_TYPE + * @{ + */ +#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \ + ((type) == GLB_GPIO_INT_CONTROL_ASYNC)) + +/** @defgroup GLB_DLL_XTAL_TYPE + * @{ + */ +#define IS_GLB_DLL_XTAL_TYPE(type) (((type) == GLB_DLL_XTAL_NONE) || \ + ((type) == GLB_DLL_XTAL_32M) || \ + ((type) == GLB_DLL_XTAL_RC32M)) + +/*@} end of group GLB_Public_Constants */ + +/** @defgroup GLB_Public_Macros + * @{ + */ +#define UART_SIG_SWAP_GPIO0_GPIO7 0x01 /* GPIO0-7 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_GPIO8_GPIO15 0x02 /* GPIO8-15 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_NONE 0x00 /* GPIO0-22 uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */ +#define JTAG_SIG_SWAP_GPIO0_GPIO3 0x01 /* GPIO0-3 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO4_GPIO7 0x02 /* GPIO4-7 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO8_GPIO11 0x04 /* GPIO8-11 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */ + +#define GLB_AHB_CLOCK_CPU (0x0000000000000001UL) +#define GLB_AHB_CLOCK_SDU (0x0000000000000002UL) +#define GLB_AHB_CLOCK_SEC (0x0000000000000004UL) +#define GLB_AHB_CLOCK_DMA_0 (0x0000000000000008UL) +#define GLB_AHB_CLOCK_DMA_1 (0x0000000000000010UL) +#define GLB_AHB_CLOCK_DMA_2 (0x0000000000000020UL) +#define GLB_AHB_CLOCK_CCI (0x0000000000000040UL) +#define GLB_AHB_CLOCK_RF_TOP (0x0000000000000080UL) +#define GLB_AHB_CLOCK_GPIP (0x0000000000000100UL) +#define GLB_AHB_CLOCK_TZC (0x0000000000000200UL) +#define GLB_AHB_CLOCK_EF_CTRL (0x0000000000000400UL) +#define GLB_AHB_CLOCK_SF_CTRL (0x0000000000000800UL) +#define GLB_AHB_CLOCK_EMAC (0x0000000000001000UL) +#define GLB_AHB_CLOCK_UART0 (0x0000000000002000UL) +#define GLB_AHB_CLOCK_UART1 (0x0000000000004000UL) +#define GLB_AHB_CLOCK_UART2 (0x0000000000008000UL) +#define GLB_AHB_CLOCK_UART3 (0x0000000000010000UL) +#define GLB_AHB_CLOCK_UART4 (0x0000000000020000UL) +#define GLB_AHB_CLOCK_SPI (0x0000000000040000UL) +#define GLB_AHB_CLOCK_I2C (0x0000000000080000UL) +#define GLB_AHB_CLOCK_PWM (0x0000000000100000UL) +#define GLB_AHB_CLOCK_TIMER (0x0000000000200000UL) +#define GLB_AHB_CLOCK_IR (0x0000000000400000UL) +#define GLB_AHB_CLOCK_CHECKSUM (0x0000000000800000UL) +#define GLB_AHB_CLOCK_QDEC (0x0000000001000000UL) +#define GLB_AHB_CLOCK_KYS (0x0000000002000000UL) +#define GLB_AHB_CLOCK_I2S (0x0000000004000000UL) +#define GLB_AHB_CLOCK_USB11 (0x0000000008000000UL) +#define GLB_AHB_CLOCK_CAM (0x0000000010000000UL) +#define GLB_AHB_CLOCK_MJPEG (0x0000000020000000UL) +#define GLB_AHB_CLOCK_BT_BLE_NORMAL (0x0000000040000000UL) +#define GLB_AHB_CLOCK_BT_BLE_LP (0x0000000080000000UL) +#define GLB_AHB_CLOCK_ZB_NORMAL (0x0000000100000000UL) +#define GLB_AHB_CLOCK_ZB_LP (0x0000000200000000UL) +#define GLB_AHB_CLOCK_WIFI_NORMAL (0x0000000400000000UL) +#define GLB_AHB_CLOCK_WIFI_LP (0x0000000800000000UL) +#define GLB_AHB_CLOCK_BT_BLE_2_NORMAL (0x0000001000000000UL) +#define GLB_AHB_CLOCK_BT_BLE_2_LP (0x0000002000000000UL) +#define GLB_AHB_CLOCK_EMI_MISC (0x0000004000000000UL) +#define GLB_AHB_CLOCK_PSRAM0_CTRL (0x0000008000000000UL) +#define GLB_AHB_CLOCK_PSRAM1_CTRL (0x0000010000000000UL) +#define GLB_AHB_CLOCK_USB20 (0x0000020000000000UL) +#define GLB_AHB_CLOCK_MIX2 (0x0000040000000000UL) +#define GLB_AHB_CLOCK_AUDIO (0x0000080000000000UL) +#define GLB_AHB_CLOCK_SDH (0x0000100000000000UL) + +/*@} end of group GLB_Public_Macros */ + +/** @defgroup GLB_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void); +void BMX_TO_IRQHandler(void); +void GPIO_INT0_IRQHandler(void); +#endif +/*----------*/ +GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void); +BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv); +uint8_t GLB_Get_BCLK_Div(void); +uint8_t GLB_Get_HCLK_Div(void); +BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType); +BL_Err_Type GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq); +BL_Err_Type System_Core_Clock_Update_From_RC32M(void); +/*----------*/ +BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable); +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable); +BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef); +BL_Err_Type GLB_Set_USB_CLK(uint8_t enable); +BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk); +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel); +BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel); +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div); +BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable); +BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable); +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div); +BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable); +BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable); +BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel); +/*----------*/ +BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel); +BL_Err_Type GLB_SW_System_Reset(void); +BL_Err_Type GLB_SW_CPU_Reset(void); +BL_Err_Type GLB_SW_POR_Reset(void); +BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1); +BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1); +uint64_t GLB_PER_Clock_Gate_Status_Get(void); +BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips); +BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips); +/*----------*/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg); +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void); +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void); +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType); +uint32_t GLB_BMX_Get_Err_Addr(void); +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type GLB_Set_SRAM_RET(uint32_t value); +uint32_t GLB_Get_SRAM_RET(void); +BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value); +uint32_t GLB_Get_SRAM_SLP(void); +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value); +uint32_t GLB_Get_SRAM_PARM(void); +/*----------*/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType); +/*----------*/ +BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType); +BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable); +BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable); +BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable); +BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable); +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState); +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod); +BL_Err_Type GLB_Select_Internal_Flash(void); +BL_Err_Type GLB_Select_External_Flash(void); +BL_Err_Type GLB_Deswap_Flash_Pin(void); +BL_Err_Type GLB_Swap_Flash_CS_IO2_Pin(); +BL_Err_Type GLB_Swap_Flash_IO0_IO3_Pin(); +BL_Err_Type GLB_Swap_Flash_Pin(void); +BL_Err_Type GLB_Select_Internal_PSram(void); +/*----------*/ +BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div); +/*----------*/ +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel); +BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div); +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, + uint8_t pti, uint8_t channel); +/*----------*/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun); +/*----------*/ +BL_Err_Type GLB_Power_Off_DLL(void); +BL_Err_Type GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType); +BL_Err_Type GLB_Enable_DLL_All_Clks(void); +BL_Err_Type GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk); +BL_Err_Type GLB_Disable_DLL_All_Clks(void); +BL_Err_Type GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk); +/*----------*/ +BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio); +BL_Err_Type GLB_IR_LED_Driver_Enable(void); +BL_Err_Type GLB_IR_LED_Driver_Disable(void); +BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio); +BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio); +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias); +/*----------*/ +BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg); +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt); +BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Set_Flash_Pad_HZ(void); +BL_Err_Type GLB_Set_Psram_Pad_HZ(void); +uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val); +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); +BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear); +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, + GLB_GPIO_INT_TRIG_Type intTrgMod); +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); +BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear); +BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, + GLB_GPIO_INT_TRIG_Type intTrgMod); +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void); +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); +BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); +/*----------*/; + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_GLB_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..fb47d2f3c187e1156adb5db754001d2acdfe81c5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h @@ -0,0 +1,951 @@ +/** + + ****************************************************************************** + + * @file bl702_gpio.h + + * @version V1.2 + + * @date 2020-09-04 + + * @brief This file is the description of.IP register + + ****************************************************************************** + + * @attention + + * + + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ + * + + * Redistribution and use in source and binary forms, with or without modification, + + * are permitted provided that the following conditions are met: + + * 1. Redistributions of source code must retain the above copyright notice, + + * this list of conditions and the following disclaimer. + + * 2. Redistributions in binary form must reproduce the above copyright notice, + + * this list of conditions and the following disclaimer in the documentation + + * and/or other materials provided with the distribution. + + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + + * may be used to endorse or promote products derived from this software + + * without specific prior written permission. + + * + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + * + + ****************************************************************************** + + */ + +#ifndef __BL702_GPIO_H__ +#define __BL702_GPIO_H__ + +typedef enum { + GLB_GPIO_PIN_0 = 0, + GLB_GPIO_PIN_1, + GLB_GPIO_PIN_2, + GLB_GPIO_PIN_3, + GLB_GPIO_PIN_4, + GLB_GPIO_PIN_5, + GLB_GPIO_PIN_6, + GLB_GPIO_PIN_7, + GLB_GPIO_PIN_8, + GLB_GPIO_PIN_9, + GLB_GPIO_PIN_10, + GLB_GPIO_PIN_11, + GLB_GPIO_PIN_12, + GLB_GPIO_PIN_13, + GLB_GPIO_PIN_14, + GLB_GPIO_PIN_15, + GLB_GPIO_PIN_16, + GLB_GPIO_PIN_17, + GLB_GPIO_PIN_18, + GLB_GPIO_PIN_19, + GLB_GPIO_PIN_20, + GLB_GPIO_PIN_21, + GLB_GPIO_PIN_22, + GLB_GPIO_PIN_23, + GLB_GPIO_PIN_24, + GLB_GPIO_PIN_25, + GLB_GPIO_PIN_26, + GLB_GPIO_PIN_27, + GLB_GPIO_PIN_28, + GLB_GPIO_PIN_29, + GLB_GPIO_PIN_30, + GLB_GPIO_PIN_31, + GLB_GPIO_PIN_MAX, +} GLB_GPIO_Type; + +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_AF ((uint32_t)0x00000002U) /*!< Alternate function */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function */ +#define GPIO_PULL_UP ((uint32_t)0x00000000U) /*!< GPIO pull up */ +#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) /*!< GPIO pull down */ +#define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */ + +typedef enum { + GPIO_FUN_CLK_OUT = 0, + GPIO_FUN_BT_COEXIST = 1, + GPIO_FUN_FLASH_PSRAM = 2, + GPIO_FUN_QSPI = 2, + GPIO_FUN_I2S = 3, + GPIO_FUN_SPI = 4, + GPIO_FUN_I2C = 6, + GPIO_FUN_UART = 7, + GPIO_FUN_PWM = 8, + GPIO_FUN_CAM = 9, + GPIO_FUN_ANALOG = 10, + GPIO_FUN_USB = 10, + GPIO_FUN_DAC = 10, + GPIO_FUN_ADC = 10, + GPIO_FUN_GPIO = 11, + GPIO_FUN_RF_TEST = 12, + GPIO_FUN_SCAN = 13, + GPIO_FUN_E21_JTAG = 14, + GPIO_FUN_DEBUG = 15, + GPIO_FUN_EXTERNAL_PA = 16, + GPIO_FUN_USB_TRANCEIVER = 17, + GPIO_FUN_USB_CONTROLLER = 18, + GPIO_FUN_ETHER_MAC = 19, + GPIO_FUN_EMAC = 19, + GPIO_FUN_QDEC = 20, + GPIO_FUN_QDEC_LED = 24, + GPIO_FUN_KEY_SCAN_IN = 21, + GPIO_FUN_KEY_SCAN_ROW = 21, + GPIO_FUN_KEY_SCAN_DRIVE = 22, + GPIO_FUN_KEY_SCAN_COL = 22, + GPIO_FUN_CAM_MISC = 23, + GPIO_FUN_UART0_RTS = 0x70, + GPIO_FUN_UART0_CTS = 0x71, + GPIO_FUN_UART0_TX = 0x72, + GPIO_FUN_UART0_RX = 0x73, + GPIO_FUN_UART1_RTS = 0x74, + GPIO_FUN_UART1_CTS = 0x75, + GPIO_FUN_UART1_TX = 0x76, + GPIO_FUN_UART1_RX = 0x77, + GPIO_FUN_GPIO_OUTPUT_UP = 240, + GPIO_FUN_GPIO_OUTPUT_DOWN = 241, + GPIO_FUN_GPIO_OUTPUT_NONE = 242, + GPIO_FUN_GPIO_INPUT_UP = 243, + GPIO_FUN_GPIO_INPUT_DOWN = 244, + GPIO_FUN_GPIO_INPUT_NONE = 245, + GPIO_FUN_GPIO_EXTI_RISING_EDGE = 246, + GPIO_FUN_GPIO_EXTI_FALLING_EDGE = 247, + GPIO_FUN_GPIO_EXTI_HIGH_LEVEL = 248, + GPIO_FUN_GPIO_EXTI_LOW_LEVEL = 249, + GPIO_FUN_WAKEUP = 250, + GPIO_FUN_UNUSED = 255 +} GLB_GPIO_FUNC_Type; + +typedef struct +{ + uint8_t gpioPin; + uint8_t gpioFun; + uint8_t gpioMode; + uint8_t pullType; + uint8_t drive; + uint8_t smtCtrl; +} GLB_GPIO_Cfg_Type; + +/* GPIO0 function definition */ +#define GPIO0_FUN_CLK_OUT_0 0 +#define GPIO0_FUN_BT_ABORT 1 +#define GPIO0_FUN_UNUSED2 2 +#define GPIO0_FUN_I2S0_BCLK 3 +#define GPIO0_FUN_SPI_0_MISO_SPI_0_MOSI 4 +#define GPIO0_FUN_I2C0_SCL 6 +#define GPIO0_FUN_UART_SIG0_UART_SIG4 7 +#define GPIO0_FUN_PWM_CH0 8 +#define GPIO0_FUN_PIX_CLK 9 +#define GPIO0_FUN_UNUSED10 10 +#define GPIO0_FUN_REG_GPIO_0 11 +#define GPIO0_FUN_UNUSED12 12 +#define GPIO0_FUN_SCAN_IN_0 13 +#define GPIO0_FUN_E21_TMS_E21_TCK 14 +#define GPIO0_FUN_S_CCI_CLK 15 +#define GPIO0_FUN_FEM_GPIO_0 16 +#define GPIO0_FUN_USB_TX_DN_USB_RX_DN 17 +#define GPIO0_FUN_USB_SUS 18 +#define GPIO0_FUN_MII_REF_CLK 19 +#define GPIO0_FUN_QDEC0_A 20 +#define GPIO0_FUN_ROW_I_0 21 +#define GPIO0_FUN_COL_O_0 22 +#define GPIO0_FUN_CAM_PWRDN 23 +/* GPIO1 function definition */ +#define GPIO1_FUN_CLK_OUT_1 0 +#define GPIO1_FUN_BT_ACTIVE 1 +#define GPIO1_FUN_UNUSED2 2 +#define GPIO1_FUN_I2S0_FS 3 +#define GPIO1_FUN_SPI_0_MOSI_SPI_0_MISO 4 +#define GPIO1_FUN_I2C0_SDA 6 +#define GPIO1_FUN_UART_SIG1_UART_SIG5 7 +#define GPIO1_FUN_PWM_CH1 8 +#define GPIO1_FUN_FRAME_VLD 9 +#define GPIO1_FUN_UNUSED10 10 +#define GPIO1_FUN_REG_GPIO_1 11 +#define GPIO1_FUN_UNUSED12 12 +#define GPIO1_FUN_SCAN_IN_1 13 +#define GPIO1_FUN_E21_TDI_E21_TDO 14 +#define GPIO1_FUN_S_CCI_CS 15 +#define GPIO1_FUN_FEM_GPIO_1 16 +#define GPIO1_FUN_USB_TX_OE 17 +#define GPIO1_FUN_USB_ENUM 18 +#define GPIO1_FUN_MII_TXD_0 19 +#define GPIO1_FUN_QDEC0_B 20 +#define GPIO1_FUN_ROW_I_1 21 +#define GPIO1_FUN_COL_O_1 22 +#define GPIO1_FUN_CAM_REF_CLK 23 +/* GPIO2 function definition */ +#define GPIO2_FUN_CLK_OUT_0 0 +#define GPIO2_FUN_BT_PRI 1 +#define GPIO2_FUN_UNUSED2 2 +#define GPIO2_FUN_I2S0_DIO_I2S0_DO 3 +#define GPIO2_FUN_SPI_0_SS 4 +#define GPIO2_FUN_I2C0_SCL 6 +#define GPIO2_FUN_UART_SIG2_UART_SIG6 7 +#define GPIO2_FUN_PWM_CH2 8 +#define GPIO2_FUN_LINE_VLD 9 +#define GPIO2_FUN_UNUSED10 10 +#define GPIO2_FUN_REG_GPIO_2 11 +#define GPIO2_FUN_UNUSED12 12 +#define GPIO2_FUN_SCAN_IN_2 13 +#define GPIO2_FUN_E21_TCK_E21_TMS 14 +#define GPIO2_FUN_S_CCI_DATA_0 15 +#define GPIO2_FUN_FEM_GPIO_2 16 +#define GPIO2_FUN_USB_TX_DP_USB_RX_DP 17 +#define GPIO2_FUN_USB_OEB 18 +#define GPIO2_FUN_MII_TXD_1 19 +#define GPIO2_FUN_QDEC0_LED 20 +#define GPIO2_FUN_ROW_I_2 21 +#define GPIO2_FUN_COL_O_2 22 +#define GPIO2_FUN_CAM_RESET 23 +/* GPIO3 function definition */ +#define GPIO3_FUN_CLK_OUT_1 0 +#define GPIO3_FUN_BT_ABORT 1 +#define GPIO3_FUN_UNUSED2 2 +#define GPIO3_FUN_I2S0_RCLK_O_I2S0_DI 3 +#define GPIO3_FUN_SPI_0_SCLK 4 +#define GPIO3_FUN_I2C0_SDA 6 +#define GPIO3_FUN_UART_SIG3_UART_SIG7 7 +#define GPIO3_FUN_PWM_CH3 8 +#define GPIO3_FUN_PIX_DAT0 9 +#define GPIO3_FUN_UNUSED10 10 +#define GPIO3_FUN_REG_GPIO_3 11 +#define GPIO3_FUN_RF_TEST_0 12 +#define GPIO3_FUN_UNUSED13 13 +#define GPIO3_FUN_E21_TDO_E21_TDI 14 +#define GPIO3_FUN_DEBUG_0 15 +#define GPIO3_FUN_FEM_GPIO_3 16 +#define GPIO3_FUN_USB_SUS_EXT 17 +#define GPIO3_FUN_VOP 18 +#define GPIO3_FUN_UNUSED19 19 +#define GPIO3_FUN_QDEC1_A 20 +#define GPIO3_FUN_ROW_I_3 21 +#define GPIO3_FUN_COL_O_3 22 +#define GPIO3_FUN_CAM_PWRDN 23 +/* GPIO4 function definition */ +#define GPIO4_FUN_CLK_OUT_0 0 +#define GPIO4_FUN_BT_ACTIVE 1 +#define GPIO4_FUN_UNUSED2 2 +#define GPIO4_FUN_I2S0_BCLK 3 +#define GPIO4_FUN_SPI_0_MISO_SPI_0_MOSI 4 +#define GPIO4_FUN_I2C0_SCL 6 +#define GPIO4_FUN_UART_SIG4_UART_SIG0 7 +#define GPIO4_FUN_PWM_CH4 8 +#define GPIO4_FUN_PIX_DAT1 9 +#define GPIO4_FUN_UNUSED10 10 +#define GPIO4_FUN_REG_GPIO_4 11 +#define GPIO4_FUN_RF_TEST_1 12 +#define GPIO4_FUN_UNUSED13 13 +#define GPIO4_FUN_E21_TMS_E21_TCK 14 +#define GPIO4_FUN_DEBUG_1 15 +#define GPIO4_FUN_FEM_GPIO_4 16 +#define GPIO4_FUN_USB_ENUM_EXT 17 +#define GPIO4_FUN_VOM 18 +#define GPIO4_FUN_UNUSED19 19 +#define GPIO4_FUN_QDEC1_B 20 +#define GPIO4_FUN_ROW_I_4 21 +#define GPIO4_FUN_COL_O_4 22 +#define GPIO4_FUN_CAM_REF_CLK 23 +/* GPIO5 function definition */ +#define GPIO5_FUN_CLK_OUT_1 0 +#define GPIO5_FUN_BT_PRI 1 +#define GPIO5_FUN_UNUSED2 2 +#define GPIO5_FUN_I2S0_FS 3 +#define GPIO5_FUN_SPI_0_MOSI_SPI_0_MISO 4 +#define GPIO5_FUN_I2C0_SDA 6 +#define GPIO5_FUN_UART_SIG5_UART_SIG1 7 +#define GPIO5_FUN_PWM_CH0 8 +#define GPIO5_FUN_PIX_DAT2 9 +#define GPIO5_FUN_UNUSED10 10 +#define GPIO5_FUN_REG_GPIO_5 11 +#define GPIO5_FUN_RF_TEST_2 12 +#define GPIO5_FUN_UNUSED13 13 +#define GPIO5_FUN_E21_TDI_E21_TDO 14 +#define GPIO5_FUN_DEBUG_2 15 +#define GPIO5_FUN_FEM_GPIO_0 16 +#define GPIO5_FUN_USB_TX_DN_USB_RX_DN 17 +#define GPIO5_FUN_BD 18 +#define GPIO5_FUN_UNUSED19 19 +#define GPIO5_FUN_QDEC1_LED 20 +#define GPIO5_FUN_ROW_I_5 21 +#define GPIO5_FUN_COL_O_5 22 +#define GPIO5_FUN_CAM_RESET 23 +/* GPIO6 function definition */ +#define GPIO6_FUN_CLK_OUT_0 0 +#define GPIO6_FUN_BT_ABORT 1 +#define GPIO6_FUN_UNUSED2 2 +#define GPIO6_FUN_I2S0_DIO_I2S0_DO 3 +#define GPIO6_FUN_SPI_0_SS 4 +#define GPIO6_FUN_I2C0_SCL 6 +#define GPIO6_FUN_UART_SIG6_UART_SIG2 7 +#define GPIO6_FUN_PWM_CH1 8 +#define GPIO6_FUN_PIX_DAT3 9 +#define GPIO6_FUN_UNUSED10 10 +#define GPIO6_FUN_REG_GPIO_6 11 +#define GPIO6_FUN_RF_TEST_3 12 +#define GPIO6_FUN_UNUSED13 13 +#define GPIO6_FUN_E21_TCK_E21_TMS 14 +#define GPIO6_FUN_DEBUG_3 15 +#define GPIO6_FUN_FEM_GPIO_1 16 +#define GPIO6_FUN_USB_TX_OE 17 +#define GPIO6_FUN_VIP 18 +#define GPIO6_FUN_UNUSED19 19 +#define GPIO6_FUN_QDEC2_A 20 +#define GPIO6_FUN_ROW_I_6 21 +#define GPIO6_FUN_COL_O_6 22 +#define GPIO6_FUN_CAM_PWRDN 23 +/* GPIO7 function definition */ +#define GPIO7_FUN_CLK_OUT_1 0 +#define GPIO7_FUN_BT_ACTIVE 1 +#define GPIO7_FUN_UNUSED2 2 +#define GPIO7_FUN_I2S0_RCLK_O_I2S0_DI 3 +#define GPIO7_FUN_SPI_0_SCLK 4 +#define GPIO7_FUN_I2C0_SDA 6 +#define GPIO7_FUN_UART_SIG7_UART_SIG3 7 +#define GPIO7_FUN_PWM_CH2 8 +#define GPIO7_FUN_UNUSED9 9 +#define GPIO7_FUN_USB_DP_GPIP_CH_6_GPDAC_VREF_EXT 10 +#define GPIO7_FUN_REG_GPIO_7 11 +#define GPIO7_FUN_UNUSED12 12 +#define GPIO7_FUN_SCAN_RSTB 13 +#define GPIO7_FUN_E21_TDO_E21_TDI 14 +#define GPIO7_FUN_S_CCI_DATA_1 15 +#define GPIO7_FUN_FEM_GPIO_2 16 +#define GPIO7_FUN_USB_TX_DP_USB_RX_DP 17 +#define GPIO7_FUN_VIM 18 +#define GPIO7_FUN_MII_RXD_0 19 +#define GPIO7_FUN_QDEC2_B 20 +#define GPIO7_FUN_ROW_I_7 21 +#define GPIO7_FUN_COL_O_7 22 +#define GPIO7_FUN_CAM_REF_CLK 23 +/* GPIO8 function definition */ +#define GPIO8_FUN_CLK_OUT_0 0 +#define GPIO8_FUN_BT_PRI 1 +#define GPIO8_FUN_UNUSED2 2 +#define GPIO8_FUN_I2S0_BCLK 3 +#define GPIO8_FUN_SPI_0_MISO_SPI_0_MOSI 4 +#define GPIO8_FUN_I2C0_SCL 6 +#define GPIO8_FUN_UART_SIG0_UART_SIG4 7 +#define GPIO8_FUN_PWM_CH3 8 +#define GPIO8_FUN_UNUSED9 9 +#define GPIO8_FUN_USB_DM_GPIP_CH_0 10 +#define GPIO8_FUN_REG_GPIO_8 11 +#define GPIO8_FUN_RF_TEST_4 12 +#define GPIO8_FUN_SCAN_CLK 13 +#define GPIO8_FUN_E21_TMS_E21_TCK 14 +#define GPIO8_FUN_DEBUG_4 15 +#define GPIO8_FUN_FEM_GPIO_3 16 +#define GPIO8_FUN_USB_SUS_EXT 17 +#define GPIO8_FUN_RCV 18 +#define GPIO8_FUN_MII_RXD_1 19 +#define GPIO8_FUN_QDEC2_LED 20 +#define GPIO8_FUN_ROW_I_0 21 +#define GPIO8_FUN_COL_O_8 22 +#define GPIO8_FUN_CAM_RESET 23 +/* GPIO9 function definition */ +#define GPIO9_FUN_CLK_OUT_1 0 +#define GPIO9_FUN_BT_ABORT 1 +#define GPIO9_FUN_UNUSED2 2 +#define GPIO9_FUN_I2S0_FS 3 +#define GPIO9_FUN_SPI_0_MOSI_SPI_0_MISO 4 +#define GPIO9_FUN_I2C0_SDA 6 +#define GPIO9_FUN_UART_SIG1_UART_SIG5 7 +#define GPIO9_FUN_PWM_CH4 8 +#define GPIO9_FUN_UNUSED9 9 +#define GPIO9_FUN_PMIP_DC_TP_CLKPLL_DC_TP_GPIP_CH_7 10 +#define GPIO9_FUN_REG_GPIO_9 11 +#define GPIO9_FUN_RF_TEST_5 12 +#define GPIO9_FUN_SCAN_EN 13 +#define GPIO9_FUN_E21_TDI_E21_TDO 14 +#define GPIO9_FUN_DEBUG_5 15 +#define GPIO9_FUN_FEM_GPIO_4 16 +#define GPIO9_FUN_USB_ENUM_EXT 17 +#define GPIO9_FUN_USB_SUS 18 +#define GPIO9_FUN_UNUSED19 19 +#define GPIO9_FUN_QDEC0_A 20 +#define GPIO9_FUN_ROW_I_1 21 +#define GPIO9_FUN_COL_O_9 22 +#define GPIO9_FUN_CAM_PWRDN 23 +/* GPIO10 function definition */ +#define GPIO10_FUN_CLK_OUT_0 0 +#define GPIO10_FUN_BT_ACTIVE 1 +#define GPIO10_FUN_UNUSED2 2 +#define GPIO10_FUN_I2S0_DIO_I2S0_DO 3 +#define GPIO10_FUN_SPI_0_SS 4 +#define GPIO10_FUN_I2C0_SCL 6 +#define GPIO10_FUN_UART_SIG2_UART_SIG6 7 +#define GPIO10_FUN_PWM_CH0 8 +#define GPIO10_FUN_UNUSED9 9 +#define GPIO10_FUN_MICBIAS 10 +#define GPIO10_FUN_REG_GPIO_10 11 +#define GPIO10_FUN_RF_TEST_6 12 +#define GPIO10_FUN_UNUSED13 13 +#define GPIO10_FUN_E21_TCK_E21_TMS 14 +#define GPIO10_FUN_DEBUG_6 15 +#define GPIO10_FUN_FEM_GPIO_0 16 +#define GPIO10_FUN_USB_TX_DN_USB_RX_DN 17 +#define GPIO10_FUN_USB_ENUM 18 +#define GPIO10_FUN_UNUSED19 19 +#define GPIO10_FUN_QDEC0_B 20 +#define GPIO10_FUN_ROW_I_2 21 +#define GPIO10_FUN_COL_O_10 22 +#define GPIO10_FUN_CAM_REF_CLK 23 +/* GPIO11 function definition */ +#define GPIO11_FUN_CLK_OUT_1 0 +#define GPIO11_FUN_BT_PRI 1 +#define GPIO11_FUN_UNUSED2 2 +#define GPIO11_FUN_I2S0_RCLK_O_I2S0_DI 3 +#define GPIO11_FUN_SPI_0_SCLK 4 +#define GPIO11_FUN_I2C0_SDA 6 +#define GPIO11_FUN_UART_SIG3_UART_SIG7 7 +#define GPIO11_FUN_PWM_CH1 8 +#define GPIO11_FUN_UNUSED9 9 +#define GPIO11_FUN_GPIP_CH_3 10 +#define GPIO11_FUN_REG_GPIO_11 11 +#define GPIO11_FUN_RF_TEST_7 12 +#define GPIO11_FUN_UNUSED13 13 +#define GPIO11_FUN_E21_TDO_E21_TDI 14 +#define GPIO11_FUN_DEBUG_7 15 +#define GPIO11_FUN_FEM_GPIO_1 16 +#define GPIO11_FUN_USB_TX_OE 17 +#define GPIO11_FUN_USB_OEB 18 +#define GPIO11_FUN_UNUSED19 19 +#define GPIO11_FUN_QDEC0_LED 20 +#define GPIO11_FUN_ROW_I_3 21 +#define GPIO11_FUN_COL_O_11 22 +#define GPIO11_FUN_CAM_RESET 23 +/* GPIO12 function definition */ +#define GPIO12_FUN_CLK_OUT_0 0 +#define GPIO12_FUN_BT_ABORT 1 +#define GPIO12_FUN_UNUSED2 2 +#define GPIO12_FUN_I2S0_BCLK 3 +#define GPIO12_FUN_SPI_0_MISO_SPI_0_MOSI 4 +#define GPIO12_FUN_I2C0_SCL 6 +#define GPIO12_FUN_UART_SIG4_UART_SIG0 7 +#define GPIO12_FUN_PWM_CH2 8 +#define GPIO12_FUN_PIX_DAT4 9 +#define GPIO12_FUN_GPIP_CH_4 10 +#define GPIO12_FUN_REG_GPIO_12 11 +#define GPIO12_FUN_RF_TEST_8 12 +#define GPIO12_FUN_UNUSED13 13 +#define GPIO12_FUN_E21_TMS_E21_TCK 14 +#define GPIO12_FUN_DEBUG_8 15 +#define GPIO12_FUN_FEM_GPIO_2 16 +#define GPIO12_FUN_USB_TX_DP_USB_RX_DP 17 +#define GPIO12_FUN_VOP 18 +#define GPIO12_FUN_UNUSED19 19 +#define GPIO12_FUN_QDEC1_A 20 +#define GPIO12_FUN_ROW_I_4 21 +#define GPIO12_FUN_COL_O_12 22 +#define GPIO12_FUN_CAM_PWRDN 23 +/* GPIO13 function definition */ +#define GPIO13_FUN_CLK_OUT_1 0 +#define GPIO13_FUN_BT_ACTIVE 1 +#define GPIO13_FUN_UNUSED2 2 +#define GPIO13_FUN_I2S0_FS 3 +#define GPIO13_FUN_SPI_0_MOSI_SPI_0_MISO 4 +#define GPIO13_FUN_I2C0_SDA 6 +#define GPIO13_FUN_UART_SIG5_UART_SIG1 7 +#define GPIO13_FUN_PWM_CH3 8 +#define GPIO13_FUN_UNUSED9 9 +#define GPIO13_FUN_UNUSED10 10 +#define GPIO13_FUN_REG_GPIO_13 11 +#define GPIO13_FUN_UNUSED12 12 +#define GPIO13_FUN_UNUSED13 13 +#define GPIO13_FUN_E21_TDI_E21_TDO 14 +#define GPIO13_FUN_DEBUG_9 15 +#define GPIO13_FUN_FEM_GPIO_3 16 +#define GPIO13_FUN_USB_SUS_EXT 17 +#define GPIO13_FUN_VOM 18 +#define GPIO13_FUN_UNUSED19 19 +#define GPIO13_FUN_QDEC1_B 20 +#define GPIO13_FUN_ROW_I_5 21 +#define GPIO13_FUN_COL_O_13 22 +#define GPIO13_FUN_CAM_REF_CLK 23 +/* GPIO14 function definition */ +#define GPIO14_FUN_CLK_OUT_0 0 +#define GPIO14_FUN_BT_PRI 1 +#define GPIO14_FUN_UNUSED2 2 +#define GPIO14_FUN_I2S0_DIO_I2S0_DO 3 +#define GPIO14_FUN_SPI_0_SS 4 +#define GPIO14_FUN_I2C0_SCL 6 +#define GPIO14_FUN_UART_SIG6_UART_SIG2 7 +#define GPIO14_FUN_PWM_CH4 8 +#define GPIO14_FUN_UNUSED9 9 +#define GPIO14_FUN_GPIP_CH_5_ATEST_OUT_0 10 +#define GPIO14_FUN_REG_GPIO_14 11 +#define GPIO14_FUN_RF_TEST_9 12 +#define GPIO14_FUN_SCAN_OUT_0 13 +#define GPIO14_FUN_E21_TCK_E21_TMS 14 +#define GPIO14_FUN_DEBUG_10 15 +#define GPIO14_FUN_FEM_GPIO_4 16 +#define GPIO14_FUN_USB_ENUM_EXT 17 +#define GPIO14_FUN_BD 18 +#define GPIO14_FUN_UNUSED19 19 +#define GPIO14_FUN_QDEC1_LED 20 +#define GPIO14_FUN_ROW_I_6 21 +#define GPIO14_FUN_COL_O_14 22 +#define GPIO14_FUN_CAM_RESET 23 +/* GPIO15 function definition */ +#define GPIO15_FUN_CLK_OUT_1 0 +#define GPIO15_FUN_BT_ABORT 1 +#define GPIO15_FUN_UNUSED2 2 +#define GPIO15_FUN_I2S0_RCLK_O_I2S0_DI 3 +#define GPIO15_FUN_SPI_0_SCLK 4 +#define GPIO15_FUN_I2C0_SDA 6 +#define GPIO15_FUN_UART_SIG7_UART_SIG3 7 +#define GPIO15_FUN_PWM_CH0 8 +#define GPIO15_FUN_UNUSED9 9 +#define GPIO15_FUN_GPIP_CH_1_ATEST_OUT_1 10 +#define GPIO15_FUN_REG_GPIO_15 11 +#define GPIO15_FUN_RF_TEST_10 12 +#define GPIO15_FUN_SCAN_OUT_1 13 +#define GPIO15_FUN_E21_TDO_E21_TDI 14 +#define GPIO15_FUN_DEBUG_11 15 +#define GPIO15_FUN_FEM_GPIO_0 16 +#define GPIO15_FUN_USB_TX_DN_USB_RX_DN 17 +#define GPIO15_FUN_VIP 18 +#define GPIO15_FUN_UNUSED19 19 +#define GPIO15_FUN_QDEC2_A 20 +#define GPIO15_FUN_ROW_I_7 21 +#define GPIO15_FUN_COL_O_15 22 +#define GPIO15_FUN_CAM_PWRDN 23 +/* GPIO16 function definition */ +#define GPIO16_FUN_CLK_OUT_0 0 +#define GPIO16_FUN_BT_ACTIVE 1 +#define GPIO16_FUN_UNUSED2 2 +#define GPIO16_FUN_I2S0_BCLK 3 +#define GPIO16_FUN_SPI_0_MISO_SPI_0_MOSI 4 +#define GPIO16_FUN_I2C0_SCL 6 +#define GPIO16_FUN_UART_SIG0_UART_SIG4 7 +#define GPIO16_FUN_PWM_CH1 8 +#define GPIO16_FUN_UNUSED9 9 +#define GPIO16_FUN_UNUSED10 10 +#define GPIO16_FUN_REG_GPIO_16 11 +#define GPIO16_FUN_RF_TEST_11 12 +#define GPIO16_FUN_UNUSED13 13 +#define GPIO16_FUN_E21_TMS_E21_TCK 14 +#define GPIO16_FUN_DEBUG_12 15 +#define GPIO16_FUN_FEM_GPIO_1 16 +#define GPIO16_FUN_USB_TX_OE 17 +#define GPIO16_FUN_VIM 18 +#define GPIO16_FUN_UNUSED19 19 +#define GPIO16_FUN_QDEC2_B 20 +#define GPIO16_FUN_ROW_I_0 21 +#define GPIO16_FUN_COL_O_16 22 +#define GPIO16_FUN_CAM_REF_CLK 23 +/* GPIO17 function definition */ +#define GPIO17_FUN_CLK_OUT_1 0 +#define GPIO17_FUN_BT_PRI 1 +#define GPIO17_FUN_SF_IO_0_SF2_CS2 2 +#define GPIO17_FUN_I2S0_FS 3 +#define GPIO17_FUN_SPI_0_MOSI_SPI_0_MISO 4 +#define GPIO17_FUN_I2C0_SDA 6 +#define GPIO17_FUN_UART_SIG1_UART_SIG5 7 +#define GPIO17_FUN_PWM_CH2 8 +#define GPIO17_FUN_PIX_DAT4 9 +#define GPIO17_FUN_GPIP_CH_2_PSW_IRRCV 10 +#define GPIO17_FUN_REG_GPIO_17 11 +#define GPIO17_FUN_RF_TEST_12 12 +#define GPIO17_FUN_SCAN_OUT_2 13 +#define GPIO17_FUN_E21_TDI_E21_TDO 14 +#define GPIO17_FUN_DEBUG_13 15 +#define GPIO17_FUN_FEM_GPIO_2 16 +#define GPIO17_FUN_USB_TX_DP_USB_RX_DP 17 +#define GPIO17_FUN_RCV 18 +#define GPIO17_FUN_UNUSED19 19 +#define GPIO17_FUN_QDEC2_LED 20 +#define GPIO17_FUN_ROW_I_1 21 +#define GPIO17_FUN_COL_O_17 22 +#define GPIO17_FUN_CAM_RESET 23 +/* GPIO18 function definition */ +#define GPIO18_FUN_CLK_OUT_0 0 +#define GPIO18_FUN_BT_ABORT 1 +#define GPIO18_FUN_SF_IO_1 2 +#define GPIO18_FUN_I2S0_DIO_I2S0_DO 3 +#define GPIO18_FUN_SPI_0_SS 4 +#define GPIO18_FUN_I2C0_SCL 6 +#define GPIO18_FUN_UART_SIG2_UART_SIG6 7 +#define GPIO18_FUN_PWM_CH3 8 +#define GPIO18_FUN_PIX_DAT5 9 +#define GPIO18_FUN_GPIP_CH_8 10 +#define GPIO18_FUN_REG_GPIO_18 11 +#define GPIO18_FUN_RF_TEST_13 12 +#define GPIO18_FUN_UNUSED13 13 +#define GPIO18_FUN_E21_TCK_E21_TMS 14 +#define GPIO18_FUN_M_CCI_CLK_DEBUG_14 15 +#define GPIO18_FUN_FEM_GPIO_3 16 +#define GPIO18_FUN_USB_SUS_EXT 17 +#define GPIO18_FUN_USB_SUS 18 +#define GPIO18_FUN_RMII_MDC 19 +#define GPIO18_FUN_QDEC0_A 20 +#define GPIO18_FUN_ROW_I_2 21 +#define GPIO18_FUN_COL_O_18 22 +#define GPIO18_FUN_CAM_PWRDN 23 +/* GPIO19 function definition */ +#define GPIO19_FUN_CLK_OUT_1 0 +#define GPIO19_FUN_BT_ACTIVE 1 +#define GPIO19_FUN_SF_CS 2 +#define GPIO19_FUN_I2S0_RCLK_O_I2S0_DI 3 +#define GPIO19_FUN_SPI_0_SCLK 4 +#define GPIO19_FUN_I2C0_SDA 6 +#define GPIO19_FUN_UART_SIG3_UART_SIG7 7 +#define GPIO19_FUN_PWM_CH4 8 +#define GPIO19_FUN_PIX_DAT6 9 +#define GPIO19_FUN_GPIP_CH_9 10 +#define GPIO19_FUN_REG_GPIO_19 11 +#define GPIO19_FUN_RF_TEST_14 12 +#define GPIO19_FUN_UNUSED13 13 +#define GPIO19_FUN_E21_TDO_E21_TDI 14 +#define GPIO19_FUN_M_CCI_CS_DEBUG_15 15 +#define GPIO19_FUN_FEM_GPIO_4 16 +#define GPIO19_FUN_USB_ENUM_EXT 17 +#define GPIO19_FUN_USB_ENUM 18 +#define GPIO19_FUN_RMII_MDIO 19 +#define GPIO19_FUN_QDEC0_B 20 +#define GPIO19_FUN_ROW_I_3 21 +#define GPIO19_FUN_COL_O_19 22 +#define GPIO19_FUN_CAM_REF_CLK 23 +/* GPIO20 function definition */ +#define GPIO20_FUN_CLK_OUT_0 0 +#define GPIO20_FUN_BT_PRI 1 +#define GPIO20_FUN_SF_IO_3 2 +#define GPIO20_FUN_I2S0_BCLK 3 +#define GPIO20_FUN_SPI_0_MISO_SPI_0_MOSI 4 +#define GPIO20_FUN_I2C0_SCL 6 +#define GPIO20_FUN_UART_SIG4_UART_SIG0 7 +#define GPIO20_FUN_PWM_CH0 8 +#define GPIO20_FUN_PIX_DAT7 9 +#define GPIO20_FUN_GPIP_CH_10 10 +#define GPIO20_FUN_REG_GPIO_20 11 +#define GPIO20_FUN_RF_TEST_15 12 +#define GPIO20_FUN_UNUSED13 13 +#define GPIO20_FUN_E21_TMS_E21_TCK 14 +#define GPIO20_FUN_M_CCI_DI_DEBUG_16 15 +#define GPIO20_FUN_FEM_GPIO_0 16 +#define GPIO20_FUN_USB_TX_DN_USB_RX_DN 17 +#define GPIO20_FUN_USB_OEB 18 +#define GPIO20_FUN_RMII_RXERR 19 +#define GPIO20_FUN_QDEC0_LED 20 +#define GPIO20_FUN_ROW_I_4 21 +#define GPIO20_FUN_COL_O_0 22 +#define GPIO20_FUN_CAM_RESET 23 +/* GPIO21 function definition */ +#define GPIO21_FUN_CLK_OUT_1 0 +#define GPIO21_FUN_BT_ABORT 1 +#define GPIO21_FUN_SF_CLK 2 +#define GPIO21_FUN_I2S0_FS 3 +#define GPIO21_FUN_SPI_0_MOSI_SPI_0_MISO 4 +#define GPIO21_FUN_I2C0_SDA 6 +#define GPIO21_FUN_UART_SIG5_UART_SIG1 7 +#define GPIO21_FUN_PWM_CH1 8 +#define GPIO21_FUN_UNUSED9 9 +#define GPIO21_FUN_GPIP_CH_11 10 +#define GPIO21_FUN_REG_GPIO_21 11 +#define GPIO21_FUN_RF_TEST_16 12 +#define GPIO21_FUN_UNUSED13 13 +#define GPIO21_FUN_E21_TDI_E21_TDO 14 +#define GPIO21_FUN_M_CCI_DO_DEBUG_17 15 +#define GPIO21_FUN_FEM_GPIO_1 16 +#define GPIO21_FUN_USB_TX_OE 17 +#define GPIO21_FUN_VOP 18 +#define GPIO21_FUN_RMII_TX_EN 19 +#define GPIO21_FUN_QDEC1_A 20 +#define GPIO21_FUN_ROW_I_5 21 +#define GPIO21_FUN_COL_O_1 22 +#define GPIO21_FUN_CAM_PWRDN 23 +/* GPIO22 function definition */ +#define GPIO22_FUN_CLK_OUT_0 0 +#define GPIO22_FUN_BT_ACTIVE 1 +#define GPIO22_FUN_SF_IO_2 2 +#define GPIO22_FUN_I2S0_DIO_I2S0_DO 3 +#define GPIO22_FUN_SPI_0_SS 4 +#define GPIO22_FUN_I2C0_SCL 6 +#define GPIO22_FUN_UART_SIG6_UART_SIG2 7 +#define GPIO22_FUN_PWM_CH2 8 +#define GPIO22_FUN_UNUSED9 9 +#define GPIO22_FUN_LEDDRV_0 10 +#define GPIO22_FUN_REG_GPIO_22 11 +#define GPIO22_FUN_RF_TEST_17 12 +#define GPIO22_FUN_UNUSED13 13 +#define GPIO22_FUN_E21_TCK_E21_TMS 14 +#define GPIO22_FUN_DEBUG_18 15 +#define GPIO22_FUN_FEM_GPIO_2 16 +#define GPIO22_FUN_USB_TX_DP_USB_RX_DP 17 +#define GPIO22_FUN_VOM 18 +#define GPIO22_FUN_RMII_RX_DV 19 +#define GPIO22_FUN_QDEC1_B 20 +#define GPIO22_FUN_ROW_I_6 21 +#define GPIO22_FUN_COL_O_2 22 +#define GPIO22_FUN_CAM_REF_CLK 23 +/* GPIO23 function definition */ +#define GPIO23_FUN_CLK_OUT_1 0 +#define GPIO23_FUN_BT_PRI 1 +#define GPIO23_FUN_SF2_IO_2_SF3_CS2 2 +#define GPIO23_FUN_I2S0_RCLK_O_I2S0_DI 3 +#define GPIO23_FUN_SPI_0_SCLK 4 +#define GPIO23_FUN_I2C0_SDA 6 +#define GPIO23_FUN_UART_SIG7_UART_SIG3 7 +#define GPIO23_FUN_PWM_CH3 8 +#define GPIO23_FUN_PIX_DAT4 9 +#define GPIO23_FUN_LEDDRV_1_FLASH_PULL_OUT_0 10 +#define GPIO23_FUN_REG_GPIO_23 11 +#define GPIO23_FUN_RF_TEST_18 12 +#define GPIO23_FUN_UNUSED13 13 +#define GPIO23_FUN_E21_TDO_E21_TDI 14 +#define GPIO23_FUN_DEBUG_19 15 +#define GPIO23_FUN_FEM_GPIO_3 16 +#define GPIO23_FUN_USB_SUS_EXT 17 +#define GPIO23_FUN_BD 18 +#define GPIO23_FUN_UNUSED19 19 +#define GPIO23_FUN_QDEC1_LED 20 +#define GPIO23_FUN_ROW_I_7 21 +#define GPIO23_FUN_COL_O_3 22 +#define GPIO23_FUN_CAM_RESET 23 +/* GPIO24 function definition */ +#define GPIO24_FUN_CLK_OUT_0 0 +#define GPIO24_FUN_BT_ABORT 1 +#define GPIO24_FUN_SF2_IO_1 2 +#define GPIO24_FUN_I2S0_BCLK 3 +#define GPIO24_FUN_SPI_0_MISO_SPI_0_MOSI 4 +#define GPIO24_FUN_I2C0_SCL 6 +#define GPIO24_FUN_UART_SIG0_UART_SIG4 7 +#define GPIO24_FUN_PWM_CH4 8 +#define GPIO24_FUN_PIX_DAT5 9 +#define GPIO24_FUN_FLASH_PULL_OUT_1 10 +#define GPIO24_FUN_REG_GPIO_24 11 +#define GPIO24_FUN_RF_TEST_19 12 +#define GPIO24_FUN_UNUSED13 13 +#define GPIO24_FUN_E21_TMS_E21_TCK 14 +#define GPIO24_FUN_DEBUG_20 15 +#define GPIO24_FUN_FEM_GPIO_4 16 +#define GPIO24_FUN_USB_ENUM_EXT 17 +#define GPIO24_FUN_VIP 18 +#define GPIO24_FUN_RMII_MDC 19 +#define GPIO24_FUN_QDEC2_A 20 +#define GPIO24_FUN_ROW_I_0 21 +#define GPIO24_FUN_COL_O_4 22 +#define GPIO24_FUN_CAM_PWRDN 23 +/* GPIO25 function definition */ +#define GPIO25_FUN_CLK_OUT_1 0 +#define GPIO25_FUN_BT_ACTIVE 1 +#define GPIO25_FUN_SF2_CS 2 +#define GPIO25_FUN_I2S0_FS 3 +#define GPIO25_FUN_SPI_0_MOSI_SPI_0_MISO 4 +#define GPIO25_FUN_I2C0_SDA 6 +#define GPIO25_FUN_UART_SIG1_UART_SIG5 7 +#define GPIO25_FUN_PWM_CH0 8 +#define GPIO25_FUN_PIX_DAT6 9 +#define GPIO25_FUN_FLASH_PULL_OUT_2 10 +#define GPIO25_FUN_REG_GPIO_25 11 +#define GPIO25_FUN_RF_TEST_20 12 +#define GPIO25_FUN_UNUSED13 13 +#define GPIO25_FUN_E21_TDI_E21_TDO 14 +#define GPIO25_FUN_DEBUG_21 15 +#define GPIO25_FUN_FEM_GPIO_0 16 +#define GPIO25_FUN_USB_TX_DN_USB_RX_DN 17 +#define GPIO25_FUN_VIM 18 +#define GPIO25_FUN_RMII_MDIO 19 +#define GPIO25_FUN_QDEC2_B 20 +#define GPIO25_FUN_ROW_I_1 21 +#define GPIO25_FUN_COL_O_5 22 +#define GPIO25_FUN_CAM_REF_CLK 23 +/* GPIO26 function definition */ +#define GPIO26_FUN_CLK_OUT_0 0 +#define GPIO26_FUN_BT_PRI 1 +#define GPIO26_FUN_SF2_IO_3 2 +#define GPIO26_FUN_I2S0_DIO_I2S0_DO 3 +#define GPIO26_FUN_SPI_0_SS 4 +#define GPIO26_FUN_I2C0_SCL 6 +#define GPIO26_FUN_UART_SIG2_UART_SIG6 7 +#define GPIO26_FUN_PWM_CH1 8 +#define GPIO26_FUN_PIX_DAT7 9 +#define GPIO26_FUN_FLASH_PULL_OUT_3 10 +#define GPIO26_FUN_REG_GPIO_26 11 +#define GPIO26_FUN_RF_TEST_21 12 +#define GPIO26_FUN_UNUSED13 13 +#define GPIO26_FUN_E21_TCK_E21_TMS 14 +#define GPIO26_FUN_DEBUG_22 15 +#define GPIO26_FUN_FEM_GPIO_1 16 +#define GPIO26_FUN_USB_TX_OE 17 +#define GPIO26_FUN_RCV 18 +#define GPIO26_FUN_RMII_RXERR 19 +#define GPIO26_FUN_QDEC2_LED 20 +#define GPIO26_FUN_ROW_I_2 21 +#define GPIO26_FUN_COL_O_6 22 +#define GPIO26_FUN_CAM_RESET 23 +/* GPIO27 function definition */ +#define GPIO27_FUN_CLK_OUT_1 0 +#define GPIO27_FUN_BT_ABORT 1 +#define GPIO27_FUN_SF2_CLK 2 +#define GPIO27_FUN_I2S0_RCLK_O_I2S0_DI 3 +#define GPIO27_FUN_SPI_0_SCLK 4 +#define GPIO27_FUN_I2C0_SDA 6 +#define GPIO27_FUN_UART_SIG3_UART_SIG7 7 +#define GPIO27_FUN_PWM_CH2 8 +#define GPIO27_FUN_UNUSED9 9 +#define GPIO27_FUN_FLASH_PULL_OUT_4 10 +#define GPIO27_FUN_REG_GPIO_27 11 +#define GPIO27_FUN_RF_TEST_22 12 +#define GPIO27_FUN_UNUSED13 13 +#define GPIO27_FUN_E21_TDO_E21_TDI 14 +#define GPIO27_FUN_DEBUG_23 15 +#define GPIO27_FUN_FEM_GPIO_2 16 +#define GPIO27_FUN_USB_TX_DP_USB_RX_DP 17 +#define GPIO27_FUN_USB_SUS 18 +#define GPIO27_FUN_RMII_TX_EN 19 +#define GPIO27_FUN_QDEC0_A 20 +#define GPIO27_FUN_ROW_I_3 21 +#define GPIO27_FUN_COL_O_7 22 +#define GPIO27_FUN_CAM_PWRDN 23 +/* GPIO28 function definition */ +#define GPIO28_FUN_CLK_OUT_0 0 +#define GPIO28_FUN_BT_ACTIVE 1 +#define GPIO28_FUN_SF2_IO_0 2 +#define GPIO28_FUN_I2S0_BCLK 3 +#define GPIO28_FUN_SPI_0_MISO_SPI_0_MOSI 4 +#define GPIO28_FUN_I2C0_SCL 6 +#define GPIO28_FUN_UART_SIG4_UART_SIG0 7 +#define GPIO28_FUN_PWM_CH3 8 +#define GPIO28_FUN_PIX_DAT4 9 +#define GPIO28_FUN_FLASH_PULL_OUT_5 10 +#define GPIO28_FUN_REG_GPIO_28 11 +#define GPIO28_FUN_RF_TEST_23 12 +#define GPIO28_FUN_UNUSED13 13 +#define GPIO28_FUN_E21_TMS_E21_TCK 14 +#define GPIO28_FUN_DEBUG_24 15 +#define GPIO28_FUN_FEM_GPIO_3 16 +#define GPIO28_FUN_USB_SUS_EXT 17 +#define GPIO28_FUN_USB_ENUM 18 +#define GPIO28_FUN_RMII_RX_DV 19 +#define GPIO28_FUN_QDEC0_B 20 +#define GPIO28_FUN_ROW_I_4 21 +#define GPIO28_FUN_COL_O_8 22 +#define GPIO28_FUN_CAM_REF_CLK 23 +/* GPIO29 function definition */ +#define GPIO29_FUN_CLK_OUT_1 0 +#define GPIO29_FUN_BT_PRI 1 +#define GPIO29_FUN_UNUSED2 2 +#define GPIO29_FUN_I2S0_FS 3 +#define GPIO29_FUN_SPI_0_MOSI_SPI_0_MISO 4 +#define GPIO29_FUN_I2C0_SDA 6 +#define GPIO29_FUN_UART_SIG5_UART_SIG1 7 +#define GPIO29_FUN_PWM_CH4 8 +#define GPIO29_FUN_PIX_DAT5 9 +#define GPIO29_FUN_UNUSED10 10 +#define GPIO29_FUN_REG_GPIO_29 11 +#define GPIO29_FUN_RF_TEST_24 12 +#define GPIO29_FUN_UNUSED13 13 +#define GPIO29_FUN_E21_TDI_E21_TDO 14 +#define GPIO29_FUN_DEBUG_25 15 +#define GPIO29_FUN_FEM_GPIO_4 16 +#define GPIO29_FUN_USB_ENUM_EXT 17 +#define GPIO29_FUN_USB_OEB 18 +#define GPIO29_FUN_UNUSED19 19 +#define GPIO29_FUN_QDEC0_LED 20 +#define GPIO29_FUN_ROW_I_5 21 +#define GPIO29_FUN_COL_O_9 22 +#define GPIO29_FUN_CAM_RESET 23 +/* GPIO30 function definition */ +#define GPIO30_FUN_CLK_OUT_0 0 +#define GPIO30_FUN_BT_ABORT 1 +#define GPIO30_FUN_UNUSED2 2 +#define GPIO30_FUN_I2S0_DIO_I2S0_DO 3 +#define GPIO30_FUN_SPI_0_SS 4 +#define GPIO30_FUN_I2C0_SCL 6 +#define GPIO30_FUN_UART_SIG6_UART_SIG2 7 +#define GPIO30_FUN_PWM_CH0 8 +#define GPIO30_FUN_PIX_DAT6 9 +#define GPIO30_FUN_UNUSED10 10 +#define GPIO30_FUN_REG_GPIO_30 11 +#define GPIO30_FUN_RF_TEST_25 12 +#define GPIO30_FUN_UNUSED13 13 +#define GPIO30_FUN_E21_TCK_E21_TMS 14 +#define GPIO30_FUN_DEBUG_26 15 +#define GPIO30_FUN_FEM_GPIO_0 16 +#define GPIO30_FUN_USB_TX_DN_USB_RX_DN 17 +#define GPIO30_FUN_VOP 18 +#define GPIO30_FUN_UNUSED19 19 +#define GPIO30_FUN_QDEC1_A 20 +#define GPIO30_FUN_ROW_I_6 21 +#define GPIO30_FUN_COL_O_10 22 +#define GPIO30_FUN_CAM_PWRDN 23 +/* GPIO31 function definition */ +#define GPIO31_FUN_CLK_OUT_1 0 +#define GPIO31_FUN_BT_ACTIVE 1 +#define GPIO31_FUN_UNUSED2 2 +#define GPIO31_FUN_I2S0_RCLK_O_I2S0_DI 3 +#define GPIO31_FUN_SPI_0_SCLK 4 +#define GPIO31_FUN_I2C0_SDA 6 +#define GPIO31_FUN_UART_SIG7_UART_SIG3 7 +#define GPIO31_FUN_PWM_CH1 8 +#define GPIO31_FUN_PIX_DAT7 9 +#define GPIO31_FUN_UNUSED10 10 +#define GPIO31_FUN_REG_GPIO_31 11 +#define GPIO31_FUN_RF_TEST_26 12 +#define GPIO31_FUN_UNUSED13 13 +#define GPIO31_FUN_E21_TDO_E21_TDI 14 +#define GPIO31_FUN_DEBUG_27 15 +#define GPIO31_FUN_FEM_GPIO_1 16 +#define GPIO31_FUN_USB_TX_OE 17 +#define GPIO31_FUN_VOM 18 +#define GPIO31_FUN_UNUSED19 19 +#define GPIO31_FUN_QDEC1_B 20 +#define GPIO31_FUN_ROW_I_7 21 +#define GPIO31_FUN_COL_O_11 22 +#define GPIO31_FUN_CAM_REF_CLK 23 + +#endif /*__BL702_GPIO_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_hbn.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_hbn.h new file mode 100644 index 0000000000000000000000000000000000000000..60811f7fb2e4b5fb08468349e7dac508095f194e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_hbn.h @@ -0,0 +1,563 @@ +/** + ****************************************************************************** + * @file bl702_hbn.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_HBN_H__ +#define __BL702_HBN_H__ + +#include "hbn_reg.h" +#include "bl702_aon.h" +#include "bl702_sflash.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Public_Types + * @{ + */ + +/** + * @brief HBN PIR interrupt configuration type definition + */ +typedef struct +{ + BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */ + BL_Fun_Type highIntEn; /*!< High will trigger interrupt */ +} HBN_PIR_INT_CFG_Type; + +/** + * @brief HBN PIR low pass filter type definition + */ +typedef enum { + HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */ + HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */ +} HBN_PIR_LPF_Type; + +/** + * @brief HBN PIR high pass filter type definition + */ +typedef enum { + HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */ + HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */ + HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */ +} HBN_PIR_HPF_Type; + +/** + * @brief HBN BOR threshold type definition + */ +typedef enum { + HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */ + HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */ +} HBN_BOR_THRES_Type; + +/** + * @brief HBN BOR mode type definition + */ +typedef enum { + HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ + HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ +} HBN_BOR_MODE_Type; + +/** + * @brief HBN 32K clock type definition + */ +typedef enum { + HBN_32K_RC = 0, /*!< HBN use rc 32k */ + HBN_32K_XTAL, /*!< HBN use xtal 32k */ + HBN_32K_DIG = 3, /*!< HBN use dig 32k */ +} HBN_32K_CLK_Type; + +/** + * @brief HBN xclk clock type definition + */ +typedef enum { + HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */ + HBN_XCLK_CLK_XTAL, /*!< use XTAL as xclk clock */ +} HBN_XCLK_CLK_Type; + +/** + * @brief HBN root clock type definition + */ +typedef enum { + HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */ + HBN_ROOT_CLK_XTAL, /*!< use XTAL as root clock */ + HBN_ROOT_CLK_DLL, /*!< use DLL as root clock */ +} HBN_ROOT_CLK_Type; + +/** + * @brief HBN UART clock type definition + */ +typedef enum { + HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */ + HBN_UART_CLK_96M, /*!< Select 96M as UART clock */ +} HBN_UART_CLK_Type; + +/** + * @brief HBN RTC interrupt delay type definition + */ +typedef enum { + HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */ + HBN_RTC_INT_DELAY_0T = 1, /*!< HBN RTC interrupt delay 0T */ +} HBN_RTC_INT_Delay_Type; + +/** + * @brief HBN interrupt type definition + */ +typedef enum { + HBN_INT_GPIO9 = 0, /*!< HBN interrupt type: GPIO9 */ + HBN_INT_GPIO10 = 1, /*!< HBN interrupt type: GPIO10 */ + HBN_INT_GPIO11 = 2, /*!< HBN interrupt type: GPIO11 */ + HBN_INT_GPIO12 = 3, /*!< HBN interrupt type: GPIO12 */ + HBN_INT_GPIO13 = 4, /*!< HBN interrupt type: GPIO13 */ + HBN_INT_RTC = 16, /*!< HBN interrupt type: RTC */ + HBN_INT_PIR, /*!< HBN interrupt type: PIR */ + HBN_INT_BOR, /*!< HBN interrupt type: BOR */ + HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */ + HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */ +} HBN_INT_Type; + +/** + * @brief HBN acomp interrupt type definition + */ +typedef enum { + HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */ + HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */ +} HBN_ACOMP_INT_EDGE_Type; + +/** + * @brief HBN reset event type definition + */ +typedef enum { + HBN_RST_EVENT_POR_OUT, /*!< por_out event */ + HBN_RST_EVENT_EXT_RST_N, /*!< ext_rst_n event */ + HBN_RST_EVENT_SW_RST, /*!< sw_rst event */ + HBN_RST_EVENT_PWR_RST_N, /*!< pwr_rst_n event */ + HBN_RST_EVENT_BOR_OUT, /*!< bor_out_ event */ +} HBN_RST_EVENT_Type; + +/** + * @brief HBN GPIO interrupt trigger type definition + */ +typedef enum { + HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: sync falling edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: sync rising edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: sync low level trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: sync high level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: async rising edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: async low level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: async high level trigger */ +} HBN_GPIO_INT_Trigger_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT0_INT_GPIO9 = 0, /*!< HBN out 0 interrupt type: GPIO9 */ + HBN_OUT0_INT_GPIO10 = 1, /*!< HBN out 0 interrupt type: GPIO10 */ + HBN_OUT0_INT_GPIO11 = 2, /*!< HBN out 0 interrupt type: GPIO11 */ + HBN_OUT0_INT_GPIO12 = 3, /*!< HBN out 0 interrupt type: GPIO12 */ + HBN_OUT0_INT_GPIO13 = 4, /*!< HBN out 0 interrupt type: GPIO13 */ + HBN_OUT0_INT_RTC, /*!< HBN out 0 interrupt type: RTC */ + HBN_OUT0_MAX, /*!< HBN out 0 max num */ +} HBN_OUT0_INT_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT1_INT_PIR, /*!< HBN out 1 interrupt type: PIR */ + HBN_OUT1_INT_BOR, /*!< HBN out 1 interrupt type: BOR */ + HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */ + HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */ + HBN_OUT1_MAX, /*!< HBN out 1 max num */ +} HBN_OUT1_INT_Type; + +/** + * @brief HBN LDO level type definition + */ +typedef enum { + HBN_LDO_LEVEL_0P60V = 0, /*!< HBN LDO voltage 0.60V */ + HBN_LDO_LEVEL_0P65V = 1, /*!< HBN LDO voltage 0.65V */ + HBN_LDO_LEVEL_0P70V = 2, /*!< HBN LDO voltage 0.70V */ + HBN_LDO_LEVEL_0P75V = 3, /*!< HBN LDO voltage 0.75V */ + HBN_LDO_LEVEL_0P80V = 4, /*!< HBN LDO voltage 0.80V */ + HBN_LDO_LEVEL_0P85V = 5, /*!< HBN LDO voltage 0.85V */ + HBN_LDO_LEVEL_0P90V = 6, /*!< HBN LDO voltage 0.90V */ + HBN_LDO_LEVEL_0P95V = 7, /*!< HBN LDO voltage 0.95V */ + HBN_LDO_LEVEL_1P00V = 8, /*!< HBN LDO voltage 1.00V */ + HBN_LDO_LEVEL_1P05V = 9, /*!< HBN LDO voltage 1.05V */ + HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */ + HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */ + HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */ + HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */ + HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */ + HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */ +} HBN_LDO_LEVEL_Type; + +/** + * @brief HBN LDO11RT drive strength type definition + */ +typedef enum { + HBN_LDO11RT_DRIVE_STRENGTH_5_50UA = 0, /*!< HBN LDO11RT drive strength 0: 5uA to 50uA */ + HBN_LDO11RT_DRIVE_STRENGTH_10_100UA = 1, /*!< HBN LDO11RT drive strength 1: 10uA to 100uA */ + HBN_LDO11RT_DRIVE_STRENGTH_15_150UA = 2, /*!< HBN LDO11RT drive strength 2: 15uA to 150uA */ + HBN_LDO11RT_DRIVE_STRENGTH_25_250UA = 3, /*!< HBN LDO11RT drive strength 3: 25uA to 250uA */ +} HBN_LDO11RT_DRIVE_STRENGTH_Type; + +/** + * @brief HBN level type definition + */ +typedef enum { + HBN_LEVEL_0, /*!< HBN pd_core */ + HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */ + HBN_LEVEL_2, /*!< HBN pd_aon_hbncore + pd_core */ + HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ +} HBN_LEVEL_Type; + +/** + * @brief HBN BOR configuration type definition + */ +typedef struct +{ + uint8_t enableBor; /*!< Enable BOR or not */ + uint8_t enableBorInt; /*!< Enable BOR interrupt or not */ + uint8_t borThreshold; /*!< BOR threshold */ + uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */ +} HBN_BOR_CFG_Type; + +/** + * @brief HBN APP configuration type definition + */ +typedef struct +{ + uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */ + uint32_t sleepTime; /*!< HBN sleep time */ + uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ + HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ + SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + uint8_t flashPinCfg; /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */ + HBN_LEVEL_Type hbnLevel; /*!< HBN level */ + HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ +} HBN_APP_CFG_Type; + +/*@} end of group HBN_Public_Types */ + +/** @defgroup HBN_Public_Constants + * @{ + */ + +/** @defgroup HBN_PIR_LPF_TYPE + * @{ + */ +#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \ + ((type) == HBN_PIR_LPF_DIV2)) + +/** @defgroup HBN_PIR_HPF_TYPE + * @{ + */ +#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \ + ((type) == HBN_PIR_HPF_METHOD1) || \ + ((type) == HBN_PIR_HPF_METHOD2)) + +/** @defgroup HBN_BOR_THRES_TYPE + * @{ + */ +#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \ + ((type) == HBN_BOR_THRES_2P4V)) + +/** @defgroup HBN_BOR_MODE_TYPE + * @{ + */ +#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \ + ((type) == HBN_BOR_MODE_POR_RELEVANT)) + +/** @defgroup HBN_32K_CLK_TYPE + * @{ + */ +#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \ + ((type) == HBN_32K_XTAL) || \ + ((type) == HBN_32K_DIG)) + +/** @defgroup HBN_XCLK_CLK_TYPE + * @{ + */ +#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \ + ((type) == HBN_XCLK_CLK_XTAL)) + +/** @defgroup HBN_ROOT_CLK_TYPE + * @{ + */ +#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \ + ((type) == HBN_ROOT_CLK_XTAL) || \ + ((type) == HBN_ROOT_CLK_DLL)) + +/** @defgroup HBN_UART_CLK_TYPE + * @{ + */ +#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \ + ((type) == HBN_UART_CLK_96M)) + +/** @defgroup HBN_RTC_INT_DELAY_TYPE + * @{ + */ +#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \ + ((type) == HBN_RTC_INT_DELAY_0T)) + +/** @defgroup HBN_INT_TYPE + * @{ + */ +#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO9) || \ + ((type) == HBN_INT_GPIO10) || \ + ((type) == HBN_INT_GPIO11) || \ + ((type) == HBN_INT_GPIO12) || \ + ((type) == HBN_INT_GPIO13) || \ + ((type) == HBN_INT_RTC) || \ + ((type) == HBN_INT_PIR) || \ + ((type) == HBN_INT_BOR) || \ + ((type) == HBN_INT_ACOMP0) || \ + ((type) == HBN_INT_ACOMP1)) + +/** @defgroup HBN_ACOMP_INT_EDGE_TYPE + * @{ + */ +#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \ + ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE)) + +/** @defgroup HBN_RST_EVENT_TYPE + * @{ + */ +#define IS_HBN_RST_EVENT_TYPE(type) (((type) == HBN_RST_EVENT_POR_OUT) || \ + ((type) == HBN_RST_EVENT_EXT_RST_N) || \ + ((type) == HBN_RST_EVENT_SW_RST) || \ + ((type) == HBN_RST_EVENT_PWR_RST_N) || \ + ((type) == HBN_RST_EVENT_BOR_OUT)) + +/** @defgroup HBN_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + +/** @defgroup HBN_OUT0_INT_TYPE + * @{ + */ +#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO9) || \ + ((type) == HBN_OUT0_INT_GPIO10) || \ + ((type) == HBN_OUT0_INT_GPIO11) || \ + ((type) == HBN_OUT0_INT_GPIO12) || \ + ((type) == HBN_OUT0_INT_GPIO13) || \ + ((type) == HBN_OUT0_INT_RTC) || \ + ((type) == HBN_OUT0_MAX)) + +/** @defgroup HBN_OUT1_INT_TYPE + * @{ + */ +#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \ + ((type) == HBN_OUT1_INT_BOR) || \ + ((type) == HBN_OUT1_INT_ACOMP0) || \ + ((type) == HBN_OUT1_INT_ACOMP1) || \ + ((type) == HBN_OUT1_MAX)) + +/** @defgroup HBN_LDO_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \ + ((type) == HBN_LDO_LEVEL_0P65V) || \ + ((type) == HBN_LDO_LEVEL_0P70V) || \ + ((type) == HBN_LDO_LEVEL_0P75V) || \ + ((type) == HBN_LDO_LEVEL_0P80V) || \ + ((type) == HBN_LDO_LEVEL_0P85V) || \ + ((type) == HBN_LDO_LEVEL_0P90V) || \ + ((type) == HBN_LDO_LEVEL_0P95V) || \ + ((type) == HBN_LDO_LEVEL_1P00V) || \ + ((type) == HBN_LDO_LEVEL_1P05V) || \ + ((type) == HBN_LDO_LEVEL_1P10V) || \ + ((type) == HBN_LDO_LEVEL_1P15V) || \ + ((type) == HBN_LDO_LEVEL_1P20V) || \ + ((type) == HBN_LDO_LEVEL_1P25V) || \ + ((type) == HBN_LDO_LEVEL_1P30V) || \ + ((type) == HBN_LDO_LEVEL_1P35V)) + +/** @defgroup HBN_LDO11RT_DRIVE_STRENGTH_TYPE + * @{ + */ +#define IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(type) (((type) == HBN_LDO11RT_DRIVE_STRENGTH_5_50UA) || \ + ((type) == HBN_LDO11RT_DRIVE_STRENGTH_10_100UA) || \ + ((type) == HBN_LDO11RT_DRIVE_STRENGTH_15_150UA) || \ + ((type) == HBN_LDO11RT_DRIVE_STRENGTH_25_250UA)) + +/** @defgroup HBN_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \ + ((type) == HBN_LEVEL_1) || \ + ((type) == HBN_LEVEL_2) || \ + ((type) == HBN_LEVEL_3)) + +/*@} end of group HBN_Public_Constants */ + +/** @defgroup HBN_Public_Macros + * @{ + */ +#define HBN_RAM_SIZE (4 * 1024) +#define HBN_RTC_COMP_BIT0_39 0x01 +#define HBN_RTC_COMP_BIT0_23 0x02 +#define HBN_RTC_COMP_BIT13_39 0x04 +#define HBN_STATUS_ENTER_FLAG 0x4e424845 +#define HBN_STATUS_WAKEUP_FLAG 0x4e424857 +#define HBN_WAKEUP_GPIO_NONE 0x00 +#define HBN_WAKEUP_GPIO_10 0x02 +#define HBN_WAKEUP_GPIO_11 0x04 +#define HBN_WAKEUP_GPIO_12 0x08 +#define HBN_WAKEUP_GPIO_13 0x10 +#define HBN_WAKEUP_GPIO_ALL 0x1E + +/*@} end of group HBN_Public_Macros */ + +/** @defgroup HBN_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void); +void HBN_OUT1_IRQHandler(void); +#endif +/*----------*/ +void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg); +void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg); +void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); +BL_Err_Type HBN_Reset(void); +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv); +BL_Err_Type HBN_Disable(void); +/*----------*/ +BL_Err_Type HBN_PIR_Enable(void); +BL_Err_Type HBN_PIR_Disable(void); +BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg); +BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf); +BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf); +BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold); +uint16_t HBN_Get_PIR_Threshold(void); +BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval); +uint16_t HBN_Get_PIR_Interval(void); +/*----------*/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void); +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode); +/*----------*/ +BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength); +/*----------*/ +BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType); +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel); +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk); +BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk); +/*----------*/ +BL_Err_Type HBN_Set_HRAM_slp(void); +BL_Err_Type HBN_Set_HRAM_Ret(void); +/*----------*/ +uint32_t HBN_Get_Status_Flag(void); +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag); +uint32_t HBN_Get_Wakeup_Addr(void); +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr); +/*----------*/ +BL_Err_Type HBN_Clear_RTC_Counter(void); +BL_Err_Type HBN_Enable_RTC_Counter(void); +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode); +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh); +BL_Err_Type HBN_Clear_RTC_INT(void); +/*----------*/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType); +BL_Err_Type HBN_GPIO_INT_Disable(void); +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType); +uint8_t HBN_Get_Pin_Wakeup_Mode(void); +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType); +BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable); +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); +BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal); +/*----------*/ +BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +/*----------*/ +BL_Err_Type HBN_Enable_BOR_IRQ(void); +BL_Err_Type HBN_Disable_BOR_IRQ(void); +/*----------*/ +BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event); +BL_Err_Type HBN_Clear_Reset_Event(void); +/*----------*/ +BL_Err_Type HBN_Out0_IRQHandler_Install(void); +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type HBN_Out1_IRQHandler_Install(void); +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, + uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask); +/*----------*/ +BL_Err_Type HBN_Power_On_Xtal_32K(void); +BL_Err_Type HBN_Power_Off_Xtal_32K(void); +BL_Err_Type HBN_Power_On_RC32K(void); +BL_Err_Type HBN_Power_Off_RC32K(void); +BL_Err_Type HBN_Trim_RC32K(void); +BL_Err_Type HBN_Set_Pad_23_28_Pullnone(void); +BL_Err_Type HBN_Set_Pad_23_28_Pullup(void); +BL_Err_Type HBN_Set_Pad_23_28_Pulldown(void); +BL_Err_Type HBN_Set_Pad_23_28_ActiveIE(void); +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg); +/*----------*/ +void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); +/*----------*/; + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_HBN_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..aae370b6a6abdc0a516d7ab76c4a152b60ce8022 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c.h @@ -0,0 +1,199 @@ +/** + ****************************************************************************** + * @file bl702_i2c.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_I2C_H__ +#define __BL702_I2C_H__ + +#include "i2c_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types + * @{ + */ + +/** + * @brief I2C No. type definition + */ +typedef enum { + I2C0_ID = 0, /*!< I2C0 define */ + I2C_ID_MAX, /*!< I2C max define */ +} I2C_ID_Type; + +/** + * @brief I2C read/write type definition + */ +typedef enum { + I2C_WRITE = 0, /*!< I2C write direction */ + I2C_READ, /*!< I2C read direction */ +} I2C_Direction_Type; + +/** + * @brief I2C interrupt type definition + */ +typedef enum { + I2C_TRANS_END_INT, /*!< I2C transfer end interrupt */ + I2C_TX_FIFO_READY_INT, /*!< I2C TX fifo ready interrupt */ + I2C_RX_FIFO_READY_INT, /*!< I2C RX fifo ready interrupt */ + I2C_NACK_RECV_INT, /*!< I2C nack received interrupt */ + I2C_ARB_LOST_INT, /*!< I2C arbitration lost interrupt */ + I2C_FIFO_ERR_INT, /*!< I2C TX/RX FIFO error interrupt */ + I2C_INT_ALL, /*!< I2C interrupt all type */ +} I2C_INT_Type; + +/** + * @brief I2S start condition phase structure type definition + */ +typedef struct +{ + uint8_t len0; /*!< Length of START condition phase 0 */ + uint8_t len1; /*!< Length of START condition phase 1 */ + uint8_t len2; /*!< Length of START condition phase 2 */ + uint8_t len3; /*!< Length of START condition phase 3 */ +} I2C_Start_Condition_Phase_Type; + +/** + * @brief I2S stop condition phase structure type definition + */ +typedef struct +{ + uint8_t len0; /*!< Length of STOP condition phase 0 */ + uint8_t len1; /*!< Length of STOP condition phase 1 */ + uint8_t len2; /*!< Length of STOP condition phase 2 */ + uint8_t len3; /*!< Length of STOP condition phase 3 */ +} I2C_Stop_Condition_Phase_Type; + +/** + * @brief I2S data phase structure type definition + */ +typedef struct +{ + uint8_t len0; /*!< Length of DATA phase 0 */ + uint8_t len1; /*!< Length of DATA phase 1 */ + uint8_t len2; /*!< Length of DATA phase 2 */ + uint8_t len3; /*!< Length of DATA phase 3 */ +} I2C_Data_Phase_Type; + +/** + * @brief I2S transfer structure type definition + */ +typedef struct +{ + uint8_t slaveAddr; /*!< I2C slave address */ + BL_Fun_Type stopEveryByte; /*!< I2C all data byte with stop bit */ + uint8_t subAddrSize; /*!< Specifies the size of I2C sub address section */ + uint32_t subAddr; /*!< I2C sub address */ + uint16_t dataSize; /*!< Specifies the size of I2C data section */ + uint8_t *data; /*!< Specifies the pointer of I2C R/W data */ +} I2C_Transfer_Cfg; + +/*@} end of group I2C_Public_Types */ + +/** @defgroup I2C_Public_Constants + * @{ + */ + +/** @defgroup I2C_ID_TYPE + * @{ + */ +#define IS_I2C_ID_TYPE(type) (((type) == I2C0_ID) || \ + ((type) == I2C_ID_MAX)) + +/** @defgroup I2C_DIRECTION_TYPE + * @{ + */ +#define IS_I2C_DIRECTION_TYPE(type) (((type) == I2C_WRITE) || \ + ((type) == I2C_READ)) + +/** @defgroup I2C_INT_TYPE + * @{ + */ +#define IS_I2C_INT_TYPE(type) (((type) == I2C_TRANS_END_INT) || \ + ((type) == I2C_TX_FIFO_READY_INT) || \ + ((type) == I2C_RX_FIFO_READY_INT) || \ + ((type) == I2C_NACK_RECV_INT) || \ + ((type) == I2C_ARB_LOST_INT) || \ + ((type) == I2C_FIFO_ERR_INT) || \ + ((type) == I2C_INT_ALL)) + +/*@} end of group I2C_Public_Constants */ + +/** @defgroup I2C_Public_Macros + * @{ + */ + +/*@} end of group I2C_Public_Macros */ + +/** @defgroup I2C_Public_Functions + * @{ + */ + +/** + * @brief I2C Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_IRQHandler(void); +#endif +void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data); +uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo); +void I2C_Enable(I2C_ID_Type i2cNo); +void I2C_Disable(I2C_ID_Type i2cNo); +BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt); +BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo); +void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase); +void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk); +void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable); +void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg); +BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo); +BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo); +BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); +BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); +void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask); +void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun); + +/*@} end of group I2C_Public_Functions */ + +/*@} end of group I2C */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_I2C_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c_gpio_sim.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c_gpio_sim.h new file mode 100644 index 0000000000000000000000000000000000000000..5460576525e4ce1a4f89ce32c93b3b72f2c15bca --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c_gpio_sim.h @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file bl702_i2c_gpio_sim.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_I2C_GPIO_SIM_H__ +#define __BL702_I2C_GPIO_SIM_H__ + +#include "bl702_glb.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2C_GPIO_SIM + * @{ + */ + +/** @defgroup I2C_GPIO_SIM_Public_Types + * @{ + */ + +/*@} end of group I2C_GPIO_SIM_Public_Types */ + +/** @defgroup I2C_GPIO_SIM_Public_Functions + * @{ + */ + +/** + * @brief I2C Functions + */ +void I2C_GPIO_Sim_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin); +int I2C_Start(void); +void I2C_Stop(void); +uint8_t I2C_GetAck(void); +void I2C_SendByte(uint8_t Data); +uint8_t I2C_ReadByte(uint8_t ack); +int SCCB_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin); +int SCCB_Write(uint8_t slave_addr, uint8_t *data, uint32_t wrsize); +int SCCB_Read(uint8_t slave_addr, uint8_t *data, uint32_t rdsize); + +/*@} end of group I2C_GPIO_SIM_Public_Functions */ + +/*@} end of group I2C_GPIO_SIM */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_I2C_GPIO_SIM_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2s.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2s.h new file mode 100644 index 0000000000000000000000000000000000000000..9fb5d00a2e007cdf0cbdc2822fba9416be4eb79d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2s.h @@ -0,0 +1,295 @@ +/** + ****************************************************************************** + * @file bl702_i2s.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_I2S_H__ +#define __BL702_I2S_H__ + +#include "i2s_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/** @defgroup I2S_Public_Types + * @{ + */ + +/** + * @brief I2S mode type definition + */ +typedef enum { + I2S_MODE_I2S_LEFT, /*!< Left-Justified Mode */ + I2S_MODE_I2S_RIGHT, /*!< Right-Justified Mode */ + I2S_MODE_I2S_DSP, /*!< DSP Mode */ +} I2S_Mode_Type; + +/** + * @brief I2S role type definition + */ +typedef enum { + I2S_ROLE_MASTER = 0, /*!< I2S as master */ + I2S_ROLE_SLAVE = 1, /*!< I2S as slave */ +} I2S_Role_Type; + +/** + * @brief I2S data size type definition + */ +typedef enum { + I2S_SIZE_DATA_8 = 0, /*!< I2S data size 8 bits */ + I2S_SIZE_DATA_16, /*!< I2S data size 16 bits */ + I2S_SIZE_DATA_24, /*!< I2S data size 24 bits */ + I2S_SIZE_DATA_32, /*!< I2S data size 32 bits */ +} I2S_Data_Size_Type; + +/** + * @brief I2S frame size type definition + */ +typedef enum { + I2S_SIZE_FRAME_8 = 0, /*!< I2S frame size 8 bits */ + I2S_SIZE_FRAME_16, /*!< I2S frame size 16 bits */ + I2S_SIZE_FRAME_24, /*!< I2S frame size 24 bits */ + I2S_SIZE_FRAME_32, /*!< I2S frame size 32 bits */ +} I2S_Frame_Size_Type; + +/** + * @brief I2S endian data type definition + */ +typedef enum { + I2S_DATA_ENDIAN_MSB = 0, /*!< I2S use MSB first */ + I2S_DATA_ENDIAN_LSB, /*!< I2S use LSB first */ +} I2S_Endian_Type; + +/** + * @brief I2S frame select mode type definition + */ +typedef enum { + I2S_FS_MODE_EVEN = 0, /*!< I2S frame is even */ + I2S_FS_MODE_1T, /*!< I2S frame is only 1T high */ +} I2S_Fs_Mode_Type; + +/** + * @brief I2S rx mono mode channel select type definition + */ +typedef enum { + I2S_RX_MONO_MODE_LEFT_CHANNEL, /*!< I2S rx mono mode left channel */ + I2S_RX_MONO_MODE_RIGHT_CHANNEL, /*!< I2S rx mono mode right channel */ +} I2S_Mono_Mode_Channel; + +/** + * @brief I2S frame channel mode type definition + */ +typedef enum { + I2S_FS_CHANNELS_2 = 0, /*!< I2S frame is for 2 channels */ + I2S_FS_CHANNELS_3, /*!< I2S frame is for 3 channels */ + I2S_FS_CHANNELS_4, /*!< I2S frame is for 4 channels */ +} I2S_Fs_Channel_Type; + +/** + * @brief I2S mono control definition + */ +typedef enum { + I2S_MONO_CONTROL_STEREO = 0, /*!< I2S output stereo */ + I2S_MONO_CONTROL_MONO, /*!< I2S output mono */ +} I2S_MonoControl_Type; + +/** + * @brief I2S fifo 24-bit data align type definition + */ +typedef enum { + I2S_FIFO_24_RIGHT_JUSTIFIED = 0, /*!< I2S fifo:[31:24]0x00,[23:0]24bit_data */ + I2S_FIFO_24_LEFT_JUSTIFIED, /*!< I2S fifo:[31:8]24bit_data,[7:0]0x00 */ +} I2S_FIFO_24_Justified_Type; + +/** + * @brief I2S configuration structure type definition + */ +typedef struct +{ + I2S_Endian_Type endianType; /*!< I2S endian configuration */ + I2S_Mode_Type modeType; /*!< I2S mode configuration */ + uint32_t audioFreqHz; /*!< I2S audio pll output frequency in Hz */ + uint32_t sampleFreqHz; /*!< I2S sample data frequency in Hz */ + BL_Fun_Type bclkInvert; /*!< I2S bclk invert configuration */ + I2S_Frame_Size_Type frameSize; /*!< I2S frame size configuration */ + BL_Fun_Type fsInvert; /*!< I2S frame select invert configuration */ + I2S_Fs_Mode_Type fsMode; /*!< I2S frame mode configuration */ + I2S_Fs_Channel_Type fsChannel; /*!< I2S frame channels configuration */ + uint32_t dataOffset; /*!< I2S data output offset configuration */ + I2S_Data_Size_Type dataSize; /*!< I2S data size configuration */ + BL_Fun_Type monoMode; /*!< I2S enable mono mode,when this mode enable,lRMerge must be disabled */ + I2S_Mono_Mode_Channel monoModeChannel; /*!< I2S mono mode channel configuration */ +} I2S_CFG_Type; + +/** + * @brief I2S FIFO configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type lRMerge; /*!< I2S FIFO contains both left and right channel data in one entry */ + BL_Fun_Type frameDataExchange; /*!< I2S exchange left and right channel data in one entry */ + BL_Fun_Type txfifoDmaEnable; /*!< Enable or disable I2S tx fifo dma function. */ + BL_Fun_Type rxfifoDmaEnable; /*!< Enable or disable I2S rx fifo dma function. */ + uint8_t rxFifoLevel; /*!< I2S receive fifo interrupt trigger level. only valid when fifo mode enabled. */ + uint8_t txFifoLevel; /*!< I2S transmit fifo interrupt trigger level. only valid when fifo mode enabled. */ +} I2S_FifoCfg_Type; + +/** + * @brief I2S IO configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type deglitchEn; /*!< Enable or disable deglitch(for all the input pins) */ + uint8_t deglitchCnt; /*!< Deglitch cycle count(unit:cycle of I2S kernel clock) */ + BL_Fun_Type inverseBCLK; /*!< Enable or disable inverse BCLK signal */ + BL_Fun_Type inverseFS; /*!< Enable or disable inverse FS signal */ + BL_Fun_Type inverseRX; /*!< Enable or disable inverse RX signal */ + BL_Fun_Type inverseTX; /*!< Enable or disable inverse TX signal */ +} I2S_IOCfg_Type; + +/*@} end of group I2S_Public_Types */ + +/** @defgroup I2S_Public_Constants + * @{ + */ + +/** @defgroup I2S_MODE_TYPE + * @{ + */ +#define IS_I2S_MODE_TYPE(type) (((type) == I2S_MODE_I2S_LEFT) || \ + ((type) == I2S_MODE_I2S_RIGHT) || \ + ((type) == I2S_MODE_I2S_DSP)) + +/** @defgroup I2S_ROLE_TYPE + * @{ + */ +#define IS_I2S_ROLE_TYPE(type) (((type) == I2S_ROLE_MASTER) || \ + ((type) == I2S_ROLE_SLAVE)) + +/** @defgroup I2S_DATA_SIZE_TYPE + * @{ + */ +#define IS_I2S_DATA_SIZE_TYPE(type) (((type) == I2S_SIZE_DATA_8) || \ + ((type) == I2S_SIZE_DATA_16) || \ + ((type) == I2S_SIZE_DATA_24) || \ + ((type) == I2S_SIZE_DATA_32)) + +/** @defgroup I2S_FRAME_SIZE_TYPE + * @{ + */ +#define IS_I2S_FRAME_SIZE_TYPE(type) (((type) == I2S_SIZE_FRAME_8) || \ + ((type) == I2S_SIZE_FRAME_16) || \ + ((type) == I2S_SIZE_FRAME_24) || \ + ((type) == I2S_SIZE_FRAME_32)) + +/** @defgroup I2S_ENDIAN_TYPE + * @{ + */ +#define IS_I2S_ENDIAN_TYPE(type) (((type) == I2S_DATA_ENDIAN_MSB) || \ + ((type) == I2S_DATA_ENDIAN_LSB)) + +/** @defgroup I2S_FS_MODE_TYPE + * @{ + */ +#define IS_I2S_FS_MODE_TYPE(type) (((type) == I2S_FS_MODE_EVEN) || \ + ((type) == I2S_FS_MODE_1T)) + +/** @defgroup I2S_MONO_MODE_CHANNEL + * @{ + */ +#define IS_I2S_MONO_MODE_CHANNEL(type) (((type) == I2S_RX_MONO_MODE_LEFT_CHANNEL) || \ + ((type) == I2S_RX_MONO_MODE_RIGHT_CHANNEL)) + +/** @defgroup I2S_FS_CHANNEL_TYPE + * @{ + */ +#define IS_I2S_FS_CHANNEL_TYPE(type) (((type) == I2S_FS_CHANNELS_2) || \ + ((type) == I2S_FS_CHANNELS_3) || \ + ((type) == I2S_FS_CHANNELS_4)) + +/** @defgroup I2S_MONOCONTROL_TYPE + * @{ + */ +#define IS_I2S_MONOCONTROL_TYPE(type) (((type) == I2S_MONO_CONTROL_STEREO) || \ + ((type) == I2S_MONO_CONTROL_MONO)) + +/** @defgroup I2S_FIFO_24_JUSTIFIED_TYPE + * @{ + */ +#define IS_I2S_FIFO_24_JUSTIFIED_TYPE(type) (((type) == I2S_FIFO_24_RIGHT_JUSTIFIED) || \ + ((type) == I2S_FIFO_24_LEFT_JUSTIFIED)) + +/*@} end of group I2S_Public_Constants */ + +/** @defgroup I2S_Public_Macros + * @{ + */ +#define I2S_TX_FIFO_SIZE 16 +#define I2S_RX_FIFO_SIZE 16 + +/*@} end of group I2S_Public_Macros */ + +/** @defgroup I2S_Public_Functions + * @{ + */ + +/** + * @brief I2S Functions + */ +void I2S_SetBclkPeriod(I2S_CFG_Type *i2sCfg); +void I2S_Init(I2S_CFG_Type *i2sCfg); +void I2S_FifoConfig(I2S_FifoCfg_Type *fifoCfg); +void I2S_IOConfig(I2S_IOCfg_Type *ioCfg); +void I2S_Enable(I2S_Role_Type roleType); +void I2S_Disable(void); +uint32_t I2S_Read(void); +void I2S_Write(uint32_t data); +void I2S_Mute(BL_Fun_Type enabled); +void I2S_SetFifoJustified(I2S_FIFO_24_Justified_Type justType); +uint32_t I2S_GetTxFIFO_AvlCnt(void); +uint32_t I2S_GetRxFIFO_AvlCnt(void); +void I2S_Flush(void); + +/*@} end of group I2S_Public_Functions */ + +/*@} end of group I2S */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_I2S_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ir.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ir.h new file mode 100644 index 0000000000000000000000000000000000000000..b39f9a7969ceb540cae10869405bc8cbec99a744 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ir.h @@ -0,0 +1,257 @@ +/** + ****************************************************************************** + * @file bl702_ir.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_IR_H__ +#define __BL702_IR_H__ + +#include "ir_reg.h" +#include "bl702_common.h" +#include "bl702_hbn.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup IR + * @{ + */ + +/** @defgroup IR_Public_Types + * @{ + */ + +/** + * @brief IR direction type definition + */ +typedef enum { + IR_TX, /*!< IR TX direction */ + IR_RX, /*!< IR RX direction */ + IR_TXRX, /*!< IR TX and RX direction */ +} IR_Direction_Type; + +/** + * @brief IR word type definition + */ +typedef enum { + IR_WORD_0, /*!< IR data word 0 */ + IR_WORD_1, /*!< IR data word 1 */ +} IR_Word_Type; + +/** + * @brief IR RX mode type definition + */ +typedef enum { + IR_RX_NEC, /*!< IR RX NEC mode */ + IR_RX_RC5, /*!< IR RX RC5 mode */ + IR_RX_SWM, /*!< IR RX software pulse-width detection mode */ +} IR_RxMode_Type; + +/** + * @brief IR interrupt type definition + */ +typedef enum { + IR_INT_TX, /*!< IR TX transfer end interrupt */ + IR_INT_RX, /*!< IR RX transfer end interrupt */ + IR_INT_ALL, /*!< IR all interrupt */ +} IR_INT_Type; + +/** + * @brief IR fifo underflow or overflow type definition + */ +typedef enum { + IR_RX_FIFO_UNDERFLOW, /*!< Underflow flag of rx fifo */ + IR_RX_FIFO_OVERFLOW, /*!< Overflow flag of rx fifo */ +} IR_FifoStatus_Type; + +/** + * @brief IR TX configuration structure type definition + */ +typedef struct +{ + uint8_t dataBits; /*!< Bit count of data phase */ + BL_Fun_Type tailPulseInverse; /*!< Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type tailPulse; /*!< Enable or disable signal of tail pulse (don't care if SWM is enabled) */ + BL_Fun_Type headPulseInverse; /*!< Enable or disable signal of head pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type headPulse; /*!< Enable or disable signal of head pulse (don't care if SWM is enabled) */ + BL_Fun_Type logic1PulseInverse; /*!< Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type logic0PulseInverse; /*!< Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type dataPulse; /*!< Enable or disable signal of data pulse (don't care if SWM is enabled) */ + BL_Fun_Type outputModulation; /*!< Enable or disable signal of output modulation */ + BL_Fun_Type outputInverse; /*!< Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high */ +} IR_TxCfg_Type; + +/** + * @brief IR TX pulse width configuration structure type definition + */ +typedef struct +{ + uint8_t logic0PulseWidth_1; /*!< Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) */ + uint8_t logic0PulseWidth_0; /*!< Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) */ + uint8_t logic1PulseWidth_1; /*!< Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled) */ + uint8_t logic1PulseWidth_0; /*!< Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled) */ + uint8_t headPulseWidth_1; /*!< Pulse width of head pulse phase 1 (don't care if SWM is enabled) */ + uint8_t headPulseWidth_0; /*!< Pulse width of head pulse phase 0 (don't care if SWM is enabled) */ + uint8_t tailPulseWidth_1; /*!< Pulse width of tail pulse phase 1 (don't care if SWM is enabled) */ + uint8_t tailPulseWidth_0; /*!< Pulse width of tail pulse phase 0 (don't care if SWM is enabled) */ + uint8_t moduWidth_1; /*!< Modulation phase 1 width */ + uint8_t moduWidth_0; /*!< Modulation phase 0 width */ + uint16_t pulseWidthUnit; /*!< Pulse width unit */ +} IR_TxPulseWidthCfg_Type; + +/** + * @brief IR TX software mode pulse width(multiples of pulse width unit) configuration structure type definition + */ +typedef struct +{ + uint32_t swmData0; /*!< SWM pulse width data 0~7,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData1; /*!< SWM pulse width data 8~15,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData2; /*!< SWM pulse width data 16~23,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData3; /*!< SWM pulse width data 24~31,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData4; /*!< SWM pulse width data 32~39,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData5; /*!< SWM pulse width data 40~47,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData6; /*!< SWM pulse width data 48~55,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData7; /*!< SWM pulse width data 56~63,multiples of pulse width unit,each pulse is represented by 4-bit */ +} IR_TxSWMPulseWidthCfg_Type; + +/** + * @brief IR RX configuration structure type definition + */ +typedef struct +{ + IR_RxMode_Type rxMode; /*!< Set ir rx mode */ + BL_Fun_Type inputInverse; /*!< Enable or disable signal of input inverse */ + uint16_t endThreshold; /*!< Pulse width threshold to trigger end condition */ + uint16_t dataThreshold; /*!< Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled) */ + BL_Fun_Type rxDeglitch; /*!< Enable or disable signal of rx input de-glitch function */ + uint8_t DeglitchCnt; /*!< De-glitch function cycle count */ +} IR_RxCfg_Type; + +/*@} end of group IR_Public_Types */ + +/** @defgroup IR_Public_Constants + * @{ + */ + +/** @defgroup IR_DIRECTION_TYPE + * @{ + */ +#define IS_IR_DIRECTION_TYPE(type) (((type) == IR_TX) || \ + ((type) == IR_RX) || \ + ((type) == IR_TXRX)) + +/** @defgroup IR_WORD_TYPE + * @{ + */ +#define IS_IR_WORD_TYPE(type) (((type) == IR_WORD_0) || \ + ((type) == IR_WORD_1)) + +/** @defgroup IR_RXMODE_TYPE + * @{ + */ +#define IS_IR_RXMODE_TYPE(type) (((type) == IR_RX_NEC) || \ + ((type) == IR_RX_RC5) || \ + ((type) == IR_RX_SWM)) + +/** @defgroup IR_INT_TYPE + * @{ + */ +#define IS_IR_INT_TYPE(type) (((type) == IR_INT_TX) || \ + ((type) == IR_INT_RX) || \ + ((type) == IR_INT_ALL)) + +/** @defgroup IR_FIFOSTATUS_TYPE + * @{ + */ +#define IS_IR_FIFOSTATUS_TYPE(type) (((type) == IR_RX_FIFO_UNDERFLOW) || \ + ((type) == IR_RX_FIFO_OVERFLOW)) + +/*@} end of group IR_Public_Constants */ + +/** @defgroup IR_Public_Macros + * @{ + */ +#define IR_RX_FIFO_SIZE 64 + +/*@} end of group IR_Public_Macros */ + +/** @defgroup IR_Public_Functions + * @{ + */ + +/** + * @brief IR Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void IRRX_IRQHandler(void); +void IRTX_IRQHandler(void); +#endif +BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg); +BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg); +BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg); +BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg); +BL_Err_Type IR_DeInit(void); +BL_Err_Type IR_Enable(IR_Direction_Type direct); +BL_Err_Type IR_Disable(IR_Direction_Type direct); +BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM); +BL_Err_Type IR_RxFIFOClear(void); +BL_Err_Type IR_SendData(IR_Word_Type irWord, uint32_t data); +BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length); +BL_Err_Type IR_SendCommand(uint32_t word1, uint32_t word0); +BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length); +BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command); +BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType); +BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun); +BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType); +BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts); +uint32_t IR_ReceiveData(IR_Word_Type irWord); +uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length); +BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command); +uint8_t IR_GetRxDataBitCount(void); +uint8_t IR_GetRxFIFOCount(void); +IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length); +BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length); +uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data); +BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, + uint8_t code1L); +BL_Err_Type IR_LEDSend(uint32_t data); + +/*@} end of group IR_Public_Functions */ + +/*@} end of group IR */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_IR_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_it.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_it.h new file mode 100644 index 0000000000000000000000000000000000000000..ab6f23c1c14ad6d80f16e71938a3a8a4b12491c1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_it.h @@ -0,0 +1,49 @@ +#ifndef __BL702_IT_H__ +#define __BL702_IT_H__ + +#include "bl702.h" +#include "bl_common.h" + +/** @addtogroup BL606_Peripheral_Driver + * @{ + */ + +/** @addtogroup COMMON + * @{ + */ + +/** @defgroup COMMON_Public_Types + * @{ + */ + +/*@} end of group COMMON_Public_Types */ + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** @defgroup DRIVER_INT_PERIPH + * @{ + */ +#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) + +/*@} end of group DRIVER_INT_PERIPH */ + +/** @defgroup DRIVER_INT_MASK + * @{ + */ +#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) + +/*@} end of group COMMON_Public_Constants */ + +/*@} end of group DRIVER_Public_Macro */ + +/** @defgroup DRIVER_Public_FunctionDeclaration + * @brief DRIVER functions declaration + * @{ + */ +void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); + +/*@} end of group DRIVER_COMMON */ + +#endif /* __BL602_COMMON_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_kys.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_kys.h new file mode 100644 index 0000000000000000000000000000000000000000..03f7dbea39a438b83318b712478b94c50cf75586 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_kys.h @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file bl702_kys.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_KYS_H__ +#define __BL702_KYS_H__ + +#include "kys_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup KYS + * @{ + */ + +/** @defgroup KYS_Public_Types + * @{ + */ + +/** + * @brief KYS keycode type definition + */ +typedef enum { + KYS_KEYCODE_0, /*!< KYS keycode 0 */ + KYS_KEYCODE_1, /*!< KYS keycode 1 */ + KYS_KEYCODE_2, /*!< KYS keycode 2 */ + KYS_KEYCODE_3, /*!< KYS keycode 3 */ +} KYS_Keycode_Type; + +/** + * @brief KYS configuration structure type definition + */ +typedef struct +{ + uint8_t col; /*!< Col of keyboard,max:20 */ + uint8_t row; /*!< Row of keyboard,max:8 */ + uint8_t idleDuration; /*!< Idle duration between column scans */ + BL_Fun_Type ghostEn; /*!< Enable or disable ghost key event detection */ + BL_Fun_Type deglitchEn; /*!< Enable or disable deglitch function */ + uint8_t deglitchCnt; /*!< Deglitch count */ +} KYS_CFG_Type; + +/*@} end of group KYS_Public_Types */ + +/** @defgroup KYS_Public_Constants + * @{ + */ + +/** @defgroup KYS_KEYCODE_TYPE + * @{ + */ +#define IS_KYS_KEYCODE_TYPE(type) (((type) == KYS_KEYCODE_0) || \ + ((type) == KYS_KEYCODE_1) || \ + ((type) == KYS_KEYCODE_2) || \ + ((type) == KYS_KEYCODE_3)) + +/*@} end of group KYS_Public_Constants */ + +/** @defgroup KYS_Public_Macros + * @{ + */ + +/*@} end of group KYS_Public_Macros */ + +/** @defgroup KYS_Public_Functions + * @{ + */ + +/** + * @brief UART Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void KYS_IRQHandler(void); +#endif +BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg); +BL_Err_Type KYS_Enable(void); +BL_Err_Type KYS_Disable(void); +BL_Err_Type KYS_IntMask(BL_Mask_Type intMask); +BL_Err_Type KYS_IntClear(void); +BL_Err_Type KYS_Int_Callback_Install(intCallback_Type *cbFun); +uint8_t KYS_GetIntStatus(void); +uint8_t KYS_GetKeycode(KYS_Keycode_Type keycode, uint8_t *col, uint8_t *row); + +/*@} end of group KYS_Public_Functions */ + +/*@} end of group KYS */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_KYS_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_l1c.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_l1c.h new file mode 100644 index 0000000000000000000000000000000000000000..a4faaa266d314c2f7ae016610717905d89b5395a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_l1c.h @@ -0,0 +1,203 @@ +/** + ****************************************************************************** + * @file bl702_l1c.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_L1C_H__ +#define __BL702_L1C_H__ + +#include "l1c_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup L1C + * @{ + */ + +/** @defgroup L1C_Public_Types + * @{ + */ + +/** + * @brief L1C configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type wrapDis; /*!< wrap disable */ + BL_Fun_Type bypassEn; /*!< bypass cache enable */ + uint8_t wayDis; /*!< Disable part of cache ways & used as ITCM */ + BL_Fun_Type cntEn; /*!< l1c count enable */ +} L1C_CACHE_Cfg_Type; + +/** + * @brief L1C BMX arb mode type definition + */ +typedef enum { + L1C_BMX_ARB_FIX, /*!< 0->fix */ + L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + L1C_BMX_ARB_RANDOM, /*!< 3->random */ +} L1C_BMX_ARB_Type; + +/** + * @brief L1C BMX configuration structure type definition + */ +typedef struct +{ + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +} L1C_BMX_Cfg_Type; + +/** + * @brief L1C BMX bus err type definition + */ +typedef enum { + L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + L1C_BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +} L1C_BMX_BUS_ERR_Type; + +/** + * @brief L1C BMX bus err interrupt type definition + */ +typedef enum { + L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */ + L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */ +} L1C_BMX_ERR_INT_Type; + +/** + * @brief L1C BMX time out interrupt type definition + */ +typedef enum { + L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */ + L1C_BMX_TO_INT_ALL, /*!< L1C_BMX timeout interrupt max num */ +} L1C_BMX_TO_INT_Type; + +/*@} end of group L1C_Public_Types */ + +/** @defgroup L1C_Public_Constants + * @{ + */ + +/** @defgroup L1C_BMX_ARB_TYPE + * @{ + */ +#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) || \ + ((type) == L1C_BMX_ARB_ROUND_ROBIN) || \ + ((type) == L1C_BMX_ARB_RANDOM)) + +/** @defgroup L1C_BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == L1C_BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup L1C_BMX_ERR_INT_TYPE + * @{ + */ +#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \ + ((type) == L1C_BMX_ERR_INT_ALL)) + +/** @defgroup L1C_BMX_TO_INT_TYPE + * @{ + */ +#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \ + ((type) == L1C_BMX_TO_INT_ALL)) + +/*@} end of group L1C_Public_Constants */ + +/** @defgroup L1C_Public_Macros + * @{ + */ +#define L1C_WAY_DISABLE_NONE 0x00 +#define L1C_WAY_DISABLE_ONE 0x01 +#define L1C_WAY_DISABLE_TWO 0x03 +#define L1C_WAY_DISABLE_THREE 0x07 +#define L1C_WAY_DISABLE_ALL 0x0F +#define L1C_WAY_DISABLE_USER 0xFF +#if 1 +/*NP config address */ +#define L1C_CONF_REG (L1C_BASE + 0x00) +#define L1C_HIT_CNT_LSB_REG (L1C_BASE + 0x04) +#define L1C_HIT_CNT_MSB_REG (L1C_BASE + 0x08) +#define L1C_MISS_CNT_REG (L1C_BASE + 0x0C) +/* Get miss and hit count */ +#define L1C_Get_Miss_Cnt() BL702_REG_RD(L1C_MISS_CNT_REG) +#define L1C_Get_Hit_Cnt_LSB() BL702_REG_RD(L1C_HIT_CNT_LSB_REG) +#define L1C_Get_Hit_Cnt_MSB() BL702_REG_RD(L1C_HIT_CNT_MSB_REG) +#endif + +/*@} end of group L1C_Public_Macros */ + +/** @defgroup L1C_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_ERR_IRQHandler(void); +void L1C_BMX_TO_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type L1C_Cache_Enable_Set(uint8_t wayDisable); +void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn); +BL_Err_Type L1C_Cache_Flush(uint8_t wayDisable); +BL_Err_Type L1C_Cache_Flush_Ext(void); +void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh); +uint32_t L1C_Cache_Miss_Count_Get(void); +void L1C_Cache_Read_Disable(void); +/*----------*/ +BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap); +BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal); +BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable); +/*----------*/ +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg); +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void); +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void); +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void); +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void); +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType); +uint32_t L1C_BMX_Get_Err_Addr(void); +BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, + intCallback_Type *cbFun); +/*----------*/; + +/*@} end of group L1C_Public_Functions */ + +/*@} end of group L1C */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_L1C_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_mjpeg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_mjpeg.h new file mode 100644 index 0000000000000000000000000000000000000000..87dbb08feed7267d386c28ceb2d65e9aeef2f391 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_mjpeg.h @@ -0,0 +1,229 @@ +/** + ****************************************************************************** + * @file bl702_mjpeg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_MJPEG_H__ +#define __BL702_MJPEG_H__ + +#include "mjpeg_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup MJPEG + * @{ + */ + +/** @defgroup MJPEG_Public_Types + * @{ + */ + +/** + * @brief MJPEG YUV format definition + */ +typedef enum { + MJPEG_YUV420, /*!< MJPEG YUV420 planar mode */ + MJPEG_YUV400, /*!< MJPEG YUV400 grey scale mode */ + MJPEG_YUV422_PLANAR, /*!< MJPEG YUV422 planar mode */ + MJPEG_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */ +} MJPEG_YUV_Mode_Type; + +/** + * @brief MJPEG burst type definition + */ +typedef enum { + MJPEG_BURST_SINGLE, /*!< MJPEG burst single */ + MJPEG_BURST_INCR4, /*!< MJPEG burst incr4 */ + MJPEG_BURST_INCR8, /*!< MJPEG burst incr8 */ + MJPEG_BURST_INCR16, /*!< MJPEG burst incr16 */ +} MJPEG_Burst_Type; + +/** + * @brief MJPEG swap mode block definition + */ +typedef enum { + MJPEG_BLOCK_0, /*!< Memory block 0 */ + MJPEG_BLOCK_1, /*!< Memory block 1 */ +} MJPEG_Swap_Block_Type; + +/** + * @brief MJPEG interrupt type definition + */ +typedef enum { + MJPEG_INT_NORMAL, /*!< MJPEG normal write interrupt */ + MJPEG_INT_CAM_OVERWRITE, /*!< MJPEG camera overwrite interrupt */ + MJPEG_INT_MEM_OVERWRITE, /*!< MJPEG memory overwrite interrupt */ + MJPEG_INT_FRAME_OVERWRITE, /*!< MJPEG frame overwrite interrupt */ + MJPEG_INT_BACK_IDLE, /*!< MJPEG back idle interrupt */ + MJPEG_INT_SWAP, /*!< MJPEG swap memory block interrupt */ + MJPEG_INT_ALL, /*!< MJPEG all interrupt type */ +} MJPEG_INT_Type; + +/** + * @brief MJPEG configuration strcut definition + */ +typedef struct +{ + MJPEG_Burst_Type burst; /*!< MJPEG burst type */ + uint8_t quality; /*!< MJPEG quantization selection, 1-75:Q table selection, others:Q100(lossless) */ + MJPEG_YUV_Mode_Type yuv; /*!< MJPEG control YUV mode */ + uint16_t waitCount; /*!< Cycle count in wait state, default value:0x400 */ + uint32_t bufferMjpeg; /*!< MJPEG buffer addr */ + uint32_t sizeMjpeg; /*!< MJPEG buffer size */ + uint32_t bufferCamYY; /*!< CAM buffer address of Y frame */ + uint32_t sizeCamYY; /*!< CAM buffer size of Y frame */ + uint32_t bufferCamUV; /*!< CAM buffer address of UV frame */ + uint32_t sizeCamUV; /*!< CAM buffer size of UV frame */ + uint16_t resolutionX; /*!< CAM RESOLUTION X */ + uint16_t resolutionY; /*!< CAM RESOLUTION Y */ + BL_Fun_Type bitOrderEnable; /*!< MJPEG bitstream order adjustment */ + BL_Fun_Type evenOrderEnable; /*!< Enable:U is even byte of UV frame and V is odd byte of UV frame */ + BL_Fun_Type swapModeEnable; /*!< Enable or disable write swap mode */ + BL_Fun_Type overStopEnable; /*!< Enable:if camera overwrite error occur,mjpeg will stop fetch data */ + BL_Fun_Type reflectDmy; /*!< UV dummy with relect */ + BL_Fun_Type verticalDmy; /*!< MJPEG last half vertical block with dummy data 0x80 */ + BL_Fun_Type horizationalDmy; /*!< MJPEG last half horizational block with dummy data 0x80 */ +} MJPEG_CFG_Type; + +/** + * @brief MJPEG packet configuration strcut definition + */ +typedef struct +{ + BL_Fun_Type packetEnable; /*!< Enable or disable packet mode */ + BL_Fun_Type endToTail; /*!< Enable or disable jpeg end jump to packet tail */ + uint16_t frameHead; /*!< Preserve head memory space for each frame */ + BL_Fun_Type frameTail; /*!< Enable:auto fill tail 0xFF and 0xD9 */ + uint16_t packetHead; /*!< Packet head byte count */ + uint16_t packetBody; /*!< Packet body byte count */ + uint16_t packetTail; /*!< Packet tail byte count */ +} MJPEG_Packet_Type; + +/** + * @brief MJPEG frame information strcut definition + */ +typedef struct +{ + uint8_t validFrames; /*!< Valid frames */ + uint32_t curFrameAddr; /*!< Current frame address */ + uint32_t curFrameBytes; /*!< Current frame bytes */ + uint8_t curFrameQ; /*!< Current frame Q mode */ + uint32_t status; /*!< MJPEG module status */ +} MJPEG_Frame_Info; + +/*@} end of group MJPEG_Public_Types */ + +/** @defgroup MJPEG_Public_Constants + * @{ + */ + +/** @defgroup MJPEG_YUV_MODE_TYPE + * @{ + */ +#define IS_MJPEG_YUV_MODE_TYPE(type) (((type) == MJPEG_YUV420) || \ + ((type) == MJPEG_YUV400) || \ + ((type) == MJPEG_YUV422_PLANAR) || \ + ((type) == MJPEG_YUV422_INTERLEAVE)) + +/** @defgroup MJPEG_BURST_TYPE + * @{ + */ +#define IS_MJPEG_BURST_TYPE(type) (((type) == MJPEG_BURST_SINGLE) || \ + ((type) == MJPEG_BURST_INCR4) || \ + ((type) == MJPEG_BURST_INCR8) || \ + ((type) == MJPEG_BURST_INCR16)) + +/** @defgroup MJPEG_SWAP_BLOCK_TYPE + * @{ + */ +#define IS_MJPEG_SWAP_BLOCK_TYPE(type) (((type) == MJPEG_BLOCK_0) || \ + ((type) == MJPEG_BLOCK_1)) + +/** @defgroup MJPEG_INT_TYPE + * @{ + */ +#define IS_MJPEG_INT_TYPE(type) (((type) == MJPEG_INT_NORMAL) || \ + ((type) == MJPEG_INT_CAM_OVERWRITE) || \ + ((type) == MJPEG_INT_MEM_OVERWRITE) || \ + ((type) == MJPEG_INT_FRAME_OVERWRITE) || \ + ((type) == MJPEG_INT_BACK_IDLE) || \ + ((type) == MJPEG_INT_SWAP) || \ + ((type) == MJPEG_INT_ALL)) + +/*@} end of group MJPEG_Public_Constants */ + +/** @defgroup MJPEG_Public_Macros + * @{ + */ + +/*@} end of group MJPEG_Public_Macros */ + +/** @defgroup MJPEG_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void MJPEG_IRQHandler(void); +#endif +void MJPEG_Init(MJPEG_CFG_Type *cfg); +void MJPEG_Packet_Config(MJPEG_Packet_Type *cfg); +void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0); +void MJPEG_Set_YUYV_Order_Planar(uint8_t yy, uint8_t uv); +void MJPEG_Deinit(void); +void MJPEG_Enable(void); +void MJPEG_Disable(void); +void MJPEG_SW_Enable(uint8_t count); +void MJPEG_SW_Run(void); +void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info); +uint8_t MJPEG_Get_Frame_Count(void); +void MJPEG_Pop_Frame(void); +void MJPEG_Current_Block_Clear(void); +MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void); +BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block); +BL_Sts_Type MJPEG_Current_Block_Is_Start(void); +BL_Sts_Type MJPEG_Current_Block_Is_End(void); +uint32_t MJPEG_Get_Remain_Bit(void); +void MJPEG_Set_Frame_Threshold(uint8_t count); +void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask); +void MJPEG_IntClr(MJPEG_INT_Type intType); +void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun); + +/*@} end of group MJPEG_Public_Functions */ + +/*@} end of group MJPEG */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_MJPEG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nf_cfg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nf_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..c3764d32ad80ef51b40a09684635de7d5c43f95e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nf_cfg.h @@ -0,0 +1,48 @@ +/** + ****************************************************************************** + * @file bl702_nf_cfg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_NF_CFG_H__ +#define __BL702_NF_CFG_H__ + +#include "string.h" +#include "bl702_nflash.h" +#include "bl702_sf_ctrl.h" + +/** @defgroup NF_CFG_Public_Functions + * @{ + */ +uint32_t NF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, Nand_Flash_Cfg_Type *pFlashCfg); + +#endif /* __BL702_NF_CFG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nflash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nflash.h new file mode 100644 index 0000000000000000000000000000000000000000..e7ed487b83e796c7abb3db949f3225cd1eb1aafb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nflash.h @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file bl702_nflah.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_NFLAH_H__ +#define __BL702_NFLAH_H__ + +#include "bl702_common.h" +#include "bl702_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH + * @{ + */ + +/** @defgroup SFLAH_Public_Types + * @{ + */ + +/** + * @brief Serial flash configuration structure type definition + */ +/*@} end of group SFLAH_Public_Types */ + +/** @defgroup SFLAH_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_Public_Constants */ + +/** @defgroup SFLAH_Public_Macros + * @{ + */ +#define BFLB_NAND_FLASH_BLK_DATA_SIZE (128 * 1024) +#define BFLB_NAND_FLASH_BLK_TOTAL_SIZE ((128 + 4) * 1024) +#define BFLB_NAND_FLASH_PAGE_SIZE (2048) +#define BFLB_NAND_FLASH_PAGE_TOTAL_SIZE (2048 + 64) +#define BFLB_NAND_FLASH_PAGES_PER_BLOCK (64) +#define BFLB_NAND_FLASH_CMD_INVALID (0xff) +#define DISK_SECTOR_SIZE (512) +typedef unsigned char BYTE; +typedef unsigned long DWORD; +typedef unsigned int UINT; +typedef BYTE DSTATUS; +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + +typedef enum { + READ_DATA_FROM_CACHE = 0, //date:2048 bytes in each page + READ_SPARE_DATA_FROM_CACHE = 1, //spare date:64 bytes in each page +} BL_Nand_Flash_READ_DATE_TYPE; + +typedef struct +{ + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */ + uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk128EraseCmd; /*!< Block 128K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t programLoadCmd; /*!< Program Load cmd */ + uint8_t qprogramLoadCmd; /*!< Program Load cmd x4*/ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t pageReadToCacheCmd; /*!< Page read comamnd */ + uint8_t getFeaturesCmd; /*!< GET FEATURES command to read the status */ + uint8_t setFeaturesCmd; /*!< SET FEATURES command to read the status */ + uint8_t readFromCacheCmd; /*!< Read from cache command */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE132k; /*!< 132K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +} __attribute__((packed)) Nand_Flash_Cfg_Type; + +//BL_Nand_Flash_Program_Bit_Err_Type ATTR_TCM_SECTION NFlash_Pass(uint8_t errorCode, BL_Nand_Flash_OP_Type opType); +BL_Err_Type NFlash_GetJedecId(Nand_Flash_Cfg_Type *flashCfg, uint8_t *data); +BL_Err_Type ATTR_TCM_SECTION NFlash_Erase(Nand_Flash_Cfg_Type *flashCfg, uint32_t startAddr, uint32_t endAddr); +BL_Err_Type ATTR_TCM_SECTION NFlash_Blk128_Erase(Nand_Flash_Cfg_Type *flashCfg, uint32_t blockNum); +BL_Err_Type ATTR_TCM_SECTION NFlash_Write_Enable(Nand_Flash_Cfg_Type *flashCfg); +BL_Err_Type ATTR_TCM_SECTION NFlash_Read(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type ATTR_TCM_SECTION NFlash_Program(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, const uint8_t *data, uint32_t len); +BL_Err_Type ATTR_TCM_SECTION NFlash_Page_Read_To_Cache(Nand_Flash_Cfg_Type *flashCfg, uint32_t absolutePageNum); +BL_Err_Type ATTR_TCM_SECTION NFlash_Get_Feature(Nand_Flash_Cfg_Type *flashCfg, uint8_t *data, uint8_t cmdType); +BL_Err_Type ATTR_TCM_SECTION NFlash_Read_From_Cache(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t readType); +BL_Err_Type ATTR_TCM_SECTION NFlash_Program_Execute(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr); +BL_Err_Type ATTR_TCM_SECTION NFlash_Set_Feature(Nand_Flash_Cfg_Type *flashCfg); +BL_Err_Type ATTR_TCM_SECTION NFlash_Program_Load(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, const uint8_t *data, uint32_t len); +BL_Err_Type ATTR_TCM_SECTION NFlash_Check_Bad_Block(Nand_Flash_Cfg_Type *flashCfg, uint32_t blockNum, uint8_t *data, uint32_t len); +DRESULT ff_disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count); +DRESULT ff_disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count); +DSTATUS ff_disk_initialize(BYTE pdrv); + +/*@} end of group SFLAH_Public_Functions */ + +/*@} end of group SFLAH */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SFLAH_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pds.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pds.h new file mode 100644 index 0000000000000000000000000000000000000000..8dc6f30c91cb746d186439d58383eb1a2aa90348 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pds.h @@ -0,0 +1,796 @@ +/** + ****************************************************************************** + * @file bl702_pds.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_PDS_H__ +#define __BL702_PDS_H__ + +#include "pds_reg.h" +#include "bl702_ef_ctrl.h" +#include "bl702_aon.h" +#include "bl702_hbn.h" +#include "bl702_sflash.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Public_Types + * @{ + */ + +/** + * @brief PDS LDO level type definition + */ +typedef enum { + PDS_LDO_LEVEL_0P60V = 0, /*!< PDS LDO voltage 0.60V */ + PDS_LDO_LEVEL_0P65V = 1, /*!< PDS LDO voltage 0.65V */ + PDS_LDO_LEVEL_0P70V = 2, /*!< PDS LDO voltage 0.70V */ + PDS_LDO_LEVEL_0P75V = 3, /*!< PDS LDO voltage 0.75V */ + PDS_LDO_LEVEL_0P80V = 4, /*!< PDS LDO voltage 0.80V */ + PDS_LDO_LEVEL_0P85V = 5, /*!< PDS LDO voltage 0.85V */ + PDS_LDO_LEVEL_0P90V = 6, /*!< PDS LDO voltage 0.90V */ + PDS_LDO_LEVEL_0P95V = 7, /*!< PDS LDO voltage 0.95V */ + PDS_LDO_LEVEL_1P00V = 8, /*!< PDS LDO voltage 1.00V */ + PDS_LDO_LEVEL_1P05V = 9, /*!< PDS LDO voltage 1.05V */ + PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */ + PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */ + PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */ + PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */ + PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */ + PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */ +} PDS_LDO_LEVEL_Type; + +/** + * @brief PDS RAM configuration type definition + */ +typedef struct +{ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET1N : 1; /*!< [0] 0~16KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET1N : 1; /*!< [1] 16~32KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET1N : 1; /*!< [2] 32~48KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET1N : 1; /*!< [3] 48~64KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET2N : 1; /*!< [4] 0~16KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET2N : 1; /*!< [5] 16~32KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET2N : 1; /*!< [6] 32~48KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET2N : 1; /*!< [7] 48~64KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_PGEN : 1; /*!< [8] 0~16KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_PGEN : 1; /*!< [9] 16~32KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_PGEN : 1; /*!< [10] 32~48KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_PGEN : 1; /*!< [11] 48~64KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_RSV : 20; /*!< [31:12]reserve */ +} PDS_RAM_CFG_Type; + +/** + * @brief PDS PAD pin configuration type definition + */ +typedef enum { + PDS_PAD_PIN_GPIO_17, /*!< PAD GPIO 17 */ + PDS_PAD_PIN_GPIO_18, /*!< PAD GPIO 18 */ + PDS_PAD_PIN_GPIO_19, /*!< PAD GPIO 19 */ + PDS_PAD_PIN_GPIO_20, /*!< PAD GPIO 20 */ + PDS_PAD_PIN_GPIO_21, /*!< PAD GPIO 21 */ + PDS_PAD_PIN_GPIO_22, /*!< PAD GPIO 22 */ + PDS_PAD_PIN_GPIO_23, /*!< PAD GPIO 23 */ + PDS_PAD_PIN_GPIO_24, /*!< PAD GPIO 24 */ + PDS_PAD_PIN_GPIO_25, /*!< PAD GPIO 25 */ + PDS_PAD_PIN_GPIO_26, /*!< PAD GPIO 26 */ + PDS_PAD_PIN_GPIO_27, /*!< PAD GPIO 27 */ + PDS_PAD_PIN_GPIO_28, /*!< PAD GPIO 28 */ +} PDS_PAD_PIN_Type; + +/** + * @brief PDS PAD configuration type definition + */ +typedef enum { + PDS_PAD_CFG_PULL_NONE, /*!< no PD/PU/IE on PAD */ + PDS_PAD_CFG_PULL_DOWN, /*!< Pulldown PAD */ + PDS_PAD_CFG_PULL_UP, /*!< Pullup PAD */ + PDS_PAD_CFG_ACTIVE_IE, /*!< Active IE */ +} PDS_PAD_CFG_Type; + +/** + * @brief PDS configuration type definition + */ +typedef struct +{ + uint32_t pdsStart : 1; /*!< [0]PDS Start */ + uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */ + uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */ + uint32_t saveWifiState : 1; /*!< [3]Save WIFI State Before Enter PDS */ + uint32_t dcdc18Off : 1; /*!< [4]power down dcdc18 during PDS */ + uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */ + uint32_t gpioIePuPd : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */ + uint32_t puFlash : 1; /*!< [7]turn off Flash Power During PDS */ + uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */ + uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */ + uint32_t swPuFlash : 1; /*!< [10]SW Turn on Flash */ + uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */ + uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */ + uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */ + uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */ + uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */ + uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */ + uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */ + uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */ + uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */ + uint32_t reserved20 : 1; /*!< [20]Reserved */ + uint32_t cpu0WfiMask : 1; /*!< [21]pds start condition mask np_wfi */ + uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */ + uint32_t pdsForceRamClkEn : 1; /*!< [23]Force SRAM CLK Enable */ + uint32_t pdsLdoVol : 4; /*!< [27:24]LDO voltage value in PDS mode */ + uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */ + uint32_t pdsCtlPllSel : 2; /*!< [31:30]select the way PLL controlled by PDS */ +} PDS_CFG_Type; + +/** + * @brief PDS configuration type definition + */ +typedef struct +{ + uint32_t pdsStart : 1; /*!< [0]PDS Start */ + uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */ + uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */ + uint32_t saveWifiState : 1; /*!< [3]Save WIFI State Before Enter PDS */ + uint32_t dcdc18Off : 1; /*!< [4]power down dcdc18 during PDS */ + uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */ + uint32_t gpioIePuPd : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */ + uint32_t puFlash : 1; /*!< [7]turn off Flash Power During PDS */ + uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */ + uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */ + uint32_t swPuFlash : 1; /*!< [10]SW Turn on Flash */ + uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */ + uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */ + uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */ + uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */ + uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */ + uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */ + uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */ + uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */ + uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */ + uint32_t reserved20 : 1; /*!< [20]Reserved */ + uint32_t cpu0WfiMask : 1; /*!< [21]pds start condition mask np_wfi */ + uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */ + uint32_t pdsForceRamClkEn : 1; /*!< [23]Force SRAM CLK Enable */ + uint32_t pdsLdoVol : 4; /*!< [27:24]LDO voltage value in PDS mode */ + uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */ + uint32_t pdsCtlPllSel : 2; /*!< [31:30]select the way PLL controlled by PDS */ +} PDS_CTL_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t forceCpuPwrOff : 1; /*!< [0]manual force NP power off */ + uint32_t rsv1 : 1; /*!< [1]reserve */ + uint32_t forceBzPwrOff : 1; /*!< [2]manual force BZ power off */ + uint32_t forceUsbPwrOff : 1; /*!< [3]manual force USB power off */ + uint32_t forceCpuIsoEn : 1; /*!< [4]manual force NP isolation */ + uint32_t rsv5 : 1; /*!< [5]reserve */ + uint32_t forceBzIsoEn : 1; /*!< [6]manual force BZ isolation */ + uint32_t forceUsbIsoEn : 1; /*!< [7]manual force USB isolation */ + uint32_t forceCpuPdsRst : 1; /*!< [8]manual force NP pds reset */ + uint32_t rsv9 : 1; /*!< [9]reserve */ + uint32_t forceBzPdsRst : 1; /*!< [10]manual force BZ pds reset */ + uint32_t forceUsbPdsRst : 1; /*!< [11]manual force USB pds reset */ + uint32_t forceCpuMemStby : 1; /*!< [12]manual force NP memory sleep */ + uint32_t rsv13 : 1; /*!< [13]reserve */ + uint32_t forceBzMemStby : 1; /*!< [14]manual force BZ memory sleep */ + uint32_t forceUsbMemStby : 1; /*!< [15]manual force USB memory sleep */ + uint32_t forceCpuGateClk : 1; /*!< [16]manual force NP clock gated */ + uint32_t rsv17 : 1; /*!< [17]reserve */ + uint32_t forceBzGateClk : 1; /*!< [18]manual force BZ clock gated */ + uint32_t forceUsbGateClk : 1; /*!< [19]manual force USB clock gated */ + uint32_t rsv20_31 : 12; /*!< [31:20]reserve */ +} PDS_CTL2_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t rsv0 : 1; /*!< [0]reserve */ + uint32_t forceMiscPwrOff : 1; /*!< [1]manual force MISC pwr_off */ + uint32_t forceBlePwrOff : 1; /*!< [2]manual force BZ_BLE pwr_off */ + uint32_t rsv3_4 : 2; /*!< [4:3]reserve */ + uint32_t forceBleIsoEn : 1; /*!< [5]manual force BZ_BLE iso_en */ + uint32_t rsv6 : 1; /*!< [6]reserve */ + uint32_t forceMiscPdsRst : 1; /*!< [7]manual force MISC pds_rst */ + uint32_t forceBlePdsRst : 1; /*!< [8]manual force BZ_BLE pds_rst */ + uint32_t rsv9 : 1; /*!< [9]reserve */ + uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */ + uint32_t forceBleMemStby : 1; /*!< [11]manual force BZ_BLE mem_stby */ + uint32_t rsv12 : 1; /*!< [12]reserve */ + uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */ + uint32_t forceBleGateClk : 1; /*!< [14]manual force BZ_BLE gate_clk */ + uint32_t rsv15_23 : 9; /*!< [23:15]reserve */ + uint32_t CpuIsoEn : 1; /*!< [24]make NP isolated at PDS Sleep state */ + uint32_t rsv25_26 : 2; /*!< [26:25]reserve */ + uint32_t BzIsoEn : 1; /*!< [27]make BZ isolated at PDS Sleep state */ + uint32_t BleIsoEn : 1; /*!< [28]make Ble isolated at PDS Sleep state */ + uint32_t UsbIsoEn : 1; /*!< [29]make USB isolated at PDS Sleep state */ + uint32_t MiscIsoEn : 1; /*!< [30]make misc isolated at PDS Sleep state */ + uint32_t rsv31 : 1; /*!< [31]reserve */ +} PDS_CTL3_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t cpuPwrOff : 1; /*!< [0] */ + uint32_t cpuRst : 1; /*!< [1] */ + uint32_t cpuMemStby : 1; /*!< [2] */ + uint32_t cpuGateClk : 1; /*!< [3] */ + uint32_t rsv4_11 : 8; /*!< [11:4]reserve */ + uint32_t BzPwrOff : 1; /*!< [12] */ + uint32_t BzRst : 1; /*!< [13] */ + uint32_t BzMemStby : 1; /*!< [14] */ + uint32_t BzGateClk : 1; /*!< [15] */ + uint32_t BlePwrOff : 1; /*!< [16] */ + uint32_t BleRst : 1; /*!< [17] */ + uint32_t BleMemStby : 1; /*!< [18] */ + uint32_t BleGateClk : 1; /*!< [19] */ + uint32_t UsbPwrOff : 1; /*!< [20] */ + uint32_t UsbRst : 1; /*!< [21] */ + uint32_t UsbMemStby : 1; /*!< [22] */ + uint32_t UsbGateClk : 1; /*!< [23] */ + uint32_t MiscPwrOff : 1; /*!< [24] */ + uint32_t MiscRst : 1; /*!< [25] */ + uint32_t MiscMemStby : 1; /*!< [26] */ + uint32_t MiscGateClk : 1; /*!< [27] */ + uint32_t rsv28_29 : 2; /*!< [29:28]reserve */ + uint32_t MiscAnaPwrOff : 1; /*!< [30] */ + uint32_t MiscDigPwrOff : 1; /*!< [31] */ +} PDS_CTL4_Type; + +/** + * @brief PDS default level configuration type definition + */ +typedef struct +{ + PDS_CTL_Type pdsCtl; /*!< PDS_CTL configuration */ + PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */ + PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */ + PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */ +} PDS_DEFAULT_LV_CFG_Type; + +/** + * @brief PDS interrupt type definition + */ +typedef enum { + PDS_INT_WAKEUP = 0, /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */ + PDS_INT_RF_DONE, /*!< PDS RF done interrupt */ + PDS_INT_PLL_DONE, /*!< PDS PLL done interrupt */ + PDS_INT_PDS_SLEEP_CNT, /*!< wakeup trigger by pds_sleep_cnt=0 */ + PDS_INT_HBN_IRQ_OUT0, /*!< wakeup trigger by hbn_irq_out[0] */ + PDS_INT_HBN_IRQ_OUT1, /*!< wakeup trigger by hbn_irq_out[1] */ + PDS_INT_GPIO_IRQ, /*!< wakeup trigger by gpio_irq */ + PDS_INT_IRRX, /*!< wakeup trigger by irrx_int */ + PDS_INT_BLE_SLP_IRQ, /*!< wakeup trigger by ble_slp_irq */ + PDS_INT_USB_WKUP, /*!< wakeup trigger by usb_wkup */ + PDS_INT_KYS_QDEC, /*!< wakeup trigger by kys_int or qdec */ + PDS_INT_MAX, /*!< PDS int max number */ +} PDS_INT_Type; + +/** + * @brief PDS vddcore GPIO interrupt type definition + */ +typedef enum { + PDS_VDDCORE_GPIO_SRC_GPIO_0, /*!< PDS VDDCORE GPIO0 as PDS interrupt source */ + PDS_VDDCORE_GPIO_SRC_GPIO_1, /*!< PDS VDDCORE GPIO1 as PDS interrupt source */ + PDS_VDDCORE_GPIO_SRC_GPIO_2, /*!< PDS VDDCORE GPIO2 as PDS interrupt source */ + PDS_VDDCORE_GPIO_SRC_GPIO_3, /*!< PDS VDDCORE GPIO3 as PDS interrupt source */ + PDS_VDDCORE_GPIO_SRC_GPIO_4, /*!< PDS VDDCORE GPIO4 as PDS interrupt source */ + PDS_VDDCORE_GPIO_SRC_GPIO_5, /*!< PDS VDDCORE GPIO5 as PDS interrupt source */ + PDS_VDDCORE_GPIO_SRC_GPIO_6, /*!< PDS VDDCORE GPIO6 as PDS interrupt source */ + PDS_VDDCORE_GPIO_SRC_GPIO_7, /*!< PDS VDDCORE GPIO7 as PDS interrupt source */ +} PDS_VDDCORE_GPIO_SRC_Type; + +/** + * @brief PDS reset event type definition + */ +typedef enum { + PDS_RST_EVENT_BUS_RST, /*!< hreset_n (Bus Reset) */ + PDS_RST_EVENT_HBN_PWR_ON_RST, /*!< pwr_rst_n (hbn power on reset) */ + PDS_RST_EVENT_PDS_RST, /*!< pds_rst_n (pds reset) */ + PDS_RST_EVENT_MAX, /*!< PDS rst event max number */ +} PDS_RST_EVENT_Type; + +/** + * @brief PDS PLL status type definition + */ +typedef enum { + PDS_PLL_STS_OFF = 0, /*!< 2'b00 */ + PDS_PLL_STS_SFREG = 1, /*!< 2'b01 */ + PDS_PLL_STS_PU = 2, /*!< 2'b10 */ + PDS_PLL_STS_RDY = 3, /*!< 2'b11 */ +} PDS_PLL_STS_Type; + +/** + * @brief PDS RF status type definition + */ +typedef enum { + PDS_RF_STS_OFF = 0, /*!< 4'b0000 */ + PDS_RF_STS_PU_MBG = 1, /*!< 4'b0001 */ + PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */ + PDS_RF_STS_PU_SFREG = 7, /*!< 4'b0111 */ + PDS_RF_STS_BZ_EN_AON = 15, /*!< 4'b1111 */ +} PDS_RF_STS_Type; + +/** + * @brief PDS status type definition + */ +typedef enum { + PDS_STS_IDLE = 0, /*!< 4'b0000 */ + PDS_STS_ECG = 8, /*!< 4'b1000 */ + PDS_STS_ERST = 12, /*!< 4'b1100 */ + PDS_STS_EISO = 15, /*!< 4'b1111 */ + PDS_STS_POFF = 7, /*!< 4'b0111 */ + PDS_STS_PRE_BGON = 3, /*!< 4'b0011 */ + PDS_STS_PRE_BGON1 = 1, /*!< 4'b0001 */ + PDS_STS_BGON = 5, /*!< 4'b0101 */ + PDS_STS_CLK_SW_32M = 4, /*!< 4'b0100 */ + PDS_STS_PON_DCDC = 6, /*!< 4'b0110 */ + PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */ + PDS_STS_PON = 10, /*!< 4'b1010 */ + PDS_STS_DISO = 2, /*!< 4'b0010 */ + PDS_STS_DCG = 13, /*!< 4'b1101 */ + PDS_STS_DRST = 11, /*!< 4'b1011 */ + PDS_STS_WAIT_EFUSE = 9, /*!< 4'b1001 */ +} PDS_STS_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + PDS_PLL_XTAL_NONE, /*!< XTAL is none */ + PDS_PLL_XTAL_32M, /*!< XTAL is 32M */ + PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ +} PDS_PLL_XTAL_Type; + +/** + * @brief PLL output clock type definition + */ +typedef enum { + PDS_PLL_CLK_480M, /*!< PLL output clock:480M */ + PDS_PLL_CLK_240M, /*!< PLL output clock:240M */ + PDS_PLL_CLK_192M, /*!< PLL output clock:192M */ + PDS_PLL_CLK_160M, /*!< PLL output clock:160M */ + PDS_PLL_CLK_120M, /*!< PLL output clock:120M */ + PDS_PLL_CLK_96M, /*!< PLL output clock:96M */ + PDS_PLL_CLK_80M, /*!< PLL output clock:80M */ + PDS_PLL_CLK_48M, /*!< PLL output clock:48M */ + PDS_PLL_CLK_32M, /*!< PLL output clock:32M */ +} PDS_PLL_CLK_Type; + +/** + * @brief PDS level 0-7 mode HBN GPIO interrupt trigger type definition + */ +typedef enum { + PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync falling edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync rising edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync low level trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync high level trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async falling edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async rising edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async low level trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async high level trigger */ +} PDS_AON_GPIO_INT_Trigger_Type; + +/** + * @brief PDS APP configuration type definition + */ +typedef struct +{ + uint8_t pdsLevel; /*!< PDS level */ + uint8_t turnOffXtal32m; /*!< Wheather turn off XTAL32M */ + uint8_t turnOffDll; /*!< Wheather turn off DLL */ + uint8_t turnOffRF; /*!< Wheather turn off RF */ + uint8_t useXtal32k; /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */ + uint8_t pdsAonGpioWakeupSrc; /*!< PDS level 0-7,31 mode aon GPIO Wakeup source(HBN wakeup pin) */ + PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0-7,31 mode aon GPIO Triger type(HBN wakeup pin) */ + uint8_t powerDownFlash; /*!< Whether power down flash */ + uint8_t pdsHoldGpio; /*!< Whether pds hold gpio level */ + uint8_t turnOffFlashPad; /*!< Whether turn off flash pad(GPIO17-GPIO22, GPIO23-GPIO28) */ + uint8_t flashPinCfg; /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */ + uint8_t turnoffPLL; /*!< Whether trun off PLL */ + uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ + uint8_t flashContRead; /*!< Whether enable flash continue read */ + uint32_t sleepTime; /*!< PDS sleep time */ + SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ + void (*preCbFun)(void); /*!< Pre callback function */ + void (*postCbFun)(void); /*!< Post callback function */ +} PDS_APP_CFG_Type; + +/** + * @brief PDS LDO voltage type definition + */ +typedef enum { + PDS_LDO_VOLTAGE_0P60V, /*!< PDS LDO voltage 0.60V */ + PDS_LDO_VOLTAGE_0P65V, /*!< PDS LDO voltage 0.65V */ + PDS_LDO_VOLTAGE_0P70V, /*!< PDS LDO voltage 0.70V */ + PDS_LDO_VOLTAGE_0P75V, /*!< PDS LDO voltage 0.75V */ + PDS_LDO_VOLTAGE_0P80V, /*!< PDS LDO voltage 0.80V */ + PDS_LDO_VOLTAGE_0P85V, /*!< PDS LDO voltage 0.85V */ + PDS_LDO_VOLTAGE_0P90V, /*!< PDS LDO voltage 0.9V */ + PDS_LDO_VOLTAGE_0P95V, /*!< PDS LDO voltage 0.95V */ + PDS_LDO_VOLTAGE_1P00V, /*!< PDS LDO voltage 1.0V */ + PDS_LDO_VOLTAGE_1P05V, /*!< PDS LDO voltage 1.05V */ + PDS_LDO_VOLTAGE_1P10V, /*!< PDS LDO voltage 1.1V */ + PDS_LDO_VOLTAGE_1P15V, /*!< PDS LDO voltage 1.15V */ + PDS_LDO_VOLTAGE_1P20V, /*!< PDS LDO voltage 1.2V */ + PDS_LDO_VOLTAGE_1P25V, /*!< PDS LDO voltage 1.25V */ + PDS_LDO_VOLTAGE_1P30V, /*!< PDS LDO voltage 1.3V */ + PDS_LDO_VOLTAGE_1P35V, /*!< PDS LDO voltage 1.35V */ +} PDS_LDO_VOLTAGE_Type; + +/** + * @brief PDS auto power down configuration type definition + */ +typedef struct +{ + BL_Fun_Type mbgPower; /*!< PDS auto [31] MBG power */ + BL_Fun_Type ldo18rfPower; /*!< PDS auto [30] LDO18RF power */ + BL_Fun_Type sfregPower; /*!< PDS auto [29] SF_REG power */ + BL_Fun_Type pllPower; /*!< PDS auto [28] PLL power */ + BL_Fun_Type cpu0Power; /*!< PDS auto [19] NP power */ + BL_Fun_Type rc32mPower; /*!< PDS auto [17] RC32M power */ + BL_Fun_Type xtalPower; /*!< PDS auto [14] XTAL power */ + BL_Fun_Type allPower; /*!< PDS auto [13] all power */ + BL_Fun_Type isoPower; /*!< PDS auto [11] ISO power */ + BL_Fun_Type bzPower; /*!< PDS auto [10] BZ power */ + BL_Fun_Type sramDisStanby; /*!< PDS auto [9] SRAM memory stanby disable */ + BL_Fun_Type cgPower; /*!< PDS auto [8] CG power */ + BL_Fun_Type cpu1Power; /*!< PDS auto [7] AP power */ + BL_Fun_Type usbPower; /*!< PDS auto [3] USB power */ +} PDS_AUTO_POWER_DOWN_CFG_Type; + +/** + * @brief PDS auto configuration type definition + */ +typedef struct +{ + PDS_LDO_VOLTAGE_Type vddcoreVol; /*!< PDS auto [27:24] VDDCORE voltage, reference 0x4001F80C[27:24], recommended 0xA */ + BL_Fun_Type vddcoreVolEn; /*!< PDS auto [18] VDDCORE voltage enable bit */ + BL_Fun_Type cpu0NotNeedWFI; /*!< PDS auto [21] NP not need WFI to get in PDS mode */ + BL_Fun_Type cpu1NotNeedWFI; /*!< PDS auto [20] AP not need WFI to get in PDS mode */ + BL_Fun_Type busReset; /*!< PDS auto [16] bus reset bit, reset after wake up from PDS mode */ + BL_Fun_Type disIrqWakeUp; /*!< PDS auto [15] disable IRQ request to wake up from PDS mode, except PDS counter IRQ */ + BL_Fun_Type powerOffXtalForever; /*!< PDS auto [2] power off xtal after get in PDS mode, and never power on xtal after wake up */ + BL_Fun_Type sleepForever; /*!< PDS auto [1] sleep forever after get in PDS mode, need reset system to restart */ +} PDS_AUTO_NORMAL_CFG_Type; + +/** + * @brief PDS force type definition + */ +typedef enum { + PDS_FORCE_NP, /*!< PDS force NP */ + PDS_FORCE_RSV, /*!< rsv */ + PDS_FORCE_BZ, /*!< PDS force BZ */ + PDS_FORCE_USB, /*!< PDS force USB */ +} PDS_FORCE_Type; + +/** + * @brief PDS force type definition + */ +typedef enum { + AUDIO_PLL_12288000_HZ, /*!< PDS AUDIO PLL SET AS 12.288MHZ */ + AUDIO_PLL_11289600_HZ, /*!< PDS AUDIO PLL SET AS 11.2896HZ */ + AUDIO_PLL_5644800_HZ, /*!< PDS AUDIO PLL SET AS 2.822400HZ */ + AUDIO_PLL_24576000_HZ, /*!< PDS AUDIO PLL SET AS 24.576000MHZ */ + AUDIO_PLL_24000000_HZ, /*!< PDS AUDIO PLL SET AS 24.000000MHZ */ +} PDS_AUDIO_PLL_Type; + +/*@} end of group PDS_Public_Types */ + +/** @defgroup PDS_Public_Constants + * @{ + */ + +/** @defgroup PDS_LDO_LEVEL_TYPE + * @{ + */ +#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \ + ((type) == PDS_LDO_LEVEL_0P65V) || \ + ((type) == PDS_LDO_LEVEL_0P70V) || \ + ((type) == PDS_LDO_LEVEL_0P75V) || \ + ((type) == PDS_LDO_LEVEL_0P80V) || \ + ((type) == PDS_LDO_LEVEL_0P85V) || \ + ((type) == PDS_LDO_LEVEL_0P90V) || \ + ((type) == PDS_LDO_LEVEL_0P95V) || \ + ((type) == PDS_LDO_LEVEL_1P00V) || \ + ((type) == PDS_LDO_LEVEL_1P05V) || \ + ((type) == PDS_LDO_LEVEL_1P10V) || \ + ((type) == PDS_LDO_LEVEL_1P15V) || \ + ((type) == PDS_LDO_LEVEL_1P20V) || \ + ((type) == PDS_LDO_LEVEL_1P25V) || \ + ((type) == PDS_LDO_LEVEL_1P30V) || \ + ((type) == PDS_LDO_LEVEL_1P35V)) + +/** @defgroup PDS_PAD_PIN_TYPE + * @{ + */ +#define IS_PDS_PAD_PIN_TYPE(type) (((type) == PDS_PAD_PIN_GPIO_17) || \ + ((type) == PDS_PAD_PIN_GPIO_18) || \ + ((type) == PDS_PAD_PIN_GPIO_19) || \ + ((type) == PDS_PAD_PIN_GPIO_20) || \ + ((type) == PDS_PAD_PIN_GPIO_21) || \ + ((type) == PDS_PAD_PIN_GPIO_22) || \ + ((type) == PDS_PAD_PIN_GPIO_23) || \ + ((type) == PDS_PAD_PIN_GPIO_24) || \ + ((type) == PDS_PAD_PIN_GPIO_25) || \ + ((type) == PDS_PAD_PIN_GPIO_26) || \ + ((type) == PDS_PAD_PIN_GPIO_27) || \ + ((type) == PDS_PAD_PIN_GPIO_28)) + +/** @defgroup PDS_PAD_CFG_TYPE + * @{ + */ +#define IS_PDS_PAD_CFG_TYPE(type) (((type) == PDS_PAD_CFG_PULL_NONE) || \ + ((type) == PDS_PAD_CFG_PULL_DOWN) || \ + ((type) == PDS_PAD_CFG_PULL_UP) || \ + ((type) == PDS_PAD_CFG_ACTIVE_IE)) + +/** @defgroup PDS_INT_TYPE + * @{ + */ +#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) || \ + ((type) == PDS_INT_RF_DONE) || \ + ((type) == PDS_INT_PLL_DONE) || \ + ((type) == PDS_INT_PDS_SLEEP_CNT) || \ + ((type) == PDS_INT_HBN_IRQ_OUT0) || \ + ((type) == PDS_INT_HBN_IRQ_OUT1) || \ + ((type) == PDS_INT_GPIO_IRQ) || \ + ((type) == PDS_INT_IRRX) || \ + ((type) == PDS_INT_BLE_SLP_IRQ) || \ + ((type) == PDS_INT_USB_WKUP) || \ + ((type) == PDS_INT_KYS_QDEC) || \ + ((type) == PDS_INT_MAX)) + +/** @defgroup PDS_VDDCORE_GPIO_SRC_TYPE + * @{ + */ +#define IS_PDS_VDDCORE_GPIO_SRC_TYPE(type) (((type) == PDS_VDDCORE_GPIO_SRC_GPIO_0) || \ + ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_1) || \ + ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_2) || \ + ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_3) || \ + ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_4) || \ + ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_5) || \ + ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_6) || \ + ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_7)) + +/** @defgroup PDS_RST_EVENT_TYPE + * @{ + */ +#define IS_PDS_RST_EVENT_TYPE(type) (((type) == PDS_RST_EVENT_BUS_RST) || \ + ((type) == PDS_RST_EVENT_HBN_PWR_ON_RST) || \ + ((type) == PDS_RST_EVENT_PDS_RST) || \ + ((type) == PDS_RST_EVENT_MAX)) + +/** @defgroup PDS_PLL_STS_TYPE + * @{ + */ +#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) || \ + ((type) == PDS_PLL_STS_SFREG) || \ + ((type) == PDS_PLL_STS_PU) || \ + ((type) == PDS_PLL_STS_RDY)) + +/** @defgroup PDS_RF_STS_TYPE + * @{ + */ +#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) || \ + ((type) == PDS_RF_STS_PU_MBG) || \ + ((type) == PDS_RF_STS_PU_LDO15RF) || \ + ((type) == PDS_RF_STS_PU_SFREG) || \ + ((type) == PDS_RF_STS_BZ_EN_AON)) + +/** @defgroup PDS_STS_TYPE + * @{ + */ +#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) || \ + ((type) == PDS_STS_ECG) || \ + ((type) == PDS_STS_ERST) || \ + ((type) == PDS_STS_EISO) || \ + ((type) == PDS_STS_POFF) || \ + ((type) == PDS_STS_PRE_BGON) || \ + ((type) == PDS_STS_PRE_BGON1) || \ + ((type) == PDS_STS_BGON) || \ + ((type) == PDS_STS_CLK_SW_32M) || \ + ((type) == PDS_STS_PON_DCDC) || \ + ((type) == PDS_STS_PON_LDO11_MISC) || \ + ((type) == PDS_STS_PON) || \ + ((type) == PDS_STS_DISO) || \ + ((type) == PDS_STS_DCG) || \ + ((type) == PDS_STS_DRST) || \ + ((type) == PDS_STS_WAIT_EFUSE)) + +/** @defgroup PDS_PLL_XTAL_TYPE + * @{ + */ +#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \ + ((type) == PDS_PLL_XTAL_32M) || \ + ((type) == PDS_PLL_XTAL_RC32M)) + +/** @defgroup PDS_PLL_CLK_TYPE + * @{ + */ +#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \ + ((type) == PDS_PLL_CLK_240M) || \ + ((type) == PDS_PLL_CLK_192M) || \ + ((type) == PDS_PLL_CLK_160M) || \ + ((type) == PDS_PLL_CLK_120M) || \ + ((type) == PDS_PLL_CLK_96M) || \ + ((type) == PDS_PLL_CLK_80M) || \ + ((type) == PDS_PLL_CLK_48M) || \ + ((type) == PDS_PLL_CLK_32M)) + +/** @defgroup PDS_AON_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + +/** @defgroup PDS_LDO_VOLTAGE_TYPE + * @{ + */ +#define IS_PDS_LDO_VOLTAGE_TYPE(type) (((type) == PDS_LDO_VOLTAGE_0P60V) || \ + ((type) == PDS_LDO_VOLTAGE_0P65V) || \ + ((type) == PDS_LDO_VOLTAGE_0P70V) || \ + ((type) == PDS_LDO_VOLTAGE_0P75V) || \ + ((type) == PDS_LDO_VOLTAGE_0P80V) || \ + ((type) == PDS_LDO_VOLTAGE_0P85V) || \ + ((type) == PDS_LDO_VOLTAGE_0P90V) || \ + ((type) == PDS_LDO_VOLTAGE_0P95V) || \ + ((type) == PDS_LDO_VOLTAGE_1P00V) || \ + ((type) == PDS_LDO_VOLTAGE_1P05V) || \ + ((type) == PDS_LDO_VOLTAGE_1P10V) || \ + ((type) == PDS_LDO_VOLTAGE_1P15V) || \ + ((type) == PDS_LDO_VOLTAGE_1P20V) || \ + ((type) == PDS_LDO_VOLTAGE_1P25V) || \ + ((type) == PDS_LDO_VOLTAGE_1P30V) || \ + ((type) == PDS_LDO_VOLTAGE_1P35V)) + +/** @defgroup PDS_FORCE_TYPE + * @{ + */ +#define IS_PDS_FORCE_TYPE(type) (((type) == PDS_FORCE_NP) || \ + ((type) == PDS_FORCE_RSV) || \ + ((type) == PDS_FORCE_BZ) || \ + ((type) == PDS_FORCE_USB)) + +/** @defgroup PDS_AUDIO_PLL_TYPE + * @{ + */ +#define IS_PDS_AUDIO_PLL_TYPE(type) (((type) == AUDIO_PLL_12288000_HZ) || \ + ((type) == AUDIO_PLL_11289600_HZ) || \ + ((type) == AUDIO_PLL_5644800_HZ)) + +/*@} end of group PDS_Public_Constants */ + +/** @defgroup PDS_Public_Macros + * @{ + */ +#define PDS_LDO_MIN_PU_CNT (25) /* LDO need 25 cycles to power up */ +#define PDS_WARMUP_CNT (38) /* LDO hw warmup compensation latency cycles */ +#define PDS_WARMUP_LATENCY_CNT (38) /* LDO hw warmup compensation latency cycles */ +#define PDS_FORCE_PWR_OFF_OFFSET (0) +#define PDS_FORCE_ISO_EN_OFFSET (4) +#define PDS_FORCE_PDS_RST_OFFSET (8) +#define PDS_FORCE_MEM_STBY_OFFSET (12) +#define PDS_FORCE_GATE_CLK_OFFSET (16) +#define PDS_INT_MASK_BIT_OFFSET (8) +#define PDS_AON_WAKEUP_GPIO_NONE (0x00) +#define PDS_AON_WAKEUP_GPIO_9 (0x01) +#define PDS_AON_WAKEUP_GPIO_10 (0x02) +#define PDS_AON_WAKEUP_GPIO_11 (0x04) +#define PDS_AON_WAKEUP_GPIO_12 (0x08) +#define PDS_AON_WAKEUP_GPIO_13 (0x10) +#define PDS_AON_WAKEUP_GPIO_ALL (0x1E) + +/*@} end of group PDS_Public_Macros */ + +/** @defgroup PDS_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void PDS_WAKEUP_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg); +BL_Err_Type PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg); +/*----------*/ +BL_Err_Type PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt); +BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3); +BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt); +/*----------*/ +BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable); +BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask); +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType); +BL_Err_Type PDS_IntClear(void); +PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void); +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void); +PDS_STS_Type PDS_Get_PdsStstus(void); +/*----------*/ +BL_Err_Type PDS_Clear_Reset_Event(void); +BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event); +/*----------*/ +BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src, + PDS_AON_GPIO_INT_Trigger_Type mode); +BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask); +PDS_STS_Type PDS_Get_Vddcore_GPIO_IntStatus(void); +BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void); +/*----------*/ +BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void); +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type PDS_Trim_RC32M(void); +BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void); +BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void); +BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType); +BL_Err_Type PDS_Enable_PLL_All_Clks(void); +BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk); +BL_Err_Type PDS_Disable_PLL_All_Clks(void); +BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk); +BL_Err_Type PDS_Power_Off_PLL(void); +BL_Err_Type PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq); +/*----------*/ +void PDS_Reset(void); +void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt); +void PDS_Auto_Time_Config(uint32_t sleepDuration); +void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable); +void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain); +void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain); +/*----------*/; + +/*@} end of group PDS_Public_Functions */ + +/*@} end of group PDS */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_PDS_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_psram.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_psram.h new file mode 100644 index 0000000000000000000000000000000000000000..5f9a78b12499c25f45fa6a14b938ecdee3b5e81a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_psram.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file bl702_psram.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_PSRAM_H__ +#define __BL702_PSRAM_H__ + +#include "sf_ctrl_reg.h" +#include "bl702_common.h" +#include "bl702_sf_ctrl.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup PSRAM + * @{ + */ + +/** @defgroup PSRAM_Public_Types + * @{ + */ + +/** + * @brief Psram drive strength type definition + */ +typedef enum { + PSRAM_DRIVE_STRENGTH_50_OHMS, /*!< Drive strength 50 ohms(default) */ + PSRAM_DRIVE_STRENGTH_100_OHMS, /*!< Drive strength 100 ohms */ + PSRAM_DRIVE_STRENGTH_200_OHMS, /*!< Drive strength 200 ohms */ +} PSRAM_Drive_Strength; + +/** + * @brief Psram burst length size type definition + */ +typedef enum { + PSRAM_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */ + PSRAM_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */ + PSRAM_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */ + PSRAM_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 bytes(default) */ +} PSRAM_Burst_Length; + +/** + * @brief Psram ctrl mode type definition + */ +typedef enum { + PSRAM_SPI_CTRL_MODE, /*!< Psram SPI ctrl mode */ + PSRAM_QPI_CTRL_MODE, /*!< Psram QPI ctrl mode */ +} PSRAM_Ctrl_Mode; + +/** + * @brief Psram ctrl configuration structure type definition + */ +typedef struct +{ + uint8_t readIdCmd; /*!< Read ID command */ + uint8_t readIdDmyClk; /*!< Read ID command dummy clock */ + uint8_t burstToggleCmd; /*!< Burst toggle length command */ + uint8_t resetEnableCmd; /*!< Psram reset enable command */ + uint8_t resetCmd; /*!< Psram reset command */ + uint8_t enterQuadModeCmd; /*!< Psram enter quad mode command */ + uint8_t exitQuadModeCmd; /*!< Psram exit quad mode command */ + uint8_t readRegCmd; /*!< Read register command */ + uint8_t readRegDmyClk; /*!< Read register command dummy clock */ + uint8_t writeRegCmd; /*!< Write register command */ + uint8_t readCmd; /*!< Psram read command */ + uint8_t readDmyClk; /*!< Psram read command dummy clock */ + uint8_t fReadCmd; /*!< Psram fast read command */ + uint8_t fReadDmyClk; /*!< Psram fast read command dummy clock */ + uint8_t fReadQuadCmd; /*!< Psram fast read quad command */ + uint8_t fReadQuadDmyClk; /*!< Psram fast read quad command dummy clock */ + uint8_t writeCmd; /*!< Psram write command */ + uint8_t quadWriteCmd; /*!< Psram quad write command */ + uint16_t pageSize; /*!< Psram page size */ + PSRAM_Ctrl_Mode ctrlMode; /*!< Psram ctrl mode */ + PSRAM_Drive_Strength driveStrength; /*!< Psram drive strength */ + PSRAM_Burst_Length burstLength; /*!< Psram burst length size */ +} SPI_Psram_Cfg_Type; + +/*@} end of group PSRAM_Public_Types */ + +/** @defgroup PSRAM_Public_Constants + * @{ + */ + +/** @defgroup PSRAM_DRIVE_STRENGTH + * @{ + */ +#define IS_PSRAM_DRIVE_STRENGTH(type) (((type) == PSRAM_DRIVE_STRENGTH_50_OHMS) || \ + ((type) == PSRAM_DRIVE_STRENGTH_100_OHMS) || \ + ((type) == PSRAM_DRIVE_STRENGTH_200_OHMS)) + +/** @defgroup PSRAM_BURST_LENGTH + * @{ + */ +#define IS_PSRAM_BURST_LENGTH(type) (((type) == PSRAM_BURST_LENGTH_16_BYTES) || \ + ((type) == PSRAM_BURST_LENGTH_32_BYTES) || \ + ((type) == PSRAM_BURST_LENGTH_64_BYTES) || \ + ((type) == PSRAM_BURST_LENGTH_512_BYTES)) + +/** @defgroup PSRAM_CTRL_MODE + * @{ + */ +#define IS_PSRAM_CTRL_MODE(type) (((type) == PSRAM_SPI_CTRL_MODE) || \ + ((type) == PSRAM_QPI_CTRL_MODE)) + +/*@} end of group PSRAM_Public_Constants */ + +/** @defgroup PSRAM_Public_Macros + * @{ + */ + +/*@} end of group PSRAM_Public_Macros */ + +/** @defgroup PSRAM_Public_Functions + * @{ + */ + +/** + * @brief PSRAM Functions + */ +void Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg); +void Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue); +void Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue); +BL_Err_Type Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg); +BL_Err_Type Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg); +void Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data); +BL_Err_Type Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg); +BL_Err_Type Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg); +BL_Err_Type Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode); +BL_Err_Type Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode); +BL_Err_Type Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len); +BL_Err_Type Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn, + BL_Fun_Type wbEn, BL_Fun_Type waEn); +BL_Err_Type Psram_Write(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type Psram_Read(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); + +/*@} end of group PSRAM_Public_Functions */ + +/*@} end of group PSRAM */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_PSRAM_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pwm.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..02e571cc7b7ac2e3349e77922ddc304b25832572 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pwm.h @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file bl702_pwm.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_PWM_H__ +#define __BL702_PWM_H__ + +#include "pwm_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup PWM + * @{ + */ + +/** @defgroup PWM_Public_Types + * @{ + */ + +/** + * @brief PWM No. type definition + */ +typedef enum { + PWM_CH0 = 0, /*!< PWM Channel 0 define */ + PWM_CH1, /*!< PWM Channel 1 define */ + PWM_CH2, /*!< PWM Channel 2 define */ + PWM_CH3, /*!< PWM Channel 3 define */ + PWM_CH4, /*!< PWM Channel 4 define */ + PWM_CH_MAX, /*!< */ +} PWM_CH_ID_Type; + +/** + * @brief PWM Clock definition + */ +typedef enum { + PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */ + PWM_CLK_BCLK, /*!< PWM Clock source :Bus CLK */ + PWM_CLK_32K, /*!< PWM Clock source :32K CLK */ +} PWM_Clk_Type; + +/** + * @brief PWM Stop Mode definition + */ +typedef enum { + PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */ + PWM_STOP_GRACEFUL, /*!< PWM stop graceful select define */ +} PWM_Stop_Mode_Type; + +/** + * @brief PWM mode type def + */ +typedef enum { + PWM_POL_NORMAL = 0, /*!< PWM normal polarity mode define */ + PWM_POL_INVERT, /*!< PWM invert polarity mode define */ +} PWM_Polarity_Type; + +/** + * @brief PWM interrupt type def + */ +typedef enum { + PWM_INT_PULSE_CNT = 0, /*!< PWM Pulse count interrupt define */ + PWM_INT_ALL, /*!< */ +} PWM_INT_Type; + +/** + * @brief PWM configuration structure type definition + */ +typedef struct +{ + PWM_CH_ID_Type ch; /*!< PWM channel */ + PWM_Clk_Type clk; /*!< PWM Clock */ + PWM_Stop_Mode_Type stopMode; /*!< PWM Stop Mode */ + PWM_Polarity_Type pol; /*!< PWM mode type */ + uint16_t clkDiv; /*!< PWM clkDiv num */ + uint16_t period; /*!< PWM period set */ + uint16_t threshold1; /*!< PWM threshold1 num */ + uint16_t threshold2; /*!< PWM threshold2 num */ + uint16_t intPulseCnt; /*!< PWM interrupt pulse count */ +} PWM_CH_CFG_Type; + +/*@} end of group PWM_Public_Types */ + +/** @defgroup PWM_Public_Constants + * @{ + */ + +/** @defgroup PWM_CH_ID_TYPE + * @{ + */ +#define IS_PWM_CH_ID_TYPE(type) (((type) == PWM_CH0) || \ + ((type) == PWM_CH1) || \ + ((type) == PWM_CH2) || \ + ((type) == PWM_CH3) || \ + ((type) == PWM_CH4) || \ + ((type) == PWM_CH_MAX)) + +/** @defgroup PWM_CLK_TYPE + * @{ + */ +#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK) || \ + ((type) == PWM_CLK_BCLK) || \ + ((type) == PWM_CLK_32K)) + +/** @defgroup PWM_STOP_MODE_TYPE + * @{ + */ +#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT) || \ + ((type) == PWM_STOP_GRACEFUL)) + +/** @defgroup PWM_POLARITY_TYPE + * @{ + */ +#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_NORMAL) || \ + ((type) == PWM_POL_INVERT)) + +/** @defgroup PWM_INT_TYPE + * @{ + */ +#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_PULSE_CNT) || \ + ((type) == PWM_INT_ALL)) + +/*@} end of group PWM_Public_Constants */ + +/** @defgroup PWM_Public_Macros + * @{ + */ +#define IS_PWM_CH(CH) ((CH) < PWM_CH_MAX) + +/*@} end of group PWM_Public_Macros */ + +/** @defgroup PWM_Public_Functions + * @{ + */ + +/** + * @brief PWM Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void PWM_IRQHandler(void); +#endif +BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg); +void PWM_Channel_Update(PWM_CH_ID_Type ch, uint16_t period, uint16_t threshold1, uint16_t threshold2); +void PWM_Channel_Set_Div(PWM_CH_ID_Type ch, uint16_t div); +void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch, uint16_t threshold1); +void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch, uint16_t threshold2); +void PWM_Channel_Set_Period(PWM_CH_ID_Type ch, uint16_t period); +void PWM_Channel_Get(PWM_CH_ID_Type ch, uint16_t *period, uint16_t *threshold1, uint16_t *threshold2); +void PWM_IntMask(PWM_CH_ID_Type ch, PWM_INT_Type intType, BL_Mask_Type intMask); +void PWM_Channel_Enable(PWM_CH_ID_Type ch); +void PWM_Channel_Disable(PWM_CH_ID_Type ch); +void PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable); +void PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value); +void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun); +BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle); + + +/*@} end of group PWM_Public_Functions */ + +/*@} end of group PWM */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_PWM_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_qdec.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_qdec.h new file mode 100644 index 0000000000000000000000000000000000000000..6a00945b87a5949628390a764ea09369ce2fc379 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_qdec.h @@ -0,0 +1,283 @@ +/** + ****************************************************************************** + * @file bl702_qdec.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_QDEC_H__ +#define __BL702_QDEC_H__ + +#include "qdec_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup QDEC + * @{ + */ + +/** @defgroup QDEC_Public_Types + * @{ + */ + +/** + * @brief QDEC port type definition + */ +typedef enum { + QDEC0_ID, /*!< QDEC0 port define */ + QDEC1_ID, /*!< QDEC1 port define */ + QDEC2_ID, /*!< QDEC2 port define */ + QDEC_ID_MAX, /*!< QDEC MAX ID define */ +} QDEC_ID_Type; + +/** + * @brief QDEC sample work mode type definition + */ +typedef enum { + QDEC_SAMPLE_SINGLE_MOD, /*!< Stop sample if rpt_rdy */ + QDEC_SAMPLE_CONTINUE_MOD, /*!< Continue sample */ +} QDEC_SAMPLE_MODE_Type; + +/** + * @brief QDEC sample period type definition + */ +typedef enum { + QDEC_SAMPLE_PERIOD_32US, /*!< 32 us at clock 1MHz */ + QDEC_SAMPLE_PERIOD_64US, /*!< 64 us at clock 1MHz */ + QDEC_SAMPLE_PERIOD_128US, /*!< 128 us at clock 1MHz */ + QDEC_SAMPLE_PERIOD_256US, /*!< 256 us at clock 1MHz */ + QDEC_SAMPLE_PERIOD_512US, /*!< 512 us at clock 1MHz */ + QDEC_SAMPLE_PERIOD_1MS, /*!< 1 ms at clock 1MHz */ + QDEC_SAMPLE_PERIOD_2MS, /*!< 2 ms at clock 1MHz */ + QDEC_SAMPLE_PERIOD_4MS, /*!< 4 ms at clock 1MHz */ + QDEC_SAMPLE_PERIOD_8MS, /*!< 8 ms at clock 1MHz */ + QDEC_SAMPLE_PERIOD_16MS, /*!< 16 ms at clock 1MHz */ + QDEC_SAMPLE_PERIOD_32MS, /*!< 32 ms at clock 1MHz */ + QDEC_SAMPLE_PERIOD_65MS, /*!< 65 ms at clock 1MHz */ + QDEC_SAMPLE_PERIOD_131MS, /*!< 131 ms at clock 1MHz */ +} QDEC_SAMPLE_PERIOD_Type; + +/** + * @brief QDEC report work mode type definition + */ +typedef enum { + QDEC_REPORT_SAMPLE_CHANGE_MOD, /*!< Count time only if sample change */ + QDEC_REPORT_TIME_MOD, /*!< Continue time */ +} QDEC_REPORT_MODE_Type; + +/** + * @brief QDEC sample config structure type definition + */ +typedef struct +{ + QDEC_SAMPLE_MODE_Type sampleMod; /*!< Sample work mode */ + QDEC_SAMPLE_PERIOD_Type samplePeriod; /*!< Sample period time */ +} QDEC_SAMPLE_Type; + +/** + * @brief QDEC report config structure type definition + */ +typedef struct +{ + QDEC_REPORT_MODE_Type reportMod; /*!< Report work mode */ + uint16_t reportPeriod; /*!< RPT_US report period in [us/report] = SP * RP */ +} QDEC_REPORT_Type; + +/** + * @brief QDEC acc work mode type definition + */ +typedef enum { + QDEC_ACC_STOP_SAMPLE_IF_OVERFLOW, /*!< Stop accumulate if overflow */ + QDEC_ACC_CONTINUE_ACCUMULATE, /*!< Continue accumulate */ +} QDEC_ACC_MODE_Type; + +/** + * @brief QDEC led config structure type definition + */ +typedef struct +{ + BL_Fun_Type ledEn; /*!< LED enable */ + BL_Fun_Type ledSwap; /*!< LED on/off polarity swap */ + uint16_t ledPeriod; /*!< Period in us the LED is switched on prior to sampling */ +} QDEC_LED_Type; + +/** + * @brief QDEC deglitch config structure type definition + */ +typedef struct +{ + BL_Fun_Type deglitchEn; /*!< deglitch enable */ + uint8_t deglitchStrength; /*!< deglitch strength */ +} QDEC_DEGLITCH_Type; + +/** + * @brief QDEC config structure type definition + */ +typedef struct +{ + QDEC_SAMPLE_Type sampleCfg; /*!< QDEC sample config structure */ + QDEC_REPORT_Type reportCfg; /*!< QDEC report config structure */ + QDEC_ACC_MODE_Type accMod; /*!< QDEC acc mode config */ + QDEC_LED_Type ledCfg; /*!< QDEC led config structure */ + QDEC_DEGLITCH_Type deglitchCfg; /*!< QDEC deglitch config structure */ +} QDEC_CFG_Type; + +/** + * @brief QDEC direction type definition + */ +typedef enum { + QDEC_DIRECTION_NO_CHANGE, /*!< Direction of last change no change */ + QDEC_DIRECTION_CLOCKWISE, /*!< Direction of last change clockwise */ + QDEC_DIRECTION_COUNTER_CLOCKWISE, /*!< Direction of last change counter-clockwise */ + QDEC_DIRECTION_ERROR, /*!< Direction of last change error */ +} QDEC_DIRECTION_Type; + +/** + * @brief QDEC interrupt type definition + */ +typedef enum { + QDEC_INT_REPORT, /*!< report interrupt */ + QDEC_INT_SAMPLE, /*!< sample interrupt */ + QDEC_INT_ERROR, /*!< error interrupt */ + QDEC_INT_OVERFLOW, /*!< ACC1 and ACC2 overflow interrupt */ + QDEC_INT_ALL, /*!< interrupt max num */ +} QDEC_INT_Type; + +/*@} end of group QDEC_Public_Types */ + +/** @defgroup QDEC_Public_Constants + * @{ + */ + +/** @defgroup QDEC_ID_TYPE + * @{ + */ +#define IS_QDEC_ID_TYPE(type) (((type) == QDEC0_ID) || \ + ((type) == QDEC1_ID) || \ + ((type) == QDEC2_ID) || \ + ((type) == QDEC_ID_MAX)) + +/** @defgroup QDEC_SAMPLE_MODE_TYPE + * @{ + */ +#define IS_QDEC_SAMPLE_MODE_TYPE(type) (((type) == QDEC_SAMPLE_SINGLE_MOD) || \ + ((type) == QDEC_SAMPLE_CONTINUE_MOD)) + +/** @defgroup QDEC_SAMPLE_PERIOD_TYPE + * @{ + */ +#define IS_QDEC_SAMPLE_PERIOD_TYPE(type) (((type) == QDEC_SAMPLE_PERIOD_32US) || \ + ((type) == QDEC_SAMPLE_PERIOD_64US) || \ + ((type) == QDEC_SAMPLE_PERIOD_128US) || \ + ((type) == QDEC_SAMPLE_PERIOD_256US) || \ + ((type) == QDEC_SAMPLE_PERIOD_512US) || \ + ((type) == QDEC_SAMPLE_PERIOD_1MS) || \ + ((type) == QDEC_SAMPLE_PERIOD_2MS) || \ + ((type) == QDEC_SAMPLE_PERIOD_4MS) || \ + ((type) == QDEC_SAMPLE_PERIOD_8MS) || \ + ((type) == QDEC_SAMPLE_PERIOD_16MS) || \ + ((type) == QDEC_SAMPLE_PERIOD_32MS) || \ + ((type) == QDEC_SAMPLE_PERIOD_65MS) || \ + ((type) == QDEC_SAMPLE_PERIOD_131MS)) + +/** @defgroup QDEC_REPORT_MODE_TYPE + * @{ + */ +#define IS_QDEC_REPORT_MODE_TYPE(type) (((type) == QDEC_REPORT_SAMPLE_CHANGE_MOD) || \ + ((type) == QDEC_REPORT_TIME_MOD)) + +/** @defgroup QDEC_ACC_MODE_TYPE + * @{ + */ +#define IS_QDEC_ACC_MODE_TYPE(type) (((type) == QDEC_ACC_STOP_SAMPLE_IF_OVERFLOW) || \ + ((type) == QDEC_ACC_CONTINUE_ACCUMULATE)) + +/** @defgroup QDEC_DIRECTION_TYPE + * @{ + */ +#define IS_QDEC_DIRECTION_TYPE(type) (((type) == QDEC_DIRECTION_NO_CHANGE) || \ + ((type) == QDEC_DIRECTION_CLOCKWISE) || \ + ((type) == QDEC_DIRECTION_COUNTER_CLOCKWISE) || \ + ((type) == QDEC_DIRECTION_ERROR)) + +/** @defgroup QDEC_INT_TYPE + * @{ + */ +#define IS_QDEC_INT_TYPE(type) (((type) == QDEC_INT_REPORT) || \ + ((type) == QDEC_INT_SAMPLE) || \ + ((type) == QDEC_INT_ERROR) || \ + ((type) == QDEC_INT_OVERFLOW) || \ + ((type) == QDEC_INT_ALL)) + +/*@} end of group QDEC_Public_Constants */ + +/** @defgroup QDEC_Public_Macros + * @{ + */ + +/*@} end of group QDEC_Public_Macros */ + +/** @defgroup QDEC_Public_Functions + * @{ + */ + +/** + * @brief QDEC Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void QDEC0_IRQHandler(void); +void QDEC1_IRQHandler(void); +void QDEC2_IRQHandler(void); +#endif +void QDEC_Init(QDEC_ID_Type qdecId, QDEC_CFG_Type *qdecCfg); +void QDEC_DeInit(QDEC_ID_Type qdecId); +void QDEC_Enable(QDEC_ID_Type qdecId); +void QDEC_Disable(QDEC_ID_Type qdecId); +void QDEC_SetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType, BL_Mask_Type intMask); +BL_Mask_Type QDEC_GetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType); +void QDEC_Int_Callback_Install(QDEC_ID_Type qdecId, QDEC_INT_Type intType, intCallback_Type *cbFun); +BL_Sts_Type QDEC_Get_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType); +void QDEC_Clr_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType); +QDEC_DIRECTION_Type QDEC_Get_Sample_Direction(QDEC_ID_Type qdecId); +uint8_t QDEC_Get_Err_Cnt(QDEC_ID_Type qdecId); +uint16_t QDEC_Get_Sample_Val(QDEC_ID_Type qdecId); +void QDEC_IntHandler(QDEC_ID_Type qdecId, QDEC_INT_Type intType); + +/*@} end of group QDEC_Public_Functions */ + +/*@} end of group QDEC */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_QDEC_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_romdriver.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_romdriver.h new file mode 100644 index 0000000000000000000000000000000000000000..9f1439b04bdff3def48b78337015e63dd01bae87 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_romdriver.h @@ -0,0 +1,632 @@ +/** + ****************************************************************************** + * @file bl702_romdriver.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_ROMDRIVER_H__ +#define __BL702_ROMDRIVER_H__ + +#include "bl702_common.h" +#include "bl702_aon.h" +#include "bl702_glb.h" +#include "bl702_hbn.h" +#include "bl702_xip_sflash.h" +#include "bl702_sflash.h" +#include "bl702_sf_ctrl.h" +#include "bl702_psram.h" +#include "softcrc.h" + +#define ROMAPI_INDEX_SECT_SIZE (0x800) +#define ROMAPI_INDEX_MAX (ROMAPI_INDEX_SECT_SIZE / 4 - 1) + +typedef enum { + ROM_API_INDEX_REV = 0, + + ROM_API_INDEX_FUNC_START = 4, + + ROM_API_INDEX_AON_Power_On_MBG = ROM_API_INDEX_FUNC_START, + ROM_API_INDEX_AON_Power_Off_MBG, + ROM_API_INDEX_AON_Power_On_XTAL, + ROM_API_INDEX_AON_Set_Xtal_CapCode, + ROM_API_INDEX_AON_Power_Off_XTAL, + + ROM_API_INDEX_ASM_Delay_Us, + ROM_API_INDEX_BL702_Delay_US, + ROM_API_INDEX_BL702_Delay_MS, + ROM_API_INDEX_BL702_MemCpy, + ROM_API_INDEX_BL702_MemCpy4, + ROM_API_INDEX_BL702_MemCpy_Fast, + ROM_API_INDEX_ARCH_MemCpy_Fast, + ROM_API_INDEX_BL702_MemSet, + ROM_API_INDEX_BL702_MemSet4, + ROM_API_INDEX_BL702_MemCmp, + ROM_API_INDEX_BFLB_Soft_CRC32, + + ROM_API_INDEX_GLB_Get_Root_CLK_Sel, + ROM_API_INDEX_GLB_Set_System_CLK_Div, + ROM_API_INDEX_GLB_Get_BCLK_Div, + ROM_API_INDEX_GLB_Get_HCLK_Div, + ROM_API_INDEX_Update_SystemCoreClockWith_XTAL, + ROM_API_INDEX_GLB_Set_System_CLK, + ROM_API_INDEX_System_Core_Clock_Update_From_RC32M, + ROM_API_INDEX_GLB_Set_SF_CLK, + ROM_API_INDEX_GLB_Power_Off_DLL, + ROM_API_INDEX_GLB_Power_On_DLL, + ROM_API_INDEX_GLB_Enable_DLL_All_Clks, + ROM_API_INDEX_GLB_Enable_DLL_Clk, + ROM_API_INDEX_GLB_Disable_DLL_All_Clks, + ROM_API_INDEX_GLB_Disable_DLL_Clk, + ROM_API_INDEX_GLB_SW_System_Reset, + ROM_API_INDEX_GLB_SW_CPU_Reset, + ROM_API_INDEX_GLB_SW_POR_Reset, + ROM_API_INDEX_GLB_Select_Internal_Flash, + ROM_API_INDEX_GLB_Swap_Flash_Pin, + ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin, + ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin, + ROM_API_INDEX_GLB_Select_Internal_PSram, + ROM_API_INDEX_GLB_GPIO_Init, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable, + ROM_API_INDEX_GLB_GPIO_Set_HZ, + ROM_API_INDEX_GLB_Deswap_Flash_Pin, + ROM_API_INDEX_GLB_Select_External_Flash, + ROM_API_INDEX_GLB_GPIO_Get_Fun, + + ROM_API_INDEX_EF_Ctrl_Busy, + ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0, + ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0, + ROM_API_INDEX_EF_Ctrl_Clear, + ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity, + ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim, + ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim, + + ROM_API_INDEX_PDS_Trim_RC32M, + ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref, + ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref, + ROM_API_INDEX_PDS_Power_On_PLL, + ROM_API_INDEX_PDS_Enable_PLL_All_Clks, + ROM_API_INDEX_PDS_Disable_PLL_All_Clks, + ROM_API_INDEX_PDS_Enable_PLL_Clk, + ROM_API_INDEX_PDS_Disable_PLL_Clk, + ROM_API_INDEX_PDS_Power_Off_PLL, + ROM_API_INDEX_PDS_Reset, + ROM_API_INDEX_PDS_Enable, + ROM_API_INDEX_PDS_Auto_Time_Config, + ROM_API_INDEX_PDS_Auto_Enable, + ROM_API_INDEX_PDS_Manual_Force_Turn_Off, + ROM_API_INDEX_PDS_Manual_Force_Turn_On, + + ROM_API_INDEX_HBN_Enable, + ROM_API_INDEX_HBN_Reset, + ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg, + ROM_API_INDEX_HBN_Trim_RC32K, + ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel, + + ROM_API_INDEX_XIP_SFlash_State_Save, + ROM_API_INDEX_XIP_SFlash_State_Restore, + ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Write_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_With_Lock, + ROM_API_INDEX_XIP_SFlash_Write_With_Lock, + ROM_API_INDEX_XIP_SFlash_Erase_With_Lock, + + ROM_API_INDEX_SFlash_Init, + ROM_API_INDEX_SFlash_SetSPIMode, + ROM_API_INDEX_SFlash_Read_Reg, + ROM_API_INDEX_SFlash_Write_Reg, + ROM_API_INDEX_SFlash_Read_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Write_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Busy, + ROM_API_INDEX_SFlash_Write_Enable, + ROM_API_INDEX_SFlash_Qspi_Enable, + ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable, + ROM_API_INDEX_SFlash_Chip_Erase, + ROM_API_INDEX_SFlash_Sector_Erase, + ROM_API_INDEX_SFlash_Blk32_Erase, + ROM_API_INDEX_SFlash_Blk64_Erase, + ROM_API_INDEX_SFlash_Erase, + ROM_API_INDEX_SFlash_Program, + ROM_API_INDEX_SFlash_GetUniqueId, + ROM_API_INDEX_SFlash_GetJedecId, + ROM_API_INDEX_SFlash_GetDeviceId, + ROM_API_INDEX_SFlash_Powerdown, + ROM_API_INDEX_SFlash_Releae_Powerdown, + ROM_API_INDEX_SFlash_Restore_From_Powerdown, + ROM_API_INDEX_SFlash_SetBurstWrap, + ROM_API_INDEX_SFlash_DisableBurstWrap, + ROM_API_INDEX_SFlash_Software_Reset, + ROM_API_INDEX_SFlash_Reset_Continue_Read, + ROM_API_INDEX_SFlash_Set_IDbus_Cfg, + ROM_API_INDEX_SFlash_IDbus_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Read_Disable, + ROM_API_INDEX_SFlash_Read, + + ROM_API_INDEX_L1C_Cache_Enable_Set, + ROM_API_INDEX_L1C_Cache_Write_Set, + ROM_API_INDEX_L1C_Cache_Flush, + ROM_API_INDEX_L1C_Cache_Hit_Count_Get, + ROM_API_INDEX_L1C_Cache_Miss_Count_Get, + ROM_API_INDEX_L1C_Cache_Read_Disable, + ROM_API_INDEX_L1C_Set_Wrap, + ROM_API_INDEX_L1C_Set_Way_Disable, + ROM_API_INDEX_L1C_IROM_2T_Access_Set, + + ROM_API_INDEX_SF_Ctrl_Enable, + ROM_API_INDEX_SF_Ctrl_Psram_Init, + ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay, + ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay, + ROM_API_INDEX_SF_Ctrl_Cmds_Set, + ROM_API_INDEX_SF_Ctrl_Set_Owner, + ROM_API_INDEX_SF_Ctrl_Disable, + ROM_API_INDEX_SF_Ctrl_Select_Pad, + ROM_API_INDEX_SF_Ctrl_Select_Bank, + ROM_API_INDEX_SF_Ctrl_AES_Enable_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable_LE, + ROM_API_INDEX_SF_Ctrl_AES_Set_Region, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable, + ROM_API_INDEX_SF_Ctrl_AES_Disable, + ROM_API_INDEX_SF_Ctrl_Is_AES_Enable, + ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Select_Clock, + ROM_API_INDEX_SF_Ctrl_SendCmd, + ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set, + ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set, + ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set, + ROM_API_INDEX_SF_Ctrl_GetBusyState, + ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock, + ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Flash_Identify, + + ROM_API_INDEX_Psram_Init, + ROM_API_INDEX_Psram_ReadReg, + ROM_API_INDEX_Psram_WriteReg, + ROM_API_INDEX_Psram_SetDriveStrength, + ROM_API_INDEX_Psram_SetBurstWrap, + ROM_API_INDEX_Psram_ReadId, + ROM_API_INDEX_Psram_EnterQuadMode, + ROM_API_INDEX_Psram_ExitQuadMode, + ROM_API_INDEX_Psram_ToggleBurstLength, + ROM_API_INDEX_Psram_SoftwareReset, + ROM_API_INDEX_Psram_Set_IDbus_Cfg, + ROM_API_INDEX_Psram_Cache_Write_Set, + ROM_API_INDEX_Psram_Write, + ROM_API_INDEX_Psram_Read, + + ROM_API_INDEX_FUNC_LAST = ROM_API_INDEX_Psram_Read, + + ROM_API_INDEX_FUNC_INVALID_START, + + ROM_API_INDEX_FUNC_LAST_ENTRY = ROMAPI_INDEX_MAX +} ROM_API_INDEX_e; + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup ROMDRIVER + * @{ + */ + +/** @defgroup ROMDRIVER_Public_Types + * @{ + */ +#define ROM_APITABLE ((uint32_t *)0x21018800) + +#define RomDriver_AON_Power_On_MBG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG]) +#define RomDriver_AON_Power_Off_MBG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG]) +#define RomDriver_AON_Power_On_XTAL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL]) +#define RomDriver_AON_Set_Xtal_CapCode \ + ((BL_Err_Type(*)(uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode]) +#define RomDriver_AON_Power_Off_XTAL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL]) + +#define RomDriver_ASM_Delay_Us \ + ((void (*)(uint32_t core, uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us]) +#define RomDriver_BL702_Delay_US \ + ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702_Delay_US]) +#define RomDriver_BL702_Delay_MS \ + ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702_Delay_MS]) +#define RomDriver_BL702_MemCpy \ + ((void *(*)(void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy]) +#define RomDriver_BL702_MemCpy4 \ + ((uint32_t * (*)(uint32_t * dst, const uint32_t *src, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy4]) +#define RomDriver_BL702_MemCpy_Fast \ + ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy_Fast]) +#define RomDriver_ARCH_MemCpy_Fast \ + ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_ARCH_MemCpy_Fast]) +#define RomDriver_BL702_MemSet \ + ((void *(*)(void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemSet]) +#define RomDriver_BL702_MemSet4 \ + ((uint32_t * (*)(uint32_t * dst, const uint32_t val, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL702_MemSet4]) +#define RomDriver_BL702_MemCmp \ + ((int (*)(const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCmp]) +#define RomDriver_BFLB_Soft_CRC32 \ + ((uint32_t(*)(void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32]) + +#define RomDriver_GLB_Get_Root_CLK_Sel \ + ((GLB_ROOT_CLK_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel]) +#define RomDriver_GLB_Set_System_CLK_Div \ + ((BL_Err_Type(*)(uint8_t hclkDiv, uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div]) +#define RomDriver_GLB_Get_BCLK_Div \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div]) +#define RomDriver_GLB_Get_HCLK_Div \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div]) +#define RomDriver_Update_SystemCoreClockWith_XTAL \ + ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL]) +#define RomDriver_GLB_Set_System_CLK \ + ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK]) +#define RomDriver_System_Core_Clock_Update_From_RC32M \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M]) +#define RomDriver_GLB_Set_SF_CLK \ + ((BL_Err_Type(*)(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK]) +#define RomDriver_GLB_Power_Off_DLL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_DLL]) +#define RomDriver_GLB_Power_On_DLL \ + ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_DLL]) +#define RomDriver_GLB_Enable_DLL_All_Clks \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_All_Clks]) +#define RomDriver_GLB_Enable_DLL_Clk \ + ((BL_Err_Type(*)(GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_Clk]) +#define RomDriver_GLB_Disable_DLL_All_Clks \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_All_Clks]) +#define RomDriver_GLB_Disable_DLL_Clk \ + ((BL_Err_Type(*)(GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_Clk]) +#define RomDriver_GLB_SW_System_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset]) +#define RomDriver_GLB_SW_CPU_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset]) +#define RomDriver_GLB_SW_POR_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset]) +#define RomDriver_GLB_Select_Internal_Flash \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash]) +#define RomDriver_GLB_Swap_Flash_Pin \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin]) +#define RomDriver_GLB_Swap_Flash_CS_IO2_Pin \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin]) +#define RomDriver_GLB_Swap_Flash_IO0_IO3_Pin \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin]) +#define RomDriver_GLB_Select_Internal_PSram \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_PSram]) +#define RomDriver_GLB_GPIO_Init \ + ((BL_Err_Type(*)(GLB_GPIO_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init]) +#define RomDriver_GLB_GPIO_OUTPUT_Enable \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable]) +#define RomDriver_GLB_GPIO_OUTPUT_Disable \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable]) +#define RomDriver_GLB_GPIO_Set_HZ \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ]) +#define RomDriver_GLB_Deswap_Flash_Pin \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin]) +#define RomDriver_GLB_Select_External_Flash \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash]) +#define RomDriver_GLB_GPIO_Get_Fun \ + ((uint8_t(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun]) + +#define RomDriver_EF_Ctrl_Busy \ + ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy]) +#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0]) +#define RomDriver_EF_Ctrl_Load_Efuse_R0 \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0]) +#define RomDriver_EF_Ctrl_Clear \ + ((void (*)(uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear]) +#define RomDriver_EF_Ctrl_Get_Trim_Parity \ + ((uint8_t(*)(uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity]) +#define RomDriver_EF_Ctrl_Read_RC32K_Trim \ + ((void (*)(Efuse_Ana_RC32K_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim]) +#define RomDriver_EF_Ctrl_Read_RC32M_Trim \ + ((void (*)(Efuse_Ana_RC32M_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim]) + +#define RomDriver_PDS_Trim_RC32M \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M]) +#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref]) +#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref]) +#define RomDriver_PDS_Power_On_PLL \ + ((BL_Err_Type(*)(PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL]) +#define RomDriver_PDS_Enable_PLL_All_Clks \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks]) +#define RomDriver_PDS_Disable_PLL_All_Clks \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks]) +#define RomDriver_PDS_Enable_PLL_Clk \ + ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk]) +#define RomDriver_PDS_Disable_PLL_Clk \ + ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk]) +#define RomDriver_PDS_Power_Off_PLL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL]) +#define RomDriver_PDS_Reset \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset]) +#define RomDriver_PDS_Enable \ + ((void (*)(PDS_CFG_Type * cfg, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Enable]) +#define RomDriver_PDS_Auto_Time_Config \ + ((void (*)(uint32_t sleepDuration))ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Time_Config]) +#define RomDriver_PDS_Auto_Enable \ + ((void (*)(PDS_AUTO_POWER_DOWN_CFG_Type * powerCfg, PDS_AUTO_NORMAL_CFG_Type * normalCfg, BL_Fun_Type enable)) ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Enable]) +#define RomDriver_PDS_Manual_Force_Turn_Off \ + ((void (*)(PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_Off]) +#define RomDriver_PDS_Manual_Force_Turn_On \ + ((void (*)(PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_On]) + +#define RomDriver_HBN_Enable \ + ((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable]) +#define RomDriver_HBN_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset]) +#define RomDriver_HBN_GPIO_Dbg_Pull_Cfg \ + ((BL_Err_Type(*)(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg]) +#define RomDriver_HBN_Trim_RC32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K]) +#define RomDriver_HBN_Set_ROOT_CLK_Sel \ + ((BL_Err_Type(*)(HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel]) + +#define RomDriver_XIP_SFlash_State_Save \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) +#define RomDriver_XIP_SFlash_State_Restore \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) +#define RomDriver_XIP_SFlash_Erase_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) +#define RomDriver_XIP_SFlash_Write_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) +#define RomDriver_XIP_SFlash_Read_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) +#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) +#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) +#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) +#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \ + ((BL_Err_Type(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) +#define RomDriver_XIP_SFlash_Read_With_Lock \ + ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * dst, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock]) +#define RomDriver_XIP_SFlash_Write_With_Lock \ + ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * src, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock]) +#define RomDriver_XIP_SFlash_Erase_With_Lock \ + ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock]) + +#define RomDriver_SFlash_Init \ + ((void (*)(const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) +#define RomDriver_SFlash_SetSPIMode \ + ((BL_Err_Type(*)(SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) +#define RomDriver_SFlash_Read_Reg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) +#define RomDriver_SFlash_Write_Reg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) +#define RomDriver_SFlash_Read_Reg_With_Cmd \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) +#define RomDriver_SFlash_Write_Reg_With_Cmd \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) +#define RomDriver_SFlash_Busy \ + ((BL_Sts_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) +#define RomDriver_SFlash_Write_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) +#define RomDriver_SFlash_Qspi_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) +#define RomDriver_SFlash_Volatile_Reg_Write_Enable \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) +#define RomDriver_SFlash_Chip_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) +#define RomDriver_SFlash_Sector_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) +#define RomDriver_SFlash_Blk32_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) +#define RomDriver_SFlash_Blk64_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) +#define RomDriver_SFlash_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) +#define RomDriver_SFlash_Program \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) +#define RomDriver_SFlash_GetUniqueId \ + ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId]) +#define RomDriver_SFlash_GetJedecId \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) +#define RomDriver_SFlash_GetDeviceId \ + ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) +#define RomDriver_SFlash_Powerdown \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown]) +#define RomDriver_SFlash_Releae_Powerdown \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) +#define RomDriver_SFlash_Restore_From_Powerdown \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) +#define RomDriver_SFlash_SetBurstWrap \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) +#define RomDriver_SFlash_DisableBurstWrap \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) +#define RomDriver_SFlash_Software_Reset \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) +#define RomDriver_SFlash_Reset_Continue_Read \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) +#define RomDriver_SFlash_Set_IDbus_Cfg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) +#define RomDriver_SFlash_IDbus_Read_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) +#define RomDriver_SFlash_Cache_Read_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) +#define RomDriver_SFlash_Cache_Read_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable]) +#define RomDriver_SFlash_Read \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) + +#define RomDriver_L1C_Cache_Enable_Set \ + ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Enable_Set]) +#define RomDriver_L1C_Cache_Write_Set \ + ((void (*)(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Write_Set]) +#define RomDriver_L1C_Cache_Flush \ + ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Flush]) +#define RomDriver_L1C_Cache_Hit_Count_Get \ + ((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Hit_Count_Get]) +#define RomDriver_L1C_Cache_Miss_Count_Get \ + ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Miss_Count_Get]) +#define RomDriver_L1C_Cache_Read_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Read_Disable]) +#define RomDriver_L1C_Set_Wrap \ + ((BL_Err_Type(*)(BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap]) +#define RomDriver_L1C_Set_Way_Disable \ + ((BL_Err_Type(*)(uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable]) +#define RomDriver_L1C_IROM_2T_Access_Set \ + ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set]) + +#define RomDriver_SF_Ctrl_Enable \ + ((void (*)(const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) +#define RomDriver_SF_Ctrl_Psram_Init \ + ((void (*)(SF_Ctrl_Psram_Cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Init]) +#define RomDriver_SF_Ctrl_Get_Clock_Delay \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]) +#define RomDriver_SF_Ctrl_Set_Clock_Delay \ + ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]) +#define RomDriver_SF_Ctrl_Cmds_Set \ + ((void (*)(SF_Ctrl_Cmds_Cfg * cmdsCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set]) +#define RomDriver_SF_Ctrl_Set_Owner \ + ((void (*)(SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) +#define RomDriver_SF_Ctrl_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable]) +#define RomDriver_SF_Ctrl_Select_Pad \ + ((void (*)(SF_Ctrl_Pad_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) +#define RomDriver_SF_Ctrl_Select_Bank \ + ((void (*)(SF_Ctrl_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Bank]) +#define RomDriver_SF_Ctrl_AES_Enable_BE \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE]) +#define RomDriver_SF_Ctrl_AES_Enable_LE \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE]) +#define RomDriver_SF_Ctrl_AES_Set_Region \ + ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region]) +#define RomDriver_SF_Ctrl_AES_Set_Key \ + ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) +#define RomDriver_SF_Ctrl_AES_Set_Key_BE \ + ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) +#define RomDriver_SF_Ctrl_AES_Set_IV \ + ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV]) +#define RomDriver_SF_Ctrl_AES_Set_IV_BE \ + ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE]) +#define RomDriver_SF_Ctrl_AES_Enable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable]) +#define RomDriver_SF_Ctrl_AES_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable]) +#define RomDriver_SF_Ctrl_Is_AES_Enable \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]) +#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \ + ((void (*)(uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset]) +#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \ + ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) +#define RomDriver_SF_Ctrl_Select_Clock \ + ((void (*)(SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock]) +#define RomDriver_SF_Ctrl_SendCmd \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) +#define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set]) +#define RomDriver_SF_Ctrl_Psram_Write_Icache_Set \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set]) +#define RomDriver_SF_Ctrl_Psram_Read_Icache_Set \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set]) +#define RomDriver_SF_Ctrl_GetBusyState \ + ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) +#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \ + ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) +#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \ + ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) +#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \ + ((BL_Err_Type(*)(uint32_t flashID, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) +#define RomDriver_SF_Cfg_Init_Flash_Gpio \ + ((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) +#define RomDriver_SF_Cfg_Flash_Identify \ + ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) + +#define RomDriver_Psram_Init \ + ((void (*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_Cmds_Cfg * cmdsCfg, SF_Ctrl_Psram_Cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_Init]) +#define RomDriver_Psram_ReadReg \ + ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadReg]) +#define RomDriver_Psram_WriteReg \ + ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_WriteReg]) +#define RomDriver_Psram_SetDriveStrength \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetDriveStrength]) +#define RomDriver_Psram_SetBurstWrap \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetBurstWrap]) +#define RomDriver_Psram_ReadId \ + ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadId]) +#define RomDriver_Psram_EnterQuadMode \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_EnterQuadMode]) +#define RomDriver_Psram_ExitQuadMode \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_ExitQuadMode]) +#define RomDriver_Psram_ToggleBurstLength \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, PSRAM_Ctrl_Mode ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_ToggleBurstLength]) +#define RomDriver_Psram_SoftwareReset \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, PSRAM_Ctrl_Mode ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_SoftwareReset]) +#define RomDriver_Psram_Set_IDbus_Cfg \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Set_IDbus_Cfg]) +#define RomDriver_Psram_Cache_Write_Set \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)) ROM_APITABLE[ROM_API_INDEX_Psram_Cache_Write_Set]) +#define RomDriver_Psram_Write \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Write]) +#define RomDriver_Psram_Read \ + ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Read]) +/*@} end of group ROMDRIVER_Public_Types */ + +/** @defgroup ROMDRIVER_Public_Constants + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Constants */ + +/** @defgroup ROMDRIVER_Public_Macros + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Macros */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_ROMDRIVER_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_dbg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_dbg.h new file mode 100644 index 0000000000000000000000000000000000000000..d30442544fdb3c8fcf385e9da8ab8212a6e97521 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_dbg.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file bl702_sec_dbg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_SEC_DBG_H__ +#define __BL702_SEC_DBG_H__ + +#include "sec_dbg_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_DBG + * @{ + */ + +/** @defgroup SEC_DBG_Public_Types + * @{ + */ + +/*@} end of group SEC_DBG_Public_Types */ + +/** @defgroup SEC_DBG_Public_Constants + * @{ + */ + +/*@} end of group SEC_DBG_Public_Constants */ + +/** @defgroup SEC_DBG_Public_Macros + * @{ + */ + +/*@} end of group SEC_DBG_Public_Macros */ + +/** @defgroup SEC_DBG_Public_Functions + * @{ + */ +void Sec_Dbg_Read_Chip_ID(uint8_t id[8]); +void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]); +uint32_t Sec_Dbg_Read_Dbg_Mode(void); +uint32_t Sec_Dbg_Read_Dbg_Enable(void); + +/*@} end of group SEC_DBG_Public_Functions */ + +/*@} end of group SEC_DBG */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_SEC_DBG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h new file mode 100644 index 0000000000000000000000000000000000000000..81cfad433d82a9b98abb699063349561097d2e28 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h @@ -0,0 +1,580 @@ +/** + ****************************************************************************** + * @file bl702_sec_eng.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_SEC_ENG_H__ +#define __BL702_SEC_ENG_H__ + +#include "sec_eng_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_ENG + * @{ + */ + +/** @defgroup SEC_ENG_Public_Types + * @{ + */ + +/** + * @brief AES port type definition + */ +typedef enum { + SEC_ENG_AES_ID0, /*!< AES0 port define */ +} SEC_ENG_AES_ID_Type; + +/** + * @brief SHA port type definition + */ +typedef enum { + SEC_ENG_SHA_ID0, /*!< SHA0 port define */ +} SEC_ENG_SHA_ID_Type; + +/** + * @brief SHA type definition + */ +typedef enum { + SEC_ENG_SHA256, /*!< SHA type:SHA256 */ + SEC_ENG_SHA224, /*!< SHA type:SHA224 */ + SEC_ENG_SHA1, /*!< SHA type:SHA1 */ + SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */ +} SEC_ENG_SHA_Type; + +/** + * @brief AES type definition + */ +typedef enum { + SEC_ENG_AES_ECB, /*!< AES mode type:ECB */ + SEC_ENG_AES_CTR, /*!< AES mode type:CTR */ + SEC_ENG_AES_CBC, /*!< AES mode type:CBC */ +} SEC_ENG_AES_Type; + +/** + * @brief AES KEY type definition + */ +typedef enum { + SEC_ENG_AES_KEY_128BITS, /*!< AES KEY type:128 bits */ + SEC_ENG_AES_KEY_256BITS, /*!< AES KEY type:256 bits */ + SEC_ENG_AES_KEY_192BITS, /*!< AES KEY type:192 bits */ + SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */ +} SEC_ENG_AES_Key_Type; + +/** + * @brief AES CTR mode counter type definition + */ +typedef enum { + SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */ + SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */ + SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */ + SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */ +} SEC_ENG_AES_Counter_Type; + +/** + * @brief AES use new or old value type definition + */ +typedef enum { + SEC_ENG_AES_USE_NEW, /*!< Use new value */ + SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */ +} SEC_ENG_AES_ValueUsed_Type; + +/** + * @brief AES KEY source type definition + */ +typedef enum { + SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */ + SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */ +} SEC_ENG_AES_Key_Src_Type; + +/** + * @brief AES KEY source type definition + */ +typedef enum { + SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */ + SEC_ENG_AES_DECRYPTION, /*!< AES decryption */ +} SEC_ENG_AES_EnDec_Type; + +/** + * @brief AES PKA register size type definition + */ +typedef enum { + SEC_ENG_PKA_REG_SIZE_8 = 1, /*!< Register size is 8 Bytes */ + SEC_ENG_PKA_REG_SIZE_16, /*!< Register size is 16 Bytes */ + SEC_ENG_PKA_REG_SIZE_32, /*!< Register size is 32 Bytes */ + SEC_ENG_PKA_REG_SIZE_64, /*!< Register size is 64 Bytes */ + SEC_ENG_PKA_REG_SIZE_96, /*!< Register size is 96 Bytes */ + SEC_ENG_PKA_REG_SIZE_128, /*!< Register size is 128 Bytes */ + SEC_ENG_PKA_REG_SIZE_192, /*!< Register size is 192 Bytes */ + SEC_ENG_PKA_REG_SIZE_256, /*!< Register size is 256 Bytes */ + SEC_ENG_PKA_REG_SIZE_384, /*!< Register size is 384 Bytes */ + SEC_ENG_PKA_REG_SIZE_512, /*!< Register size is 512 Bytes */ +} SEC_ENG_PKA_REG_SIZE_Type; + +/** + * @brief AES PKA register size type definition + */ +typedef enum { + SEC_ENG_PKA_OP_PPSEL, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MOD2N = 0x11, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LDIV2N = 0x12, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LMUL2N = 0x13, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LDIV = 0x14, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LSQR = 0x15, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LMUL = 0x16, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LSUB = 0x17, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LADD = 0x18, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LCMP = 0x19, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MDIV2 = 0x21, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MINV = 0x22, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MEXP = 0x23, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MSQR = 0x24, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MMUL = 0x25, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MREM = 0x26, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MSUB = 0x27, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MADD = 0x28, /*!< PKA operation type */ + SEC_ENG_PKA_OP_RESIZE = 0x31, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MOVDAT = 0x32, /*!< PKA operation type */ + SEC_ENG_PKA_OP_NLIR = 0x33, /*!< PKA operation type */ + SEC_ENG_PKA_OP_SLIR = 0x34, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CLIR = 0x35, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CFLIRI_BUFFER = 0x36, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CTLIRI_PLD = 0x37, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CFLIR_BUFFER = 0x38, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CTLIR_PLD = 0x39, /*!< PKA operation type */ +} SEC_ENG_PKA_OP_Type; + +/** + * @brief Sec Eng Interrupt Type Def + */ +typedef enum { + SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */ + SEC_ENG_INT_AES, /*!< Sec Eng Aes Interrupt Type */ + SEC_ENG_INT_SHA, /*!< Sec Eng Sha Interrupt Type */ + SEC_ENG_INT_PKA, /*!< Sec Eng Pka Interrupt Type */ + SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */ + SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */ + SEC_ENG_INT_ALL, /*!< Sec Eng All Interrupt Types */ +} SEC_ENG_INT_Type; + +/** + * @brief SEC_ENG SHA context + */ +typedef struct +{ + uint32_t total[2]; /*!< Number of bytes processed */ + uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ + uint32_t *shaPadding; /*!< Padding data */ + uint8_t shaFeed; /*!< Sha has feed data */ +} SEC_Eng_SHA256_Ctx; + +/** + * @brief SEC_ENG SHA link mode context + */ +typedef struct +{ + uint32_t total[2]; /*!< Number of bytes processed */ + uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ + uint32_t *shaPadding; /*!< Padding data */ + uint32_t linkAddr; /*!< Link configure address */ +} SEC_Eng_SHA256_Link_Ctx; + +/** + * @brief SEC_ENG AES context + */ +typedef struct +{ + uint8_t aesFeed; /*!< AES has feed data */ + SEC_ENG_AES_Type mode; /*!< AES mode */ +} SEC_Eng_AES_Ctx; + +/** + * @brief SEC_ENG SHA link config structure type definition + */ +typedef struct +{ + uint32_t : 2; /*!< [1:0]reserved */ + uint32_t shaMode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1 */ + uint32_t : 1; /*!< [5]reserved */ + uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */ + uint32_t : 2; /*!< [8:7]reserved */ + uint32_t shaIntClr : 1; /*!< [9]Clear interrupt */ + uint32_t shaIntSet : 1; /*!< [10]Set interrupt */ + uint32_t : 5; /*!< [15:11]reserved */ + uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */ + uint32_t shaSrcAddr; /*!< Message source address */ + uint32_t result[8]; /*!< Result of SHA */ +} __attribute__((aligned(4))) SEC_Eng_SHA_Link_Config_Type; + +/** + * @brief SEC_ENG AES link config structure type definition + */ +typedef struct +{ + uint32_t : 3; /*!< [2:0]Reserved */ + uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ + uint32_t aesDecEn : 1; /*!< [5]Encode or decode */ + uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */ + uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */ + uint32_t : 1; /*!< [8]Reserved */ + uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */ + uint32_t aesIntSet : 1; /*!< [10]Set interrupt */ + uint32_t : 1; /*!< [11]Reserved */ + uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ + uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */ + uint32_t : 1; /*!< [15]Reserved */ + uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */ + uint32_t aesSrcAddr; /*!< Message source address */ + uint32_t aesDstAddr; /*!< Message destination address */ + uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ + uint32_t aesIV1; /*!< Big endian initial vector */ + uint32_t aesIV2; /*!< Big endian initial vector */ + uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ + uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */ + uint32_t aesKey1; /*!< Big endian aes key */ + uint32_t aesKey2; /*!< Big endian aes key */ + uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */ + uint32_t aesKey4; /*!< Big endian aes key */ + uint32_t aesKey5; /*!< Big endian aes key */ + uint32_t aesKey6; /*!< Big endian aes key */ + uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */ +} __attribute__((aligned(4))) SEC_Eng_AES_Link_Config_Type; + +/** + * @brief SEC_ENG GMAC link config structure type definition + */ +typedef struct +{ + uint32_t : 9; /*!< [8:0]reserved */ + uint32_t gmacIntClr : 1; /*!< [9]Clear interrupt */ + uint32_t gmacIntSet : 1; /*!< [10]Set interrupt */ + uint32_t : 5; /*!< [15:11]reserved */ + uint32_t gmacMsgLen : 16; /*!< [31:16]Number of 128-bit block */ + uint32_t gmacSrcAddr; /*!< Message source address */ + uint32_t gmacKey0; /*!< GMAC key */ + uint32_t gmacKey1; /*!< GMAC key */ + uint32_t gmacKey2; /*!< GMAC key */ + uint32_t gmacKey3; /*!< GMAC key */ + uint32_t result[4]; /*!< Result of GMAC */ + uint32_t dummy; /*!< Not use,trigger GMAC will clear this value */ +} __attribute__((aligned(4))) SEC_Eng_GMAC_Link_Config_Type; + +/** + * @brief SEC_ENG PKA status type definition + */ +typedef struct +{ + uint16_t primeFail : 1; /*!< [0]Prime fail */ + uint16_t errUnknown : 1; /*!< [1]Err unknown opc */ + uint16_t errOverflow : 1; /*!< [2]Err opq overflow */ + uint16_t errSrc2 : 1; /*!< [3]Err invalid src2 */ + uint16_t errSrc1 : 1; /*!< [4]Err invalid src1 */ + uint16_t errSrc0 : 1; /*!< [5]Err invalid src0 */ + uint16_t errDiv0 : 1; /*!< [6]Err div by 0 */ + uint16_t errFull : 1; /*!< [7]Err cam full */ + uint16_t lastOpc : 1; /*!< [8]Last opc */ + uint16_t opqFull : 1; /*!< [9]Opq full */ + uint16_t cmdIndex : 5; /*!< [14:10]Cmd err index */ + uint16_t errCmd : 1; /*!< [15]Err cmd */ +} SEC_Eng_PKA_Status_Type; + +/*@} end of group SEC_ENG_Public_Types */ + +/** @defgroup SEC_ENG_Public_Constants + * @{ + */ + +/** @defgroup SEC_ENG_AES_ID_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0)) + +/** @defgroup SEC_ENG_SHA_ID_TYPE + * @{ + */ +#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0)) + +/** @defgroup SEC_ENG_SHA_TYPE + * @{ + */ +#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || \ + ((type) == SEC_ENG_SHA224) || \ + ((type) == SEC_ENG_SHA1) || \ + ((type) == SEC_ENG_SHA1_RSVD)) + +/** @defgroup SEC_ENG_AES_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || \ + ((type) == SEC_ENG_AES_CTR) || \ + ((type) == SEC_ENG_AES_CBC)) + +/** @defgroup SEC_ENG_AES_KEY_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || \ + ((type) == SEC_ENG_AES_KEY_256BITS) || \ + ((type) == SEC_ENG_AES_KEY_192BITS) || \ + ((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS)) + +/** @defgroup SEC_ENG_AES_COUNTER_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_COUNTER_TYPE(type) (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_1) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_2) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_3)) + +/** @defgroup SEC_ENG_AES_VALUEUSED_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || \ + ((type) == SEC_ENG_AES_USE_OLD)) + +/** @defgroup SEC_ENG_AES_KEY_SRC_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || \ + ((type) == SEC_ENG_AES_KEY_HW)) + +/** @defgroup SEC_ENG_AES_ENDEC_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || \ + ((type) == SEC_ENG_AES_DECRYPTION)) + +/** @defgroup SEC_ENG_PKA_REG_SIZE_TYPE + * @{ + */ +#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type) (((type) == SEC_ENG_PKA_REG_SIZE_8) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_16) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_32) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_64) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_96) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_128) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_192) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_256) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_384) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_512)) + +/** @defgroup SEC_ENG_PKA_OP_TYPE + * @{ + */ +#define IS_SEC_ENG_PKA_OP_TYPE(type) (((type) == SEC_ENG_PKA_OP_PPSEL) || \ + ((type) == SEC_ENG_PKA_OP_MOD2N) || \ + ((type) == SEC_ENG_PKA_OP_LDIV2N) || \ + ((type) == SEC_ENG_PKA_OP_LMUL2N) || \ + ((type) == SEC_ENG_PKA_OP_LDIV) || \ + ((type) == SEC_ENG_PKA_OP_LSQR) || \ + ((type) == SEC_ENG_PKA_OP_LMUL) || \ + ((type) == SEC_ENG_PKA_OP_LSUB) || \ + ((type) == SEC_ENG_PKA_OP_LADD) || \ + ((type) == SEC_ENG_PKA_OP_LCMP) || \ + ((type) == SEC_ENG_PKA_OP_MDIV2) || \ + ((type) == SEC_ENG_PKA_OP_MINV) || \ + ((type) == SEC_ENG_PKA_OP_MEXP) || \ + ((type) == SEC_ENG_PKA_OP_MSQR) || \ + ((type) == SEC_ENG_PKA_OP_MMUL) || \ + ((type) == SEC_ENG_PKA_OP_MREM) || \ + ((type) == SEC_ENG_PKA_OP_MSUB) || \ + ((type) == SEC_ENG_PKA_OP_MADD) || \ + ((type) == SEC_ENG_PKA_OP_RESIZE) || \ + ((type) == SEC_ENG_PKA_OP_MOVDAT) || \ + ((type) == SEC_ENG_PKA_OP_NLIR) || \ + ((type) == SEC_ENG_PKA_OP_SLIR) || \ + ((type) == SEC_ENG_PKA_OP_CLIR) || \ + ((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || \ + ((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) || \ + ((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) || \ + ((type) == SEC_ENG_PKA_OP_CTLIR_PLD)) + +/** @defgroup SEC_ENG_INT_TYPE + * @{ + */ +#define IS_SEC_ENG_INT_TYPE(type) (((type) == SEC_ENG_INT_TRNG) || \ + ((type) == SEC_ENG_INT_AES) || \ + ((type) == SEC_ENG_INT_SHA) || \ + ((type) == SEC_ENG_INT_PKA) || \ + ((type) == SEC_ENG_INT_CDET) || \ + ((type) == SEC_ENG_INT_GMAC) || \ + ((type) == SEC_ENG_INT_ALL)) + +/*@} end of group SEC_ENG_Public_Constants */ + +/** @defgroup SEC_ENG_Public_Macros + * @{ + */ +#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24 +#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK 0x01000000 + +/*@} end of group SEC_ENG_Public_Macros */ + +/** @defgroup SEC_ENG_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SEC_GMAC_IRQHandler(void); +void SEC_CDET_IRQHandler(void); +void SEC_TRNG_IRQHandler(void); +void SEC_PKA_IRQHandler(void); +void SEC_AES_IRQHandler(void); +void SEC_SHA_IRQHandler(void); +#endif +void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type type, + uint32_t shaTmpBuf[16], + uint32_t padding[16]); +void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo); +BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, + uint32_t len); +BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash); +void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo); +void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo); +void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, + uint32_t shaTmpBuf[16], uint32_t padding[16]); +BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, + const uint8_t *input, uint32_t len); +BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, + uint8_t *hash); +BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, + SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType); +void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo); +BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, + uint8_t *out); +void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src); +void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, + const uint8_t *iv); +void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, + const uint8_t *iv); +void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType); +BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, + uint8_t *out); +BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo); +BL_Err_Type Sec_Eng_Trng_Enable(void); +void Sec_Eng_Trng_Int_Enable(void); +void Sec_Eng_Trng_Int_Disable(void); +BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]); +BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len); +void Sec_Eng_Trng_Int_Read_Trigger(void); +void Sec_Eng_Trng_Int_Read(uint8_t data[32]); +void Sec_Eng_Trng_Disable(void); +void Sec_Eng_PKA_Reset(void); +void Sec_Eng_PKA_BigEndian_Enable(void); +void Sec_Eng_PKA_LittleEndian_Enable(void); +void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status); +void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, + uint8_t lastOp); +void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize); +void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp); +void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp); +void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx); +void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, + uint8_t s2RegIdx, uint8_t lastOp); +void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx, uint32_t size, + uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx); +void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType, + uint8_t invrRegIdx, + uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx); +void Sec_Eng_GMAC_Enable_LE(void); +void Sec_Eng_GMAC_Enable_BE(void); +void Sec_Eng_GMAC_Enable_Link(void); +void Sec_Eng_GMAC_Disable_Link(void); +BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out); +void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask); +void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType); +void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun); +BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType); +/*----------*/ +void SEC_Eng_Turn_On_Sec_Ring(void); +void SEC_Eng_Turn_Off_Sec_Ring(void); +/*----------*/; + +/*@} end of group SEC_ENG_Public_Functions */ + +/*@} end of group SEC_ENG */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_SEC_ENG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..5c050373156463378a1f0a2c4f04584801ab7ac1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file bl702_sf_cfg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_SF_CFG_H__ +#define __BL702_SF_CFG_H__ + +#include "string.h" +#include "bl702_sflash.h" +#include "bl702_sf_ctrl.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_Public_Types */ + +/** @defgroup SF_CFG_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_Public_Constants */ + +/** @defgroup SF_CFG_Public_Macros + * @{ + */ +/* Flash option 0 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_21 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_19 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_17 +#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_18 +#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_22 +#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_20 +/* Flash option 1 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_27 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_25 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_28 +#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_24 +#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_23 +#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_26 +/* Flash option 2 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK2_GPIO 38 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS2_GPIO 38 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA02_GPIO 38 +#define BFLB_EXTFLASH_DATA12_GPIO 38 +#define BFLB_EXTFLASH_DATA22_GPIO 38 +#define BFLB_EXTFLASH_DATA32_GPIO 38 +#define BFLB_FLASH_CFG_SF2_EXT_23_28 0 +#define BFLB_FLASH_CFG_SF2_INT_512K 1 +#define BFLB_FLASH_CFG_SF2_INT_1M 2 +#define BFLB_FLASH_CFG_SF1_EXT_17_22 3 +#define BFLB_SF2_SWAP_NONE 0 +#define BFLB_SF2_SWAP_CS_IO2 1 +#define BFLB_SF2_SWAP_IO0_IO3 2 +#define BFLB_SF2_SWAP_BOTH 3 +#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 +#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF + +/*@} end of group SF_CFG_Public_Macros */ + +/** @defgroup SF_CFG_Public_Functions + * @{ + */ +BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); +void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault); +uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, + SPI_Flash_Cfg_Type *pFlashCfg); +void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); +void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); + +/*@} end of group SF_CFG_Public_Functions */ + +/*@} end of group SF_CFG */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_SF_CFG_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg_ext.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..e1666d7292a627c10ac2af0948982f14e7dc8edf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg_ext.h @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file bl702_sf_cfg_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_SF_CFG_EXT_H__ +#define __BL702_SF_CFG_EXT_H__ + +#include "string.h" +#include "bl702_sflash.h" +#include "bl702_sf_ctrl.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG_EXT + * @{ + */ + +/** @defgroup SF_CFG_EXT_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Types */ + +/** @defgroup SF_CFG_EXT_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Constants */ + +/** @defgroup SF_CFG_EXT_Public_Macros + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Macros */ + +/** @defgroup SF_CFG_EXT_Public_Functions + * @{ + */ +void SF_Cfg_Init_Internal_Flash_Gpio(void); +BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); +uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, + uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg); + +/*@} end of group SF_CFG_EXT_Public_Functions */ + +/*@} end of group SF_CFG_EXT */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_SF_CFG_EXT_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_ctrl.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..756e26009f5285289948060009f03e7932e4d43f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_ctrl.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file bl702_sf_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_SF_CTRL_H__ +#define __BL702_SF_CTRL_H__ + +#include "sf_ctrl_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Serial flash pad select type definition + */ +typedef enum { + SF_CTRL_PAD_SEL_SF1, /*!< SF Ctrl pad select sf1, flash use GPIO 17-22, no psram */ + SF_CTRL_PAD_SEL_SF2, /*!< SF Ctrl pad select sf2, flash use GPIO 23-28, no psram, embedded flash */ + SF_CTRL_PAD_SEL_SF3, /*!< SF Ctrl pad select sf3, flash use GPIO 32-37, no psram */ + SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2, /*!< SF Ctrl pad select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */ + SF_CTRL_PAD_SEL_DUAL_BANK_SF2_SF3, /*!< SF Ctrl pad select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */ + SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1, /*!< SF Ctrl pad select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */ + SF_CTRL_PAD_SEL_DUAL_CS_SF2, /*!< SF Ctrl pad select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */ + SF_CTRL_PAD_SEL_DUAL_CS_SF3, /*!< SF Ctrl pad select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */ +} SF_Ctrl_Pad_Select; + +/** + * @brief Serial flash system bus control type definition + */ +typedef enum { + SF_CTRL_SEL_FLASH, /*!< SF Ctrl system bus control flash */ + SF_CTRL_SEL_PSRAM, /*!< SF Ctrl system bus control psram */ +} SF_Ctrl_Select; + +/** + * @brief Serail flash controller wrap mode len type definition + */ +typedef enum { + SF_CTRL_WRAP_LEN_8, /*!< SF Ctrl wrap length: 8 */ + SF_CTRL_WRAP_LEN_16, /*!< SF Ctrl wrap length: 16 */ + SF_CTRL_WRAP_LEN_32, /*!< SF Ctrl wrap length: 32 */ + SF_CTRL_WRAP_LEN_64, /*!< SF Ctrl wrap length: 64 */ + SF_CTRL_WRAP_LEN_128, /*!< SF Ctrl wrap length: 128 */ + SF_CTRL_WRAP_LEN_256, /*!< SF Ctrl wrap length: 256 */ + SF_CTRL_WRAP_LEN_512, /*!< SF Ctrl wrap length: 512 */ + SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */ + SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */ + SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */ +} SF_Ctrl_Wrap_Len_Type; + +/** + * @brief Serial flash controller owner type definition + */ +typedef enum { + SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ + SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ +} SF_Ctrl_Owner_Type; + +/** + * @brief Serial flash controller select clock type definition + */ +typedef enum { + SF_CTRL_SAHB_CLOCK, /*!< Serial flash controller select default sahb clock */ + SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */ +} SF_Ctrl_Sahb_Type; + +/** + * @brief Serial flash controller owner type definition + */ +typedef enum { + HIGH_SPEED_MODE_CLOCK, /*!< Serial flash controller high speed mode clk_ahb>clk_sf */ + REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */ +} SF_Ctrl_Ahb2sif_Type; + +/** + * @brief Read and write type definition + */ +typedef enum { + SF_CTRL_READ, /*!< Serail flash read command flag */ + SF_CTRL_WRITE, /*!< Serail flash write command flag */ +} SF_Ctrl_RW_Type; + +/** + * @brief Serail flash interface IO type definition + */ +typedef enum { + SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ + SF_CTRL_DO_MODE, /*!< Dual Output mode define */ + SF_CTRL_QO_MODE, /*!< Quad Output mode define */ + SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ + SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ +} SF_Ctrl_IO_Type; + +/** + * @brief Serail flash controller interface mode type definition + */ +typedef enum { + SF_CTRL_SPI_MODE, /*!< SPI mode define */ + SF_CTRL_QPI_MODE, /*!< QPI mode define */ +} SF_Ctrl_Mode_Type; + +/** + * @brief Serail flash controller command mode type definition + */ +typedef enum { + SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ + SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ +} SF_Ctrl_Cmd_Mode_Type; + +/** + * @brief Serail flash controller address mode type definition + */ +typedef enum { + SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ + SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ + SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ +} SF_Ctrl_Addr_Mode_Type; + +/** + * @brief Serail flash controller dummy mode type definition + */ +typedef enum { + SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ + SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ + SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ +} SF_Ctrl_Dmy_Mode_Type; + +/** + * @brief Serail flash controller data mode type definition + */ +typedef enum { + SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ + SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ + SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ +} SF_Ctrl_Data_Mode_Type; + +/** + * @brief Serail flash controller AES type definition + */ +typedef enum { + SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ + SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ + SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ + SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ +} SF_Ctrl_AES_Key_Type; + +/** + * @brief Serail flash controller configuration structure type definition + */ +typedef struct +{ + SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ + SF_Ctrl_Sahb_Type sahbClock; /*!< Sflash clock sahb sram select */ + SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */ + uint8_t clkDelay; /*!< Clock count for read due to pad delay */ + uint8_t clkInvert; /*!< Clock invert */ + uint8_t rxClkInvert; /*!< RX clock invert */ + uint8_t doDelay; /*!< Data out delay */ + uint8_t diDelay; /*!< Data in delay */ + uint8_t oeDelay; /*!< Output enable delay */ +} SF_Ctrl_Cfg_Type; + +/** + * @brief SF Ctrl psram controller configuration structure type definition + */ +typedef struct +{ + SF_Ctrl_Owner_Type owner; /*!< Psram interface bus owner */ + SF_Ctrl_Pad_Select padSel; /*!< SF Ctrl pad select */ + SF_Ctrl_Select bankSel; /*!< SF Ctrl bank select */ + BL_Fun_Type psramRxClkInvertSrc; /*!< Select psram rx clock invert source */ + BL_Fun_Type psramRxClkInvertSel; /*!< Select inveted psram rx clock */ + BL_Fun_Type psramDelaySrc; /*!< Select psram read delay source */ + uint8_t psramClkDelay; /*!< Psram read delay cycle = n + 1 */ +} SF_Ctrl_Psram_Cfg; + +/** + * @brief SF Ctrl cmds configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type cmdsEn; /*!< SF Ctrl cmds enable */ + BL_Fun_Type burstToggleEn; /*!< SF Ctrl burst toggle mode enable */ + BL_Fun_Type wrapModeEn; /*!< SF Ctrl wrap mode cmd enable */ + SF_Ctrl_Wrap_Len_Type wrapLen; /*!< SF Ctrl wrap length */ +} SF_Ctrl_Cmds_Cfg; + +/** + * @brief Serail flash command configuration structure type definition + */ +typedef struct +{ + uint8_t rwFlag; /*!< Read write flag */ + SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ + SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ + uint8_t addrSize; /*!< Address size */ + uint8_t dummyClks; /*!< Dummy clocks */ + SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ + SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ + uint8_t rsv[1]; /*!< */ + uint32_t nbData; /*!< Transfer number of bytes */ + uint32_t cmdBuf[2]; /*!< Command buffer */ +} SF_Ctrl_Cmd_Cfg_Type; + +/*@} end of group SF_CTRL_Public_Types */ + +/** @defgroup SF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup SF_CTRL_PAD_SELECT + * @{ + */ +#define IS_SF_CTRL_PAD_SELECT(type) (((type) == SF_CTRL_PAD_SEL_SF1) || \ + ((type) == SF_CTRL_PAD_SEL_SF2) || \ + ((type) == SF_CTRL_PAD_SEL_SF3) || \ + ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2) || \ + ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF2_SF3) || \ + ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1) || \ + ((type) == SF_CTRL_PAD_SEL_DUAL_CS_SF2) || \ + ((type) == SF_CTRL_PAD_SEL_DUAL_CS_SF3)) + +/** @defgroup SF_CTRL_SELECT + * @{ + */ +#define IS_SF_CTRL_SELECT(type) (((type) == SF_CTRL_SEL_FLASH) || \ + ((type) == SF_CTRL_SEL_PSRAM)) + +/** @defgroup SF_CTRL_WRAP_LEN_TYPE + * @{ + */ +#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) || \ + ((type) == SF_CTRL_WRAP_LEN_16) || \ + ((type) == SF_CTRL_WRAP_LEN_32) || \ + ((type) == SF_CTRL_WRAP_LEN_64) || \ + ((type) == SF_CTRL_WRAP_LEN_128) || \ + ((type) == SF_CTRL_WRAP_LEN_256) || \ + ((type) == SF_CTRL_WRAP_LEN_512) || \ + ((type) == SF_CTRL_WRAP_LEN_1024) || \ + ((type) == SF_CTRL_WRAP_LEN_2048) || \ + ((type) == SF_CTRL_WRAP_LEN_4096)) + +/** @defgroup SF_CTRL_OWNER_TYPE + * @{ + */ +#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ + ((type) == SF_CTRL_OWNER_IAHB)) + +/** @defgroup SF_CTRL_SAHB_TYPE + * @{ + */ +#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \ + ((type) == SF_CTRL_FLASH_CLOCK)) + +/** @defgroup SF_CTRL_AHB2SIF_TYPE + * @{ + */ +#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \ + ((type) == REMOVE_CLOCK_CONSTRAIN)) + +/** @defgroup SF_CTRL_RW_TYPE + * @{ + */ +#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ + ((type) == SF_CTRL_WRITE)) + +/** @defgroup SF_CTRL_IO_TYPE + * @{ + */ +#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ + ((type) == SF_CTRL_DO_MODE) || \ + ((type) == SF_CTRL_QO_MODE) || \ + ((type) == SF_CTRL_DIO_MODE) || \ + ((type) == SF_CTRL_QIO_MODE)) + +/** @defgroup SF_CTRL_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ + ((type) == SF_CTRL_QPI_MODE)) + +/** @defgroup SF_CTRL_CMD_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ + ((type) == SF_CTRL_CMD_4_LINES)) + +/** @defgroup SF_CTRL_ADDR_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ + ((type) == SF_CTRL_ADDR_2_LINES) || \ + ((type) == SF_CTRL_ADDR_4_LINES)) + +/** @defgroup SF_CTRL_DMY_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ + ((type) == SF_CTRL_DUMMY_2_LINES) || \ + ((type) == SF_CTRL_DUMMY_4_LINES)) + +/** @defgroup SF_CTRL_DATA_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ + ((type) == SF_CTRL_DATA_2_LINES) || \ + ((type) == SF_CTRL_DATA_4_LINES)) + +/** @defgroup SF_CTRL_AES_KEY_TYPE + * @{ + */ +#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ + ((type) == SF_CTRL_AES_256BITS) || \ + ((type) == SF_CTRL_AES_192BITS) || \ + ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) + +/*@} end of group SF_CTRL_Public_Constants */ + +/** @defgroup SF_CTRL_Public_Macros + * @{ + */ +#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF +#define FLASH_CTRL_BUF_SIZE 256 + +/*@} end of group SF_CTRL_Public_Macros */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SF_Ctrl_IRQHandler(void); +#endif +void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); +void SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *psramCfg); +uint8_t SF_Ctrl_Get_Clock_Delay(void); +void SF_Ctrl_Set_Clock_Delay(uint8_t delay); +void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg); +void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel); +void SF_Ctrl_Select_Bank(SF_Ctrl_Select sel); +void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); +void SF_Ctrl_Disable(void); +void SF_Ctrl_AES_Enable_BE(void); +void SF_Ctrl_AES_Enable_LE(void); +void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, + uint32_t endAddr, + uint8_t locked); +void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); +void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); +void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); +void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); +void SF_Ctrl_AES_Enable(void); +void SF_Ctrl_AES_Disable(void); +uint8_t SF_Ctrl_Is_AES_Enable(void); +void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset); +uint32_t SF_Ctrl_Get_Flash_Image_Offset(void); +void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType); +void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); +void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); +void SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); +void SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); +BL_Sts_Type SF_Ctrl_GetBusyState(void); + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_SF_CTRL_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash.h new file mode 100644 index 0000000000000000000000000000000000000000..a907b4d2047b8b6a1ca87b02357f79833358ba99 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash.h @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file bl702_sflah.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_SFLAH_H__ +#define __BL702_SFLAH_H__ + +#include "bl702_common.h" +#include "bl702_sf_ctrl.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH + * @{ + */ + +/** @defgroup SFLAH_Public_Types + * @{ + */ + +/** + * @brief Serial flash configuration structure type definition + */ +typedef struct +{ + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */ + uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +} __attribute__((packed)) SPI_Flash_Cfg_Type; + +/*@} end of group SFLAH_Public_Types */ + +/** @defgroup SFLAH_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_Public_Constants */ + +/** @defgroup SFLAH_Public_Macros + * @{ + */ +#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) +#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) +#define BFLB_SPIFLASH_CMD_INVALID 0xff + +/*@} end of group SFLAH_Public_Macros */ + +/** @defgroup SFLAH_Public_Functions + * @{ + */ +void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg); +BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode); +BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); +BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); +BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, + uint8_t regLen); +BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, + uint8_t regLen); +BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum); +BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); +BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); +BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr); +BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); +void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen); +void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data); +void SFlash_GetDeviceId(uint8_t *data); +void SFlash_Powerdown(void); +void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead); +void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, + uint32_t len); +BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead); +BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, + uint8_t wayDisable); +void SFlash_Cache_Read_Disable(void); +BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead); +BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, + uint32_t len); + +/*@} end of group SFLAH_Public_Functions */ + +/*@} end of group SFLAH */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_SFLAH_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..e3a5ecfd25d8c16e3a11df49b08a126be536b610 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file bl702_sflah_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_SFLAH_EXT_H__ +#define __BL702_SFLAH_EXT_H__ + +#include "bl702_sflash.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH_EXT + * @{ + */ + +/** @defgroup SFLAH_EXT_Public_Types + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Types */ + +/** @defgroup SFLAH_EXT_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Constants */ + +/** @defgroup SFLAH_EXT_Public_Macros + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Macros */ + +/** @defgroup SFLAH_EXT_Public_Functions + * @{ + */ +BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, + uint8_t regLen); +BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, + uint8_t regLen); + +/*@} end of group SFLAH_EXT_Public_Functions */ + +/*@} end of group SFLAH_EXT */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_SFLAH_EXT_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_snflash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_snflash.h new file mode 100644 index 0000000000000000000000000000000000000000..0974d5518a2933288dceafbd871b836afd882657 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_snflash.h @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file bl702_snflash.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef NANDFLASH_XT26G01A_H +#define NANDFLASH_XT26G01A_H + +#include "bl702_aon.h" +#include "bl702_common.h" +#include "bl702_glb.h" +#include "bl702_hbn.h" +#include "bl702_spi.h" +#include "bl702_gpio.h" + +#include "ffconf.h" +#include "ff.h" +#include "diskio.h" + +#define FLASH_WRITE_READ_SIZE (2560) +#define READ_PRINT_OPEN (0) + +#define SPI_PIN_CLK GLB_GPIO_PIN_11 +#define SPI_PIN_MOSI GLB_GPIO_PIN_12 +#define SPI_PIN_MISO GLB_GPIO_PIN_21 +#define SPI_PIN_CS GLB_GPIO_PIN_10 + +#define NANDFLASH_WRITE_ENABLE (0x06) +#define NANDFLASH_WRITE_DISABLE (0x04) +#define NANDFLASH_GET_FEATURES (0x0F) +#define NANDFLASH_SET_FEATURES (0x1F) +#define NANDFLASH_PAGE_READ_TO_CACHE (0x13) +#define NANDFLASH_READ_FROM_CACHE (0x03) +#define NANDFLASH_READ_ID (0x9F) +#define NANDFLASH_PROGRAM_LOAD (0x02) +#define NANDFLASH_PROGRAM_LOAD_RANDOM_DATA (0x84) +#define NANDFLASH_PROGRAM_EXECUTE (0x10) +#define NANDFLASH_BLOCK_ERASE (0xD8) +#define NANDFLASH_RESET (0xFF) + +#define NANDFLASH_BLOCK_LOCK_ADDR (0xA0) +#define NANDFLASH_FEATURE_ADDR (0xB0) +#define NANDFLASH_STATUS_ADDR (0xC0) +#define NANDFLASH_DUMMY_BYTE (0x00) +#define NANDFLASH_PAGE_SIZE (2048) +#define NANDFLASH_PAGE_TOTAL_SIZE (2048 + 64) +#define NANDFLASH_BLOCK_SIZE (128 * 1024) +#define NANDFLASH_PAGES_PER_BLOCK (64) + +typedef struct +{ + SPI_ID_Type spiNo; + SPI_CFG_Type spiCfg; + SPI_ClockCfg_Type clockCfg; +} NANDFLASH_CFG_Type; + +extern NANDFLASH_CFG_Type nfCfg; + +typedef struct +{ + uint8_t Reserved0 : 1; + uint8_t CMP : 1; + uint8_t INV : 1; + uint8_t BP0 : 1; + uint8_t BP1 : 1; + uint8_t BP2 : 1; + uint8_t Reserved6 : 1; + uint8_t BRWD : 1; +} NANDFLASH_BLOCK_LOCK_Type; + +typedef struct +{ + uint8_t QE : 1; + uint8_t Reserved1 : 1; + uint8_t Reserved2 : 1; + uint8_t Reserved3 : 1; + uint8_t ECC_EN : 1; + uint8_t Reserved5 : 1; + uint8_t OTP_EN : 1; + uint8_t OTP_PRT : 1; +} NANDFLASH_FEATURE_Type; + +typedef struct +{ + uint8_t OIP : 1; + uint8_t WEL : 1; + uint8_t EFAIL_ECCS0 : 1; + uint8_t PFAIL_ECCS1 : 1; + uint8_t ECCS2 : 1; + uint8_t ECCS3 : 1; + uint8_t Reserved6 : 1; + uint8_t Reserved7 : 1; +} NANDFLASH_STATUS_Type; + +typedef enum { + NO_BIT_ERROR = 0, + ONE_BIT_ERROR_DETECTED_AND_CORRECTED = 1, + TWO_BIT_ERROR_DETECTED_AND_CORRECTED = 2, + THREE_BIT_ERROR_DETECTED_AND_CORRECTED = 3, + FOUR_BIT_ERROR_DETECTED_AND_CORRECTED = 4, + FIVE_BIT_ERROR_DETECTED_AND_CORRECTED = 5, + SIX_BIT_ERROR_DETECTED_AND_CORRECTED = 6, + SEVEN_BIT_ERROR_DETECTED_AND_CORRECTED = 7, + BIT_ERROR_DETECTED_AND_NOT_CORRECTED = 8, + EIGHT_BIT_ERROR_DETECTED_AND_CORRECTED_MAX = 9 +} NANDFLASH_ECC_Type; + +void ATTR_TCM_SECTION Nandflash_Psram_Cfg(void); +void Nandflash_Init(void); + +void Nandflash_Gpio_Init(GLB_GPIO_Type clk, GLB_GPIO_Type mosi, GLB_GPIO_Type miso); +void Nandflash_CS_High(void); +void Nandflash_CS_Low(void); +void Nandflash_Clock_Init(uint8_t enable, uint8_t div); +void Nandflash_SPI_Init(NANDFLASH_CFG_Type *pNandflashCfg); + +void Nandflash_WriteEnable(NANDFLASH_CFG_Type *pNandflashCfg); +void Nandflash_WriteDisable(NANDFLASH_CFG_Type *pNandflashCfg); +void Nandflash_Get_BlockLock(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pBlockLock); +void Nandflash_Set_BlockLock(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pBlockLock); +void Nandflash_Get_Feature(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pFeature); +void Nandflash_Set_Feature(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pFeature); +void Nandflash_Get_Status(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pStatus); +void Nandflash_Set_Status(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pStatus); + +NANDFLASH_ECC_Type Nandflash_CheckBadBlock(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum, uint8_t *buff, uint32_t len); + +NANDFLASH_ECC_Type Nandflash_PagesRead(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len); +NANDFLASH_ECC_Type Nandflash_PageRead(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len); +NANDFLASH_ECC_Type Nandflash_PageReadToCache(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr); +void Nandflash_ReadFromCache(NANDFLASH_CFG_Type *pNandflashCfg, uint16_t offset, uint8_t *buff, uint32_t len); + +void Nandflash_ReadID(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pManufactureID, uint8_t *pDeviceID); +void Nandflash_PagesProgram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, const uint8_t *buff, uint32_t len); +void Nandflash_PageProgram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, const uint8_t *buff, uint32_t len); +void Nandflash_ProgramLoad(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t pageOffset, const uint8_t *buff, uint32_t len); +void Nandflash_ProgramExecute(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr); +void Nandflash_InternalDataMove(NANDFLASH_CFG_Type *pNandflashCfg); +void Nandflash_ProgramLoadRandomData(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len); +void Nandflash_BlockErase(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr); +void Nandflash_Reset(NANDFLASH_CFG_Type *pNandflashCfg); + +void Nandflash_WriteUnprotect(NANDFLASH_CFG_Type *pNandflashCfg); +NANDFLASH_ECC_Type Nandflash_Check_ECC_Status(NANDFLASH_CFG_Type *pNandflashCfg); + +int Nandflash_Disk_Status(void); +int Nandflash_Disk_Initialize(void); +int Nandflash_Disk_Read(BYTE *buff, LBA_t sector, UINT count); +int Nandflash_Disk_Write(const BYTE *buff, LBA_t sector, UINT count); +int Nandflash_Disk_Ioctl(BYTE cmd, void *buff); +DSTATUS Nandflash_Translate_Result_Code(int result); + +#endif diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_spi.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..a3276bbf5a615e0a82f21e141d9064f0a9f89170 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_spi.h @@ -0,0 +1,317 @@ +/** + ****************************************************************************** + * @file bl702_spi.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_SPI_H__ +#define __BL702_SPI_H__ + +#include "spi_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types + * @{ + */ + +/** + * @brief SPI No. type definition + */ +typedef enum { + SPI_ID_0, /*!< SPI0 port define */ + SPI_ID_MAX, /*!< SPI MAX ID define */ +} SPI_ID_Type; + +/** + * @brief SPI byte inverse type definition + */ +typedef enum { + SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */ + SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */ +} SPI_BYTE_INVERSE_Type; + +/** + * @brief SPI bit inverse type definition + */ +typedef enum { + SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */ + SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */ +} SPI_BIT_INVERSE_Type; + +/** + * @brief SPI clock phase inverse type definition + */ +typedef enum { + SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */ + SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */ +} SPI_CLK_PHASE_INVERSE_Type; + +/** + * @brief SPI clock polarity type definition + */ +typedef enum { + SPI_CLK_POLARITY_LOW, /*!< SPI clock output low at IDLE state */ + SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */ +} SPI_CLK_POLARITY_Type; + +/** + * @brief SPI frame size(also the valid width for each fifo entry) type definition + */ +typedef enum { + SPI_FRAME_SIZE_8, /*!< SPI frame size 8 bit */ + SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */ + SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */ + SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */ +} SPI_FrameSize_Type; + +/** + * @brief SPI work mode select type definition + */ +typedef enum { + SPI_WORK_MODE_SLAVE, /*!< SPI work at slave mode */ + SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */ +} SPI_WORK_MODE_Type; + +/** + * @brief SPI enable or disable timeout judgment definition + */ +typedef enum { + SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */ + SPI_TIMEOUT_ENABLE, /*!< SPI enable timeout judgment */ +} SPI_Timeout_Type; + +/** + * @brief SPI fifo overflow/underflow flag type definition + */ +typedef enum { + SPI_FIFO_TX_OVERFLOW, /*!< SPI tx fifo overflow flag */ + SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */ + SPI_FIFO_RX_OVERFLOW, /*!< SPI rx fifo overflow flag */ + SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */ +} SPI_FifoStatus_Type; + +/** + * @brief SPI interrupt type definition + */ +typedef enum { + SPI_INT_END, /*!< SPI transfer end interrupt,shared by both master and slave mode */ + SPI_INT_TX_FIFO_REQ, /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */ + SPI_INT_RX_FIFO_REQ, /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */ + SPI_INT_SLAVE_TIMEOUT, /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */ + SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */ + SPI_INT_FIFO_ERROR, /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */ + SPI_INT_ALL, /*!< All the interrupt */ +} SPI_INT_Type; + +/** + * @brief SPI configuration type definition + */ +typedef struct +{ + BL_Fun_Type deglitchEnable; /*!< Enable or disable de-glitch function */ + BL_Fun_Type continuousEnable; /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */ + SPI_BYTE_INVERSE_Type byteSequence; /*!< The byte is sent first in SPI transfer */ + SPI_BIT_INVERSE_Type bitSequence; /*!< The bit is sent first in SPI transfer */ + SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */ + SPI_CLK_POLARITY_Type clkPolarity; /*!< SPI clock plarity */ + SPI_FrameSize_Type frameSize; /*!< SPI frame size(also the valid width for each fifo entry) */ +} SPI_CFG_Type; + +/** + * @brief SPI configuration type definition + */ +typedef struct +{ + uint8_t startLen; /*!< Length of start condition */ + uint8_t stopLen; /*!< Length of stop condition */ + uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */ + uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */ + uint8_t intervalLen; /*!< Length of interval between frame */ +} SPI_ClockCfg_Type; + +/** + * @brief SPI DMA configuration type definition + */ +typedef struct +{ + uint8_t txFifoThreshold; /*!< SPI tx FIFO threshold */ + uint8_t rxFifoThreshold; /*!< SPI rx FIFO threshold */ + BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ + BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ +} SPI_FifoCfg_Type; + +/*@} end of group SPI_Public_Types */ + +/** @defgroup SPI_Public_Constants + * @{ + */ + +/** @defgroup SPI_ID_TYPE + * @{ + */ +#define IS_SPI_ID_TYPE(type) (((type) == SPI_ID_0) || \ + ((type) == SPI_ID_MAX)) + +/** @defgroup SPI_BYTE_INVERSE_TYPE + * @{ + */ +#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \ + ((type) == SPI_BYTE_INVERSE_BYTE3_FIRST)) + +/** @defgroup SPI_BIT_INVERSE_TYPE + * @{ + */ +#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \ + ((type) == SPI_BIT_INVERSE_LSB_FIRST)) + +/** @defgroup SPI_CLK_PHASE_INVERSE_TYPE + * @{ + */ +#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \ + ((type) == SPI_CLK_PHASE_INVERSE_1)) + +/** @defgroup SPI_CLK_POLARITY_TYPE + * @{ + */ +#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \ + ((type) == SPI_CLK_POLARITY_HIGH)) + +/** @defgroup SPI_FRAMESIZE_TYPE + * @{ + */ +#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) || \ + ((type) == SPI_FRAME_SIZE_16) || \ + ((type) == SPI_FRAME_SIZE_24) || \ + ((type) == SPI_FRAME_SIZE_32)) + +/** @defgroup SPI_WORK_MODE_TYPE + * @{ + */ +#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \ + ((type) == SPI_WORK_MODE_MASTER)) + +/** @defgroup SPI_TIMEOUT_TYPE + * @{ + */ +#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \ + ((type) == SPI_TIMEOUT_ENABLE)) + +/** @defgroup SPI_FIFOSTATUS_TYPE + * @{ + */ +#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) || \ + ((type) == SPI_FIFO_TX_UNDERFLOW) || \ + ((type) == SPI_FIFO_RX_OVERFLOW) || \ + ((type) == SPI_FIFO_RX_UNDERFLOW)) + +/** @defgroup SPI_INT_TYPE + * @{ + */ +#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) || \ + ((type) == SPI_INT_TX_FIFO_REQ) || \ + ((type) == SPI_INT_RX_FIFO_REQ) || \ + ((type) == SPI_INT_SLAVE_TIMEOUT) || \ + ((type) == SPI_INT_SLAVE_UNDERRUN) || \ + ((type) == SPI_INT_FIFO_ERROR) || \ + ((type) == SPI_INT_ALL)) + +/*@} end of group SPI_Public_Constants */ + +/** @defgroup SPI_Public_Macros + * @{ + */ +#define SPI_RX_FIFO_SIZE 4 +#define SPI_TX_FIFO_SIZE 4 + +/*@} end of group SPI_Public_Macros */ + +/** @defgroup SPI_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SPI_IRQHandler(void); +#endif +BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg); +BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo); +BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk); +BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg); +BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg); +BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType); +BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType); +BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value); +BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt); +BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint); +BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType); +BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, uint32_t data); +BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo, uint16_t *sendBuff, uint16_t *recvBuff, uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, + SPI_Timeout_Type timeoutType); +uint32_t SPI_ReceiveData(SPI_ID_Type spiNo); +uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo); +uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo); +BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType); +BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts); +BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo); + +/*@} end of group SPI_Public_Functions */ + +/*@} end of group SPI */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_SPI_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_timer.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..b125c67b86f84dceddecebba38e1853b7ae5eea9 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_timer.h @@ -0,0 +1,247 @@ +/** + ****************************************************************************** + * @file bl702_timer.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_TIMER_H__ +#define __BL702_TIMER_H__ + +#include "timer_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Public_Types + * @{ + */ + +/** + * @brief TIMER channel type definition + */ +typedef enum { + TIMER_CH0, /*!< TIMER channel 0 port define */ + TIMER_CH1, /*!< TIMER channel 1 port define */ + TIMER_CH_MAX, /*!< */ +} TIMER_Chan_Type; + +/** + * @brief TIMER clock source type definition + */ +typedef enum { + TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */ + TIMER_CLKSRC_32K, /*!< TIMER clock source :32K CLK */ + TIMER_CLKSRC_1K, /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */ + TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */ +} TIMER_ClkSrc_Type; + +/** + * @brief TIMER match compare ID type definition + */ +typedef enum { + TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */ + TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */ + TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */ +} TIMER_Comp_ID_Type; + +/** + * @brief TIMER preload source type definition + */ +typedef enum { + TIMER_PRELOAD_TRIG_NONE, /*!< TIMER no preload source, just free run */ + TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */ + TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */ + TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */ +} TIMER_PreLoad_Trig_Type; + +/** + * @brief TIMER count register run mode type definition + */ +typedef enum { + TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */ + TIMER_COUNT_FREERUN, /*!< TIMER count register free run */ +} TIMER_CountMode_Type; + +/** + * @brief TIMER interrupt type definition + */ +typedef enum { + TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */ + TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */ + TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */ + TIMER_INT_ALL, /*!< */ +} TIMER_INT_Type; + +/** + * @brief Watchdog timer interrupt type definition + */ +typedef enum { + WDT_INT, /*!< Comparator 0 match cause interrupt */ + WDT_INT_ALL, /*!< */ +} WDT_INT_Type; + +/** + * @brief TIMER configuration structure type definition + */ +typedef struct +{ + TIMER_Chan_Type timerCh; /*!< Timer channel */ + TIMER_ClkSrc_Type clkSrc; /*!< Timer clock source */ + TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */ + TIMER_CountMode_Type countMode; /*!< Timer count mode */ + uint8_t clockDivision; /*!< Timer clock divison value */ + uint32_t matchVal0; /*!< Timer match 0 value 0 */ + uint32_t matchVal1; /*!< Timer match 1 value 0 */ + uint32_t matchVal2; /*!< Timer match 2 value 0 */ + uint32_t preLoadVal; /*!< Timer preload value */ +} TIMER_CFG_Type; + +/*@} end of group TIMER_Public_Types */ + +/** @defgroup TIMER_Public_Constants + * @{ + */ + +/** @defgroup TIMER_CHAN_TYPE + * @{ + */ +#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \ + ((type) == TIMER_CH1) || \ + ((type) == TIMER_CH_MAX)) + +/** @defgroup TIMER_CLKSRC_TYPE + * @{ + */ +#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \ + ((type) == TIMER_CLKSRC_32K) || \ + ((type) == TIMER_CLKSRC_1K) || \ + ((type) == TIMER_CLKSRC_XTAL)) + +/** @defgroup TIMER_COMP_ID_TYPE + * @{ + */ +#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \ + ((type) == TIMER_COMP_ID_1) || \ + ((type) == TIMER_COMP_ID_2)) + +/** @defgroup TIMER_PRELOAD_TRIG_TYPE + * @{ + */ +#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP0) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP1) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP2)) + +/** @defgroup TIMER_COUNTMODE_TYPE + * @{ + */ +#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \ + ((type) == TIMER_COUNT_FREERUN)) + +/** @defgroup TIMER_INT_TYPE + * @{ + */ +#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \ + ((type) == TIMER_INT_COMP_1) || \ + ((type) == TIMER_INT_COMP_2) || \ + ((type) == TIMER_INT_ALL)) + +/** @defgroup WDT_INT_TYPE + * @{ + */ +#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \ + ((type) == WDT_INT_ALL)) + +/*@} end of group TIMER_Public_Constants */ + +/** @defgroup TIMER_Public_Macros + * @{ + */ +#define WDT_ENABLE_ACCESS() \ + { \ + BL_WR_REG(TIMER_BASE, TIMER_WFAR, BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \ + BL_WR_REG(TIMER_BASE, TIMER_WSAR, BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \ + } + +/*@} end of group TIMER_Public_Macros */ + +/** @defgroup TIMER_Public_Functions + * @{ + */ + +/** + * @brief UART Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH0_IRQHandler(void); +void TIMER_CH1_IRQHandler(void); +void TIMER_WDT_IRQHandler(void); +#endif +BL_Err_Type TIMER_Init(TIMER_CFG_Type *timerCfg); +uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val); +uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh); +BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh); +void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val); +void TIMER_SetPreloadSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc); +void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode); +void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +void TIMER_Enable(TIMER_Chan_Type timerCh); +void TIMER_Disable(TIMER_Chan_Type timerCh); +void TIMER_IntMask(TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask); +void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc, uint8_t div); +uint16_t WDT_GetMatchValue(void); +void WDT_SetCompValue(uint16_t val); +uint16_t WDT_GetCounterValue(void); +void WDT_ResetCounterValue(void); +BL_Sts_Type WDT_GetResetStatus(void); +void WDT_ClearResetStatus(void); +void WDT_Enable(void); +void WDT_Disable(void); +void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask); +void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun); +void WDT_Int_Callback_Install(WDT_INT_Type wdtInt, intCallback_Type *cbFun); + +/*@} end of group TIMER_Public_Functions */ + +/*@} end of group TIMER */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_TIMER_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_uart.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..5b81c1573f7451d66241a73e4fe7cb1f1b0c2a5b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_uart.h @@ -0,0 +1,326 @@ +/** + ****************************************************************************** + * @file bl702_uart.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_UART_H__ +#define __BL702_UART_H__ + +#include "uart_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_Public_Types + * @{ + */ + +/** + * @brief UART port type definition + */ +typedef enum { + UART0_ID, /*!< UART0 port define */ + UART1_ID, /*!< UART1 port define */ + UART_ID_MAX, /*!< UART MAX ID define */ +} UART_ID_Type; + +/** + * @brief UART direction type definition + */ +typedef enum { + UART_TX, /*!< UART TX Direction */ + UART_RX, /*!< UART RX Direction */ + UART_TXRX, /*!< UART TX and RX Direction */ +} UART_Direction_Type; + +/** + * @brief UART parity type definition + */ +typedef enum { + UART_PARITY_NONE, /*!< UART parity none define */ + UART_PARITY_ODD, /*!< UART parity odd define */ + UART_PARITY_EVEN, /*!< UART parity even define */ +} UART_Parity_Type; + +/** + * @brief UART data bits type definiton + */ +typedef enum { + UART_DATABITS_5, /*!< UART data bits length:5 bits */ + UART_DATABITS_6, /*!< UART data bits length:6 bits */ + UART_DATABITS_7, /*!< UART data bits length:7 bits */ + UART_DATABITS_8, /*!< UART data bits length:8 bits */ +} UART_DataBits_Type; + +/** + * @brief UART stop bits type definiton + */ +typedef enum { + UART_STOPBITS_0_5, /*!< UART data stop bits length:0.5 bits */ + UART_STOPBITS_1, /*!< UART data stop bits length:1 bits */ + UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */ + UART_STOPBITS_2, /*!< UART data stop bits length:2 bits */ +} UART_StopBits_Type; + +/** + * @brief UART each data byte is send out LSB-first or MSB-first type definiton + */ +typedef enum { + UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */ + UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */ +} UART_ByteBitInverse_Type; + +/** + * @brief UART auto baudrate detection using codeword 0x55 or start bit definiton + */ +typedef enum { + UART_AUTOBAUD_0X55, /*!< UART auto baudrate detection using codeword 0x55 */ + UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */ +} UART_AutoBaudDetection_Type; + +/** + * @brief UART interrupt type definition + */ +typedef enum { + UART_INT_TX_END, /*!< UART tx transfer end interrupt */ + UART_INT_RX_END, /*!< UART rx transfer end interrupt */ + UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */ + UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */ + UART_INT_RTO, /*!< UART rx time-out interrupt */ + UART_INT_PCE, /*!< UART rx parity check error interrupt */ + UART_INT_TX_FER, /*!< UART tx fifo overflow/underflow error interrupt */ + UART_INT_RX_FER, /*!< UART rx fifo overflow/underflow error interrupt */ + UART_INT_LSE, /*!< UART rx lin mode sync field error interrupt */ + UART_INT_ALL, /*!< All the interrupt */ +} UART_INT_Type; + +/** + * @brief UART overflow or underflow type definition + */ +typedef enum { + UART_TX_OVERFLOW, /*!< UART tx fifo overflow */ + UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */ + UART_RX_OVERFLOW, /*!< UART rx fifo overflow */ + UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */ +} UART_Overflow_Type; + +/** + * @brief UART configuration structure type definition + */ +typedef struct +{ + uint32_t uartClk; /*!< Uart module clock */ + uint32_t baudRate; /*!< Uart baudrate */ + UART_DataBits_Type dataBits; /*!< Uart frame length of data bit */ + UART_StopBits_Type stopBits; /*!< Uart frame length of stop bit */ + UART_Parity_Type parity; /*!< Uart parity check type */ + BL_Fun_Type ctsFlowControl; /*!< Enable or disable tx CTS flow control */ + BL_Fun_Type rxDeglitch; /*!< Enable or disable rx input de-glitch function */ + BL_Fun_Type rtsSoftwareControl; /*!< Enable or disable rx RTS output SW control mode */ + BL_Fun_Type txSoftwareControl; /*!< Enable or disable tx output SW control mode */ + BL_Fun_Type txLinMode; /*!< Enable or disable tx LIN mode,LIN header will be sent before sending data */ + BL_Fun_Type rxLinMode; /*!< Enable or disable rx LIN mode,LIN header will be required and checked before receiving data */ + uint8_t txBreakBitCnt; /*!< Uart tx break bit count,additional 8 bit times will be added since LIN break field requires at + least 13 bit times */ + UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */ +} UART_CFG_Type; + +/** + * @brief UART FIFO configuration structure type definition + */ +typedef struct +{ + uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */ + uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */ + BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ + BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ +} UART_FifoCfg_Type; + +/** + * @brief UART infrared configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type txIrEnable; /*!< Enable or disable uart tx ir mode */ + BL_Fun_Type rxIrEnable; /*!< Enable or disable uart rx ir mode */ + BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */ + BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */ + uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */ + uint16_t txIrPulseStop; /*!< Set stop position of uart tx ir pulse */ + uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */ +} UART_IrCfg_Type; + +/*@} end of group UART_Public_Types */ + +/** @defgroup UART_Public_Constants + * @{ + */ + +/** @defgroup UART_ID_TYPE + * @{ + */ +#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \ + ((type) == UART1_ID) || \ + ((type) == UART_ID_MAX)) + +/** @defgroup UART_DIRECTION_TYPE + * @{ + */ +#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \ + ((type) == UART_RX) || \ + ((type) == UART_TXRX)) + +/** @defgroup UART_PARITY_TYPE + * @{ + */ +#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \ + ((type) == UART_PARITY_ODD) || \ + ((type) == UART_PARITY_EVEN)) + +/** @defgroup UART_DATABITS_TYPE + * @{ + */ +#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \ + ((type) == UART_DATABITS_6) || \ + ((type) == UART_DATABITS_7) || \ + ((type) == UART_DATABITS_8)) + +/** @defgroup UART_STOPBITS_TYPE + * @{ + */ +#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) || \ + ((type) == UART_STOPBITS_1_5) || \ + ((type) == UART_STOPBITS_2)) + +/** @defgroup UART_BYTEBITINVERSE_TYPE + * @{ + */ +#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \ + ((type) == UART_MSB_FIRST)) + +/** @defgroup UART_AUTOBAUDDETECTION_TYPE + * @{ + */ +#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \ + ((type) == UART_AUTOBAUD_STARTBIT)) + +/** @defgroup UART_INT_TYPE + * @{ + */ +#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) || \ + ((type) == UART_INT_RX_END) || \ + ((type) == UART_INT_TX_FIFO_REQ) || \ + ((type) == UART_INT_RX_FIFO_REQ) || \ + ((type) == UART_INT_RTO) || \ + ((type) == UART_INT_PCE) || \ + ((type) == UART_INT_TX_FER) || \ + ((type) == UART_INT_RX_FER) || \ + ((type) == UART_INT_LSE) || \ + ((type) == UART_INT_ALL)) + +/** @defgroup UART_OVERFLOW_TYPE + * @{ + */ +#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) || \ + ((type) == UART_TX_UNDERFLOW) || \ + ((type) == UART_RX_OVERFLOW) || \ + ((type) == UART_RX_UNDERFLOW)) + +/*@} end of group UART_Public_Constants */ + +/** @defgroup UART_Public_Macros + * @{ + */ +#define UART_RX_FIFO_SIZE 128 +#define UART_TX_FIFO_SIZE 128 +#define UART_DEFAULT_RECV_TIMEOUT 80 + +/*@} end of group UART_Public_Macros */ + +/** @defgroup UART_Public_Functions + * @{ + */ + +/** + * @brief UART Functions + */ +#if (!defined BFLB_USE_HAL_DRIVER) || (defined BFLB_EFLASH_LOADER) +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +#endif +BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg); +BL_Err_Type UART_DeInit(UART_ID_Type uartId); +BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg); +BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg); +BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct); +BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct); +BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length); +BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length); +BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time); +BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt); +BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet); +BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId); +BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId); +BL_Err_Type UART_SetTxValue(UART_ID_Type uartId); +BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId); +BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun); +BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud); +BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId); +BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId); +BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType); +BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len); +BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len); +uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen); +uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet); +uint8_t UART_GetTxFifoCount(UART_ID_Type uartId); +uint8_t UART_GetRxFifoCount(UART_ID_Type uartId); +BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType); +BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId); +BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId); +BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow); + +/*@} end of group UART_Public_Functions */ + +/*@} end of group UART */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_UART_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_usb.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_usb.h new file mode 100644 index 0000000000000000000000000000000000000000..fb1f535c48555e89ea5c1247c72f6a6c65b402bb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_usb.h @@ -0,0 +1,423 @@ +/** + ****************************************************************************** + * @file bl702_usb.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_USB_H__ +#define __BL702_USB_H__ + +#include "usb_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup USB + * @{ + */ + +/** @defgroup USB_Public_Types + * @{ + */ + +/** + * @brief USB end point ID + */ +typedef enum { + EP_ID0 = 0, /*!< USB end point 0 */ + EP_ID1, /*!< USB end point 1 */ + EP_ID2, /*!< USB end point 2 */ + EP_ID3, /*!< USB end point 3 */ + EP_ID4, /*!< USB end point 4 */ + EP_ID5, /*!< USB end point 5 */ + EP_ID6, /*!< USB end point 6 */ + EP_ID7, /*!< USB end point 7 */ +} USB_EP_ID; + +/** + * @brief USB end point type + */ +typedef enum { + EP_INT = 0, /*!< interrupt transfer ep */ + EP_ISO = 2, /*!< isochronous transfer ep */ + EP_BULK = 4, /*!< bulk transfer ep */ + EP_CTRL = 5, /*!< control transfer ep */ +} EP_XFER_Type; + +/** + * @brief USB end point transfer directions + */ +typedef enum { + EP_DISABLED = 0, /*!< end point disabled */ + EP_IN = 1, /*!< IN end point,device to host */ + EP_OUT = 2, /*!< OUT end point ,host to device */ +} EP_XFER_DIR; + +typedef enum { + USB_INT_SOF = 0, + USB_INT_RESET, + USB_INT_VBUS_TGL, + USB_INT_GET_DCT_CMD, + USB_INT_EP0_SETUP_CMD, + USB_INT_EP0_SETUP_DONE, + USB_INT_EP0_IN_CMD, + USB_INT_EP0_IN_DONE, + USB_INT_EP0_OUT_CMD, + USB_INT_EP0_OUT_DONE, + USB_INT_EP1_CMD, + USB_INT_EP1_DONE, + USB_INT_EP2_CMD, + USB_INT_EP2_DONE, + USB_INT_EP3_CMD, + USB_INT_EP3_DONE, + USB_INT_EP4_CMD, + USB_INT_EP4_DONE, + USB_INT_EP5_CMD, + USB_INT_EP5_DONE, + USB_INT_EP6_CMD, + USB_INT_EP6_DONE, + USB_INT_EP7_CMD, + USB_INT_EP7_DONE, + USB_INT_RESET_END = 27, + USB_INT_LPM_WAKEUP = 28, + USB_INT_LPM_PACKET = 29, + USB_INT_LOST_SOF_3_TIMES = 30, + USB_INT_ERROR = 31, + USB_INT_ALL = 32, /* special */ +} USB_INT_Type; + +typedef enum { + USB_FIFO_EMPTY = 0, + USB_FIFO_FULL, +} USB_FIFO_STATUS_Type; + +typedef enum { + USB_FIFO_ERROR_OVERFLOW = 0, + USB_FIFO_ERROR_UNDERFLOW, +} USB_FIFO_ERROR_FLAG_Type; + +typedef enum { + USB_EP_STATUS_ACK = 0, + USB_EP_STATUS_NACK, + USB_EP_STATUS_STALL, + USB_EP_STATUS_NSTALL, +} USB_EP_STATUS_Type; + +typedef enum { + USB_LPM_DEFAULT_RESP_ACK = 0, + USB_LPM_DEFAULT_RESP_NACK, + USB_LPM_DEFAULT_RESP_STALL, + USB_LPM_DEFAULT_RESP_NYET, +} USB_LPM_DEFAULT_RESP_Type; + +typedef enum { + USB_ERROR_UTMI_RX = 0, + USB_ERROR_XFER_TO, + USB_ERROR_IVLD_EP, + USB_ERROR_PID_SEQ, + USB_ERROR_PID_CKS, + USB_ERROR_CRC5, + USB_ERROR_CRC16, +} USB_ERROR_Type; + +/** + * @brief USB configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type EnumOutEn; /*!< EP0 IN direction enable or disable */ + BL_Fun_Type EnumInEn; /*!< EP0 OUT direction enable or disable */ + uint8_t EnumMaxPacketSize; /*!< EP0 max packet size, only valid when SoftwareCtrl is set */ + uint8_t DeviceAddress; /*!< Device(EP0) address, only valid when SoftwareCtrl is set */ + BL_Fun_Type SoftwareCtrl; /*!< EP0 software control enable */ + BL_Fun_Type RomBaseDescriptorUsed; /*!< Enable signal of ROM-based descriptors (don't care if SoftwareCtrl is set) */ +} USB_Config_Type; + +/** + * @brief end point configuration structure type definition + */ +typedef struct +{ + uint16_t EPMaxPacketSize; /*!< Endpoint max packet size */ + EP_XFER_DIR dir; /*!< Endpoint direction */ + EP_XFER_Type type; /*!< Endpoint type */ +} EP_Config_Type; + +typedef struct +{ + uint32_t cr_ep_size : 9; + uint32_t cr_ep_dir : 2; + uint32_t cr_ep_type : 3; + uint32_t cr_ep_stall : 1; + uint32_t cr_ep_nack : 1; + uint32_t cr_ep_rdy : 1; + uint32_t reserved_17_31 : 15; +} usb_reg_epx_config_t; + +typedef struct +{ + uint32_t ep_dma_tx_en : 1; + uint32_t ep_dma_rx_en : 1; + uint32_t ep_tx_fifo_clr : 1; + uint32_t ep_rx_fifo_clr : 1; + uint32_t ep_tx_fifo_overflow : 1; + uint32_t ep_tx_fifo_underflow : 1; + uint32_t ep_rx_fifo_overflow : 1; + uint32_t ep_rx_fifo_underflow : 1; + uint32_t reserved_8_31 : 24; +} usb_reg_epx_fifo_config_t; + +typedef struct +{ + uint32_t ep_tx_fifo_cnt : 7; + uint32_t reserved_7_13 : 7; + uint32_t ep_tx_fifo_empty : 1; + uint32_t ep_tx_fifo_full : 1; + uint32_t ep_rx_fifo_cnt : 7; + uint32_t reserved_23_29 : 7; + uint32_t ep_rx_fifo_empty : 1; + uint32_t ep_rx_fifo_full : 1; +} usb_reg_epx_fifo_status_t; + +typedef struct +{ + uint32_t fifo : 8; + uint32_t reserved_8_31 : 24; +} usb_reg_epx_fifo_t; + +/*@} end of group USB_Public_Types */ + +/** @defgroup USB_Public_Constants + * @{ + */ + +/** @defgroup USB_EP_ID + * @{ + */ +#define IS_USB_EP_ID(type) (((type) == EP_ID0) || \ + ((type) == EP_ID1) || \ + ((type) == EP_ID2) || \ + ((type) == EP_ID3) || \ + ((type) == EP_ID4) || \ + ((type) == EP_ID5) || \ + ((type) == EP_ID6) || \ + ((type) == EP_ID7)) + +/** @defgroup EP_XFER_TYPE + * @{ + */ +#define IS_EP_XFER_TYPE(type) (((type) == EP_INT) || \ + ((type) == EP_ISO) || \ + ((type) == EP_CTRL) || \ + ((type) == EP_BULK)) + +/** @defgroup EP_XFER_DIR + * @{ + */ +#define IS_EP_XFER_DIR(type) (((type) == EP_DISABLED) || \ + ((type) == EP_IN) || \ + ((type) == EP_OUT)) + +/*@} end of group USB_Public_Constants */ + +/** @defgroup USB_Public_Macros + * @{ + */ +#define USB_INT_TYPE_SOF 0x00000001 +#define USB_INT_TYPE_RESET 0x00000002 +#define USB_INT_TYPE_GET_DCT_CMD 0x00000008 +#define USB_INT_TYPE_EP0_SETUP_CMD 0x00000010 +#define USB_INT_TYPE_EP0_SETUP_DONE 0x00000020 +#define USB_INT_TYPE_EP0_IN_CMD 0x00000040 +#define USB_INT_TYPE_EP0_IN_DONE 0x00000080 +#define USB_INT_TYPE_EP0_OUT_CMD 0x00000100 +#define USB_INT_TYPE_EP0_OUT_DONE 0x00000200 +#define USB_INT_TYPE_EP1_CMD 0x00000400 +#define USB_INT_TYPE_EP1_DONE 0x00000800 +#define USB_INT_TYPE_EP2_CMD 0x00001000 +#define USB_INT_TYPE_EP2_DONE 0x00002000 +#define USB_INT_TYPE_EP3_CMD 0x00004000 +#define USB_INT_TYPE_EP3_DONE 0x00008000 +#define USB_INT_TYPE_EP4_CMD 0x00010000 +#define USB_INT_TYPE_EP4_DONE 0x00020000 +#define USB_INT_TYPE_EP5_CMD 0x00040000 +#define USB_INT_TYPE_EP5_DONE 0x00080000 +#define USB_INT_TYPE_EP6_CMD 0x00100000 +#define USB_INT_TYPE_EP6_DONE 0x00200000 +#define USB_INT_TYPE_EP7_CMD 0x00400000 +#define USB_INT_TYPE_EP7_DONE 0x00800000 +#define USB_INT_TYPE_RESET_END 0x08000000 +#define USB_INT_TYPE_LPM_WAKEUP 0x10000000 +#define USB_INT_TYPE_LPM_PACKET 0x20000000 +#define USB_INT_TYPE_LOST_SOF_3_TIMES 0x40000000 +#define USB_INT_TYPE_ERROR 0x80000000 +#define USB_INT_TYPE_ALL (USB_INT_TYPE_SOF | \ + USB_INT_TYPE_RESET | \ + USB_INT_TYPE_GET_DCT_CMD | \ + USB_INT_TYPE_EP0_SETUP_CMD | \ + USB_INT_TYPE_EP0_SETUP_DONE | \ + USB_INT_TYPE_EP0_IN_CMD | \ + USB_INT_TYPE_EP0_IN_DONE | \ + USB_INT_TYPE_EP0_OUT_CMD | \ + USB_INT_TYPE_EP0_OUT_DONE | \ + USB_INT_TYPE_EP1_CMD | \ + USB_INT_TYPE_EP1_DONE | \ + USB_INT_TYPE_EP2_CMD | \ + USB_INT_TYPE_EP2_DONE | \ + USB_INT_TYPE_EP3_CMD | \ + USB_INT_TYPE_EP3_DONE | \ + USB_INT_TYPE_EP4_CMD | \ + USB_INT_TYPE_EP4_DONE | \ + USB_INT_TYPE_EP5_CMD | \ + USB_INT_TYPE_EP5_DONE | \ + USB_INT_TYPE_EP6_CMD | \ + USB_INT_TYPE_EP6_DONE | \ + USB_INT_TYPE_EP7_CMD | \ + USB_INT_TYPE_EP7_DONE | \ + USB_INT_TYPE_RESET_END | \ + USB_INT_TYPE_LPM_WAKEUP | \ + USB_INT_TYPE_LPM_PACKET | \ + USB_INT_TYPE_LOST_SOF_3_TIMES | \ + USB_INT_TYPE_ERROR) + +#define USB_EP_TX_FIFO_EMPTY 0x00004000 +#define USB_EP_TX_FIFO_FULL 0x00008000 +#define USB_EP_RX_FIFO_EMPTY 0x40000000 +#define USB_EP_RX_FIFO_FULL 0x80000000 +#define USB_EP_FIFO_STATUS_MASK (USB_EP_TX_FIFO_EMPTY | \ + USB_EP_TX_FIFO_FULL | \ + USB_EP_RX_FIFO_EMPTY | \ + USB_EP_RX_FIFO_FULL) +#define USB_EP_TX_FIFO_OVERFLOW 0x00000010 +#define USB_EP_TX_FIFO_UNDERFLOW 0x00000020 +#define USB_EP_RX_FIFO_OVERFLOW 0x00000040 +#define USB_EP_RX_FIFO_UNDERLOW 0x00000080 +#define USB_EP_FIFO_ERROR_MASK (USB_EP_TX_FIFO_OVERFLOW | \ + USB_EP_TX_FIFO_UNDERFLOW | \ + USB_EP_RX_FIFO_OVERFLOW | \ + USB_EP_RX_FIFO_UNDERLOW) + +#define EP_ID_MAX 8 + +/*@} end of group USB_Public_Macros */ + +/** @defgroup USB_Public_Functions + * @{ + */ + +/** + * @brief USB Functions + */ + +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void USB_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type USB_Enable(void); +BL_Err_Type USB_Disable(void); +BL_Err_Type USB_Set_Config(BL_Fun_Type enable, USB_Config_Type *usbCfg); +BL_Err_Type USB_Set_Device_Addr(uint8_t addr); +uint8_t USB_Get_Device_Addr(void); +/*----------*/ +BL_Err_Type USB_Set_EPx_Xfer_Size(USB_EP_ID epId, uint8_t size); +BL_Err_Type USB_Set_EPx_IN_Busy(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_IN_Stall(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_OUT_Busy(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_OUT_Stall(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_Rdy(USB_EP_ID epId); +BL_Sts_Type USB_Is_EPx_RDY_Free(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_STALL(USB_EP_ID epId); +BL_Err_Type USB_Clr_EPx_STALL(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_Busy(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_Status(USB_EP_ID epId, USB_EP_STATUS_Type sts); +USB_EP_STATUS_Type USB_Get_EPx_Status(USB_EP_ID epId); +/*----------*/ +BL_Err_Type USB_IntEn(USB_INT_Type intType, uint8_t enable); +BL_Err_Type USB_IntMask(USB_INT_Type intType, BL_Mask_Type intMask); +BL_Sts_Type USB_Get_IntStatus(USB_INT_Type intType); +BL_Err_Type USB_Clr_IntStatus(USB_INT_Type intType); +BL_Err_Type USB_Clr_EPx_IntStatus(USB_EP_ID epId); +/*----------*/ +uint16_t USB_Get_Frame_Num(void); +/*----------*/ +BL_Err_Type USB_Set_EPx_Config(USB_EP_ID epId, EP_Config_Type *epCfg); +BL_Err_Type USB_Set_EPx_Type(USB_EP_ID epId, EP_XFER_Type type); +EP_XFER_Type USB_Get_EPx_Type(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_Dir(USB_EP_ID epId, EP_XFER_DIR dir); +EP_XFER_DIR USB_Get_EPx_Dir(USB_EP_ID epId); +BL_Err_Type USB_Set_EPx_Size(USB_EP_ID epId, uint32_t size); +/*----------*/ +BL_Sts_Type USB_Get_EPx_TX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag); +BL_Sts_Type USB_Get_EPx_RX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag); +BL_Err_Type USB_Clr_EPx_TX_FIFO_Errors(USB_EP_ID epId); +BL_Err_Type USB_Clr_EPx_RX_FIFO_Errors(USB_EP_ID epId); +/*----------*/ +BL_Err_Type USB_EPx_Write_Data_To_FIFO(USB_EP_ID epId, uint8_t *pData, uint16_t len); +BL_Err_Type USB_EPx_Read_Data_From_FIFO(USB_EP_ID epId, uint8_t *pBuff, uint16_t len); +/*----------*/ +BL_Err_Type USB_Set_EPx_TX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState); +BL_Err_Type USB_Set_EPx_RX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState); +BL_Err_Type USB_EPx_Write_Data_To_FIFO_DMA(USB_EP_ID epId, uint8_t *pData, uint16_t len); +BL_Err_Type USB_EPx_Read_Data_From_FIFO_DMA(USB_EP_ID epId, uint8_t *pBuff, uint16_t len); +/*----------*/ +uint16_t USB_Get_EPx_TX_FIFO_CNT(USB_EP_ID epId); +uint16_t USB_Get_EPx_RX_FIFO_CNT(USB_EP_ID epId); +BL_Sts_Type USB_Get_EPx_TX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts); +BL_Sts_Type USB_Get_EPx_RX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts); +/*----------*/ +BL_Err_Type USB_Set_Internal_PullUp_Config(BL_Fun_Type newState); +/*----------*/ +BL_Sts_Type USB_Get_LPM_Status(void); +uint16_t USB_Get_LPM_Packet_Attr(void); +BL_Err_Type USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_Type defaultResp); +BL_Err_Type USB_LPM_Enable(void); +BL_Err_Type USB_LPM_Disable(void); +/*----------*/ +BL_Err_Type USB_Device_Output_K_State(uint16_t stateWidth); +/*----------*/ +uint8_t USB_Get_Current_Packet_PID(void); +uint8_t USB_Get_Current_Packet_EP(void); +/*----------*/ +BL_Sts_Type USB_Get_Error_Status(USB_ERROR_Type err); +BL_Err_Type USB_Clr_Error_Status(USB_ERROR_Type err); +/*----------*/ + +/*@} end of group USB_Public_Functions */ + +/*@} end of group USB */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_USB_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h new file mode 100644 index 0000000000000000000000000000000000000000..621e4969784f908fca88d336770f51a12d6470eb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h @@ -0,0 +1,99 @@ +/** + ****************************************************************************** + * @file bl702_xip_sflash.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_XIP_SFLASH_H__ +#define __BL702_XIP_SFLASH_H__ + +#include "bl702_common.h" +#include "bl702_sflash.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_Public_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Types */ + +/** @defgroup XIP_SFLASH_Public_Constants + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Constants */ + +/** @defgroup XIP_SFLASH_Public_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Macros */ + +/** @defgroup XIP_SFLASH_Public_Functions + * @{ + */ +void XIP_SFlash_Opt_Enter(void); +void XIP_SFlash_Opt_Exit(void); +BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset); +BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset); +BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, + uint32_t startaddr, uint32_t endaddr); +BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, + uint8_t *data, uint32_t len); +BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, + uint8_t *data, uint32_t len); +BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, + uint8_t *data); +BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, + uint8_t *data); +BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, + uint8_t *data, uint8_t idLen); +BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len); +int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *dst, int len); +int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *src, + int len); +int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len); + +/*@} end of group XIP_SFLASH_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_XIP_SFLASH_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..931eb8c6efe9f66ad0f45fd03e5aaaa49f53110c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h @@ -0,0 +1,86 @@ +/** + ****************************************************************************** + * @file bl702_xip_sflash_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702_XIP_SFLASH_EXT_H__ +#define __BL702_XIP_SFLASH_EXT_H__ + +#include "bl702_common.h" +#include "bl702_sflash.h" +#include "bl702_xip_sflash.h" +#include "bl702_sf_cfg.h" +#include "bl702_sf_cfg_ext.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_EXT_Public_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Types */ + +/** @defgroup XIP_SFLASH_EXT_Public_Constants + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Constants */ + +/** @defgroup XIP_SFLASH_EXT_Public_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Macros */ + +/** @defgroup XIP_SFLASH_EXT_Public_Functions + * @{ + */ + +BL_Err_Type XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg); +int XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len); +int XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len); +int XIP_SFlash_Erase(uint32_t addr, int len); + +/*@} end of group XIP_SFLASH_EXT_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL702_Peripheral_Driver */ + +#endif /* __BL702_XIP_SFLASH_EXT_H__ */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_acomp.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_acomp.c new file mode 100644 index 0000000000000000000000000000000000000000..25ab9ad756a77f283c4a67ceedd91f6690b8d108 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_acomp.c @@ -0,0 +1,202 @@ +/** + ****************************************************************************** + * @file bl702_acomp.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_acomp.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup ACOMP + * @{ + */ + +/** @defgroup ACOMP_Private_Macros + * @{ + */ + +/*@} end of group ACOMP_Private_Macros */ + +/** @defgroup ACOMP_Private_Types + * @{ + */ + +/*@} end of group ACOMP_Private_Types */ + +/** @defgroup ACOMP_Private_Variables + * @{ + */ + +/*@} end of group ACOMP_Private_Variables */ + +/** @defgroup ACOMP_Global_Variables + * @{ + */ + +/*@} end of group ACOMP_Global_Variables */ + +/** @defgroup ACOMP_Private_Fun_Declaration + * @{ + */ + +/*@} end of group ACOMP_Private_Fun_Declaration */ + +/** @defgroup ACOMP_Private_Functions + * @{ + */ + +/*@} end of group ACOMP_Private_Functions */ + +/** @defgroup ACOMP_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Analog compare init + * + * @param acompNo: Compare ID + * @param cfg: Compare consideration pointer + * + * @return None + * +*******************************************************************************/ +void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + if (acompNo == AON_ACOMP0_ID) { + /* Disable ACOMP first */ + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); + + /* Set ACOMP config */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, cfg->muxEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, cfg->posChanSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, cfg->negChanSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, cfg->levelFactor); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, cfg->biasProg); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, cfg->hysteresisPosVolt); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, cfg->hysteresisNegVolt); + + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); + + } else { + /* Disable ACOMP first */ + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); + + /* Set ACOMP config */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, cfg->muxEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, cfg->posChanSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, cfg->negChanSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, cfg->levelFactor); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, cfg->biasProg); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, cfg->hysteresisPosVolt); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, cfg->hysteresisNegVolt); + + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); + } +} + +/****************************************************************************/ /** + * @brief Analog compare enable + * + * @param acompNo: Compare ID + * + * @return None + * +*******************************************************************************/ +void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + if (acompNo == AON_ACOMP0_ID) { + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); + } else { + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN); + tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); + } +} + +/****************************************************************************/ /** + * @brief Analog compare enable + * + * @param acompNo: Compare ID + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL); + + /* Disable ACOMP first */ + if (acompNo == AON_ACOMP0_ID) { + if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) { + return SET; + } else { + return RESET; + } + } else { + if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) { + return SET; + } else { + return RESET; + } + } +} + +/*@} end of group ACOMP_Public_Functions */ + +/*@} end of group ACOMP */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..4e003973ff935ecf9c11027dfebf03d9796e2c4f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c @@ -0,0 +1,1570 @@ +/** + ****************************************************************************** + * @file bl702_adc.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_adc.h" +#include "bl702_ef_ctrl.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ +#undef MSG +#define MSG(...) +#define AON_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } +#define ADC_RESTART_DUMMY_WAIT BL702_Delay_US(100) + +/*@} end of group ADC_Private_Macros */ + +/** @defgroup ADC_Private_Types + * @{ + */ + +/*@} end of group ADC_Private_Types */ + +/** @defgroup ADC_Private_Variables + * @{ + */ +static intCallback_Type *adcIntCbfArra[ADC_INT_ALL] = { NULL }; +static ADC_Gain_Coeff_Type adcGainCoeffCal = { + .adcGainCoeffEnable = DISABLE, + .adcgainCoeffVal = 0, + .coe = 1, +}; + +/*@} end of group ADC_Private_Variables */ + +/** @defgroup ADC_Global_Variables + * @{ + */ + +/*@} end of group ADC_Global_Variables */ + +/** @defgroup ADC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group ADC_Private_Fun_Declaration */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/*@} end of group ADC_Private_Functions */ + +/** @defgroup ADC_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Software reset the whole ADC + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Reset(void) +{ + uint32_t regCmd; + + /* reset ADC */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); + AON_CLK_SET_DUMMY_WAIT; + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); +} + +/****************************************************************************/ /** + * @brief ADC glable enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC glable disable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC normal mode init + * + * @param cfg: ADC normal mode configuration + * + * @return None + * +*******************************************************************************/ +void ADC_Init(ADC_CFG_Type *cfg) +{ + uint32_t regCfg1; + uint32_t regCfg2; + uint32_t regCalib; + + CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel)); + CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel)); + CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv)); + CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1)); + CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2)); + CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode)); + CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel)); + CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm)); + CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref)); + CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode)); + CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth)); + + /* config 1 */ + regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); + AON_CLK_SET_DUMMY_WAIT; + + /* config 2 */ + regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode); + /* pga_vcmi_en is for mic */ + regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN); + + if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) { + regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN); + } else { + regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN); + } + + /* pga_os_cal is for mic */ + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2); + + /* calibration offset */ + regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE); + regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal); + BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler); +#endif + + ADC_Gain_Trim(); +} + +/****************************************************************************/ /** + * @brief ADC normal mode channel config + * + * @param posCh: ADC pos channel type + * @param negCh: ADC neg channel type + * @param contEn: ENABLE or DISABLE continuous mode + * + * @return None + * +*******************************************************************************/ +void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn) +{ + uint32_t regCmd; + uint32_t regCfg1; + + CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh)); + CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh)); + + /* set channel */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh); + regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); + + /* set continuous mode */ + regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); +} + +/****************************************************************************/ /** + * @brief ADC scan mode channel config + * + * @param posChList[]: ADC pos channel list type + * @param negChList[]: ADC neg channel list type + * @param scanLength: ADC scan length + * @param contEn: ENABLE or DISABLE continuous mode + * + * @return None + * +*******************************************************************************/ +void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn) +{ + uint32_t tmpVal, i; + uint32_t dealLen; + + CHECK_PARAM((scanLength < 13)); + + /* Deal with the first 6 */ + dealLen = 6; + + if (scanLength < dealLen) { + dealLen = scanLength; + } + + /* Set first 6 scan channels */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1); + + for (i = 0; i < dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (posChList[i] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal); + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1); + + for (i = 0; i < dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (negChList[i] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal); + + /* Set the left channels */ + if (scanLength > dealLen) { + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2); + + for (i = 0; i < scanLength - dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (posChList[i + dealLen] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal); + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2); + + for (i = 0; i < scanLength - dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (negChList[i + dealLen] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal); + } + + /* Scan mode */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC normal mode convert start + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Start(void) +{ + uint32_t regCmd; + + /* disable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); + + ADC_RESTART_DUMMY_WAIT; + + /* enable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); +} + +/****************************************************************************/ /** + * @brief ADC normal mode convert stop + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Stop(void) +{ + uint32_t regCmd; + + /* disable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); +} + +/****************************************************************************/ /** + * @brief ADC FIFO configuration + * + * @param fifoCfg: ADC FIFO confifuration pointer + * + * @return None + * +*******************************************************************************/ +void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold)); + + /* + * DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur + * DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt + */ + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold); + + /* Enable DMA */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn); + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO data count + * + * @param None + * + * @return data count in FIFO + * +*******************************************************************************/ +uint8_t ADC_Get_FIFO_Count(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT); +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO full status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_FIFO_Is_Full(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO empty status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_FIFO_Is_Empty(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) { + return RESET; + } else { + return SET; + } +} + +/****************************************************************************/ /** + * @brief ADC read DMA FIFO data + * + * @param None + * + * @return ADC result if return 0 that means this is error data,user should ignore this data. + * +*******************************************************************************/ +uint32_t ADC_Read_FIFO(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA); + + return (tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC parse result + * + * @param orgVal: Original A to D value + * @param len: Original AD vaule count + * @param result: Final Result array pointer + * + * @return None + * +*******************************************************************************/ +void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result) +{ + uint8_t neg = 0; + uint32_t tmpVal1 = 0, tmpVal2 = 0; + ADC_Data_Width_Type dataType; + ADC_SIG_INPUT_Type sigType; + float ref = 2.0; + uint32_t i = 0; + + float coe = 1.0; + + if (adcGainCoeffCal.adcGainCoeffEnable) { + coe = adcGainCoeffCal.coe; + } + + tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL); + sigType = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE); + + if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) { + ref = 3.2; + } + + if (sigType == ADC_INPUT_SINGLE_END) { + for (i = 0; i < len; i++) { + result[i].posChan = orgVal[i] >> 21; + result[i].negChan = -1; + + if (dataType == ADC_DATA_WIDTH_12) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); + result[i].volt = result[i].value / 4096.0 * ref; + } else if (dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); + result[i].volt = result[i].value / 16384.0 * ref; + } else if (dataType == ADC_DATA_WIDTH_16_WITH_64_AVERAGE || dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE) { + result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); + result[i].volt = result[i].value / 65536.0 * ref; + } + } + } else { + for (i = 0; i < len; i++) { + neg = 0; + result[i].posChan = orgVal[i] >> 21; + result[i].negChan = (orgVal[i] >> 16) & 0x1F; + + if (orgVal[i] & 0x8000) { + orgVal[i] = ~orgVal[i]; + orgVal[i] += 1; + neg = 1; + } + + if (dataType == ADC_DATA_WIDTH_12) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); + result[i].volt = result[i].value / 2048.0 * ref; + } else if (dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); + result[i].volt = result[i].value / 8192.0 * ref; + } else if (dataType == ADC_DATA_WIDTH_16_WITH_64_AVERAGE || dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE) { + result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); + result[i].volt = result[i].value / 32768.0 * ref; + } + + if (neg) { + result[i].volt = -result[i].volt; + } + } + } +} + +/****************************************************************************/ /** + * @brief ADC mask or unmask certain or all interrupt + * + * @param intType: interrupt type + * @param intMask: mask or unmask + * + * @return None + * +*******************************************************************************/ +BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK); + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK); + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); + return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); + return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); + return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK); + break; + + case ADC_INT_FIFO_READY: + tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); + return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); + break; + default: + break; + } + return 0; +} + +/****************************************************************************/ /** + * @brief ADC mask or unmask certain or all interrupt + * + * @param intType: interrupt type + * @param intMask: mask or unmask + * + * @return None + * +*******************************************************************************/ +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + } + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + } + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + } + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + + case ADC_INT_FIFO_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); + } + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + + case ADC_INT_ALL: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + } else { + /* Disable this interrupt */ + tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief ADC clear certain or all interrupt + * + * @param intType: interrupt type + * + * @return None + * +*******************************************************************************/ +void ADC_IntClr(ADC_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_FIFO_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_ALL: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief ADC get interrupt status + * + * @param intType: interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) +{ + uint32_t tmpVal; + BL_Sts_Type bitStatus = RESET; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET; + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET; + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET; + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET; + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET; + break; + + case ADC_INT_FIFO_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY)) ? SET : RESET; + break; + + case ADC_INT_ALL: + break; + + default: + break; + } + + return bitStatus; +} + +/****************************************************************************/ /** + * @brief ADC install interrupt callback + * + * @param intType: ADC interrupt type + * @param cbFun: ADC interrupt callback + * + * @return None + * +*******************************************************************************/ +void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + adcIntCbfArra[intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief ADC DMA interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void GPADC_DMA_IRQHandler(void) +{ + if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) { + ADC_IntClr(ADC_INT_POS_SATURATION); + + if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) { + adcIntCbfArra[ADC_INT_POS_SATURATION](); + } + } + + if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) { + ADC_IntClr(ADC_INT_NEG_SATURATION); + + if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) { + adcIntCbfArra[ADC_INT_NEG_SATURATION](); + } + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) { + ADC_IntClr(ADC_INT_FIFO_UNDERRUN); + + if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_UNDERRUN](); + } + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) { + ADC_IntClr(ADC_INT_FIFO_OVERRUN); + + if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_OVERRUN](); + } + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) { + ADC_IntClr(ADC_INT_FIFO_READY); + + if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_READY](); + } + } + + if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) { + ADC_IntClr(ADC_INT_FIFO_READY); + + if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_READY](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief ADC VBAT enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Vbat_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC VBAT disable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Vbat_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC TSEN Config + * + * @param tsenMod: None + * + * @return None + * +*******************************************************************************/ +void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type)); + + /* config gpadc_reg_cmd */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + /* enable sensor dc test mux*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN); + /*selected sen output current channel*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0); + /* enable chip sensor*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU); + /*dwa_en */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + + /* config 2 */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + /*tsvbe low=0*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + /*dly_sel=2*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2); + /*test_sel=0*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0); + /*test_en=0*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN); + /*ts_en*/ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); + /*select tsen ext or inner*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2); + /*pga vcmi enable*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); + /*0:512uS;1:16mS;2:32mS;3:64mS*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); + + /* config 3 */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + /* set gpadc_dither_en */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); + + /* set 4000F90C[19](gpadc_mic2_diff) = 1 + * debug advise form Ran + * 2020.08.26 + */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC TSEN Enable + * + * @return None + * +*******************************************************************************/ +void ADC_Tsen_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC TSEN Disable + * + * @return None + * +*******************************************************************************/ +void ADC_Tsen_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC Clear fifo + * + * @return None + * +*******************************************************************************/ +void ADC_FIFO_Clear(void) +{ + uint32_t tmpVal; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief config pga + * + * @param pga_vcmi_enable: enable or not vcmi + * @param pga_os_cal: pga os cal value + * @return None + * +*******************************************************************************/ +void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + + if (pga_vcmi_enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, pga_os_cal); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} +/****************************************************************************/ /** + * @brief TSEN_Get_V_Error + * + * @param None + * + * @return None + * +*******************************************************************************/ +uint32_t TSEN_Get_V_Error(void) +{ + uint32_t v0 = 0, v1 = 0; + uint32_t v_error = 0; + uint32_t regVal = 0; + ADC_Result_Type result; + uint32_t tmpVal; + uint8_t gainCalEnabled = 0; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_LOW(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v0 = result.value; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_HIGH(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v1 = result.value; + + v_error = v0 - v1; + + return v_error; +} + +/****************************************************************************/ /** + * @brief Trim TSEN + * + * @param tsen_offset: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset) +{ + uint8_t average_index = 0; + uint32_t v_error_sum = 0; + uint32_t tmpVal = 0; + float A1 = 0.0, A2 = 0.0, C = 0.0, delta = 0.0; + Efuse_TSEN_Refcode_Corner_Type trim; + + EF_Ctrl_Read_TSEN_Trim(&trim); + + if (trim.tsenRefcodeCornerEn) { + if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) { + MSG("TSEN ATE Version = %d\r\n", trim.tsenRefcodeCornerVersion); + + *tsen_offset = trim.tsenRefcodeCorner; + + if (trim.tsenRefcodeCornerVersion == 0) { + /* debug advise by ran + * 2020.9.04 + */ + + //set 4000F90C[19](gpadc_mic2_diff) = 0 + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 0); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + + for (average_index = 0; average_index < 50; average_index++) { + v_error_sum += TSEN_Get_V_Error(); + } + + v_error_sum /= 50; + + MSG("A1 = %d\r\n", v_error_sum); + A1 = v_error_sum; + + v_error_sum = 0; + + //set 4000F90C[19](gpadc_mic2_diff) = 1 + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + + for (average_index = 0; average_index < 50; average_index++) { + v_error_sum += TSEN_Get_V_Error(); + } + + v_error_sum /= 50; + + MSG("A2 = %d\r\n", v_error_sum); + A2 = v_error_sum; + + MSG("C = %d\r\n", *tsen_offset); + C = *tsen_offset; + + delta = A2 - (7.753 / 5.62 * A1) + 2.133 / 5.62 * C + 72; + + MSG("delta=A2-7.753/5.62*A1+2.133/5.62*C+72x; delta = %d\r\n", (uint16_t)delta); + + *tsen_offset = delta + C; + } + + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_SET_TSVBE_LOW(void) +{ + uint32_t tmpVal; + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_SET_TSVBE_HIGH(void) +{ + uint32_t tmpVal; + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param tsen_offset: tsen_offset form efuse trim data + * + * @return tempture + * +*******************************************************************************/ +float TSEN_Get_Temp(uint32_t tsen_offset) +{ + uint32_t v0 = 0, v1 = 0; + float temp = 0; + uint32_t regVal = 0; + ADC_Result_Type result; + uint32_t tmpVal; + uint8_t gainCalEnabled = 0; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_LOW(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v0 = result.value; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_HIGH(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v1 = result.value; + + if (v0 > v1) { + temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753; + } else { + temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753; + } + + return temp; +} + +/****************************************************************************/ /** + * @brief ADC MIC Config + * + * @param adc_mic_config: adc_mic_config + * + * @return success or not + * +*******************************************************************************/ +BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config) +{ + uint32_t tmpVal1 = 0, tmpVal2 = 0; + + CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb)); + CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain)); + CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode)); + CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn)); + + tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + + tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn); + + if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) { + /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/ + return ERROR; + } else { + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn); + } + + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief ADC MIC bias control + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_MIC_Bias_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC MIC bias control + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_MIC_Bias_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief Trim ADC Gain + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) +{ + Efuse_ADC_Gain_Coeff_Type trim; + uint32_t tmp; + + EF_Ctrl_Read_ADC_Gain_Trim(&trim); + + if (trim.adcGainCoeffEn) { + if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) { + adcGainCoeffCal.adcGainCoeffEnable = ENABLE; + adcGainCoeffCal.adcgainCoeffVal = trim.adcGainCoeff; + tmp = adcGainCoeffCal.adcgainCoeffVal; + + if (tmp & 0x800) { + tmp = ~tmp; + tmp += 1; + tmp = tmp & 0xfff; + //printf("val==%08x\r\n",(unsigned int)tmp); + adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0)); + //printf("coe==%0f\r\n",adcGainCoeffCal.coe); + } else { + adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0)); + //printf("coe==%0f\r\n",adcGainCoeffCal.coe); + } + + return SUCCESS; + } + } + + return ERROR; +} + +/*@} end of group ADC_Public_Functions */ + +/*@} end of group ADC */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_aon.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_aon.c new file mode 100644 index 0000000000000000000000000000000000000000..85a402cd1cffa5b75cbbd2294e5a4af12ce4b845 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_aon.c @@ -0,0 +1,518 @@ +/** + ****************************************************************************** + * @file bl702_aon.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_aon.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Private_Macros + * @{ + */ +#define AON_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group AON_Private_Macros */ + +/** @defgroup AON_Private_Types + * @{ + */ + +/*@} end of group AON_Private_Types */ + +/** @defgroup AON_Private_Variables + * @{ + */ + +/*@} end of group AON_Private_Variables */ + +/** @defgroup AON_Global_Variables + * @{ + */ + +/*@} end of group AON_Global_Variables */ + +/** @defgroup AON_Private_Fun_Declaration + * @{ + */ + +/*@} end of group AON_Private_Fun_Declaration */ + +/** @defgroup AON_Private_Functions + * @{ + */ + +/*@} end of group AON_Private_Functions */ + +/** @defgroup AON_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Power on MXX band gap + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void) +{ + uint32_t tmpVal = 0; + + /* Power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off MXX band gap + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void) +{ + uint32_t tmpVal = 0; + + /* Power OFF */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on XTAL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + /* Polling for ready */ + do { + BL702_Delay_US(10); + timeOut++; + tmpVal = BL_RD_REG(AON_BASE, AON_TSEN); + } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120); + + if (timeOut >= 120) { + return TIMEOUT; + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set XTAL cap code + * + * @param capIn: Cap code in + * @param capOut: Cap code out + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut); + BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal); + + BL702_Delay_US(100); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get XTAL cap code + * + * @param None + * + * @return Cap code + * +*******************************************************************************/ +uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); + + return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON); +} + +/****************************************************************************/ /** + * @brief Power off XTAL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on bandgap system + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void) +{ + uint32_t tmpVal = 0; + + /* power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); + BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal); + + BL702_Delay_US(55); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off bandgap system + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void) +{ + uint32_t tmpVal = 0; + + /* power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); + BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal); + + BL702_Delay_US(55); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on LDO11 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON); + BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal); + + BL702_Delay_US(55); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off LDO11 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON); + BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal); + + BL702_Delay_US(55); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on LDO15_RF + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void) +{ + uint32_t tmpVal = 0; + + /* ldo15rf power on */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702_Delay_US(90); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off LDO15_RF + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void) +{ + uint32_t tmpVal = 0; + + /* ldo15rf power off */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power on source follow regular + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void) +{ + uint32_t tmpVal = 0; + + /* power on sfreg */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702_Delay_US(10); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power off source follow regular + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void) +{ + uint32_t tmpVal = 0; + + /* power off sfreg */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off the power can be shut down in PDS0 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void) +{ + uint32_t tmpVal = 0; + + /* power off bz */ + tmpVal = BL_RD_REG(AON_BASE, AON_MISC); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_BZ_EN_AON); + BL_WR_REG(AON_BASE, AON_MISC, tmpVal); + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + /* gating Clock, no more use */ + //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0); + //tmpVal=tmpVal&(~(1<<6)); + //tmpVal=tmpVal&(~(1<<7)); + //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on the power powered down in PDS0 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702_Delay_US(20); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702_Delay_US(60); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702_Delay_US(20); + + /* power on bz */ + tmpVal = BL_RD_REG(AON_BASE, AON_MISC); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_BZ_EN_AON); + BL_WR_REG(AON_BASE, AON_MISC, tmpVal); + + /* ungating Clock, no more use */ + //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0); + //tmpVal=tmpVal|((1<<6)); + //tmpVal=tmpVal|((1<<7)); + //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on the power powered down in PDS0 + * + * @param delay: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((delay <= 0x3)); + + /* config ldo11soc_sstart_delay_aon */ + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay); + BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal); + + return SUCCESS; +} + +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_cam.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_cam.c new file mode 100644 index 0000000000000000000000000000000000000000..0157e388bc80eaf63036146bf29e02a947a881c0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_cam.c @@ -0,0 +1,762 @@ +/** + ****************************************************************************** + * @file bl702_cam.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702.h" +#include "bl702_cam.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup CAM + * @{ + */ + +/** @defgroup CAM_Private_Macros + * @{ + */ + +/*@} end of group CAM_Private_Macros */ + +/** @defgroup CAM_Private_Types + * @{ + */ + +/*@} end of group CAM_Private_Types */ + +/** @defgroup CAM_Private_Variables + * @{ + */ +static intCallback_Type *camIntCbfArra[CAM_INT_ALL] = { NULL }; + +/*@} end of group CAM_Private_Variables */ + +/** @defgroup CAM_Global_Variables + * @{ + */ + +/*@} end of group CAM_Global_Variables */ + +/** @defgroup CAM_Private_Fun_Declaration + * @{ + */ + +/*@} end of group CAM_Private_Fun_Declaration */ + +/** @defgroup CAM_Private_Functions + * @{ + */ + +/*@} end of group CAM_Private_Functions */ + +/** @defgroup CAM_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Camera module init + * + * @param cfg: Camera configuration structure pointer + * + * @return None + * +*******************************************************************************/ +void CAM_Init(CAM_CFG_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_CAM_SW_MODE_TYPE(cfg->swMode)); + CHECK_PARAM(IS_CAM_FRAME_MODE_TYPE(cfg->frameMode)); + CHECK_PARAM(IS_CAM_YUV_MODE_TYPE(cfg->yuvMode)); + CHECK_PARAM(IS_CAM_FRAME_ACTIVE_POL(cfg->framePol)); + CHECK_PARAM(IS_CAM_LINE_ACTIVE_POL(cfg->linePol)); + CHECK_PARAM(IS_CAM_BURST_TYPE(cfg->burstType)); + CHECK_PARAM(IS_CAM_SENSOR_MODE_TYPE(cfg->camSensorMode)); + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM); + + /* Set camera configuration */ + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE); + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); + BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_SW_MODE, cfg->swMode); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_INTERLV_MODE, cfg->frameMode); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAM_VLD_POL, cfg->framePol); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_LINE_VLD_POL, cfg->linePol); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HBURST, cfg->burstType); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_MODE, cfg->camSensorMode); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_WAIT_CYCLE, cfg->waitCount); + + switch (cfg->yuvMode) { + case CAM_YUV422: + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN); + break; + + case CAM_YUV420_EVEN: + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EVEN); + break; + + case CAM_YUV420_ODD: + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EVEN); + break; + + case CAM_YUV400_EVEN: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EVEN); + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN); + break; + + case CAM_YUV400_ODD: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EVEN); + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN); + break; + + default: + break; + } + + BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal); + + /* Set frame count to issue interrupt at sw mode */ + tmpVal = BL_RD_REG(CAM_BASE, CAM_INT_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_CNT_TRGR_INT, cfg->swIntCnt); + BL_WR_REG(CAM_BASE, CAM_INT_CONTROL, tmpVal); + + /* Set camera memory start address, memory size and frame size in burst */ + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_ADDR_START_0, cfg->memStart0 & 0xFFFFFFF0); + + if (cfg->burstType == CAM_BURST_TYPE_SINGLE) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 4); + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 4); + } else if (cfg->burstType == CAM_BURST_TYPE_INCR4) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 16); + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 16); + } else if (cfg->burstType == CAM_BURST_TYPE_INCR8) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 32); + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 32); + } else if (cfg->burstType == CAM_BURST_TYPE_INCR16) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 64); + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 64); + } + + if (!cfg->frameMode) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_ADDR_START_1, cfg->memStart1 & 0xFFFFFFF0); + + if (cfg->burstType == CAM_BURST_TYPE_SINGLE) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 4); + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 4); + } else if (cfg->burstType == CAM_BURST_TYPE_INCR4) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 16); + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 16); + } else if (cfg->burstType == CAM_BURST_TYPE_INCR8) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 32); + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 32); + } else if (cfg->burstType == CAM_BURST_TYPE_INCR16) { + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 64); + BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 64); + } + } + + /* Clear interrupt */ + BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 0xFFFF0); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(CAM_IRQn, CAM_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief Deinit camera module + * + * @param None + * + * @return None + * +*******************************************************************************/ +void CAM_Deinit(void) +{ + //GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_CAM); +} + +/****************************************************************************/ /** + * @brief Enable camera module + * + * @param None + * + * @return None + * +*******************************************************************************/ +void CAM_Enable(void) +{ + uint32_t tmpVal; + + /* Enable camera module */ + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE); + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); + BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable camera module + * + * @param None + * + * @return None + * +*******************************************************************************/ +void CAM_Disable(void) +{ + uint32_t tmpVal; + + /* Disable camera module */ + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE); + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); + BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal); +} + +/****************************************************************************/ /** + * @brief Camera clock gate function + * + * @param enable: Enable or disable + * + * @return None + * +*******************************************************************************/ +void CAM_Clock_Gate(BL_Fun_Type enable) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_PIX_CLK_CG, enable); + BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal); +} + +/****************************************************************************/ /** + * @brief Camera hsync crop function + * + * @param start: Valid hsync start count + * @param end: Valid hsync end count + * + * @return None + * +*******************************************************************************/ +void CAM_Hsync_Crop(uint16_t start, uint16_t end) +{ + BL_WR_REG(CAM_BASE, CAM_HSYNC_CONTROL, (start << 16) + end); +} + +/****************************************************************************/ /** + * @brief Camera vsync crop function + * + * @param start: Valid vsync start count + * @param end: Valid vsync end count + * + * @return None + * +*******************************************************************************/ +void CAM_Vsync_Crop(uint16_t start, uint16_t end) +{ + BL_WR_REG(CAM_BASE, CAM_VSYNC_CONTROL, (start << 16) + end); +} + +/****************************************************************************/ /** + * @brief Camera set total valid pix count in a line function + * + * @param count: Count value + * + * @return None + * +*******************************************************************************/ +void CAM_Set_Hsync_Total_Count(uint16_t count) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_HCNT, count); + BL_WR_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL, tmpVal); +} + +/****************************************************************************/ /** + * @brief Camera set total valid line count in a frame function + * + * @param count: Count value + * + * @return None + * +*******************************************************************************/ +void CAM_Set_Vsync_Total_Count(uint16_t count) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_VCNT, count); + BL_WR_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL, tmpVal); +} + +/****************************************************************************/ /** + * @brief Get one camera frame in interleave mode + * + * @param info: Interleave mode camera frame infomation pointer + * + * @return None + * +*******************************************************************************/ +void CAM_Interleave_Get_Frame_Info(CAM_Interleave_Frame_Info *info) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR); + + info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_0); + info->curFrameAddr = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR0_0); + info->curFrameBytes = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT0_0); + info->status = tmpVal; +} + +/****************************************************************************/ /** + * @brief Get one camera frame in planar mode + * + * @param info: Planar mode camera frame infomation pointer + * + * @return None + * +*******************************************************************************/ +void CAM_Planar_Get_Frame_Info(CAM_Planar_Frame_Info *info) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR); + + info->validFrames0 = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_0); + info->validFrames1 = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_1); + info->curFrameAddr0 = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR0_0); + info->curFrameAddr1 = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR1_0); + info->curFrameBytes0 = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT0_0); + info->curFrameBytes1 = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT1_0); + info->status = tmpVal; +} + +/****************************************************************************/ /** + * @brief Get available count 0 of frames + * + * @param None + * + * @return Frames count + * +*******************************************************************************/ +uint8_t CAM_Get_Frame_Count_0(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT_0); +} + +/****************************************************************************/ /** + * @brief Get available count 1 of frames + * + * @param None + * + * @return Frames count + * +*******************************************************************************/ +uint8_t CAM_Get_Frame_Count_1(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT_1); +} + +/****************************************************************************/ /** + * @brief Pop one camera frame in interleave mode + * + * @param None + * + * @return None + * +*******************************************************************************/ +void CAM_Interleave_Pop_Frame(void) +{ + /* Pop one frame */ + BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 1); +} + +/****************************************************************************/ /** + * @brief Pop one camera frame in planar mode + * + * @param None + * + * @return None + * +*******************************************************************************/ +void CAM_Planar_Pop_Frame(void) +{ + /* Pop one frame */ + BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 3); +} + +/****************************************************************************/ /** + * @brief CAMERA Enable Disable Interrupt + * + * @param intType: CAMERA Interrupt Type + * @param intMask: Enable or Disable + * + * @return None + * +*******************************************************************************/ +void CAM_IntMask(CAM_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_CAM_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(CAM_BASE, CAM_INT_CONTROL); + + switch (intType) { + case CAM_INT_NORMAL_0: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_0_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_0_EN); + } + + break; + + case CAM_INT_NORMAL_1: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_1_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_1_EN); + } + + break; + + case CAM_INT_MEMORY_OVERWRITE_0: + case CAM_INT_MEMORY_OVERWRITE_1: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN); + } + + break; + + case CAM_INT_FRAME_OVERWRITE_0: + case CAM_INT_FRAME_OVERWRITE_1: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN); + } + + break; + + case CAM_INT_FIFO_OVERWRITE_0: + case CAM_INT_FIFO_OVERWRITE_1: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN); + } + + break; + + case CAM_INT_VSYNC_CNT_ERROR: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN); + } + + break; + + case CAM_INT_HSYNC_CNT_ERROR: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN); + } + + break; + + case CAM_INT_ALL: + if (intMask == UNMASK) { + /* Enable all interrupt */ + tmpVal |= 0x7F; + } else { + /* Disable all interrupt */ + tmpVal &= 0xFFFFFF80; + } + + break; + + default: + break; + } + + BL_WR_REG(CAM_BASE, CAM_INT_CONTROL, tmpVal); +} + +/****************************************************************************/ /** + * @brief CAMERA Interrupt Clear + * + * @param intType: CAMERA Interrupt Type + * + * @return None + * +*******************************************************************************/ +void CAM_IntClr(CAM_INT_Type intType) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP); + + switch (intType) { + case CAM_INT_NORMAL_0: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR_0); + break; + + case CAM_INT_NORMAL_1: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR_1); + break; + + case CAM_INT_MEMORY_OVERWRITE_0: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR_0); + break; + + case CAM_INT_MEMORY_OVERWRITE_1: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR_1); + break; + + case CAM_INT_FRAME_OVERWRITE_0: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR_0); + break; + + case CAM_INT_FRAME_OVERWRITE_1: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR_1); + break; + + case CAM_INT_FIFO_OVERWRITE_0: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR_0); + break; + + case CAM_INT_FIFO_OVERWRITE_1: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR_1); + break; + + case CAM_INT_VSYNC_CNT_ERROR: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_CLR_0); + break; + + case CAM_INT_HSYNC_CNT_ERROR: + tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_CLR_0); + break; + + case CAM_INT_ALL: + tmpVal = 0xFFFF0; + + default: + break; + } + + BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, tmpVal); +} + +/****************************************************************************/ /** + * @brief Install camera interrupt callback function + * + * @param intType: CAMERA interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void CAM_Int_Callback_Install(CAM_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_CAM_INT_TYPE(intType)); + + camIntCbfArra[intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief CAM hardware mode with frame start address wrap to memory address start function enable or disable + * + * @param enable: Enable or disable + * @return None + * +*******************************************************************************/ +void CAM_HW_Mode_Wrap(BL_Fun_Type enable) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, enable); + BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal); +} + +/****************************************************************************/ /** + * @brief Camera interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void CAM_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR); + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_0)) { + CAM_IntClr(CAM_INT_NORMAL_0); + + if (camIntCbfArra[CAM_INT_NORMAL_0] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_NORMAL_0](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_1)) { + CAM_IntClr(CAM_INT_NORMAL_1); + + if (camIntCbfArra[CAM_INT_NORMAL_1] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_NORMAL_1](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_0)) { + CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_0); + + if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_1)) { + CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_1); + + if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_0)) { + CAM_IntClr(CAM_INT_FRAME_OVERWRITE_0); + + if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_1)) { + CAM_IntClr(CAM_INT_FRAME_OVERWRITE_1); + + if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_0)) { + CAM_IntClr(CAM_INT_FIFO_OVERWRITE_0); + + if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_1)) { + CAM_IntClr(CAM_INT_FIFO_OVERWRITE_1); + + if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) { + CAM_IntClr(CAM_INT_HSYNC_CNT_ERROR); + + if (camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) { + CAM_IntClr(CAM_INT_VSYNC_CNT_ERROR); + + if (camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR] != NULL) { + /* call the callback function */ + camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR](); + } + } +} +#endif + +/*@} end of group CAM_Public_Functions */ + +/*@} end of group CAM */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_clock.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..8d3f58bbc9cd1bc03e5f682dec35fba4ea6260ef --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_clock.c @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file bl702_clock.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_clock.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup CLOCK + * @{ + */ + +/** @defgroup CLOCK_Private_Macros + * @{ + */ + +/*@} end of group CLOCK_Private_Macros */ + +/** @defgroup CLOCK_Private_Types + * @{ + */ + +/*@} end of group CLOCK_Private_Types */ + +/** @defgroup CLOCK_Private_Variables + * @{ + */ +static Clock_Cfg_Type clkCfg; + +/*@} end of group CLOCK_Private_Variables */ + +/** @defgroup CLOCK_Global_Variables + * @{ + */ + +/*@} end of group CLOCK_Global_Variables */ + +/** @defgroup CLOCK_Private_Fun_Declaration + * @{ + */ + +/*@} end of group CLOCK_Private_Fun_Declaration */ + +/** @defgroup CLOCK_Private_Functions + * @{ + */ + +/*@} end of group CLOCK_Private_Functions */ + +/** @defgroup CLOCK_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Set System Clock + * + * @param type: System clock type + * @param clock: System clock value + * + * @return None + * +*******************************************************************************/ +void Clock_System_Clock_Set(BL_System_Clock_Type type, uint32_t clock) +{ + if (type < BL_SYSTEM_CLOCK_MAX) { + clkCfg.systemClock[type] = clock / 1000000; + } +} + +/****************************************************************************/ /** + * @brief Set Peripheral Clock + * + * @param type: Peripheral clock type + * @param clock: Peripheral clock value + * + * @return None + * +*******************************************************************************/ +void Clock_Peripheral_Clock_Set(BL_AHB_Slave1_Type type, uint32_t clock) +{ + if (type < BL_AHB_SLAVE1_MAX) { + if (type == BL_AHB_SLAVE1_I2S) { + clkCfg.i2sClock = clock; + } else { + clkCfg.peripheralClock[type] = clock / 1000000; + } + } +} + +/****************************************************************************/ /** + * @brief Get System Clock + * + * @param type: System clock type + * + * @return System clock value + * +*******************************************************************************/ +uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type) +{ + if (type < BL_SYSTEM_CLOCK_MAX) { + return clkCfg.systemClock[type] * 1000000; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Get Peripheral Clock + * + * @param type: Peripheral clock type + * + * @return Peripheral clock value + * +*******************************************************************************/ +uint32_t Clock_Peripheral_Clock_Get(BL_AHB_Slave1_Type type) +{ + if (type < BL_AHB_SLAVE1_MAX) { + if (type == BL_AHB_SLAVE1_I2S) { + return clkCfg.i2sClock; + } else { + return clkCfg.peripheralClock[type] * 1000000; + } + } + + return 0; +} + +/*@} end of group CLOCK_Public_Functions */ + +/*@} end of group CLOCK */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c new file mode 100644 index 0000000000000000000000000000000000000000..1a3e908d8823f98e6a84c010cf6632caf6955064 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c @@ -0,0 +1,389 @@ +/** + ****************************************************************************** + * @file bl702_common.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "l1c_reg.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Periph_Driver + * @{ + */ + +/** @defgroup DRIVER_COMMON DRIVER_COMMON + * @brief Digger driver common functions + * @{ + */ + +/** @defgroup DRIVER_Private_Type + * @{ + */ + +/*@} end of group DRIVER_Private_Type*/ + +/** @defgroup DRIVER_Private_Defines + * @{ + */ + +/*@} end of group DRIVER_Private_Defines */ + +/** @defgroup DRIVER_Private_Variables + * @{ + */ +pFunc __Interrupt_Handlers[IRQn_LAST] = { 0 }; + +/*@} end of group DRIVER_Private_Variables */ + +/** @defgroup DRIVER_Global_Variables + * @{ + */ + +/*@} end of group DRIVER_Global_Variables */ + +/** @defgroup DRIVER_Private_FunctionDeclaration + * @{ + */ + +/*@} end of group DRIVER_Private_FunctionDeclaration */ + +/** @defgroup DRIVER_Private_Functions + * @{ + */ + +/*@} end of group DRIVER_Private_Functions */ + +/** @defgroup DRIVER_Public_Functions + * @{ + */ + +void Trap_Handler(void) +{ + unsigned long cause; + unsigned long epc; + unsigned long tval; + uint8_t isecall = 0; + + MSG("Trap_Handler\r\n"); + + cause = read_csr(mcause); + MSG("mcause=%08x\r\n", (uint32_t)cause); + epc = read_csr(mepc); + MSG("mepc:%08x\r\n", (uint32_t)epc); + tval = read_csr(mtval); + MSG("mtval:%08x\r\n", (uint32_t)tval); + + cause = (cause & 0x3ff); + + switch (cause) { + case 1: + MSG("Instruction access fault\r\n"); + break; + + case 2: + MSG("Illegal instruction\r\n"); + break; + + case 3: + MSG("Breakpoint\r\n"); + break; + + case 4: + MSG("Load address misaligned\r\n"); + break; + + case 5: + MSG("Load access fault\r\n"); + break; + + case 6: + MSG("Store/AMO address misaligned\r\n"); + break; + + case 7: + MSG("Store/AMO access fault\r\n"); + break; + + case 8: + MSG("Environment call from U-mode\r\n"); + epc += 4; + write_csr(mepc, epc); + break; + + case 11: + MSG("Environment call from M-mode\r\n"); + epc += 4; + write_csr(mepc, epc); + isecall = 1; + break; + + default: + MSG("Cause num=%d\r\n", (uint32_t)cause); + epc += 4; + write_csr(mepc, epc); + break; + } + + if (!isecall) { + while (1) + ; + } +} + +void Interrupt_Handler(void) +{ + pFunc interruptFun; + uint32_t num = 0; + volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL; + + /* Store a few register values that might be useful when determining why this + function was called. */ + __asm volatile("csrr %0, mepc" + : "=r"(ulMEPC)); + __asm volatile("csrr %0, mcause" + : "=r"(ulMCAUSE)); + + if ((ulMCAUSE & 0x80000000) == 0) { + /*Exception*/ + MSG("Exception should not be here\r\n"); + } else { + num = ulMCAUSE & 0x3FF; + + if (num < IRQn_LAST) { + interruptFun = __Interrupt_Handlers[num]; + + if (NULL != interruptFun) { + interruptFun(); + } else { + MSG("Interrupt num:%d IRQHandler not installed\r\n", (unsigned int)num); + + if (num >= IRQ_NUM_BASE) { + MSG("Peripheral Interrupt num:%d \r\n", (unsigned int)num - IRQ_NUM_BASE); + } + + while (1) + ; + } + } else { + MSG("Unexpected interrupt num:%d\r\n", (unsigned int)num); + } + } +} + +void trap_handler(void) +{ +#define MCAUSE_INT_MASK 0x80000000 // [31]=1 interrupt, else exception +#define MCAUSE_CODE_MASK 0x7FFFFFFF // low bits show code + + unsigned long mcause_value = read_csr(mcause); + if (mcause_value & MCAUSE_INT_MASK) { + // Branch to interrupt handler here + Interrupt_Handler(); + } else { + // Branch to exception handle + Trap_Handler(); + } +} + +void FreeRTOS_Interrupt_Handler(void) +{ + Interrupt_Handler(); +} + +void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) +{ + if (irq < IRQn_LAST) { + __Interrupt_Handlers[irq] = interruptFun; + } +} + +/****************************************************************************/ /** + * @brief delay us + * + * @param[in] core: systemcoreclock + * + * @param[in] cnt: delay cnt us + * + * @return none + * + *******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +#ifdef ARCH_ARM +#ifndef __GNUC__ +__WEAK +__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2, #0x01 cmp r2, #0x00 bne loop end bx lr +} +#else +__WEAK +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + __asm__ __volatile__( + "lsr r0,#0x10\n\t" + "mul r0,r1,r0\n\t" + "mov r2,r0\n\t" + "lsr r2,#0x04\n\t" + "lsr r2,#0x03\n\t" + "cmp r2,#0x01\n\t" + "beq end\n\t" + "cmp r2,#0x00\n\t" + "beq end\n" + "loop :" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "sub r2,r2,#0x01\n\t" + "cmp r2,#0x00\n\t" + "bne loop\n" + "end :" + "mov r0,r0\n\t"); +} +#endif +#endif +#ifdef ARCH_RISCV +__WEAK +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + uint32_t codeAddress = 0; + uint32_t divVal = 40; + + codeAddress = (uint32_t)&ASM_Delay_Us; + + /* 1M=100K*10, so multiple is 10 */ + /* loop function take 4 instructions, so instructionNum is 4 */ + /* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */ + /* divVal = multiple*instructionNum*irom2TAccess */ + if (((codeAddress & (0xF << 24)) >> 24) == 0x01) { + /* IROM space */ + if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) { + /* instruction 2T */ + divVal = 80; + } + } + + __asm__ __volatile__( + ".align 4\n\t" + "lw a4,%1\n\t" + "lui a5,0x18\n\t" + "addi a5,a5,1696\n\t" + "divu a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a4,%1\n\t" + "lw a5,%0\n\t" + "mul a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a4,%1\n\t" + "lw a5,%2\n\t" + "divu a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a5,%1\n\t" + "li a4,0x1\n\t" + "beq a5,zero,end\n\t" + "beq a5,a4,end\n\t" + "nop\n\t" + "nop\n\t" + ".align 4\n\t" + "loop :\n" + "addi a4,a5,-1\n\t" + "mv a5,a4\n\t" + "bnez a5,loop\n\t" + "nop\n\t" + "end :\n\t" + "nop\n" + : /* output */ + : "m"(cnt), "m"(core), "m"(divVal) /* input */ + : "t1", "a4", "a5" /* destruct description */ + ); +} +#endif +#endif + +/****************************************************************************/ /** + * @brief delay us + * + * @param[in] cnt: delay cnt us + * + * @return none + * + *******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION BL702_Delay_US(uint32_t cnt) +{ + ASM_Delay_Us(SystemCoreClockGet(), cnt); +} +#endif +/****************************************************************************/ /** + * @brief delay ms + * + * @param[in] cnt: delay cnt ms + * + * @return none + * + *******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION BL702_Delay_MS(uint32_t cnt) +{ + uint32_t i = 0; + uint32_t count = 0; + + if (cnt >= 1024) { + /* delay (n*1024) ms */ + count = 1024; + + for (i = 0; i < (cnt / 1024); i++) { + BL702_Delay_US(1024 * 1000); + } + } + + if (cnt & 0x3FF) { + /* delay (1-1023)ms */ + count = cnt & 0x3FF; + BL702_Delay_US(count * 1000); + } + + //BL702_Delay_US(((cnt<<10)-(cnt<<4)-(cnt<<3))); +} +#endif +/* +char *_sbrk(int incr) +{} +*/ +/*@} end of group DRIVER_Public_Functions */ + +/*@} end of group DRIVER_COMMON */ + +/*@} end of group BL702_Periph_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dac.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..1243d8ee14db60ed7ebd0c431c3facd48bd181aa --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dac.c @@ -0,0 +1,518 @@ +/** + ****************************************************************************** + * @file bl702_dac.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_dac.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ +#define GPIP_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group DAC_Private_Macros */ + +/** @defgroup DAC_Private_Types + * @{ + */ + +/*@} end of group DAC_Private_Types */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/*@} end of group DAC_Private_Variables */ + +/** @defgroup DAC_Global_Variables + * @{ + */ + +/*@} end of group DAC_Global_Variables */ + +/** @defgroup DAC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group DAC_Private_Fun_Declaration */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/*@} end of group DAC_Private_Functions */ + +/** @defgroup DAC_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief DAC initialization + * + * @param cfg: DAC configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); + + /* Set DAC config */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel); + + if (ENABLE == cfg->resetChanA) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + if (ENABLE == cfg->resetChanB) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + /* Clear reset */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief DAC channel A initialization + * + * @param cfg: DAC channel configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); + + /* Set channel A config */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_OUTMUX, cfg->outMux); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanEn); + + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief DAC channel B initialization + * + * @param cfg: DAC channel configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); + + /* Set channel A config */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_OUTMUX, cfg->outMux); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanEn); + + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief Select DAC channel B source + * + * @param src: DAC channel B source selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src)); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, src); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Select DAC channel A source + * + * @param src: DAC channel A source selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src)); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, src); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable DAC channel B + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanB_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN2); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable DAC channel B + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanB_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN2); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable DAC channel A + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanA_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable DAC channel A + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanA_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Select DAC DMA TX format + * + * @param fmt: DAC DMA TX format selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt)); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, fmt); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable DAC DMA TX + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable DAC DMA TX + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable DAC DMA TX + * + * @param data: The data to be send + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_DMA_WriteData(uint32_t data) +{ + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_WDATA, data); +} + +/****************************************************************************/ /** + * @brief AON and GPIP DAC config + * + * @param cfg: AON and GPIP DAC configuration + * + * @return config success or not + * +*******************************************************************************/ +BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); + CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->div)); + CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt)); + + /* AON Set DAC config */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel); + + if (ENABLE == cfg->resetChanA) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + if (ENABLE == cfg->resetChanB) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + /* AON Clear reset */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + + /* GPIP Set DAC config */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, cfg->div); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* GPIP Set DMA config */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_TX_EN, cfg->dmaEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, cfg->dmaFmt); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AON and GPIP DAC channel A config + * + * @param cfg: AON and GPIP DAC channel A configuration + * + * @return None + * +*******************************************************************************/ +void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src)); + + /* GPIP select source */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, cfg->src); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* GPIP enable or disable channel */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* AON enable or disable channel */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanCovtEn); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief AON and GPIP DAC channel B config + * + * @param cfg: AON and GPIP DAC channel B configuration + * + * @return None + * +*******************************************************************************/ +void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src)); + + /* GPIP select source */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, cfg->src); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* GPIP enable or disable channel */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN2, cfg->chanEn); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* AON enable or disable channel */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanCovtEn); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief DAC channel A set value + * + * @param val: DAC value + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanA_Value(uint16_t val) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_DATA); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_DATA, val); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_DATA, tmpVal); +} + +/****************************************************************************/ /** + * @brief DAC channel B set value + * + * @param val: DAC value + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanB_Value(uint16_t val) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_DATA); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_DATA, val); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_DATA, tmpVal); +} + +/*@} end of group DAC_Public_Functions */ + +/*@} end of group DAC */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dma.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..dce68185a8f11c8394f74229fc90b97608dd920f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dma.c @@ -0,0 +1,750 @@ +/** + ****************************************************************************** + * @file bl702_dma.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702.h" +#include "bl702_dma.h" +#include "string.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ +#define DMA_CHANNEL_OFFSET 0x100 +#define DMA_Get_Channel(ch) (DMA_BASE + DMA_CHANNEL_OFFSET + (ch)*0x100) +static intCallback_Type *dmaIntCbfArra[DMA_CH_MAX][DMA_INT_ALL] = { + { NULL, NULL }, + { NULL, NULL }, + { NULL, NULL }, + { NULL, NULL } +}; +static DMA_LLI_Ctrl_Type PingPongListArra[DMA_CH_MAX][2]; + +/*@} end of group DMA_Private_Macros */ + +/** @defgroup DMA_Private_Types + * @{ + */ + +/*@} end of group DMA_Private_Types */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/*@} end of group DMA_Private_Variables */ + +/** @defgroup DMA_Global_Variables + * @{ + */ + +/*@} end of group DMA_Global_Variables */ + +/** @defgroup DMA_Private_Fun_Declaration + * @{ + */ + +/*@} end of group DMA_Private_Fun_Declaration */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief DMA interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void DMA_ALL_IRQHandler(void) +{ + uint32_t tmpVal; + uint32_t intClr; + uint8_t ch; + /* Get DMA register */ + uint32_t DMAChs = DMA_BASE; + + for (ch = 0; ch < DMA_CH_MAX; ch++) { + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); + + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) { + /* Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); + intClr |= (1 << ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); + BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); + + if (dmaIntCbfArra[ch][DMA_INT_TCOMPLETED] != NULL) { + /* Call the callback function */ + dmaIntCbfArra[ch][DMA_INT_TCOMPLETED](); + } + } + } + + for (ch = 0; ch < DMA_CH_MAX; ch++) { + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); + + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) { + /*Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); + intClr |= (1 << ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); + BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); + + if (dmaIntCbfArra[ch][DMA_INT_ERR] != NULL) { + /* Call the callback function */ + dmaIntCbfArra[ch][DMA_INT_ERR](); + } + } + } +} +#endif + +/*@} end of group DMA_Private_Functions */ + +/** @defgroup DMA_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief DMA enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void DMA_Enable(void) +{ + uint32_t tmpVal; + /* Get DMA register */ + uint32_t DMAChs = DMA_BASE; + + tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal); +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(DMA_ALL_IRQn, DMA_ALL_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief DMA disable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void DMA_Disable(void) +{ + uint32_t tmpVal; + /* Get DMA register */ + uint32_t DMAChs = DMA_BASE; + + tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA channel init + * + * @param chCfg: DMA configuration + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(chCfg->ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch)); + CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth)); + CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth)); + CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSzie)); + CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSzie)); + CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph)); + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_DMA); + + /* Config channel config */ + BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr); + BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSzie); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSzie); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_ADD_MODE, chCfg->dstAddMode); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_MIN_MODE, chCfg->dstMinMode); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FIX_CNT, chCfg->fixCnt); + + /* FIXME: how to deal with SLargerD */ + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_SLARGERD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA channel update source memory address and len + * + * @param ch: DMA channel + * @param memAddr: source memoty address + * @param len: source memory data length + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* config channel config*/ + BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA channel update destination memory address and len + * + * @param ch: DMA channel + * @param memAddr: destination memoty address + * @param len: destination memory data length + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* config channel config*/ + BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); +} + +/****************************************************************************/ /** + * @brief Get DMA channel tranfersize + * + * @param ch: DMA channel + * + * @return tranfersize size + * +*******************************************************************************/ +uint32_t DMA_Channel_TranferSize(uint8_t ch) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE); +} + +/****************************************************************************/ /** + * @brief Get DMA channel busy status + * + * @param ch: DMA channel + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief DMA enable + * + * @param ch: DMA channel number + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Enable(uint8_t ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA disable + * + * @param ch: DMA channel number + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Disable(uint8_t ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA init LLI transfer + * + * @param ch: DMA channel number + * @param lliCfg: LLI configuration + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_Init(uint8_t ch, DMA_LLI_Cfg_Type *lliCfg) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph)); + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_DMA); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief DMA channel update LLI + * + * @param ch: DMA channel number + * @param LLI: LLI addr + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_Update(uint8_t ch, uint32_t LLI) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* Config channel config */ + //BL_WR_REG(DMAChs, DMA_LLI, LLI); + BL702_MemCpy4((uint32_t *)DMAChs, (uint32_t *)LLI, 4); +} + +/****************************************************************************/ /** + * @brief DMA LLI PingPong Structure Start + * + * @param dmaPpStruct: dma pp struct pointer + * @param Ping_Transfer_len: ping len + * @param Pong_Transfer_len: pong len + * + * @return Succrss or not + * +*******************************************************************************/ +BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len) +{ + struct DMA_Control_Reg dmaCtrlRegVal_temp; + + if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) { + return ERROR; + } + + dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl; + dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp; + + dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl; + dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp; + + DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg); + DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief DMA LLI Start New Transmit for Ping-Pong Buf + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf) +{ + CPU_Interrupt_Disable(DMA_ALL_IRQn); + + if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) { + DMA_LLI_Update(dmaPpBuf->dmaChan, (uint32_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]); + DMA_Channel_Enable(dmaPpBuf->dmaChan); + dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0; + } + + CPU_Interrupt_Enable(DMA_ALL_IRQn); +} + +/****************************************************************************/ /** + * @brief DMA LLI Remove Completed Ping-Pong Buf List + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return Next Ping-Pong Buf List Header + * +*******************************************************************************/ +DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf) +{ + CPU_Interrupt_Disable(DMA_ALL_IRQn); + + dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL; + CPU_Interrupt_Enable(DMA_ALL_IRQn); + return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex]; +} + +/****************************************************************************/ /** + * @brief DMA LLI Append Buf to List + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * @param dmaLliList: New LLI Buf to Append + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList) +{ + DMA_LLI_Ctrl_Type *pLliList = NULL; + CPU_Interrupt_Disable(DMA_ALL_IRQn); + + pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]; + + if (pLliList == NULL) { + dmaLliList->nextLLI = 0; + dmaLliList->dmaCtrl.I = 1; + dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList; + } else { + /*Append to last */ + while (pLliList->nextLLI != 0) { + pLliList = (DMA_LLI_Ctrl_Type *)pLliList->nextLLI; + } + + pLliList->nextLLI = (uint32_t)dmaLliList; + pLliList->dmaCtrl.I = 0; + dmaLliList->nextLLI = 0; + dmaLliList->dmaCtrl.I = 1; + } + + if (DMA_Channel_Is_Busy(dmaPpBuf->dmaChan) == RESET) { + /* DMA stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable) + or has already stopped before this function is called */ + if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) { + /* DMA has already stopped before this function is called */ + DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf); + } + } + + CPU_Interrupt_Enable(DMA_ALL_IRQn); +} + +/****************************************************************************/ /** + * @brief DMA LLi Destroy Ping-Pong Buf + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf) +{ + /* DMA LLI Disable */ + DMA_Channel_Disable(dmaPpBuf->dmaChan); + + if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) { + dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]); + } + + dmaPpBuf->lliListHeader[0] = NULL; + + if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) { + dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]); + } + + dmaPpBuf->lliListHeader[1] = NULL; + dmaPpBuf->idleIndex = 0; +} + +/****************************************************************************/ /** + * @brief Mask/Unmask the DMA interrupt + * + * @param ch: DMA channel number + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void DMA_IntMask(uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + CHECK_PARAM(IS_DMA_INT_TYPE(intType)); + + switch (intType) { + case DMA_INT_TCOMPLETED: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } + + break; + + case DMA_INT_ERR: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + } + + break; + + case DMA_INT_ALL: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief Install DMA interrupt callback function + * + * @param dmaChan: DMA Channel type + * @param intType: DMA interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan)); + CHECK_PARAM(IS_DMA_INT_TYPE(intType)); + + dmaIntCbfArra[dmaChan][intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief DMA LLI PingPong Structure Initial + * + * @param dmaPpStruct: DMA LLI PingPong Config Parameter + * + * @return start success or not + * +*******************************************************************************/ +BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct) +{ + //setup lliList + dmaPpStruct->dmaCtrlRegVal.I = 1; + dmaPpStruct->trans_index = 0; + + if (dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_M2P) { + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[0]; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[1]; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; + } else if (dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_P2M) { + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->chache_buf_addr[0]; + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->chache_buf_addr[1]; + } else { + return ERROR; + /*V1.0 version DMA LLI Ping-Pong structure not support P2P & M2M MODE*/ + } + + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX]; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; + + DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg); + + DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief DMA LLI PingPong Structure Start + * + * @param dmaPpStruct: None + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct) +{ + DMA_Channel_Enable(dmaPpStruct->dmaChan); +} + +/****************************************************************************/ /** + * @brief DMA LLI PingPong Structure Stop + * + * @param dmaPpStruct: None + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct) +{ + DMA_Channel_Disable(dmaPpStruct->dmaChan); +} + +/*@} end of group DMA_Public_Functions */ + +/*@} end of group DMA */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..7f52a248b50cd25b9e039c2078b8c128849dd957 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c @@ -0,0 +1,1728 @@ +/** + ****************************************************************************** + * @file bl702_sec_ef_ctrl.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl702_ef_ctrl.h" +#include "ef_data_0_reg.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_EF_CTRL + * @{ + */ + +/** @defgroup SEC_EF_CTRL_Private_Macros + * @{ + */ +#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) +#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) +#define EF_CTRL_DFT_TIMEOUT_VAL (160 * 1000) +#ifndef BOOTROM +#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() +#else +#define EF_CTRL_LOAD_BEFORE_READ_R0 +#endif +#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, EF_CTRL_EFUSE_R0_SIZE / 4) + +/*@} end of group SEC_EF_CTRL_Private_Macros */ + +/** @defgroup SEC_EF_CTRL_Private_Types + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Types */ + +/** @defgroup SEC_EF_CTRL_Private_Variables + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Variables */ + +/** @defgroup SEC_EF_CTRL_Global_Variables + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Global_Variables */ + +/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ + +/** @defgroup SEC_EF_CTRL_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Switch efuse region 0 control to AHB clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +/* static */ void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) +{ + uint32_t tmpVal; + uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; + + while (EF_Ctrl_Busy() == SET) { + timeout--; + + if (timeout == 0) { + break; + } + } + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Program efuse region 0 + * + * @param None + * + * @return None + * +*******************************************************************************/ +static void EF_Ctrl_Program_Efuse_0(void) +{ + uint32_t tmpVal; + + /* Select auto mode and select ef clock */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + /* Program */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (1 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (1 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + /* Add delay for POR to be stable */ + BL702_Delay_US(4); + + /* Trigger */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (1 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (1 << EF_CTRL_EF_IF_0_RW_POS) | + (1 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); +} + +/*@} end of group SEC_EF_CTRL_Private_Functions */ + +/** @defgroup SEC_EF_CTRL_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Load efuse region 0 + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) +{ + uint32_t tmpVal; + uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; + + EF_CTRL_DATA0_CLEAR; + + /* Trigger read */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (1 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + BL702_Delay_US(10); + + /* Wait for efuse control idle*/ + do { + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); + timeout--; + + if (timeout == 0) { + break; + } + } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || + + (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); + + /* Switch to AHB clock */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Check efuse busy status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); + + if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY)) { + return SET; + } + + return RESET; +} +#endif + +/****************************************************************************/ /** + * @brief Check efuse whether finish loading + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type EF_Ctrl_AutoLoad_Done(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); + + if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Efuse write debug password + * + * @param passWdLow: password low 32 bits + * @param passWdHigh: password high 32 bits + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read debug password + * + * @param passWdLow: password low 32 bits pointer to store value + * @param passWdHigh: password high 32 bits pointer to store value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh) +{ + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); + *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); +} + +/****************************************************************************/ /** + * @brief Efuse lock reading for passwd + * + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse lock writing for passwd + * + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read security configuration + * + * @param cfg: security configuration pointer + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read security configuration + * + * @param cfg: security configuration pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + + cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE); + cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS); + cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN); +} + +/****************************************************************************/ /** + * @brief Efuse write security boot configuration + * + * @param sign[1]: Sign configuration pointer + * @param aes[1]: AES configuration pointer + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]); + + if (aes[0] != EF_CTRL_SF_AES_NONE) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN, 1); + } + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse write security boot configuration + * + * @param sign[1]: Sign configuration pointer + * @param aes[1]: AES configuration pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE); + sign[0] = (EF_Ctrl_Sign_Type)(tmpVal2 & 0x01); + + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN); + + if (tmpVal2) { + aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE); + } else { + aes[0] = EF_CTRL_SF_AES_NONE; + } +} + +/****************************************************************************/ /** + * @brief Analog Trim parity calculate + * + * @param val: Value of efuse trim data + * @param len: Length of bit to calculate + * + * @return Parity bit value + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) +{ + uint8_t cnt = 0; + uint8_t i = 0; + + for (i = 0; i < len; i++) { + if (val & (1 << i)) { + cnt++; + } + } + + return cnt & 0x01; +} +#endif + +/****************************************************************************/ /** + * @brief Efuse write analog trim + * + * @param index: index of analog trim + * @param trim: trim value + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (index == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, trim); + } + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read analog trim + * + * @param index: index of analog trim + * @param trim: trim value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + if (index == 0) { + *trim = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + } +} + +/****************************************************************************/ /** + * @brief Efuse read RC32M trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) +{ + uint32_t tmpVal = 0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + trim->trimRc32mCodeFrExt = (tmpVal >> 10) & 0xff; + trim->trimRc32mCodeFrExtParity = (tmpVal >> 18) & 0x01; + trim->trimRc32mExtCodeEn = (tmpVal >> 19) & 0x01; +} +#endif + +/****************************************************************************/ /** + * @brief Efuse read RC32K trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) +{ + uint32_t tmpVal = 0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + trim->trimRc32kCodeFrExt = (tmpVal >> 20) & 0x3ff; + trim->trimRc32kCodeFrExtParity = (tmpVal >> 30) & 0x01; + trim->trimRc32kExtCodeEn = (tmpVal >> 31) & 0x01; +} +#endif + +/****************************************************************************/ /** + * @brief Efuse read TSEN trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) +{ + uint32_t tmpVal = 0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + trim->tsenRefcodeCornerEn = tmpVal & 0x01; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + trim->tsenRefcodeCorner = tmpVal & 0xfff; + trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); + trim->tsenRefcodeCornerVersion = (tmpVal >> 30) & 0x01; +} + +/****************************************************************************/ /** + * @brief Efuse read ADC Gain trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) +{ + uint32_t tmpVal = 0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + trim->adcGainCoeff = (tmpVal >> 1) & 0xfff; + trim->adcGainCoeffParity = (tmpVal >> 13) & 0x01; + trim->adcGainCoeffEn = (tmpVal >> 14) & 0x01; +} + +/****************************************************************************/ /** + * @brief Efuse write software usage + * + * @param index: index of software usage + * @param usage: usage value + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) +{ + /* switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (index == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage); + } + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read software usage + * + * @param index: index of software usage + * @param usage: usage value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + if (index == 0) { + *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); + } +} + +/****************************************************************************/ /** + * @brief Efuse read software usage + * + * @param index: index of software usage + * @param program: usage value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + + if (index == 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0); + } + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse write MAC address + * + * @param mac[6]: MAC address buffer + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* The low 32 bits */ + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); + /* The high 16 bits */ + tmpVal = machigh[0] + (machigh[1] << 8); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse Ctrl get zero bit count + * + * @param val: Value to count + * + * @return Zero bit count + * +*******************************************************************************/ +static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) +{ + uint32_t cnt = 0; + uint32_t i = 0; + + for (i = 0; i < 8; i++) { + if ((val & (1 << i)) == 0) { + cnt += 1; + } + } + + return cnt; +} + +/****************************************************************************/ /** + * @brief Efuse read MAC address + * + * @param mac[8]: MAC address buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal; + uint32_t i = 0; + uint32_t cnt = 0; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); + BL_WRWD_TO_BYTEP(maclow, tmpVal); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + BL_WRWD_TO_BYTEP(machigh, tmpVal); + + /* Get original parity */ + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); + + /* Check parity */ + for (i = 0; i < 8; i++) { + cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + + if ((cnt & 0x3f) == (tmpVal & 0x3f)) { + return SUCCESS; + } else { + return ERROR; + } +} + +/****************************************************************************/ /** + * @brief Efuse read MAC address + * + * @param mac[7]: MAC address buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); + BL_WRWD_TO_BYTEP(maclow, tmpVal); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + machigh[0] = tmpVal & 0xff; + machigh[1] = (tmpVal >> 8) & 0xff; + machigh[2] = (tmpVal >> 16) & 0xff; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse lock writing for MAC address + * + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_MAC_Address(uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Whether a value bits is all zero + * + * @param val: value to check + * @param start: start bit + * @param len: total length of bits to check + * + * @return 1 for all bits zero 0 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) +{ + uint32_t mask = 0; + + val = (val >> start); + + if (len >= 32) { + mask = 0xffffffff; + } else { + mask = (1 << len) - 1; + } + + if ((val & mask) == 0) { + return 1; + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief Whether MAC address slot is empty + * + * @param slot: MAC address slot + * @param reload: whether reload to check + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload) +{ + uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff; + uint32_t part1Empty = 0, part2Empty = 0; + + if (slot == 0) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); + tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + } else if (slot == 1) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0); + tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); + } else if (slot == 2) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); + tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); + } + + part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32)); + part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22)); + + return (part1Empty && part2Empty); +} + +/****************************************************************************/ /** + * @brief Efuse write optional MAC address + * + * @param slot: MAC address slot + * @param mac[6]: MAC address buffer + * @param program: Whether program + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal; + uint32_t i = 0, cnt; + + if (slot >= 3) { + return ERROR; + } + + /* Change to local order */ + for (i = 0; i < 3; i++) { + tmpVal = mac[i]; + mac[i] = mac[5 - i]; + mac[5 - i] = tmpVal; + } + + if (slot == 2) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + } else { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + } + + /* The low 32 bits */ + if (slot == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); + } else if (slot == 1) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0, BL_RDWD_FRM_BYTEP(maclow)); + } else if (slot == 2) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, BL_RDWD_FRM_BYTEP(maclow)); + } + + /* The high 16 bits */ + tmpVal = machigh[0] + (machigh[1] << 8); + cnt = 0; + + for (i = 0; i < 6; i++) { + cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + + tmpVal |= ((cnt & 0x3f) << 16); + + if (slot == 0) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); + } else if (slot == 1) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, tmpVal); + } else if (slot == 2) { + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, tmpVal); + } + + if (program) { + if (slot == 2) { + EF_Ctrl_Program_Efuse_0(); + } else { + EF_Ctrl_Program_Efuse_0(); + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse read optional MAC address + * + * @param slot: MAC address slot + * @param mac[6]: MAC address buffer + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpVal = 0; + uint32_t i = 0; + uint32_t cnt = 0; + + if (slot >= 3) { + return ERROR; + } + + /* Trigger read data from efuse */ + if (reload) { + if (slot == 2) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } else { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + } + + if (slot == 0) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); + } else if (slot == 1) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0); + } else if (slot == 2) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); + } + + BL_WRWD_TO_BYTEP(maclow, tmpVal); + + if (slot == 0) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + } else if (slot == 1) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); + } else if (slot == 2) { + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); + } + + machigh[0] = tmpVal & 0xff; + machigh[1] = (tmpVal >> 8) & 0xff; + + /* Check parity */ + for (i = 0; i < 6; i++) { + cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + + if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { + /* Change to network order */ + for (i = 0; i < 3; i++) { + tmpVal = mac[i]; + mac[i] = mac[5 - i]; + mac[5 - i] = tmpVal; + } + + return SUCCESS; + } else { + return ERROR; + } +} + +/****************************************************************************/ /** + * @brief Efuse read chip ID + * + * @param chipID[8]: Chip ID buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) +{ + return EF_Ctrl_Read_MAC_Address(chipID); +} + +/****************************************************************************/ /** + * @brief Efuse get chip PID&&VID + * + * @param pid[1]: Chip PID + * @param vid[1]: Chip VID + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W3); + pid[0] = (uint16_t)(tmpVal & 0xFFFF); + vid[0] = (uint16_t)(tmpVal >> 16); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse get customer PID&&VID + * + * @param pid[1]: Customer PID + * @param vid[1]: Customer VID + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W2); + pid[0] = (uint16_t)(tmpVal & 0xFFFF); + vid[0] = (uint16_t)(tmpVal >> 16); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse read device info + * + * @param deviceInfo: Device info pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo) +{ + uint32_t tmpVal; + uint32_t *p = (uint32_t *)deviceInfo; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); + *p = tmpVal; +} + +/****************************************************************************/ /** + * @brief Whether Capcode is empty + * + * @param reload: Whether reload + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t reload) +{ + uint32_t tmp = 0xffffffff; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + return (EF_Ctrl_Is_All_Bits_Zero(tmp, 2, 8)); +} + +/****************************************************************************/ /** + * @brief Efuse write Cap code + * + * @param code: Cap code value + * @param program: Whether program + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t code, uint8_t program) +{ + uint32_t tmp; + uint8_t trim; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + + trim = code; + trim |= ((EF_Ctrl_Get_Trim_Parity(code, 6)) << 6); + trim |= (1 << 7); + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp | (trim << 2)); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } + + while (SET == EF_Ctrl_Busy()) + ; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse read Cap code + * + * @param code: Cap code pointer + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t *code, uint8_t reload) +{ + uint32_t tmp; + Efuse_Capcode_Info_Type *trim = (Efuse_Capcode_Info_Type *)&tmp; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0)) >> 2; + + if (trim->en) { + if (trim->parity == EF_Ctrl_Get_Trim_Parity(trim->capCode, 6)) { + *code = trim->capCode; + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Whether power offset slot is empty + * + * @param slot: Power offset code slot + * @param reload: Whether reload + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload) +{ + uint32_t tmp1 = 0xffffffff; + uint32_t part1Empty = 0, part2Empty = 0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if (slot == 0) { + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 15, 17)); + part2Empty = 1; + } else if (slot == 1) { + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1); + part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 16)); + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 1)); + } else if (slot == 2) { + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1); + part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 16)); + + tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 1, 1)); + } + + return (part1Empty && part2Empty); +} + +/****************************************************************************/ /** + * @brief Efuse write power offset + * + * @param slot: Power offset slot + * @param pwrOffset[3]: Power offset value array + * @param program: Whether program + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program) +{ + uint64_t tmp = 0; + uint32_t k = 0; + uint64_t Value = 0; + uint8_t parity; + + if (slot >= 3) { + return ERROR; + } + + for (k = 0; k < 3; k++) { + /* Use 5 bits as signed value */ + if (pwrOffset[k] > 15) { + pwrOffset[k] = 15; + } + + if (pwrOffset[k] < -16) { + pwrOffset[k] = -16; + } + + tmp = ((uint64_t)((pwrOffset[k]) & 0x1f)) << (k * 5); + Value += tmp; + } + + parity = EF_Ctrl_Get_Trim_Parity(Value, 15); + + if (slot == 0) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + tmp |= (Value << 16); + tmp |= (1 << 15); + tmp |= (uint32_t)(parity << 31); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp); + } else if (slot == 1) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1); + tmp |= (Value << 0); + tmp |= (uint32_t)(parity << 15); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1, tmp); + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + tmp |= (1 << 0); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp); + } else if (slot == 2) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1); + tmp |= (Value << 16); + tmp |= (uint32_t)(parity << 31); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1, tmp); + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + tmp |= (1 << 1); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp); + } + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } + + while (SET == EF_Ctrl_Busy()) + ; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Efuse read poweroffset value + * + * @param slot: Power offset slot + * @param pwrOffset[3]: Power offset array + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload) +{ + uint64_t pwrOffsetValue = 0; + + uint32_t tmp = 0, k; + uint8_t en = 0, parity = 0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if (reload) { + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if (slot == 0) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); + en = (tmp >> 15) & 0x01; + pwrOffsetValue = (tmp >> 16) & 0x7fff; + parity = (tmp >> 31) & 0x01; + } else if (slot == 1) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1); + pwrOffsetValue = (tmp >> 0) & 0x7fff; + parity = (tmp >> 15) & 0x01; + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + en = (tmp >> 0) & 0x01; + } else if (slot == 2) { + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1); + pwrOffsetValue = (tmp >> 16) & 0x7fff; + parity = (tmp >> 31) & 0x01; + + tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); + en = (tmp >> 1) & 0x01; + } + + if (en) { + if (parity == EF_Ctrl_Get_Trim_Parity(pwrOffsetValue, 15)) { + for (k = 0; k < 3; k++) { + tmp = (pwrOffsetValue >> (k * 5)) & 0x1f; + + if (tmp >= 16) { + pwrOffset[k] = tmp - 32; + } else { + pwrOffset[k] = tmp; + } + } + + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Efuse write AES key + * + * @param index: index of key slot + * @param keyData: key data buffer + * @param len: key data length in words + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) +{ + uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); + + if (index > 5) { + return; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Every key is 4 words len*/ + BL702_MemCpy4(pAESKeyStart0 + index * 4, keyData, len); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse read AES key from specified region and index + * + * @param index: index of key slot + * @param keyData: key data buffer + * @param len: key data length in words + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) +{ + uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); + + if (index > 5) { + return; + } + + /* Trigger read data from efuse*/ + EF_CTRL_LOAD_BEFORE_READ_R0; + + /* Every key is 4 words len*/ + BL702_MemCpy4(keyData, pAESKeyStart0 + index * 4, len); +} + +/****************************************************************************/ /** + * @brief Efuse lock writing for aes key + * + * @param index: index of key slot + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) +{ + uint32_t tmpVal; + + if (index > 5) { + return; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + + if (index <= 3) { + tmpVal |= (1 << (index + 19)); + } else { + tmpVal |= (1 << (index + 19)); + tmpVal |= (1 << (index - 4 + 13)); + } + + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Efuse lock reading for aes key + * + * @param index: index of key slot + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) +{ + uint32_t tmpVal; + + if (index > 5) { + return; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); + tmpVal |= (1 << (index + 26)); + BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); + + if (program) { + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************/ /** + * @brief Program data to efuse region 0 + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Add delay for CLK to be stable */ + BL702_Delay_US(4); + + BL702_MemCpy4(pEfuseStart0 + index, data, len); + + EF_Ctrl_Program_Efuse_0(); +} + +/****************************************************************************/ /** + * @brief Read data from efuse region 0 + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + BL702_MemCpy4(data, pEfuseStart0 + index, len); +} + +/****************************************************************************/ /** + * @brief Clear efuse data register + * + * @param index: index of efuse in word + * @param len: data length + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + uint32_t i = 0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Clear data */ + for (i = 0; i < len; i++) { + pEfuseStart0[index + i] = 0; + } +} +#endif + +/****************************************************************************/ /** + * @brief efuse ctrl crc enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Crc_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET); + BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); + tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN); + BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief efuse ctrl get crc busy status + * + * @param None + * + * @return DISABLE or ENABLE + * +*******************************************************************************/ +BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); + return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY); +} + +/****************************************************************************/ /** + * @brief efuse ctrl set golden value + * + * @param goldenValue: Crc golden value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) +{ + BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); +} + +/****************************************************************************/ /** + * @brief efuse ctrl get crc result + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Crc_Result(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); + return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR); +} + +/*@} end of group SEC_EF_CTRL_Public_Functions */ + +/*@} end of group SEC_EF_CTRL */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_emac.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_emac.c new file mode 100644 index 0000000000000000000000000000000000000000..04b9becc6e4903bbda2364f7eb6407184f5515f5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_emac.c @@ -0,0 +1,647 @@ +/** + ****************************************************************************** + * @file bl702_emac.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702.h" +#include "bl702_emac.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup EMAC + * @{ + */ + +/** @defgroup EMAC_Private_Macros + * @{ + */ +#define PHY_MAX_RETRY (0x3F0) + +/*@} end of group EMAC_Private_Macros */ + +/** @defgroup EMAC_Private_Types + * @{ + */ + +/*@} end of group EMAC_Private_Types */ + +/** @defgroup EMAC_Private_Variables + * @{ + */ +static intCallback_Type *emacIntCbfArra[EMAC_INT_CNT] = { NULL }; + +/*@} end of group EMAC_Private_Variables */ + +/** @defgroup EMAC_Global_Variables + * @{ + */ + +/*@} end of group EMAC_Global_Variables */ + +/** @defgroup EMAC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group EMAC_Private_Fun_Declaration */ + +/** @defgroup EMAC_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Set MAC Address + * + * @param macAddr[6]: MAC address buffer array + * + * @return None + * +*******************************************************************************/ +static void EMAC_SetMACAddress(uint8_t macAddr[6]) +{ + BL_WR_REG(EMAC_BASE, EMAC_MAC_ADDR1, (macAddr[0] << 8) | macAddr[1]); + BL_WR_REG(EMAC_BASE, EMAC_MAC_ADDR0, (macAddr[2] << 24) | (macAddr[3] << 16) | (macAddr[4] << 8) | (macAddr[5] << 0)); +} + +/****************************************************************************/ /** + * @brief Set PHY Address + * + * @param phyAddress: Phy address + * + * @return None + * +*******************************************************************************/ +void EMAC_Phy_SetAddress(uint16_t phyAddress) +{ + uint32_t tmpVal; + + /* Set Phy Address */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FIAD, phyAddress); + BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal); +} + +/****************************************************************************/ /** + * @brief Set PHY Address + * + * @param phyAddress: Phy address + * + * @return None + * +*******************************************************************************/ +void EMAC_Phy_Set_Full_Duplex(uint8_t fullDuplex) +{ + uint32_t tmpVal; + + /* Set MAC duplex config */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FULLD, fullDuplex); + BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal); +} + +/****************************************************************************/ /** + * @brief Read PHY register + * + * @param phyReg: PHY register + * @param regValue: PHY register value pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_Phy_Read(uint16_t phyReg, uint16_t *regValue) +{ + uint32_t tmpVal; + + /* Set Register Address */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg); + BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal); + + /* Trigger read */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIICOMMAND); + tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RSTAT); + BL_WR_REG(EMAC_BASE, EMAC_MIICOMMAND, tmpVal); + + BL_DRV_DUMMY; + + do { + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIISTATUS); + BL702_Delay_US(16); + } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY)); + + *regValue = BL_RD_REG(EMAC_BASE, EMAC_MIIRX_DATA); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Write PHY register + * + * @param phyReg: PHY register + * @param regValue: PHY register value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_Phy_Write(uint16_t phyReg, uint16_t regValue) +{ + uint32_t tmpVal; + + /* Set Register Address */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg); + BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal); + + /* Set Write data */ + BL_WR_REG(EMAC_BASE, EMAC_MIITX_DATA, regValue); + + /* Trigger write */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIICOMMAND); + tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_WCTRLDATA); + BL_WR_REG(EMAC_BASE, EMAC_MIICOMMAND, tmpVal); + + BL_DRV_DUMMY; + + do { + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIISTATUS); + } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY)); + + return SUCCESS; +} + +/*@} end of group EMAC_Private_Functions */ + +/** @defgroup EMAC_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Initialize EMAC module + * + * @param cfg: EMAC configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_Init(EMAC_CFG_Type *cfg) +{ + uint32_t tmpVal; + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC); + + /* Set MAC config */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RMII_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RECSMALL, cfg->recvSmallFrame); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PAD, cfg->padEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_HUGEN, cfg->recvHugeFrame); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CRCEN, cfg->crcEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_NOPRE, cfg->noPreamble); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_BRO, cfg->recvBroadCast); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PRO, ENABLE); + //tmpVal |= (1 << 7); /* local loopback in emac */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_IFG, cfg->interFrameGapCheck); + BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal); + + /* Set inter frame gap value */ + BL_WR_REG(EMAC_BASE, EMAC_IPGT, cfg->interFrameGapValue); + + /* Set MII interface */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIMODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MIINOPRE, cfg->miiNoPreamble); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CLKDIV, cfg->miiClkDiv); + BL_WR_REG(EMAC_BASE, EMAC_MIIMODE, tmpVal); + + /* Set collision */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_COLLCONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXRET, cfg->maxTxRetry); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_COLLVALID, cfg->collisionValid); + BL_WR_REG(EMAC_BASE, EMAC_COLLCONFIG, tmpVal); + + /* Set frame length */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_PACKETLEN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MINFL, cfg->minFrameLen); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXFL, cfg->maxFrameLen); + BL_WR_REG(EMAC_BASE, EMAC_PACKETLEN, tmpVal); + + EMAC_SetMACAddress(cfg->macAddr); + + void EMAC_IRQHandler(void); + Interrupt_Handler_Register(EMAC_IRQn, EMAC_IRQHandler); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief DeInitialize EMAC module + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_DeInit(void) +{ + EMAC_Disable(); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Initialize EMAC TX RX MDA buffer + * + * @param handle: EMAC handle pointer + * @param txBuff: TX buffer + * @param txBuffCount: TX buffer count + * @param rxBuff: RX buffer + * @param rxBuffCount: RX buffer count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_DMADescListInit(EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, uint8_t *rxBuff, uint32_t rxBuffCount) +{ + uint32_t i = 0; + + /* Set the Ethernet handler env */ + handle->bd = (EMAC_BD_Desc_Type *)(EMAC_BASE + EMAC_DMA_DESC_OFFSET); + handle->txIndexEMAC = 0; + handle->txIndexCPU = 0; + handle->txBuffLimit = txBuffCount - 1; + /* The receive descriptors' address starts right after the last transmit BD. */ + handle->rxIndexEMAC = txBuffCount; + handle->rxIndexCPU = txBuffCount; + handle->rxBuffLimit = txBuffCount + rxBuffCount - 1; + + /* Fill each DMARxDesc descriptor with the right values */ + for (i = 0; i < txBuffCount; i++) { + /* Get the pointer on the ith member of the Tx Desc list */ + handle->bd[i].Buffer = (NULL == txBuff) ? 0 : (uint32_t)(txBuff + (ETH_MAX_PACKET_SIZE * i)); + handle->bd[i].C_S_L = 0; + } + + /* For the last TX DMA Descriptor, it should be wrap back */ + handle->bd[handle->txBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(TX_WR); + + for (i = txBuffCount; i < (txBuffCount + rxBuffCount); i++) { + /* Get the pointer on the ith member of the Rx Desc list */ + handle->bd[i].Buffer = (NULL == rxBuff) ? 0 : (uint32_t)(rxBuff + (ETH_MAX_PACKET_SIZE * (i - txBuffCount))); + handle->bd[i].C_S_L = (ETH_MAX_PACKET_SIZE << 16) | + EMAC_BD_FIELD_MSK(RX_IRQ) | + EMAC_BD_FIELD_MSK(RX_E); + } + + /* For the last RX DMA Descriptor, it should be wrap back */ + handle->bd[handle->rxBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(RX_WR); + + /* For the TX DMA Descriptor, it will wrap to 0 according to EMAC_TX_BD_NUM*/ + BL_WR_REG(EMAC_BASE, EMAC_TX_BD_NUM, txBuffCount); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get TX MDA buffer descripter for data to send + * + * @param handle: EMAC handle pointer + * @param txDMADesc: TX DMA descriptor pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc) +{ + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Start TX + * + * @param handle: EMAC handle pointer + * @param txDMADesc: TX DMA descriptor pointer + * @param len: len + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len) +{ + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable EMAC module + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_Enable(void) +{ + uint32_t tmpVal; + + /* Enable EMAC */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN); + tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RXEN); + BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief EMAC_Enable_TX + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_Enable_TX(void) +{ + uint32_t tmpVal; + + /* Enable EMAC */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN); + BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief EMAC_Disable_TX + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_Disable_TX(void) +{ + uint32_t tmpVal; + + /* Enable EMAC */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN); + BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable EMAC module + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_Disable(void) +{ + uint32_t tmpVal; + + /* Enable EMAC */ + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN); + tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_RXEN); + BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief EMAC mask or unmask certain or all interrupt + * + * @param intType: EMAC interrupt type + * @param intMask: EMAC interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_IntMask(EMAC_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_MASK); + + /* Mask or unmask certain or all interrupt */ + if (MASK == intMask) { + tmpVal |= intType; + } else { + tmpVal &= (~intType); + } + + /* Write back */ + BL_WR_REG(EMAC_BASE, EMAC_INT_MASK, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get EMAC interrupt status + * + * @param intType: EMAC interrupt type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Sts_Type EMAC_GetIntStatus(EMAC_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_EMAC_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_SOURCE); + + return (tmpVal & intType) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief Clear EMAC interrupt + * + * @param intType: EMAC interrupt type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_ClrIntStatus(EMAC_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_EMAC_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_SOURCE); + + BL_WR_REG(EMAC_BASE, EMAC_INT_SOURCE, tmpVal | intType); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief EMAC_Int_Callback_Install + * + * @param intIdx: EMAC_INT_Index + * @param cbFun: call back + * + * @return None + * +*******************************************************************************/ +BL_Err_Type EMAC_Int_Callback_Install(EMAC_INT_Index intIdx, intCallback_Type *cbFun) +{ + /* Check the parameters */ + + emacIntCbfArra[intIdx] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief EMAC_IRQHandler + * + * @param None + * + * @return None + * +*******************************************************************************/ +void EMAC_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_MASK); + + if (SET == EMAC_GetIntStatus(EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXB_M)) { + EMAC_ClrIntStatus(EMAC_INT_TX_DONE); + + if (emacIntCbfArra[EMAC_INT_TX_DONE_IDX]) { + emacIntCbfArra[EMAC_INT_TX_DONE_IDX](); + } + } + + if (SET == EMAC_GetIntStatus(EMAC_INT_TX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXE_M)) { + EMAC_ClrIntStatus(EMAC_INT_TX_ERROR); + + if (emacIntCbfArra[EMAC_INT_TX_ERROR_IDX]) { + emacIntCbfArra[EMAC_INT_TX_ERROR_IDX](); + } + } + + if (SET == EMAC_GetIntStatus(EMAC_INT_RX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXB_M)) { + EMAC_ClrIntStatus(EMAC_INT_RX_DONE); + + if (emacIntCbfArra[EMAC_INT_RX_DONE_IDX]) { + emacIntCbfArra[EMAC_INT_RX_DONE_IDX](); + } + } + + if (SET == EMAC_GetIntStatus(EMAC_INT_RX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXE_M)) { + EMAC_ClrIntStatus(EMAC_INT_RX_ERROR); + + if (emacIntCbfArra[EMAC_INT_RX_ERROR_IDX]) { + emacIntCbfArra[EMAC_INT_RX_ERROR_IDX](); + } + } + + if (SET == EMAC_GetIntStatus(EMAC_INT_RX_BUSY) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_BUSY_M)) { + EMAC_ClrIntStatus(EMAC_INT_RX_BUSY); + + if (emacIntCbfArra[EMAC_INT_RX_BUSY_IDX]) { + emacIntCbfArra[EMAC_INT_RX_BUSY_IDX](); + } + } + + if (SET == EMAC_GetIntStatus(EMAC_INT_TX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXC_M)) { + EMAC_ClrIntStatus(EMAC_INT_TX_CTRL); + + if (emacIntCbfArra[EMAC_INT_TX_CTRL_IDX]) { + emacIntCbfArra[EMAC_INT_TX_CTRL_IDX](); + } + } + + if (SET == EMAC_GetIntStatus(EMAC_INT_RX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXC_M)) { + EMAC_ClrIntStatus(EMAC_INT_RX_CTRL); + + if (emacIntCbfArra[EMAC_INT_RX_CTRL_IDX]) { + emacIntCbfArra[EMAC_INT_RX_CTRL_IDX](); + } + } +} + +/****************************************************************************/ /** + * @brief Request to pause TX + * + * @param timeCount: Pause time count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_TxPauseReq(uint16_t timeCount) +{ + BL_WR_REG(EMAC_BASE, EMAC_TXCTRL, (1 << 16) | timeCount); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set hash value + * + * @param hash0: Hash value one + * @param hash1: Hash value two + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EMAC_SetHash(uint32_t hash0, uint32_t hash1) +{ + BL_WR_REG(EMAC_BASE, EMAC_HASH0_ADDR, hash0); + + BL_WR_REG(EMAC_BASE, EMAC_HASH1_ADDR, hash1); + + return SUCCESS; +} + +/*@} end of group EMAC_Public_Functions */ + +/*@} end of group EMAC */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_glb.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_glb.c new file mode 100644 index 0000000000000000000000000000000000000000..805533e27061f423461ae1c0137cee16e82be84d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_glb.c @@ -0,0 +1,4034 @@ +/** + ****************************************************************************** + * @file bl702_glb.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_glb.h" +#include "bl702_hbn.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Private_Macros + * @{ + */ +#define GLB_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } +#define GLB_GPIO_Get_Reg(pin) (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4) +#define GLB_GPIO_INT0_NUM (32) +#define GLB_REG_BCLK_DIS_TRUE (*(volatile uint32_t *)(0x40000FFC) = (0x00000001)) +#define GLB_REG_BCLK_DIS_FALSE (*(volatile uint32_t *)(0x40000FFC) = (0x00000000)) +#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) + +/*@} end of group GLB_Private_Macros */ + +/** @defgroup GLB_Private_Types + * @{ + */ + +/*@} end of group GLB_Private_Types */ + +/** @defgroup GLB_Private_Variables + * @{ + */ +static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL] = { NULL }; +static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL }; +static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; +static intCallback_Type *glbGpioInt0CbfArra2[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + +/*@} end of group GLB_Private_Variables */ + +/** @defgroup GLB_Global_Variables + * @{ + */ + +/*@} end of group GLB_Global_Variables */ + +/** @defgroup GLB_Private_Fun_Declaration + * @{ + */ + +/*@} end of group GLB_Private_Fun_Declaration */ + +/** @defgroup GLB_Private_Functions + * @{ + */ + +/*@} end of group GLB_Private_Functions */ + +/** @defgroup GLB_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief get root clock selection + * + * @param None + * + * @return root clock selection + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) { + case 0: + return GLB_ROOT_CLK_RC32M; + case 1: + return GLB_ROOT_CLK_XTAL; + case 2: + case 3: + return GLB_ROOT_CLK_DLL; + default: + return GLB_ROOT_CLK_RC32M; + } +} +#endif + +/****************************************************************************/ /** + * @brief Set System clock divider + * + * @param hclkDiv: HCLK divider + * @param bclkDiv: BCLK divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* recommend: fclk<=160MHz, bclk<=80MHz */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + //SystemCoreClockSet(SystemCoreClockGet() / ((uint16_t)hclkDiv + 1)); + GLB_CLK_SET_DUMMY_WAIT; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get Bus clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); +} +#endif + +/****************************************************************************/ /** + * @brief Get CPU clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); +} +#endif + +/****************************************************************************/ /** + * @brief update SystemCoreClock value + * + * @param xtalType: XTAL frequency type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType) +{ + CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType)); + + switch (xtalType) { + case GLB_DLL_XTAL_NONE: + break; + case GLB_DLL_XTAL_32M: + SystemCoreClockSet(32000000); + break; + case GLB_DLL_XTAL_RC32M: + SystemCoreClockSet(32000000); + break; + default: + break; + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set System clock + * + * @param xtalType: XTAL frequency type + * @param clkFreq: clock frequency selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType)); + CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq)); + + /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + + /* Before config XTAL and DLL ,make sure root clk is from RC32M */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + GLB_Set_System_CLK_Div(0, 0); + SystemCoreClockSet(32 * 1000 * 1000); + + if (xtalType == GLB_DLL_XTAL_NONE) { + if (clkFreq == GLB_SYS_CLK_RC32M) { + return SUCCESS; + } else { + return ERROR; + } + } + + if (xtalType != GLB_DLL_XTAL_RC32M) { + /* power on xtal first */ + AON_Power_On_XTAL(); + } + + /* Bl702 make PLL Setting out of RF, so following setting can be removed*/ + //AON_Power_On_MBG(); + //AON_Power_On_LDO15_RF(); + + /* always power up PLL and enable all PLL clock output */ + //PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType); + //BL702_Delay_US(55); + //PDS_Enable_PLL_All_Clks(); + + /* always power up DLL and enable all DLL clock output */ + GLB_Power_Off_DLL(); + GLB_Power_On_DLL(xtalType); + GLB_Enable_DLL_All_Clks(); + + /* reg_pll_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + + /* select pll output clock before select root clock */ + if (clkFreq >= GLB_SYS_CLK_DLL57P6M) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_DLL57P6M); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + } + /* select root clock */ + switch (clkFreq) { + case GLB_SYS_CLK_RC32M: + break; + case GLB_SYS_CLK_XTAL: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + Update_SystemCoreClockWith_XTAL(xtalType); + break; + case GLB_SYS_CLK_DLL57P6M: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL); + SystemCoreClockSet(57 * 6000 * 1000); + break; + case GLB_SYS_CLK_DLL96M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL); + SystemCoreClockSet(96 * 1000 * 1000); + break; + case GLB_SYS_CLK_DLL144M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL); + SystemCoreClockSet(144 * 1000 * 1000); + break; + default: + break; + } + + GLB_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief This is demo for user that use RC32M as default bootup clock instead of DLL,when APP is + * started, this function can be called to set DLL to 160M + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void) +{ + SF_Ctrl_Cfg_Type sfCtrlCfg = { + .owner = SF_CTRL_OWNER_IAHB, + .clkDelay = 1, + .clkInvert = 1, + .rxClkInvert = 1, + .doDelay = 0, + .diDelay = 0, + .oeDelay = 0, + }; + /* Use RC32M as DLL ref source to set up DLL to 144M */ + GLB_Set_System_CLK(GLB_DLL_XTAL_RC32M, GLB_SYS_CLK_DLL144M); + /* Flash controller also need changes since system (bus) clock changed */ + SF_Ctrl_Enable(&sfCtrlCfg); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set CAM clock + * + * @param enable: Enable or disable CAM clock + * @param clkSel: CAM clock type + * @param div: clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set mac154 and zigbee clock + * + * @param enable: Enable or disable mac154 and zigbee clock + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_M154_ZBEN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_M154_ZBEN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set BLE clock + * + * @param enable: Enable or disable BLE clock + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set I2S clock + * + * @param enable: Enable or disable I2S clock + * @param outRef: I2S output ref clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_I2S_OUT_REF_CLK_TYPE(outRef)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_0_REF_CLK_OE, outRef); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S0_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S0_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set USB clock + * + * @param enable: Enable or disable USB clock + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_USB_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_48M_DIV_EN, 1); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USB_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USB_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set QDEC clock + * + * @param clkSel: QDEC clock type + * @param div: clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_QDEC_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_SEL, clkSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DMA clock + * + * @param enable: Enable or disable DMA clock + * @param clk: DMA ID type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); + if (enable) { + tmpVal2 |= (1 << clk); + } else { + tmpVal2 &= (~(1 << clk)); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set IR clock divider + * + * @param enable: enable or disable IR clock + * @param clkSel: IR clock type + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel)); + CHECK_PARAM((div <= 0x3F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set sflash clock + * + * @param enable: Enable or disable sflash clock + * @param clkSel: sflash clock type + * @param div: clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + GLB_DLL_CLK_Type clk; + + CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel)); + CHECK_PARAM((div <= 0x7)); + + /* disable SFLASH clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Select flash clock, all Flash CLKs are divied by DLL_288M */ + clk = GLB_DLL_CLK_288M; + GLB_Enable_DLL_Clk(clk); + /* clock divider */ + /* Select flash clock, all Flash CLKs are divied by DLL_288M */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div); + switch (clkSel) { + case GLB_SFLASH_CLK_144M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0); + break; + case GLB_SFLASH_CLK_XCLK: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1); + break; + case GLB_SFLASH_CLK_57P6M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3); + break; + case GLB_SFLASH_CLK_72M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1); + break; + case GLB_SFLASH_CLK_BCLK: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2); + break; + case GLB_SFLASH_CLK_96M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3); + break; + default: + break; + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* enable or disable flash clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set UART clock + * + * @param enable: Enable or disable UART clock + * @param clkSel: UART clock type + * @param div: clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((div <= 0x7)); + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + /* disable UART clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Set div */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Select clock source for uart */ + HBN_Set_UART_CLK_Sel(clkSel); + + /* Set enable or disable */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select chip clock out 0 type + * + * @param clkSel: chip clock out type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select chip clock out 1 type + * + * @param clkSel: chip clock out type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set I2C clock + * + * @param enable: Enable or disable I2C clock + * @param div: clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief invert eth rx clock + * + * @param enable: invert or not invert + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief invert rf test clock out + * + * @param enable: invert or not invert + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_RF_TEST_CLK_O); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_RF_TEST_CLK_O); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set SPI clock + * + * @param enable: Enable or disable SPI clock + * @param div: clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((div <= 0x1F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief invert eth tx clock + * + * @param enable: invert or not invert + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief invert eth ref clock out + * + * @param enable: invert or not invert + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select eth ref clock out + * + * @param clkSel: eth ref clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select PKA clock source + * + * @param clkSel: PKA clock selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Software system reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL702_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software CPU reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL702_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software power on reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL702_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Reset slave 1 + * + * @param slave1: slave num + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal &= (~(1 << slave1)); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal |= (1 << slave1); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal &= (~(1 << slave1)); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief clock gate + * + * @param enable: ENABLE or DISABLE + * @param slave1: AHB slaveClk type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1) +{ + /* gate QDEC <=> gate QDEC0 + QDEC1 +QDEC2 + I2S */ + /* gate I2S <=> gate I2S + QDEC2 */ + + uint32_t tmpVal = 0; + + if ((BL_AHB_SLAVE1_GLB == slave1) || (BL_AHB_SLAVE1_TZ2 == slave1) || + (BL_AHB_SLAVE1_CCI == slave1) || (BL_AHB_SLAVE1_L1C == slave1) || + (BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM == slave1)) { + /* not support */ + return ERROR; + } + + /* gate QDEC and I2S */ + if (BL_AHB_SLAVE1_QDEC == slave1) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + if (enable) { + /* clear bit means clock gate */ + tmpVal &= (~(1 << 0x18)); + tmpVal &= (~(1 << 0x19)); + tmpVal &= (~(1 << 0x1A)); + } else { + /* set bit means clock pass */ + tmpVal |= (1 << 0x18); + tmpVal |= (1 << 0x19); + tmpVal |= (1 << 0x1A); + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); + return SUCCESS; + } + + /* gate KYS */ + if (BL_AHB_SLAVE1_KYS == slave1) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + if (enable) { + /* clear bit means clock gate */ + tmpVal &= (~(1 << 0x1B)); + } else { + /* set bit means clock pass */ + tmpVal |= (1 << 0x1B); + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); + return SUCCESS; + } + + /* gate I2S and QDEC2 */ + if (BL_AHB_SLAVE1_I2S == slave1) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + if (enable) { + /* clear bit means clock gate */ + tmpVal &= (~(1 << 0x1A)); + } else { + /* set bit means clock pass */ + tmpVal |= (1 << 0x1A); + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); + return SUCCESS; + } + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + if (enable) { + /* clear bit means clock gate */ + tmpVal &= (~(1 << slave1)); + } else { + /* set bit means clock pass */ + tmpVal |= (1 << slave1); + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get IPs clock gate value + * + * @param None + * + * @return clock gate value + * +*******************************************************************************/ +uint64_t GLB_PER_Clock_Gate_Status_Get(void) +{ + /* api request from cjy */ + + uint32_t tmpValCfg0 = 0; + uint32_t tmpValCfg1 = 0; + uint32_t tmpValCfg2 = 0; + uint32_t targetBit = 0; + uint64_t targetVal = 0; + + tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); + tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); + for (uint8_t i = 0; i < 64; i++) { + targetBit = 0; + switch (i) { + case GLB_AHB_CLOCK_IP_CPU: + targetBit = tmpValCfg0 & (1 << 0); + break; + case GLB_AHB_CLOCK_IP_SDU: + targetBit = tmpValCfg0 & (1 << 1); + break; + case GLB_AHB_CLOCK_IP_SEC: + targetBit = (tmpValCfg0 & (1 << 2)) && (tmpValCfg1 & (1 << 3)) && (tmpValCfg1 & (1 << 4)); + break; + case GLB_AHB_CLOCK_IP_DMA_0: + targetBit = (tmpValCfg0 & (1 << 3)) && (tmpValCfg1 & (1 << 12)); + break; + case GLB_AHB_CLOCK_IP_DMA_1: + break; + case GLB_AHB_CLOCK_IP_DMA_2: + break; + case GLB_AHB_CLOCK_IP_CCI: + targetBit = tmpValCfg0 & (1 << 4); + break; + case GLB_AHB_CLOCK_IP_RF_TOP: + break; + case GLB_AHB_CLOCK_IP_GPIP: + targetBit = tmpValCfg1 & (1 << 2); + break; + case GLB_AHB_CLOCK_IP_TZC: + targetBit = tmpValCfg1 & (1 << 5); + break; + case GLB_AHB_CLOCK_IP_EF_CTRL: + targetBit = tmpValCfg1 & (1 << 7); + break; + case GLB_AHB_CLOCK_IP_SF_CTRL: + targetBit = tmpValCfg1 & (1 << 11); + break; + case GLB_AHB_CLOCK_IP_EMAC: + targetBit = tmpValCfg1 & (1 << 13); + break; + case GLB_AHB_CLOCK_IP_UART0: + targetBit = tmpValCfg1 & (1 << 16); + break; + case GLB_AHB_CLOCK_IP_UART1: + targetBit = tmpValCfg1 & (1 << 17); + break; + case GLB_AHB_CLOCK_IP_UART2: + break; + case GLB_AHB_CLOCK_IP_UART3: + break; + case GLB_AHB_CLOCK_IP_UART4: + break; + case GLB_AHB_CLOCK_IP_SPI: + targetBit = tmpValCfg1 & (1 << 18); + break; + case GLB_AHB_CLOCK_IP_I2C: + targetBit = tmpValCfg1 & (1 << 19); + break; + case GLB_AHB_CLOCK_IP_PWM: + targetBit = tmpValCfg1 & (1 << 20); + break; + case GLB_AHB_CLOCK_IP_TIMER: + targetBit = tmpValCfg1 & (1 << 21); + break; + case GLB_AHB_CLOCK_IP_IR: + targetBit = tmpValCfg1 & (1 << 22); + break; + case GLB_AHB_CLOCK_IP_CHECKSUM: + targetBit = tmpValCfg1 & (1 << 23); + break; + case GLB_AHB_CLOCK_IP_QDEC: + targetBit = (tmpValCfg1 & (1 << 24)) && (tmpValCfg1 & (1 << 25)) && (tmpValCfg1 & (1 << 26)); + break; + case GLB_AHB_CLOCK_IP_KYS: + targetBit = tmpValCfg1 & (1 << 27); + break; + case GLB_AHB_CLOCK_IP_I2S: + targetBit = tmpValCfg1 & (1 << 26); + break; + case GLB_AHB_CLOCK_IP_USB11: + targetBit = tmpValCfg1 & (1 << 28); + break; + case GLB_AHB_CLOCK_IP_CAM: + targetBit = tmpValCfg1 & (1 << 29); + break; + case GLB_AHB_CLOCK_IP_MJPEG: + targetBit = tmpValCfg1 & (1 << 30); + break; + case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: + targetBit = (tmpValCfg2 & (1 << 0)) && (tmpValCfg2 & (1 << 4)); + break; + case GLB_AHB_CLOCK_IP_BT_BLE_LP: + break; + case GLB_AHB_CLOCK_IP_ZB_NORMAL: + targetBit = tmpValCfg2 & (1 << 0); + break; + case GLB_AHB_CLOCK_IP_ZB_LP: + break; + case GLB_AHB_CLOCK_IP_WIFI_NORMAL: + break; + case GLB_AHB_CLOCK_IP_WIFI_LP: + break; + case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL: + break; + case GLB_AHB_CLOCK_IP_BT_BLE_2_LP: + break; + case GLB_AHB_CLOCK_IP_EMI_MISC: + break; + case GLB_AHB_CLOCK_IP_PSRAM0_CTRL: + break; + case GLB_AHB_CLOCK_IP_PSRAM1_CTRL: + break; + case GLB_AHB_CLOCK_IP_USB20: + break; + case GLB_AHB_CLOCK_IP_MIX2: + break; + case GLB_AHB_CLOCK_IP_AUDIO: + break; + case GLB_AHB_CLOCK_IP_SDH: + break; + default: + break; + } + if (!targetBit) { + targetVal |= ((uint64_t)1 << i); + } + } + + return targetVal; +} + +/****************************************************************************/ /** + * @brief get first 1 from u64, then clear it + * + * @param val: target value + * @param bit: first 1 in bit + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit) +{ + if (!*val) { + return ERROR; + } + + for (uint8_t i = 0; i < 64; i++) { + if ((*val) & ((uint64_t)1 << i)) { + *bit = i; + (*val) &= ~((uint64_t)1 << i); + break; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief hold IPs clock + * + * @param ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ...... + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips) +{ + /* api request from cjy */ + + uint32_t tmpValCfg0 = 0; + uint32_t tmpValCfg1 = 0; + uint32_t tmpValCfg2 = 0; + uint32_t bitfield = 0; + + tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); + tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); + while (ips) { + if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) { + switch (bitfield) { + case GLB_AHB_CLOCK_IP_CPU: + tmpValCfg0 &= ~(1 << 0); + break; + case GLB_AHB_CLOCK_IP_SDU: + tmpValCfg0 &= ~(1 << 1); + break; + case GLB_AHB_CLOCK_IP_SEC: + tmpValCfg0 &= ~(1 << 2); + tmpValCfg1 &= ~(1 << 3); + tmpValCfg1 &= ~(1 << 4); + break; + case GLB_AHB_CLOCK_IP_DMA_0: + tmpValCfg0 &= ~(1 << 3); + tmpValCfg1 &= ~(1 << 12); + break; + case GLB_AHB_CLOCK_IP_DMA_1: + break; + case GLB_AHB_CLOCK_IP_DMA_2: + break; + case GLB_AHB_CLOCK_IP_CCI: + tmpValCfg0 &= ~(1 << 4); + break; + case GLB_AHB_CLOCK_IP_RF_TOP: + break; + case GLB_AHB_CLOCK_IP_GPIP: + tmpValCfg1 &= ~(1 << 2); + break; + case GLB_AHB_CLOCK_IP_TZC: + tmpValCfg1 &= ~(1 << 5); + break; + case GLB_AHB_CLOCK_IP_EF_CTRL: + tmpValCfg1 &= ~(1 << 7); + break; + case GLB_AHB_CLOCK_IP_SF_CTRL: + tmpValCfg1 &= ~(1 << 11); + break; + case GLB_AHB_CLOCK_IP_EMAC: + tmpValCfg1 &= ~(1 << 13); + break; + case GLB_AHB_CLOCK_IP_UART0: + tmpValCfg1 &= ~(1 << 16); + break; + case GLB_AHB_CLOCK_IP_UART1: + tmpValCfg1 &= ~(1 << 17); + break; + case GLB_AHB_CLOCK_IP_UART2: + break; + case GLB_AHB_CLOCK_IP_UART3: + break; + case GLB_AHB_CLOCK_IP_UART4: + break; + case GLB_AHB_CLOCK_IP_SPI: + tmpValCfg1 &= ~(1 << 18); + break; + case GLB_AHB_CLOCK_IP_I2C: + tmpValCfg1 &= ~(1 << 19); + break; + case GLB_AHB_CLOCK_IP_PWM: + tmpValCfg1 &= ~(1 << 20); + break; + case GLB_AHB_CLOCK_IP_TIMER: + tmpValCfg1 &= ~(1 << 21); + break; + case GLB_AHB_CLOCK_IP_IR: + tmpValCfg1 &= ~(1 << 22); + break; + case GLB_AHB_CLOCK_IP_CHECKSUM: + tmpValCfg1 &= ~(1 << 23); + break; + case GLB_AHB_CLOCK_IP_QDEC: + tmpValCfg1 &= ~(1 << 24); + tmpValCfg1 &= ~(1 << 25); + tmpValCfg1 &= ~(1 << 26); + break; + case GLB_AHB_CLOCK_IP_KYS: + tmpValCfg1 &= ~(1 << 27); + break; + case GLB_AHB_CLOCK_IP_I2S: + tmpValCfg1 &= ~(1 << 26); + break; + case GLB_AHB_CLOCK_IP_USB11: + tmpValCfg1 &= ~(1 << 28); + break; + case GLB_AHB_CLOCK_IP_CAM: + tmpValCfg1 &= ~(1 << 29); + break; + case GLB_AHB_CLOCK_IP_MJPEG: + tmpValCfg1 &= ~(1 << 30); + break; + case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: + tmpValCfg2 &= ~(1 << 0); + tmpValCfg2 &= ~(1 << 4); + break; + case GLB_AHB_CLOCK_IP_BT_BLE_LP: + break; + case GLB_AHB_CLOCK_IP_ZB_NORMAL: + tmpValCfg2 &= ~(1 << 0); + break; + case GLB_AHB_CLOCK_IP_ZB_LP: + break; + case GLB_AHB_CLOCK_IP_WIFI_NORMAL: + break; + case GLB_AHB_CLOCK_IP_WIFI_LP: + break; + case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL: + break; + case GLB_AHB_CLOCK_IP_BT_BLE_2_LP: + break; + case GLB_AHB_CLOCK_IP_EMI_MISC: + break; + case GLB_AHB_CLOCK_IP_PSRAM0_CTRL: + break; + case GLB_AHB_CLOCK_IP_PSRAM1_CTRL: + break; + case GLB_AHB_CLOCK_IP_USB20: + break; + case GLB_AHB_CLOCK_IP_MIX2: + break; + case GLB_AHB_CLOCK_IP_AUDIO: + break; + case GLB_AHB_CLOCK_IP_SDH: + break; + default: + break; + } + } + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief release IPs clock + * + * @param ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ...... + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips) +{ + /* api request from cjy */ + + uint32_t tmpValCfg0 = 0; + uint32_t tmpValCfg1 = 0; + uint32_t tmpValCfg2 = 0; + uint32_t bitfield = 0; + + tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); + tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); + while (ips) { + if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) { + switch (bitfield) { + case GLB_AHB_CLOCK_IP_CPU: + tmpValCfg0 |= (1 << 0); + break; + case GLB_AHB_CLOCK_IP_SDU: + tmpValCfg0 |= (1 << 1); + break; + case GLB_AHB_CLOCK_IP_SEC: + tmpValCfg0 |= (1 << 2); + tmpValCfg1 |= (1 << 3); + tmpValCfg1 |= (1 << 4); + break; + case GLB_AHB_CLOCK_IP_DMA_0: + tmpValCfg0 |= (1 << 3); + tmpValCfg1 |= (1 << 12); + break; + case GLB_AHB_CLOCK_IP_DMA_1: + break; + case GLB_AHB_CLOCK_IP_DMA_2: + break; + case GLB_AHB_CLOCK_IP_CCI: + tmpValCfg0 |= (1 << 4); + break; + case GLB_AHB_CLOCK_IP_RF_TOP: + break; + case GLB_AHB_CLOCK_IP_GPIP: + tmpValCfg1 |= (1 << 2); + break; + case GLB_AHB_CLOCK_IP_TZC: + tmpValCfg1 |= (1 << 5); + break; + case GLB_AHB_CLOCK_IP_EF_CTRL: + tmpValCfg1 |= (1 << 7); + break; + case GLB_AHB_CLOCK_IP_SF_CTRL: + tmpValCfg1 |= (1 << 11); + break; + case GLB_AHB_CLOCK_IP_EMAC: + tmpValCfg1 |= (1 << 13); + break; + case GLB_AHB_CLOCK_IP_UART0: + tmpValCfg1 |= (1 << 16); + break; + case GLB_AHB_CLOCK_IP_UART1: + tmpValCfg1 |= (1 << 17); + break; + case GLB_AHB_CLOCK_IP_UART2: + break; + case GLB_AHB_CLOCK_IP_UART3: + break; + case GLB_AHB_CLOCK_IP_UART4: + break; + case GLB_AHB_CLOCK_IP_SPI: + tmpValCfg1 |= (1 << 18); + break; + case GLB_AHB_CLOCK_IP_I2C: + tmpValCfg1 |= (1 << 19); + break; + case GLB_AHB_CLOCK_IP_PWM: + tmpValCfg1 |= (1 << 20); + break; + case GLB_AHB_CLOCK_IP_TIMER: + tmpValCfg1 |= (1 << 21); + break; + case GLB_AHB_CLOCK_IP_IR: + tmpValCfg1 |= (1 << 22); + break; + case GLB_AHB_CLOCK_IP_CHECKSUM: + tmpValCfg1 |= (1 << 23); + break; + case GLB_AHB_CLOCK_IP_QDEC: + tmpValCfg1 |= (1 << 24); + tmpValCfg1 |= (1 << 25); + tmpValCfg1 |= (1 << 26); + break; + case GLB_AHB_CLOCK_IP_KYS: + tmpValCfg1 |= (1 << 27); + break; + case GLB_AHB_CLOCK_IP_I2S: + tmpValCfg1 |= (1 << 26); + break; + case GLB_AHB_CLOCK_IP_USB11: + tmpValCfg1 |= (1 << 28); + break; + case GLB_AHB_CLOCK_IP_CAM: + tmpValCfg1 |= (1 << 29); + break; + case GLB_AHB_CLOCK_IP_MJPEG: + tmpValCfg1 |= (1 << 30); + break; + case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: + tmpValCfg2 |= (1 << 0); + tmpValCfg2 |= (1 << 4); + break; + case GLB_AHB_CLOCK_IP_BT_BLE_LP: + break; + case GLB_AHB_CLOCK_IP_ZB_NORMAL: + tmpValCfg2 |= (1 << 0); + break; + case GLB_AHB_CLOCK_IP_ZB_LP: + break; + case GLB_AHB_CLOCK_IP_WIFI_NORMAL: + break; + case GLB_AHB_CLOCK_IP_WIFI_LP: + break; + case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL: + break; + case GLB_AHB_CLOCK_IP_BT_BLE_2_LP: + break; + case GLB_AHB_CLOCK_IP_EMI_MISC: + break; + case GLB_AHB_CLOCK_IP_PSRAM0_CTRL: + break; + case GLB_AHB_CLOCK_IP_PSRAM1_CTRL: + break; + case GLB_AHB_CLOCK_IP_USB20: + break; + case GLB_AHB_CLOCK_IP_MIX2: + break; + case GLB_AHB_CLOCK_IP_AUDIO: + break; + case GLB_AHB_CLOCK_IP_SDH: + break; + default: + break; + } + } + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX init + * + * @param BmxCfg: BMX config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler); + Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get BMX error status + * + * @param errType: BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET; + } +} + +/****************************************************************************/ /** + * @brief Get BMX error address + * + * @param None + * + * @return NP BMX error address + * +*******************************************************************************/ +uint32_t GLB_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR); +} + +/****************************************************************************/ /** + * @brief BMX error interrupt callback install + * + * @param intType: BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType)); + + glbBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void) +{ + BMX_ERR_INT_Type intType; + + for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) { + if (glbBmxErrIntCbfArra[intType] != NULL) { + glbBmxErrIntCbfArra[intType](); + } + } + + while (1) { + MSG("BMX_ERR_IRQHandler\r\n"); + BL702_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief BMX timeout interrupt callback install + * + * @param intType: BMX timeout interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType)); + + glbBmxToIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX Time Out interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_TO_IRQHandler(void) +{ + BMX_TO_INT_Type intType; + + for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) { + if (glbBmxToIntCbfArra[intType] != NULL) { + glbBmxToIntCbfArra[intType](); + } + } + + while (1) { + MSG("BMX_TO_IRQHandler\r\n"); + BL702_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief set sram_ret value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_RET(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_RET, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_ret value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_RET(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_RET); +} + +/****************************************************************************/ /** + * @brief set sram_slp value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_SLP, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_slp value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_SLP(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_SLP); +} + +/****************************************************************************/ /** + * @brief set sram_param value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_parm value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_PARM(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_PARM); +} + +/****************************************************************************/ /** + * @brief select EM type + * + * @param emType: EM type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_EM_TYPE(emType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType); + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select pin as EMAC or CAM + * + * @param pinType: pin type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_EMAC_CAM_PIN_TYPE(pinType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PIN_SEL_EMAC_CAM, pinType); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief EXT_RST PAD SMT + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EXT_RST_SMT); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EXT_RST_SMT); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Key Scan Column Drive + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap UART gpio pins sig function + * + * @param swapSel: UART swap set gpio pins selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((swapSel <= 0xF)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, swapSel); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap JTAG gpio pins function + * + * @param swapSel: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((swapSel <= 0xFF)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief CCI use GPIO 0 1 2 7 + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief CCI use JTAG pin + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap SPI0 MOSI with MISO + * + * @param newState: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select SPI_0 act mode + * + * @param mod: SPI work mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief use internal flash + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f); + BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief use external flash + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00); + BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Deswap internal flash pin + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Swap internal flash CS and IO2 pin + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_CS_IO2_Pin(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Swap internal flash IO3 and IO0 pin + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_IO0_IO3_Pin(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Swap internal flash IO3 and IO0 pin + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void) +{ + /*To be removed*/ + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Select internal psram + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_PSram(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00); + BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set PDM clock + * + * @param enable: Enable or disable PDM clock + * @param div: clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM0_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set MTimer clock + * + * @param enable: enable or disable MTimer clock + * @param clkSel: clock selection + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel)); + CHECK_PARAM((div <= 0x1FFFF)); + + /* disable MTimer clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + } + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set ADC clock + * + * @param enable: enable or disable ADC clock + * @param clkSel: ADC clock selection + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel)); + + /* disable ADC clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + } + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DAC clock + * + * @param enable: enable frequency divider or not + * @param clkSel: ADC clock selection + * @param div: src divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_DAC_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } + + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select DIG clock source + * + * @param clkSel: DIG clock selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel) +{ + uint32_t tmpVal; + uint32_t dig512kEn; + uint32_t dig32kEn; + + /* disable DIG512K and DIG32K clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); + dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + /* repristinate DIG512K and DIG32K clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DIG 512K clock + * + * @param enable: enable or disable DIG 512K clock + * @param compensation: enable or disable DIG 512K clock compensation + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + if (compensation) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DIG 32K clock + * + * @param enable: enable or disable DIG 32K clock + * @param compensation: enable or disable DIG 32K clock compensation + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint8_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + if (compensation) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); + } + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set BT coex signal + * + * @param enable: ENABLE or DISABLE, if enable, the AP JTAG will be replaced by BT Coex Signal + * @param bandWidth: BT Bandwidth + * @param pti: BT Packet Traffic Information + * @param channel: BT Channel + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, uint8_t pti, uint8_t channel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_BT_BANDWIDTH_TYPE(bandWidth)); + CHECK_PARAM((pti <= 0xF)); + CHECK_PARAM((channel <= 78)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_BW, bandWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_PTI, pti); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_CHANNEL, channel); + BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL); + if (enable) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 0); + } + BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select UART signal function + * + * @param sig: UART signal + * @param fun: UART function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun) +{ + uint32_t sig_pos = 0; + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig)); + CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0); + sig_pos = (sig * 4); + /* Clear original val */ + tmpVal &= (~(0xf << sig_pos)); + /* Set new value */ + tmpVal |= (fun << sig_pos); + BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power off DLL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_DLL(void) +{ + uint32_t tmpVal = 0; + + /* GLB->dll.BF.ppu_dll = 0; */ + /* GLB->dll.BF.pu_dll = 0; */ + /* GLB->dll.BF.dll_reset = 1; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief power on DLL + * + * @param xtalType: DLL xtal type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType)); + + /* GLB->dll.BF.dll_refclk_sel = XXX; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + switch (xtalType) { + case GLB_DLL_XTAL_NONE: + return ERROR; + case GLB_DLL_XTAL_32M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 0); + break; + case GLB_DLL_XTAL_RC32M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 1); + break; + default: + break; + } + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + /* GLB->dll.BF.dll_prechg_sel = 1; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_PRECHG_SEL, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + /* GLB->dll.BF.ppu_dll = 1; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + BL702_Delay_US(2); + + /* GLB->dll.BF.pu_dll = 1; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + BL702_Delay_US(2); + + /* GLB->dll.BF.dll_reset = 0; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 0); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + /* delay for settling */ + BL702_Delay_US(5); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief enable all DLL output clock + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_All_Clks(void) +{ + uint32_t tmpVal = 0; + + /* GLB->dll.WORD = GLB->dll.WORD | 0x000000f8; include 288m and mmdiv */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief enable one of DLL output clock + * + * @param dllClk: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + switch (dllClk) { + case GLB_DLL_CLK_57P6M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 1); + break; + case GLB_DLL_CLK_96M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 1); + break; + case GLB_DLL_CLK_144M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 1); + break; + case GLB_DLL_CLK_288M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 1); + break; + case GLB_DLL_CLK_MMDIV: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 1); + break; + default: + break; + } + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief disable all DLL output clock + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_All_Clks(void) +{ + uint32_t tmpVal = 0; + + /* GLB->dll.WORD = GLB->dll.WORD & ~0x000000f8; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 0); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief disable one of DLL output clock + * + * @param dllClk: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + switch (dllClk) { + case GLB_DLL_CLK_57P6M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 0); + break; + case GLB_DLL_CLK_96M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 0); + break; + case GLB_DLL_CLK_144M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 0); + break; + case GLB_DLL_CLK_288M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 0); + break; + case GLB_DLL_CLK_MMDIV: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 0); + break; + default: + break; + } + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Select ir rx gpio (gpio17~gpio31) + * + * @param gpio: IR gpio selected + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio) +{ + uint32_t tmpVal = 0; + + /* Select gpio between gpio17 and gpio31 */ + if (gpio > 16 && gpio < 32) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 16); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Enable(void) +{ + uint32_t tmpVal = 0; + + /* Enable led driver */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Disable(void) +{ + uint32_t tmpVal = 0; + + /* Disable led driver */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable ir led driver gpio output(gpio 22 or 23) + * + * @param gpio: IR gpio selected + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio) +{ + uint32_t tmpVal = 0; + + if (gpio == GLB_GPIO_PIN_22) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 1); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } else if (gpio == GLB_GPIO_PIN_23) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 2); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable ir led driver gpio output(gpio 22 or 23) + * + * @param gpio: IR gpio selected + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio) +{ + uint32_t tmpVal = 0; + + if (gpio == GLB_GPIO_PIN_22) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~1); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } else if (gpio == GLB_GPIO_PIN_23) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~2); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set ir led driver ibias + * + * @param ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias) +{ + uint32_t tmpVal = 0; + + /* Set driver ibias */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0xF); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO initialization + * + * @param cfg: GPIO configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) +{ + uint8_t gpioPin = cfg->gpioPin; + uint8_t realPin; + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + + /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */ + /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */ + /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */ + /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */ + + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + + realPin = gpioPin; + /* sf pad use exclusive ie/pd/pu/drive/smtctrl */ + if (gpioPin >= 23 && gpioPin <= 28) { + if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) { + realPin += 9; + } + } + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4); + if (realPin % 2 == 0) { + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + /* Set input or output */ + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + tmpOut |= (1 << pos); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } + + /* Set pull up or down */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + if (cfg->pullType == GPIO_PULL_UP) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + } else if (cfg->pullType == GPIO_PULL_DOWN) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + } + } else { + /* analog mode */ + + /* clear ie && oe */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + tmpOut &= ~(1 << pos); + + /* clear pu && pd */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + } + + /* set drive && smt && func */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun); + } else { + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + /* Set input or output */ + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + tmpOut |= (1 << pos); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + + /* Set pull up or down */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + if (cfg->pullType == GPIO_PULL_UP) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + } else if (cfg->pullType == GPIO_PULL_DOWN) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + } + } else { + /* analog mode */ + + /* clear ie && oe */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + tmpOut &= ~(1 << pos); + + /* clear pu && pd */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + } + + /* set drive && smt && func */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun); + } + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal); + + *pOut = tmpOut; + + /* always on pads IE control (in HBN) */ + if (gpioPin >= 9 && gpioPin <= 13) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + uint32_t aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT); + + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + aonPadIeSmt &= ~(1 << (gpioPin - 9)); + } else { + aonPadIeSmt |= (1 << (gpioPin - 9)); + } + } else { + /* analog mode */ + + /* clear aon pad ie */ + aonPadIeSmt &= ~(1 << (gpioPin - 9)); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + } + + if (gpioPin >= 23 && gpioPin <= 28) { + if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) { + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + if (gpioPin % 2 == 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun); + } + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + /* sf pad use GPIO23-GPIO28 pinmux&&outputEn */ + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpOut |= (1 << pos); + } + } + *pOut = tmpOut; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief init GPIO function in pin list + * + * @param gpioFun: GPIO pin function + * @param pinList: GPIO pin list + * @param cnt: GPIO pin count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = (uint8_t)gpioFun, + .gpioMode = GPIO_MODE_AF, + .pullType = GPIO_PULL_UP, + .drive = 1, + .smtCtrl = 1 + }; + + if (gpioFun == GPIO_FUN_ANALOG) { + gpioCfg.gpioMode = GPIO_MODE_ANALOG; + } + + for (uint8_t i = 0; i < cnt; i++) { + gpioCfg.gpioPin = pinList[i]; + GLB_GPIO_Init(&gpioCfg); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set input function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + uint32_t aonPadIeSmt; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + if (gpioPin % 2 == 0) { + /* [0] is ie */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } else { + /* [16] is ie */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + /* always on pads IE control (in HBN) */ + if (gpioPin >= 9 && gpioPin <= 13) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT); + aonPadIeSmt |= (1 << (gpioPin - 9)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set input function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + uint32_t aonPadIeSmt; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + if (gpioPin % 2 == 0) { + /* [0] is ie */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } else { + /* [16] is ie */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + /* always on pads IE control (in HBN) */ + if (gpioPin >= 9 && gpioPin <= 13) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT); + aonPadIeSmt &= ~(1 << (gpioPin - 9)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set output function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34); + tmpVal = tmpVal | (1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set output function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34); + tmpVal = tmpVal & ~(1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set High-Z + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin) +{ + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + uint32_t aonPadIeSmt; + uint8_t realPin; + + /* always on pads IE control (in HBN) */ + if (gpioPin >= 9 && gpioPin <= 13) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT); + aonPadIeSmt &= ~(1 << (gpioPin - 9)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + } + + realPin = gpioPin; + /* sf pad use exclusive ie/pd/pu/drive/smtctrl */ + if (gpioPin >= 23 && gpioPin <= 28) { + if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) { + realPin += 9; + } + } + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4); + + /* pu=0, pd=0, ie=0 */ + if (realPin % 2 == 0) { + tmpVal = (tmpVal & 0xffffff00); + } else { + tmpVal = (tmpVal & 0xff00ffff); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal); + + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* func_sel=swgpio */ + if (gpioPin % 2 == 0) { + tmpVal = (tmpVal & 0xffff00ff); + tmpVal |= 0x0B00; + } else { + tmpVal = (tmpVal & 0x00ffffff); + tmpVal |= (0x0B00 << 16); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + /* Disable output anyway*/ + *pOut = tmpOut; + + return SUCCESS; +} + +BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Pad_HZ(void) +{ + uint32_t tmpVal; + uint32_t offset; + + for (offset = 23; offset <= 28; offset++) { + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4); + /* pu=0, pd=0, ie=0 */ + if (offset % 2 == 0) { + tmpVal = (tmpVal & 0xffffff00); + } else { + tmpVal = (tmpVal & 0xff00ffff); + } + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal); + + if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (offset - 23))) == 0) { + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4); + /* func_sel=swgpio */ + if (offset % 2 == 0) { + tmpVal = (tmpVal & 0xffff00ff); + tmpVal |= 0x0B00; + } else { + tmpVal = (tmpVal & 0x00ffffff); + tmpVal |= (0x0B00 << 16); + } + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal); + } + } + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET); + tmpVal &= 0xE07FFFFF; + BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal); + + return SUCCESS; +} + +BL_Err_Type ATTR_TCM_SECTION GLB_Set_Psram_Pad_HZ(void) +{ + uint32_t tmpVal; + uint32_t offset; + + for (offset = 32; offset <= 37; offset++) { + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4); + /* pu=0, pd=0, ie=0 */ + if (offset % 2 == 0) { + tmpVal = (tmpVal & 0xffffff00); + } else { + tmpVal = (tmpVal & 0xff00ffff); + } + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal); + + if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (offset - 32))) > 0) { + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4); + /* func_sel=swgpio */ + if ((offset - 9) % 2 == 0) { + tmpVal = (tmpVal & 0xffff00ff); + tmpVal |= 0x0B00; + } else { + tmpVal = (tmpVal & 0x00ffffff); + tmpVal |= (0x0B00 << 16); + } + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4, tmpVal); + } + } + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + 4); + tmpVal &= 0xFFFFFFC0; + BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + 4, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GPIO function + * + * @param gpioPin: GPIO type + * + * @return GPIO function + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + if (gpioPin % 2 == 0) { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL); + } else { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL); + } +} +#endif + +/****************************************************************************/ /** + * @brief Write GPIO + * + * @param gpioPin: GPIO type + * @param val: GPIO value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val) +{ + uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2)); + uint32_t pos = gpioPin % 32; + uint32_t tmpOut; + + tmpOut = *pOut; + if (val > 0) { + tmpOut |= (1 << pos); + } else { + tmpOut &= (~(1 << pos)); + } + *pOut = tmpOut; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read GPIO + * + * @param gpioPin: GPIO type + * + * @return GPIO value + * +*******************************************************************************/ +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin) +{ + uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2)); + uint32_t pos = gpioPin % 32; + + if ((*p) & (1 << pos)) { + return 1; + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask + * + * @param gpioPin: GPIO type + * @param intMask: GPIO interrupt MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1); + if (intMask == MASK) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask + * + * @param gpioPin: GPIO type + * @param intClear: GPIO interrupt clear or unclear + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1); + if (intClear == SET) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GLB GPIO interrrupt status + * + * @param gpioPin: GPIO type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal = 0; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1); + } + + return (tmpVal & (1 << gpioPin)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mode + * + * @param gpioPin: GPIO type + * @param intCtlMod: GPIO interrupt control mode + * @param intTrgMod: GPIO interrupt trigger mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod) +{ + uint32_t tmpVal; + uint32_t tmpGpioPin; + + CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod)); + CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod)); + + if (gpioPin < GLB_GPIO_PIN_10) { + /* GPIO0 ~ GPIO9 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1); + tmpGpioPin = gpioPin; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal); + } else if (gpioPin < GLB_GPIO_PIN_20) { + /* GPIO10 ~ GPIO19 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_10; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal); + } else if (gpioPin < GLB_GPIO_PIN_30) { + /* GPIO20 ~ GPIO29 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_20; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal); + } else { + /* GPIO30 ~ GPIO31 not recommend */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_30; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get GPIO interrupt control mode + * + * @param gpioPin: GPIO pin type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t bitVal; + + if (gpioPin < GLB_GPIO_PIN_10) { + /* GPIO0 - GPIO9 */ + bitVal = gpioPin - 0; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) { + /* GPIO10 - GPIO19 */ + bitVal = gpioPin - 10; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else if ((gpioPin > GLB_GPIO_PIN_19) && (gpioPin < GLB_GPIO_PIN_30)) { + /* GPIO20 - GPIO29 */ + bitVal = gpioPin - 20; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else { + /* GPIO30 ~ GPIO31 not recommend */ + bitVal = gpioPin - 30; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask 2 + * + * @param gpioPin: GPIO type + * @param intMask: GPIO interrupt MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MASK1); + if (intMask == MASK) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MASK1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask 2 + * + * @param gpioPin: GPIO type + * @param intClear: GPIO interrupt clear or unclear + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_CLR1); + if (intClear == SET) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_CLR1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GLB GPIO interrrupt status 2 + * + * @param gpioPin: GPIO type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal = 0; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_STAT1); + } + + return (tmpVal & (1 << gpioPin)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mode 2 + * + * @param gpioPin: GPIO type + * @param intCtlMod: GPIO interrupt control mode + * @param intTrgMod: GPIO interrupt trigger mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod) +{ + uint32_t tmpVal; + uint32_t tmpGpioPin; + + CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod)); + CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod)); + + if (gpioPin < GLB_GPIO_PIN_10) { + /* GPIO0 ~ GPIO9 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1); + tmpGpioPin = gpioPin; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1, tmpVal); + } else if (gpioPin < GLB_GPIO_PIN_20) { + /* GPIO10 ~ GPIO19 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_10; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2, tmpVal); + } else if (gpioPin < GLB_GPIO_PIN_30) { + /* GPIO20 ~ GPIO29 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_20; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3, tmpVal); + } else { + /* GPIO30 ~ GPIO31 not recommend */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_30; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get GPIO interrupt control mode 2 + * + * @param gpioPin: GPIO pin type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t bitVal; + + if (gpioPin < GLB_GPIO_PIN_10) { + /* GPIO0 - GPIO9 */ + bitVal = gpioPin - 0; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) { + /* GPIO10 - GPIO19 */ + bitVal = gpioPin - 10; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else if ((gpioPin > GLB_GPIO_PIN_19) && (gpioPin < GLB_GPIO_PIN_30)) { + /* GPIO20 - GPIO29 */ + bitVal = gpioPin - 20; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else { + /* GPIO30 ~ GPIO31 not recommend */ + bitVal = gpioPin - 30; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } +} + +/****************************************************************************/ /** + * @brief GPIO INT0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler callback install + * + * @param gpioPin: GPIO pin type + * @param cbFun: callback function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun) +{ + if (gpioPin < 32) { + glbGpioInt0CbfArra[gpioPin] = cbFun; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler callback install2 + * + * @param gpioPin: GPIO pin type + * @param cbFun: callback function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun) +{ + if (gpioPin < 32) { + glbGpioInt0CbfArra2[gpioPin] = cbFun; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void GPIO_INT0_IRQHandler(void) +{ + GLB_GPIO_Type gpioPin; + uint32_t timeOut = 0; + + for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_31; gpioPin++) { + if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) { + GLB_GPIO_IntClear(gpioPin, SET); + + /* timeout check */ + timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT; + do { + timeOut--; + } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut); + if (!timeOut) { + MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + + /* if timeOut==0, GPIO interrupt status not cleared */ + GLB_GPIO_IntClear(gpioPin, RESET); + + if (glbGpioInt0CbfArra[gpioPin] != NULL) { + /* Call the callback function */ + glbGpioInt0CbfArra[gpioPin](); + } + } + if (SET == GLB_Get_GPIO_Int2Status(gpioPin)) { + GLB_GPIO_Int2Clear(gpioPin, SET); + + /* timeout check */ + timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT; + do { + timeOut--; + } while ((SET == GLB_Get_GPIO_Int2Status(gpioPin)) && timeOut); + if (!timeOut) { + MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + + /* if timeOut==0, GPIO interrupt status not cleared */ + GLB_GPIO_Int2Clear(gpioPin, RESET); + + if (glbGpioInt0CbfArra2[gpioPin] != NULL) { + /* Call the callback function */ + glbGpioInt0CbfArra2[gpioPin](); + } + } + } +} +#endif + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_hbn.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_hbn.c new file mode 100644 index 0000000000000000000000000000000000000000..6449176a56b6aae6b574f4f7485fd086f9967818 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_hbn.c @@ -0,0 +1,2014 @@ +/** + ****************************************************************************** + * @file bl702_hbn.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_hbn.h" +#include "bl702_glb.h" +#include "bl702_xip_sflash.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Private_Macros + * @{ + */ +#define HBN_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group HBN_Private_Macros */ + +/** @defgroup HBN_Private_Types + * @{ + */ + +/*@} end of group HBN_Private_Types */ + +/** @defgroup HBN_Private_Variables + * @{ + */ +static intCallback_Type *hbnInt0CbfArra[HBN_OUT0_MAX] = { NULL, NULL, NULL, NULL, NULL, NULL }; +static intCallback_Type *hbnInt1CbfArra[HBN_OUT1_MAX] = { NULL, NULL, NULL, NULL }; + +/*@} end of group HBN_Private_Variables */ + +/** @defgroup HBN_Global_Variables + * @{ + */ + +/*@} end of group HBN_Global_Variables */ + +/** @defgroup HBN_Private_Fun_Declaration + * @{ + */ + +/*@} end of group HBN_Private_Fun_Declaration */ + +/** @defgroup HBN_Private_Functions + * @{ + */ + +/*@} end of group HBN_Private_Functions */ + +/** @defgroup HBN_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Enter HBN + * + * @param cfg: HBN APP Config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) +{ + uint32_t valLow = 0, valHigh = 0; + uint64_t val; + uint32_t tmpVal = 0, tmpVal2 = 0; + + /* work clock select */ + if (cfg->useXtal32k) { + HBN_32K_Sel(HBN_32K_XTAL); + } else { + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* turn off RC32K during HBN */ + if ((cfg->hbnLevel) >= HBN_LEVEL_2) { + HBN_Power_Off_RC32K(); + } else { + HBN_Power_On_RC32K(); + } + + /* clear aon pad interrupt before config them */ + HBN_Clear_IRQ(HBN_INT_GPIO9); + HBN_Clear_IRQ(HBN_INT_GPIO10); + HBN_Clear_IRQ(HBN_INT_GPIO11); + HBN_Clear_IRQ(HBN_INT_GPIO12); + HBN_Clear_IRQ(HBN_INT_GPIO13); + + /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc)); + + if (cfg->gpioWakeupSrc != 0) { + HBN_Aon_Pad_IeSmt_Cfg(cfg->gpioWakeupSrc); + HBN_GPIO_INT_Enable(cfg->gpioTrigType); + } else { + HBN_Aon_Pad_IeSmt_Cfg(0); + } + + /* always disable and mask aon_pad_GPIO9, mask/unmask and ie_enable/ie_disable */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK); + tmpVal2 |= (1 << 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, tmpVal2); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT); + tmpVal2 &= ~(1 << 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + /* HBN RTC config and enable */ + if (cfg->sleepTime != 0) { + // set rtc enable flag + BL_WR_WORD(0x40010FFC, 0x1); + + HBN_Clear_RTC_Counter(); + HBN_Get_RTC_Timer_Val(&valLow, &valHigh); + val = valLow + ((uint64_t)valHigh << 32); + val += cfg->sleepTime; + HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39); + HBN_Enable_RTC_Counter(); + } + + HBN_Power_Down_Flash(cfg->flashCfg); + + switch (cfg->flashPinCfg) { + case 0: + HBN_Set_Pad_23_28_Pullup(); + break; + + case 1: + /* need do nothing */ + break; + + case 2: + /* need do nothing */ + break; + + case 3: + /* can do nothing */ + break; + + default: + break; + } + + GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + + /* power off xtal */ + AON_Power_Off_XTAL(); + + HBN_Enable_Ext(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel); +} + +/****************************************************************************/ /** + * @brief power down and switch clock + * + * @param flashCfg: None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +{ + SPI_Flash_Cfg_Type bhFlashCfg; + + if (flashCfg == NULL) { + /* fix this some time */ + /* SFlash_Cache_Flush(); */ + XIP_SFlash_Read_Via_Cache_Need_Lock(BL702_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(SPI_Flash_Cfg_Type)); + /* fix this some time */ + /* SFlash_Cache_Flush(); */ + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Reset_Continue_Read(&bhFlashCfg); + } else { + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Reset_Continue_Read(flashCfg); + } + + SFlash_Powerdown(); +} + +/****************************************************************************/ /** + * @brief Enable HBN mode + * + * @param aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to + * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01. + * @param ldoLevel: LDO volatge level + * @param hbnLevel: HBN work level + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel)); + + /* Setting from guide */ + /* RAM Retion, no longer use */ + /* BL_WR_REG(HBN_BASE,HBN_SRAM,0x24); */ + + /* AON GPIO IE */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + /* HBN mode LDO level */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Select RC32M */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch (hbnLevel) { + case HBN_LEVEL_0: + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_1: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_2: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_3: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + default: + break; + } + + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Enable HBN mode */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + while (1) { + BL702_Delay_MS(1000); + } +} + +/****************************************************************************/ /** + * @brief Reset HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Reset HBN mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief reset HBN by software + * + * @param npXtalType: NP clock type + * @param bclkDiv: NP clock div + * @param apXtalType: AP clock type + * @param fclkDiv: AP clock div + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv) +{ + uint32_t tmp[12]; + + tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL); + tmp[1] = BL_RD_REG(HBN_BASE, HBN_TIME_L); + tmp[2] = BL_RD_REG(HBN_BASE, HBN_TIME_H); + tmp[3] = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmp[4] = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmp[5] = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmp[6] = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + tmp[7] = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + tmp[8] = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmp[9] = BL_RD_REG(HBN_BASE, HBN_RSV0); + tmp[10] = BL_RD_REG(HBN_BASE, HBN_RSV1); + tmp[11] = BL_RD_REG(HBN_BASE, HBN_RSV2); + /* DO HBN reset */ + HBN_Reset(); + /* HBN need 3 32k cyclce to recovery */ + BL702_Delay_US(100); + /* Recover HBN value */ + BL_WR_REG(HBN_BASE, HBN_TIME_L, tmp[1]); + BL_WR_REG(HBN_BASE, HBN_TIME_H, tmp[2]); + BL_WR_REG(HBN_BASE, HBN_CTL, tmp[0]); + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp[3]); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmp[4]); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmp[5]); + BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmp[6]); + BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmp[7]); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmp[8]); + BL_WR_REG(HBN_BASE, HBN_RSV0, tmp[9]); + BL_WR_REG(HBN_BASE, HBN_RSV1, tmp[10]); + BL_WR_REG(HBN_BASE, HBN_RSV2, tmp[11]); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Disable HBN mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable HBN PIR + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable HBN PIR + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Config HBN PIR interrupt + * + * @param pirIntCfg: HBN PIR interrupt configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg) +{ + uint32_t tmpVal; + uint32_t bit4 = 0; + uint32_t bit5 = 0; + uint32_t bitVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + + /* low trigger interrupt */ + if (pirIntCfg->lowIntEn == ENABLE) { + bit5 = 0; + } else { + bit5 = 1; + } + + /* high trigger interrupt */ + if (pirIntCfg->highIntEn == ENABLE) { + bit4 = 0; + } else { + bit4 = 1; + } + + bitVal = bit4 | (bit5 << 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select HBN PIR low pass filter + * + * @param lpf: HBN PIR low pass filter selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select HBN PIR high pass filter + * + * @param hpf: HBN PIR high pass filter selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set HBN PIR threshold value + * + * @param threshold: HBN PIR threshold value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold) +{ + uint32_t tmpVal; + + CHECK_PARAM((threshold <= 0x3FFF)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold); + BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN PIR threshold value + * + * @param None + * + * @return HBN PIR threshold value + * +*******************************************************************************/ +uint16_t HBN_Get_PIR_Threshold(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH); +} + +/****************************************************************************/ /** + * @brief Set HBN PIR interval value + * + * @param interval: HBN PIR interval value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval) +{ + uint32_t tmpVal; + + CHECK_PARAM((interval <= 0xFFF)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval); + BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN PIR interval value + * + * @param None + * + * @return HBN PIR interval value + * +*******************************************************************************/ +uint16_t HBN_Get_PIR_Interval(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL); +} + +/****************************************************************************/ /** + * @brief get HBN bor out state + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_MISC), HBN_R_BOR_OUT) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief set HBN bor config + * + * @param enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset + * @param threshold: bor threshold + * @param mode: bor work mode with por + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold)); + CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + + if (enable) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 0); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, threshold); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, mode); + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11aon voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11rt voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11soc voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11 all voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11rt drive strength + * + * @param strength: ldo11rt drive strength + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(strength)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_ILOAD_SEL, strength); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN select 32K + * + * @param clkType: HBN 32k clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType)); + + HBN_Trim_RC32K(); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select uart clock source + * + * @param clkSel: uart clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select xclk clock source + * + * @param xClk: xclk clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + + switch (xClk) { + case HBN_XCLK_CLK_RC32M: + tmpVal2 &= (~(1 << 0)); + break; + + case HBN_XCLK_CLK_XTAL: + tmpVal2 |= (1 << 0); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select root clk source + * + * @param rootClk: root clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + + switch (rootClk) { + case HBN_ROOT_CLK_RC32M: + tmpVal2 = 0x0; + break; + + case HBN_ROOT_CLK_XTAL: + tmpVal2 = 0x1; + break; + + case HBN_ROOT_CLK_DLL: + tmpVal2 |= (1 << 1); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set HBN_RAM sleep mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_slp(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set HBN_RAM retension mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_Ret(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); + + /* Delay >1s */ + BL702_Delay_US(1100); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + /* Delay >800us */ + BL702_Delay_US(880); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off RC3K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Trim RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void) +{ + Efuse_Ana_RC32K_Trim_Type trim; + int32_t tmpVal = 0; + + EF_Ctrl_Read_RC32K_Trim(&trim); + + if (trim.trimRc32kExtCodeEn) { + if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN); + BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal); + BL702_Delay_US(2); + return SUCCESS; + } + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Get HBN status flag + * + * @param None + * + * @return HBN status flag value + * +*******************************************************************************/ +uint32_t HBN_Get_Status_Flag(void) +{ + return BL_RD_REG(HBN_BASE, HBN_RSV0); +} + +/****************************************************************************/ /** + * @brief Set HBN status flag + * + * @param flag: Status Flag + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag) +{ + BL_WR_REG(HBN_BASE, HBN_RSV0, flag); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN wakeup address + * + * @param None + * + * @return HBN wakeup address + * +*******************************************************************************/ +uint32_t HBN_Get_Wakeup_Addr(void) +{ + return BL_RD_REG(HBN_BASE, HBN_RSV1); +} + +/****************************************************************************/ /** + * @brief Set HBN wakeup address + * + * @param addr: HBN wakeup address + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr) +{ + BL_WR_REG(HBN_BASE, HBN_RSV1, addr); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set RTC timer configuration + * + * @param delay: RTC interrupt delay 32 clocks + * @param compValLow: RTC interrupt commpare value low 32 bits + * @param compValHigh: RTC interrupt commpare value high 32 bits + * @param compMode: RTC interrupt commpare + * mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay)); + + BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow); + BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set interrupt delay option */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay); + /* Set RTC compare mode */ + tmpVal |= (compMode << 1); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get RTC timer count value + * + * @param valLow: RTC count value pointer for low 32 bits + * @param valHigh: RTC count value pointer for high 8 bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh) +{ + uint32_t tmpVal; + + /* Tigger RTC val read */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + + /* Read RTC val */ + *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); + *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_INT(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable GPIO interrupt + * + * @param gpioIntTrigType: HBN GPIO interrupt trigger type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable GPIO interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT); + + if (tmpVal & (1 << irqType)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief HBN get pin wakeup mode value + * + * @param None + * + * @return HBN pin wakeup mode value + * +*******************************************************************************/ +uint8_t HBN_Get_Pin_Wakeup_Mode(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE); +} + +/****************************************************************************/ /** + * @brief HBN clear interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_INT_TYPE(irqType)); + + /* set clear bit */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmpVal |= (1 << irqType); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal); + + /* unset clear bit */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmpVal &= (~(1 << irqType)); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN hardware pullup or pulldown configuration + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + } + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN Config AON pad input and SMT + * + * @param padCfg: AON pad config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, padCfg); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN wakeup pin mask configuration + * + * @param maskVal: mask value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable ACOMP0 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); + tmpVal2 = tmpVal2 | (1 << edge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable ACOMP0 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); + tmpVal2 = tmpVal2 & (~(1 << edge)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable ACOMP1 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); + tmpVal2 = tmpVal2 | (1 << edge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable ACOMP1 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); + tmpVal2 = tmpVal2 & (~(1 << edge)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable BOR interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_BOR_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable BOR interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_BOR_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get HBN reset event status + * + * @param event: HBN reset event type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RESET_EVENT); + + return (tmpVal & (1 << event)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief clear HBN reset event status + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_Reset_Event(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out0 install interrupt callback + * + * @param intType: HBN out0 interrupt type + * @param cbFun: HBN out0 interrupt callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType)); + + hbnInt0CbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out1 install interrupt callback + * + * @param intType: HBN out1 interrupt type + * @param cbFun: HBN out1 interrupt callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType)); + + hbnInt1CbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN GPIO debug pull config + * + * @param pupdEn: Enable or disable GPIO pull down and pull up + * @param dlyEn: Enable or disable GPIO wakeup delay function + * @param dlySec: GPIO wakeup delay sec 1 to 7 + * @param gpioIrq: HBN GPIO num + * @param gpioMask: HBN GPIO MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask) +{ + uint32_t tmpVal; + + CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7))); + CHECK_PARAM((gpioIrq >= HBN_INT_GPIO9) && (gpioIrq <= HBN_INT_GPIO13)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, pupdEn); + + if (gpioMask != UNMASK) { + tmpVal = tmpVal | (1 << (gpioIrq + 8)); + } else { + tmpVal = tmpVal & ~(1 << (gpioIrq + 8)); + } + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set pad 23-28 pull none + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pullnone(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x00); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x00); + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set pad 23-28 pull up + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pullup(void) +{ + uint32_t tmpVal = 0; + + /********************************************/ + /* GPIO28 is bootpin, so leave it pull none */ + /********************************************/ + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x00); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x1F); + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set pad 23-28 pull down + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pulldown(void) +{ + uint32_t tmpVal = 0; + + /********************************************/ + /* GPIO28 is bootpin, so leave it pull none */ + /********************************************/ + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x1F); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x00); + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set pad 23-28 active ie + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_ActiveIE(void) +{ + uint32_t tmpVal = 0; + + /********************************************/ + /* GPIO28 is bootpin, so leave it pull none */ + /********************************************/ + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x1F); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x1F); + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set BOR config + * + * @param cfg: Enable or disable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg) +{ + uint32_t tmpVal = 0; + + if (cfg->enableBorInt) { + HBN_Enable_BOR_IRQ(); + } else { + HBN_Disable_BOR_IRQ(); + } + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, cfg->borThreshold); + + if (cfg->enablePorInBor) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOR_SEL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOR_SEL); + } + + if (cfg->enableBor) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR); + } + + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN OUT0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +void HBN_OUT0_IRQHandler(void) +{ + if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) { + HBN_Clear_IRQ(HBN_INT_GPIO9); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO9] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO9](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) { + HBN_Clear_IRQ(HBN_INT_GPIO10); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO10] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO10](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) { + HBN_Clear_IRQ(HBN_INT_GPIO11); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO11] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO11](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) { + HBN_Clear_IRQ(HBN_INT_GPIO12); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO12] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO12](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO13)) { + HBN_Clear_IRQ(HBN_INT_GPIO13); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO13] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO13](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_RTC)) { + HBN_Clear_IRQ(HBN_INT_RTC); + HBN_Clear_RTC_INT(); + + if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_RTC](); + } + } +} + +/****************************************************************************/ /** + * @brief HBN OUT1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +void HBN_OUT1_IRQHandler(void) +{ + /* PIR */ + if (SET == HBN_Get_INT_State(HBN_INT_PIR)) { + HBN_Clear_IRQ(HBN_INT_PIR); + + if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_PIR](); + } + } + + /* BOR */ + if (SET == HBN_Get_INT_State(HBN_INT_BOR)) { + HBN_Clear_IRQ(HBN_INT_BOR); + + if (hbnInt1CbfArra[HBN_OUT1_INT_BOR] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_BOR](); + } + } + + /* ACOMP0 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) { + HBN_Clear_IRQ(HBN_INT_ACOMP0); + + if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0](); + } + } + + /* ACOMP1 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) { + HBN_Clear_IRQ(HBN_INT_ACOMP1); + + if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1](); + } + } +} + +/****************************************************************************/ /** + * @brief Enable HBN mode + * + * @param aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to + * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01. + * @param ldoLevel: LDO volatge level + * @param hbnLevel: HBN work level + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel)); + + /* Setting from guide */ + /* RAM Retion */ + BL_WR_REG(HBN_BASE, HBN_SRAM, 0x24); + /* AON GPIO IE */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + ///* Power off 1.8V */ + //tmpVal=BL_RD_REG(AON_BASE,AON_PMIP); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO11_SOC); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_RF); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_IO); + ///* SOC11 enum is not the same as VDD11*/ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_SOC_VOUT_SEL,ldoLevel-1); + //BL_WR_REG(AON_BASE,AON_PMIP,tmpVal); + // + ///* Set RT voltage */ + //tmpVal=BL_RD_REG(AON_BASE,AON); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW3); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW2); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW1); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_BYPASS); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO18_AON); + ///* RT11 enum is not the same as VDD11*/ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_RT_VOUT_SEL,ldoLevel-1); + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_VDD11_SEL,ldoLevel); + //BL_WR_REG(AON_BASE,AON,tmpVal); + + /* Select RC32M */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch (hbnLevel) { + case HBN_LEVEL_0: + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_1: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_2: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_3: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + default: + break; + } + + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Enable HBN mode */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + while (1) { + BL702_Delay_MS(1000); + } +} + +/****************************************************************************/ /** + * @brief HBN out0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out0_IRQHandler_Install(void) +{ + Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out1 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out1_IRQHandler_Install(void) +{ + Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler); + return SUCCESS; +} + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..6a52759a7f086497a06fbde945991cab5ab106bf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c.c @@ -0,0 +1,824 @@ +/** + ****************************************************************************** + * @file bl702_i2c.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_i2c.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ +#define I2C_FIFO_STATUS_TIMEOUT (160 * 1000 * 2) +#define PUT_UINT32_LE(n, b, i) \ + { \ + (b)[(i)] = (uint8_t)((n)); \ + (b)[(i) + 1] = (uint8_t)((n) >> 8); \ + (b)[(i) + 2] = (uint8_t)((n) >> 16); \ + (b)[(i) + 3] = (uint8_t)((n) >> 24); \ + } + +/*@} end of group I2C_Private_Macros */ + +/** @defgroup I2C_Private_Types + * @{ + */ + +/*@} end of group I2C_Private_Types */ + +/** @defgroup I2C_Private_Variables + * @{ + */ +intCallback_Type *i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL] = { { NULL } }; + +/*@} end of group I2C_Private_Variables */ + +/** @defgroup I2C_Global_Variables + * @{ + */ + +/*@} end of group I2C_Global_Variables */ + +/** @defgroup I2C_Private_Fun_Declaration + * @{ + */ + +/*@} end of group I2C_Private_Fun_Declaration */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief I2C interrupt handler + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static void I2C_IntHandler(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_TXF_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_RXF_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_NAK_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_ARB_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, I2C_FER_INT)) { + if (i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL) { + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT](); + } + } +} +#endif + +/*@} end of group I2C_Private_Functions */ + +/** @defgroup I2C_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief I2C write word data + * + * @param i2cNo: I2C ID type + * @param data: Data word + * + * @return None + * +*******************************************************************************/ +void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data) +{ + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data); +} + +/****************************************************************************/ /** + * @brief I2C read word data + * + * @param i2cNo: I2C ID type + * + * @return word data + * +*******************************************************************************/ +uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo) +{ + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + return BL_RD_REG(I2Cx, I2C_FIFO_RDATA); +} + +/****************************************************************************/ /** + * @brief I2C enable + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +void I2C_Enable(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2C disable + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +void I2C_Disable(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); + + /* Clear I2C fifo */ + tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR); + BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal); + + /* Clear I2C interrupt status */ + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR); + BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2C set global reset function + * + * @param i2cNo: I2C ID type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo) +{ + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_I2C); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief I2C init function + * + * @param i2cNo: I2C ID type + * @param direct: I2C read or write direct + * @param cfg: I2C transfer config struct + * + * @return None + * +*******************************************************************************/ +void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_I2C); + + /* I2C write config */ + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + + if (direct == I2C_WRITE) { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr); + + if (cfg->subAddrSize > 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize - 1); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); + + /* Set sub address */ + BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(I2C_IRQn, I2C_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief Set de-glitch function cycle count value + * + * @param i2cNo: I2C ID type + * @param cnt: De-glitch function cycle count + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + + if (cnt > 0) { + /* enable de-glitch function */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN); + } else if (cnt == 0) { + /* disable de-glitch function */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN); + } else { + return ERROR; + } + + /* Set count value */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_DEG_CNT, cnt); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set i2c prd + * + * @param i2cNo: I2C ID type + * @param phase: I2C phase value + * + * @return None + * +*******************************************************************************/ +void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + //phase_cycles = (32000000 / phase / 4) - 1; + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal); + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal); + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2C set scl output clock + * + * @param i2cNo: I2C ID type + * @param clk: Clock set + * + * @return None + * +*******************************************************************************/ +void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk) +{ + uint8_t bclkDiv = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + bclkDiv = GLB_Get_BCLK_Div(); + + if (clk >= 100000) { + GLB_Set_I2C_CLK(1, 0); + I2C_SetPrd(i2cNo, (SystemCoreClockGet() / (bclkDiv + 1)) / (clk * 4) - 1); + } else if (clk >= 8000) { + GLB_Set_I2C_CLK(1, 9); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 10) / (clk * 4) - 1); + } else if (clk >= 800) { + GLB_Set_I2C_CLK(1, 99); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 100) / (clk * 4) - 1); + } else { + GLB_Set_I2C_CLK(1, 255); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 256) / (clk * 4) - 1); + } +} + +/****************************************************************************/ /** + * @brief I2C set scl sync + * + * @param i2cNo: I2C ID type + * @param enable: Enable or disable I2C scl sync + * + * @return None + * +*******************************************************************************/ +void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); + } + + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Get i2c busy state + * + * @param i2cNo: I2C ID type + * + * @return RESET or SET + * +*******************************************************************************/ +BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_BUS_BUSY); + return ((BL_IS_REG_BIT_SET(tmpVal, I2C_STS_I2C_BUS_BUSY)) ? SET : RESET); +} + +/****************************************************************************/ /** + * @brief Get i2c transfer end state + * + * @param i2cNo: I2C ID type + * + * @return RESET or SET + * +*******************************************************************************/ +BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? SET : RESET); +} + +/****************************************************************************/ /** + * @brief I2C master write block data + * + * @param i2cNo: I2C ID type + * @param cfg: I2C transfer config struct + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) +{ + uint8_t i; + uint32_t timeOut = 0; + uint32_t temp = 0; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + I2C_Disable(i2cNo); + I2C_Init(i2cNo, I2C_WRITE, cfg); + I2C_Enable(i2cNo); + + /* Set I2C write data */ + for (i = 0; i < cfg->dataSize; i++) { + temp += (cfg->data[i] << ((i % 4) * 8)); + + if ((i + 1) % 4 == 0) { + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); + temp = 0; + } + } + + if ((cfg->dataSize % 4) != 0) { + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); + } + + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + I2C_Disable(i2cNo); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief I2C master read block data + * + * @param i2cNo: I2C ID type + * @param cfg: I2C transfer config struct + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) +{ + uint8_t i = 0; + uint32_t timeOut = 0; + uint32_t temp = 0; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + I2C_Disable(i2cNo); + I2C_Init(i2cNo, I2C_READ, cfg); + I2C_Enable(i2cNo); + + /* Read I2C data */ + while (cfg->dataSize - i >= 4) { + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); + PUT_UINT32_LE(temp, cfg->data, i); + i += 4; + } + + if (i < cfg->dataSize) { + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); + + while (i < cfg->dataSize) { + cfg->data[i] = (temp & 0xff); + temp = (temp >> 8); + i++; + } + } + + timeOut = I2C_FIFO_STATUS_TIMEOUT; + + while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) { + timeOut--; + + if (timeOut == 0) { + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + I2C_Disable(i2cNo); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Mask/Unmask the I2C interrupt + * + * @param i2cNo: I2C ID type + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + CHECK_PARAM(IS_I2C_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + + switch (intType) { + case I2C_TRANS_END_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + } + + break; + + case I2C_TX_FIFO_READY_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + } + + break; + + case I2C_RX_FIFO_READY_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + } + + break; + + case I2C_NACK_RECV_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + } + + break; + + case I2C_ARB_LOST_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + } + + break; + + case I2C_FIFO_ERR_INT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } + + break; + + case I2C_INT_ALL: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } else { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } + + break; + + default: + break; + } + + BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); +} + +/****************************************************************************/ /** + * @brief Install I2C interrupt callback function + * + * @param i2cNo: I2C ID type + * @param intType: Specifies the interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + CHECK_PARAM(IS_I2C_INT_TYPE(intType)); + + i2cIntCbfArra[i2cNo][intType] = cbFun; +} +#endif + +/****************************************************************************/ /** + * @brief I2C IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_IRQHandler(void) +{ + I2C_IntHandler(I2C0_ID); +} +#endif + +/*@} end of group I2C_Public_Functions */ + +/*@} end of group I2C */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c_gpio_sim.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c_gpio_sim.c new file mode 100644 index 0000000000000000000000000000000000000000..2f6367f4a5f05c68a8d21429ae5a3ebe490fc2fd --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c_gpio_sim.c @@ -0,0 +1,470 @@ +/** + ****************************************************************************** + * @file bl702_i2c_gpio_sim.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_glb.h" +#include "bl702_gpio.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2C_GPIO_SIM + * @{ + */ + +/** @defgroup I2C_GPIO_SIM_Private_Macros + * @{ + */ +#define SCL_H GLB_GPIO_Write(sclPin, 1) +#define SCL_L GLB_GPIO_Write(sclPin, 0) +#define SDA_H GLB_GPIO_Write(sdaPin, 1) +#define SDA_L GLB_GPIO_Write(sdaPin, 0) +#define SDA_read GLB_GPIO_Read(sdaPin) +#define I2C_Delay_US(a) BL702_Delay_US(a) +#define I2C_Delay_Const I2C_Delay_US(2) + +/*@} end of group I2C_GPIO_SIM_Private_Macros */ + +/** @defgroup I2C_GPIO_SIM_Private_Types + * @{ + */ + +/*@} end of group I2C_GPIO_SIM_Private_Types */ + +/** @defgroup I2C_GPIO_SIM_Private_Variables + * @{ + */ +static GLB_GPIO_Type sclPin; +static GLB_GPIO_Type sdaPin; +static uint8_t sda_out = 0; + +/*@} end of group I2C_GPIO_SIM_Private_Variables */ + +/** @defgroup I2C_GPIO_SIM_Global_Variables + * @{ + */ + +/*@} end of group I2C_GPIO_SIM_Global_Variables */ + +/** @defgroup I2C_GPIO_SIM_Private_Fun_Declaration + * @{ + */ + +/*@} end of group I2C_GPIO_SIM_Private_Fun_Declaration */ + +/** @defgroup I2C_GPIO_SIM_Private_Functions + * @{ + */ + +/*@} end of group I2C_GPIO_SIM_Private_Functions */ + +/** @defgroup I2C_GPIO_SIM_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief I2C GPIO init function + * + * @param sclGPIOPin: I2C SCL GPIO pin + * @param sdaGPIOPin: I2C SDA GPIO pin + * + * @return None + * +*******************************************************************************/ +void I2C_GPIO_Sim_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin) +{ + GLB_GPIO_Cfg_Type cfg; + uint8_t gpiopins[2]; + uint8_t gpiofuns[2]; + int i; + + sclPin = sclGPIOPin; + sdaPin = sdaGPIOPin; + + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 1; + cfg.smtCtrl = 1; + cfg.gpioMode = GPIO_MODE_OUTPUT; + + gpiopins[0] = sclPin; + gpiopins[1] = sdaPin; + gpiofuns[0] = 11; + gpiofuns[1] = 11; + + for (i = 0; i < sizeof(gpiopins) / sizeof(gpiopins[0]); i++) { + cfg.gpioPin = gpiopins[i]; + cfg.gpioFun = gpiofuns[i]; + GLB_GPIO_Init(&cfg); + } +} + +/****************************************************************************/ /** + * @brief I2C SDA out function + * + * @param None + * + * @return None + * +*******************************************************************************/ +static void I2C_SDA_OUT(void) +{ + GLB_GPIO_Cfg_Type cfg; + + if (sda_out == 1) { + return; + } + + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 1; + cfg.smtCtrl = 1; + cfg.gpioMode = GPIO_MODE_OUTPUT; + cfg.gpioPin = sdaPin; + cfg.gpioFun = 11; + + GLB_GPIO_Init(&cfg); + + sda_out = 1; +} + +/****************************************************************************/ /** + * @brief I2C SDA in function + * + * @param None + * + * @return None + * +*******************************************************************************/ +static void I2C_SDA_IN(void) +{ + GLB_GPIO_Cfg_Type cfg; + + if (sda_out == 0) { + return; + } + + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 1; + cfg.smtCtrl = 1; + cfg.gpioMode = GPIO_MODE_INPUT; + cfg.gpioPin = sdaPin; + cfg.gpioFun = 11; + + GLB_GPIO_Init(&cfg); + + sda_out = 0; +} + +/****************************************************************************/ /** + * @brief I2C start function + * + * @param None + * + * @return None + * +*******************************************************************************/ +void I2C_Start(void) +{ + I2C_SDA_OUT(); + SDA_H; + I2C_Delay_Const; + SCL_H; + I2C_Delay_Const; + SDA_L; + I2C_Delay_Const; + SCL_L; +} + +/****************************************************************************/ /** + * @brief I2C stop function + * + * @param None + * + * @return None + * +*******************************************************************************/ +void I2C_Stop(void) +{ + I2C_SDA_OUT(); + SCL_L; + I2C_Delay_Const; + SDA_L; + I2C_Delay_Const; + SCL_H; + I2C_Delay_Const; + SDA_H; + I2C_Delay_Const; +} + +/****************************************************************************/ /** + * @brief I2C ack function + * + * @param None + * + * @return None + * +*******************************************************************************/ +static void I2C_Ack(void) +{ + SCL_L; + I2C_Delay_Const; + I2C_SDA_OUT(); + SDA_L; + I2C_Delay_Const; + SCL_H; + I2C_Delay_Const; + SCL_L; +} + +/****************************************************************************/ /** + * @brief I2C no ack function + * + * @param None + * + * @return None + * +*******************************************************************************/ +static void I2C_NoAck(void) +{ + SCL_L; + I2C_Delay_Const; + I2C_SDA_OUT(); + SDA_H; + I2C_Delay_Const; + SCL_H; + I2C_Delay_Const; + SCL_L; +} + +/****************************************************************************/ /** + * @brief I2C get ack function + * + * @param None + * + * @return None + * +*******************************************************************************/ +uint8_t I2C_GetAck(void) +{ + uint8_t time = 0; + + I2C_Delay_Const; + I2C_SDA_IN(); + + I2C_Delay_Const; + SCL_H; + I2C_Delay_Const; + + while (SDA_read) { + time++; + + if (time > 25) { + SCL_L; + return 0; + } + } + + SCL_L; + + return 1; +} + +/****************************************************************************/ /** + * @brief I2C send byte function + * + * @param Data: send data + * + * @return None + * +*******************************************************************************/ +void I2C_SendByte(uint8_t Data) +{ + uint8_t cnt; + + I2C_SDA_OUT(); + + for (cnt = 0; cnt < 8; cnt++) { + SCL_L; + I2C_Delay_Const; + + if (Data & 0x80) { + SDA_H; + } else { + SDA_L; + } + + Data <<= 1; + I2C_Delay_Const; + SCL_H; + I2C_Delay_Const; + } + + SCL_L; + + I2C_Delay_Const; +} + +/****************************************************************************/ /** + * @brief I2C read byte function + * + * @param ack: i2c ack byte + * + * @return None + * +*******************************************************************************/ +uint8_t I2C_ReadByte(uint8_t ack) +{ + uint8_t cnt; + uint8_t data = 0; + + I2C_SDA_IN(); + + for (cnt = 0; cnt < 8; cnt++) { + SCL_L; + I2C_Delay_Const; + + SCL_H; + I2C_Delay_Const; + data <<= 1; + + if (SDA_read) { + data |= 0x01; + } + } + + if (ack == 1) { + I2C_Ack(); + } else { + I2C_NoAck(); + } + + return data; +} + +/****************************************************************************/ /** + * @brief SCCB init function + * + * @param sclGPIOPin: I2C SCL GPIO pin + * @param sdaGPIOPin: I2C SDA GPIO pin + * + * @return None + * +*******************************************************************************/ +int SCCB_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin) +{ + I2C_GPIO_Sim_Init(sclGPIOPin, sdaGPIOPin); + return 0; +} + +/****************************************************************************/ /** + * @brief SCCB write function + * + * @param slave_addr: salve addr + * @param data: write data + * @param wrsize: write data len + * + * @return None + * +*******************************************************************************/ +int SCCB_Write(uint8_t slave_addr, uint8_t *data, uint32_t wrsize) +{ + uint32_t i = 0; + + I2C_Start(); + + I2C_SendByte((slave_addr << 1) | 0); + + if (!I2C_GetAck()) { + I2C_Stop(); + return -1; + } + + for (i = 0; i < wrsize; i++) { + I2C_SendByte(data[i]); + + if (!I2C_GetAck()) { + I2C_Stop(); + return -1; + } + } + + I2C_Stop(); + + return 0; +} + +/****************************************************************************/ /** + * @brief SCCB read function + * + * @param slave_addr: salve addr + * @param data: read data + * @param rdsize: read data len + * + * @return None + * +*******************************************************************************/ +int SCCB_Read(uint8_t slave_addr, uint8_t *data, uint32_t rdsize) +{ + uint32_t i = 0; + + if (0 == rdsize) { + return -1; + } + + I2C_Start(); + + I2C_SendByte((slave_addr << 1) | 1); + + if (!I2C_GetAck()) { + I2C_Stop(); + return -1; + } + + for (i = 0; i < rdsize - 1; i++) { + data[i] = I2C_ReadByte(1); + } + + data[i] = I2C_ReadByte(0); + + I2C_Stop(); + + return 0; +} + +/*@} end of group I2C_GPIO_SIM_Public_Functions */ + +/*@} end of group I2C_GPIO_SIM */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2s.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..ba311e19ab8f377032cdad569ecea71dc82fc8bf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2s.c @@ -0,0 +1,469 @@ +/** + ****************************************************************************** + * @file bl702_i2s.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_i2s.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/** @defgroup I2S_Private_Macros + * @{ + */ + +/*@} end of group I2S_Private_Macros */ + +/** @defgroup I2S_Private_Types + * @{ + */ + +/*@} end of group I2S_Private_Types */ + +/** @defgroup I2S_Private_Variables + * @{ + */ + +/*@} end of group I2S_Private_Variables */ + +/** @defgroup I2S_Global_Variables + * @{ + */ + +/*@} end of group I2S_Global_Variables */ + +/** @defgroup I2S_Private_Fun_Declaration + * @{ + */ + +/*@} end of group I2S_Private_Fun_Declaration */ + +/** @defgroup I2S_Private_Functions + * @{ + */ + +/*@} end of group I2S_Private_Functions */ + +/** @defgroup I2S_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief I2S BCLK config + * + * @param i2sCfg: I2S configuration pointer + * + * @return NONE + * +*******************************************************************************/ +void I2S_SetBclkPeriod(I2S_CFG_Type *i2sCfg) +{ + uint32_t overSampleRate; + uint32_t bclkDivCnt; + uint32_t tmpVal; + + CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize)); + + overSampleRate = i2sCfg->audioFreqHz / i2sCfg->sampleFreqHz; + + switch (i2sCfg->frameSize) { + case I2S_SIZE_FRAME_8: + bclkDivCnt = overSampleRate / 16; + break; + + case I2S_SIZE_FRAME_16: + bclkDivCnt = overSampleRate / 32; + break; + + case I2S_SIZE_FRAME_24: + bclkDivCnt = overSampleRate / 48; + break; + + case I2S_SIZE_FRAME_32: + bclkDivCnt = overSampleRate / 64; + break; + + default: + bclkDivCnt = overSampleRate / 16; + break; + } + + bclkDivCnt = (bclkDivCnt / 2) - 1; + + tmpVal = (bclkDivCnt << 16) | bclkDivCnt; + BL_WR_REG(I2S_BASE, I2S_BCLK_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2S configuration + * + * @param i2sCfg: I2S configuration pointer + * + * @return NONE + * +*******************************************************************************/ +void I2S_Init(I2S_CFG_Type *i2sCfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_I2S_ENDIAN_TYPE(i2sCfg->endianType)); + CHECK_PARAM(IS_I2S_MODE_TYPE(i2sCfg->modeType)); + CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize)); + CHECK_PARAM(IS_I2S_FS_MODE_TYPE(i2sCfg->fsMode)); + CHECK_PARAM(IS_I2S_FS_CHANNEL_TYPE(i2sCfg->fsChannel)); + CHECK_PARAM(IS_I2S_DATA_SIZE_TYPE(i2sCfg->dataSize)); + CHECK_PARAM(IS_I2S_MONO_MODE_CHANNEL(i2sCfg->monoModeChannel)); + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_I2S); + + tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG); + + /* Set data endian*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_ENDIAN, i2sCfg->endianType); + + /* Set I2S mode */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_MODE, i2sCfg->modeType); + + /* Set BCLK invert */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, i2sCfg->bclkInvert); + + /* Set FS size */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FRAME_SIZE, i2sCfg->frameSize); + + /* Set FS invert */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, i2sCfg->fsInvert); + + /* Set FS mode */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_1T_MODE, i2sCfg->fsMode); + + /* Set FS channel mode */ + + switch (i2sCfg->fsChannel) { + case I2S_FS_CHANNELS_2: + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE); + break; + + case I2S_FS_CHANNELS_3: + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE); + break; + + case I2S_FS_CHANNELS_4: + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE); + break; + + default: + break; + } + + /* Set Data size */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DATA_SIZE, i2sCfg->dataSize); + + /* Set Data offset */ + if (i2sCfg->dataOffset != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_OFS_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_OFS_CNT, i2sCfg->dataOffset - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_OFS_EN); + } + + /* Set mono mode */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_MODE, i2sCfg->monoMode); + + /* Set rx mono mode channel left or right */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_RX_CH, i2sCfg->monoModeChannel); + + /* Clear mute mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); + + BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal); + + I2S_SetBclkPeriod(i2sCfg); +} + +/****************************************************************************/ /** + * @brief I2S configure FIFO function + * + * @param fifoCfg: FIFO configuration structure pointer + * + * @return None + * +*******************************************************************************/ +void I2S_FifoConfig(I2S_FifoCfg_Type *fifoCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_0); + /* Set packed mode */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_MERGE, fifoCfg->lRMerge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_EXCHG, fifoCfg->frameDataExchange); + /* Clear tx and rx FIFO signal */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR); + + /* Set DMA config */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_TX_EN, fifoCfg->txfifoDmaEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_RX_EN, fifoCfg->rxfifoDmaEnable); + + BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal); + + /* Set CLR signal to 0*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_TX_FIFO_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_RX_FIFO_CLR); + BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal); + + tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1); + /* Set TX and RX FIFO threshold */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_TX_FIFO_TH, fifoCfg->txFifoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_RX_FIFO_TH, fifoCfg->rxFifoLevel); + + BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_1, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2S configure IO function + * + * @param ioCfg: IO configuration structure pointer + * + * @return None + * +*******************************************************************************/ +void I2S_IOConfig(I2S_IOCfg_Type *ioCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(I2S_BASE, I2S_IO_CONFIG); + /* Enable or disable deglitch */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_EN, ioCfg->deglitchEn); + + /* Set deglitch cycle count */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_CNT, ioCfg->deglitchCnt); + + /* Enable or disable inverse BCLK signal */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, ioCfg->inverseBCLK); + + /* Enable or disable inverse FS signal */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, ioCfg->inverseFS); + + /* Enable or disable inverse RX signal */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_RXD_INV, ioCfg->inverseRX); + + /* Enable or disable inverse TX signal */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_TXD_INV, ioCfg->inverseTX); + + BL_WR_REG(I2S_BASE, I2S_IO_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable I2S + * + * @param roleType: I2S master or slave + * + * @return None + * +*******************************************************************************/ +void I2S_Enable(I2S_Role_Type roleType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_I2S_ROLE_TYPE(roleType)); + + tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN); + + /* Set role type */ + if (I2S_ROLE_MASTER == roleType) { + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); + } else if (I2S_ROLE_SLAVE == roleType) { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); + } + + BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable I2S + * + * @param None + * + * @return None + * +*******************************************************************************/ +void I2S_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN); + + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); + BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2S read data + * + * @param None + * + * @return Data read + * +*******************************************************************************/ +uint32_t I2S_Read(void) +{ + while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT)) { + }; + + return BL_RD_REG(I2S_BASE, I2S_FIFO_RDATA); +} + +/****************************************************************************/ /** + * @brief I2S write data + * + * @param data: write data + * + * @return None + * +*******************************************************************************/ +void I2S_Write(uint32_t data) +{ + while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT)) { + }; + + BL_WR_REG(I2S_BASE, I2S_FIFO_WDATA, data); +} + +/****************************************************************************/ /** + * @brief I2S set mute + * + * @param enabled: mute enabled or not + * + * @return None + * +*******************************************************************************/ +void I2S_Mute(BL_Fun_Type enabled) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG); + + if (enabled ? 1 : 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); + } + + BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2S set 24-bit data align mode in fifo + * + * @param justType: Align mode + * + * @return None + * +*******************************************************************************/ +void I2S_SetFifoJustified(I2S_FIFO_24_Justified_Type justType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_I2S_FIFO_24_JUSTIFIED_TYPE(justType)); + + tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_24B_LJ, justType); + BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief I2S flush + * + * @param None + * + * @return data count in TX FIFO + * +*******************************************************************************/ +uint32_t I2S_GetTxFIFO_AvlCnt(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief I2S flush + * + * @param None + * + * @return data count in RX FIFO + * +*******************************************************************************/ +uint32_t I2S_GetRxFIFO_AvlCnt(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief I2S flush + * + * @param None + * + * @return None + * +*******************************************************************************/ +void I2S_Flush(void) +{ + while (I2S_TX_FIFO_SIZE != I2S_GetTxFIFO_AvlCnt()) + ; +} + +/*@} end of group I2S_Public_Functions */ + +/*@} end of group I2S */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ir.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ir.c new file mode 100644 index 0000000000000000000000000000000000000000..3c306d2e1cccb2d4132c9800730a407dbd5dcf0f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ir.c @@ -0,0 +1,1156 @@ +/** + ****************************************************************************** + * @file bl702_ir.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_ir.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup IR + * @{ + */ + +/** @defgroup IR_Private_Macros + * @{ + */ +#define NEC_HEAD_H_MIN 17000 +#define NEC_HEAD_H_MAX 19000 +#define NEC_HEAD_L_MIN 8400 +#define NEC_HEAD_L_MAX 9600 +#define NEC_BIT0_H_MIN 525 +#define NEC_BIT0_H_MAX 1725 +#define RC5_ONE_PLUSE_MIN 1175 +#define RC5_ONE_PLUSE_MAX 2375 +#define RC5_TWO_PLUSE_MIN 2955 +#define RC5_TWO_PLUSE_MAX 4155 +#define IR_TX_INT_TIMEOUT_COUNT (100 * 160 * 1000) +#define IR_RX_INT_TIMEOUT_COUNT (100 * 160 * 1000) + +/*@} end of group IR_Private_Macros */ + +/** @defgroup IR_Private_Types + * @{ + */ + +/*@} end of group IR_Private_Types */ + +/** @defgroup IR_Private_Variables + * @{ + */ +static intCallback_Type *irIntCbfArra[IR_INT_ALL] = { NULL, NULL }; + +/*@} end of group IR_Private_Variables */ + +/** @defgroup IR_Global_Variables + * @{ + */ + +/*@} end of group IR_Global_Variables */ + +/** @defgroup IR_Private_Fun_Declaration + * @{ + */ + +/*@} end of group IR_Private_Fun_Declaration */ + +/** @defgroup IR_Private_Functions + * @{ + */ + +/*@} end of group IR_Private_Functions */ + +/** @defgroup IR_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief IR RX IRQ handler function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void IRRX_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + + if (BL_IS_REG_BIT_SET(tmpVal, IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_END_MASK)) { + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); + + if (irIntCbfArra[IR_INT_RX] != NULL) { + irIntCbfArra[IR_INT_RX](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief IR TX IRQ handler function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void IRTX_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); + + if (BL_IS_REG_BIT_SET(tmpVal, IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_END_MASK)) { + BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR)); + + if (irIntCbfArra[IR_INT_TX] != NULL) { + irIntCbfArra[IR_INT_TX](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief IR tx initialization function + * + * @param irTxCfg: IR tx configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg) +{ + uint32_t tmpVal; + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR); + + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + /* Set data bit */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, irTxCfg->dataBits - 1); + /* Set tail pulse */ + ENABLE == irTxCfg->tailPulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_HL_INV)); + ENABLE == irTxCfg->tailPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_EN)); + /* Set head pulse */ + ENABLE == irTxCfg->headPulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_HL_INV)); + ENABLE == irTxCfg->headPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_EN)); + /* Enable or disable logic 1 and 0 pulse inverse */ + ENABLE == irTxCfg->logic1PulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV)); + ENABLE == irTxCfg->logic0PulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV)); + /* Enable or disable data pulse */ + ENABLE == irTxCfg->dataPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_DATA_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_DATA_EN)); + /* Enable or disable output modulation */ + ENABLE == irTxCfg->outputModulation ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_MOD_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_MOD_EN)); + /* Enable or disable output inverse */ + ENABLE == irTxCfg->outputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_OUT_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_OUT_INV)); + + /* Write back */ + BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(IRTX_IRQn, IRTX_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR tx pulse width configure function + * + * @param irTxPulseWidthCfg: IR tx pulse width configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE, IRTX_PW); + /* Set logic 0 pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH0_W, irTxPulseWidthCfg->logic0PulseWidth_0 - 1); + /* Set logic 0 pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH1_W, irTxPulseWidthCfg->logic0PulseWidth_1 - 1); + /* Set logic 1 pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH0_W, irTxPulseWidthCfg->logic1PulseWidth_0 - 1); + /* Set logic 1 pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH1_W, irTxPulseWidthCfg->logic1PulseWidth_1 - 1); + /* Set head pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH0_W, irTxPulseWidthCfg->headPulseWidth_0 - 1); + /* Set head pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH1_W, irTxPulseWidthCfg->headPulseWidth_1 - 1); + /* Set tail pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH0_W, irTxPulseWidthCfg->tailPulseWidth_0 - 1); + /* Set tail pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH1_W, irTxPulseWidthCfg->tailPulseWidth_1 - 1); + BL_WR_REG(IR_BASE, IRTX_PW, tmpVal); + + tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH); + /* Set modulation phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH0_W, irTxPulseWidthCfg->moduWidth_0 - 1); + /* Set modulation phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH1_W, irTxPulseWidthCfg->moduWidth_1 - 1); + /* Set pulse width unit */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, irTxPulseWidthCfg->pulseWidthUnit - 1); + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR tx software mode pulse width(multiples of pulse width unit) configure function + * + * @param irTxSWMPulseWidthCfg: IR tx software mode pulse width configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg) +{ + /* Set swm pulse width,multiples of pulse width unit */ + BL_WR_REG(IR_BASE, IRTX_SWM_PW_0, irTxSWMPulseWidthCfg->swmData0); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_1, irTxSWMPulseWidthCfg->swmData1); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_2, irTxSWMPulseWidthCfg->swmData2); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_3, irTxSWMPulseWidthCfg->swmData3); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_4, irTxSWMPulseWidthCfg->swmData4); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_5, irTxSWMPulseWidthCfg->swmData5); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_6, irTxSWMPulseWidthCfg->swmData6); + BL_WR_REG(IR_BASE, IRTX_SWM_PW_7, irTxSWMPulseWidthCfg->swmData7); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR rx initialization function + * + * @param irRxCfg: IR rx configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode)); + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR); + + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + + /* Set rx mode */ + switch (irRxCfg->rxMode) { + case IR_RX_NEC: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0); + break; + + case IR_RX_RC5: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1); + break; + + case IR_RX_SWM: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2); + break; + + default: + break; + } + + /* Enable or disable input inverse */ + ENABLE == irRxCfg->inputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)); + /* Enable or disable rx input de-glitch function */ + ENABLE == irRxCfg->rxDeglitch ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)); + /* Set de-glitch function cycle count */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DEG_CNT, irRxCfg->DeglitchCnt); + /* Write back */ + BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG); + /* Set pulse width threshold to trigger end condition */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, irRxCfg->endThreshold - 1); + /* Set pulse width threshold for logic0/1 detection */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DATA_TH, irRxCfg->dataThreshold - 1); + /* Write back */ + BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(IRRX_IRQn, IRRX_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR set default value of all registers function + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_DeInit(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_IRR); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR enable function + * + * @param direct: IR direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_Enable(IR_Direction_Type direct) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); + + if (direct == IR_TX || direct == IR_TXRX) { + /* Enable ir tx unit */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_EN)); + } + + if (direct == IR_RX || direct == IR_TXRX) { + /* Enable ir rx unit */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR disable function + * + * @param direct: IR direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_Disable(IR_Direction_Type direct) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); + + if (direct == IR_TX || direct == IR_TXRX) { + /* Disable ir tx unit */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_EN)); + } + + if (direct == IR_RX || direct == IR_TXRX) { + /* Disable ir rx unit */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR tx software mode enable or disable function + * + * @param txSWM: Enable or disable + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM) +{ + uint32_t tmpVal; + + /* Enable or disable tx swm */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + + if (ENABLE == txSWM) { + BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN)); + } else { + BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR clear rx fifo function + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_RxFIFOClear(void) +{ + uint32_t tmpVal; + + /* Clear rx fifo */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0); + BL_WR_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_RX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send data function + * + * @param irWord: IR tx data word 0 or 1 + * @param data: data to send + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SendData(IR_Word_Type irWord, uint32_t data) +{ + /* Check the parameters */ + CHECK_PARAM(IS_IR_WORD_TYPE(irWord)); + + /* Write word 0 or word 1 */ + if (IR_WORD_0 == irWord) { + BL_WR_REG(IR_BASE, IRTX_DATA_WORD0, data); + } else { + BL_WR_REG(IR_BASE, IRTX_DATA_WORD1, data); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR software mode send pulse width data function + * + * @param data: data to send + * @param length: Length of send buffer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length) +{ + uint8_t i = 0, j = 0; + uint16_t minData = data[0]; + uint32_t tmpVal; + uint32_t pwVal = 0; + uint32_t count = (length + 7) / 8; + + /* Search for min value */ + for (i = 1; i < length; i++) { + if (minData > data[i] && data[i] != 0) { + minData = data[i]; + } + } + + /* Set pulse width unit */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH); + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, minData)); + + /* Set tx SWM pulse width data as multiples of pulse width unit */ + for (i = 0; i < count; i++) { + pwVal = 0; + + if (i < count - 1) { + for (j = 0; j < 8; j++) { + tmpVal = ((2 * data[j + i * 8] + minData) / (2 * minData) - 1) & 0xf; + pwVal |= tmpVal << (4 * j); + } + + *(volatile uint32_t *)(IR_BASE + IRTX_SWM_PW_0_OFFSET + i * 4) = pwVal; + } else { + for (j = 0; j < length % 8; j++) { + tmpVal = ((2 * data[j + i * 8] + minData) / (2 * minData) - 1) & 0xf; + pwVal |= tmpVal << (4 * j); + } + + *(volatile uint32_t *)(IR_BASE + IRTX_SWM_PW_0_OFFSET + i * 4) = pwVal; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send command function + * + * @param word1: IR send data word 1 + * @param word0: IR send data word 0 + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SendCommand(uint32_t word1, uint32_t word0) +{ + uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; + + /* Write data */ + IR_SendData(IR_WORD_1, word1); + IR_SendData(IR_WORD_0, word0); + + /* Mask tx interrupt */ + IR_IntMask(IR_INT_TX, MASK); + + /* Clear tx interrupt */ + IR_ClrIntStatus(IR_INT_TX); + + /* Enable ir tx */ + IR_Enable(IR_TX); + + /* Wait for tx interrupt */ + while (SET != IR_GetIntStatus(IR_INT_TX)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + IR_Disable(IR_TX); + + return TIMEOUT; + } + } + + /* Disable ir tx */ + IR_Disable(IR_TX); + + /* Clear tx interrupt */ + IR_ClrIntStatus(IR_INT_TX); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send command in software mode function + * + * @param data: IR fifo data to send + * @param length: Length of data + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length) +{ + uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; + + /* Write fifo */ + IR_SWMSendData(data, length); + + /* Mask tx interrupt */ + IR_IntMask(IR_INT_TX, MASK); + + /* Clear tx interrupt */ + IR_ClrIntStatus(IR_INT_TX); + + /* Enable ir tx */ + IR_Enable(IR_TX); + + /* Wait for tx interrupt */ + while (SET != IR_GetIntStatus(IR_INT_TX)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + IR_Disable(IR_TX); + + return TIMEOUT; + } + } + + /* Disable ir tx */ + IR_Disable(IR_TX); + + /* Clear tx interrupt */ + IR_ClrIntStatus(IR_INT_TX); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send in NEC protocol + * + * @param address: Address + * @param command: Command + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command) +{ + uint32_t tmpVal = ((~command & 0xff) << 24) + (command << 16) + ((~address & 0xff) << 8) + address; + + IR_SendCommand(0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR interrupt mask or unmask function + * + * @param intType: IR interrupt type + * @param intMask: Mask or unmask + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_INT_TYPE(intType)); + + if (intType == IR_INT_TX || intType == IR_INT_ALL) { + /* Mask or unmask tx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); + BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_END_MASK, intMask)); + } + + if (intType == IR_INT_RX || intType == IR_INT_ALL) { + /* Mask or unmask rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_MASK, intMask)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear ir interrupt function + * + * @param intType: IR interrupt type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_INT_TYPE(intType)); + + if (intType == IR_INT_TX || intType == IR_INT_ALL) { + /* Clear tx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); + BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR)); + } + + if (intType == IR_INT_RX || intType == IR_INT_ALL) { + /* Clear rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR install interrupt callback function + * + * @param intType: IR interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_IR_INT_TYPE(intType)); + + irIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR get interrupt status function + * + * @param intType: IR int type + * + * @return IR tx or rx interrupt status + * +*******************************************************************************/ +BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_INT_TYPE(intType)); + + /* Read tx or rx interrupt status */ + if (IR_INT_TX == intType) { + tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IRTX_END_INT); + } else if (IR_INT_RX == intType) { + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IRRX_END_INT); + } + + if (tmpVal) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief IR get rx fifo underflow or overflow status function + * + * @param fifoSts: IR fifo status type + * + * @return IR rx fifo status + * +*******************************************************************************/ +BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_FIFOSTATUS_TYPE(fifoSts)); + + /* Read rx fifo status */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0); + + if (fifoSts == IR_RX_FIFO_UNDERFLOW) { + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_UNDERFLOW); + } else { + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_OVERFLOW); + } + + if (tmpVal) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief IR receive data function + * + * @param irWord: IR rx data word 0 or 1 + * + * @return Data received + * +*******************************************************************************/ +uint32_t IR_ReceiveData(IR_Word_Type irWord) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_WORD_TYPE(irWord)); + + /* Read word 0 or word 1 */ + if (IR_WORD_0 == irWord) { + tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD0); + } else { + tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD1); + } + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief IR software mode receive pulse width data function + * + * @param data: Data received + * @param length: Max length of receive buffer + * + * @return Length of datas received + * +*******************************************************************************/ +uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length) +{ + uint8_t rxLen = 0; + + while (rxLen < length && IR_GetRxFIFOCount() > 0) { + /* Read data */ + data[rxLen++] = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_RDATA) & 0xffff; + } + + return rxLen; +} + +/****************************************************************************/ /** + * @brief IR receive in NEC protocol + * + * @param address: Address + * @param command: Command + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command) +{ + uint32_t tmpVal = IR_ReceiveData(IR_WORD_0); + + *address = tmpVal & 0xff; + *command = (tmpVal >> 16) & 0xff; + + if ((~(*address) & 0xff) != ((tmpVal >> 8) & 0xff) || (~(*command) & 0xff) != ((tmpVal >> 24) & 0xff)) { + return ERROR; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR get rx data bit count function + * + * @param None + * + * @return IR rx data bit count + * +*******************************************************************************/ +uint8_t IR_GetRxDataBitCount(void) +{ + uint32_t tmpVal; + + /* Read rx data bit count */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_COUNT); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_STS_IRRX_DATA_CNT); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief IR get rx fifo count function + * + * @param None + * + * @return IR rx fifo available count + * +*******************************************************************************/ +uint8_t IR_GetRxFIFOCount(void) +{ + uint32_t tmpVal; + + /* Read rx fifo count */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_CNT); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief IR learning to set rx and tx mode function + * + * @param data: Buffer to save data + * @param length: Length of data + * + * @return Protocol type + * +*******************************************************************************/ +IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length) +{ + uint32_t tmpVal; + uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR); + + /* Disable rx,set rx in software mode and enable rx input inverse */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2); + tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV); + BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal); + /* Set pulse width threshold to trigger end condition */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG); + BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, 19999)); + + /* Clear and mask rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_MASK); + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); + + /* Enable rx */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN)); + + /* Wait for rx interrupt */ + while (SET != IR_GetIntStatus(IR_INT_RX)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + IR_Disable(IR_RX); + + return IR_RX_SWM; + } + } + + /* Disable rx */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN)); + + /* Clear rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); + BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); + + /*Receive data */ + *length = IR_GetRxFIFOCount(); + *length = IR_SWMReceiveData((uint16_t *)data, *length); + + /* Judge protocol type */ + if (NEC_HEAD_H_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < NEC_HEAD_H_MAX && NEC_HEAD_L_MIN < (data[0] >> 16) && (data[0] >> 16) < NEC_HEAD_L_MAX && NEC_BIT0_H_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < NEC_BIT0_H_MAX) { + /* Set rx in NEC mode */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0)); + /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */ + BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x23270d47); + /* Set tx in NEC mode */ + /* Tx configure */ + BL_WR_REG(IR_BASE, IRTX_CONFIG, 0x1f514); + /* Set logic 0,logic 1,head and tail pulse width */ + BL_WR_REG(IR_BASE, IRTX_PW, 0x7f2000); + /* Set modulation phase width and pulse width unit */ + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110464); + + return IR_RX_NEC; + } else if (RC5_ONE_PLUSE_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < RC5_ONE_PLUSE_MAX && ((RC5_ONE_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_TWO_PLUSE_MAX)) && + ((RC5_ONE_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_TWO_PLUSE_MAX))) { + /* Set rx in RC-5 mode */ + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1)); + /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */ + BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x13870a6a); + /* Set tx in RC-5 mode */ + /* Tx configure */ + BL_WR_REG(IR_BASE, IRTX_CONFIG, 0xc134); + /* Set logic 0,logic 1,head and tail pulse width */ + BL_WR_REG(IR_BASE, IRTX_PW, 0); + /* Set modulation phase width and pulse width unit */ + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x221106f1); + + return IR_RX_RC5; + } else if ((data[0] >> 16) != 0) { + /* Set tx in software mode */ + /* Tx configure */ + BL_WR_REG(IR_BASE, IRTX_CONFIG, *length << 12 | 0xc); + /* Set modulation phase width */ + BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110000); + + return IR_RX_SWM; + } else { + tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE); + + if (tmpVal == 0) { + return IR_RX_NEC; + } else if (tmpVal == 1) { + return IR_RX_RC5; + } else { + return IR_RX_SWM; + } + } +} + +/****************************************************************************/ /** + * @brief IR receive data according to mode which is learned function + * + * @param mode: Protocol type + * @param data: Buffer to save data + * + * @return Length of data + * +*******************************************************************************/ +uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data) +{ + uint8_t length = 0; + uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); + + /* Disable ir rx */ + IR_Disable(IR_RX); + + /* Clear and mask rx interrupt */ + IR_ClrIntStatus(IR_INT_RX); + IR_IntMask(IR_INT_RX, MASK); + + /* Enable ir rx */ + IR_Enable(IR_RX); + + /* Wait for rx interrupt */ + while (SET != IR_GetIntStatus(IR_INT_RX)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + IR_Disable(IR_RX); + + return TIMEOUT; + } + } + + /* Disable ir rx */ + IR_Disable(IR_RX); + + /* Clear rx interrupt */ + IR_ClrIntStatus(IR_INT_RX); + + /* Receive data according to mode */ + if (mode == IR_RX_NEC || mode == IR_RX_RC5) { + /* Get data bit count */ + length = IR_GetRxDataBitCount(); + data[0] = IR_ReceiveData(IR_WORD_0); + } else { + /* Get fifo count */ + length = IR_GetRxFIFOCount(); + length = IR_SWMReceiveData((uint16_t *)data, length); + } + + return length; +} + +/****************************************************************************/ /** + * @brief IR send data according to mode which is learned function + * + * @param mode: Protocol type + * @param data: Buffer of data to send + * @param length: Length of data + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); + + /* Set send length */ + tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, length - 1); + BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal); + + if (mode == IR_RX_NEC || mode == IR_RX_RC5) { + IR_SendCommand(0, data[0]); + } else { + IR_SWMSendCommand((uint16_t *)data, length); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR init to control led function + * + * @param clk: Clock source + * @param div: Clock division(1~64) + * @param unit: Pulse width unit(multiples of clock pulse width, 1~4096) + * @param code0H: code 0 high level time(multiples of pulse width unit, 1~16) + * @param code0L: code 0 low level time(multiples of pulse width unit, 1~16) + * @param code1H: code 1 high level time(multiples of pulse width unit, 1~16) + * @param code1L: code 1 low level time(multiples of pulse width unit, 1~16) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L) +{ + IR_TxCfg_Type txCfg = { + 24, /* 24-bit data */ + DISABLE, /* Disable signal of tail pulse inverse */ + DISABLE, /* Disable signal of tail pulse */ + DISABLE, /* Disable signal of head pulse inverse */ + DISABLE, /* Disable signal of head pulse */ + DISABLE, /* Disable signal of logic 1 pulse inverse */ + DISABLE, /* Disable signal of logic 0 pulse inverse */ + ENABLE, /* Enable signal of data pulse */ + DISABLE, /* Disable signal of output modulation */ + ENABLE /* Enable signal of output inverse */ + }; + + IR_TxPulseWidthCfg_Type txPWCfg = { + code0L, /* Pulse width of logic 0 pulse phase 1 */ + code0H, /* Pulse width of logic 0 pulse phase 0 */ + code1L, /* Pulse width of logic 1 pulse phase 1 */ + code1H, /* Pulse width of logic 1 pulse phase 0 */ + 1, /* Pulse width of head pulse phase 1 */ + 1, /* Pulse width of head pulse phase 0 */ + 1, /* Pulse width of tail pulse phase 1 */ + 1, /* Pulse width of tail pulse phase 0 */ + 1, /* Modulation phase 1 width */ + 1, /* Modulation phase 0 width */ + unit /* Pulse width unit */ + }; + + HBN_Set_XCLK_CLK_Sel(clk); + GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, div - 1); + + /* Disable ir before config */ + IR_Disable(IR_TXRX); + + /* IR tx init */ + IR_TxInit(&txCfg); + IR_TxPulseWidthConfig(&txPWCfg); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief IR send 24-bit data to control led function + * + * @param data: Data to send(24-bit) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_LEDSend(uint32_t data) +{ + /* Change MSB_first to LSB_first */ + data = ((data >> 1) & 0x55555555) | ((data << 1) & 0xaaaaaaaa); + data = ((data >> 2) & 0x33333333) | ((data << 2) & 0xcccccccc); + data = ((data >> 4) & 0x0f0f0f0f) | ((data << 4) & 0xf0f0f0f0); + data = ((data >> 16) & 0xff) | (data & 0xff00) | ((data << 16) & 0xff0000); + IR_SendCommand(0, data); + + return SUCCESS; +} + +/*@} end of group IR_Public_Functions */ + +/*@} end of group IR */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_kys.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_kys.c new file mode 100644 index 0000000000000000000000000000000000000000..7d5c4550f8d8fd2da0f608f74e67513a012652b0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_kys.c @@ -0,0 +1,274 @@ +/** + ****************************************************************************** + * @file bl702_kys.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_kys.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup KYS + * @{ + */ + +/** @defgroup KYS_Private_Macros + * @{ + */ + +/*@} end of group KYS_Private_Macros */ + +/** @defgroup KYS_Private_Types + * @{ + */ + +/*@} end of group KYS_Private_Types */ + +/** @defgroup KYS_Private_Variables + * @{ + */ +static intCallback_Type *KYSIntCbfArra[1] = { NULL }; + +/*@} end of group KYS_Private_Variables */ + +/** @defgroup KYS_Global_Variables + * @{ + */ + +/*@} end of group KYS_Global_Variables */ + +/** @defgroup KYS_Private_Fun_Declaration + * @{ + */ + +/*@} end of group KYS_Private_Fun_Declaration */ + +/** @defgroup KYS_Private_Functions + * @{ + */ + +/*@} end of group KYS_Private_Functions */ + +/** @defgroup KYS_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief KYS interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void KYS_IRQHandler(void) +{ + if (KYSIntCbfArra[0] != NULL) { + KYSIntCbfArra[0](); + } +} +#endif + +/****************************************************************************/ /** + * @brief KYS initialization function + * + * @param kysCfg: KYS configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + /* Set col and row */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_COL_NUM, kysCfg->col - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM, kysCfg->row - 1); + + /* Set idle duration between column scans */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_RC_EXT, kysCfg->idleDuration); + + /* Enable or disable ghost key event detection */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_GHOST_EN, kysCfg->ghostEn); + + /* Enable or disable deglitch function */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_EN, kysCfg->deglitchEn); + + /* Set deglitch count */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_CNT, kysCfg->deglitchCnt); + + /* Write back */ + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(KYS_IRQn, KYS_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable KYS + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_SET_REG_BIT(tmpVal, KYS_KS_EN)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable KYS + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_CLR_REG_BIT(tmpVal, KYS_KS_EN)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief KYS mask or unmask interrupt + * + * @param intMask: KYS interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_IntMask(BL_Mask_Type intMask) +{ + if (MASK == intMask) { + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 0); + } else { + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 1); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief KYS clear interrupt + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_IntClear(void) +{ + BL_WR_REG(KYS_BASE, KYS_KEYCODE_CLR, 0xf); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Install KYS interrupt callback function + * + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_Int_Callback_Install(intCallback_Type *cbFun) +{ + KYSIntCbfArra[0] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief KYS get interrupt status + * + * @param None + * + * @return Status of interrupt + * +*******************************************************************************/ +uint8_t KYS_GetIntStatus(void) +{ + return BL_RD_REG(KYS_BASE, KYS_KS_INT_STS) & 0xf; +} + +/****************************************************************************/ /** + * @brief KYS get keycode value + * + * @param keycode: KYS keycode type + * @param col: Col of key + * @param row: Row of key + * + * @return Keycode value + * +*******************************************************************************/ +uint8_t KYS_GetKeycode(KYS_Keycode_Type keycode, uint8_t *col, uint8_t *row) +{ + uint32_t tmpVal; + uint8_t keyValue; + + /* Get keycode value */ + keyValue = BL_RD_REG(KYS_BASE, KYS_KEYCODE_VALUE) >> (8 * keycode) & 0xff; + + /* Get total row number of keyboard */ + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM); + + /* Calculate col and row of the key */ + *col = keyValue / (tmpVal + 1); + *row = keyValue % (tmpVal + 1); + + return keyValue; +} + +/*@} end of group KYS_Public_Functions */ + +/*@} end of group KYS */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_l1c.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_l1c.c new file mode 100644 index 0000000000000000000000000000000000000000..6682b359a24fc99438db71486d73f27dd3a1b2e3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_l1c.c @@ -0,0 +1,665 @@ +/** + ****************************************************************************** + * @file bl702_l1c.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_l1c.h" +#include "bl702_common.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup L1C + * @{ + */ + +/** @defgroup L1C_Private_Macros + * @{ + */ + +/*@} end of group L1C_Private_Macros */ + +/** @defgroup L1C_Private_Types + * @{ + */ + +/*@} end of group L1C_Private_Types */ + +/** @defgroup L1C_Private_Variables + * @{ + */ +static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = { NULL }; +static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL }; + +/*@} end of group L1C_Private_Variables */ + +/** @defgroup L1C_Global_Variables + * @{ + */ + +/*@} end of group L1C_Global_Variables */ + +/** @defgroup L1C_Private_Fun_Declaration + * @{ + */ + +/*@} end of group L1C_Private_Fun_Declaration */ + +/** @defgroup L1C_Private_Functions + * @{ + */ + +/*@} end of group L1C_Private_Functions */ + +/** @defgroup L1C_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Enable cache + * + * @param wayDisable: cache way disable config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Enable_Set(uint8_t wayDisable) +{ + L1C_Cache_Flush(wayDisable); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief L1C cache write set + * + * @param wtEn: L1C write through enable + * @param wbEn: L1C write back enable + * @param waEn: L1C write allocate enable + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + + if (wtEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WT_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WT_EN); + } + + if (wbEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WB_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WB_EN); + } + + if (waEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WA_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WA_EN); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Flush cache + * + * @param wayDisable: cache way disable config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(uint8_t wayDisable) +{ + uint32_t tmpVal; + uint32_t cnt = 0; + uint8_t finWayDisable = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN); + finWayDisable = BL_GET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + /*Set Tag RAM to zero */ + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_INVALID_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_INVALID_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Polling for invalid done */ + do { + BL702_Delay_US(1); + cnt++; + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100); + + /* data flush */ + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_FLUSH_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Polling for flush done */ + do { + BL702_Delay_US(1); + cnt++; + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_FLUSH_DONE) && cnt < 100); + + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + if (wayDisable != 0xff) { + finWayDisable = wayDisable; + } + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal |= (finWayDisable << L1C_WAY_DIS_POS); + + /* If way disable is 0x0f, cacheable can't be set */ + if (finWayDisable != 0x0f) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Flush cache external api + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush_Ext(void) +{ + uint32_t tmpVal; + + /* Disable early respone */ + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + L1C_Cache_Flush((tmpVal >> L1C_WAY_DIS_POS) & 0xf); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get cache hit count + * + * @param hitCountLow: hit count low 32 bits pointer + * @param hitCountHigh: hit count high 32 bits pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) +{ + *hitCountLow = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_LSB); + *hitCountHigh = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_MSB); +} +#endif + +/****************************************************************************/ /** + * @brief Get cache miss count + * + * @param None + * + * @return Cache miss count + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint32_t ATTR_TCM_SECTION L1C_Cache_Miss_Count_Get(void) +{ + return BL_RD_REG(L1C_BASE, L1C_MISS_CNT); +} +#endif + +/****************************************************************************/ /** + * @brief Disable read from flash or psram with cache + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION L1C_Cache_Read_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief wrap set + * + * @param wrap: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap) +{ + uint32_t tmpVal = 0; + uint8_t cacheEn = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); + + if (cacheEn != 0) { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + } + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + + if (wrap == ENABLE) { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + if (cacheEn != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief cache way disable set + * + * @param disableVal: cache way disable value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + if (disableVal != 0x0f) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set for ROM 2T access if CPU freq >120MHz + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief L1C BMX init + * + * @param l1cBmxCfg: L1C BMX config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler); + Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS); + BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS); + BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get L1C BMX error status + * + * @param errType: L1C BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType)); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + + if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) { + return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET; + } +} + +/****************************************************************************/ /** + * @brief Get L1C BMX error address + * + * @param None + * + * @return NP L1C BMX error address + * +*******************************************************************************/ +uint32_t L1C_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR); +} + +/****************************************************************************/ /** + * @brief L1C BMX error interrupt callback install + * + * @param intType: L1C BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType)); + + l1cBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_ERR_IRQHandler(void) +{ + L1C_BMX_ERR_INT_Type intType; + + for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) { + if (l1cBmxErrIntCbfArra[intType] != NULL) { + l1cBmxErrIntCbfArra[intType](); + } + } + + while (1) { + MSG("L1C_BMX_ERR_IRQHandler\r\n"); + BL702_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief L1C BMX timeout interrupt callback install + * + * @param intType: L1C BMX timeout interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType)); + + l1cBmxToIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX Time Out interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_TO_IRQHandler(void) +{ + L1C_BMX_TO_INT_Type intType; + + for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) { + if (l1cBmxToIntCbfArra[intType] != NULL) { + l1cBmxToIntCbfArra[intType](); + } + } + + while (1) { + MSG("L1C_BMX_TO_IRQHandler\r\n"); + BL702_Delay_MS(1000); + } +} +#endif + +/*@} end of group L1C_Public_Functions */ + +/*@} end of group L1C */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_mjpeg.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_mjpeg.c new file mode 100644 index 0000000000000000000000000000000000000000..cdef1536bc161a55fb5e9bb6084399c3df74678e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_mjpeg.c @@ -0,0 +1,740 @@ +/** + ****************************************************************************** + * @file bl702_mjpeg.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702.h" +#include "bl702_mjpeg.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup MJPEG + * @{ + */ + +/** @defgroup MJPEG_Private_Macros + * @{ + */ + +/*@} end of group MJPEG_Private_Macros */ + +/** @defgroup MJPEG_Private_Types + * @{ + */ + +/*@} end of group MJPEG_Private_Types */ + +/** @defgroup MJPEG_Private_Variables + * @{ + */ +static intCallback_Type *mjpegIntCbfArra[MJPEG_INT_ALL] = { NULL }; + +/*@} end of group MJPEG_Private_Variables */ + +/** @defgroup MJPEG_Global_Variables + * @{ + */ + +/*@} end of group MJPEG_Global_Variables */ + +/** @defgroup MJPEG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group MJPEG_Private_Fun_Declaration */ + +/** @defgroup MJPEG_Private_Functions + * @{ + */ + +/*@} end of group MJPEG_Private_Functions */ + +/** @defgroup MJPEG_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Mjpeg module init + * + * @param cfg: Mjpeg configuration structure pointer + * + * @return None + * +*******************************************************************************/ +void MJPEG_Init(MJPEG_CFG_Type *cfg) +{ + uint32_t tmpVal; + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG); + + /* disable mjpeg */ + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); + + /* basic stuff */ + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YUV_MODE, cfg->yuv); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Q_MODE, cfg->quality); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_H_BUST, cfg->burst); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_BIT_ORDER, cfg->bitOrderEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_ORDER_U_EVEN, cfg->evenOrderEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_WR_OVER_STOP, cfg->overStopEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_REFLECT_DMY, cfg->reflectDmy); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_HBLK_DMY, cfg->verticalDmy); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_WBLK_DMY, cfg->horizationalDmy); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_WAIT_CYCLE, cfg->waitCount); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_SIZE); + + switch (cfg->yuv) { + case MJPEG_YUV422_INTERLEAVE: + case MJPEG_YUV422_PLANAR: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3); + break; + + case MJPEG_YUV420: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 15) >> 4); + break; + + case MJPEG_YUV400: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 7) >> 3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3); + break; + + default: + break; + } + + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_SIZE, tmpVal); + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_SWAP_MODE, cfg->swapModeEnable); + BL_WR_REG(MJPEG_BASE, MJPEG_SWAP_MODE, tmpVal); + + /*align buffer to 16 bytes boundary, should be kept the same as CAM module*/ + BL_WR_REG(MJPEG_BASE, MJPEG_YY_FRAME_ADDR, (cfg->bufferCamYY & 0xFFFFFFF0)); + BL_WR_REG(MJPEG_BASE, MJPEG_UV_FRAME_ADDR, (cfg->bufferCamUV & 0xFFFFFFF0)); + BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM, (cfg->sizeCamUV << 16) + cfg->sizeCamYY); + + /*align buffer to 16 bytes boundary*/ + BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_FRAME_ADDR, (cfg->bufferMjpeg & 0xFFFFFFF0)); + /*align buffer size in unit of 64 bytes */ + BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg >> 6); + + /* Clear interrupt */ + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x3F00); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(MJPEG_IRQn, MJPEG_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief Mjpeg packet mode configure + * + * @param cfg: Packet configuration + * + * @return None + * +*******************************************************************************/ +void MJPEG_Packet_Config(MJPEG_Packet_Type *cfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_PAKET_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_PKET_EN, cfg->packetEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_JEND_TO_PEND, cfg->endToTail); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_PKET_BODY_BYTE, cfg->packetBody); + BL_WR_REG(MJPEG_BASE, MJPEG_PAKET_CTRL, tmpVal); + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_HEAD_BYTE, cfg->frameHead); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_TAIL_EXP, cfg->frameTail); + BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal); + + BL_WR_REG(MJPEG_BASE, MJPEG_PAKET_HEAD_TAIL, (cfg->packetTail << 16) + cfg->packetHead); +} + +/****************************************************************************/ /** + * @brief Mjpeg set YUYV order, only work in interleave mode + * + * @param y0: Y0 order + * @param u0: U0 order + * @param y1: Y1 order + * @param v0: V0 order + * + * @return None + * +*******************************************************************************/ +void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y0_ORDER, y0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_U0_ORDER, u0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y1_ORDER, y1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_V0_ORDER, v0); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); + + MJPEG_Set_YUYV_Order_Planar(0, 1); +} + +/****************************************************************************/ /** + * @brief Mjpeg set YY/UV order, only work in planar mode + * + * @param yy: YY order + * @param uv: UV order + * + * @return None + * +*******************************************************************************/ +void MJPEG_Set_YUYV_Order_Planar(uint8_t yy, uint8_t uv) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AHB_LSEL, yy); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AHB_FSEL, yy); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AHB_LSEL, uv); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AHB_FSEL, uv); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); +} + +/****************************************************************************/ /** + * @brief Deinit mjpeg module + * + * @param None + * + * @return None + * +*******************************************************************************/ +void MJPEG_Deinit(void) +{ + //GLB_AHB_Slave2_Reset(BL_AHB_SLAVE2_MJPEG); +} + +/****************************************************************************/ /** + * @brief Enable mjpeg module + * + * @param None + * + * @return None + * +*******************************************************************************/ +void MJPEG_Enable(void) +{ + uint32_t tmpVal; + + /* Enable mjpeg module */ + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable mjpeg module + * + * @param None + * + * @return None + * +*******************************************************************************/ +void MJPEG_Disable(void) +{ + uint32_t tmpVal; + + /* Disable mjpeg module */ + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); +} + +/****************************************************************************/ /** + * @brief Enable&disable mjpeg software mode and set frame count + * + * @param count: Frame count + * + * @return None + * +*******************************************************************************/ +void MJPEG_SW_Enable(uint8_t count) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_FRAME, count); + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); +} + +/****************************************************************************/ /** + * @brief MJPEG software mode run, software mode enable first + * + * @param None + * + * @return None + * +*******************************************************************************/ +void MJPEG_SW_Run(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); +} + +/****************************************************************************/ /** + * @brief Get one mjpeg frame + * + * @param info: Mjpeg frame infomation pointer + * + * @return None + * +*******************************************************************************/ +void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); + + info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, MJPEG_FRAME_VALID_CNT); + info->curFrameAddr = BL_RD_REG(MJPEG_BASE, MJPEG_START_ADDR0); + info->curFrameBytes = (BL_RD_REG(MJPEG_BASE, MJPEG_BIT_CNT0) + 7) >> 3; + info->curFrameQ = BL_RD_REG(MJPEG_BASE, MJPEG_Q_MODE0) & 0x3f; + info->status = tmpVal; +} + +/****************************************************************************/ /** + * @brief Get available count of frames + * + * @param None + * + * @return Frames count + * +*******************************************************************************/ +uint8_t MJPEG_Get_Frame_Count(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3), MJPEG_FRAME_VALID_CNT); +} + +/****************************************************************************/ /** + * @brief Pop one mjpeg frame + * + * @param None + * + * @return None + * +*******************************************************************************/ +void MJPEG_Pop_Frame(void) +{ + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 1); +} + +/****************************************************************************/ /** + * @brief Free current read memory block + * + * @param None + * + * @return None + * +*******************************************************************************/ +void MJPEG_Current_Block_Clear(void) +{ + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2); +} + +/****************************************************************************/ /** + * @brief Current read memory block index + * + * @param None + * + * @return Block number + * +*******************************************************************************/ +MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_READ_SWAP_IDX); +} + +/****************************************************************************/ /** + * @brief Get block status, full or not full + * + * @param block: Block number + * + * @return Block status + * +*******************************************************************************/ +BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block) +{ + CHECK_PARAM(IS_MJPEG_SWAP_BLOCK_TYPE(block)); + + if (MJPEG_BLOCK_0 == block) { + return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP0_FULL); + } else { + return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP1_FULL); + } +} + +/****************************************************************************/ /** + * @brief Current read memory block is frame start + * + * @param None + * + * @return Set or reset + * +*******************************************************************************/ +BL_Sts_Type MJPEG_Current_Block_Is_Start(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FSTART); +} + +/****************************************************************************/ /** + * @brief Current read memory block is frame end + * + * @param None + * + * @return Set or reset + * +*******************************************************************************/ +BL_Sts_Type MJPEG_Current_Block_Is_End(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FEND); +} + +/****************************************************************************/ /** + * @brief Get frame remain bit count in last block, only valid when current read memory block is + * frame end + * + * @param None + * + * @return Bit count + * +*******************************************************************************/ +uint32_t MJPEG_Get_Remain_Bit(void) +{ + return BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_BIT_CNT); +} + +/****************************************************************************/ /** + * @brief Set frame threshold to issue normal interrupt + * + * @param count: Frame threshold + * + * @return None + * +*******************************************************************************/ +void MJPEG_Set_Frame_Threshold(uint8_t count) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_CNT_TRGR_INT, count); + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal); +} + +/****************************************************************************/ /** + * @brief MJPEG Enable Disable Interrupt + * + * @param intType: MJPEG Interrupt Type + * @param intMask: Enable or Disable + * + * @return None + * +*******************************************************************************/ +void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); + + switch (intType) { + case MJPEG_INT_NORMAL: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); + } + + break; + + case MJPEG_INT_CAM_OVERWRITE: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); + } + + break; + + case MJPEG_INT_MEM_OVERWRITE: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); + } + + break; + + case MJPEG_INT_FRAME_OVERWRITE: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); + } + + break; + + case MJPEG_INT_BACK_IDLE: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); + } + + break; + + case MJPEG_INT_SWAP: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); + } else { + /* Disable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); + } + + break; + + case MJPEG_INT_ALL: + if (intMask == UNMASK) { + /* Enable all interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); + } else { + /* Disable all interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); + } + + break; + + default: + break; + } + + BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal); +} + +/****************************************************************************/ /** + * @brief MJPEG Interrupt Clear + * + * @param intType: MJPEG Interrupt Type + * + * @return None + * +*******************************************************************************/ +void MJPEG_IntClr(MJPEG_INT_Type intType) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP); + + switch (intType) { + case MJPEG_INT_NORMAL: + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_CLR); + break; + + case MJPEG_INT_CAM_OVERWRITE: + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_CLR); + break; + + case MJPEG_INT_MEM_OVERWRITE: + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_CLR); + break; + + case MJPEG_INT_FRAME_OVERWRITE: + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_CLR); + break; + + case MJPEG_INT_BACK_IDLE: + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_CLR); + break; + + case MJPEG_INT_SWAP: + tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_CLR); + break; + + case MJPEG_INT_ALL: + tmpVal = 0x3F00; + + default: + break; + } + + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, tmpVal); +} + +/****************************************************************************/ /** + * @brief Install mjpeg interrupt callback function + * + * @param intType: MJPEG interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); + + mjpegIntCbfArra[intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief Mjpeg interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void MJPEG_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); + + if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_NORMAL_INT)) { + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x100); + + if (mjpegIntCbfArra[MJPEG_INT_NORMAL] != NULL) { + /* call the callback function */ + mjpegIntCbfArra[MJPEG_INT_NORMAL](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_CAM_INT)) { + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x200); + + if (mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE] != NULL) { + /* call the callback function */ + mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_MEM_INT)) { + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x400); + + if (mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE] != NULL) { + /* call the callback function */ + mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_FRAME_INT)) { + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x800); + + if (mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE] != NULL) { + /* call the callback function */ + mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_IDLE_INT)) { + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x1000); + + if (mjpegIntCbfArra[MJPEG_INT_BACK_IDLE] != NULL) { + /* call the callback function */ + mjpegIntCbfArra[MJPEG_INT_BACK_IDLE](); + } + } + + if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_SWAP_INT)) { + BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2000); + + if (mjpegIntCbfArra[MJPEG_INT_SWAP] != NULL) { + /* call the callback function */ + mjpegIntCbfArra[MJPEG_INT_SWAP](); + } + } +} +#endif + +/*@} end of group MJPEG_Public_Functions */ + +/*@} end of group MJPEG */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pds.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pds.c new file mode 100644 index 0000000000000000000000000000000000000000..e0b073dbc255fdbece93e7c611f86504c6265a23 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pds.c @@ -0,0 +1,1335 @@ +/** + ****************************************************************************** + * @file bl702_pds.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702.h" +#include "bl702_pds.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Private_Macros + * @{ + */ + +/*@} end of group PDS_Private_Macros */ + +/** @defgroup PDS_Private_Types + * @{ + */ + +/*@} end of group PDS_Private_Types */ + +/** @defgroup PDS_Private_Variables + * @{ + */ +static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX][1] = { { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL } }; + +/*@} end of group PDS_Private_Variables */ + +/** @defgroup PDS_Global_Variables + * @{ + */ + +/*@} end of group PDS_Global_Variables */ + +/** @defgroup PDS_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PDS_Private_Fun_Declaration */ + +/** @defgroup PDS_Private_Functions + * @{ + */ + +/*@} end of group PDS_Private_Functions */ + +/** @defgroup PDS_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief power down sleep ram configure + * + * @param ramCfg: power down sleep force ram configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg) +{ + if (NULL == ramCfg) { + return ERROR; + } + + /* PDS_RAM1 config */ + BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep set pad configure + * + * @param pin: power down sleep pad num + * @param cfg: power down sleep pad type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg) +{ + uint32_t tmpVal = 0; + uint32_t tmpPu = 0; + uint32_t tmpPd = 0; + + if (pin < PDS_PAD_PIN_GPIO_23) { + /* GPIO17 - GPIO22 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD); + + switch (cfg) { + case PDS_PAD_CFG_PULL_NONE: + tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin); + tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin); + break; + + case PDS_PAD_CFG_PULL_DOWN: + tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin); + tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin); + break; + + case PDS_PAD_CFG_PULL_UP: + tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin); + tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin); + break; + + case PDS_PAD_CFG_ACTIVE_IE: + tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin); + tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD, tmpPd); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU, tmpPu); + BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal); + } else { + /* GPIO23 - GPIO28 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD); + + switch (cfg) { + case PDS_PAD_CFG_PULL_NONE: + tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23)); + tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23)); + break; + + case PDS_PAD_CFG_PULL_DOWN: + tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23)); + tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23)); + break; + + case PDS_PAD_CFG_PULL_UP: + tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23)); + tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23)); + break; + + case PDS_PAD_CFG_ACTIVE_IE: + tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23)); + tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23)); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD, tmpPd); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU, tmpPu); + BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable power down sleep + * + * @param cfg: power down sleep configuration 1 + * @param cfg4: power down sleep configuration 2 + * @param pdsSleepCnt: power down sleep count cycle + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt) +{ + /* PDS sleep time 0 <=> sleep forever */ + /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */ + /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */ + if (!pdsSleepCnt) { + cfg->sleepForever = 0; + } else if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) { + return ERROR; + } else { + BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT); + } + + /* PDS_CTL4 config */ + BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4); + + /* PDS_CTL config */ + if (cfg->pdsStart) { + BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0))); + BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0))); + } else { + BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep force configure + * + * @param cfg2: power down sleep force configuration 1 + * @param cfg3: power down sleep force configuration 2 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3) +{ + /* PDS_CTL2 config */ + BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2); + + /* PDS_CTL3 config */ + BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep force configure + * + * @param defaultLvCfg: power down sleep default level configuration + * @param pdsSleepCnt: power down sleep time count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt) +{ + PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3)); + PDS_App_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep int enable + * + * @param intType: PDS int type + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable) +{ + uint32_t offset = 0; + uint32_t tmpVal = 0; + + if ((intType < PDS_INT_PDS_SLEEP_CNT) || (intType > PDS_INT_KYS_QDEC)) { + return ERROR; + } + + switch (intType) { + case PDS_INT_WAKEUP: + case PDS_INT_RF_DONE: + case PDS_INT_PLL_DONE: + return ERROR; + + case PDS_INT_PDS_SLEEP_CNT: + offset = 16; + break; + + case PDS_INT_HBN_IRQ_OUT0: + offset = 17; + break; + + case PDS_INT_HBN_IRQ_OUT1: + offset = 18; + break; + + case PDS_INT_GPIO_IRQ: + offset = 19; + break; + + case PDS_INT_IRRX: + offset = 20; + break; + + case PDS_INT_BLE_SLP_IRQ: + offset = 21; + break; + + case PDS_INT_USB_WKUP: + offset = 22; + break; + + case PDS_INT_KYS_QDEC: + offset = 23; + break; + + case PDS_INT_MAX: + break; + + default: + break; + } + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + + if (enable) { + tmpVal = tmpVal | (1 << offset); + } else { + tmpVal = tmpVal & ~(1 << offset); + } + + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep int mask + * + * @param intType: PDS int type + * @param intMask: MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t offset = 0; + uint32_t tmpVal = 0; + + if (intType > PDS_INT_PLL_DONE) { + return ERROR; + } + + switch (intType) { + case PDS_INT_WAKEUP: + offset = 8; + break; + + case PDS_INT_RF_DONE: + offset = 10; + break; + + case PDS_INT_PLL_DONE: + offset = 11; + break; + + case PDS_INT_PDS_SLEEP_CNT: + case PDS_INT_HBN_IRQ_OUT0: + case PDS_INT_HBN_IRQ_OUT1: + case PDS_INT_GPIO_IRQ: + case PDS_INT_IRRX: + case PDS_INT_BLE_SLP_IRQ: + case PDS_INT_USB_WKUP: + case PDS_INT_KYS_QDEC: + case PDS_INT_MAX: + default: + return ERROR; + } + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + + if (intMask != UNMASK) { + tmpVal = tmpVal | (1 << offset); + } else { + tmpVal = tmpVal & ~(1 << offset); + } + + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep int status + * + * @param intType: PDS int type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType) +{ + uint32_t offset = 0; + + switch (intType) { + case PDS_INT_WAKEUP: + offset = 0; + break; + + case PDS_INT_RF_DONE: + offset = 2; + break; + + case PDS_INT_PLL_DONE: + offset = 3; + break; + + case PDS_INT_PDS_SLEEP_CNT: + offset = 24; + break; + + case PDS_INT_HBN_IRQ_OUT0: + offset = 25; + break; + + case PDS_INT_HBN_IRQ_OUT1: + offset = 26; + break; + + case PDS_INT_GPIO_IRQ: + offset = 27; + break; + + case PDS_INT_IRRX: + offset = 28; + break; + + case PDS_INT_BLE_SLP_IRQ: + offset = 29; + break; + + case PDS_INT_USB_WKUP: + offset = 30; + break; + + case PDS_INT_KYS_QDEC: + offset = 31; + break; + + case PDS_INT_MAX: + break; + + default: + break; + } + + return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << offset)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief clear power down sleep int status + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_IntClear(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep PLL status + * + * @param None + * + * @return PDS PLL status + * +*******************************************************************************/ +PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void) +{ + return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE); +} + +/****************************************************************************/ /** + * @brief get power down sleep RF status + * + * @param None + * + * @return PDS RF status + * +*******************************************************************************/ +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void) +{ + return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE); +} + +/****************************************************************************/ /** + * @brief get power down sleep status + * + * @param None + * + * @return PDS status + * +*******************************************************************************/ +PDS_STS_Type PDS_Get_PdsStstus(void) +{ + return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE); +} + +/****************************************************************************/ /** + * @brief power down sleep clear reset event + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_Clear_Reset_Event(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep reset event + * + * @param event: power down sleep reset event + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_RESET_EVENT); + + return (tmpVal & (1 << event)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief set power down sleep VDDCORE gpio interrupt config + * + * @param src: PDS VDDCORE src pin num + * @param mode: PDS VDDCORE src pin interrupt type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src, PDS_AON_GPIO_INT_Trigger_Type mode) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_PDS_VDDCORE_GPIO_SRC_TYPE(src)); + CHECK_PARAM(IS_PDS_AON_GPIO_INT_Trigger_TYPE(mode)); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, src); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, mode); + BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set power down sleep VDDCORE gpio interrupt mask + * + * @param intMask: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); + + if (intMask != UNMASK) { + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_MASK); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK); + } + + BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set power down sleep VDDCORE gpio interrupt mask + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +PDS_STS_Type PDS_Get_Vddcore_GPIO_IntStatus(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_STAT) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief set power down sleep VDDCORE gpio interrupt mask + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Install PDS interrupt callback function + * + * @param intType: PDS int type + * @param cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun) +{ + pdsIntCbfArra[intType][0] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Trim RC32M + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void) +{ + Efuse_Ana_RC32M_Trim_Type trim; + int32_t tmpVal = 0; + + EF_Ctrl_Read_RC32M_Trim(&trim); + + if (trim.trimRc32mExtCodeEn) { + if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) { + tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN); + BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal); + BL702_Delay_US(2); + return SUCCESS; + } + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Select RC32M as PLL ref source + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Select XTAL as PLL ref source + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on PLL + * + * @param xtalType: xtal type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType) +{ + uint32_t tmpVal = 0; + + /* Check parameter*/ + CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType)); + + /**************************/ + /* select PLL XTAL source */ + /**************************/ + + if ((xtalType == PDS_PLL_XTAL_RC32M) || (xtalType == PDS_PLL_XTAL_NONE)) { + PDS_Trim_RC32M(); + PDS_Select_RC32M_As_PLL_Ref(); + } else { + PDS_Select_XTAL_As_PLL_Ref(); + } + + /*******************************************/ + /* PLL power down first, not indispensable */ + /*******************************************/ + /* power off PLL first, this step is not indispensable */ + PDS_Power_Off_PLL(); + + /********************/ + /* PLL param config */ + /********************/ + + /* clkpll_icp_1u */ + /* clkpll_icp_5u */ + /* clkpll_int_frac_sw */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 0); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_CP, tmpVal); + + /* clkpll_c3 */ + /* clkpll_cz */ + /* clkpll_rz */ + /* clkpll_r4 */ + /* clkpll_r4_short */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4, 2); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_RZ, tmpVal); + + /* clkpll_refdiv_ratio */ + /* clkpll_postdiv */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 0x14); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 2); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal); + + /* clkpll_sdmin */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal); + + /* clkpll_sel_fb_clk */ + /* clkpll_sel_sample_clk can be 0/1, default is 1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_FBDV); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_FB_CLK, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_SAMPLE_CLK, 1); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_FBDV, tmpVal); + + /*************************/ + /* PLL power up sequence */ + /*************************/ + + /* pu_clkpll_sfreg=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + BL702_Delay_US(5); + + /* pu_clkpll=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + /* clkpll_pu_cp=1 */ + /* clkpll_pu_pfd=1 */ + /* clkpll_pu_fbdv=1 */ + /* clkpll_pu_postdiv=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + BL702_Delay_US(5); + + /* clkpll_sdm_reset=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + BL702_Delay_US(1); + /* clkpll_reset_fbdv=1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + BL702_Delay_US(2); + /* clkpll_reset_fbdv=0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + BL702_Delay_US(1); + /* clkpll_sdm_reset=0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + return SUCCESS; +} +#endif +/** PLL output config **/ +/* +[8] 1'h0 r/w clkpll_en_32m +[7] 1'h0 r/w clkpll_en_48m +[6] 1'h0 r/w clkpll_en_80m +[5] 1'h0 r/w clkpll_en_96m +[4] 1'h0 r/w clkpll_en_120m +[3] 1'h0 r/w clkpll_en_160m +[2] 1'h0 r/w clkpll_en_192m +[1] 1'h0 r/w clkpll_en_240m +[0] 1'h0 r/w clkpll_en_480m +*/ + +/****************************************************************************/ /** + * @brief Enable all PLL clock + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN); + tmpVal |= 0x1FF; + BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Disable all PLL clock + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN); + tmpVal &= (~0x1FF); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Enable PLL clock + * + * @param pllClk: PLL clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + uint32_t tmpVal = 0; + + /* Check parameter*/ + CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk)); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN); + tmpVal |= (1 << pllClk); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Disable PLL clock + * + * @param pllClk: PLL clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + uint32_t tmpVal = 0; + + /* Check parameter*/ + CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk)); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN); + tmpVal &= (~(1 << pllClk)); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off PLL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void) +{ + uint32_t tmpVal = 0; + + /* pu_clkpll_sfreg=0 */ + /* pu_clkpll=0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + /* clkpll_pu_cp=0 */ + /* clkpll_pu_pfd=0 */ + /* clkpll_pu_fbdv=0 */ + /* clkpll_pu_postdiv=0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set Audio PLL clock + * + * @param audioPLLFreq: Audio PLL sel frequency , have two vaild input 12.288 or 11.289 MHZ + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq) +{ + uint32_t sdmin_table[] = { 0x374BC6, 0x32CCED, 0x32CCED, 0x6E978D, 0x6C0000 }; + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_PDS_AUDIO_PLL_TYPE(audioPLLFreq)); + + /*set PDS_CLKPLL_REFDIV_RATIO as 0x2 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 0x2); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal); + + /*set clkpll_sdmin as sdmin*/ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, (uint32_t)sdmin_table[audioPLLFreq % (sizeof(sdmin_table) / sizeof(sdmin_table[0]))]); + + BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal); + + /*reset pll */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL_SFREG, 1); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + BL702_Delay_MS(10); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL, 1); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 1); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + BL702_Delay_MS(10); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 0); + BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); + + /*set div for audio pll */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL); + + if (audioPLLFreq != AUDIO_PLL_5644800_HZ) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 36); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 72); + } + + BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief PDS software reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Reset(void) +{ + uint32_t tmpVal = 0; + + tmpVal = *(uint32_t *)0x40000010; + tmpVal = tmpVal | (1 << 14); + *(uint32_t *)0x40000010 = tmpVal; + + tmpVal = *(uint32_t *)0x40000010; + tmpVal = tmpVal & ~(1 << 14); + *(uint32_t *)0x40000010 = tmpVal; +} +#endif + +/****************************************************************************/ /** + * @brief Enable power down sleep + * + * @param cfg: power down sleep configuration 1 + * @param pdsSleepCnt: power down sleep count cycle + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt) +{ + uint32_t *p = (uint32_t *)cfg; + + if (pdsSleepCnt - PDS_WARMUP_CNT <= 0) { + return; + } + + BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_CNT); + + /* Set PDS control register */ + BL_WR_REG(PDS_BASE, PDS_CTL, *p); +} +#endif + +/****************************************************************************/ /** + * @brief PDS Auto mode wake up counter config + * + * @param sleepDuration: sleep time, total pds = sleep_duration + max_warmup_cnt (32K clock cycles), + * recommend maxWarmCnt*N+2 + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Auto_Time_Config(uint32_t sleepDuration) +{ + /* PDS_TIME1 */ + BL_WR_REG(PDS_BASE, PDS_TIME1, sleepDuration); +} +#endif + +/****************************************************************************/ /** + * @brief PDS Auto mode config and enable + * + * @param powerCfg: PDS Auto mode power domain config + * @param normalCfg: PDS Auto mode power normal config + * @param enable: PDS Auto mode Enable or Disable + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable) +{ + uint32_t pdsCtl = 0; + + CHECK_PARAM(IS_PDS_LDO_VOLTAGE_TYPE(normalCfg->vddcoreVol)); + + /* power config */ + pdsCtl |= (powerCfg->mbgPower << 31) | + (powerCfg->ldo18rfPower << 30) | + (powerCfg->sfregPower << 29) | + (powerCfg->pllPower << 28) | + (powerCfg->cpu0Power << 19) | + (powerCfg->rc32mPower << 17) | + (powerCfg->xtalPower << 14) | + (powerCfg->allPower << 13) | + (powerCfg->isoPower << 11) | + (powerCfg->bzPower << 10) | + (powerCfg->sramDisStanby << 9) | + (powerCfg->cgPower << 8) | + (powerCfg->cpu1Power << 7) | + (powerCfg->usbPower << 3); + pdsCtl = BL_SET_REG_BITS_VAL(pdsCtl, PDS_CR_PDS_LDO_VOL, normalCfg->vddcoreVol); + pdsCtl |= (normalCfg->vddcoreVolEn << 18) | + (normalCfg->cpu0NotNeedWFI << 21) | + (normalCfg->cpu1NotNeedWFI << 20) | + (normalCfg->busReset << 16) | + (normalCfg->disIrqWakeUp << 15) | + (normalCfg->powerOffXtalForever << 2) | + (normalCfg->sleepForever << 1); + BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl); + + pdsCtl = BL_RD_REG(PDS_BASE, PDS_CTL); + + if (enable) { + pdsCtl |= (1 << 0); + } else { + pdsCtl &= ~(1 << 0); + } + + BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl); +} +#endif + +/****************************************************************************/ /** + * @brief PDS force turn off XXX domain + * + * @param domain: PDS domain + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain) +{ + uint32_t tmpVal = 0; + + /* memory sleep */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal |= 1 << (domain + PDS_FORCE_MEM_STBY_OFFSET); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* gate clock */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal |= 1 << (domain + PDS_FORCE_GATE_CLK_OFFSET); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* pds reset */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal |= 1 << (domain + PDS_FORCE_PDS_RST_OFFSET); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* isolation on */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal |= 1 << (domain + PDS_FORCE_ISO_EN_OFFSET); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* power off */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal |= 1 << (domain + PDS_FORCE_PWR_OFF_OFFSET); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief PDS force turn on XXX domain + * + * @param domain: PDS domain + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain) +{ + uint32_t tmpVal = 0; + + /* power on */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_PWR_OFF_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* isolation off */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_ISO_EN_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* pds de_reset */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_PDS_RST_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* memory active */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_MEM_STBY_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* clock on */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_GATE_CLK_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Power down sleep wake up interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +void PDS_WAKEUP_IRQHandler(void) +{ + for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) { + if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType][0] != NULL)) { + pdsIntCbfArra[intType][0](); + } + } + PDS_Set_Vddcore_GPIO_IntClear(); + PDS_IntClear(); +} + +/****************************************************************************/ /** + * @brief PDS wakeup IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void) +{ + Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler); + return SUCCESS; +} + +/*@} end of group PDS_Public_Functions */ + +/*@} end of group PDS */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_psram.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_psram.c new file mode 100644 index 0000000000000000000000000000000000000000..935563e389bebd6f2e096726c26da0b0229f59b1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_psram.c @@ -0,0 +1,764 @@ +/** + ****************************************************************************** + * @file bl702_psram.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_psram.h" +#include "bl702_l1c.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup PSRAM + * @{ + */ + +/** @defgroup PSRAM_Private_Macros + * @{ + */ + +/*@} end of group PSRAM_Private_Macros */ + +/** @defgroup PSRAM_Private_Types + * @{ + */ + +/*@} end of group PSRAM_Private_Types */ + +/** @defgroup PSRAM_Private_Variables + * @{ + */ + +/*@} end of group PSRAM_Private_Variables */ + +/** @defgroup PSRAM_Global_Variables + * @{ + */ + +/*@} end of group PSRAM_Global_Variables */ + +/** @defgroup PSRAM_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PSRAM_Private_Fun_Declaration */ + +/** @defgroup PSRAM_Private_Functions + * @{ + */ + +/*@} end of group PSRAM_Private_Functions */ + +/** @defgroup PSRAM_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Init serial psram control interface + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param cmdsCfg: Serial Serial Flash controller configuration pointer + * @param sfCtrlPsramCfg: Serial psram controller configuration pointer + * + * @return None + * +*******************************************************************************/ +//#ifndef BFLB_USE_ROM_DRIVER +//__WEAK +void ATTR_TCM_SECTION Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) +{ + SF_Ctrl_Psram_Init(sfCtrlPsramCfg); + SF_Ctrl_Cmds_Set(cmdsCfg); + + Psram_SetDriveStrength(psramCfg); + Psram_SetBurstWrap(psramCfg); +} +//#endif + +/****************************************************************************/ /** + * @brief Read psram register + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param regValue: Register value pointer to store data + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) +{ + /* Check the parameters */ + CHECK_PARAM(IS_PSRAM_CTRL_MODE(psramCfg->ctrlMode)); + + uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type psramCmd; + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + if (psramCfg->ctrlMode == PSRAM_QPI_CTRL_MODE) { + psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + } + + psramCmd.cmdBuf[0] = (psramCfg->readRegCmd) << 24; + psramCmd.rwFlag = SF_CTRL_READ; + psramCmd.addrSize = 3; + psramCmd.dummyClks = psramCfg->readRegDmyClk; + psramCmd.nbData = 1; + + SF_Ctrl_SendCmd(&psramCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + } + + BL702_MemCpy(regValue, psramCtrlBuf, 1); +} +#endif + +/****************************************************************************/ /** + * @brief Write psram register + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param regValue: Register value pointer storing data + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) +{ + /* Check the parameters */ + CHECK_PARAM(IS_PSRAM_CTRL_MODE(psramCfg->ctrlMode)); + + uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type psramCmd; + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + BL702_MemCpy(psramCtrlBuf, regValue, 1); + + if (psramCfg->ctrlMode == PSRAM_QPI_CTRL_MODE) { + psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + } + + psramCmd.cmdBuf[0] = (psramCfg->writeRegCmd) << 24; + psramCmd.rwFlag = SF_CTRL_WRITE; + psramCmd.addrSize = 3; + psramCmd.nbData = 1; + + SF_Ctrl_SendCmd(&psramCmd); +} +#endif + +/****************************************************************************/ /** + * @brief Set psram driver strength + * + * @param psramCfg: Serial psram parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg) +{ + uint32_t stat = 0; + /* Check the parameters */ + CHECK_PARAM(IS_PSRAM_DRIVE_STRENGTH(psramCfg->driveStrength)); + + Psram_ReadReg(psramCfg, (uint8_t *)&stat); + + if ((stat & 0x3) == psramCfg->driveStrength) { + return SUCCESS; + } + + stat &= (~0x3); + stat |= psramCfg->driveStrength; + + Psram_WriteReg(psramCfg, (uint8_t *)&stat); + /* Wait for write done */ + + Psram_ReadReg(psramCfg, (uint8_t *)&stat); + + if ((stat & 0x3) == psramCfg->driveStrength) { + return SUCCESS; + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Set psram burst wrap size + * + * @param psramCfg: Serial psram parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg) +{ + uint32_t stat = 0; + /* Check the parameters */ + CHECK_PARAM(IS_PSRAM_BURST_LENGTH(psramCfg->burstLength)); + + Psram_ReadReg(psramCfg, (uint8_t *)&stat); + + if (((stat >> 5) & 0x3) == psramCfg->burstLength) { + return SUCCESS; + } + + stat &= (~(0x3 << 5)); + stat |= (psramCfg->burstLength << 5); + + Psram_WriteReg(psramCfg, (uint8_t *)&stat); + /* Wait for write done */ + + Psram_ReadReg(psramCfg, (uint8_t *)&stat); + + if (((stat >> 5) & 0x3) == psramCfg->burstLength) { + return SUCCESS; + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Get psram ID + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param data: Data pointer to store read data + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data) +{ + uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type psramCmd; + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + psramCmd.cmdBuf[0] = (psramCfg->readIdCmd) << 24; + psramCmd.rwFlag = SF_CTRL_READ; + psramCmd.addrSize = 3; + psramCmd.dummyClks = psramCfg->readIdDmyClk; + psramCmd.nbData = 8; + + SF_Ctrl_SendCmd(&psramCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + } + + BL702_MemCpy(data, psramCtrlBuf, 8); +} +#endif + +/****************************************************************************/ /** + * @brief Psram enter quad mode + * + * @param psramCfg: Serial psram parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg) +{ + SF_Ctrl_Cmd_Cfg_Type psramCmd; + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + psramCmd.cmdBuf[0] = (psramCfg->enterQuadModeCmd) << 24; + psramCmd.rwFlag = SF_CTRL_READ; + + SF_Ctrl_SendCmd(&psramCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Psram exit quad mode + * + * @param psramCfg: Serial psram parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg) +{ + SF_Ctrl_Cmd_Cfg_Type psramCmd; + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + + psramCmd.cmdBuf[0] = (psramCfg->exitQuadModeCmd) << 24; + psramCmd.rwFlag = SF_CTRL_READ; + + SF_Ctrl_SendCmd(&psramCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Psram toggle burst length + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param ctrlMode: Psram ctrl mode type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) +{ + SF_Ctrl_Cmd_Cfg_Type psramCmd; + /* Check the parameters */ + CHECK_PARAM(IS_PSRAM_CTRL_MODE(ctrlMode)); + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + if (ctrlMode == PSRAM_QPI_CTRL_MODE) { + psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + } + + psramCmd.cmdBuf[0] = (psramCfg->burstToggleCmd) << 24; + psramCmd.rwFlag = SF_CTRL_READ; + + SF_Ctrl_SendCmd(&psramCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Psram software reset + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param ctrlMode: Psram ctrl mode type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) +{ + SF_Ctrl_Cmd_Cfg_Type psramCmd; + /* Check the parameters */ + CHECK_PARAM(IS_PSRAM_CTRL_MODE(ctrlMode)); + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + if (ctrlMode == PSRAM_QPI_CTRL_MODE) { + psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + } + + /* Reset enable */ + psramCmd.cmdBuf[0] = (psramCfg->resetEnableCmd) << 24; + /* rwFlag don't care */ + psramCmd.rwFlag = SF_CTRL_READ; + /* Wait for write done */ + + SF_Ctrl_SendCmd(&psramCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + } + + /* Reset */ + psramCmd.cmdBuf[0] = (psramCfg->resetCmd) << 24; + /* rwFlag don't care */ + psramCmd.rwFlag = SF_CTRL_READ; + SF_Ctrl_SendCmd(&psramCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + } + + BL702_Delay_US(50); + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Psram set IDbus config + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param ioMode: Psram ctrl mode type + * @param addr: Address to read/write + * @param len: Data length to read/write + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, + SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len) +{ + uint8_t cmd, dummyClks; + SF_Ctrl_Cmd_Cfg_Type psramCmd; + uint8_t cmdValid = 1; + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode)); + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); + + /* read mode cache set */ + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + if (SF_CTRL_NIO_MODE == ioMode) { + cmd = psramCfg->fReadCmd; + dummyClks = psramCfg->fReadDmyClk; + } else if (SF_CTRL_QIO_MODE == ioMode) { + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = psramCfg->fReadQuadCmd; + dummyClks = psramCfg->fReadQuadDmyClk; + } else { + return ERROR; + } + + /* prepare command */ + psramCmd.rwFlag = SF_CTRL_READ; + psramCmd.addrSize = 3; + psramCmd.cmdBuf[0] = (cmd << 24) | addr; + psramCmd.dummyClks = dummyClks; + psramCmd.nbData = len; + SF_Ctrl_Psram_Read_Icache_Set(&psramCmd, cmdValid); + + /* write mode cache set */ + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + if (SF_CTRL_NIO_MODE == ioMode) { + cmd = psramCfg->writeCmd; + } else if (SF_CTRL_QIO_MODE == ioMode) { + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = psramCfg->quadWriteCmd; + } else { + return ERROR; + } + + dummyClks = 0; + + /* prepare command */ + psramCmd.rwFlag = SF_CTRL_WRITE; + psramCmd.addrSize = 3; + psramCmd.cmdBuf[0] = (cmd << 24) | addr; + psramCmd.dummyClks = dummyClks; + psramCmd.nbData = len; + SF_Ctrl_Psram_Write_Icache_Set(&psramCmd, cmdValid); + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set cache write to psram with cache + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param ioMode: Psram controller interface mode + * @param wtEn: Psram cache write through enable + * @param wbEn: Psram cache write back enable + * @param waEn: Psram cache write allocate enable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, + BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) +{ + BL_Err_Type stat; + + /* Cache now only support 32 bytes read */ + stat = Psram_Set_IDbus_Cfg(psramCfg, ioMode, 0, 32); + + if (SUCCESS != stat) { + return stat; + } + + L1C_Cache_Write_Set(wtEn, wbEn, waEn); + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Write psram one region + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param ioMode: Write mode: SPI mode or QPI mode + * @param addr: Start address to be write + * @param data: Data pointer to be write + * @param len: Data length to be write + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_Write(SPI_Psram_Cfg_Type *psramCfg, + SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t i = 0, curLen = 0; + uint32_t burstLen = 512; + uint8_t cmd; + SF_Ctrl_Cmd_Cfg_Type psramCmd; + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode)); + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + if (SF_CTRL_NIO_MODE == ioMode) { + cmd = psramCfg->writeCmd; + } else if (SF_CTRL_QIO_MODE == ioMode) { + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = psramCfg->quadWriteCmd; + } else { + return ERROR; + } + + /* Prepare command */ + psramCmd.rwFlag = SF_CTRL_WRITE; + psramCmd.addrSize = 3; + + if (psramCfg->burstLength == PSRAM_BURST_LENGTH_16_BYTES) { + burstLen = 16; + } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_32_BYTES) { + burstLen = 32; + } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_64_BYTES) { + burstLen = 64; + } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_512_BYTES) { + burstLen = 512; + } + + for (i = 0; i < len;) { + /* Get current programmed length within page size */ + curLen = burstLen - addr % burstLen; + + if (curLen > len - i) { + curLen = len - i; + } + + /* Prepare command */ + BL702_MemCpy_Fast(psramCtrlBuf, data, curLen); + psramCmd.cmdBuf[0] = (cmd << 24) | (addr); + psramCmd.nbData = curLen; + + SF_Ctrl_SendCmd(&psramCmd); + + /* Adjust address and programmed length */ + addr += curLen; + i += curLen; + data += curLen; + + /* Wait for write done */ + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Read data from psram + * + * @param psramCfg: Serial psram parameter configuration pointer + * @param ioMode: IoMode: psram controller interface mode + * @param addr: Psram read start address + * @param data: Data pointer to store data read from psram + * @param len: Data length to read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION Psram_Read(SPI_Psram_Cfg_Type *psramCfg, + SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t curLen, i; + uint32_t burstLen = 512; + uint8_t cmd, dummyClks; + SF_Ctrl_Cmd_Cfg_Type psramCmd; + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode)); + + if (((uint32_t)&psramCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); + } else { + BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); + } + + if (SF_CTRL_NIO_MODE == ioMode) { + cmd = psramCfg->fReadCmd; + dummyClks = psramCfg->fReadDmyClk; + } else if (SF_CTRL_QIO_MODE == ioMode) { + psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; + psramCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = psramCfg->fReadQuadCmd; + dummyClks = psramCfg->fReadQuadDmyClk; + } else { + return ERROR; + } + + /* Prepare command */ + psramCmd.rwFlag = SF_CTRL_READ; + psramCmd.addrSize = 3; + psramCmd.dummyClks = dummyClks; + + if (psramCfg->burstLength == PSRAM_BURST_LENGTH_16_BYTES) { + burstLen = 16; + } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_32_BYTES) { + burstLen = 32; + } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_64_BYTES) { + burstLen = 64; + } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_512_BYTES) { + burstLen = 512; + } + + /* Read data */ + for (i = 0; i < len;) { + /* Prepare command */ + psramCmd.cmdBuf[0] = (cmd << 24) | (addr); + curLen = burstLen - addr % burstLen; + + if (curLen > len - i) { + curLen = len - i; + } + + if (curLen >= FLASH_CTRL_BUF_SIZE) { + curLen = FLASH_CTRL_BUF_SIZE; + psramCmd.nbData = curLen; + } else { + /* Make sf_ctrl word read */ + psramCmd.nbData = ((curLen + 3) >> 2) << 2; + } + + SF_Ctrl_SendCmd(&psramCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + } + + BL702_MemCpy_Fast(data, psramCtrlBuf, curLen); + + addr += curLen; + i += curLen; + data += curLen; + } + + return SUCCESS; +} +#endif + +/*@} end of group PSRAM_Public_Functions */ + +/*@} end of group PSRAM */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pwm.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..3e03700be4e5d39fbb74108ae466927ac6bbe9d6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pwm.c @@ -0,0 +1,614 @@ +/** + ****************************************************************************** + * @file bl702_pwm.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_pwm.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup PWM + * @{ + */ + +/** @defgroup PWM_Private_Macros + * @{ + */ +#define PWM_Get_Channel_Reg(ch) (PWM_BASE + PWM_CHANNEL_OFFSET + (ch)*0x20) +#define PWM_INT_TIMEOUT_COUNT (160 * 1000) +#define PWM_STOP_TIMEOUT_COUNT (160 * 1000) + +/*@} end of group PWM_Private_Macros */ + +/** @defgroup PWM_Private_Types + * @{ + */ + +/*@} end of group PWM_Private_Types */ + +/** @defgroup PWM_Private_Variables + * @{ + */ + +/** + * @brief PWM interrupt callback function address array + */ +static intCallback_Type *PWMIntCbfArra[PWM_CH_MAX][PWM_INT_ALL] = { + { NULL } +}; + +/*@} end of group PWM_Private_Variables */ + +/** @defgroup PWM_Global_Variables + * @{ + */ + +/*@} end of group PWM_Global_Variables */ + +/** @defgroup PWM_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph); +#endif + +/*@} end of group PWM_Private_Fun_Declaration */ + +/** @defgroup PWM_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief PWM interrupt handle + * + * @param intPeriph: Select the peripheral, such as PWM0_IRQn + * + * @return SUCCESS + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph) +{ + uint32_t i; + uint32_t tmpVal; + uint32_t timeoutCnt = PWM_INT_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_BASE; + + for (i = 0; i < PWM_CH_MAX; i++) { + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + + if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i)) != 0) { + /* Clear interrupt */ + tmpVal |= (1 << (i + PWM_INT_CLEAR_POS)); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + + /* FIXME: we need set pwm_int_clear to 0 by software and + before this,we must make sure pwm_interrupt_sts is 0*/ + do { + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + timeoutCnt--; + + if (timeoutCnt == 0) { + break; + } + } while (BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i)); + + tmpVal &= (~(1 << (i + PWM_INT_CLEAR_POS))); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + + if (PWMIntCbfArra[i][PWM_INT_PULSE_CNT] != NULL) { + /* Call the callback function */ + PWMIntCbfArra[i][PWM_INT_PULSE_CNT](); + } + } + } + + return SUCCESS; +} +#endif + +/*@} end of group PWM_Private_Functions */ + +/** @defgroup PWM_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief PWM channel init + * + * @param chCfg: PWM configuration + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg) +{ + uint32_t tmpVal; + uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(chCfg->ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(chCfg->ch)); + CHECK_PARAM(IS_PWM_CLK_TYPE(chCfg->clk)); + CHECK_PARAM(IS_PWM_POLARITY_TYPE(chCfg->pol)); + CHECK_PARAM(IS_PWM_STOP_MODE_TYPE(chCfg->stopMode)); + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_PWM); + + /* Config pwm clock and polarity */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + + while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, chCfg->clk); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, chCfg->pol); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, chCfg->stopMode); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, chCfg->clkDiv); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, chCfg->threshold1); + BL_WR_REG(PWMx, PWM_THRE2, chCfg->threshold2); + BL_WR_REG(PWMx, PWM_PERIOD, chCfg->period); + + /* Config interrupt pulse count */ + tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT); + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, chCfg->intPulseCnt)); + PWM_IntMask(chCfg->ch, PWM_INT_PULSE_CNT, chCfg->intPulseCnt != 0 ? UNMASK : MASK); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(PWM_IRQn, PWM_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief PWM channel update source memory address and len + * + * @param ch: PWM channel + * @param period: period + * @param threshold1: threshold1 + * @param threshold2: threshold2 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Update(PWM_CH_ID_Type ch, uint16_t period, uint16_t threshold1, uint16_t threshold2) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, threshold1); + BL_WR_REG(PWMx, PWM_THRE2, threshold2); + BL_WR_REG(PWMx, PWM_PERIOD, period); +} + +/****************************************************************************/ /** + * @brief PWM channel update clock divider + * + * @param ch: PWM channel + * @param div: Clock divider + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Div(PWM_CH_ID_Type ch, uint16_t div) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + BL_WR_REG(PWMx, PWM_CLKDIV, div); +} + +/****************************************************************************/ /** + * @brief PWM channel update threshold1 + * + * @param ch: PWM channel + * @param threshold1: threshold1 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch, uint16_t threshold1) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, threshold1); +} + +/****************************************************************************/ /** + * @brief PWM channel update threshold2 + * + * @param ch: PWM channel + * @param threshold2: threshold2 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch, uint16_t threshold2) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE2, threshold2); +} + +/****************************************************************************/ /** + * @brief PWM channel update period + * + * @param ch: PWM channel + * @param period: period + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Period(PWM_CH_ID_Type ch, uint16_t period) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_PERIOD, period); +} + +/****************************************************************************/ /** + * @brief PWM get configuration + * + * @param ch: PWM channel + * @param period: period pointer + * @param threshold1: threshold1 pointer + * @param threshold2: threshold2 pointer + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Get(PWM_CH_ID_Type ch, uint16_t *period, uint16_t *threshold1, uint16_t *threshold2) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* get pwm period and duty */ + tmpVal = BL_RD_REG(PWMx, PWM_THRE1); + *threshold1 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE1); + tmpVal = BL_RD_REG(PWMx, PWM_THRE2); + *threshold2 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE2); + tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); + *period = BL_GET_REG_BITS_VAL(tmpVal, PWM_PERIOD); +} + +/****************************************************************************/ /** + * @brief PWM enable + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Enable(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm clock to enable pwm */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_CLR_REG_BIT(tmpVal, PWM_STOP_EN)); +} + +/****************************************************************************/ /** + * @brief PWM disable + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Disable(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm clock to disable pwm */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + PWM_IntMask(ch, PWM_INT_PULSE_CNT, MASK); +} + +/****************************************************************************/ /** + * @brief PWM channel software mode enable or disable + * + * @param ch: PWM channel number + * @param enable: Enable or disable + * + * @return None + * +*******************************************************************************/ +void PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, PWM_SW_MODE, enable)); +} + +/****************************************************************************/ /** + * @brief PWM channel force output high or low + * + * @param ch: PWM channel number + * @param value: Output value + * + * @return None + * +*******************************************************************************/ +void PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, PWM_SW_FORCE_VAL, value)); +} + +/****************************************************************************/ /** + * @brief PWM channel force output high + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Fource_Output(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_SW_MODE)); +} + +/****************************************************************************/ /** + * @brief Mask/Unmask the PWM interrupt + * + * @param ch: PWM channel number + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void PWM_IntMask(PWM_CH_ID_Type ch, PWM_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + CHECK_PARAM(IS_PWM_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT); + + switch (intType) { + case PWM_INT_PULSE_CNT: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } else { + /* MASK(Disable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } + + break; + + case PWM_INT_ALL: + if (intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } else { + /* MASK(Disable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief Install PWM interrupt callback function + * + * @param ch: PWM channel number + * @param intType: PWM interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun) +{ + PWMIntCbfArra[ch][intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief PWM smart configure according to frequency and duty cycle function + * + * @param ch: PWM channel number + * @param frequency: PWM frequency + * @param dutyCycle: PWM duty cycle + * + * @return SUCCESS or TIMEOUT + * +*******************************************************************************/ +BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle) +{ + uint32_t tmpVal; + uint16_t clkDiv, period, threshold2; + uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + if (frequency <= 32) { + clkDiv = 500; + period = 64000 / frequency; + threshold2 = 640 * dutyCycle / frequency; + } else if (frequency <= 62) { + clkDiv = 16; + period = 2000000 / frequency; + threshold2 = 20000 * dutyCycle / frequency; + } else if (frequency <= 124) { + clkDiv = 8; + period = 4000000 / frequency; + threshold2 = 40000 * dutyCycle / frequency; + } else if (frequency <= 246) { + clkDiv = 4; + period = 8000000 / frequency; + threshold2 = 80000 * dutyCycle / frequency; + } else if (frequency <= 490) { + clkDiv = 2; + period = 16000000 / frequency; + threshold2 = 160000 * dutyCycle / frequency; + } else { + clkDiv = 1; + period = 32000000 / frequency; + threshold2 = 320000 * dutyCycle / frequency; + } + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + if (BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL) != PWM_CLK_XCLK) { + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) { + timeoutCnt--; + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_XCLK); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, PWM_POL_NORMAL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_GRACEFUL); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, clkDiv); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_PERIOD, period); + BL_WR_REG(PWMx, PWM_THRE1, 0); + BL_WR_REG(PWMx, PWM_THRE2, threshold2); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief PWM interrupt function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void PWM_IRQHandler(void) +{ + PWM_IntHandler(PWM_IRQn); +} +#endif + +/*@} end of group PWM_Public_Functions */ + +/*@} end of group PWM */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_qdec.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_qdec.c new file mode 100644 index 0000000000000000000000000000000000000000..ecce934dc5ff2a8976591a22da5d18b0c4e8ac10 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_qdec.c @@ -0,0 +1,548 @@ +/** + ****************************************************************************** + * @file bl702_qdec.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_qdec.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup QDEC + * @{ + */ + +/** @defgroup QDEC_Private_Macros + * @{ + */ + +/*@} end of group QDEC_Private_Macros */ + +/** @defgroup QDEC_Private_Types + * @{ + */ + +/*@} end of group QDEC_Private_Types */ + +/** @defgroup QDEC_Private_Variables + * @{ + */ +static const uint32_t qdecAddr[QDEC_ID_MAX] = { QDEC0_BASE, QDEC1_BASE, QDEC2_BASE }; +static intCallback_Type *qdecIntCbfArra[QDEC_ID_MAX][QDEC_INT_ALL] = { { NULL, NULL, NULL, NULL }, + { NULL, NULL, NULL, NULL }, + { NULL, NULL, NULL, NULL } }; + +/*@} end of group QDEC_Private_Variables */ + +/** @defgroup QDEC_Global_Variables + * @{ + */ + +/*@} end of group QDEC_Global_Variables */ + +/** @defgroup QDEC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group QDEC_Private_Fun_Declaration */ + +/** @defgroup QDEC_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief QDEC init + * + * @param qdecId: QDEC ID + * @param qdecCfg: QDEC config + * + * @return None + * +*******************************************************************************/ +void QDEC_Init(QDEC_ID_Type qdecId, QDEC_CFG_Type *qdecCfg) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + CHECK_PARAM(IS_QDEC_SAMPLE_MODE_TYPE(qdecCfg->sampleCfg.sampleMod)); + CHECK_PARAM(IS_QDEC_SAMPLE_PERIOD_TYPE(qdecCfg->sampleCfg.samplePeriod)); + CHECK_PARAM(IS_QDEC_REPORT_MODE_TYPE(qdecCfg->reportCfg.reportMod)); + CHECK_PARAM((qdecCfg->ledCfg.ledPeriod) <= 0x1FF); + CHECK_PARAM((qdecCfg->deglitchCfg.deglitchStrength) <= 0xF); + + /* qdec_ctrl */ + tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_PERIOD, qdecCfg->sampleCfg.samplePeriod); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_PERIOD, qdecCfg->reportCfg.reportPeriod); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_EN, qdecCfg->ledCfg.ledEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_POL, qdecCfg->ledCfg.ledSwap); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_EN, qdecCfg->deglitchCfg.deglitchEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_CNT, qdecCfg->deglitchCfg.deglitchStrength); + BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal); + + /* qdec_ctrl1 */ + tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_MODE, qdecCfg->sampleCfg.sampleMod); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_MODE, qdecCfg->reportCfg.reportMod); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_PERIOD, qdecCfg->ledCfg.ledPeriod); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_ACC_MODE, qdecCfg->accMod); + BL_WR_REG(QDECx, QDEC0_CTRL1, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(QDEC0_IRQn, QDEC0_IRQHandler); + Interrupt_Handler_Register(QDEC1_IRQn, QDEC1_IRQHandler); + Interrupt_Handler_Register(QDEC2_IRQn, QDEC2_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief QDEC deinit + * + * @param qdecId: QDEC ID + * + * @return None + * +*******************************************************************************/ +void QDEC_DeInit(QDEC_ID_Type qdecId) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + /* deconfig qdec */ + tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_PERIOD, 10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_PERIOD, 2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_CNT, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_POL, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_EN, 0); + BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal); + tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_PERIOD, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_INPUT_SWAP, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_MODE, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_MODE, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_ACC_MODE, 1); + BL_WR_REG(QDECx, QDEC0_CTRL1, tmpVal); + + /* enable qdec */ + tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_EN, 1); + BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal); + + /* deconfig interrupt */ + tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN, 1); + BL_WR_REG(QDECx, QDEC0_INT_EN, tmpVal); + + /* clear status */ + tmpVal = BL_RD_REG(QDECx, QDEC0_INT_CLR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_CLR, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_CLR, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_CLR, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_CLR, 1); + BL_WR_REG(QDECx, QDEC0_INT_STS, tmpVal); + + /* clear value */ + tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE); + + /* disable qdec */ + tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_EN, 0); + BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal); +} + +/****************************************************************************/ /** + * @brief QDEC enable + * + * @param qdecId: QDEC ID + * + * @return None + * +*******************************************************************************/ +void QDEC_Enable(QDEC_ID_Type qdecId) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + /* qdec_ctrl */ + tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0); + tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_EN); + BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal); +} + +/****************************************************************************/ /** + * @brief QDEC disable + * + * @param qdecId: QDEC ID + * + * @return None + * +*******************************************************************************/ +void QDEC_Disable(QDEC_ID_Type qdecId) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + /* qdec_ctrl */ + tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0); + tmpVal = BL_CLR_REG_BIT(tmpVal, QDEC_EN); + BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal); +} + +/****************************************************************************/ /** + * @brief set QDEC interrupt mask + * + * @param qdecId: QDEC ID + * @param intType: QDEC interrupt type + * @param intMask: MASK or UNMASK + * + * @return None + * +*******************************************************************************/ +void QDEC_SetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + CHECK_PARAM(IS_QDEC_INT_TYPE(intType)); + + /* qdec_int_en */ + tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN); + + switch (intType) { + case QDEC_INT_REPORT: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN, (intMask ? 0 : 1)); + break; + + case QDEC_INT_SAMPLE: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN, (intMask ? 0 : 1)); + break; + + case QDEC_INT_ERROR: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN, (intMask ? 0 : 1)); + break; + + case QDEC_INT_OVERFLOW: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN, (intMask ? 0 : 1)); + break; + + default: + break; + } + + BL_WR_REG(QDECx, QDEC0_INT_EN, tmpVal); +} + +/****************************************************************************/ /** + * @brief get QDEC interrupt mask + * + * @param qdecId: QDEC ID + * @param intType: QDEC interrupt type + * + * @return MASK or UNMASK + * +*******************************************************************************/ +BL_Mask_Type QDEC_GetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + CHECK_PARAM(IS_QDEC_INT_TYPE(intType)); + + /* qdec_int_en */ + tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN); + + switch (intType) { + case QDEC_INT_REPORT: + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN) ? UNMASK : MASK; + + case QDEC_INT_SAMPLE: + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN) ? UNMASK : MASK; + + case QDEC_INT_ERROR: + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN) ? UNMASK : MASK; + + case QDEC_INT_OVERFLOW: + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN) ? UNMASK : MASK; + + default: + return UNMASK; + } +} + +/****************************************************************************/ /** + * @brief QDEC interrupt callback install + * + * @param qdecId: QDEC ID + * @param intType: QDEC interrupt type + * @param cbFun: interrupt callback + * + * @return None + * +*******************************************************************************/ +void QDEC_Int_Callback_Install(QDEC_ID_Type qdecId, QDEC_INT_Type intType, intCallback_Type *cbFun) +{ + qdecIntCbfArra[qdecId][intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief QDEC get interrupt status + * + * @param qdecId: QDEC ID + * @param intType: QDEC interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type QDEC_Get_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + CHECK_PARAM(IS_QDEC_INT_TYPE(intType)); + + /* qdec_int_sts */ + tmpVal = BL_RD_REG(QDECx, QDEC0_INT_STS); + + switch (intType) { + case QDEC_INT_REPORT: + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_STS) ? SET : RESET; + + case QDEC_INT_SAMPLE: + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_STS) ? SET : RESET; + + case QDEC_INT_ERROR: + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_STS) ? SET : RESET; + + case QDEC_INT_OVERFLOW: + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_STS) ? SET : RESET; + + default: + return RESET; + } +} + +/****************************************************************************/ /** + * @brief QDEC clear interrupt status + * + * @param qdecId: QDEC ID + * @param intType: QDEC interrupt type + * + * @return None + * +*******************************************************************************/ +void QDEC_Clr_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + CHECK_PARAM(IS_QDEC_INT_TYPE(intType)); + + /* qdec_int_clr */ + tmpVal = BL_RD_REG(QDECx, QDEC0_INT_CLR); + + switch (intType) { + case QDEC_INT_REPORT: + tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_RPT_RDY_CLR); + break; + + case QDEC_INT_SAMPLE: + tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_SPL_RDY_CLR); + break; + + case QDEC_INT_ERROR: + tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_DBL_RDY_CLR); + break; + + case QDEC_INT_OVERFLOW: + tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_OVERFLOW_CLR); + break; + + default: + break; + } + + BL_WR_REG(QDECx, QDEC0_INT_CLR, tmpVal); +} + +/****************************************************************************/ /** + * @brief QDEC get sample direction + * + * @param qdecId: QDEC ID + * + * @return None + * +*******************************************************************************/ +QDEC_DIRECTION_Type QDEC_Get_Sample_Direction(QDEC_ID_Type qdecId) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + /* qdec_value */ + tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE); + + return (QDEC_DIRECTION_Type)BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_VAL); +} + +/****************************************************************************/ /** + * @brief QDEC get error count + * + * @param qdecId: QDEC ID + * + * @return None + * +*******************************************************************************/ +uint8_t QDEC_Get_Err_Cnt(QDEC_ID_Type qdecId) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + /* qdec_value */ + tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE); + + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_ACC2_VAL); +} + +/****************************************************************************/ /** + * @brief QDEC get sample value + * + * @param qdecId: QDEC ID + * + * @return None + * +*******************************************************************************/ +uint16_t QDEC_Get_Sample_Val(QDEC_ID_Type qdecId) +{ + uint32_t tmpVal = 0; + uint32_t QDECx = qdecAddr[qdecId]; + + /* qdec_value */ + tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE); + + return BL_GET_REG_BITS_VAL(tmpVal, QDEC_ACC1_VAL); +} + +/****************************************************************************/ /** + * @brief QDEC interrupt handler + * + * @param qdecId: QDEC ID + * @param intType: QDEC interrupt type + * + * @return None + * +*******************************************************************************/ +void QDEC_IntHandler(QDEC_ID_Type qdecId, QDEC_INT_Type intType) +{ + if (SET == QDEC_Get_Int_Status(qdecId, intType)) { + QDEC_Clr_Int_Status(qdecId, intType); + + if (qdecIntCbfArra[qdecId][intType] != NULL) { + qdecIntCbfArra[qdecId][intType](); + } + } +} + +/****************************************************************************/ /** + * @brief QDEC0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void QDEC0_IRQHandler(void) +{ + QDEC_INT_Type intType; + + for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) { + if (UNMASK == QDEC_GetIntMask(QDEC0_ID, intType)) { + QDEC_IntHandler(QDEC0_ID, intType); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief QDEC1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void QDEC1_IRQHandler(void) +{ + QDEC_INT_Type intType; + + for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) { + if (UNMASK == QDEC_GetIntMask(QDEC1_ID, intType)) { + QDEC_IntHandler(QDEC1_ID, intType); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief QDEC2 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void QDEC2_IRQHandler(void) +{ + QDEC_INT_Type intType; + + for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) { + if (UNMASK == QDEC_GetIntMask(QDEC2_ID, intType)) { + QDEC_IntHandler(QDEC2_ID, intType); + } + } +} +#endif + +/*@} end of group QDEC_Private_Functions */ + +/*@} end of group QDEC */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romapi.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romapi.c new file mode 100644 index 0000000000000000000000000000000000000000..019fe4653c32923ee166cbe4a3bded617c43f89a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romapi.c @@ -0,0 +1,1106 @@ +#include "bl702_romdriver.h" + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + AON_Power_On_MBG(void) +{ + return RomDriver_AON_Power_On_MBG(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + AON_Power_Off_MBG(void) +{ + return RomDriver_AON_Power_Off_MBG(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + AON_Power_On_XTAL(void) +{ + return RomDriver_AON_Power_On_XTAL(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut) +{ + return RomDriver_AON_Set_Xtal_CapCode(capIn, capOut); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + AON_Power_Off_XTAL(void) +{ + return RomDriver_AON_Power_Off_XTAL(); +} +/******************************************************************************/ + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_TCM_SECTION void ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + RomDriver_ASM_Delay_Us(core, cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_US(uint32_t cnt) +{ + RomDriver_BL702_Delay_US(cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_MS(uint32_t cnt) +{ + RomDriver_BL702_Delay_MS(cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemCpy(void *dst, const void *src, uint32_t n) +{ + return RomDriver_BL702_MemCpy(dst, src, n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint32_t * + BL702_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n) +{ + return RomDriver_BL702_MemCpy4(dst, src, n); +} + +// __ALWAYS_INLINE ATTR_TCM_SECTION +// void* BL702_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) { +// return RomDriver_BL702_MemCpy_Fast(pdst, psrc, n); +// } + +__ALWAYS_INLINE ATTR_TCM_SECTION void *ARCH_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) +{ + return RomDriver_ARCH_MemCpy_Fast(pdst, psrc, n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemSet(void *s, uint8_t c, uint32_t n) +{ + return RomDriver_BL702_MemSet(s, c, n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint32_t * + BL702_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n) +{ + return RomDriver_BL702_MemSet4(dst, val, n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION int BL702_MemCmp(const void *s1, const void *s2, uint32_t n) +{ + return RomDriver_BL702_MemCmp(s1, s2, n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint32_t + BFLB_Soft_CRC32(void *dataIn, uint32_t len) +{ + return RomDriver_BFLB_Soft_CRC32(dataIn, len); +} +/******************************************************************************/ + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_CLOCK_SECTION + GLB_ROOT_CLK_Type + GLB_Get_Root_CLK_Sel(void) +{ + return RomDriver_GLB_Get_Root_CLK_Sel(); +} +#if 0 +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv) +{ + return RomDriver_GLB_Set_System_CLK_Div(hclkDiv, bclkDiv); +} +#endif +__ALWAYS_INLINE ATTR_CLOCK_SECTION + uint8_t + GLB_Get_BCLK_Div(void) +{ + return RomDriver_GLB_Get_BCLK_Div(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + uint8_t + GLB_Get_HCLK_Div(void) +{ + return RomDriver_GLB_Get_HCLK_Div(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType) +{ + return RomDriver_Update_SystemCoreClockWith_XTAL(xtalType); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) +{ + return RomDriver_GLB_Set_System_CLK(xtalType, clkFreq); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + System_Core_Clock_Update_From_RC32M(void) +{ + return RomDriver_System_Core_Clock_Update_From_RC32M(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) +{ + return RomDriver_GLB_Set_SF_CLK(enable, clkSel, div); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Power_Off_DLL(void) +{ + return RomDriver_GLB_Power_Off_DLL(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType) +{ + return RomDriver_GLB_Power_On_DLL(xtalType); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Enable_DLL_All_Clks(void) +{ + return RomDriver_GLB_Enable_DLL_All_Clks(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk) +{ + return RomDriver_GLB_Enable_DLL_Clk(dllClk); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Disable_DLL_All_Clks(void) +{ + return RomDriver_GLB_Disable_DLL_All_Clks(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk) +{ + return RomDriver_GLB_Disable_DLL_Clk(dllClk); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_SW_System_Reset(void) +{ + return RomDriver_GLB_SW_System_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_SW_CPU_Reset(void) +{ + return RomDriver_GLB_SW_CPU_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_SW_POR_Reset(void) +{ + return RomDriver_GLB_SW_POR_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_Select_Internal_Flash(void) +{ + return RomDriver_GLB_Select_Internal_Flash(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_Swap_Flash_Pin(void) +{ + return RomDriver_GLB_Swap_Flash_Pin(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_Swap_Flash_CS_IO2_Pin(void) +{ + return RomDriver_GLB_Swap_Flash_CS_IO2_Pin(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_Swap_Flash_IO0_IO3_Pin(void) +{ + return RomDriver_GLB_Swap_Flash_IO0_IO3_Pin(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_Select_Internal_PSram(void) +{ + return RomDriver_GLB_Select_Internal_PSram(); +} + +/* aon pads GPIO9~GPIO13 IE controlled by HBN reg_aon_pad_ie_smt, abandon romdriver for this reason */ +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) +{ + return RomDriver_GLB_GPIO_Init(cfg); +} +#endif + +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin); +} +#endif + +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin); +} +#endif + +/* aon pads GPIO9~GPIO13 IE controlled by HBN reg_aon_pad_ie_smt, abandon romdriver for this reason */ +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_Set_HZ(gpioPin); +} +#endif + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_Deswap_Flash_Pin(void) +{ + return RomDriver_GLB_Deswap_Flash_Pin(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + GLB_Select_External_Flash(void) +{ + return RomDriver_GLB_Select_External_Flash(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint8_t + GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_Get_Fun(gpioPin); +} +/******************************************************************************/ + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Sts_Type + EF_Ctrl_Busy(void) +{ + return RomDriver_EF_Ctrl_Busy(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Sw_AHB_Clk_0(void) +{ + RomDriver_EF_Ctrl_Sw_AHB_Clk_0(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Load_Efuse_R0(void) +{ + RomDriver_EF_Ctrl_Load_Efuse_R0(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Clear(uint32_t index, uint32_t len) +{ + RomDriver_EF_Ctrl_Clear(index, len); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + uint8_t + EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) +{ + return RomDriver_EF_Ctrl_Get_Trim_Parity(val, len); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) +{ + RomDriver_EF_Ctrl_Read_RC32K_Trim(trim); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) +{ + RomDriver_EF_Ctrl_Read_RC32M_Trim(trim); +} +/******************************************************************************/ + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Trim_RC32M(void) +{ + return RomDriver_PDS_Trim_RC32M(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Select_RC32M_As_PLL_Ref(void) +{ + return RomDriver_PDS_Select_RC32M_As_PLL_Ref(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Select_XTAL_As_PLL_Ref(void) +{ + return RomDriver_PDS_Select_XTAL_As_PLL_Ref(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType) +{ + return RomDriver_PDS_Power_On_PLL(xtalType); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Enable_PLL_All_Clks(void) +{ + return RomDriver_PDS_Enable_PLL_All_Clks(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Disable_PLL_All_Clks(void) +{ + return RomDriver_PDS_Disable_PLL_All_Clks(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + return RomDriver_PDS_Enable_PLL_Clk(pllClk); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + return RomDriver_PDS_Disable_PLL_Clk(pllClk); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + PDS_Power_Off_PLL(void) +{ + return RomDriver_PDS_Power_Off_PLL(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Reset(void) +{ + RomDriver_PDS_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt) +{ + RomDriver_PDS_Enable(cfg, pdsSleepCnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Auto_Time_Config(uint32_t sleepDuration) +{ + RomDriver_PDS_Auto_Time_Config(sleepDuration); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable) +{ + RomDriver_PDS_Auto_Enable(powerCfg, normalCfg, enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain) +{ + RomDriver_PDS_Manual_Force_Turn_Off(domain); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain) +{ + RomDriver_PDS_Manual_Force_Turn_On(domain); +} +/******************************************************************************/ + +/******************************************************************************/ +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + RomDriver_HBN_Enable(aGPIOIeCfg, ldoLevel, hbnLevel); +} +#endif + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + HBN_Reset(void) +{ + return RomDriver_HBN_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask) +{ + return RomDriver_HBN_GPIO_Dbg_Pull_Cfg(pupdEn, dlyEn, dlySec, gpioIrq, gpioMask); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + HBN_Trim_RC32K(void) +{ + return RomDriver_HBN_Trim_RC32K(); +} + +__ALWAYS_INLINE ATTR_CLOCK_SECTION + BL_Err_Type + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) +{ + return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk); +} +/******************************************************************************/ + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) +{ + return RomDriver_XIP_SFlash_State_Save(pFlashCfg, offset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset) +{ + return RomDriver_XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr) +{ + return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg, ioMode, startaddr, endaddr); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg, ioMode, addr, data, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg, ioMode, addr, data, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) +{ + return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg, ioMode, data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) +{ + return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg, ioMode, data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data, uint8_t idLen) +{ + return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg, ioMode, data, idLen); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *dst, int len) +{ + return RomDriver_XIP_SFlash_Read_With_Lock(pFlashCfg, ioMode, addr, dst, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *src, int len) +{ + return RomDriver_XIP_SFlash_Write_With_Lock(pFlashCfg, ioMode, addr, src, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len) +{ + return RomDriver_XIP_SFlash_Erase_With_Lock(pFlashCfg, ioMode, addr, len); +} +/******************************************************************************/ + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) +{ + RomDriver_SFlash_Init(pSfCtrlCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) +{ + return RomDriver_SFlash_SetSPIMode(mode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Read_Reg(flashCfg, regIndex, regValue, regLen); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Write_Reg(flashCfg, regIndex, regValue, regLen); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg, readRegCmd, regValue, regLen); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg, writeRegCmd, regValue, regLen); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Sts_Type + SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Busy(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Write_Enable(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Qspi_Enable(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Chip_Erase(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) +{ + return RomDriver_SFlash_Sector_Erase(flashCfg, secNum); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + return RomDriver_SFlash_Blk32_Erase(flashCfg, blkNum); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + return RomDriver_SFlash_Blk64_Erase(flashCfg, blkNum); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) +{ + return RomDriver_SFlash_Erase(flashCfg, startaddr, endaddr); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_SFlash_Program(flashCfg, ioMode, addr, data, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) +{ + RomDriver_SFlash_GetUniqueId(data, idLen); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) +{ + RomDriver_SFlash_GetJedecId(flashCfg, data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetDeviceId(uint8_t *data) +{ + RomDriver_SFlash_GetDeviceId(data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Powerdown(void) +{ + RomDriver_SFlash_Powerdown(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) +{ + RomDriver_SFlash_Releae_Powerdown(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) +{ + return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg, flashContRead); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + RomDriver_SFlash_SetBurstWrap(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + RomDriver_SFlash_DisableBurstWrap(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Software_Reset(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Reset_Continue_Read(flashCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) +{ + return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, addr, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) +{ + return RomDriver_SFlash_IDbus_Read_Enable(flashCfg, ioMode, contRead); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) +{ + return RomDriver_SFlash_Cache_Read_Enable(flashCfg, ioMode, contRead, wayDisable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Cache_Read_Disable(void) +{ + RomDriver_SFlash_Cache_Read_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_SFlash_Read(flashCfg, ioMode, contRead, addr, data, len); +} +/******************************************************************************/ + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + L1C_Cache_Enable_Set(uint8_t wayDisable) +{ + return RomDriver_L1C_Cache_Enable_Set(wayDisable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) +{ + RomDriver_L1C_Cache_Write_Set(wtEn, wbEn, waEn); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + L1C_Cache_Flush(uint8_t wayDisable) +{ + return RomDriver_L1C_Cache_Flush(wayDisable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) +{ + RomDriver_L1C_Cache_Hit_Count_Get(hitCountLow, hitCountHigh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint32_t + L1C_Cache_Miss_Count_Get(void) +{ + return RomDriver_L1C_Cache_Miss_Count_Get(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Read_Disable(void) +{ + RomDriver_L1C_Cache_Read_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + L1C_Set_Wrap(BL_Fun_Type wrap) +{ + return RomDriver_L1C_Set_Wrap(wrap); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + L1C_Set_Way_Disable(uint8_t disableVal) +{ + return RomDriver_L1C_Set_Way_Disable(disableVal); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + L1C_IROM_2T_Access_Set(uint8_t enable) +{ + return RomDriver_L1C_IROM_2T_Access_Set(enable); +} +/******************************************************************************/ + +/******************************************************************************/ +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) +{ + RomDriver_SF_Ctrl_Enable(cfg); +} + +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +void SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) +{ + RomDriver_SF_Ctrl_Psram_Init(sfCtrlPsramCfg); +} +#endif + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint8_t + SF_Ctrl_Get_Clock_Delay(void) +{ + return RomDriver_SF_Ctrl_Get_Clock_Delay(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Clock_Delay(uint8_t delay) +{ + RomDriver_SF_Ctrl_Set_Clock_Delay(delay); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg) +{ + RomDriver_SF_Ctrl_Cmds_Set(cmdsCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) +{ + RomDriver_SF_Ctrl_Set_Owner(owner); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Disable(void) +{ + RomDriver_SF_Ctrl_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel) +{ + RomDriver_SF_Ctrl_Select_Pad(sel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Bank(SF_Ctrl_Select sel) +{ + RomDriver_SF_Ctrl_Select_Bank(sel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable_BE(void) +{ + RomDriver_SF_Ctrl_AES_Enable_BE(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable_LE(void) +{ + RomDriver_SF_Ctrl_AES_Enable_LE(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, + uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) +{ + RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hwKey, startAddr, endAddr, locked); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addrOffset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addrOffset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable(void) +{ + RomDriver_SF_Ctrl_AES_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Disable(void) +{ + RomDriver_SF_Ctrl_AES_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint8_t + SF_Ctrl_Is_AES_Enable(void) +{ + return RomDriver_SF_Ctrl_Is_AES_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) +{ + RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint32_t + SF_Ctrl_Get_Flash_Image_Offset(void) +{ + return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) +{ + RomDriver_SF_Ctrl_Select_Clock(sahbType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) +{ + RomDriver_SF_Ctrl_SendCmd(cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg, cmdValid); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + RomDriver_SF_Ctrl_Psram_Write_Icache_Set(cfg, cmdValid); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + RomDriver_SF_Ctrl_Psram_Read_Icache_Set(cfg, cmdValid); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Sts_Type + SF_Ctrl_GetBusyState(void) +{ + return RomDriver_SF_Ctrl_GetBusyState(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +{ + return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg); +} + +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) +{ + RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); +} +#endif + +__ALWAYS_INLINE ATTR_TCM_SECTION + uint32_t + SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, + SPI_Flash_Cfg_Type *pFlashCfg) +{ + return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg); +} +/******************************************************************************/ + +/******************************************************************************/ +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +void Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) +{ + RomDriver_Psram_Init(psramCfg, cmdsCfg, sfCtrlPsramCfg); +} +#endif + +__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) +{ + RomDriver_Psram_ReadReg(psramCfg, regValue); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) +{ + RomDriver_Psram_WriteReg(psramCfg, regValue); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg) +{ + return RomDriver_Psram_SetDriveStrength(psramCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg) +{ + return RomDriver_Psram_SetBurstWrap(psramCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data) +{ + RomDriver_Psram_ReadId(psramCfg, data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg) +{ + return RomDriver_Psram_EnterQuadMode(psramCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg) +{ + return RomDriver_Psram_ExitQuadMode(psramCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) +{ + return RomDriver_Psram_ToggleBurstLength(psramCfg, ctrlMode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) +{ + return RomDriver_Psram_SoftwareReset(psramCfg, ctrlMode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, + SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len) +{ + return RomDriver_Psram_Set_IDbus_Cfg(psramCfg, ioMode, addr, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, + BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) +{ + return RomDriver_Psram_Cache_Write_Set(psramCfg, ioMode, wtEn, wbEn, waEn); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_Write(SPI_Psram_Cfg_Type *psramCfg, + SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_Psram_Write(psramCfg, ioMode, addr, data, len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION + BL_Err_Type + Psram_Read(SPI_Psram_Cfg_Type *psramCfg, + SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_Psram_Read(psramCfg, ioMode, addr, data, len); +} +/******************************************************************************/ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romdriver.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romdriver.c new file mode 100644 index 0000000000000000000000000000000000000000..31c57ca562d9ff7ad0c4c0973a4b6672ad765038 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romdriver.c @@ -0,0 +1,246 @@ +#include "bl702_romdriver.h" +#include + +/** @addtogroup BL702_Periph_Driver + * @{ + */ + +/** @defgroup ROMDRIVER + * @brief ROMDRIVER common functions + * @{ + */ + +/** @defgroup ROMDRIVER_Private_Type + * @{ + */ +uint32_t const romDriverTable[] = { + 0x07020001, + 0x00000000, + 0x00000000, + 0x00000000, + + [ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG, + [ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG, + [ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL, + [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode, + [ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL, + + [ROM_API_INDEX_ASM_Delay_Us] = (uint32_t)ASM_Delay_Us, + [ROM_API_INDEX_BL702_Delay_US] = (uint32_t)BL702_Delay_US, + [ROM_API_INDEX_BL702_Delay_MS] = (uint32_t)BL702_Delay_MS, + [ROM_API_INDEX_BL702_MemCpy] = (uint32_t)BL702_MemCpy, + [ROM_API_INDEX_BL702_MemCpy4] = (uint32_t)BL702_MemCpy4, + [ROM_API_INDEX_BL702_MemCpy_Fast] = (uint32_t)BL702_MemCpy_Fast, + [ROM_API_INDEX_ARCH_MemCpy_Fast] = (uint32_t)ARCH_MemCpy_Fast, + [ROM_API_INDEX_BL702_MemSet] = (uint32_t)BL702_MemSet, + [ROM_API_INDEX_BL702_MemSet4] = (uint32_t)BL702_MemSet4, + [ROM_API_INDEX_BL702_MemCmp] = (uint32_t)BL702_MemCmp, + [ROM_API_INDEX_BFLB_Soft_CRC32] = (uint32_t)BFLB_Soft_CRC32, + + [ROM_API_INDEX_GLB_Get_Root_CLK_Sel] = (uint32_t)GLB_Get_Root_CLK_Sel, + [ROM_API_INDEX_GLB_Set_System_CLK_Div] = (uint32_t)GLB_Set_System_CLK_Div, + [ROM_API_INDEX_GLB_Get_BCLK_Div] = (uint32_t)GLB_Get_BCLK_Div, + [ROM_API_INDEX_GLB_Get_HCLK_Div] = (uint32_t)GLB_Get_HCLK_Div, + [ROM_API_INDEX_Update_SystemCoreClockWith_XTAL] = (uint32_t)Update_SystemCoreClockWith_XTAL, + [ROM_API_INDEX_GLB_Set_System_CLK] = (uint32_t)GLB_Set_System_CLK, + [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M, + [ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK, + [ROM_API_INDEX_GLB_Power_Off_DLL] = (uint32_t)GLB_Power_Off_DLL, + [ROM_API_INDEX_GLB_Power_On_DLL] = (uint32_t)GLB_Power_On_DLL, + [ROM_API_INDEX_GLB_Enable_DLL_All_Clks] = (uint32_t)GLB_Enable_DLL_All_Clks, + [ROM_API_INDEX_GLB_Enable_DLL_Clk] = (uint32_t)GLB_Enable_DLL_Clk, + [ROM_API_INDEX_GLB_Disable_DLL_All_Clks] = (uint32_t)GLB_Disable_DLL_All_Clks, + [ROM_API_INDEX_GLB_Disable_DLL_Clk] = (uint32_t)GLB_Disable_DLL_Clk, + [ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset, + [ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset, + [ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset, + [ROM_API_INDEX_GLB_Select_Internal_Flash] = (uint32_t)GLB_Select_Internal_Flash, + [ROM_API_INDEX_GLB_Swap_Flash_Pin] = (uint32_t)GLB_Swap_Flash_Pin, + [ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin] = (uint32_t)GLB_Swap_Flash_CS_IO2_Pin, + [ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin] = (uint32_t)GLB_Swap_Flash_IO0_IO3_Pin, + [ROM_API_INDEX_GLB_Select_Internal_PSram] = (uint32_t)GLB_Select_Internal_PSram, + [ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable] = (uint32_t)GLB_GPIO_OUTPUT_Enable, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable] = (uint32_t)GLB_GPIO_OUTPUT_Disable, + [ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ, + [ROM_API_INDEX_GLB_Deswap_Flash_Pin] = (uint32_t)GLB_Deswap_Flash_Pin, + [ROM_API_INDEX_GLB_Select_External_Flash] = (uint32_t)GLB_Select_External_Flash, + [ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun, + + [ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy, + [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0, + [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0, + [ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear, + [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity, + [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim, + [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim, + + [ROM_API_INDEX_PDS_Trim_RC32M] = (uint32_t)PDS_Trim_RC32M, + [ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref, + [ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref] = (uint32_t)PDS_Select_XTAL_As_PLL_Ref, + [ROM_API_INDEX_PDS_Power_On_PLL] = (uint32_t)PDS_Power_On_PLL, + [ROM_API_INDEX_PDS_Enable_PLL_All_Clks] = (uint32_t)PDS_Enable_PLL_All_Clks, + [ROM_API_INDEX_PDS_Disable_PLL_All_Clks] = (uint32_t)PDS_Disable_PLL_All_Clks, + [ROM_API_INDEX_PDS_Enable_PLL_Clk] = (uint32_t)PDS_Enable_PLL_Clk, + [ROM_API_INDEX_PDS_Disable_PLL_Clk] = (uint32_t)PDS_Disable_PLL_Clk, + [ROM_API_INDEX_PDS_Power_Off_PLL] = (uint32_t)PDS_Power_Off_PLL, + [ROM_API_INDEX_PDS_Reset] = (uint32_t)PDS_Reset, + [ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable, + [ROM_API_INDEX_PDS_Auto_Time_Config] = (uint32_t)PDS_Auto_Time_Config, + [ROM_API_INDEX_PDS_Auto_Enable] = (uint32_t)PDS_Auto_Enable, + [ROM_API_INDEX_PDS_Manual_Force_Turn_Off] = (uint32_t)PDS_Manual_Force_Turn_Off, + [ROM_API_INDEX_PDS_Manual_Force_Turn_On] = (uint32_t)PDS_Manual_Force_Turn_On, + + [ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable, + [ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset, + [ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO_Dbg_Pull_Cfg, + [ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K, + [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel] = (uint32_t)HBN_Set_ROOT_CLK_Sel, + + [ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save, + [ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore, + [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock, + + [ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init, + [ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode, + [ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg, + [ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg, + [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy, + [ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable, + [ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable, + [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable, + [ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase, + [ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase, + [ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase, + [ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase, + [ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase, + [ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program, + [ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId, + [ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId, + [ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId, + [ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown, + [ROM_API_INDEX_SFlash_Releae_Powerdown] = (uint32_t)SFlash_Releae_Powerdown, + [ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown, + [ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap, + [ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap, + [ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset, + [ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read, + [ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg, + [ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Read_Enable] = (uint32_t)SFlash_Cache_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Read_Disable] = (uint32_t)SFlash_Cache_Read_Disable, + [ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read, + + [ROM_API_INDEX_L1C_Cache_Enable_Set] = (uint32_t)L1C_Cache_Enable_Set, + [ROM_API_INDEX_L1C_Cache_Write_Set] = (uint32_t)L1C_Cache_Write_Set, + [ROM_API_INDEX_L1C_Cache_Flush] = (uint32_t)L1C_Cache_Flush, + [ROM_API_INDEX_L1C_Cache_Hit_Count_Get] = (uint32_t)L1C_Cache_Hit_Count_Get, + [ROM_API_INDEX_L1C_Cache_Miss_Count_Get] = (uint32_t)L1C_Cache_Miss_Count_Get, + [ROM_API_INDEX_L1C_Cache_Read_Disable] = (uint32_t)L1C_Cache_Read_Disable, + [ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap, + [ROM_API_INDEX_L1C_Set_Way_Disable] = (uint32_t)L1C_Set_Way_Disable, + [ROM_API_INDEX_L1C_IROM_2T_Access_Set] = (uint32_t)L1C_IROM_2T_Access_Set, + + [ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable, + [ROM_API_INDEX_SF_Ctrl_Psram_Init] = (uint32_t)SF_Ctrl_Psram_Init, + [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay, + [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay, + [ROM_API_INDEX_SF_Ctrl_Cmds_Set] = (uint32_t)SF_Ctrl_Cmds_Set, + [ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner, + [ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable, + [ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad, + [ROM_API_INDEX_SF_Ctrl_Select_Bank] = (uint32_t)SF_Ctrl_Select_Bank, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable, + [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Select_Clock] = (uint32_t)SF_Ctrl_Select_Clock, + [ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd, + [ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set] = (uint32_t)SF_Ctrl_Flash_Read_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set] = (uint32_t)SF_Ctrl_Psram_Write_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set] = (uint32_t)SF_Ctrl_Psram_Read_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState, + [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock, + [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify, + + [ROM_API_INDEX_Psram_Init] = (uint32_t)Psram_Init, + [ROM_API_INDEX_Psram_ReadReg] = (uint32_t)Psram_ReadReg, + [ROM_API_INDEX_Psram_WriteReg] = (uint32_t)Psram_WriteReg, + [ROM_API_INDEX_Psram_SetDriveStrength] = (uint32_t)Psram_SetDriveStrength, + [ROM_API_INDEX_Psram_SetBurstWrap] = (uint32_t)Psram_SetBurstWrap, + [ROM_API_INDEX_Psram_ReadId] = (uint32_t)Psram_ReadId, + [ROM_API_INDEX_Psram_EnterQuadMode] = (uint32_t)Psram_EnterQuadMode, + [ROM_API_INDEX_Psram_ExitQuadMode] = (uint32_t)Psram_ExitQuadMode, + [ROM_API_INDEX_Psram_ToggleBurstLength] = (uint32_t)Psram_ToggleBurstLength, + [ROM_API_INDEX_Psram_SoftwareReset] = (uint32_t)Psram_SoftwareReset, + [ROM_API_INDEX_Psram_Set_IDbus_Cfg] = (uint32_t)Psram_Set_IDbus_Cfg, + [ROM_API_INDEX_Psram_Cache_Write_Set] = (uint32_t)Psram_Cache_Write_Set, + [ROM_API_INDEX_Psram_Write] = (uint32_t)Psram_Write, + [ROM_API_INDEX_Psram_Read] = (uint32_t)Psram_Read, + + [ROM_API_INDEX_FUNC_INVALID_START... ROM_API_INDEX_FUNC_LAST_ENTRY] = 0xdeedbeef, +}; + +/*@} end of group ROMDRIVER_Private_Type*/ + +/** @defgroup ROMDRIVER_Private_Defines + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Defines */ + +/** @defgroup ROMDRIVER_Private_Variables + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Variables */ + +/** @defgroup ROMDRIVER_Global_Variables + * @{ + */ + +/*@} end of group ROMDRIVER_Global_Variables */ + +/** @defgroup ROMDRIVER_Private_FunctionDeclaration + * @{ + */ + +/*@} end of group ROMDRIVER_Private_FunctionDeclaration */ + +/** @defgroup ROMDRIVER_Private_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Functions */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER_COMMON */ + +/*@} end of group BL702_Periph_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_dbg.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_dbg.c new file mode 100644 index 0000000000000000000000000000000000000000..662fcfd43094b10efab18b9390ae0d87ab22fa06 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_dbg.c @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file bl702_sec_dbg.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl702_sec_dbg.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_DBG + * @{ + */ + +/** @defgroup SEC_DBG_Private_Macros + * @{ + */ + +/*@} end of group SEC_DBG_Private_Macros */ + +/** @defgroup SEC_DBG_Private_Types + * @{ + */ + +/*@} end of group SEC_DBG_Private_Types */ + +/** @defgroup SEC_DBG_Private_Variables + * @{ + */ + +/*@} end of group SEC_DBG_Private_Variables */ + +/** @defgroup SEC_DBG_Global_Variables + * @{ + */ + +/*@} end of group SEC_DBG_Global_Variables */ + +/** @defgroup SEC_DBG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_DBG_Private_Fun_Declaration */ + +/** @defgroup SEC_DBG_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Sec Dbg read chip ID + * + * @param id[8]: chip ID buffer + * + * @return None + * +*******************************************************************************/ +void Sec_Dbg_Read_Chip_ID(uint8_t id[8]) +{ + uint32_t idLow, idHigh; + + idLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_LOW); + BL_WRWD_TO_BYTEP(id, idLow); + + idHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_HIGH); + BL_WRWD_TO_BYTEP((id + 4), idHigh); +} + +/****************************************************************************/ /** + * @brief Sec Dbg read MAC address + * + * @param macAddr[6]: MAC address buffer + * + * @return None + * +*******************************************************************************/ +void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]) +{ + uint32_t macLow, macHigh; + + macLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_WIFI_MAC_LOW); + BL_WRWD_TO_BYTEP(macAddr, macLow); + + macHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_WIFI_MAC_HIGH); + macAddr[4] = (macHigh >> 0) & 0xff; + macAddr[5] = (macHigh >> 8) & 0xff; +} + +/****************************************************************************/ /** + * @brief Sec Dbg read debug mode + * + * @param None + * + * @return debug mode status + * +*******************************************************************************/ +uint32_t Sec_Dbg_Read_Dbg_Mode(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_MODE); +} + +/****************************************************************************/ /** + * @brief Sec Dbg read debug enable status + * + * @param None + * + * @return enable status + * +*******************************************************************************/ +uint32_t Sec_Dbg_Read_Dbg_Enable(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_ENA); +} + +/*@} end of group SEC_DBG_Public_Functions */ + +/*@} end of group SEC_DBG */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_eng.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_eng.c new file mode 100644 index 0000000000000000000000000000000000000000..26ea4b166a278c1f64429bea4275e2046eba3869 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_eng.c @@ -0,0 +1,3387 @@ +/** + ****************************************************************************** + * @file bl702_sec_eng.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl702_sec_eng.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_ENG + * @{ + */ + +/** @defgroup SEC_ENG_Private_Macros + * @{ + */ +#define PUT_UINT32_BE(n, b, i) \ + { \ + (b)[(i)] = (uint8_t)((n) >> 24); \ + (b)[(i) + 1] = (uint8_t)((n) >> 16); \ + (b)[(i) + 2] = (uint8_t)((n) >> 8); \ + (b)[(i) + 3] = (uint8_t)((n)); \ + } +#define PUT_UINT64_BE(n, b, i) \ + { \ + (b)[(i)] = (uint8_t)((n) >> 56); \ + (b)[(i) + 1] = (uint8_t)((n) >> 48); \ + (b)[(i) + 2] = (uint8_t)((n) >> 40); \ + (b)[(i) + 3] = (uint8_t)((n) >> 32); \ + (b)[(i) + 4] = (uint8_t)((n) >> 24); \ + (b)[(i) + 5] = (uint8_t)((n) >> 16); \ + (b)[(i) + 6] = (uint8_t)((n) >> 8); \ + (b)[(i) + 7] = (uint8_t)((n)); \ + } +#define SEC_ENG_SHA_BUSY_TIMEOUT_COUNT (100 * 160 * 1000) +#define SEC_ENG_AES_BUSY_TIMEOUT_COUNT (100 * 160 * 1000) +#define SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT (100 * 160 * 1000) +#define SEC_ENG_PKA_INT_TIMEOUT_COUNT (100 * 160 * 1000) +#define SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT (100 * 160 * 1000) + +/*@} end of group SEC_ENG_Private_Macros */ + +/** @defgroup SEC_ENG_Private_Types + * @{ + */ +struct pka0_pld_cfg { + union { + struct + { + uint32_t size : 12; /*[11: 0], r/w, 0x0 */ + uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_pldi_cfg { + union { + struct + { + uint32_t rsvd : 12; /*[11: 0], r/w, 0x0 */ + uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_first_cfg { + union { + struct + { + uint32_t s0_reg_idx : 8; /*[7: 0], r/w, 0x0 */ + uint32_t s0_reg_type : 4; /*[11:8], r/w, 0x0 */ + uint32_t d_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S1_only { + union { + struct + { + uint32_t reserved_0_11 : 12; /*[11: 0], rsvd, 0x0 */ + uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S2_only { + union { + struct + { + uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ + uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /*[31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S1_S2 { + union { + struct + { + uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ + uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ + uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +struct pka0_bit_shift_op_cfg { + union { + struct + { + uint32_t bit_shift : 15; /*[14: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 17; /*[31:15], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } value; +}; + +/*@} end of group SEC_ENG_Private_Types */ + +/** @defgroup SEC_ENG_Private_Variables + * @{ + */ +static intCallback_Type *secEngIntCbfArra[SEC_ENG_INT_ALL] = { NULL }; + +/*@} end of group SEC_ENG_Private_Variables */ + +/** @defgroup SEC_ENG_Global_Variables + * @{ + */ + +/*@} end of group SEC_ENG_Global_Variables */ + +/** @defgroup SEC_ENG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_ENG_Private_Fun_Declaration */ + +/** @defgroup SEC_ENG_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief SHA256 initialization function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param shaType: SHA type + * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes + * @param padding[16]: SHA padding buffer for store padding data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t shaTmpBuf[16], uint32_t padding[16]) +{ + uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); + + /* Deal SHA control register to set SHA mode */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MODE, shaType); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + /* Clear context */ + memset(shaCtx, 0, sizeof(SEC_Eng_SHA256_Ctx)); + + /* Init temp buffer and padding buffer */ + shaCtx->shaBuf = shaTmpBuf; + shaCtx->shaPadding = padding; + BL702_MemSet(shaCtx->shaPadding, 0, 64); + BL702_MemSet(shaCtx->shaPadding, 0x80, 1); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_SHA_IRQn, SEC_SHA_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief SHA start function + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Set SHA enable */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_EN); + /* Hash sel 0 for new start */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_HASH_SEL); + + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief SHA256 update input data function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param input: SHA input data pointer, and the address should be word align + * @param len: SHA input data length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) +{ + uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + uint32_t fill; + uint32_t left; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + if (len == 0) { + return SUCCESS; + } + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + /* SHA need set se_sha_sel to 1 to keep the last SHA state */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_HASH_SEL, shaCtx->shaFeed); + + left = shaCtx->total[0] & 0x3F; + fill = 64 - left; + + shaCtx->total[0] += (uint32_t)len; + shaCtx->total[0] &= 0xFFFFFFFF; + + if (shaCtx->total[0] < (uint32_t)len) { + shaCtx->total[1]++; + } + + if (left && len >= fill) { + BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); + /* Set data source address */ + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_MSA, (uint32_t)shaCtx->shaBuf); + + /* Set data length */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MSG_LEN, 1); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + /* Trigger */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_TRIG_1T); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + shaCtx->shaFeed = 1; + input += fill; + len -= fill; + left = 0; + } + + fill = len / 64; + len = len % 64; + + if (fill > 0) { + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + /* SHA need set se_sha_sel to 1 to keep the last sha state */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_HASH_SEL, shaCtx->shaFeed); + + /* Fill data */ + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_MSA, (uint32_t)input); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MSG_LEN, fill); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_TRIG_1T); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + input += (fill * 64); + shaCtx->shaFeed = 1; + } + + if (len > 0) { + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + /* Copy left data into temp buffer */ + BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); + } + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SHA256 finish to get output function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param hash: SHA output data of SHA result + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t shaMode; + uint8_t msgLen[8]; + uint8_t *p = (uint8_t *)hash; + uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3); + low = (shaCtx->total[0] << 3); + + PUT_UINT32_BE(high, msgLen, 0); + PUT_UINT32_BE(low, msgLen, 4); + + last = shaCtx->total[0] & 0x3F; + padn = (last < 56) ? (56 - last) : (120 - last); + + Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); + + /* Wait for shaPadding idle */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + BL702_MemCpy_Fast(shaCtx->shaPadding, msgLen, 8); + Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 8); + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY)); + + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MODE); + /* Copy SHA value */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_0); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_1); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_2); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_3); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_4); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + + if (shaMode == SEC_ENG_SHA224 || shaMode == SEC_ENG_SHA256) { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_5); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_6); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + + if (shaMode == SEC_ENG_SHA256) { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_7); + *p++ = (tmpVal & 0xff); + *p++ = ((tmpVal >> 8) & 0xff); + *p++ = ((tmpVal >> 16) & 0xff); + *p++ = ((tmpVal >> 24) & 0xff); + } + } + + /* Disable SHA engine*/ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_HASH_SEL); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_EN); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SHA enable link mode and set link config address + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Enable sha and enable link mode */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief SHA disable link mode + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Disable sha and disable link mode */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief SHA256 link mode initialization function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param linkAddr: SHA link configure address + * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes + * @param padding[16]: SHA padding buffer for store padding data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t shaTmpBuf[16], uint32_t padding[16]) +{ + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Clear context */ + memset(shaCtx, 0, sizeof(SEC_Eng_SHA256_Link_Ctx)); + + /* Init temp buffer,padding buffer and link address */ + shaCtx->shaBuf = shaTmpBuf; + shaCtx->shaPadding = padding; + BL702_MemSet(shaCtx->shaPadding, 0, 64); + BL702_MemSet(shaCtx->shaPadding, 0x80, 1); + shaCtx->linkAddr = linkAddr; + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_SHA_IRQn, SEC_SHA_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief SHA256 link mode update input data function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param input: SHA input data pointer, and the address should be word align + * @param len: SHA input data length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t fill; + uint32_t left; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + if (len == 0) { + return SUCCESS; + } + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Set link address */ + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); + + left = shaCtx->total[0] & 0x3F; + fill = 64 - left; + + shaCtx->total[0] += (uint32_t)len; + shaCtx->total[0] &= 0xFFFFFFFF; + + if (shaCtx->total[0] < (uint32_t)len) { + shaCtx->total[1]++; + } + + if (left && len >= fill) { + BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); + /* Set data source address */ + *(uint32_t *)(shaCtx->linkAddr + 4) = (uint32_t)shaCtx->shaBuf; + + /* Set data length */ + *((uint16_t *)shaCtx->linkAddr + 1) = 1; + /* Trigger */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); + + /* Choose accumulating last hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) |= 0x40; + input += fill; + len -= fill; + left = 0; + } + + fill = len / 64; + len = len % 64; + + if (fill > 0) { + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Fill data */ + *(uint32_t *)(shaCtx->linkAddr + 4) = (uint32_t)input; + *((uint16_t *)shaCtx->linkAddr + 1) = fill; + + /* Trigger */ + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); + + input += (fill * 64); + /* Choose accumulating last hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) |= 0x40; + } + + if (len > 0) { + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Copy left data into temp buffer */ + BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); + } + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SHA256 link mode finish to get output function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param hash: SHA output data of SHA result + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t msgLen[8]; + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t shaMode = (*(uint32_t *)shaCtx->linkAddr) >> 2 & 0x7; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Set link address */ + BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); + + high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3); + low = (shaCtx->total[0] << 3); + + PUT_UINT32_BE(high, msgLen, 0); + PUT_UINT32_BE(low, msgLen, 4); + + last = shaCtx->total[0] & 0x3F; + padn = (last < 56) ? (56 - last) : (120 - last); + + Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); + + /* Wait for shaPadding idle */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, msgLen, 8); + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); + + /* Get result according to SHA mode,result is placed in (link address + offset:8) */ + switch (shaMode) { + case 0: + BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 32); + break; + + case 1: + BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 28); + break; + + case 2: + BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 20); + break; + + case 3: + BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 20); + break; + + default: + break; + } + + /* Choose new hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) &= ~0x40; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AES initialization function + * + * @param aesCtx: AES context pointer + * @param aesNo: AES ID type + * @param aesType: AES type:ECB,CTR,CBC + * @param keyType: AES key type:128,256,192 + * @param enDecType: AES encryption or decryption + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_TYPE(aesType)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_TYPE(keyType)); + CHECK_PARAM(IS_SEC_ENG_AES_ENDEC_TYPE(enDecType)); + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY)); + + /* Set AES mode type*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_BLOCK_MODE, aesType); + + /* Set AES key type */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE, keyType); + + /* Set AES encryption or decryption */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_DEC_EN, enDecType); + + /* Clear dec_key_sel to select new key */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL); + + /* Clear aes iv sel to select new iv */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_IV_SEL); + + /* Clear AES interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_INT_CLR_1T); + + /* Enable AES */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_EN); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + /* Clear AES context */ + memset(aesCtx, 0, sizeof(SEC_Eng_AES_Ctx)); + + /* Enable ID0 Access for HW Key */ + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x03); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AES enable function,set AES bigendian + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_ENDIAN, 0x0f); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief AES enable function,set AES littleendian + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_ENDIAN, 0x00); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief AES enable link mode + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Enable aes link mode */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE)); + + /* Enable ID0 Access for HW Key */ + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x03); +} + +/****************************************************************************/ /** + * @brief AES disable link mode + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Disable aes link mode */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE)); +} + +/****************************************************************************/ /** + * @brief AES work in link mode + * + * @param aesNo: AES ID type + * @param linkAddr: Address of config structure in link mode + * @param in: AES input data buffer to deal with + * @param len: AES input data length + * @param out: AES output data buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Link address should word align */ + if ((linkAddr & 0x03) != 0 || len % 16 != 0) { + return ERROR; + } + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); + + /* Set link address */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_LINK, linkAddr); + + /* Change source buffer address and destination buffer address */ + *(uint32_t *)(linkAddr + 4) = (uint32_t)in; + *(uint32_t *)(linkAddr + 8) = (uint32_t)out; + + /* Set data length */ + *((uint16_t *)linkAddr + 1) = len / 16; + + /* Enable aes */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN)); + + /* Start aes engine and wait finishing */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T)); + __NOP(); + __NOP(); + timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); + + /* Disable aes */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AES set hardware key source:efuse region for CPU0 or region efuse for CPU1 + * + * @param aesNo: AES ID type + * @param src: AES key source type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_SBOOT); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_SBOOT_KEY_SEL, src); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_SBOOT, tmpVal); +} + +/****************************************************************************/ /** + * @brief AES set KEY and IV + * + * @param aesNo: AES ID type + * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW + * @param key: AES KEY pointer + * @param iv: AES IV pointer + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t keyType; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); + + /* Set IV */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + + /* Select hardware key */ + if (keySrc == SEC_ENG_AES_KEY_HW) { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_HW); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_0, *key); + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0, tmpVal); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_1, *key); + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1, tmpVal); + + return; + } + + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_7, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_6, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE); + + if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) { + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS) { + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_1, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_0, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + } + + /* Select software key */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_SW); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief AES set KEY and IV with bigendian + * + * @param aesNo: AES ID type + * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW + * @param key: AES KEY pointer + * @param iv: AES IV pointer + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t keyType; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); + + /* Set IV */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_0, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_1, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_2, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_3, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + + /* Select hardware key */ + if (keySrc == SEC_ENG_AES_KEY_HW) { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_HW); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_0, *key); + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0, tmpVal); + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_1, *key); + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1, tmpVal); + + return; + } + + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_0, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_1, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, BL_RDWD_FRM_BYTEP(key)); + key += 4; + + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE); + + if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) { + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, BL_RDWD_FRM_BYTEP(key)); + key += 4; + } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS) { + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_6, BL_RDWD_FRM_BYTEP(key)); + key += 4; + BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_7, BL_RDWD_FRM_BYTEP(key)); + key += 4; + } + + /* Select software key */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_SW); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief AES set counter byte type in CTR mode + * + * @param aesNo: AES ID type + * @param counterType: AES counter type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_COUNTER_TYPE(counterType)); + + /* Set counter type */ + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN); + BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_CTR_LEN, counterType)); +} + +/****************************************************************************/ /** + * @brief AES encrypt or decrypt input data + * + * @param aesCtx: AES context pointer + * @param aesNo: AES ID type + * @param in: AES input data buffer to deal with + * @param len: AES input data length + * @param out: AES output data buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, uint8_t *out) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + if (len % 16 != 0) { + return ERROR; + } + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY)); + + /* Clear trigger */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_TRIG_1T); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + /* Set input and output address */ + BL_WR_REG(AESx, SEC_ENG_SE_AES_MSA, (uint32_t)in); + BL_WR_REG(AESx, SEC_ENG_SE_AES_MDA, (uint32_t)out); + + /* Set message length */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MSG_LEN, len / 16); + + if (aesCtx->mode == SEC_ENG_AES_CTR) { + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL); + } + + /* Set IV sel:0 for new, 1 for last */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_IV_SEL, aesCtx->aesFeed); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + /* Trigger AES Engine */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_TRIG_1T); + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + /* Wait finished */ + timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY)); + + aesCtx->aesFeed = 1; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief AES finish function, clean register + * + * @param aesNo: AES ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Wait finished */ + do { + tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY)); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_EN); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_IV_SEL); + + BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief TRNG enable TRNG interrupt + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_Trng_Enable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + /* FIXME:default reseed number is 0x1ff, to verify, use 0xa to speed up */ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_TRNG_RESEED_N,0x1ff); + + /* No interrupt as default */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_EN); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + /* busy will be set to 1 after trigger, the gap is 1T */ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + do { + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_BUSY)); + + /* Clear trng interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_TRNG_IRQn, SEC_TRNG_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief TRNG enable TRNG interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Enable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_MASK); + + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief TRNG disable TRNG interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Disable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_MASK); + + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief TRNG get random data out + * + * @param data[32]: TRNG output data + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]) +{ + uint8_t *p = (uint8_t *)data; + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + /* Trigger */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + /* busy will be set to 1 after trigger, the gap is 1T */ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + do { + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_BUSY)); + + /* copy trng value */ + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_0)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_1)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_2)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_3)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_4)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_5)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_6)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_7)); + p += 4; + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + /* Clear data */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief TRNG get random data out + * + * @param data: TRNG output data buffer + * + * @param len: total length to get in bytes + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len) +{ + uint8_t tmpBuf[32]; + uint32_t readLen = 0; + uint32_t i = 0, cnt = 0; + + while (readLen < len) { + if (Sec_Eng_Trng_Read(tmpBuf) != SUCCESS) { + return -1; + } + + cnt = len - readLen; + + if (cnt > sizeof(tmpBuf)) { + cnt = sizeof(tmpBuf); + } + + for (i = 0; i < cnt; i++) { + data[readLen + i] = tmpBuf[i]; + } + + readLen += cnt; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief TRNG Interrupt Read Trigger + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Read_Trigger(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + Sec_Eng_Trng_Int_Enable(); + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + /* Trigger */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief TRNG get random data out with Interrupt + * + * @param data[32]: TRNG output data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Read(uint8_t data[32]) +{ + uint8_t *p = (uint8_t *)data; + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + /* copy trng value */ + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_0)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_1)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_2)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_3)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_4)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_5)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_6)); + p += 4; + BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_7)); + p += 4; + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + /* Clear data */ + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief Disable TRNG + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Disable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_EN); + //tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_RESEED_N); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T); + + BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal); +} + +/****************************************************************************/ /** + * @brief PKA Reset + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Reset(void) +{ + uint8_t val; + + //Disable sec engine + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, 0); + + //Enable sec engine + val = 1 << 3; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, val); +} + +/****************************************************************************/ /** + * @brief PKA Enable big endian + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_BigEndian_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_PKA_IRQn, SEC_PKA_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief PKA Enable little endian + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LittleEndian_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_PKA_IRQn, SEC_PKA_IRQHandler); +#endif +} + +/****************************************************************************/ /** + * @brief PKA get status function + * + * @param status: Structure pointer of PKA status type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + *(uint16_t *)status = (uint16_t)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_PKA_0_STATUS); +} + +/****************************************************************************/ /** + * @brief PKA clear interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Clear_Int(void) +{ + uint32_t ctrl; + + ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + ctrl = BL_SET_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); + + ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + ctrl = BL_CLR_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); +} + +/****************************************************************************/ /** + * @brief PKA get Register size according to Register type + * + * @param reg_type: PKA Register type + * + * @return Register size + * +*******************************************************************************/ +static uint16_t Sec_Eng_PKA_Get_Reg_Size(SEC_ENG_PKA_REG_SIZE_Type reg_type) +{ + switch (reg_type) { + case SEC_ENG_PKA_REG_SIZE_8: + return 8; + + case SEC_ENG_PKA_REG_SIZE_16: + return 16; + + case SEC_ENG_PKA_REG_SIZE_32: + return 32; + + case SEC_ENG_PKA_REG_SIZE_64: + return 64; + + case SEC_ENG_PKA_REG_SIZE_96: + return 96; + + case SEC_ENG_PKA_REG_SIZE_128: + return 128; + + case SEC_ENG_PKA_REG_SIZE_192: + return 192; + + case SEC_ENG_PKA_REG_SIZE_256: + return 256; + + case SEC_ENG_PKA_REG_SIZE_384: + return 384; + + case SEC_ENG_PKA_REG_SIZE_512: + return 512; + + default: + return 0; + } +} + +/****************************************************************************/ /** + * @brief PKA set pre-load register configuration + * + * @param size: Data size in word to write + * @param regIndex: Register index + * @param regType: Register type + * @param op: PKA operation + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Pld_Cfg(uint16_t size, uint8_t regIndex, SEC_ENG_PKA_REG_SIZE_Type regType, SEC_ENG_PKA_OP_Type op, uint8_t lastOp) +{ + struct pka0_pld_cfg cfg; + + cfg.value.BF.size = size; + cfg.value.BF.d_reg_index = regIndex; + cfg.value.BF.d_reg_type = regType; + cfg.value.BF.op = op; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA write common operation first configuration + * + * @param s0RegIndex: Register index + * @param s0RegType: Register type + * @param dRegIndex: Result Register index + * @param dRegType: Result Register type + * @param op: PKA operation + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_First_Cfg(uint8_t s0RegIndex, uint8_t s0RegType, uint8_t dRegIndex, uint8_t dRegType, + uint8_t op, uint8_t lastOp) +{ + struct pka0_common_op_first_cfg cfg; + + cfg.value.BF.s0_reg_idx = s0RegIndex; + cfg.value.BF.s0_reg_type = s0RegType; + + if (op != SEC_ENG_PKA_OP_LCMP) { + cfg.value.BF.d_reg_idx = dRegIndex; + cfg.value.BF.d_reg_type = dRegType; + } + + cfg.value.BF.op = op; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA write common operation second configuration1 + * + * @param s1RegIndex: Register index + * @param s1RegType: Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(uint8_t s1RegIndex, uint8_t s1RegType) +{ + struct pka0_common_op_snd_cfg_S1_only cfg; + + cfg.value.BF.s1_reg_idx = s1RegIndex; + cfg.value.BF.s1_reg_type = s1RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA write common operation second configuration2 + * + * @param s2RegIndex: Register index + * @param s2RegType: Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(uint8_t s2RegIndex, uint8_t s2RegType) +{ + struct pka0_common_op_snd_cfg_S2_only cfg; + + cfg.value.BF.s2_reg_idx = s2RegIndex; + cfg.value.BF.s2_reg_type = s2RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA write common operation second configuration1 and configuration 2 + * + * @param s1RegIndex: Configuration 1 Register index + * @param s1RegType: Configuration 1 Register type + * @param s2RegIndex: Configuration 2 Register index + * @param s2RegType: Configuration 3 Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(uint8_t s1RegIndex, uint8_t s1RegType, uint8_t s2RegIndex, uint8_t s2RegType) +{ + struct pka0_common_op_snd_cfg_S1_S2 cfg; + + cfg.value.BF.s1_reg_idx = s1RegIndex; + cfg.value.BF.s1_reg_type = s1RegType; + cfg.value.BF.s2_reg_idx = s2RegIndex; + cfg.value.BF.s2_reg_type = s2RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************/ /** + * @brief PKA wait for complete interrupt + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +static BL_Err_Type Sec_Eng_PKA_Wait_ISR(void) +{ + uint32_t pka0_ctrl; + uint32_t timeoutCnt = SEC_ENG_PKA_INT_TIMEOUT_COUNT; + + do { + pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } while (!BL_GET_REG_BITS_VAL(pka0_ctrl, SEC_ENG_SE_PKA_0_INT)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief PKA read block data from register + * + * @param dest: Pointer to buffer address + * @param src: Pointer to register address + * @param len: Data len in word + * + * @return None + * +*******************************************************************************/ +#ifdef ARCH_ARM +#ifndef __GNUC__ +__ASM void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + PUSH {R3-R6,LR} +Start0 + CMP R2,#4 + BLT Finish0 + LDR R3,[R1] + LDR R4,[R1] + LDR R5,[R1] + LDR R6,[R1] + STMIA R0!,{R3-R6} + SUBS R2,R2,#4 + B Start0 +Finish0 + POP {R3-R6,PC} +} +#else +void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + __asm__ __volatile__("push {r3-r6,lr}\n\t" + "Start0 :" + "cmp r2,#4\n\t" + "blt Finish0\n\t" + "ldr r3,[r1]\n\t" + "ldr r4,[r1]\n\t" + "ldr r5,[r1]\n\t" + "ldr r6,[r1]\n\t" + "stmia r0!,{r3-r6}\n\t" + "sub r2,r2,#4\n\t" + "b Start0\n\t" + "Finish0 :" + "pop {r3-r6,pc}\n\t"); +} +#endif +#endif +#ifdef ARCH_RISCV +void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + uint32_t wrLen = len - len % 4; + uint32_t i; + + for (i = 0; i < wrLen; i++) { + dest[i] = *src; + } +} +#endif + +/****************************************************************************/ /** + * @brief PKA Write block data to register + * + * @param dest: Pointer to register address + * @param src: Pointer to buffer address + * @param len: Data len in word + * + * @return None + * +*******************************************************************************/ +#ifdef ARCH_ARM +#ifndef __GNUC__ +__ASM void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + PUSH {R3-R6,LR} +Start1 + CMP R2,#4 + BLT Finish1 + LDMIA R1!,{R3-R6} + STR R3,[R0] + STR R4,[R0] + STR R5,[R0] + STR R6,[R0] + SUBS R2,R2,#4 + B Start1 +Finish1 + POP {R3-R6,PC} +} +#else +void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + __asm__ __volatile__("push {r3-r6,lr}\n\t" + "Start1 :" + "cmp r2,#4\n\t" + "blt Finish1\n\t" + "ldmia r1!,{r3-r6}\n\t" + "str r3,[r0]\n\t" + "str r4,[r0]\n\t" + "str r5,[r0]\n\t" + "str r6,[r0]\n\t" + "sub r2,r2,#4\n\t" + "b Start1\n\t" + "Finish1 :" + "pop {r3-r6,pc}\n\t"); +} +#endif +#endif +#ifdef ARCH_RISCV +void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) +{ + uint32_t wrLen = len - len % 4; + uint32_t i; + + for (i = 0; i < wrLen; i++) { + *dest = src[i]; + } +} +#endif + +/****************************************************************************/ /** + * @brief PKA get result + * + * @param result: Pointer to store result + * @param retSize: Result length in word + * @param regLen: register length in byte + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Get_Result(uint32_t *result, uint8_t retSize, uint16_t regLen) +{ + uint32_t ret_data = 0x00; + int index = 0x00; + + /* Wait for the result */ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + Sec_Eng_PKA_Read_Block(result, (uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), retSize); + index = retSize - (retSize % 4); + + while (index < retSize) { + ret_data = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW); + result[index] = ret_data; + index++; + } +} + +/****************************************************************************/ /** + * @brief PKA load data to register + * + * @param regType: Register type + * @param regIndex: Register index + * @param data: Data buffer + * @param size: Data length in word + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, uint8_t lastOp) +{ + int index = 0x00; + uint16_t regLen = Sec_Eng_PKA_Get_Reg_Size(regType); + + Sec_Eng_PKA_Write_Pld_Cfg(size, regIndex, regType, SEC_ENG_PKA_OP_CTLIR_PLD, lastOp); + + if (size > regLen / 4) { + size = regLen / 4; + } + + Sec_Eng_PKA_Write_Block((uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), data, size); + index = size - (size % 4); + + while (index < size) { + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data[index]); + index++; + } +} + +/****************************************************************************/ /** + * @brief PKA read data from register + * + * @param regType: Register type + * @param regIdx: Register index + * @param result: Data buffer + * @param retSize: Data length in word + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize) +{ + uint16_t regSize; + uint32_t dummyData = 0; + + regSize = Sec_Eng_PKA_Get_Reg_Size(regType); + + if (retSize > regSize / 4) { + result = NULL; + return; + } + + Sec_Eng_PKA_Write_Pld_Cfg(retSize, regIdx, regType, SEC_ENG_PKA_OP_CFLIR_BUFFER, 1); + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + Sec_Eng_PKA_Get_Result(result, retSize, regSize); +} + +/****************************************************************************/ /** + * @brief PKA clear register + * + * @param dRegType: Register type + * @param dRegIdx: Register index + * @param size: Data length in word + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Pld_Cfg(size, dRegIdx, dRegType, SEC_ENG_PKA_OP_CLIR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA load data to register + * + * @param regType: regType: Register type + * @param regIndex: regIndex: Register index + * @param data: data: Data buffer + * @param lastOp: size: Data length in word + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp) +{ + struct pka0_pldi_cfg cfg; + + cfg.value.BF.rsvd = 0; + cfg.value.BF.d_reg_index = regIndex; + cfg.value.BF.d_reg_type = regType; + cfg.value.BF.op = SEC_ENG_PKA_OP_SLIR; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA negative source data:D = (1 << SIZE{S0})-S0 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_NLIR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA move data:D = S0 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOVDAT, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA resize data:D = S0, D.Size = S0.Size + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_RESIZE, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod add:D = (S0 + S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MADD, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod sub:D = (S0 - S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSUB, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod :D = S0 mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MREM, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod mul:D = (S0 * S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MMUL, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod sqr:D = (S0 ^ 2) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSQR, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod exp:D = (S0 ^ S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MEXP, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod exp:D = (S0 ^ (S2-2) ) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MINV, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA Report COUT to 1 when S0 < S1 + * + * @param cout: Compare result + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx) +{ + uint32_t pka0_ctrl = 0x00; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, 0, 0, SEC_ENG_PKA_OP_LCMP, 1); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + + *cout = (pka0_ctrl & SEC_ENG_PKA_STATUS_LAST_OPC_MASK) >> SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET; +} + +/****************************************************************************/ /** + * @brief PKA add:D = S0 + S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LADD, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA sub:D = S0 - S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSUB, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mul:D = S0 * S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA sqr:D = S0^2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSQR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA div:D = S0 / S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA shift:D = S0 << BIT SHIFT + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL2N, 0); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA shift:D = S0 >> BIT SHIFT + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV2N, 0); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA mod 2N:D = S0 % ((1 << BIT SHIFT)-1) + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift, uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOD2N, lastOp); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if (lastOp) { + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************/ /** + * @brief PKA GF to Mont filed 2N:d = (a<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_glb.h" +#include "bl702_sf_cfg.h" +#include "softcrc.h" +#include "bl702_xip_sflash.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Private_Macros + * @{ + */ +#define BFLB_FLASH_CFG_MAGIC "FCFG" + +/*@} end of group SF_CFG_Private_Macros */ + +/** @defgroup SF_CFG_Private_Types + * @{ + */ +#ifndef BFLB_USE_ROM_DRIVER +typedef struct +{ + uint32_t jedecID; + char *name; + const SPI_Flash_Cfg_Type *cfg; +} Flash_Info_t; +#endif + +/*@} end of group SF_CFG_Private_Types */ + +/** @defgroup SF_CFG_Private_Variables + * @{ + */ +#ifndef BFLB_USE_ROM_DRIVER +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 0, + .cReadMode = 0xFF, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3d, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 3, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16DV = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3d, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 3, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80EW_16FW_32JW_32FW_32FV = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 400, + .timeE32k = 1600, + .timeE64k = 2000, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 3, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Issi = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x9d, + + .deBurstWrapCmd = 0xC0, + .deBurstWrapCmdDmyClk = 0x00, + .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, + .deBurstWrapData = 0x00, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0, + .qeBit = 0x06, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0xC0, + .burstWrapCmdDmyClk = 0x00, + .burstWrapDataMode = SF_CTRL_DATA_1_LINE, + .burstWrapData = 0x06, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 5, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x51, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 0, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_DO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 32 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 8 / 8, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0x12, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32C = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xC2, + + .deBurstWrapCmd = 0xC0, + .deBurstWrapCmdDmyClk = 0x00, + .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, + .deBurstWrapData = 0x10, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0, + .qeBit = 0x06, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA5, + + .burstWrapCmd = 0xC0, + .burstWrapCmdDmyClk = 0x00, + .burstWrapDataMode = SF_CTRL_DATA_1_LINE, + .burstWrapData = 0x02, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x38, + .qppAddrMode = SF_CTRL_ADDR_4_LINES, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 45, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_1635F = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xC2, + + .deBurstWrapCmd = 0xC0, + .deBurstWrapCmdDmyClk = 0x00, + .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, + .deBurstWrapData = 0x10, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0, + .qeBit = 0x06, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA5, + + .burstWrapCmd = 0xC0, + .burstWrapCmdDmyClk = 0x00, + .burstWrapDataMode = SF_CTRL_DATA_1_LINE, + .burstWrapData = 0x02, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x38, + .qppAddrMode = SF_CTRL_ADDR_4_LINES, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 45, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx40 = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x0B, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_DIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 6000, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x0B, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 6000, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q80L_Q80H_Q16H = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x85, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3d, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 8, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q32H = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x85, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 8, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya40 = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x68, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 0, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_DO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x68, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 0x01, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FT_VQ80 = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 8, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { + { + .jedecID = 0x1440ef, + .name = "Winb_80DV_08_33", + .cfg = &flashCfg_Winb_80DV, + }, + { + .jedecID = 0x1540ef, + .name = "Winb_16DV_16_33", + .cfg = &flashCfg_Winb_16DV, + }, + { + .jedecID = 0x1640ef, + .name = "Winb_32FV_32_33", + .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1460ef, + .name = "Winb_80EW_08_18", + .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1560ef, + .name = "Winb_16FW_16_18", + .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1660ef, + .name = "Winb_32FW_32_18", + .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1860ef, + .name = "Winb_128FW_128_18", + .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x1680ef, + .name = "Winb_32JW_32_18", + .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x13605e, + .name = "Zbit_04_33", + .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x14605e, + .name = "Zbit_08_33", + .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, + }, + { + .jedecID = 0x14609d, + .name = "ISSI_08_33", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x15609d, + .name = "ISSI_16_33", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x16609d, + .name = "ISSI_32_33", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x14709d, + .name = "ISSI_08_18", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x15709d, + .name = "ISSI_16_18", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x16709d, + .name = "ISSI_32_18", + .cfg = &flashCfg_Issi, + }, + { + .jedecID = 0x134051, + .name = "GD_MD04D_04_33", + .cfg = &flashCfg_Gd_Md_40D, + }, + { + .jedecID = 0x1440C8, + .name = "GD_Q08E_08_33", + .cfg = &flashCfg_Gd_Q80E_Q16E, + }, + { + .jedecID = 0x1540C8, + .name = "GD_Q16E_16_33", + .cfg = &flashCfg_Gd_Q80E_Q16E, + }, + { + .jedecID = 0x1640C8, + .name = "GD_Q32C_32_33", + .cfg = &flashCfg_Gd_Q32C, + }, + { + .jedecID = 0x1460C8, + .name = "GD_LQ08C_08_18", + .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID = 0x1560C8, + .name = "GD_LE16C_16_18", + .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID = 0x1660C8, + .name = "GD_LQ32D_32_18", + .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID = 0x1465C8, + .name = "GD_WQ80E_80_33", + .cfg = &flashCfg_Gd_WQ80E_WQ16E, + }, + { + .jedecID = 0x1565C8, + .name = "GD_WQ16E_16_33", + .cfg = &flashCfg_Gd_WQ80E_WQ16E, + }, + { + .jedecID = 0x1665C8, + .name = "GD_WQ32E_32_33", + .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID = 0x3425C2, + .name = "MX_25V80_08_18", + .cfg = &flashCfg_Mxic, + }, + { + .jedecID = 0x3525C2, + .name = "MX_25U16_35_18", + .cfg = &flashCfg_Mxic_1635F, + }, + { + .jedecID = 0x3625C2, + .name = "MX_25V32_32_18", + .cfg = &flashCfg_Mxic, + }, + { + .jedecID = 0x13400B, + .name = "XT_25F04D_04_33", + .cfg = &flashCfg_Xtx40, + }, + { + .jedecID = 0x15400B, + .name = "XT_25F16B_16_33", + .cfg = &flashCfg_Xtx, + }, + { + .jedecID = 0x16400B, + .name = "XT_25F32B_32_33", + .cfg = &flashCfg_Xtx, + }, + { + .jedecID = 0x14600B, + .name = "XT_25Q80B_08_18", + .cfg = &flashCfg_Xtx, + }, + { + .jedecID = 0x16600B, + .name = "XT_25Q32B_32_18", + .cfg = &flashCfg_Xtx, + }, + { + .jedecID = 0x146085, + .name = "Puya_Q80L/H_08_18/33", + .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, + }, + { + .jedecID = 0x156085, + .name = "Puya_Q16H_16_33", + .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, + }, + { + .jedecID = 0x166085, + .name = "Puya_Q32H_32_33", + .cfg = &flashCfg_Puya_Q32H, + }, + { + .jedecID = 0x134068, + .name = "Boya_Q04B_04_33", + .cfg = &flashCfg_Boya40, + }, + { + .jedecID = 0x144068, + .name = "Boya_Q08B_08_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x154068, + .name = "Boya_Q16B_16_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x164068, + .name = "Boya_Q32B_32_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x174068, + .name = "Boya_Q64A_64_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x184068, + .name = "Boya_Q128A_128_33", + .cfg = &flashCfg_Boya, + }, + { + .jedecID = 0x14605E, + .name = "FT_VQ80", + .cfg = &flashCfg_FT_VQ80, + } +}; +#endif + +/*@} end of group SF_CFG_Private_Variables */ + +/** @defgroup SF_CFG_Global_Variables + * @{ + */ + +/*@} end of group SF_CFG_Global_Variables */ + +/** @defgroup SF_CFG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CFG_Private_Fun_Declaration */ + +/** @defgroup SF_CFG_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Init external flash GPIO according to flash GPIO config + * + * @param extFlashPin: Flash GPIO config + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +/* static */ void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + GLB_GPIO_Cfg_Type cfg; + uint8_t gpiopins[6]; + uint8_t i = 0; + + cfg.gpioMode = GPIO_MODE_AF; + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 1; + cfg.smtCtrl = 1; + cfg.gpioFun = GPIO_FUN_FLASH_PSRAM; + + if (extFlashPin == 0) { + gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; + } else if (extFlashPin == 1) { + gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; + } else { + gpiopins[0] = BFLB_EXTFLASH_CLK2_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS2_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA02_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA12_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA22_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA32_GPIO; + } + + for (i = 0; i < sizeof(gpiopins); i++) { + cfg.gpioPin = gpiopins[i]; + + if (i == 0 || i == 1) { + /*flash clk and cs is output*/ + cfg.gpioMode = GPIO_MODE_OUTPUT; + } else { + /*data are bidir*/ + cfg.gpioMode = GPIO_MODE_AF; + } + + GLB_GPIO_Init(&cfg); + } +} +#endif + +/****************************************************************************/ /** + * @brief Deinit external flash GPIO according to flash GPIO config + * + * @param extFlashPin: Flash GPIO config + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +/* static */ void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + GLB_GPIO_Cfg_Type cfg; + uint8_t gpiopins[6]; + uint8_t i = 0; + + cfg.gpioMode = GPIO_MODE_INPUT; + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 1; + cfg.smtCtrl = 1; + cfg.gpioFun = GPIO_FUN_GPIO; + + if (extFlashPin == 0) { + gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; + + } else if (extFlashPin == 1) { + gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; + } else { + gpiopins[0] = BFLB_EXTFLASH_CLK2_GPIO; + gpiopins[1] = BFLB_EXTFLASH_CS2_GPIO; + gpiopins[2] = BFLB_EXTFLASH_DATA02_GPIO; + gpiopins[3] = BFLB_EXTFLASH_DATA12_GPIO; + gpiopins[4] = BFLB_EXTFLASH_DATA22_GPIO; + gpiopins[5] = BFLB_EXTFLASH_DATA32_GPIO; + } + + for (i = 0; i < sizeof(gpiopins); i++) { + cfg.gpioPin = gpiopins[i]; + GLB_GPIO_Init(&cfg); + } +} +#endif + +/*@} end of group SF_CFG_Private_Functions */ + +/** @defgroup SF_CFG_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Get flash config according to flash ID + * + * @param flashID: Flash ID + * @param pFlashCfg: Flash config pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t i; + uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; + uint32_t crc, *pCrc; + uint32_t xipOffset; + + if (flashID == 0) { + xipOffset = SF_Ctrl_Get_Flash_Image_Offset(); + SF_Ctrl_Set_Flash_Image_Offset(0); + XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); + SF_Ctrl_Set_Flash_Image_Offset(xipOffset); + + if (BL702_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { + crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); + pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); + + if (*pCrc == crc) { + BL702_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); + return SUCCESS; + } + } + } else { + for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { + if (flashInfos[i].jedecID == flashID) { + BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + return SUCCESS; + } + } + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Init flash GPIO according to flash Pin config + * + * @param flashPinCfg: Specify flash Pin config + * @param restoreDefault: Wether to restore default setting + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) +{ + uint8_t flashCfg; + uint8_t swapCfg; + uint32_t tmpVal; + + flashCfg = (flashPinCfg >> 2) & 0x03; + swapCfg = flashPinCfg & 0x03; + + if (restoreDefault) { + /* Set Default first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); + + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) { + SF_Cfg_Init_Ext_Flash_Gpio(1); + } + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF2); + + /* Default is set, so return */ + if (flashCfg == BFLB_FLASH_CFG_SF2_EXT_23_28 && swapCfg == BFLB_SF2_SWAP_NONE) { + return; + } + } + + if (flashCfg == BFLB_FLASH_CFG_SF1_EXT_17_22) { + SF_Cfg_Init_Ext_Flash_Gpio(0); + SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF1); + } else { + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); + + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) { + SF_Cfg_Init_Ext_Flash_Gpio(1); + } + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + + if (swapCfg == BFLB_SF2_SWAP_NONE) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); + } else if (swapCfg == BFLB_SF2_SWAP_CS_IO2) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); + } else if (swapCfg == BFLB_SF2_SWAP_IO0_IO3) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); + } + + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF2); + } +} + +/****************************************************************************/ /** + * @brief Identify one flash + * + * @param callFromFlash: code run at flash or ram + * @param autoScan: Auto scan all GPIO pin + * @param flashPinCfg: Specify flash GPIO config, not auto scan + * @param restoreDefault: Wether restore default flash GPIO config + * @param pFlashCfg: Flash config pointer + * + * @return Flash ID + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, + uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t jdecId = 0; + uint32_t i = 0; + uint32_t offset; + BL_Err_Type stat; + + BL702_MemCpy_Fast(pFlashCfg, &flashCfg_Gd_Q80E_Q16E, sizeof(SPI_Flash_Cfg_Type)); + + if (callFromFlash == 1) { + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); + return 0; + } + } + + if (autoScan) { + flashPinCfg = 0; + + do { + if (flashPinCfg > 0x0f) { + jdecId = 0; + break; + } + + SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); + SFlash_Releae_Powerdown(pFlashCfg); + SFlash_Reset_Continue_Read(pFlashCfg); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId = 0; + SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId = jdecId & 0xffffff; + flashPinCfg++; + } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00); + } else { + /* select media gpio */ + SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); + SFlash_Releae_Powerdown(pFlashCfg); + SFlash_Reset_Continue_Read(pFlashCfg); + SFlash_DisableBurstWrap(pFlashCfg); + SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId = jdecId & 0xffffff; + } + + for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { + if (flashInfos[i].jedecID == jdecId) { + BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + break; + } + } + + if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { + if (callFromFlash == 1) { + XIP_SFlash_State_Restore(pFlashCfg, pFlashCfg->ioMode, offset); + } + + return jdecId; + } else { + if (callFromFlash == 1) { + XIP_SFlash_State_Restore(pFlashCfg, pFlashCfg->ioMode, offset); + } + + return (jdecId | BFLB_FLASH_ID_VALID_FLAG); + } +} +#endif + +/*@} end of group SF_CFG_Public_Functions */ + +/*@} end of group SF_CFG */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c new file mode 100644 index 0000000000000000000000000000000000000000..7952b312cc2b733880acac71bde3fa2eb35a8780 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c @@ -0,0 +1,693 @@ +/** + ****************************************************************************** + * @file bl702_sf_cfg_ext.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_glb.h" +#include "bl702_sf_cfg.h" +#include "bl702_sf_cfg_ext.h" +#include "bl702_xip_sflash.h" +#include "bl702_romdriver.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG_EXT + * @{ + */ + +/** @defgroup SF_CFG_EXT_Private_Macros + * @{ + */ +#define BFLB_FLASH_CFG_MAGIC "FCFG" + +/*@} end of group SF_CFG_EXT_Private_Macros */ + +/** @defgroup SF_CFG_EXT_Private_Types + * @{ + */ +typedef struct +{ + uint32_t jedecID; + char *name; + const SPI_Flash_Cfg_Type *cfg; +} Flash_Info_t; + +/*@} end of group SF_CFG_EXT_Private_Types */ + +/** @defgroup SF_CFG_EXT_Private_Variables + * @{ + */ +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0x51, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 0, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = 0x11, + .clkDelay = 1, + .clkInvert = 0x01, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 33000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25 = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc2, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x00, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x00, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 0, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = 0x11, + .clkDelay = 1, + .clkInvert = 0x01, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 33000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_Q80 = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x01, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 33000, + .pdDelay = 20, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xef, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x01, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x31, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0x20, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x01, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 400, + .timeE32k = 1600, + .timeE64k = 2000, + .timePagePgm = 5, + .timeCe = 33000, + .pdDelay = 3, + .qeData = 0, +}; + +static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { + { + .jedecID = 0x134051, + .name = "GD_MD04D_04_33", + .cfg = &flashCfg_Gd_Md_40D, + }, + { + .jedecID = 0x1320c2, + .name = "MX_KH40_04_33", + .cfg = &flashCfg_MX_KH25, + }, + { + .jedecID = 0x1420c2, + .name = "MX_KH80_08_33", + .cfg = &flashCfg_MX_KH25, + }, + { + .jedecID = 0x1520c2, + .name = "MX_KH16_16_33", + .cfg = &flashCfg_MX_KH25, + }, + { + .jedecID = 0x1440A1, + .name = "FM_25Q80_80_33", + .cfg = &flashCfg_FM_Q80, + }, + { + .jedecID = 0x1570EF, + .name = "Winb_16JV_16_33", + .cfg = &flashCfg_Winb_16JV, + }, + { + .jedecID = 0x1870EF, + .name = "Winb_128JV_128_33", + .cfg = &flashCfg_Winb_16JV, + }, + { + .jedecID = 0x15605E, + .name = "ZB_VQ16_16_33", + .cfg = &flashCfg_Winb_16JV, + }, + { + .jedecID = 0x144020, + .name = "XM_25QH80_80_33", + .cfg = &flashCfg_Winb_16JV, + }, + { + .jedecID = 0x154020, + .name = "XM_25QH16_16_33", + .cfg = &flashCfg_Winb_16JV, + }, + { + .jedecID = 0x164020, + .name = "XM_25QH32_32_33", + .cfg = &flashCfg_Winb_16JV, + }, + { + .jedecID = 0x174020, + .name = "XM_25QH64_64_33", + .cfg = &flashCfg_Winb_16JV, + }, + { + .jedecID = 0x13325E, + .name = "ZB_D40B_80_33", + .cfg = &flashCfg_MX_KH25, + }, + { + .jedecID = 0x14325E, + .name = "ZB_D80B_80_33", + .cfg = &flashCfg_MX_KH25, + }, + { + .jedecID = 0x15405E, + .name = "ZB_25Q16B_15_33", + .cfg = &flashCfg_Winb_16JV, + }, + { + .jedecID = 0x16405E, + .name = "ZB_25Q32B_16_33", + .cfg = &flashCfg_Winb_16JV, + }, +}; + +/*@} end of group SF_CFG_EXT_Private_Variables */ + +/** @defgroup SF_CFG_EXT_Global_Variables + * @{ + */ + +/*@} end of group SF_CFG_EXT_Global_Variables */ + +/** @defgroup SF_CFG_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */ + +/** @defgroup SF_CFG_EXT_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Init internal flash GPIO + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = GPIO_FUN_GPIO, + .gpioMode = GPIO_MODE_INPUT, + .pullType = GPIO_PULL_NONE, + .drive = 0, + .smtCtrl = 1, + }; + + /* Turn on Flash pad, GPIO23 - GPIO28 */ + for (uint32_t pin = 23; pin < 29; pin++) { + gpioCfg.gpioPin = pin; + + if (pin == 25) { + gpioCfg.pullType = GPIO_PULL_DOWN; + } else { + gpioCfg.pullType = GPIO_PULL_NONE; + } + + GLB_GPIO_Init(&gpioCfg); + } +} + +/****************************************************************************/ /** + * @brief Get flash config according to flash ID + * + * @param flashID: Flash ID + * @param pFlashCfg: Flash config pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t i; + uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; + uint32_t crc, *pCrc; + + if (flashID == 0) { + XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); + + if (BL702_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { + crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); + pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); + + if (*pCrc == crc) { + BL702_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); + return SUCCESS; + } + } + } else { + if (SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS) { + /* 0x134051 flash cfg is wrong in rom, find again */ + if ((flashID&0xFFFFFF) != 0x134051) { + return SUCCESS; + } + } + + for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { + if (flashInfos[i].jedecID == flashID) { + BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + return SUCCESS; + } + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Identify one flash + * + * @param callFromFlash: code run at flash or ram + * @param autoScan: Auto scan all GPIO pin + * @param flashPinCfg: Specify flash GPIO config, not auto scan + * @param restoreDefault: Wether restore default flash GPIO config + * @param pFlashCfg: Flash config pointer + * + * @return Flash ID + * +*******************************************************************************/ +uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, + uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t jdecId = 0; + uint32_t i = 0; + uint32_t ret = 0; + + ret = SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg); + + if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) { + /* 0x134051 flash cfg is wrong in rom, find again */ + if ((ret&0xFFFFFF) != 0x134051) { + return ret; + } + } + + jdecId = (ret & 0xffffff); + + for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { + if (flashInfos[i].jedecID == jdecId) { + BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + break; + } + } + + if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { + return jdecId; + } else { + return (jdecId | BFLB_FLASH_ID_VALID_FLAG); + } +} + +/*@} end of group SF_CFG_EXT_Public_Functions */ + +/*@} end of group SF_CFG_EXT */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..95f01f5b8b8c98b734b4508d6b12f2b13ca59cbf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c @@ -0,0 +1,1449 @@ +/** + ****************************************************************************** + * @file bl702_sf_ctrl.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_sf_ctrl.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Private_Macros + * @{ + */ + +/*@} end of group SF_CTRL_Private_Macros */ + +/** @defgroup SF_CTRL_Private_Types + * @{ + */ + +/*@} end of group SF_CTRL_Private_Types */ + +/** @defgroup SF_CTRL_Private_Variables + * @{ + */ +#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) +#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x100) + +/*@} end of group SF_CTRL_Private_Variables */ + +/** @defgroup SF_CTRL_Global_Variables + * @{ + */ + +/*@} end of group SF_CTRL_Global_Variables */ + +/** @defgroup SF_CTRL_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CTRL_Private_Fun_Declaration */ + +/** @defgroup SF_CTRL_Private_Functions + * @{ + */ + +/*@} end of group SF_CTRL_Private_Functions */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Enable serail flash controller + * + * @param cfg: serial flash controller config + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + if (cfg == NULL) { + return; + } + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + if (cfg->clkDelay > 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); + } + + /* Serail out inverted, so sf ctrl send on negative edge */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); + + /* Set do di and oe delay */ + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3, tmpVal); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DO_DLY_SEL, cfg->doDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DI_DLY_SEL, cfg->diDelay); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_OE_DLY_SEL, cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4, tmpVal); + + /* Enable AHB access sram buffer and enable sf interface */ + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); + + SF_Ctrl_Set_Owner(cfg->owner); +} +#endif + +/****************************************************************************/ /** + * @brief Enable serail psram controller + * + * @param sfCtrlPsramCfg: serial psram controller config + * + * @return None + * +*******************************************************************************/ +//#ifndef BFLB_USE_ROM_DRIVER +//__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) +{ + uint32_t tmpVal = 0; + + SF_Ctrl_Select_Pad(sfCtrlPsramCfg->padSel); + SF_Ctrl_Select_Bank(sfCtrlPsramCfg->bankSel); + + /* Select psram clock delay */ + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12); + + if (sfCtrlPsramCfg->psramRxClkInvertSrc) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); + + if (sfCtrlPsramCfg->psramRxClkInvertSel) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); + } + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); + } + + if (sfCtrlPsramCfg->psramDelaySrc) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); + + if (sfCtrlPsramCfg->psramClkDelay > 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, sfCtrlPsramCfg->psramClkDelay - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); + } + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal); + + /* Enable AHB access sram buffer and enable sf interface */ + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); + + SF_Ctrl_Set_Owner(sfCtrlPsramCfg->owner); +} +//#endif + +/****************************************************************************/ /** + * @brief Get flash controller clock delay value + * + * @param None + * + * @return Clock delay value + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) { + return 0; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; + } +} +#endif + +/****************************************************************************/ /** + * @brief Set flash controller clock delay value + * + * @param delay: Clock delay value + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + if (delay > 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief SF Ctrl set cmds config + * + * @param cmdsCfg: SF Ctrl cmds config + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->wrapLen)); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); + + if (cmdsCfg->cmdsEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_EN); + } + + if (cmdsCfg->burstToggleEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_BT_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_BT_EN); + } + + if (cmdsCfg->wrapModeEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_WRAP_MODE); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_WRAP_MODE); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_WRAP_LEN, cmdsCfg->wrapLen); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief SF Ctrl pad select + * + * @param sel: pad select type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel) +{ + /* TODO: sf_if_bk_swap */ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_PAD_SELECT(sel)); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); + + if (sel <= SF_CTRL_PAD_SEL_SF3) { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel); + } else if (sel >= SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2 && sel <= SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel - SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2); + } else if (sel == SF_CTRL_PAD_SEL_DUAL_CS_SF2) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 1); + } else if (sel == SF_CTRL_PAD_SEL_DUAL_CS_SF3) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 2); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief SF Ctrl bank select + * + * @param sel: bank select type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Select_Bank(SF_Ctrl_Select sel) +{ + /* TODO: sf_if_bk_swap */ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_SELECT(sel)); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); + + if (sel == SF_CTRL_SEL_FLASH) { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Set flash controller owner:I/D AHB or system AHB + * + * @param owner: owner type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + /* Set owner */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner); + + /* Set iahb to flash interface */ + if (owner == SF_CTRL_OWNER_IAHB) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Disable flash controller + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Enable flash controller AES with big indian + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Enable flash controller AES with little indian + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Serial flash controller set AES region + * + * @param region: region number + * @param enable: enable or not + * @param hwKey: hardware key or software key + * @param startAddr: region start address + * @param endAddr: region end address + * @param locked: lock this region or not + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, + uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); + uint32_t tmpVal; + + if (!hwKey) { + regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); + } + + tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_CFG); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024); + /* sf_aes_end =1 means 1,11,1111,1111 */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked); + + BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_CFG, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Serial flash controller set AES key + * + * @param region: region number + * @param key: key data pointer + * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); + uint32_t tmpVal, i = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); + + if (NULL != key) { + if (keyType == SF_CTRL_AES_128BITS) { + i = 4; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + } else if (keyType == SF_CTRL_AES_256BITS) { + i = 8; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + } else if (keyType == SF_CTRL_AES_192BITS) { + i = 6; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + } + + tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; + + while (i--) { + BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); + key += 4; + tmpVal -= 4; + } + } +} +#endif + +/****************************************************************************/ /** + * @brief Serial flash controller set AES key with big endian + * + * @param region: region number + * @param key: key data pointer + * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); + uint32_t tmpVal, i = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); + + if (NULL != key) { + if (keyType == SF_CTRL_AES_128BITS) { + i = 4; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + */ + } else if (keyType == SF_CTRL_AES_256BITS) { + i = 8; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); + key+=4; + */ + } else if (keyType == SF_CTRL_AES_192BITS) { + i = 6; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); + */ + } + + tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; + + while (i--) { + BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); + key += 4; + tmpVal += 4; + } + } +} +#endif + +/****************************************************************************/ /** + * @brief Serial flash controller set AES iv + * + * @param region: region number + * @param iv: iv data pointer + * @param addrOffset: flash address offset + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); + uint32_t tmpVal, i = 3; + + if (iv != NULL) { + tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET; + + while (i--) { + BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); + iv += 4; + tmpVal -= 4; + } + + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + */ + BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); + iv += 4; + } +} +#endif + +/****************************************************************************/ /** + * @brief Serial flash controller set AES iv with big endian + * + * @param region: region number + * @param iv: iv data pointer + * @param addrOffset: flash address offset + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + /* Do flash key eco*/ + uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); + uint32_t tmpVal, i = 3; + + if (iv != NULL) { + tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET; + + while (i--) { + BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv)); + iv += 4; + tmpVal += 4; + } + + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + */ + BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); + iv += 4; + } +} +#endif + +/****************************************************************************/ /** + * @brief Enable serial flash controller AES + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Disable serial flash controller AES + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Check is serial flash controller AES enable + * + * @param None + * + * @return Wether AES is enable + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); + return BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN); +} +#endif + +/****************************************************************************/ /** + * @brief Set flash image offset + * + * @param addrOffset: Address offset value + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) +{ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); +} +#endif + +/****************************************************************************/ /** + * @brief Get flash image offset + * + * @param None + * + * @return :Address offset value + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) +{ + return BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); +} +#endif + +/****************************************************************************/ /** + * @brief SF controller send one command + * + * @param sahbType: Serial flash controller clock sahb sram select + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); + + if (sahbType == SF_CTRL_SAHB_CLOCK) { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL); + } else if (sahbType == SF_CTRL_FLASH_CLOCK) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL); + } + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief SF controller send one command + * + * @param cfg: Serial flash controller command configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) { + return; + } + + /* Clear trigger */ + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0); + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_1, cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_2, cfg->cmdBuf[1]); + + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE); + } + + if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { + if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_NIO_MODE); + } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DO_MODE); + } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QO_MODE); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DIO_MODE); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QIO_MODE); + } + + /* Configure cmd */ + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_CMD_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_CMD_BYTE, 0); + + /* Configure address */ + if (cfg->addrSize != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, cfg->addrSize - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, 0); + } + + /* Configure dummy */ + if (cfg->dummyClks != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, cfg->dummyClks - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, 0); + } + + /* Configure data */ + if (cfg->nbData != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, cfg->nbData - 1); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, 0); + } + + /* Set read write flag */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_RW, cfg->rwFlag); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); + + //switch sf_clk_sahb_sram_sel = 1 + SF_Ctrl_Select_Clock(SF_CTRL_FLASH_CLOCK); + /* Trigger */ + tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); + return; + } + } + + //switch sf_clk_sahb_sram_sel = 0 + SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); +} +#endif + +/****************************************************************************/ /** + * @brief Config SF controller for flash I/D cache read + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmdValid: command valid or not, for continous read, cache may need no command + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { + return; + } + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0); + + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); + } + + if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { + if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); + } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); + } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); + } + + if (cmdValid) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); + } + + /* Configure address */ + if (cfg->addrSize != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); + } + + /* configure dummy */ + if (cfg->dummyClks != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); + } + + /* Configure data */ + if (cfg->nbData != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); + } + + /* Set read write flag */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Config psram controller for psram I/D cache write + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmdValid: command valid or not, cache may need no command + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { + return; + } + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_4, cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_5, cfg->cmdBuf[1]); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3); + + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_SPI_MODE); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_QPI_MODE); + } + + if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { + if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_NIO_MODE); + } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DO_MODE); + } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QO_MODE); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DIO_MODE); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QIO_MODE); + } + + if (cmdValid) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0); + } + + /* Configure address */ + if (cfg->addrSize != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, cfg->addrSize - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, 0); + } + + /* configure dummy */ + if (cfg->dummyClks != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, cfg->dummyClks - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, 0); + } + + /* Configure data */ + if (cfg->nbData != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 0); + } + + /* Set read write flag */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_RW, cfg->rwFlag); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Config psram controller for psram I/D cache read + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmdValid: command valid or not, for continous read, cache may need no command + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); + + if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { + return; + } + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]); + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9); + + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); + } + + if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { + if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); + } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); + } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); + } + + if (cmdValid) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); + } + + /* Configure address */ + if (cfg->addrSize != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); + } + + /* configure dummy */ + if (cfg->dummyClks != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); + } + + /* Configure data */ + if (cfg->nbData != 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); + } + + /* Set read write flag */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); + + BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Get SF Ctrl busy state + * + * @param None + * + * @return SET for SF ctrl busy or RESET for SF ctrl not busy + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0); + + if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_BUSY)) { + return SET; + } else { + return RESET; + } +} +#endif + +/****************************************************************************/ /** + * @brief SF Controller interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void SF_Ctrl_IRQHandler(void) +{ + /* TODO: Not implemented */ +} +#endif + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash.c new file mode 100644 index 0000000000000000000000000000000000000000..6d157575001528a3c934edc0411a1fd1991667d6 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash.c @@ -0,0 +1,1530 @@ +/** + ****************************************************************************** + * @file bl702_sflash.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl702_sflash.h" +#include "bl702_sf_ctrl.h" +#include "bl702_l1c.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLASH + * @{ + */ + +/** @defgroup SFLASH_Private_Macros + * @{ + */ + +/*@} end of group SFLASH_Private_Macros */ + +/** @defgroup SFLASH_Private_Types + * @{ + */ + +/*@} end of group SFLASH_Private_Types */ + +/** @defgroup SFLASH_Private_Variables + * @{ + */ +#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) + +/*@} end of group SFLASH_Private_Variables */ + +/** @defgroup SFLASH_Global_Variables + * @{ + */ + +/*@} end of group SFLASH_Global_Variables */ + +/** @defgroup SFLASH_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SFLASH_Private_Fun_Declaration */ + +/** @defgroup SFLASH_Private_Functions + * @{ + */ + +/*@} end of group SFLASH_Private_Functions */ + +/** @defgroup SFLASH_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Init serial flash control interface + * + * @param pSfCtrlCfg: Serial flash controller configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) +{ + SF_Ctrl_Enable(pSfCtrlCfg); +} +#endif + +/****************************************************************************/ /** + * @brief Set serial flash control interface SPI or QPI mode + * + * @param mode: Serial flash interface mode + * + * @return BFLB_RET:SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) +{ + BL_Err_Type stat = SUCCESS; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); + + return stat; +} +#endif + +/****************************************************************************/ /** + * @brief Read flash register + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param regIndex: register index + * @param regValue: register value pointer to store data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24; + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + BL702_Delay_US(1); + cnt++; + + if (cnt > 1000) { + return ERROR; + } + } + + BL702_MemCpy(regValue, flashCtrlBuf, regLen); + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Write flash register + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param regIndex: register index + * @param regValue: register value pointer storing data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + BL702_MemCpy(flashCtrlBuf, regValue, regLen); + + flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24; + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* take 40ms for tw(write status register) as default */ + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(100); + cnt++; + + if (cnt > 400) { + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Read flash register with read command + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param readRegCmd: read command + * @param regValue: register value pointer to store data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = readRegCmd << 24; + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + BL702_Delay_US(1); + cnt++; + + if (cnt > 1000) { + return ERROR; + } + } + + BL702_MemCpy(regValue, flashCtrlBuf, regLen); + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Write flash register with write command + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param writeRegCmd: write command + * @param regValue: register value pointer storing data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + BL702_MemCpy(flashCtrlBuf, regValue, regLen); + + flashCmd.cmdBuf[0] = writeRegCmd << 24; + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* take 40ms for tw(write status register) as default */ + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(100); + cnt++; + + if (cnt > 400) { + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Check flash busy status + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SET for busy or RESET for not busy + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat = 0; + SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen); + + if ((stat & (1 << flashCfg->busyBit)) == 0) { + return RESET; + } + + return SET; +} +#endif + +/****************************************************************************/ /** + * @brief Enable flash write function + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + /* Write enable*/ + flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24; + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + SF_Ctrl_SendCmd(&flashCmd); + + SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen); + + if ((stat & (1 << flashCfg->wrEnableBit)) != 0) { + return SUCCESS; + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Enable flash flash controller QSPI interface + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat = 0, ret; + + if (flashCfg->qeReadRegLen == 0) { + ret = SFlash_Write_Enable(flashCfg); + + if (SUCCESS != ret) { + return ERROR; + } + + SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); + return SUCCESS; + } + + SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); + + if (flashCfg->qeData == 0) { + if ((stat & (1 << flashCfg->qeBit)) != 0) { + return SUCCESS; + } + } else { + if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { + return SUCCESS; + } + } + + if (flashCfg->qeWriteRegLen != 1) { + /* This is read r0,read r1 write r0,r1 case*/ + SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); + SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); + + if (flashCfg->qeData == 0) { + stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)); + } else { + stat = stat & (~(0xff << (8 * flashCfg->qeIndex))); + stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex)); + } + } else { + if (flashCfg->qeData == 0) { + stat |= (1 << (flashCfg->qeBit % 8)); + } else { + stat = flashCfg->qeData; + } + } + + ret = SFlash_Write_Enable(flashCfg); + + if (SUCCESS != ret) { + return ERROR; + } + + SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); + SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); + + if (flashCfg->qeData == 0) { + if ((stat & (1 << flashCfg->qeBit)) != 0) { + return SUCCESS; + } + } else { + if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { + return SUCCESS; + } + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Enable flash volatile register write enable + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24; + flashCmd.rwFlag = SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); +} +#endif + +/****************************************************************************/ /** + * @brief Erase flash whole chip + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24; + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(500); + cnt++; + + if (cnt > flashCfg->timeCe * 3) { + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Erase flash one sector + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param secNum: flash sector number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) +{ + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(500); + cnt++; + + if (cnt > flashCfg->timeEsector * 3) { + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Erase flash one 32K block + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param blkNum: flash 32K block number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(500); + cnt++; + + if (cnt > flashCfg->timeE32k * 3) { + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Erase flash one 64K block + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param blkNum: flash 64K block number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(500); + cnt++; + + if (cnt > flashCfg->timeE64k * 3) { + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Erase flash one region + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param startaddr: start address to erase + * @param endaddr: end address(include this address) to erase + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) +{ + uint32_t len = 0; + uint32_t eraseLen = 0; + BL_Err_Type ret = SUCCESS; + + while (startaddr <= endaddr) { + len = endaddr - startaddr + 1; + + if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && + (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && + len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { + /* 64K margin address,and length > 64K-sector size, erase one first */ + ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); + eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; + } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && + (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && + len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { + /* 32K margin address,and length > 32K-sector size, erase one first */ + ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); + eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; + } else { + /* Sector erase */ + startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); + ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); + eraseLen = flashCfg->sectorSize * 1024; + } + + startaddr += eraseLen; + + if (ret != SUCCESS) { + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Program flash one region + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: progran mode:SPI mode or QPI mode + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t i = 0, curLen = 0; + uint32_t cnt = 0; + BL_Err_Type stat; + uint8_t cmd; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { + cmd = flashCfg->pageProgramCmd; + } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) { + flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->qpageProgramCmd; + } else { + return ERROR; + } + + /* Prepare command */ + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.addrSize = 3; + + for (i = 0; i < len;) { + /* Write enable is needed for every program */ + stat = SFlash_Write_Enable(flashCfg); + + if (stat != SUCCESS) { + return stat; + } + + /* Get current programmed length within page size */ + curLen = flashCfg->pageSize - addr % flashCfg->pageSize; + + if (curLen > len - i) { + curLen = len - i; + } + + /* Prepare command */ + BL702_MemCpy_Fast(flashCtrlBuf, data, curLen); + flashCmd.cmdBuf[0] = (cmd << 24) | (addr); + flashCmd.nbData = curLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* Adjust address and programmed length */ + addr += curLen; + i += curLen; + data += curLen; + + /* Wait for write done */ + cnt = 0; + + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(100); + cnt++; + + if (cnt > flashCfg->timePagePgm * 20) { + return ERROR; + } + } + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get flash unique ID + * + * @param data: data pointer to store read data + * @param idLen: unique ID len + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + dummyClks = 4; + cmd = 0x4B; + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = idLen; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + BL702_MemCpy(data, flashCtrlBuf, idLen); +} +#endif + +/****************************************************************************/ /** + * @brief Get flash jedec ID + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param data: data pointer to store read data + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + dummyClks = flashCfg->jedecIdCmdDmyClk; + cmd = flashCfg->jedecIdCmd; + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + BL702_MemCpy(data, flashCtrlBuf, 3); +} +#endif + +/****************************************************************************/ /** + * @brief Get flash device ID + * + * @param data: data pointer to store read data + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t addr = 0x00000001; + uint8_t readMode = 0xFF; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + dummyClks = 2; + cmd = 0x94; + flashCmd.cmdBuf[0] = (cmd << 24) | (addr); + flashCmd.cmdBuf[1] = (readMode << 24); + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 4; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = 2; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } + + BL702_MemCpy(data, flashCtrlBuf, 2); +} +#endif + +/****************************************************************************/ /** + * @brief Set flash power down + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_Powerdown(void) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t cmd = 0; + uint32_t timeOut = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + cmd = 0xB9; + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } +} +#endif + +/****************************************************************************/ /** + * @brief Release flash power down for wake up + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t cmd; + uint32_t timeOut = 0; + + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + cmd = flashCfg->releasePowerDown; + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return; + } + } +} +#endif + +/****************************************************************************/ /** + * @brief Sflash restore from power down + * + * @param pFlashCfg: Flash configuration pointer + * @param flashContRead: Whether enable continuous read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) +{ + BL_Err_Type stat = SUCCESS; + uint32_t jdecId = 0; + uint8_t tmp[8]; + uint8_t ioMode = pFlashCfg->ioMode & 0xf; + + /* Wake flash up from power down */ + SFlash_Releae_Powerdown(pFlashCfg); + BL702_Delay_US(120); + + SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); + + if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) { + SFlash_Qspi_Enable(pFlashCfg); + } + + if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) { + /* unwrap */ + L1C_Set_Wrap(DISABLE); + } else { + /* burst wrap */ + L1C_Set_Wrap(ENABLE); + /* For command that is setting register instead of send command, we need write enable */ + SFlash_Write_Enable(pFlashCfg); + SFlash_SetBurstWrap(pFlashCfg); + } + + if (flashContRead) { + stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); + } else { + stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32); + } + + return stat; +} +#endif + +/****************************************************************************/ /** + * @brief Set flash burst wrap config + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t wrapData; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((flashCfg->ioMode >> 4) & 0x01) == 1) { + /* Disable burst wrap ,just return */ + return; + } + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; + flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; + dummyClks = flashCfg->burstWrapCmdDmyClk; + cmd = flashCfg->burstWrapCmd; + wrapData = flashCfg->burstWrapData; + BL702_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = 1; + + SF_Ctrl_SendCmd(&flashCmd); +} +#endif + +/****************************************************************************/ /** + * @brief Disable flash burst wrap config + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd, dummyClks; + uint32_t wrapData; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; + flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; + dummyClks = flashCfg->deBurstWrapCmdDmyClk; + cmd = flashCfg->deBurstWrapCmd; + wrapData = flashCfg->deBurstWrapData; + BL702_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); + flashCmd.cmdBuf[0] = (cmd << 24); + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = 1; + + SF_Ctrl_SendCmd(&flashCmd); +} +#endif + +/****************************************************************************/ /** + * @brief Software reset flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) +{ + uint16_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + /* Reset enable */ + flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24; + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + + /* Wait for write done */ + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(100); + cnt++; + + if (cnt > 20) { + return ERROR; + } + } + + SF_Ctrl_SendCmd(&flashCmd); + + /* Reset */ + flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24; + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + SF_Ctrl_SendCmd(&flashCmd); + + BL702_Delay_US(50); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Reset flash continous read mode + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + /* Reset continous read */ + BL702_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = flashCfg->resetCreadCmdSize; + SF_Ctrl_SendCmd(&flashCmd); +} +#endif + +/****************************************************************************/ /** + * @brief Set I/D bus read flash configuration in flash controller + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param addr: address to read/write + * @param len: data length to read/write + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) +{ + uint8_t cmd, dummyClks; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t cmdValid = 1; + uint8_t noReadModeCfg = 0; + uint8_t cReadSupport = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); + + if (SF_CTRL_NIO_MODE == ioMode) { + cmd = flashCfg->fastReadCmd; + dummyClks = flashCfg->frDmyClk; + } else if (SF_CTRL_DO_MODE == ioMode) { + flashCmd.dataMode = SF_CTRL_DATA_2_LINES; + cmd = flashCfg->fastReadDoCmd; + dummyClks = flashCfg->frDoDmyClk; + } else if (SF_CTRL_DIO_MODE == ioMode) { + flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; + flashCmd.dataMode = SF_CTRL_DATA_2_LINES; + cmd = flashCfg->fastReadDioCmd; + dummyClks = flashCfg->frDioDmyClk; + } else if (SF_CTRL_QO_MODE == ioMode) { + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->fastReadQoCmd; + dummyClks = flashCfg->frQoDmyClk; + } else if (SF_CTRL_QIO_MODE == ioMode) { + flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->fastReadQioCmd; + dummyClks = flashCfg->frQioDmyClk; + } else { + return ERROR; + } + + /*prepare command**/ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + flashCmd.cmdBuf[0] = (cmd << 24) | addr; + + if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { + noReadModeCfg = flashCfg->cReadSupport & 0x02; + cReadSupport = flashCfg->cReadSupport & 0x01; + + if (noReadModeCfg == 0) { + /* Read mode must be set*/ + if (cReadSupport == 0) { + /* Not support cont read,but we still need set read mode(winbond 80dv)*/ + flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); + } else { + /* Flash support cont read, setting depend on user parameter */ + if (contRead) { + flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode; + cmdValid = 0; + } else { + flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); + } + } + + flashCmd.addrSize++; + } + } + + flashCmd.dummyClks = dummyClks; + flashCmd.nbData = len; + SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Enable I/D bus read from flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) +{ + BL_Err_Type stat; + + stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 4); + + if (SUCCESS != stat) { + return stat; + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Enable cache read from flash with cache + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param wayDisable: cache way disable config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) +{ + BL_Err_Type stat; + + /* Cache now only support 32 bytes read */ + stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32); + + if (SUCCESS != stat) { + return stat; + } + + return L1C_Cache_Enable_Set(wayDisable); +} +#endif + +/****************************************************************************/ /** + * @brief Disable read from flash with cache + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) +{ + L1C_Cache_Read_Disable(); +} +#endif + +/****************************************************************************/ /** + * @brief Read data from flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t curLen, i; + uint8_t cmd, dummyClks; + uint32_t timeOut = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t noReadModeCfg = 0; + uint8_t cReadSupport = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + if (SF_CTRL_NIO_MODE == ioMode) { + cmd = flashCfg->fastReadCmd; + dummyClks = flashCfg->frDmyClk; + } else if (SF_CTRL_DO_MODE == ioMode) { + flashCmd.dataMode = SF_CTRL_DATA_2_LINES; + cmd = flashCfg->fastReadDoCmd; + dummyClks = flashCfg->frDoDmyClk; + } else if (SF_CTRL_DIO_MODE == ioMode) { + flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; + flashCmd.dataMode = SF_CTRL_DATA_2_LINES; + cmd = flashCfg->fastReadDioCmd; + dummyClks = flashCfg->frDioDmyClk; + } else if (SF_CTRL_QO_MODE == ioMode) { + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->fastReadQoCmd; + dummyClks = flashCfg->frQoDmyClk; + } else if (SF_CTRL_QIO_MODE == ioMode) { + flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode = SF_CTRL_DATA_4_LINES; + cmd = flashCfg->fastReadQioCmd; + dummyClks = flashCfg->frQioDmyClk; + } else { + return ERROR; + } + + /* Prepare command */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { + noReadModeCfg = flashCfg->cReadSupport & 0x02; + cReadSupport = flashCfg->cReadSupport & 0x01; + + if (noReadModeCfg == 0) { + /* Read mode must be set*/ + if (cReadSupport == 0) { + /* Not support cont read,but we still need set read mode(winbond 80dv)*/ + flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); + } else { + /* Flash support cont read, setting depend on user parameter */ + if (contRead) { + flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); + } else { + flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); + } + } + + flashCmd.addrSize++; + } + } + + flashCmd.dummyClks = dummyClks; + + /* Read data */ + for (i = 0; i < len;) { + /* Prepare command */ + flashCmd.cmdBuf[0] = (cmd << 24) | (addr); + curLen = len - i; + + if (curLen >= FLASH_CTRL_BUF_SIZE) { + curLen = FLASH_CTRL_BUF_SIZE; + flashCmd.nbData = curLen; + } else { + /* Make sf_ctrl word read */ + flashCmd.nbData = ((curLen + 3) >> 2) << 2; + } + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + + while (SET == SF_Ctrl_GetBusyState()) { + timeOut--; + + if (timeOut == 0) { + return TIMEOUT; + } + } + + BL702_MemCpy_Fast(data, flashCtrlBuf, curLen); + + addr += curLen; + i += curLen; + data += curLen; + } + + return SUCCESS; +} +#endif + +/*@} end of group SFLASH_Public_Functions */ + +/*@} end of group SFLASH */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c new file mode 100644 index 0000000000000000000000000000000000000000..e25ad8859803992b649e033a0b9aa709a36840cf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c @@ -0,0 +1,181 @@ +/** + ****************************************************************************** + * @file bl702_sflash_ext.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_sflash_ext.h" +#include "bl702_sf_ctrl.h" +#include "l1c_reg.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLASH_EXT + * @{ + */ + +/** @defgroup SFLASH_EXT_Private_Macros + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Macros */ + +/** @defgroup SFLASH_EXT_Private_Types + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Types */ + +/** @defgroup SFLASH_EXT_Private_Variables + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Variables */ + +/** @defgroup SFLASH_EXT_Global_Variables + * @{ + */ + +/*@} end of group SFLASH_EXT_Global_Variables */ + +/** @defgroup SFLASH_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Fun_Declaration */ + +/** @defgroup SFLASH_EXT_Private_Functions + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Functions */ + +/** @defgroup SFLASH_EXT_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Read flash register with read command + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param readRegCmd: read command + * @param regValue: register value pointer to store data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt = 0; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0] = readRegCmd << 24; + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + while (SET == SF_Ctrl_GetBusyState()) { + BL702_Delay_US(1); + cnt++; + + if (cnt > 1000) { + return ERROR; + } + } + + BL702_MemCpy(regValue, flashCtrlBuf, regLen); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Write flash register with write command + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param writeRegCmd: write command + * @param regValue: register value pointer storing data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) +{ + uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t cnt = 0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if (((uint32_t)&flashCmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + } else { + BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + BL702_MemCpy(flashCtrlBuf, regValue, regLen); + + flashCmd.cmdBuf[0] = writeRegCmd << 24; + flashCmd.rwFlag = SF_CTRL_WRITE; + flashCmd.nbData = regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* take 40ms for tw(write status register) as default */ + while (SET == SFlash_Busy(flashCfg)) { + BL702_Delay_US(100); + cnt++; + + if (cnt > 400) { + return ERROR; + } + } + + return SUCCESS; +} + +/*@} end of group SFLASH_EXT_Public_Functions */ + +/*@} end of group SFLASH_EXT */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_snflash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_snflash.c new file mode 100644 index 0000000000000000000000000000000000000000..4489a6d1cae5bb386352b60dca04bd5f2e4e414f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_snflash.c @@ -0,0 +1,890 @@ +/** + ****************************************************************************** + * @file bl702_snflash.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_snflash.h" +#include "bl702_psram.h" + +#define PSRAM_ADDR (0x24000000) +#define DISK_SECTOR_SIZE (512) +#define PSRAM_READ_ERITE_SIZE (256) + +static void Nandflash_Erase(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum); +static void Nandflash_PageReadToPsram(uint32_t addr, uint32_t len); +static void ATTR_TCM_SECTION Nandflash_Psram_Write(uint8_t *buff, uint32_t len, uint32_t psramWriteOffsite); +static void ATTR_TCM_SECTION Nandflash_Psram_Read(uint8_t *buff, uint32_t readLen, uint32_t psramReadOffsite); +static void Nandflash_PageWriteToPsram(const uint8_t *buff, uint32_t addr, uint32_t len); +static void Nandflash_PageProgramFromPsram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum); + +NANDFLASH_CFG_Type nfCfg = { + .spiNo = SPI_ID_0, + .spiCfg = { + DISABLE, /* Disable de-glitch function */ + DISABLE, /* Disable master continuous transfer mode */ + SPI_BYTE_INVERSE_BYTE0_FIRST, /* The byte 0 is sent first in SPI transfer */ + SPI_BIT_INVERSE_MSB_FIRST, /* MSB is sent first in SPI transfer */ + SPI_CLK_PHASE_INVERSE_0, /* SPI clock phase */ + SPI_CLK_POLARITY_LOW, /* SPI clock plarity */ + SPI_FRAME_SIZE_8 /* SPI frame size 8-bit(also the valid width for each fifo entry) */ + }, + .clockCfg = { + 1, /* Length of start condition */ + 1, /* Length of stop condition */ + 1, /* Length of data phase 0,affecting clock */ + 1, /* Length of data phase 1,affecting clock */ + 1 /* Length of interval between frame */ + } +}; + +static void ATTR_TCM_SECTION Nandflash_Psram_Write(uint8_t *buff, uint32_t len, uint32_t psramWriteOffsite) +{ + uint32_t i = 0; + uint32_t psramStartAddr = PSRAM_ADDR + psramWriteOffsite; + + for (i = 0; i < len / PSRAM_READ_ERITE_SIZE; i++) { + BL702_MemCpy_Fast((void *)(psramStartAddr + i * PSRAM_READ_ERITE_SIZE), buff, PSRAM_READ_ERITE_SIZE); + buff += PSRAM_READ_ERITE_SIZE; + } + + /*if len is not an integral multiple of PSRAM_READ_ERITE_SIZE need memcpy once again*/ + if (len % PSRAM_READ_ERITE_SIZE != 0) { + BL702_MemCpy_Fast((void *)(psramStartAddr + i * PSRAM_READ_ERITE_SIZE), buff, len % PSRAM_READ_ERITE_SIZE); + buff += (len % PSRAM_READ_ERITE_SIZE); + } +} + +static void ATTR_TCM_SECTION Nandflash_Psram_Read(uint8_t *buff, uint32_t readLen, uint32_t psramReadOffsite) +{ + uint32_t i = 0; + uint32_t psramStartAddr = PSRAM_ADDR + psramReadOffsite; + + for (i = 0; i < readLen / PSRAM_READ_ERITE_SIZE; i++) { + BL702_MemCpy_Fast(buff, (void *)(psramStartAddr + i * PSRAM_READ_ERITE_SIZE), PSRAM_READ_ERITE_SIZE); + buff += PSRAM_READ_ERITE_SIZE; + } + + /*if len is not an integral multiple of PSRAM_READ_ERITE_SIZE need memcpy once again*/ + if (readLen % PSRAM_READ_ERITE_SIZE != 0) { + BL702_MemCpy_Fast(buff, (void *)(psramStartAddr + i * PSRAM_READ_ERITE_SIZE), readLen % PSRAM_READ_ERITE_SIZE); + } +} + +void ATTR_TCM_SECTION Nandflash_Psram_Cfg() +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_17, + .gpioFun = GPIO17_FUN_SF_IO_0_SF2_CS2, + .gpioMode = GPIO_MODE_OUTPUT, + .pullType = GPIO_PULL_UP, + .drive = 3, + .smtCtrl = 1, + }; + + SPI_Psram_Cfg_Type apMemory1604 = { + .readIdCmd = 0x9F, + .readIdDmyClk = 0, + .burstToggleCmd = 0xC0, + .resetEnableCmd = 0x66, + .resetCmd = 0x99, + .enterQuadModeCmd = 0x35, + .exitQuadModeCmd = 0xF5, + .readRegCmd = 0xB5, + .readRegDmyClk = 1, + .writeRegCmd = 0xB1, + .readCmd = 0x03, + .readDmyClk = 0, + .fReadCmd = 0x0B, + .fReadDmyClk = 1, + .fReadQuadCmd = 0xEB, + .fReadQuadDmyClk = 3, + .writeCmd = 0x02, + .quadWriteCmd = 0x38, + .pageSize = 512, + .ctrlMode = PSRAM_SPI_CTRL_MODE, + .driveStrength = PSRAM_DRIVE_STRENGTH_50_OHMS, + .burstLength = PSRAM_BURST_LENGTH_512_BYTES, + }; + + SF_Ctrl_Cmds_Cfg cmdsCfg = { + .cmdsEn = ENABLE, + .burstToggleEn = ENABLE, + .wrapModeEn = DISABLE, + .wrapLen = SF_CTRL_WRAP_LEN_512, + }; + + SF_Ctrl_Psram_Cfg sfCtrlPsramCfg = { + .owner = SF_CTRL_OWNER_SAHB, + .padSel = SF_CTRL_PAD_SEL_DUAL_CS_SF2, + .bankSel = SF_CTRL_SEL_PSRAM, + .psramRxClkInvertSrc = ENABLE, + .psramRxClkInvertSel = ENABLE, + .psramDelaySrc = ENABLE, + .psramClkDelay = 0, + }; + uint8_t psramId[8] = { 0 }; + uint32_t wt_en = 1; + uint32_t wb_en = 0; + uint32_t wa_en = 0; + uint32_t i = 0; + + GLB_GPIO_Init(&gpioCfg); + + Psram_Init(&apMemory1604, &cmdsCfg, &sfCtrlPsramCfg); + Psram_SoftwareReset(&apMemory1604, apMemory1604.ctrlMode); + Psram_ReadId(&apMemory1604, psramId); + + Psram_Cache_Write_Set(&apMemory1604, SF_CTRL_QIO_MODE, wt_en, wb_en, wa_en); + L1C_Cache_Enable_Set(0x0f); +} + +void Nandflash_Gpio_Init(GLB_GPIO_Type clk, GLB_GPIO_Type mosi, GLB_GPIO_Type miso) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = GPIO_FUN_SPI0, + .gpioMode = GPIO_MODE_OUTPUT, + .pullType = GPIO_PULL_NONE, + .drive = 0, + .smtCtrl = 1 + }; + + /* cs */ + gpioCfg.gpioPin = SPI_PIN_CS; + gpioCfg.gpioFun = 11; + GLB_GPIO_Init(&gpioCfg); + GLB_GPIO_INPUT_Disable(gpioCfg.gpioPin); + GLB_GPIO_OUTPUT_Enable(gpioCfg.gpioPin); + Nandflash_CS_High(); + + /* clk */ + gpioCfg.gpioPin = clk; + gpioCfg.gpioFun = GPIO_FUN_SPI0; + GLB_GPIO_Init(&gpioCfg); + GLB_GPIO_INPUT_Disable(gpioCfg.gpioPin); + GLB_GPIO_OUTPUT_Enable(gpioCfg.gpioPin); + + /* mosi */ + gpioCfg.gpioPin = mosi; + gpioCfg.gpioFun = GPIO_FUN_SPI0; + GLB_GPIO_Init(&gpioCfg); + GLB_GPIO_INPUT_Enable(gpioCfg.gpioPin); + GLB_GPIO_OUTPUT_Enable(gpioCfg.gpioPin); + + /* miso */ + gpioCfg.gpioPin = miso; + gpioCfg.gpioFun = GPIO_FUN_SPI0; + GLB_GPIO_Init(&gpioCfg); + GLB_GPIO_INPUT_Enable(gpioCfg.gpioPin); + GLB_GPIO_OUTPUT_Enable(gpioCfg.gpioPin); + + GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER); +} + +void Nandflash_CS_High(void) +{ + GLB_GPIO_Write(SPI_PIN_CS, 1); +} + +void Nandflash_CS_Low(void) +{ + GLB_GPIO_Write(SPI_PIN_CS, 0); +} + +void Nandflash_Clock_Init(uint8_t enable, uint8_t div) +{ + GLB_Set_SPI_CLK(enable, div); + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_SPI); +} + +void Nandflash_SPI_Init(NANDFLASH_CFG_Type *pNandflashCfg) +{ + SPI_Disable(SPI_ID_0, SPI_WORK_MODE_MASTER); + SPI_IntMask(SPI_ID_0, SPI_INT_ALL, MASK); + SPI_Init(pNandflashCfg->spiNo, &(pNandflashCfg->spiCfg)); + SPI_ClockConfig(pNandflashCfg->spiNo, &(pNandflashCfg->clockCfg)); + SPI_Enable(SPI_ID_0, SPI_WORK_MODE_MASTER); +} + +void Nandflash_SendRecv(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t len) +{ + SPI_SendRecv_8bits(pNandflashCfg->spiNo, sendBuff, recvBuff, len, SPI_TIMEOUT_DISABLE); +} + +void Nandflash_WriteEnable(NANDFLASH_CFG_Type *pNandflashCfg) +{ + uint8_t cmd[1] = { 0 }; + uint8_t pBlockLock = 0xff; + + cmd[0] = NANDFLASH_WRITE_ENABLE; + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 1, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + /*check block lock status*/ + Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock); + + if (pBlockLock != 0) { + // MSG_ERR("Get BlockLock in Nandflash Write Enable and return %0x\r\n", pBlockLock); + } +} + +void Nandflash_WriteDisable(NANDFLASH_CFG_Type *pNandflashCfg) +{ + uint8_t cmd[1] = { 0 }; + + cmd[0] = NANDFLASH_WRITE_DISABLE; + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 1, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); +} + +void Nandflash_Get_BlockLock(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pBlockLock) +{ + uint8_t cmd[2] = { 0 }; + uint8_t ack[1] = { 0 }; + + cmd[0] = NANDFLASH_GET_FEATURES; + cmd[1] = NANDFLASH_BLOCK_LOCK_ADDR; + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 2, SPI_TIMEOUT_DISABLE); + SPI_Recv_8bits(pNandflashCfg->spiNo, ack, 1, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + *pBlockLock = ack[0]; +} + +void Nandflash_Set_BlockLock(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pBlockLock) +{ + uint8_t cmd[3] = { 0 }; + + cmd[0] = NANDFLASH_SET_FEATURES; + cmd[1] = NANDFLASH_BLOCK_LOCK_ADDR; + cmd[2] = *pBlockLock; + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 3, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); +} + +void Nandflash_Get_Feature(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pFeature) +{ + uint8_t cmd[2] = { 0 }; + uint8_t ack[1] = { 0 }; + + cmd[0] = NANDFLASH_GET_FEATURES; + cmd[1] = NANDFLASH_FEATURE_ADDR; + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 2, SPI_TIMEOUT_DISABLE); + SPI_Recv_8bits(pNandflashCfg->spiNo, ack, 1, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + *pFeature = ack[0]; +} + +void Nandflash_Set_Feature(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pFeature) +{ + uint8_t cmd[3] = { 0 }; + + cmd[0] = NANDFLASH_GET_FEATURES; + cmd[1] = NANDFLASH_FEATURE_ADDR; + cmd[2] = *pFeature; + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 3, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); +} + +void Nandflash_Get_Status(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pStatus) +{ + uint8_t cmd[2] = { 0 }; + uint8_t ack[1] = { 0 }; + + cmd[0] = NANDFLASH_GET_FEATURES; + cmd[1] = NANDFLASH_STATUS_ADDR; + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 2, SPI_TIMEOUT_DISABLE); + SPI_Recv_8bits(pNandflashCfg->spiNo, ack, 1, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + *pStatus = ack[0]; +} + +void Nandflash_Set_Status(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pStatus) +{ + uint8_t cmd[3] = { 0 }; + + cmd[0] = NANDFLASH_GET_FEATURES; + cmd[1] = NANDFLASH_STATUS_ADDR; + cmd[2] = *pStatus; + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 3, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); +} + +NANDFLASH_ECC_Type Nandflash_CheckBadBlock(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum, uint8_t *buff, uint32_t len) +{ + uint32_t pageNum = 0, pageAddr = 0; + NANDFLASH_ECC_Type ecc = 0; + + pageNum = blockNum * NANDFLASH_PAGES_PER_BLOCK; + + pageAddr = pageNum * NANDFLASH_PAGE_SIZE; + + if (len) { + //read to cache + ecc = Nandflash_PageReadToCache(pNandflashCfg, pageAddr); + + /* read from cache */ + Nandflash_ReadFromCache(pNandflashCfg, NANDFLASH_PAGE_SIZE, buff, len); + } + + return ecc; +} + +NANDFLASH_ECC_Type Nandflash_PageRead(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len) +{ + NANDFLASH_ECC_Type ecc = 0; + uint32_t pageAddr = addr & 0xFFFFF800; + uint32_t readLen = 0; + uint32_t pageOffset = addr - pageAddr; + + if ((pageOffset + len) <= NANDFLASH_PAGE_SIZE) { + readLen = len; + } else { + readLen = NANDFLASH_PAGE_SIZE - pageOffset; + } + + memset(buff, 0, len); + + if (readLen) { + /* read to cache */ + ecc = Nandflash_PageReadToCache(pNandflashCfg, pageAddr); + + /* read from cache */ + Nandflash_ReadFromCache(pNandflashCfg, pageOffset, buff, readLen); + } + + return ecc; +} + +NANDFLASH_ECC_Type Nandflash_PagesRead(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len) +{ + NANDFLASH_ECC_Type ecc = 0; + uint32_t startPageNum = 0, endPageNum = 0, absolutePageNum = 0; + uint32_t readLen = 0, pageOffset = 0, beginAddr = addr; + + startPageNum = addr / NANDFLASH_PAGE_SIZE; + endPageNum = (addr + len - 1) / NANDFLASH_PAGE_SIZE; + + memset(buff, 0, len); + + if (len > 0) { + for (absolutePageNum = startPageNum; absolutePageNum <= endPageNum; absolutePageNum++) { + pageOffset = addr % NANDFLASH_PAGE_SIZE; + + if (absolutePageNum == startPageNum) { + if (beginAddr + len >= NANDFLASH_PAGE_SIZE) { + readLen = (startPageNum + 1) * NANDFLASH_PAGE_SIZE - beginAddr; + } else { + readLen = len; + } + } else if ((startPageNum < absolutePageNum) && (absolutePageNum < endPageNum)) { + readLen = NANDFLASH_PAGE_SIZE; + } else if (absolutePageNum == endPageNum) { + readLen = (beginAddr + len) - (endPageNum * NANDFLASH_PAGE_SIZE); + } + + /* read to cache */ + ecc = Nandflash_PageReadToCache(pNandflashCfg, absolutePageNum * NANDFLASH_PAGE_SIZE); + /* read from cache */ + Nandflash_ReadFromCache(pNandflashCfg, pageOffset, buff, readLen); + + addr = (absolutePageNum + 1) * NANDFLASH_PAGE_SIZE; + buff += readLen; + } + } + + return ecc; +} +NANDFLASH_ECC_Type Nandflash_PageReadToCache(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr) +{ + uint8_t feature = 0; + uint8_t cmd[4] = { 0 }; + uint8_t status = 0xff; + uint8_t pBlockLock = 0xff; + NANDFLASH_ECC_Type ecc = 0; + uint32_t blockNum = 0; + uint32_t pageNum = 0; + uint32_t absolutePageNum = 0; + uint16_t cmds = 0; + /* enable ECC */ + Nandflash_Get_Feature(pNandflashCfg, &feature); + ((NANDFLASH_FEATURE_Type *)(&feature))->ECC_EN = 1; + Nandflash_Set_Feature(pNandflashCfg, &feature); + + absolutePageNum = addr / NANDFLASH_PAGE_SIZE; + blockNum = absolutePageNum / NANDFLASH_PAGES_PER_BLOCK; + pageNum = absolutePageNum % NANDFLASH_PAGES_PER_BLOCK; + /* page read to cache */ + cmd[0] = NANDFLASH_PAGE_READ_TO_CACHE; + cmd[1] = NANDFLASH_DUMMY_BYTE; + cmds = (uint16_t)(blockNum << 6) | (uint16_t)pageNum; + cmd[2] = (uint8_t)(cmds >> 8); + cmd[3] = (uint8_t)(cmds >> 0); + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 4, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + /*check block lock status*/ + Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock); + + if (pBlockLock != 0) { + // MSG_ERR("Get BlockLock in Nandflash PageRead To Cache and return %0x\r\n", pBlockLock); + } + + BL702_Delay_MS(20); + + /* Operation In Progress */ + do { + Nandflash_Get_Status(pNandflashCfg, &status); + } while ((((NANDFLASH_STATUS_Type *)(&status))->OIP)); + + /* get ecc */ + Nandflash_Get_Status(pNandflashCfg, &status); + ecc = status; + + return ecc; +} + +void Nandflash_ReadFromCache(NANDFLASH_CFG_Type *pNandflashCfg, uint16_t offset, uint8_t *buff, uint32_t len) +{ + uint32_t readLen = len; + uint8_t cmd[4] = { 0 }; + uint8_t pBlockLock = 0xff; + + if (!buff) { + return; + } + + if (readLen > NANDFLASH_PAGE_SIZE) { + readLen = NANDFLASH_PAGE_SIZE; + } + + /* read from cache */ + cmd[0] = NANDFLASH_READ_FROM_CACHE; + cmd[1] = (uint8_t)((offset >> 8) & 0x0F); + cmd[2] = (uint8_t)((offset >> 0) & 0xFF); + cmd[3] = NANDFLASH_DUMMY_BYTE; + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 4, SPI_TIMEOUT_DISABLE); + SPI_Recv_8bits(pNandflashCfg->spiNo, buff, readLen, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + /*check block lock status*/ + Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock); + + if (pBlockLock != 0) { + // MSG_ERR("Get BlockLock in Nandflash Read From Cache Erase and return %0x\r\n", pBlockLock); + } +} + +void Nandflash_ReadID(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pManufactureID, uint8_t *pDeviceID) +{ + uint8_t cmd[2] = { 0 }; + uint8_t ack[2] = { 0 }; + + cmd[0] = NANDFLASH_READ_ID; + cmd[1] = NANDFLASH_DUMMY_BYTE; + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 2, SPI_TIMEOUT_DISABLE); + SPI_Recv_8bits(pNandflashCfg->spiNo, ack, 2, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + *pManufactureID = ack[0]; + *pDeviceID = ack[1]; +} + +void Nandflash_PageProgram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, const uint8_t *buff, uint32_t len) +{ + uint32_t pageAddr = addr & 0xFFFFF800; + uint32_t writeLen = 0; + uint32_t pageOffset = addr - pageAddr; + + if ((pageOffset + len) <= NANDFLASH_PAGE_SIZE) { + writeLen = len; + } else { + writeLen = NANDFLASH_PAGE_SIZE - pageOffset; + } + + if (writeLen) { + /* program load */ + Nandflash_ProgramLoad(pNandflashCfg, pageOffset, buff, writeLen); + + /* write enable */ + Nandflash_WriteEnable(pNandflashCfg); + + /* program execute */ + Nandflash_ProgramExecute(pNandflashCfg, pageAddr); + } + + return; +} + +void Nandflash_PagesProgram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, const uint8_t *buff, uint32_t len) +{ + int32_t startPageNum = 0, endPageNum = 0, absolutePageNum = 0; + uint32_t writeLen = 0, pageAddr = 0; + uint32_t pageOffset = 0, begin_addr = addr; + + startPageNum = addr / NANDFLASH_PAGE_SIZE; + endPageNum = (addr + len - 1) / NANDFLASH_PAGE_SIZE; + + if (len > 0) { + for (absolutePageNum = startPageNum; absolutePageNum <= endPageNum; absolutePageNum++) { + pageOffset = 0; + pageAddr = absolutePageNum * NANDFLASH_PAGE_SIZE; + + if (absolutePageNum == startPageNum) { + if (begin_addr + len >= NANDFLASH_PAGE_SIZE) { + writeLen = (startPageNum + 1) * NANDFLASH_PAGE_SIZE - begin_addr; + } else { + writeLen = len; + } + + pageOffset = begin_addr % NANDFLASH_PAGE_SIZE; + } else if ((startPageNum < absolutePageNum) && (absolutePageNum < endPageNum)) { + writeLen = NANDFLASH_PAGE_SIZE; + pageOffset = 0; + } else if (absolutePageNum == endPageNum) { + writeLen = (begin_addr + len) - (endPageNum * NANDFLASH_PAGE_SIZE); + pageOffset = 0; + } + + if (writeLen) { + /* program load */ + Nandflash_ProgramLoad(pNandflashCfg, pageOffset, buff, writeLen); + + /* write enable */ + Nandflash_WriteEnable(pNandflashCfg); + + /* program execute */ + Nandflash_ProgramExecute(pNandflashCfg, pageAddr); + } + + buff += writeLen; + } + } +} + +void Nandflash_ProgramLoad(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t pageOffset, const uint8_t *buff, uint32_t len) +{ + uint8_t cmd[3] = { 0 }; + uint32_t writeLen = len; + uint8_t pBlockLock = 0xff; + + if (!buff) { + return; + } + + if (len > NANDFLASH_PAGE_SIZE) { + writeLen = NANDFLASH_PAGE_SIZE; + } else { + } + + cmd[0] = NANDFLASH_PROGRAM_LOAD; + cmd[1] = (uint8_t)((pageOffset >> 8) & 0x0F); + cmd[2] = (uint8_t)((pageOffset >> 0) & 0xFF); + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 3, SPI_TIMEOUT_DISABLE); + SPI_Send_8bits(pNandflashCfg->spiNo, (uint8_t *)buff, writeLen, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + /*check block lock status*/ + Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock); + + if (pBlockLock != 0) { + // MSG_ERR("Get BlockLock in Nandflash Program Load and return %0x\r\n", pBlockLock); + } +} + +void Nandflash_ProgramExecute(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr) +{ + uint8_t feature = 0; + uint8_t cmd[4] = { 0 }; + uint8_t status = 0xff; + uint8_t pBlockLock = 0xff; + uint32_t absolutePageNum = 0; + uint16_t cmds = 0; + uint32_t blockNum = 0; + uint32_t pageNum = 0; + absolutePageNum = addr / NANDFLASH_PAGE_SIZE; + blockNum = absolutePageNum / NANDFLASH_PAGES_PER_BLOCK; + pageNum = absolutePageNum % NANDFLASH_PAGES_PER_BLOCK; + + /* enable ECC */ + Nandflash_Get_Feature(pNandflashCfg, &feature); + ((NANDFLASH_FEATURE_Type *)(&feature))->ECC_EN = 1; + Nandflash_Set_Feature(pNandflashCfg, &feature); + + /* program execute */ + cmd[0] = NANDFLASH_PROGRAM_EXECUTE; + cmd[1] = NANDFLASH_DUMMY_BYTE; + cmds = (uint16_t)(blockNum << 6) | (uint16_t)pageNum; + cmd[2] = (uint8_t)(cmds >> 8); + cmd[3] = (uint8_t)(cmds >> 0); + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 4, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + /*check block lock status*/ + Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock); + + if (pBlockLock != 0) { + // MSG_ERR("Get BlockLock in Nandflash Program Execute and return %0x\r\n", pBlockLock); + } + + /* Operation In Progress */ + do { + Nandflash_Get_Status(pNandflashCfg, &status); + } while ((((NANDFLASH_STATUS_Type *)(&status))->OIP)); +} + +void Nandflash_InternalDataMove(NANDFLASH_CFG_Type *pNandflashCfg) +{ +} + +void Nandflash_ProgramLoadRandomData(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len) +{ +} + +static void Nandflash_Erase(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum) +{ + uint8_t cmd[4] = { 0 }; + uint16_t cmds = 0; + uint8_t pBlockLock = 0xff; + + /* block erase */ + cmd[0] = NANDFLASH_BLOCK_ERASE; + cmd[1] = NANDFLASH_DUMMY_BYTE; + cmds = (uint16_t)(blockNum << 6); + cmd[2] = (uint8_t)(cmds >> 8); + cmd[3] = (uint8_t)(cmds >> 0); + + Nandflash_CS_High(); + Nandflash_CS_Low(); + SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 4, SPI_TIMEOUT_DISABLE); + Nandflash_CS_High(); + + /*check block lock status*/ + Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock); + + if (pBlockLock != 0) { + // MSG_ERR("Get BlockLock in Nandflash Erase and return %0x\r\n", pBlockLock); + } +} + +void Nandflash_BlockErase(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr) +{ + uint8_t status = 0xff; + uint32_t blockNum = 0; + blockNum = addr / NANDFLASH_BLOCK_SIZE; + + Nandflash_WriteEnable(pNandflashCfg); + Nandflash_Erase(pNandflashCfg, blockNum); + + /* Operation In Progress */ + do { + Nandflash_Get_Status(pNandflashCfg, &status); + } while ((((NANDFLASH_STATUS_Type *)(&status))->OIP)); +} + +void Nandflash_Reset(NANDFLASH_CFG_Type *pNandflashCfg) +{ +} + +void Nandflash_WriteUnprotect(NANDFLASH_CFG_Type *pNandflashCfg) +{ +} + +NANDFLASH_ECC_Type Nandflash_Check_ECC_Status(NANDFLASH_CFG_Type *pNandflashCfg) +{ + return NO_BIT_ERROR; +} + +int Nandflash_Disk_Status(void) +{ + return 0; +} + +int Nandflash_Disk_Initialize(void) +{ + return 0; +} + +int Nandflash_Disk_Read(BYTE *buff, LBA_t sector, UINT count) +{ + //512 bytes in a sector + uint32_t startAddr = sector * DISK_SECTOR_SIZE; + uint32_t len = count * DISK_SECTOR_SIZE; + NANDFLASH_ECC_Type ecc = 0; + + if (len > 0) { + ecc = Nandflash_PagesRead(&nfCfg, startAddr, buff, len); + } + + return 0; +} + +void Nandflash_PageReadToPsram(uint32_t addr, uint32_t len) +{ + uint32_t startPageNum = 0, endPageNum = 0, absolutePageNum = 0; + uint32_t beginAddr = addr, psramWriteOffsite = 0; + uint8_t readBuff[NANDFLASH_PAGE_SIZE]; + + startPageNum = addr / NANDFLASH_PAGE_SIZE; + endPageNum = (addr + len - 1) / NANDFLASH_PAGE_SIZE; + + if (len > 0) { + for (absolutePageNum = startPageNum; absolutePageNum <= endPageNum; absolutePageNum++) { + memset(readBuff, 0, sizeof(readBuff)); + + Nandflash_PageRead(&nfCfg, beginAddr, readBuff, NANDFLASH_PAGE_SIZE); + Nandflash_Psram_Write(readBuff, NANDFLASH_PAGE_SIZE, psramWriteOffsite); + + beginAddr = (absolutePageNum + 1) * NANDFLASH_PAGE_SIZE; + psramWriteOffsite += NANDFLASH_PAGE_SIZE; + } + } +} + +static void Nandflash_PageWriteToPsram(const uint8_t *buff, uint32_t psramWriteOffsite, uint32_t len) +{ + if (len > 0) { + return Nandflash_Psram_Write((uint8_t *)buff, len, psramWriteOffsite); + } +} + +static void Nandflash_PageProgramFromPsram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum) +{ + uint8_t psramReadBuf[NANDFLASH_PAGE_SIZE]; + uint32_t startPageNum = 0, endPageNum = 0, absolutePageNum = 0; + uint32_t psramReadOffsite = 0; + + startPageNum = blockNum * NANDFLASH_PAGES_PER_BLOCK; + endPageNum = (blockNum + 1) * NANDFLASH_PAGES_PER_BLOCK - 1; + + for (absolutePageNum = startPageNum; absolutePageNum <= endPageNum; absolutePageNum++) { + memset(psramReadBuf, 0, NANDFLASH_PAGE_SIZE); + Nandflash_Psram_Read(psramReadBuf, NANDFLASH_PAGE_SIZE, psramReadOffsite); + Nandflash_PageProgram(pNandflashCfg, absolutePageNum * NANDFLASH_PAGE_SIZE, psramReadBuf, NANDFLASH_PAGE_SIZE); + psramReadOffsite += NANDFLASH_PAGE_SIZE; + } +} + +int Nandflash_Disk_Write(const BYTE *buff, LBA_t sector, UINT count) +{ + uint32_t addr = sector * DISK_SECTOR_SIZE; + uint32_t len = count * DISK_SECTOR_SIZE; + uint32_t startBlockNum = 0, endBlockNum = 0, absoluteBlockNum = 0; + uint32_t writeLen = 0, beginAddr = addr; + + startBlockNum = addr / NANDFLASH_BLOCK_SIZE; + endBlockNum = (addr + len - 1) / NANDFLASH_BLOCK_SIZE; + + if (len > 0) { + Nandflash_Psram_Cfg(); + + for (absoluteBlockNum = startBlockNum; absoluteBlockNum <= endBlockNum; absoluteBlockNum++) { + if (absoluteBlockNum == startBlockNum) { + if (addr + len >= NANDFLASH_BLOCK_SIZE) { + writeLen = (absoluteBlockNum + 1) * NANDFLASH_BLOCK_SIZE - addr; + } else { + writeLen = len; + } + } else if ((startBlockNum < absoluteBlockNum) && (absoluteBlockNum < endBlockNum)) { + writeLen = NANDFLASH_BLOCK_SIZE; + } else if (absoluteBlockNum == endBlockNum) { + writeLen = (addr + len) - (endBlockNum * NANDFLASH_BLOCK_SIZE); + } + + /*read data from block to psram*/ + Nandflash_PageReadToPsram(absoluteBlockNum * NANDFLASH_BLOCK_SIZE, NANDFLASH_BLOCK_SIZE); + /*update program data to psram*/ + Nandflash_PageWriteToPsram(buff, beginAddr % NANDFLASH_BLOCK_SIZE, writeLen); + /*erase block*/ + Nandflash_BlockErase(&nfCfg, absoluteBlockNum * NANDFLASH_BLOCK_SIZE); + /*program data from psram to block*/ + Nandflash_PageProgramFromPsram(&nfCfg, absoluteBlockNum); + + buff += writeLen; + beginAddr = (absoluteBlockNum + 1) * NANDFLASH_BLOCK_SIZE; + } + } + + return 0; +} + +int Nandflash_Disk_Ioctl(BYTE cmd, void *buff) +{ + return 0; +} + +void Nandflash_Init() +{ + Nandflash_Gpio_Init(SPI_PIN_CLK, SPI_PIN_MISO, SPI_PIN_MOSI); + Nandflash_Clock_Init(ENABLE, 0x1F); + Nandflash_SPI_Init(&nfCfg); +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_spi.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..a62dc5a065b71c026d0d6db10c16ce0b27aeac9f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_spi.c @@ -0,0 +1,1806 @@ +/** + ****************************************************************************** + * @file bl702_spi.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_spi.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ +#define SPI_TX_TIMEOUT_COUNT (160 * 1000) +#define SPI_RX_TIMEOUT_COUNT (160 * 1000) + +/*@} end of group SPI_Private_Macros */ + +/** @defgroup SPI_Private_Types + * @{ + */ + +/*@} end of group SPI_Private_Types */ + +/** @defgroup SPI_Private_Variables + * @{ + */ +static const uint32_t spiAddr[SPI_ID_MAX] = { SPI_BASE }; +static intCallback_Type *spiIntCbfArra[SPI_ID_MAX][SPI_INT_ALL] = { + { NULL } +}; + +/*@} end of group SPI_Private_Variables */ + +/** @defgroup SPI_Global_Variables + * @{ + */ + +/*@} end of group SPI_Global_Variables */ + +/** @defgroup SPI_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void SPI_IntHandler(SPI_ID_Type spiNo); +#endif + +/*@} end of group SPI_Private_Fun_Declaration */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief SPI interrupt common handler function + * + * @param spiNo: SPI ID type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static void SPI_IntHandler(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + /* Transfer end interrupt,shared by both master and slave mode */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR)); + + if (spiIntCbfArra[spiNo][SPI_INT_END] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_END](); + } + } + + /* TX fifo ready interrupt(fifo count > fifo threshold) */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) { + if (spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ](); + } + } + + /* RX fifo ready interrupt(fifo count > fifo threshold) */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) { + if (spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ](); + } + } + + /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR)); + + if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT](); + } + } + + /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) { + BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR)); + + if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN](); + } + } + + /* TX/RX fifo overflow/underflow interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) { + if (spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR] != NULL) { + spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR](); + } + } +} +#endif + +/*@} end of group SPI_Private_Functions */ + +/** @defgroup SPI_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief SPI initialization function + * + * @param spiNo: SPI ID type + * @param spiCfg: SPI configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod)); + CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence)); + CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence)); + CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv)); + CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity)); + + /* Disable clock gate */ + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_SPI); + + /* spi config */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_EN, spiCfg->deglitchEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_M_CONT_EN, spiCfg->continuousEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BYTE_INV, spiCfg->byteSequence); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BIT_INV, spiCfg->bitSequence); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_PH, (spiCfg->clkPhaseInv + 1) & 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_POL, spiCfg->clkPolarity); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, spiCfg->frameSize); + BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SPI_IRQn, SPI_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI set default value of all registers function + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo) +{ + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + if (SPI_ID_0 == spiNo) { + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SPI); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Length of data phase1/0,start/stop condition and interval between frame initialization + * function + * + * @param spiNo: SPI ID type + * @param clockCfg: Clock configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Configure length of data phase1/0 and start/stop condition */ + tmpVal = BL_RD_REG(SPIx, SPI_PRD_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, clockCfg->startLen - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, clockCfg->stopLen - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, clockCfg->dataPhase0Len - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, clockCfg->dataPhase1Len - 1); + BL_WR_REG(SPIx, SPI_PRD_0, tmpVal); + + /* Configure length of interval between frame */ + tmpVal = BL_RD_REG(SPIx, SPI_PRD_1); + BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, clockCfg->intervalLen - 1)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI configure fifo function + * + * @param spiNo: SPI ID type + * @param fifoCfg: FIFO configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set fifo threshold value */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold - 1); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal); + + /* Enable or disable dma function */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_TX_EN, fifoCfg->txFifoDmaEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_RX_EN, fifoCfg->rxFifoDmaEnable); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set SPI SCK Clcok + * + * @param spiNo: SPI ID type + * @param clk: Clk + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk) +{ + uint32_t glb_div = 1, spi_div = 1; + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + if (clk < 4395) { + clk = 4395; + } + + if (clk > 36000000) { + clk = 36000000; + } + + if (clk > 140625) { + glb_div = 1; + spi_div = 36000000 / clk; + } else { + spi_div = 256; + glb_div = clk >> 8; + } + + /* Configure length of data phase1/0 and start/stop condition */ + tmpVal = BL_RD_REG(SPIx, SPI_PRD_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, spi_div - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, spi_div - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, spi_div - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, spi_div - 1); + BL_WR_REG(SPIx, SPI_PRD_0, tmpVal); + + tmpVal = BL_RD_REG(SPIx, SPI_PRD_1); + BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, spi_div - 1)); + + GLB_Set_SPI_CLK(ENABLE, glb_div - 1); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable spi transfer + * + * @param spiNo: SPI ID type + * @param modeType: Master or slave mode select + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); + + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + + if (modeType != SPI_WORK_MODE_SLAVE) { + /* master mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); + } else { + /* slave mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); + } + + BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable spi transfer + * + * @param spiNo: SPI ID type + * @param modeType: Master or slave mode select + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); + + /* close master and slave */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); + BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set time-out value to trigger interrupt when spi bus is idle for the given value + * + * @param spiNo: SPI ID type + * @param value: Time value + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set time-out value */ + tmpVal = BL_RD_REG(SPIx, SPI_STO_VALUE); + BL_WR_REG(SPIx, SPI_STO_VALUE, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_STO_VALUE, value - 1)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set de-glitch function cycle count value + * + * @param spiNo: SPI ID type + * @param cnt: De-glitch function cycle count + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set count value */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt); + BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable rx data ignore function and set start/stop point + * + * @param spiNo: SPI ID type + * @param startPoint: Start point + * @param stopPoint: Stop point + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Enable rx ignore function */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Set start and stop point */ + tmpVal = startPoint << SPI_CR_SPI_RXD_IGNR_S_POS | stopPoint; + BL_WR_REG(SPIx, SPI_RXD_IGNR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable rx data ignore function + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Disable rx ignore function */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear tx fifo and tx fifo overflow/underflow status + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Clear tx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear rx fifo and rx fifo overflow/underflow status + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Clear rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear spi interrupt status + * + * @param spiNo: SPI ID type + * @param intType: SPI interrupt type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Clear certain or all interrupt */ + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + if (SPI_INT_ALL == intType) { + tmpVal |= 0x1f << SPI_CR_SPI_END_CLR_POS; + } else { + tmpVal |= 1 << (intType + SPI_CR_SPI_END_CLR_POS); + } + + BL_WR_REG(SPIx, SPI_INT_STS, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI mask or unmask certain or all interrupt + * + * @param spiNo: SPI ID type + * @param intType: SPI interrupt type + * @param intMask: SPI interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + /* Mask or unmask certain or all interrupt */ + if (SPI_INT_ALL == intType) { + if (MASK == intMask) { + tmpVal |= 0x3f << SPI_CR_SPI_END_MASK_POS; + } else { + tmpVal &= ~(0x3f << SPI_CR_SPI_END_MASK_POS); + } + } else { + if (MASK == intMask) { + tmpVal |= 1 << (intType + SPI_CR_SPI_END_MASK_POS); + } else { + tmpVal &= ~(1 << (intType + SPI_CR_SPI_END_MASK_POS)); + } + } + + /* Write back */ + BL_WR_REG(SPIx, SPI_INT_STS, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Install spi interrupt callback function + * + * @param spiNo: SPI ID type + * @param intType: SPI interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_INT_TYPE(intType)); + + spiIntCbfArra[spiNo][intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI write data to tx fifo + * + * @param spiNo: SPI ID type + * @param data: Data to write + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, uint32_t data) +{ + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Write tx fifo */ + BL_WR_REG(SPIx, SPI_FIFO_WDATA, data); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send 8-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t rData; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send 16-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t rData; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send 24-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t rData; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send 32-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t rData; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI receive 8-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t rxLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo with 0 */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (rxLen = 0; rxLen < tmpVal; rxLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive data and send the rest of the data 0 */ + for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive the rest of the data */ + for (; rxLen < length; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI receive 16-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t rxLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo with 0 */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (rxLen = 0; rxLen < tmpVal; rxLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive data and send the rest of the data 0 */ + for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive the rest of the data */ + for (; rxLen < length; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI receive 24-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t rxLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo with 0 */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (rxLen = 0; rxLen < tmpVal; rxLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive data and send the rest of the data 0 */ + for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff; + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive the rest of the data */ + for (; rxLen < length; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI receive 32-bit datas + * + * @param spiNo: SPI ID type + * @param buff: Buffer of datas + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t rxLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo with 0 */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (rxLen = 0; rxLen < tmpVal; rxLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive data and send the rest of the data 0 */ + for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); + } + + /* Wait receive the rest of the data */ + for (; rxLen < length; rxLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send and receive 8-bit datas at the same time + * + * @param spiNo: SPI ID type + * @param sendBuff: Buffer of datas to send + * @param recvBuff: Buffer of datas received + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[txLen - tmpVal] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[length - tmpVal + txLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send and receive 16-bit datas at the same time + * + * @param spiNo: SPI ID type + * @param sendBuff: Buffer of datas to send + * @param recvBuff: Buffer of datas received + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo, uint16_t *sendBuff, uint16_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[txLen - tmpVal] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[length - tmpVal + txLen] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send and receive 24-bit datas at the same time + * + * @param spiNo: SPI ID type + * @param sendBuff: Buffer of datas to send + * @param recvBuff: Buffer of datas received + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff; + BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI send and receive 32-bit datas at the same time + * + * @param spiNo: SPI ID type + * @param sendBuff: Buffer of datas to send + * @param recvBuff: Buffer of datas received + * @param length: Length of buffer + * @param timeoutType: Enable or disable timeout judgment + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) +{ + uint32_t tmpVal; + uint32_t txLen = 0; + uint32_t SPIx = spiAddr[spiNo]; + uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); + + /* Set valid width for each fifo entry */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3)); + + /* Disable rx ignore */ + tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); + BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); + + /* Clear tx and rx fifo */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR); + BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); + + /* Fill tx fifo */ + tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; + + for (txLen = 0; txLen < tmpVal; txLen++) { + BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]); + } + + /* Wait receive data and send the rest of the data */ + for (; txLen < length; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); + BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]); + } + + /* Wait receive the rest of the data */ + for (txLen = 0; txLen < tmpVal; txLen++) { + timeoutCnt = SPI_RX_TIMEOUT_COUNT; + + while (SPI_GetRxFifoCount(spiNo) == 0) { + if (timeoutType) { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + recvBuff[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SPI read data from rx fifo + * + * @param spiNo: SPI ID type + * + * @return Data readed + * +*******************************************************************************/ +uint32_t SPI_ReceiveData(SPI_ID_Type spiNo) +{ + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + return BL_RD_REG(SPIx, SPI_FIFO_RDATA); +} + +/****************************************************************************/ /** + * @brief Get tx fifo available count value function + * + * @param spiNo: SPI ID type + * + * @return Count value + * +*******************************************************************************/ +uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo) +{ + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Get count value */ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_TX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief Get rx fifo available count value function + * + * @param spiNo: SPI ID type + * + * @return Count value + * +*******************************************************************************/ +uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo) +{ + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Get count value */ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief Get spi interrupt status + * + * @param spiNo: SPI ID type + * @param intType: SPI interrupt type + * + * @return Status of interrupt + * +*******************************************************************************/ +BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_INT_TYPE(intType)); + + /* Get certain or all interrupt status */ + tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); + + if (SPI_INT_ALL == intType) { + if ((tmpVal & 0x3f) != 0) { + return SET; + } else { + return RESET; + } + } else { + if ((tmpVal & (1U << intType)) != 0) { + return SET; + } else { + return RESET; + } + } +} + +/****************************************************************************/ /** + * @brief Get indicator of spi bus busy + * + * @param spiNo: SPI ID type + * + * @return Status of spi bus + * +*******************************************************************************/ +BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Get bus busy status */ + tmpVal = BL_RD_REG(SPIx, SPI_BUS_BUSY); + + if (BL_IS_REG_BIT_SET(tmpVal, SPI_STS_SPI_BUS_BUSY)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Get tx/rx fifo overflow or underflow status + * + * @param spiNo: SPI ID type + * @param fifoSts: Select tx/rx overflow or underflow + * + * @return Status of tx/rx fifo + * +*******************************************************************************/ +BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_FIFOSTATUS_TYPE(fifoSts)); + + /* Get tx/rx fifo overflow or underflow status */ + tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); + + if ((tmpVal & (1U << (fifoSts + SPI_TX_FIFO_OVERFLOW_POS))) != 0) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief SPI interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void SPI_IRQHandler(void) +{ + SPI_IntHandler(SPI_ID_0); +} +#endif + +/*@} end of group SPI_Public_Functions */ + +/*@} end of group SPI */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_timer.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..ca1c841163a3ccd67a592550faa79784e4996789 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_timer.c @@ -0,0 +1,894 @@ +/** + ****************************************************************************** + * @file bl702_timer.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_timer.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Private_Macros + * @{ + */ +#define TIMER_MAX_MATCH 3 + +/*@} end of group TIMER_Private_Macros */ + +/** @defgroup TIMER_Private_Types + * @{ + */ + +/*@} end of group TIMER_Private_Types */ + +/** @defgroup TIMER_Private_Variables + * @{ + */ +intCallback_Type *timerIntCbfArra[3][TIMER_INT_ALL] = { + { NULL, NULL, NULL }, + { NULL, NULL, NULL }, + { NULL, NULL, NULL } +}; + +/*@} end of group TIMER_Private_Variables */ + +/** @defgroup TIMER_Global_Variables + * @{ + */ + +/*@} end of group TIMER_Global_Variables */ + +/** @defgroup TIMER_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh); +#endif + +/*@} end of group TIMER_Private_Fun_Declaration */ + +/** @defgroup TIMER_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief TIMER interrupt common handler function + * + * @param irqNo: Interrupt ID type + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh) +{ + uint32_t intId; + uint32_t tmpVal; + uint32_t tmpAddr; + + intId = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timerCh); + tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timerCh; + tmpVal = BL_RD_WORD(tmpAddr); + + /* Comparator 0 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_0)) { + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_0)); + + if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_0] != NULL) { + /* Call the callback function */ + timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_0](); + } + } + + /* Comparator 1 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_1)) { + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_1)); + + if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_1] != NULL) { + /* Call the callback function */ + timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_1](); + } + } + + /* Comparator 2 match interrupt */ + if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_2)) { + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_2)); + + if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_2] != NULL) { + /* Call the callback function */ + timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_2](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief Get the specified channel and match comparator value + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * + * @return Match comapre register value + * +*******************************************************************************/ +uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpVal = BL_RD_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo)); + return tmpVal; +} + +/****************************************************************************/ /** + * @brief TIMER set specified channel and comparator compare value + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * @param val: TIMER match comapre register value + * + * @return None + * +*******************************************************************************/ +void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + BL_WR_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo), val); +} + +/****************************************************************************/ /** + * @brief TIMER get the specified channel count value + * + * @param timerCh: TIMER channel type + * + * @return TIMER count register value + * +*******************************************************************************/ +uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + uint32_t tmpAddr; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + /* TO avoid risk of reading, don't read TCVWR directly*/ + /* request for read*/ + tmpAddr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timerCh; + BL_WR_WORD(tmpAddr, 1); + + /* Need wait */ + tmpVal = BL_RD_WORD(tmpAddr); + tmpVal = BL_RD_WORD(tmpAddr); + tmpVal = BL_RD_WORD(tmpAddr); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief TIMER get specified channel and comparator match status + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpVal; + BL_Sts_Type bitStatus = RESET; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpVal = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timerCh); + + switch (cmpNo) { + case TIMER_COMP_ID_0: + bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_0) ? SET : RESET; + break; + + case TIMER_COMP_ID_1: + bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_1) ? SET : RESET; + break; + + case TIMER_COMP_ID_2: + bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_2) ? SET : RESET; + break; + + default: + break; + } + + return bitStatus; +} + +/****************************************************************************/ /** + * @brief TIMER get specified channel preload value + * + * @param timerCh: TIMER channel type + * + * @return Preload register value + * +*******************************************************************************/ +uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + return BL_RD_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timerCh); +} + +/****************************************************************************/ /** + * @brief TIMER set preload register low 32bits value + * + * @param timerCh: TIMER channel type + * @param val: Preload register low 32bits value + * + * @return None + * +*******************************************************************************/ +void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timerCh, val); +} + +/****************************************************************************/ /** + * @brief TIMER set preload trigger source,COMP0,COMP1,COMP2 or None + * + * @param timerCh: TIMER channel type + * @param plSrc: TIMER preload source type + * + * @return None + * +*******************************************************************************/ +void TIMER_SetPreloadTrigSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(plSrc)); + + BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timerCh, plSrc); +} + +/****************************************************************************/ /** + * @brief TIMER set count mode:preload or free run + * + * @param timerCh: TIMER channel type + * @param countMode: TIMER count mode: TIMER_COUNT_PRELOAD or TIMER_COUNT_FREERUN + * + * @return None + * +*******************************************************************************/ +void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode) +{ + uint32_t tmpval; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(countMode)); + + tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET); + tmpval &= (~(1 << (timerCh + 1))); + tmpval |= (countMode << (timerCh + 1)); + + BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval); +} + +/****************************************************************************/ /** + * @brief TIMER clear interrupt status + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER macth comparator ID type + * + * @return None + * +*******************************************************************************/ +void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpAddr; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timerCh; + + tmpVal = BL_RD_WORD(tmpAddr); + tmpVal |= (1 << cmpNo); + + BL_WR_WORD(tmpAddr, tmpVal); +} + +/****************************************************************************/ /** + * @brief TIMER initialization function + * + * @param timerCfg: TIMER configuration structure pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type TIMER_Init(TIMER_CFG_Type *timerCfg) +{ + TIMER_Chan_Type timerCh = timerCfg->timerCh; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(timerCfg->clkSrc)); + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCfg->timerCh)); + CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(timerCfg->plTrigSrc)); + CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(timerCfg->countMode)); + + /* Configure timer clock source */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + + if (timerCh == TIMER_CH0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_1, timerCfg->clkSrc); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_2, timerCfg->clkSrc); + } + + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpVal); + + /* Configure timer clock division */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + + if (timerCh == TIMER_CH0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, timerCfg->clockDivision); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR3, timerCfg->clockDivision); + } + + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); + + /* Configure timer count mode: preload or free run */ + TIMER_SetCountMode(timerCh, timerCfg->countMode); + + /* Configure timer preload trigger src */ + TIMER_SetPreloadTrigSrc(timerCh, timerCfg->plTrigSrc); + + if (timerCfg->countMode == TIMER_COUNT_PRELOAD) { + /* Configure timer preload value */ + TIMER_SetPreloadValue(timerCh, timerCfg->preLoadVal); + + /* Configure match compare values */ + if (timerCfg->matchVal0 > 1 + timerCfg->preLoadVal) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0); + } + + if (timerCfg->matchVal1 > 1 + timerCfg->preLoadVal) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1); + } + + if (timerCfg->matchVal2 > 1 + timerCfg->preLoadVal) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2); + } + } else { + /* Configure match compare values */ + if (timerCfg->matchVal0 > 1) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0); + } + + if (timerCfg->matchVal1 > 1) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1); + } + + if (timerCfg->matchVal2 > 1) { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2); + } else { + TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2); + } + } + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER_CH0_IRQHandler); + Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER_CH1_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief TIMER enable one channel function + * + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +void TIMER_Enable(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCER); + tmpVal |= (1 << (timerCh + 1)); + + BL_WR_REG(TIMER_BASE, TIMER_TCER, tmpVal); +} + +/****************************************************************************/ /** + * @brief TIMER disable one channel function + * + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +void TIMER_Disable(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCER); + tmpVal &= (~(1 << (timerCh + 1))); + + BL_WR_REG(TIMER_BASE, TIMER_TCER, tmpVal); +} + +/****************************************************************************/ /** + * @brief TIMER mask or unmask certain or all interrupt + * + * @param timerCh: TIMER channel type + * @param intType: TIMER interrupt type + * @param intMask: TIMER interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt + * + * @return None + * +*******************************************************************************/ +void TIMER_IntMask(TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpAddr; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpAddr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timerCh; + tmpVal = BL_RD_WORD(tmpAddr); + + switch (intType) { + case TIMER_INT_COMP_0: + if (intMask == UNMASK) { + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_0)); + } else { + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_0)); + } + + break; + + case TIMER_INT_COMP_1: + if (intMask == UNMASK) { + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_1)); + } else { + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_1)); + } + + break; + + case TIMER_INT_COMP_2: + if (intMask == UNMASK) { + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_2)); + } else { + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_2)); + } + + break; + + case TIMER_INT_ALL: + if (intMask == UNMASK) { + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_0)); + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_1)); + BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_2)); + } else { + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_0)); + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_1)); + BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_2)); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief TIMER set watchdog clock source and clock division + * + * @param clkSrc: Watchdog timer clock source type + * @param div: Watchdog timer clock division value + * + * @return None + * +*******************************************************************************/ +void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc, uint8_t div) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(clkSrc)); + + /* Configure watchdog timer clock source */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT, clkSrc); + BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpVal); + + /* Configure watchdog timer clock divison */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WCDR, div); + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); +} + +/****************************************************************************/ /** + * @brief TIMER get watchdog match compare value + * + * @param None + * + * @return Watchdog match comapre register value + * +*******************************************************************************/ +uint16_t WDT_GetMatchValue(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog timer match register value */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMR); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief TIMER set watchdog match compare value + * + * @param val: Watchdog match compare value + * + * @return None + * +*******************************************************************************/ +void WDT_SetCompValue(uint16_t val) +{ + WDT_ENABLE_ACCESS(); + + /* Set watchdog timer match register value */ + BL_WR_REG(TIMER_BASE, TIMER_WMR, val); +} + +/****************************************************************************/ /** + * @brief TIMER get watchdog count register value + * + * @param None + * + * @return Watchdog count register value + * +*******************************************************************************/ +uint16_t WDT_GetCounterValue(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog timer count register value */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WVR); + + return tmpVal; +} + +/****************************************************************************/ /** + * @brief TIMER reset watchdog count register value + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_ResetCounterValue(void) +{ + uint32_t tmpVal; + + /* Reset watchdog timer count register value */ + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WCR); + + /* Set watchdog counter reset register bit0 to 1 */ + BL_WR_REG(TIMER_BASE, TIMER_WCR, BL_SET_REG_BIT(tmpVal, TIMER_WCR)); +} + +/****************************************************************************/ /** + * @brief TIMER get watchdog reset status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type WDT_GetResetStatus(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog status register */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WSR); + + return (BL_IS_REG_BIT_SET(tmpVal, TIMER_WTS)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief TIMER clear watchdog reset status + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_ClearResetStatus(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WSR); + + /* Set watchdog status register */ + BL_WR_REG(TIMER_BASE, TIMER_WSR, BL_CLR_REG_BIT(tmpVal, TIMER_WTS)); +} + +/****************************************************************************/ /** + * @brief TIMER enable watchdog function + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_Enable(void) +{ + uint32_t tmpVal; + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(TIMER_WDT_IRQn, TIMER_WDT_IRQHandler); +#endif + + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER); + + BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WE)); +} + +/****************************************************************************/ /** + * @brief Watchdog timer disable function + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_Disable(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER); + + BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WE)); +} + +/****************************************************************************/ /** + * @brief Watchdog timer mask or unmask certain or all interrupt + * + * @param intType: Watchdog interrupt type + * @param intMask: Watchdog interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt + * + * @return None + * +*******************************************************************************/ +void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_WDT_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + WDT_ENABLE_ACCESS(); + + /* Deal with watchdog match/interrupt enable register, + WRIE:watchdog reset/interrupt enable */ + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER); + + switch (intType) { + case WDT_INT: + if (intMask == UNMASK) { + /* Enable this interrupt */ + /* 0 means generates a watchdog interrupt, + a watchdog timer reset is not generated*/ + BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WRIE)); + } else { + /* Disable this interrupt */ + /* 1 means generates a watchdog timer reset, + a watchdog interrupt is not generated*/ + BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WRIE)); + } + + break; + + default: + break; + } +} + +/****************************************************************************/ /** + * @brief TIMER channel 0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH0_IRQHandler(void) +{ + TIMER_IntHandler(TIMER_CH0_IRQn, TIMER_CH0); +} +#endif + +/****************************************************************************/ /** + * @brief TIMER channel 1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH1_IRQHandler(void) +{ + TIMER_IntHandler(TIMER_CH1_IRQn, TIMER_CH1); +} +#endif + +/****************************************************************************/ /** + * @brief TIMER watchdog interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_WDT_IRQHandler(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WICR); + BL_WR_REG(TIMER_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR)); + + if (timerIntCbfArra[TIMER_WDT_IRQn - TIMER_CH0_IRQn][WDT_INT] != NULL) { + /* Call the callback function */ + timerIntCbfArra[TIMER_WDT_IRQn - TIMER_CH0_IRQn][WDT_INT](); + } +} +#endif + +/****************************************************************************/ /** + * @brief TIMER install interrupt callback + * + * @param timerChan: TIMER channel type + * @param intType: TIMER interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan)); + CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); + + timerIntCbfArra[timerChan][intType] = cbFun; +} + +/****************************************************************************/ /** + * @brief Watchdog install interrupt callback + * + * @param wdtInt: Watchdog interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void WDT_Int_Callback_Install(WDT_INT_Type wdtInt, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_WDT_INT_TYPE(wdtInt)); + + timerIntCbfArra[2][wdtInt] = cbFun; +} + +/*@} end of group TIMER_Private_Functions */ + +/*@} end of group TIMER */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_uart.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..ff7ae52e03d2b7aaace31fbdebb4fca54f9dd34e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_uart.c @@ -0,0 +1,1226 @@ +/** + ****************************************************************************** + * @file bl702_uart.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_uart.h" +#include "bl702_glb.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_Private_Macros + * @{ + */ +#define UART_TX_TIMEOUT_COUNT (160 * 1000) + +/*@} end of group UART_Private_Macros */ + +/** @defgroup UART_Private_Types + * @{ + */ + +/*@} end of group UART_Private_Types */ + +/** @defgroup UART_Private_Variables + * @{ + */ +static const uint32_t uartAddr[2] = { UART0_BASE, UART1_BASE }; +static intCallback_Type *uartIntCbfArra[2][UART_INT_ALL] = { + { NULL }, + { NULL } +}; + +/*@} end of group UART_Private_Variables */ + +/** @defgroup UART_Global_Variables + * @{ + */ + +/*@} end of group UART_Global_Variables */ + +/** @defgroup UART_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void UART_IntHandler(UART_ID_Type uartId); +#endif + +/*@} end of group UART_Private_Fun_Declaration */ + +/** @defgroup UART_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief UART interrupt common handler function + * + * @param uartId: UART ID type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static void UART_IntHandler(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t maskVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + tmpVal = BL_RD_REG(UARTx, UART_INT_STS); + maskVal = BL_RD_REG(UARTx, UART_INT_MASK); + + /* Length of uart tx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1); + + if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) { + uartIntCbfArra[uartId][UART_INT_TX_END](); + } + } + + /* Length of uart rx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2); + + if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) { + uartIntCbfArra[uartId][UART_INT_RX_END](); + } + } + + /* Tx fifo ready interrupt,auto-cleared when data is pushed */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) { + if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) { + uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ](); + } + } + + /* Rx fifo ready interrupt,auto-cleared when data is popped */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) { + if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) { + uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ](); + } + } + + /* Rx time-out interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10); + + if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) { + uartIntCbfArra[uartId][UART_INT_RTO](); + } + } + + /* Rx parity check error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20); + + if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) { + uartIntCbfArra[uartId][UART_INT_PCE](); + } + } + + /* Tx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { + if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) { + uartIntCbfArra[uartId][UART_INT_TX_FER](); + } + } + + /* Rx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { + if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) { + uartIntCbfArra[uartId][UART_INT_RX_FER](); + } + } + + /* Rx lin mode sync field error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x100); + + if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) { + uartIntCbfArra[uartId][UART_INT_LSE](); + } + } +} +#endif + +/*@} end of group UART_Private_Functions */ + +/** @defgroup UART_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief UART initialization function + * + * @param uartId: UART ID type + * @param uartCfg: UART configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg) +{ + uint32_t tmpValTxCfg = 0; + uint32_t tmpValRxCfg = 0; + uint32_t fraction = 0; + uint32_t baudRateDivisor = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity)); + CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits)); + CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits)); + CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse)); + + /* Cal the baud rate divisor */ + fraction = uartCfg->uartClk * 10 / uartCfg->baudRate % 10; + baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate; + + if (fraction >= 5) { + ++baudRateDivisor; + } + + /* Set the baud rate register value */ + BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF)); + + /* Configure parity type */ + tmpValTxCfg = BL_RD_REG(UARTx, UART_UTX_CONFIG); + tmpValRxCfg = BL_RD_REG(UARTx, UART_URX_CONFIG); + + switch (uartCfg->parity) { + case UART_PARITY_NONE: + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); + break; + + case UART_PARITY_ODD: + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL); + break; + + case UART_PARITY_EVEN: + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL); + break; + + default: + break; + } + + /* Configure data bits */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_D, (uartCfg->dataBits + 4)); + tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_BIT_CNT_D, (uartCfg->dataBits + 4)); + + /* Configure tx stop bits */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, uartCfg->stopBits); + + /* Configure tx cts flow control function */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_CTS_EN, uartCfg->ctsFlowControl); + + /* Configure rx input de-glitch function */ + tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_DEG_EN, uartCfg->rxDeglitch); + + /* Configure tx lin mode function */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_LIN_EN, uartCfg->txLinMode); + + /* Configure rx lin mode function */ + tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_LIN_EN, uartCfg->rxLinMode); + + /* Set tx break bit count for lin protocol */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_B, uartCfg->txBreakBitCnt); + + /* Write back */ + BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpValTxCfg); + BL_WR_REG(UARTx, UART_URX_CONFIG, tmpValRxCfg); + + /* Configure LSB-first or MSB-first */ + tmpValTxCfg = BL_RD_REG(UARTx, UART_DATA_CONFIG); + + if (UART_MSB_FIRST == uartCfg->byteBitInverse) { + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV); + } else { + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV); + } + + BL_WR_REG(UARTx, UART_DATA_CONFIG, tmpValTxCfg); + + tmpValTxCfg = BL_RD_REG(UARTx, UART_SW_MODE); + /* Configure rx rts output SW control mode */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_URX_RTS_SW_MODE, uartCfg->rtsSoftwareControl); + /* Configure tx output SW control mode */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_TXD_SW_MODE, uartCfg->txSoftwareControl); + BL_WR_REG(UARTx, UART_SW_MODE, tmpValTxCfg); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(UART0_IRQn, UART0_IRQHandler); + Interrupt_Handler_Register(UART1_IRQn, UART1_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set default value of all registers function + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_DeInit(UART_ID_Type uartId) +{ + if (UART0_ID == uartId) { + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0); + } else if (UART1_ID == uartId) { + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART configure fifo function + * + * @param uartId: UART ID type + * @param fifoCfg: FIFO configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Deal with uart fifo configure register */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1); + /* Configure dma tx fifo threshold */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold - 1); + /* Configure dma rx fifo threshold */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold - 1); + /* Write back */ + BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal); + + /* Enable or disable uart fifo dma function */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); + + if (ENABLE == fifoCfg->txFifoDmaEnable) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN); + } + + if (ENABLE == fifoCfg->rxFifoDmaEnable) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN); + } + + BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART configure infra function + * + * @param uartId: UART ID type + * @param irCfg: IR configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Configure tx ir mode */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + + if (ENABLE == irCfg->txIrEnable) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_EN); + } + + if (ENABLE == irCfg->txIrInverse) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_INV); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_INV); + } + + BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpVal); + + /* Configure rx ir mode */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + + if (ENABLE == irCfg->rxIrEnable) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_EN); + } + + if (ENABLE == irCfg->rxIrInverse) { + tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_INV); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_INV); + } + + BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal); + + /* Configure tx ir pulse start and stop position */ + BL_WR_REG(UARTx, UART_UTX_IR_POSITION, irCfg->txIrPulseStop << 0x10 | irCfg->txIrPulseStart); + + /* Configure rx ir pulse start position */ + BL_WR_REG(UARTx, UART_URX_IR_POSITION, irCfg->rxIrPulseStart); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable UART + * + * @param uartId: UART ID type + * @param direct: UART direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); + + if (direct == UART_TX || direct == UART_TXRX) { + /* Enable UART tx unit */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_EN)); + } + + if (direct == UART_RX || direct == UART_TXRX) { + /* Enable UART rx unit */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable UART + * + * @param uartId: UART ID type + * @param direct: UART direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); + + if (direct == UART_TX || direct == UART_TXRX) { + /* Disable UART tx unit */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_EN)); + } + + if (direct == UART_RX || direct == UART_TXRX) { + /* Disable UART rx unit */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set length of tx data transfer,tx end interrupt will assert when this length is + * reached + * + * @param uartId: UART ID type + * @param length: Length of data (unit:character/byte) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set length */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_LEN, length - 1)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set length of rx data transfer,rx end interrupt will assert when this length is + * reached + * + * @param uartId: UART ID type + * @param length: Length of data (unit:character/byte) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set length */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_LEN, length - 1)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set rx time-out value for triggering RTO interrupt + * + * @param uartId: UART ID type + * @param time: Time-out value (unit:bit time) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set time-out value */ + tmpVal = BL_RD_REG(UARTx, UART_URX_RTO_TIMER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_RTO_VALUE, time - 1); + BL_WR_REG(UARTx, UART_URX_RTO_TIMER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set de-glitch function cycle count value + * + * @param uartId: UART ID type + * @param deglitchCnt: De-glitch function cycle count + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set count value */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt); + BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set tx and rx baudrate according to auto baudrate detection value + * + * @param uartId: UART ID type + * @param autoBaudDet: Choose detection value using codeword 0x55 or start bit + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) +{ + uint32_t UARTx = uartAddr[uartId]; + uint16_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Get detection value */ + tmpVal = UART_GetAutoBaudCount(uartId, autoBaudDet); + + /* Set tx baudrate */ + BL_WR_REG(UARTx, UART_BIT_PRD, tmpVal << 0x10 | tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set rx rts output software control value + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Rts set 1*/ + tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); + BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART clear rx rts output software control value + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Rts clear 0 */ + tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); + BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART set tx output software control value + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetTxValue(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Tx set 1*/ + tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); + BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART clear tx output software control value + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Rts clear 0 */ + tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); + BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART configure tx free run mode function + * + * @param uartId: UART ID type + * @param txFreeRun: Enable or disable tx free run mode + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Enable or disable tx free run mode */ + tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); + + if (ENABLE == txFreeRun) { + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN)); + } else { + BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART configure auto baud rate detection function + * + * @param uartId: UART ID type + * @param autoBaud: Enable or disable auto function + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Enable or disable auto baud rate detection function */ + tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); + + if (ENABLE == autoBaud) { + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_ABR_EN)); + } else { + BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_ABR_EN)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART tx fifo clear + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Clear tx fifo */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); + BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_TX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART rx fifo clear + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Clear rx fifo */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); + BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_RX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART mask or unmask certain or all interrupt + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * @param intMask: UART interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(UARTx, UART_INT_MASK); + + /* Mask or unmask certain or all interrupt */ + if (UART_INT_ALL == intType) { + if (MASK == intMask) { + tmpVal |= 0x1ff; + } else { + tmpVal &= 0; + } + } else { + if (MASK == intMask) { + tmpVal |= 1 << intType; + } else { + tmpVal &= ~(1 << intType); + } + } + + /* Write back */ + BL_WR_REG(UARTx, UART_INT_MASK, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART clear certain or all interrupt + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(UARTx, UART_INT_CLEAR); + + /* Clear certain or all interrupt */ + if (UART_INT_ALL == intType) { + tmpVal |= 0x1ff; + } else { + tmpVal |= 1 << intType; + } + + /* Write back */ + BL_WR_REG(UARTx, UART_INT_CLEAR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Install uart interrupt callback function + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + + uartIntCbfArra[uartId][intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART send data to tx fifo + * + * @param uartId: UART ID type + * @param data: The data to be send + * @param len: The length of the send buffer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len) +{ + uint32_t txLen = 0; + uint32_t UARTx = uartAddr[uartId]; + uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Send data */ + while (txLen < len) { + if (UART_GetTxFifoCount(uartId) > 0) { + BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]); + timeoutCnt = UART_TX_TIMEOUT_COUNT; + } else { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART send data to tx fifo in block mode + * + * @param uartId: UART ID type + * @param data: The data to be send + * @param len: The length of the send buffer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len) +{ + uint32_t txLen = 0; + uint32_t UARTx = uartAddr[uartId]; + uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Send data */ + while (txLen < len) { + if (UART_GetTxFifoCount(uartId) > 0) { + BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]); + timeoutCnt = UART_TX_TIMEOUT_COUNT; + } else { + timeoutCnt--; + + if (timeoutCnt == 0) { + return TIMEOUT; + } + } + } + + while (UART_GetTxBusBusyStatus(uartId) == SET) { + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief UART receive data from rx fifo + * + * @param uartId: UART ID type + * @param data: The receive data buffer + * @param maxLen: The max length of the buffer + * + * @return The length of the received buffer + * +*******************************************************************************/ +uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen) +{ + uint32_t rxLen = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Receive data */ + while (rxLen < maxLen && UART_GetRxFifoCount(uartId) > 0) { + data[rxLen++] = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET); + } + + return rxLen; +} + +/****************************************************************************/ /** + * @brief UART get auto baud count value + * + * @param uartId: UART ID type + * @param autoBaudDet: Detection using codeword 0x55 or start bit + * + * @return Bit period of auto baudrate detection + * +*******************************************************************************/ +uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_AUTOBAUDDETECTION_TYPE(autoBaudDet)); + + /* Select 0x55 or start bit detection value */ + if (UART_AUTOBAUD_0X55 == autoBaudDet) { + return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) >> 0x10 & 0xffff; + } else { + return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) & 0xffff; + } +} + +/****************************************************************************/ /** + * @brief UART get tx fifo unoccupied count value + * + * @param uartId: UART ID type + * + * @return Tx fifo unoccupied count value + * +*******************************************************************************/ +uint8_t UART_GetTxFifoCount(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief UART get rx fifo occupied count value + * + * @param uartId: UART ID type + * + * @return Rx fifo occupied count value + * +*******************************************************************************/ +uint8_t UART_GetRxFifoCount(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT); +} + +/****************************************************************************/ /** + * @brief Get uart interrupt status + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * + * @return Status of interrupt + * +*******************************************************************************/ +BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + + /* Get certain or all interrupt status */ + tmpVal = BL_RD_REG(UARTx, UART_INT_STS); + + if (UART_INT_ALL == intType) { + if ((tmpVal & 0x1ff) != 0) { + return SET; + } else { + return RESET; + } + } else { + if ((tmpVal & (1U << intType)) != 0) { + return SET; + } else { + return RESET; + } + } +} + +/****************************************************************************/ /** + * @brief Get indicator of uart tx bus busy + * + * @param uartId: UART ID type + * + * @return Status of tx bus + * +*******************************************************************************/ +BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Get tx bus busy status */ + tmpVal = BL_RD_REG(UARTx, UART_STATUS); + + if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_UTX_BUS_BUSY)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Get indicator of uart rx bus busy + * + * @param uartId: UART ID type + * + * @return Status of rx bus + * +*******************************************************************************/ +BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Get rx bus busy status */ + tmpVal = BL_RD_REG(UARTx, UART_STATUS); + + if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_URX_BUS_BUSY)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief Get tx/rx fifo overflow or underflow status + * + * @param uartId: UART ID type + * @param overflow: Select tx/rx overflow or underflow + * + * @return Status of tx/rx fifo + * +*******************************************************************************/ +BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_OVERFLOW_TYPE(overflow)); + + /* Get tx/rx fifo overflow or underflow status */ + tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); + + if ((tmpVal & (1U << (overflow + 4))) != 0) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief UART0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void UART0_IRQHandler(void) +{ + UART_IntHandler(UART0_ID); +} +#endif + +/****************************************************************************/ /** + * @brief UART1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void UART1_IRQHandler(void) +{ + UART_IntHandler(UART1_ID); +} +#endif + +/*@} end of group UART_Public_Functions */ + +/*@} end of group UART */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_usb.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_usb.c new file mode 100644 index 0000000000000000000000000000000000000000..c86bf168d03a60f1ecc714d91f68339b76ff7a8a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_usb.c @@ -0,0 +1,2491 @@ +/** + ****************************************************************************** + * @file bl70x_usb.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702_usb.h" +#include "bl702_glb.h" +#include "bl702_common.h" + +/** @addtogroup BL70X_Peripheral_Driver + * @{ + */ + +/** @addtogroup USB + * @{ + */ + +/** @defgroup USB_Private_Macros + * @{ + */ + +/*@} end of group USB_Private_Macros */ + +/** @defgroup USB_Private_Types + * @{ + */ + +/*@} end of group USB_Private_Types */ + +/** @defgroup USB_Private_Variables + * @{ + */ + +/*@} end of group USB_Private_Variables */ + +/** @defgroup USB_Global_Variables + * @{ + */ + +/*@} end of group USB_Global_Variables */ + +/** @defgroup USB_Private_Fun_Declaration + * @{ + */ + +/*@} end of group USB_Private_Fun_Declaration */ + +/** @defgroup USB_Private_Functions + * @{ + */ + +/*@} end of group USB_Private_Functions */ + +/** @defgroup USB_Public_Functions + * @{ + */ + +BL_Err_Type USB_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EN); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EN); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_Set_Config(BL_Fun_Type enable, USB_Config_Type *usbCfg) +{ + uint32_t tmpVal = 0; + + /* disable USB first */ + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EN); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + + /* USB config */ + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + + if (usbCfg->SoftwareCtrl == ENABLE) { + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR, usbCfg->DeviceAddress); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, usbCfg->EnumMaxPacketSize); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_NACK_IN, usbCfg->EnumInEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT, usbCfg->EnumOutEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_ROM_DCT_EN, usbCfg->RomBaseDescriptorUsed); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_ROM_DCT_EN, usbCfg->RomBaseDescriptorUsed); + } + + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + + /* enable/disable USB */ + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EN); + } + + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_Set_Device_Addr(uint8_t addr) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR, addr); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + + return SUCCESS; +} + +uint8_t USB_Get_Device_Addr(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + + return BL_GET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR); +} + +BL_Err_Type USB_Set_EPx_Xfer_Size(USB_EP_ID epId, uint8_t size) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, size); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_IN_Busy(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_IN_Stall(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_OUT_Busy(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_OUT_Stall(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_NACK); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_Rdy(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_RDY); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_RDY); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_RDY); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_RDY); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_RDY); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_RDY); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_RDY); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_RDY); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Sts_Type USB_Is_EPx_RDY_Free(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_USB_EP0_SW_RDY); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP1_RDY); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP2_RDY); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP3_RDY); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP4_RDY); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP5_RDY); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP6_RDY); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP7_RDY); + break; + + default: + break; + } + } + + return tmpVal ? RESET : SET; +} + +BL_Err_Type USB_Set_EPx_STALL(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Clr_EPx_STALL(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + return SUCCESS; + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_Busy(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_Status(USB_EP_ID epId, USB_EP_STATUS_Type sts) +{ + switch (sts) { + case USB_EP_STATUS_ACK: + USB_Set_EPx_Rdy(epId); + break; + + case USB_EP_STATUS_NACK: + USB_Set_EPx_Busy(epId); + break; + + case USB_EP_STATUS_STALL: + USB_Set_EPx_STALL(epId); + break; + + case USB_EP_STATUS_NSTALL: + USB_Clr_EPx_STALL(epId); + break; + + default: + break; + } + + return SUCCESS; +} + +USB_EP_STATUS_Type USB_Get_EPx_Status(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + + switch ((tmpVal >> 24) & 0x7) { + case 0: + return USB_EP_STATUS_ACK; + + case 1: + return USB_EP_STATUS_STALL; + + case 2: + case 4: + case 6: + return USB_EP_STATUS_NACK; + + default: + break; + } + } else { + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + break; + + default: + tmpVal = 0; + break; + } + + switch ((tmpVal >> 14) & 0x3) { + case 0: + return USB_EP_STATUS_ACK; + + case 1: + return USB_EP_STATUS_STALL; + + case 2: + return USB_EP_STATUS_NACK; + + case 3: + default: + break; + } + } + + return USB_EP_STATUS_NSTALL; +} + +BL_Err_Type USB_IntEn(USB_INT_Type intType, uint8_t enable) +{ + uint32_t tmpVal = 0; + + if (USB_INT_ALL == intType) { + if (enable) { + BL_WR_REG(USB_BASE, USB_INT_EN, USB_INT_TYPE_ALL); + } else { + BL_WR_REG(USB_BASE, USB_INT_EN, ~USB_INT_TYPE_ALL); + } + + return SUCCESS; + } + + tmpVal = BL_RD_REG(USB_BASE, USB_INT_EN); + + if (enable) { + tmpVal |= (1 << intType); + } else { + tmpVal &= ~(1 << intType); + } + + BL_WR_REG(USB_BASE, USB_INT_EN, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_IntMask(USB_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal = 0; + + if (USB_INT_ALL == intType) { + if (intMask != UNMASK) { + BL_WR_REG(USB_BASE, USB_INT_MASK, USB_INT_TYPE_ALL); + } else { + BL_WR_REG(USB_BASE, USB_INT_MASK, ~USB_INT_TYPE_ALL); + } + + return SUCCESS; + } + + tmpVal = BL_RD_REG(USB_BASE, USB_INT_MASK); + + if (intMask != UNMASK) { + tmpVal |= (1 << intType); + } else { + tmpVal &= ~(1 << intType); + } + + BL_WR_REG(USB_BASE, USB_INT_MASK, tmpVal); + + return SUCCESS; +} + +BL_Sts_Type USB_Get_IntStatus(USB_INT_Type intType) +{ + if (USB_INT_ALL == intType) { + return BL_RD_REG(USB_BASE, USB_INT_STS) ? SET : RESET; + } + + return ((BL_RD_REG(USB_BASE, USB_INT_STS) & (1 << intType))) ? SET : RESET; +} + +BL_Err_Type USB_Clr_IntStatus(USB_INT_Type intType) +{ + uint32_t tmpVal = 0; + + if (USB_INT_ALL == intType) { + BL_WR_REG(USB_BASE, USB_INT_CLEAR, USB_INT_TYPE_ALL); + + return SUCCESS; + } + + tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR); + tmpVal |= (1 << intType); + BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_Clr_EPx_IntStatus(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR); + + if (epId == EP_ID0) { + tmpVal |= (0x3F << 4); + } else { + tmpVal |= (0x3 << (epId * 2 + 8)); + } + + BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal); + + return SUCCESS; +} + +uint16_t USB_Get_Frame_Num(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO); + + return tmpVal & 0x7ff; +} + +BL_Err_Type USB_Set_EPx_Config(USB_EP_ID epId, EP_Config_Type *epCfg) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + return ERROR; + } + + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE, epCfg->type); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR, epCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, epCfg->EPMaxPacketSize); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE, epCfg->type); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR, epCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, epCfg->EPMaxPacketSize); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE, epCfg->type); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR, epCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, epCfg->EPMaxPacketSize); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE, epCfg->type); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR, epCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, epCfg->EPMaxPacketSize); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE, epCfg->type); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR, epCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, epCfg->EPMaxPacketSize); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE, epCfg->type); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR, epCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, epCfg->EPMaxPacketSize); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE, epCfg->type); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR, epCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, epCfg->EPMaxPacketSize); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_Type(USB_EP_ID epId, EP_XFER_Type type) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + return ERROR; + } + + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE, type); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE, type); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE, type); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE, type); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE, type); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE, type); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE, type); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + + return SUCCESS; +} + +EP_XFER_Type USB_Get_EPx_Type(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + return EP_CTRL; + } + + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE); + break; + + default: + break; + } + + return (EP_XFER_Type)tmpVal; +} + +BL_Err_Type USB_Set_EPx_Dir(USB_EP_ID epId, EP_XFER_DIR dir) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + return ERROR; + } + + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR, dir); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR, dir); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR, dir); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR, dir); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR, dir); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR, dir); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR, dir); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + + return SUCCESS; +} + +EP_XFER_DIR USB_Get_EPx_Dir(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + if (epId == EP_ID0) { + return EP_DISABLED; + } + + switch (epId) { + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR); + break; + + default: + break; + } + + return (EP_XFER_DIR)tmpVal; +} + +BL_Err_Type USB_Set_EPx_Size(USB_EP_ID epId, uint32_t size) +{ + uint32_t tmpVal = 0; + + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, size); + BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, size); + BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal); + break; + + default: + break; + } + + return SUCCESS; +} + +BL_Sts_Type USB_Get_EPx_TX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag) +{ + uint32_t tmpVal = 0; + + if (errFlag == USB_FIFO_ERROR_OVERFLOW) { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_OVERFLOW); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_OVERFLOW); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_OVERFLOW); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_OVERFLOW); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_OVERFLOW); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_OVERFLOW); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_OVERFLOW); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_OVERFLOW); + break; + + default: + tmpVal = 0; + break; + } + } else { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_UNDERFLOW); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_UNDERFLOW); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_UNDERFLOW); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_UNDERFLOW); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_UNDERFLOW); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_UNDERFLOW); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_UNDERFLOW); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_UNDERFLOW); + break; + + default: + tmpVal = 0; + break; + } + } + + return tmpVal ? SET : RESET; +} + +BL_Sts_Type USB_Get_EPx_RX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag) +{ + uint32_t tmpVal = 0; + + if (errFlag == USB_FIFO_ERROR_OVERFLOW) { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_OVERFLOW); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_OVERFLOW); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_OVERFLOW); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_OVERFLOW); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_OVERFLOW); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_OVERFLOW); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_OVERFLOW); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_OVERFLOW); + break; + + default: + tmpVal = 0; + break; + } + } else { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_UNDERFLOW); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_UNDERFLOW); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_UNDERFLOW); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_UNDERFLOW); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_UNDERFLOW); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_UNDERFLOW); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_UNDERFLOW); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_UNDERFLOW); + break; + + default: + tmpVal = 0; + break; + } + } + + return tmpVal ? SET : RESET; +} + +BL_Err_Type USB_Clr_EPx_TX_FIFO_Errors(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_TX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_TX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_TX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_TX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_TX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_TX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_TX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_TX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal); + break; + + default: + break; + } + + return SUCCESS; +} + +BL_Err_Type USB_Clr_EPx_RX_FIFO_Errors(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_RX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_RX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_RX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_RX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_RX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_RX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_RX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_RX_FIFO_CLR); + BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal); + break; + + default: + break; + } + + return SUCCESS; +} + +BL_Err_Type USB_EPx_Write_Data_To_FIFO(USB_EP_ID epId, uint8_t *pData, uint16_t len) +{ + uint32_t timeout = 0x00FFFFFF; + + while ((!USB_Is_EPx_RDY_Free(epId)) && timeout) { + timeout--; + } + + if (!timeout) { + return ERROR; + } + + if (len == 1) { + USB_Set_EPx_Xfer_Size(EP_ID0, 1); + } else { + USB_Set_EPx_Xfer_Size(EP_ID0, 64); + } + + for (uint16_t i = 0; i < len; i++) { + switch (epId) { + case EP_ID0: + BL_WR_REG(USB_BASE, USB_EP0_TX_FIFO_WDATA, pData[i]); + break; + + case EP_ID1: + BL_WR_REG(USB_BASE, USB_EP1_TX_FIFO_WDATA, pData[i]); + break; + + case EP_ID2: + BL_WR_REG(USB_BASE, USB_EP2_TX_FIFO_WDATA, pData[i]); + break; + + case EP_ID3: + BL_WR_REG(USB_BASE, USB_EP3_TX_FIFO_WDATA, pData[i]); + break; + + case EP_ID4: + BL_WR_REG(USB_BASE, USB_EP4_TX_FIFO_WDATA, pData[i]); + break; + + case EP_ID5: + BL_WR_REG(USB_BASE, USB_EP5_TX_FIFO_WDATA, pData[i]); + break; + + case EP_ID6: + BL_WR_REG(USB_BASE, USB_EP6_TX_FIFO_WDATA, pData[i]); + break; + + case EP_ID7: + BL_WR_REG(USB_BASE, USB_EP7_TX_FIFO_WDATA, pData[i]); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_EPx_Read_Data_From_FIFO(USB_EP_ID epId, uint8_t *pBuff, uint16_t len) +{ + for (uint16_t i = 0; i < len; i++) { + switch (epId) { + case EP_ID0: + pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP0_RX_FIFO_RDATA); + break; + + case EP_ID1: + pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP1_RX_FIFO_RDATA); + break; + + case EP_ID2: + pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP2_RX_FIFO_RDATA); + break; + + case EP_ID3: + pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP3_RX_FIFO_RDATA); + break; + + case EP_ID4: + pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP4_RX_FIFO_RDATA); + break; + + case EP_ID5: + pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP5_RX_FIFO_RDATA); + break; + + case EP_ID6: + pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP6_RX_FIFO_RDATA); + break; + + case EP_ID7: + pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP7_RX_FIFO_RDATA); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_TX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState) +{ + uint32_t tmpVal = 0; + + if (newState == ENABLE) { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal); + break; + + default: + break; + } + } else { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP0_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP1_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP2_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP3_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP4_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP5_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP6_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP7_DMA_TX_EN); + BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_Set_EPx_RX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState) +{ + uint32_t tmpVal = 0; + + if (newState == ENABLE) { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal); + break; + + default: + break; + } + } else { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP0_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP1_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP2_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP3_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP4_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP5_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP6_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP7_DMA_RX_EN); + BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal); + break; + + default: + break; + } + } + + return SUCCESS; +} + +BL_Err_Type USB_EPx_Write_Data_To_FIFO_DMA(USB_EP_ID epId, uint8_t *pData, uint16_t len) +{ + /* not yet implemented */ + + return SUCCESS; +} + +BL_Err_Type USB_EPx_Read_Data_From_FIFO_DMA(USB_EP_ID epId, uint8_t *pBuff, uint16_t len) +{ + /* not yet implemented */ + + return SUCCESS; +} + +uint16_t USB_Get_EPx_TX_FIFO_CNT(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_CNT); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_CNT); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_CNT); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_CNT); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_CNT); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_CNT); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_CNT); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_CNT); + break; + + default: + tmpVal = 0; + break; + } + + return tmpVal; +} + +uint16_t USB_Get_EPx_RX_FIFO_CNT(USB_EP_ID epId) +{ + uint32_t tmpVal = 0; + + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_CNT); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_CNT); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_CNT); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_CNT); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_CNT); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_CNT); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_CNT); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_CNT); + break; + + default: + tmpVal = 0; + break; + } + + return tmpVal; +} + +BL_Sts_Type USB_Get_EPx_TX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts) +{ + uint32_t tmpVal = 0; + + if (sts == USB_FIFO_EMPTY) { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_EMPTY); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_EMPTY); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_EMPTY); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_EMPTY); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_EMPTY); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_EMPTY); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_EMPTY); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_EMPTY); + break; + + default: + tmpVal = 0; + break; + } + } else { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_FULL); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_FULL); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_FULL); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_FULL); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_FULL); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_FULL); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_FULL); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_FULL); + break; + + default: + tmpVal = 0; + break; + } + } + + return tmpVal ? SET : RESET; +} + +BL_Sts_Type USB_Get_EPx_RX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts) +{ + uint32_t tmpVal = 0; + + if (sts == USB_FIFO_EMPTY) { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_EMPTY); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_EMPTY); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_EMPTY); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_EMPTY); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_EMPTY); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_EMPTY); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_EMPTY); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_EMPTY); + break; + + default: + tmpVal = 0; + break; + } + } else { + switch (epId) { + case EP_ID0: + tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_FULL); + break; + + case EP_ID1: + tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_FULL); + break; + + case EP_ID2: + tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_FULL); + break; + + case EP_ID3: + tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_FULL); + break; + + case EP_ID4: + tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_FULL); + break; + + case EP_ID5: + tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_FULL); + break; + + case EP_ID6: + tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_FULL); + break; + + case EP_ID7: + tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_FULL); + break; + + default: + tmpVal = 0; + break; + } + } + + return tmpVal ? SET : RESET; +} + +BL_Err_Type USB_Set_Internal_PullUp_Config(BL_Fun_Type newState) +{ + uint32_t tmpVal = 0; + + /* recommended: fclk<=160MHz, bclk<=80MHz */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, newState); + BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal); + + return SUCCESS; +} + +BL_Sts_Type USB_Get_LPM_Status(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG); + + return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_LPM) ? SET : RESET; +} + +uint16_t USB_Get_LPM_Packet_Attr(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG); + + return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_LPM_ATTR); +} + +BL_Err_Type USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_Type defaultResp) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_LPM_RESP, defaultResp); + BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_LPM_RESP_UPD); + BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_LPM_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_LPM_EN); + BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_LPM_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_LPM_EN); + BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_Device_Output_K_State(uint16_t stateWidth) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((stateWidth <= 0x7FF)); + + tmpVal = BL_RD_REG(USB_BASE, USB_RESUME_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_RES_WIDTH, stateWidth); + BL_WR_REG(USB_BASE, USB_RESUME_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(USB_BASE, USB_RESUME_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_RES_TRIG); + BL_WR_REG(USB_BASE, USB_RESUME_CONFIG, tmpVal); + + return SUCCESS; +} + +uint8_t USB_Get_Current_Packet_PID(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO); + + return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_PID); +} + +uint8_t USB_Get_Current_Packet_EP(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO); + + return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP_NO); +} + +BL_Sts_Type USB_Get_Error_Status(USB_ERROR_Type err) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_ERROR); + + return tmpVal & (1 << err) ? SET : RESET; +} + +BL_Err_Type USB_Clr_Error_Status(USB_ERROR_Type err) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR); + tmpVal |= (1 << USB_INT_ERROR); + BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal); + + return SUCCESS; +} + +BL_Err_Type USB_Clr_RstEndIntStatus(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR); + tmpVal |= (1 << 27); + BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal); + + return SUCCESS; +} + +/*@} end of group USB_Public_Functions */ + +/*@} end of group USB */ + +/*@} end of group BL70X_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c new file mode 100644 index 0000000000000000000000000000000000000000..3bcebcaa28a63c334fd93440d2816cad91559908 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c @@ -0,0 +1,472 @@ +/** + ****************************************************************************** + * @file bl702_xip_sflash.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl702_xip_sflash.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_Private_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Macros */ + +/** @defgroup XIP_SFLASH_Private_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Types */ + +/** @defgroup XIP_SFLASH_Private_Variables + * @{ + */ +static uint8_t aesEnable; + +/*@} end of group XIP_SFLASH_Private_Variables */ + +/** @defgroup XIP_SFLASH_Global_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_Global_Variables */ + +/** @defgroup XIP_SFLASH_Private_Fun_Declaration + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ + +/** @defgroup XIP_SFLASH_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief XIP SFlash option save + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(void) +{ + aesEnable = SF_Ctrl_Is_AES_Enable(); + + if (aesEnable) { + SF_Ctrl_AES_Disable(); + } +} + +/****************************************************************************/ /** + * @brief XIP SFlash option restore + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(void) +{ + if (aesEnable) { + SF_Ctrl_AES_Enable(); + } +} + +/****************************************************************************/ /** + * @brief Save flash controller state + * + * @param pFlashCfg: Flash config pointer + * @param offset: CPU XIP flash offset pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) +{ + /* XIP_SFlash_Delay */ + volatile uint32_t i = 32 * 2; + + while (i--) + ; + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + /* Exit form continous read for accepting command */ + SFlash_Reset_Continue_Read(pFlashCfg); + /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */ + SFlash_Software_Reset(pFlashCfg); + /* For disable command that is setting register instaed of send command, we need write enable */ + SFlash_DisableBurstWrap(pFlashCfg); + /* Enable QE again in case reset command make it reset */ + SFlash_Qspi_Enable(pFlashCfg); + /* Deburst again to make sure */ + SFlash_DisableBurstWrap(pFlashCfg); + + /* Clear offset setting*/ + *offset = SF_Ctrl_Get_Flash_Image_Offset(); + SF_Ctrl_Set_Flash_Image_Offset(0); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Restore flash controller state + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param offset: CPU XIP flash offset + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset) +{ + uint32_t tmp[1]; + + SF_Ctrl_Set_Flash_Image_Offset(offset); + + SFlash_SetBurstWrap(pFlashCfg); + SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); + SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + + return SUCCESS; +} +#endif + +/*@} end of group XIP_SFLASH_Private_Functions */ + +/** @defgroup XIP_SFLASH_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Erase flash one region + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param startaddr: start address to erase + * @param endaddr: end address(include this address) to erase + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + } else { + stat = SFlash_Erase(pFlashCfg, startaddr, endaddr); + XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); + } + + return stat; +} +#endif + +/****************************************************************************/ /** + * @brief Program flash one region + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + } else { + stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len); + XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); + } + + return stat; +} +#endif + +/****************************************************************************/ /** + * @brief Read data from flash + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + } else { + stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len); + XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); + } + + return stat; +} +#endif + +/****************************************************************************/ /** + * @brief Get Flash Jedec ID + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param data: data pointer to store Jedec ID Read from flash + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + } else { + SFlash_GetJedecId(pFlashCfg, data); + XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get Flash Device ID + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param data: data pointer to store Device ID Read from flash + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + } else { + SFlash_GetDeviceId(data); + XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get Flash Unique ID + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param data: data pointer to store Device ID Read from flash + * @param idLen: Unique id len + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data, uint8_t idLen) +{ + BL_Err_Type stat; + uint32_t offset; + + stat = XIP_SFlash_State_Save(pFlashCfg, &offset); + + if (stat != SUCCESS) { + SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + } else { + SFlash_GetUniqueId(data, idLen); + XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Read data from flash via XIP + * + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) +{ + uint32_t offset; + + if (addr >= BL702_FLASH_XIP_BASE && addr < BL702_FLASH_XIP_END) { + offset = SF_Ctrl_Get_Flash_Image_Offset(); + SF_Ctrl_Set_Flash_Image_Offset(0); + /* Flash read */ + BL702_MemCpy_Fast(data, (void *)(addr - SF_Ctrl_Get_Flash_Image_Offset()), len); + SF_Ctrl_Set_Flash_Image_Offset(offset); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Read data from flash with lock + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param addr: flash read start address + * @param dst: data pointer to store data read from flash + * @param len: data length to read + * + * @return 0 + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *dst, int len) +{ + __disable_irq(); + XIP_SFlash_Read_Need_Lock(pFlashCfg, ioMode, addr, dst, len); + __enable_irq(); + return 0; +} +#endif + +/****************************************************************************/ /** + * @brief Program flash one region with lock + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param addr: Start address to be programed + * @param src: Data pointer to be programed + * @param len: Data length to be programed + * + * @return 0 + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *src, int len) +{ + __disable_irq(); + XIP_SFlash_Write_Need_Lock(pFlashCfg, ioMode, addr, src, len); + __enable_irq(); + return 0; +} +#endif + +/****************************************************************************/ /** + * @brief Erase flash one region with lock + * + * @param pFlashCfg: Flash config pointer + * @param ioMode: flash controller interface mode + * @param addr: Start address to be erased + * @param len: Data length to be erased + * + * @return 0 + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len) +{ + __disable_irq(); + XIP_SFlash_Erase_Need_Lock(pFlashCfg, ioMode, addr, addr + len - 1); + __enable_irq(); + return 0; +} +#endif + +/*@} end of group XIP_SFLASH_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c new file mode 100644 index 0000000000000000000000000000000000000000..09930bf6a5cfaabfc96d1c1f0efb6b22ac451608 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c @@ -0,0 +1,179 @@ +/** + ****************************************************************************** + * @file bl702_xip_sflash_ext.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl702_xip_sflash_ext.h" + +/** @addtogroup BL702_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_EXT_Private_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Macros */ + +/** @defgroup XIP_SFLASH_EXT_Private_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Types */ + +/** @defgroup XIP_SFLASH_EXT_Private_Variables + * @{ + */ + +static SPI_Flash_Cfg_Type flashCfg; + +/*@} end of group XIP_SFLASH_EXT_Private_Variables */ + +/** @defgroup XIP_SFLASH_EXT_Global_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Global_Variables */ + +/** @defgroup XIP_SFLASH_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Fun_Declaration */ + +/** @defgroup XIP_SFLASH_EXT_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Read data from flash with lock + * + * @param pFlashCfg:Flash config pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t ret; + + if (pFlashCfg == NULL) { + /* Get flash config identify */ + XIP_SFlash_Opt_Enter(); + ret = SF_Cfg_Flash_Identify_Ext(1, 1, 0, 0, &flashCfg); + XIP_SFlash_Opt_Exit(); + + if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) { + return ERROR; + } + } else { + memcpy(&flashCfg, pFlashCfg, sizeof(flashCfg)); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read data from flash with lock + * + * @param addr: flash read start address + * @param dst: data pointer to store data read from flash + * @param len: data length to read + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(); + XIP_SFlash_Read_Need_Lock(&flashCfg, flashCfg.ioMode & 0x0f, addr, dst, len); + XIP_SFlash_Opt_Exit(); + __enable_irq(); + return 0; +} + +/****************************************************************************/ /** + * @brief Program flash one region with lock + * + * @param addr: Start address to be programed + * @param src: Data pointer to be programed + * @param len: Data length to be programed + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(); + XIP_SFlash_Write_Need_Lock(&flashCfg, flashCfg.ioMode & 0x0f, addr, src, len); + XIP_SFlash_Opt_Exit(); + __enable_irq(); + return 0; +} + +/****************************************************************************/ /** + * @brief Erase flash one region with lock + * + * @param addr: Start address to be erased + * @param len: Data length to be erased + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Erase(uint32_t addr, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(); + XIP_SFlash_Erase_Need_Lock(&flashCfg, flashCfg.ioMode & 0x0f, addr, addr + len - 1); + XIP_SFlash_Opt_Exit(); + __enable_irq(); + return 0; +} + +/*@} end of group XIP_SFLASH_EXT_Public_Functions */ + +/*@} end of group XIP_SFLASH_EXT */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/hellowd/helloworld/main.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/hellowd/helloworld/main.c new file mode 100644 index 0000000000000000000000000000000000000000..12f75a0ad0ff7282171ef28194f81c0d617e35e2 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/hellowd/helloworld/main.c @@ -0,0 +1,39 @@ +/** + * @file main.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "hal_uart.h" + +int main(void) +{ + bflb_platform_init(0); + + for (uint8_t i = 0; i < 10; i++) { + MSG("hello world!\r\n"); + bflb_platform_delay_ms(200); + } + + BL_CASE_SUCCESS; + while (1) { + bflb_platform_delay_ms(100); + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/hellowd/helloworld/readme.md b/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/hellowd/helloworld/readme.md new file mode 100644 index 0000000000000000000000000000000000000000..bf2c1e39ad3070e0d855ac333e43dab506ff9c7b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/hellowd/helloworld/readme.md @@ -0,0 +1,5 @@ +```bash + +$ make APP=helloworld BOARD=bl706_iot + +``` \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/rt-thread/thread_delay/main.c b/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/rt-thread/thread_delay/main.c new file mode 100644 index 0000000000000000000000000000000000000000..d05ad2e09faa9c67b482f0e6ae2ca6f2e7df96b3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/examples/rt-thread/thread_delay/main.c @@ -0,0 +1,71 @@ +/** + * @file main.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include + +static rt_uint8_t test1_stack[512]; +struct rt_thread test1; + +static rt_uint8_t test2_stack[512]; +struct rt_thread test2; + +void test_thread1(void *parameter) +{ + rt_uint32_t count = 0; + while (1) { + rt_kprintf("test_thread1! %d\n", count++); + rt_thread_mdelay(2000); + } +} + +void test_thread2(void *parameter) +{ + rt_uint32_t count = 0; + while (1) { + rt_kprintf("test_thread2! %d\n", count++); + rt_thread_mdelay(500); + } +} + +extern void uart_shell_init(void); + +int main(void) +{ + rt_thread_t tid; + + uart_shell_init(); + + tid = &test1; + rt_thread_init(tid, "test1", test_thread1, RT_NULL, + test1_stack, sizeof(test1_stack), 9, 10); + rt_thread_startup(tid); + + tid = &test2; + rt_thread_init(tid, "test2", test_thread2, RT_NULL, + test2_stack, sizeof(test2_stack), 10, 10); + rt_thread_startup(tid); + + while (1) { + rt_kprintf("i am main thread\n"); + rt_thread_mdelay(1000); + } +} diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/project.build b/bsp/bouffalolab/libraries/bl_mcu_sdk/project.build new file mode 100644 index 0000000000000000000000000000000000000000..781f32768f05b29ae2c5f2f04c9ee65b6a135df1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/project.build @@ -0,0 +1,17 @@ +ifneq ($(CPU_ID),none) +cmake_definition+= -DCPU_ID=$(CPU_ID) +endif + +cmake_definition+= -DCHIP=$(CHIP) +cmake_definition+= -DBOARD=$(BOARD) +cmake_definition+= -DSUPPORT_FLOAT=$(SUPPORT_FLOAT) +cmake_definition+= -DSUPPORT_ROMAPI=$(SUPPORT_ROMAPI) +cmake_definition+= -DAPP_DIR=$(APP_DIR) +cmake_definition+= -DAPP=$(APP) +cmake_definition+= -DBOOTROM=$(BOOTROM) + +__build: + cmake $(cmake_definition) .. + make -j4 + +.PHONY:__build \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_iot_tool b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_iot_tool new file mode 100644 index 0000000000000000000000000000000000000000..9cfeb780d610d1c8ead32faebbb22ee3306b568f Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_iot_tool differ diff --git "a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_iot_tool\345\221\275\344\273\244\350\241\214\345\267\245\345\205\267\350\257\264\346\230\216.txt" "b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_iot_tool\345\221\275\344\273\244\350\241\214\345\267\245\345\205\267\350\257\264\346\230\216.txt" new file mode 100644 index 0000000000000000000000000000000000000000..ed2a4d0ac4323607a8b16fd1faf5b532b9833b60 --- /dev/null +++ "b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_iot_tool\345\221\275\344\273\244\350\241\214\345\267\245\345\205\267\350\257\264\346\230\216.txt" @@ -0,0 +1,21 @@ +build +bflb_iot_tool.exe --chipname=bl602 --xtal=40M --firmware="D:\\bouffalolab\\tool\\bflb-flash-tool\\img\\project.bin" --build + +build + download +bflb_iot_tool.exe --chipname=bl602 --port=COM9 --xtal=40M --firmware="D:\\bouffalolab\\tool\\bflb-flash-tool\\img\\project.bin" + + +--chipname:必填 +--interface:默认uart +--port:com口,默认自动查找 +--baudrate:波特率默认115200 +--xtal:xtal +--dts:device tree文件 +--firmware:默认img目录下的project.bin +--build:只生成镜像 +--erase:擦除flash +--single:单文件烧写 +--addr:烧写地址默认0 +--config:eflash_loader_cfg.ini +--ota:Haier ota文件输出路径 + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_mcu_tool b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_mcu_tool new file mode 100644 index 0000000000000000000000000000000000000000..41c69413145b2e163ded1e9dffa2def05a0c699a Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_mcu_tool differ diff --git "a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_mcu_tool\345\221\275\344\273\244\350\241\214\345\267\245\345\205\267\350\257\264\346\230\216.txt" "b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_mcu_tool\345\221\275\344\273\244\350\241\214\345\267\245\345\205\267\350\257\264\346\230\216.txt" new file mode 100644 index 0000000000000000000000000000000000000000..0189ef9c7158f8ca5ac2162715110743ce17ade2 --- /dev/null +++ "b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/bflb_mcu_tool\345\221\275\344\273\244\350\241\214\345\267\245\345\205\267\350\257\264\346\230\216.txt" @@ -0,0 +1,23 @@ +build +bflb_mcu_tool.exe --chipname=bl602 --xtal=40M --flashclk=48M --firmware="D:\\bouffalolab\\tool\\bflb-flash-tool\\img\\project.bin" --build + +build + download +bflb_mcu_tool.exe --chipname=bl602 --port=COM9 --xtal=40M --flashclk=48M --firmware="D:\\bouffalolab\\tool\\bflb-flash-tool\\img\\project.bin" + + +--chipname:必填 +--interface:默认uart +--bootsrc:默认flash +--port:com口,默认自动查找 +--baudrate:波特率默认115200 +--xtal:xtal +--flashclk:flash clock +--pllclk:pll clock +--firmware:默认img目录下的project.bin +--addr:烧写地址默认2000 +--build:只生成镜像 +--erase:擦除flash + + + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/conf/ota.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/conf/ota.toml new file mode 100644 index 0000000000000000000000000000000000000000..5e298fdf1625932dbb2cde4d973b79b17a8e2435 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/conf/ota.toml @@ -0,0 +1,5 @@ +[ota] +#max length of version_hardware is 15 bytes +version_hardware = "BFL_Module_v1.1" +#max length of version_software is 15 bytes +version_software = "EVENT_V1.1.1" diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_24M.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_24M.dts new file mode 100644 index 0000000000000000000000000000000000000000..560aaa08f19a91f15f72ea5bf0a1c41485d82afc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_24M.dts @@ -0,0 +1,348 @@ +/dts-v1/; +/include/ "bl602_base.dtsi"; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl602 IOT board"; + compatible = "bl,bl602-sample", "bl,bl602-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <5>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio2 { + status = "okay"; + pin = <2>; + feature = "button"; + active = "Hi"; + mode = "multipress"; + button { + debounce = <10>; + short_press_ms { + start = <100>; + end = <3000>; + kevent = <2>; + }; + long_press_ms { + start = <6000>; + end = <10000>; + kevent = <3>; + }; + longlong_press_ms { + start = <15000>; + kevent = <4>; + }; + trig_level = "Hi"; + }; + hbn_use = "disable"; + }; + }; + i2s { + #address-cells = <1>; + #size-cells = <1>; + i2s@40017000 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017000 0x100>; + mclk_only = "okay"; + pin { + mclk = <11>; + }; + }; + i2s@40017100 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017100 0x100>; + mclk_only = "disable"; + pin { + bclk = <12>; + fs = <29>; + do = <30>; + di = <31>; + }; + }; + }; + i2c { + #address-cells = <1>; + #size-cells = <1>; + i2c@40011000 { + status = "okay"; + compatible = "bl602_i2c"; + reg = <0x40011000 0x100>; + pin { + scl = <32>; + sda = <13>; + }; + devices { + list_addr = <0x18 0x21>; + list_driver = "i2c_es8311", "i2c_gc0308>"; + }; + }; + i2c@40011100 { + status = "disable"; + compatible = "bl602_i2c"; + reg = <0x40011100 0x100>; + pin { + /*empty here*/ + }; + }; + }; + timer { + #address-cells = <1>; + #size-cells = <1>; + timer@40014000 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014000 0x100>; + }; + timer@40014100 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014100 0x100>; + }; + }; + pwm { + #address-cells = <1>; + #size-cells = <1>; + pwm@4000A420 { + status = "okay"; + compatible = "bl602_pwm"; + reg = <0x4000A420 0x20>; + path = "/dev/pwm0"; + id = <0>; + pin = <0>; + freq = <800000>; + duty = <50>; + }; + pwm@4000A440 { + status = "disable"; + reg = <0x4000A440 0x20>; + path = "/dev/pwm1"; + id = <1>; + pin = <1>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A460 { + status = "disable"; + reg = <0x4000A460 0x20>; + path = "/dev/pwm2"; + id = <2>; + pin = <2>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A480 { + status = "disable"; + reg = <0x4000A480 0x20>; + path = "/dev/pwm3"; + id = <3>; + pin = <3>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A4A0 { + status = "disable"; + reg = <0x4000A4A0 0x20>; + path = "/dev/pwm4"; + id = <4>; + pin = <4>; + freq = <5000>; + duty = <50>; + }; + }; + ir { + #address-cells = <1>; + #size-cells = <1>; + ctrltype = <0>; + tx { + status = "disable"; + pin = <11>; // only support 11 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + interval = <100>; // ms + active_mode = "Hi"; //Hi,Lo + }; + rx { + status = "okay"; + pin = <12>; // only support 12 13 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + active_mode = "Hi"; //Hi,Lo + data_check = <2>; //bit 0:check cmd, bit 1:check addr + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl602_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <7>; + tx = <16>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "okay"; + id = <1>; + compatible = "bl602_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + spi { + #address-cells = <1>; + #size-cells = <1>; + spi@4000F000 { + status = "okay"; /* okay disable */ + mode = "master"; + reg = <0x4000F000 0x100>; /* 4KB */ + path = "/dev/spi0"; + port = <0>; + polar_phase = <1>; /* 0,1,2,3 */ + freq = <6000000>; + pin { + clk = <3>; + cs = <2>; + mosi = <1>; + miso = <0>; + }; + dma_cfg { + tx_dma_ch = <2>; + rx_dma_ch = <3>; + }; + }; + }; + gpip { + #address-cells = <1>; + #size-cells = <1>; + adc_key { + status = "disable"; + pin = <9>; + interrupt = <3>; + key_vol = <0 100 400 300 500>; + key_pcb = "SW1", "SW2", "SW3", "SW4","SW5"; + key_event = "Usr1", "Usr2", "Start", "Up", "Down"; + key_raw = <1 2 3 4 5>; + }; + }; + qspi { + #address-cells = <1>; + #size-cells = <1>; + qspi@4000A000 { + status = "disable"; + reg = <0x4000A000 0x1000>;/* 4KB */ + }; + }; + wifi { + #address-cells = <1>; + #size-cells = <1>; + region { + country_code = <86>; + }; + mac { + mode = "MBF"; + sta_mac_addr = [C8 43 57 82 73 40]; + ap_mac_addr = [C8 43 57 82 73 02]; + }; + sta { + ssid = "yourssid"; + pwd = "yourapssword"; + auto_connect_enable = <0>; + }; + ap { + ssid = "bl_test_005"; + pwd = "12345678"; + ap_channel = <11>; + auto_chan_detect = "disable"; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + /* + pwr_table = < 4 3 3 186 + 4 3 4 176 + 4 3 5 167 + 3 3 0 159 + 3 3 1 149 + 3 3 2 140 + 3 3 3 129 + 3 3 4 119 + 3 3 5 110 + 2 3 0 101 + 2 3 1 91 + 2 3 2 82 + 2 3 3 72 + 2 3 4 62 + 2 3 5 52 + 1 3 3 10>; + */ + pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode + pwr_table_11b = <20 20 20 18>;//1Mbps 2Mbps 5.5Mbps 11Mbps + pwr_table_11g = <18 18 18 18 18 18 14 14>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps + pwr_table_11n = <18 18 18 18 18 16 14 14>; //MCS0 MCS1 MCS2 MCS3 MCS4 MCS5 MCS6 MCS7 + pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 10. so 8 represents -2; 10 represents 0; 13 represents 3 + }; + rf_temp { + en_tcal = <0>; + linear_or_follow = <1>; + Tchannels = <2412 2427 2442 2457 2472>; + Tchannel_os = <180 168 163 160 157>; + Tchannel_os_low = <199 186 170 165 160>; + Troom_os = <255>; + //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256 + }; + }; + bluetooth { + #address-cells = <1>; + #size-cells = <1>; + brd_rf { + pwr_table_ble = <13>; //range:-3~15dbm; if set -3, please set 253 here + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_26M.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_26M.dts new file mode 100644 index 0000000000000000000000000000000000000000..560aaa08f19a91f15f72ea5bf0a1c41485d82afc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_26M.dts @@ -0,0 +1,348 @@ +/dts-v1/; +/include/ "bl602_base.dtsi"; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl602 IOT board"; + compatible = "bl,bl602-sample", "bl,bl602-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <5>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio2 { + status = "okay"; + pin = <2>; + feature = "button"; + active = "Hi"; + mode = "multipress"; + button { + debounce = <10>; + short_press_ms { + start = <100>; + end = <3000>; + kevent = <2>; + }; + long_press_ms { + start = <6000>; + end = <10000>; + kevent = <3>; + }; + longlong_press_ms { + start = <15000>; + kevent = <4>; + }; + trig_level = "Hi"; + }; + hbn_use = "disable"; + }; + }; + i2s { + #address-cells = <1>; + #size-cells = <1>; + i2s@40017000 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017000 0x100>; + mclk_only = "okay"; + pin { + mclk = <11>; + }; + }; + i2s@40017100 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017100 0x100>; + mclk_only = "disable"; + pin { + bclk = <12>; + fs = <29>; + do = <30>; + di = <31>; + }; + }; + }; + i2c { + #address-cells = <1>; + #size-cells = <1>; + i2c@40011000 { + status = "okay"; + compatible = "bl602_i2c"; + reg = <0x40011000 0x100>; + pin { + scl = <32>; + sda = <13>; + }; + devices { + list_addr = <0x18 0x21>; + list_driver = "i2c_es8311", "i2c_gc0308>"; + }; + }; + i2c@40011100 { + status = "disable"; + compatible = "bl602_i2c"; + reg = <0x40011100 0x100>; + pin { + /*empty here*/ + }; + }; + }; + timer { + #address-cells = <1>; + #size-cells = <1>; + timer@40014000 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014000 0x100>; + }; + timer@40014100 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014100 0x100>; + }; + }; + pwm { + #address-cells = <1>; + #size-cells = <1>; + pwm@4000A420 { + status = "okay"; + compatible = "bl602_pwm"; + reg = <0x4000A420 0x20>; + path = "/dev/pwm0"; + id = <0>; + pin = <0>; + freq = <800000>; + duty = <50>; + }; + pwm@4000A440 { + status = "disable"; + reg = <0x4000A440 0x20>; + path = "/dev/pwm1"; + id = <1>; + pin = <1>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A460 { + status = "disable"; + reg = <0x4000A460 0x20>; + path = "/dev/pwm2"; + id = <2>; + pin = <2>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A480 { + status = "disable"; + reg = <0x4000A480 0x20>; + path = "/dev/pwm3"; + id = <3>; + pin = <3>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A4A0 { + status = "disable"; + reg = <0x4000A4A0 0x20>; + path = "/dev/pwm4"; + id = <4>; + pin = <4>; + freq = <5000>; + duty = <50>; + }; + }; + ir { + #address-cells = <1>; + #size-cells = <1>; + ctrltype = <0>; + tx { + status = "disable"; + pin = <11>; // only support 11 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + interval = <100>; // ms + active_mode = "Hi"; //Hi,Lo + }; + rx { + status = "okay"; + pin = <12>; // only support 12 13 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + active_mode = "Hi"; //Hi,Lo + data_check = <2>; //bit 0:check cmd, bit 1:check addr + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl602_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <7>; + tx = <16>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "okay"; + id = <1>; + compatible = "bl602_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + spi { + #address-cells = <1>; + #size-cells = <1>; + spi@4000F000 { + status = "okay"; /* okay disable */ + mode = "master"; + reg = <0x4000F000 0x100>; /* 4KB */ + path = "/dev/spi0"; + port = <0>; + polar_phase = <1>; /* 0,1,2,3 */ + freq = <6000000>; + pin { + clk = <3>; + cs = <2>; + mosi = <1>; + miso = <0>; + }; + dma_cfg { + tx_dma_ch = <2>; + rx_dma_ch = <3>; + }; + }; + }; + gpip { + #address-cells = <1>; + #size-cells = <1>; + adc_key { + status = "disable"; + pin = <9>; + interrupt = <3>; + key_vol = <0 100 400 300 500>; + key_pcb = "SW1", "SW2", "SW3", "SW4","SW5"; + key_event = "Usr1", "Usr2", "Start", "Up", "Down"; + key_raw = <1 2 3 4 5>; + }; + }; + qspi { + #address-cells = <1>; + #size-cells = <1>; + qspi@4000A000 { + status = "disable"; + reg = <0x4000A000 0x1000>;/* 4KB */ + }; + }; + wifi { + #address-cells = <1>; + #size-cells = <1>; + region { + country_code = <86>; + }; + mac { + mode = "MBF"; + sta_mac_addr = [C8 43 57 82 73 40]; + ap_mac_addr = [C8 43 57 82 73 02]; + }; + sta { + ssid = "yourssid"; + pwd = "yourapssword"; + auto_connect_enable = <0>; + }; + ap { + ssid = "bl_test_005"; + pwd = "12345678"; + ap_channel = <11>; + auto_chan_detect = "disable"; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + /* + pwr_table = < 4 3 3 186 + 4 3 4 176 + 4 3 5 167 + 3 3 0 159 + 3 3 1 149 + 3 3 2 140 + 3 3 3 129 + 3 3 4 119 + 3 3 5 110 + 2 3 0 101 + 2 3 1 91 + 2 3 2 82 + 2 3 3 72 + 2 3 4 62 + 2 3 5 52 + 1 3 3 10>; + */ + pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode + pwr_table_11b = <20 20 20 18>;//1Mbps 2Mbps 5.5Mbps 11Mbps + pwr_table_11g = <18 18 18 18 18 18 14 14>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps + pwr_table_11n = <18 18 18 18 18 16 14 14>; //MCS0 MCS1 MCS2 MCS3 MCS4 MCS5 MCS6 MCS7 + pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 10. so 8 represents -2; 10 represents 0; 13 represents 3 + }; + rf_temp { + en_tcal = <0>; + linear_or_follow = <1>; + Tchannels = <2412 2427 2442 2457 2472>; + Tchannel_os = <180 168 163 160 157>; + Tchannel_os_low = <199 186 170 165 160>; + Troom_os = <255>; + //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256 + }; + }; + bluetooth { + #address-cells = <1>; + #size-cells = <1>; + brd_rf { + pwr_table_ble = <13>; //range:-3~15dbm; if set -3, please set 253 here + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_32M.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_32M.dts new file mode 100644 index 0000000000000000000000000000000000000000..560aaa08f19a91f15f72ea5bf0a1c41485d82afc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_32M.dts @@ -0,0 +1,348 @@ +/dts-v1/; +/include/ "bl602_base.dtsi"; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl602 IOT board"; + compatible = "bl,bl602-sample", "bl,bl602-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <5>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio2 { + status = "okay"; + pin = <2>; + feature = "button"; + active = "Hi"; + mode = "multipress"; + button { + debounce = <10>; + short_press_ms { + start = <100>; + end = <3000>; + kevent = <2>; + }; + long_press_ms { + start = <6000>; + end = <10000>; + kevent = <3>; + }; + longlong_press_ms { + start = <15000>; + kevent = <4>; + }; + trig_level = "Hi"; + }; + hbn_use = "disable"; + }; + }; + i2s { + #address-cells = <1>; + #size-cells = <1>; + i2s@40017000 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017000 0x100>; + mclk_only = "okay"; + pin { + mclk = <11>; + }; + }; + i2s@40017100 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017100 0x100>; + mclk_only = "disable"; + pin { + bclk = <12>; + fs = <29>; + do = <30>; + di = <31>; + }; + }; + }; + i2c { + #address-cells = <1>; + #size-cells = <1>; + i2c@40011000 { + status = "okay"; + compatible = "bl602_i2c"; + reg = <0x40011000 0x100>; + pin { + scl = <32>; + sda = <13>; + }; + devices { + list_addr = <0x18 0x21>; + list_driver = "i2c_es8311", "i2c_gc0308>"; + }; + }; + i2c@40011100 { + status = "disable"; + compatible = "bl602_i2c"; + reg = <0x40011100 0x100>; + pin { + /*empty here*/ + }; + }; + }; + timer { + #address-cells = <1>; + #size-cells = <1>; + timer@40014000 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014000 0x100>; + }; + timer@40014100 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014100 0x100>; + }; + }; + pwm { + #address-cells = <1>; + #size-cells = <1>; + pwm@4000A420 { + status = "okay"; + compatible = "bl602_pwm"; + reg = <0x4000A420 0x20>; + path = "/dev/pwm0"; + id = <0>; + pin = <0>; + freq = <800000>; + duty = <50>; + }; + pwm@4000A440 { + status = "disable"; + reg = <0x4000A440 0x20>; + path = "/dev/pwm1"; + id = <1>; + pin = <1>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A460 { + status = "disable"; + reg = <0x4000A460 0x20>; + path = "/dev/pwm2"; + id = <2>; + pin = <2>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A480 { + status = "disable"; + reg = <0x4000A480 0x20>; + path = "/dev/pwm3"; + id = <3>; + pin = <3>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A4A0 { + status = "disable"; + reg = <0x4000A4A0 0x20>; + path = "/dev/pwm4"; + id = <4>; + pin = <4>; + freq = <5000>; + duty = <50>; + }; + }; + ir { + #address-cells = <1>; + #size-cells = <1>; + ctrltype = <0>; + tx { + status = "disable"; + pin = <11>; // only support 11 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + interval = <100>; // ms + active_mode = "Hi"; //Hi,Lo + }; + rx { + status = "okay"; + pin = <12>; // only support 12 13 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + active_mode = "Hi"; //Hi,Lo + data_check = <2>; //bit 0:check cmd, bit 1:check addr + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl602_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <7>; + tx = <16>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "okay"; + id = <1>; + compatible = "bl602_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + spi { + #address-cells = <1>; + #size-cells = <1>; + spi@4000F000 { + status = "okay"; /* okay disable */ + mode = "master"; + reg = <0x4000F000 0x100>; /* 4KB */ + path = "/dev/spi0"; + port = <0>; + polar_phase = <1>; /* 0,1,2,3 */ + freq = <6000000>; + pin { + clk = <3>; + cs = <2>; + mosi = <1>; + miso = <0>; + }; + dma_cfg { + tx_dma_ch = <2>; + rx_dma_ch = <3>; + }; + }; + }; + gpip { + #address-cells = <1>; + #size-cells = <1>; + adc_key { + status = "disable"; + pin = <9>; + interrupt = <3>; + key_vol = <0 100 400 300 500>; + key_pcb = "SW1", "SW2", "SW3", "SW4","SW5"; + key_event = "Usr1", "Usr2", "Start", "Up", "Down"; + key_raw = <1 2 3 4 5>; + }; + }; + qspi { + #address-cells = <1>; + #size-cells = <1>; + qspi@4000A000 { + status = "disable"; + reg = <0x4000A000 0x1000>;/* 4KB */ + }; + }; + wifi { + #address-cells = <1>; + #size-cells = <1>; + region { + country_code = <86>; + }; + mac { + mode = "MBF"; + sta_mac_addr = [C8 43 57 82 73 40]; + ap_mac_addr = [C8 43 57 82 73 02]; + }; + sta { + ssid = "yourssid"; + pwd = "yourapssword"; + auto_connect_enable = <0>; + }; + ap { + ssid = "bl_test_005"; + pwd = "12345678"; + ap_channel = <11>; + auto_chan_detect = "disable"; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + /* + pwr_table = < 4 3 3 186 + 4 3 4 176 + 4 3 5 167 + 3 3 0 159 + 3 3 1 149 + 3 3 2 140 + 3 3 3 129 + 3 3 4 119 + 3 3 5 110 + 2 3 0 101 + 2 3 1 91 + 2 3 2 82 + 2 3 3 72 + 2 3 4 62 + 2 3 5 52 + 1 3 3 10>; + */ + pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode + pwr_table_11b = <20 20 20 18>;//1Mbps 2Mbps 5.5Mbps 11Mbps + pwr_table_11g = <18 18 18 18 18 18 14 14>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps + pwr_table_11n = <18 18 18 18 18 16 14 14>; //MCS0 MCS1 MCS2 MCS3 MCS4 MCS5 MCS6 MCS7 + pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 10. so 8 represents -2; 10 represents 0; 13 represents 3 + }; + rf_temp { + en_tcal = <0>; + linear_or_follow = <1>; + Tchannels = <2412 2427 2442 2457 2472>; + Tchannel_os = <180 168 163 160 157>; + Tchannel_os_low = <199 186 170 165 160>; + Troom_os = <255>; + //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256 + }; + }; + bluetooth { + #address-cells = <1>; + #size-cells = <1>; + brd_rf { + pwr_table_ble = <13>; //range:-3~15dbm; if set -3, please set 253 here + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_38.4M.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_38.4M.dts new file mode 100644 index 0000000000000000000000000000000000000000..560aaa08f19a91f15f72ea5bf0a1c41485d82afc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_38.4M.dts @@ -0,0 +1,348 @@ +/dts-v1/; +/include/ "bl602_base.dtsi"; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl602 IOT board"; + compatible = "bl,bl602-sample", "bl,bl602-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <5>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio2 { + status = "okay"; + pin = <2>; + feature = "button"; + active = "Hi"; + mode = "multipress"; + button { + debounce = <10>; + short_press_ms { + start = <100>; + end = <3000>; + kevent = <2>; + }; + long_press_ms { + start = <6000>; + end = <10000>; + kevent = <3>; + }; + longlong_press_ms { + start = <15000>; + kevent = <4>; + }; + trig_level = "Hi"; + }; + hbn_use = "disable"; + }; + }; + i2s { + #address-cells = <1>; + #size-cells = <1>; + i2s@40017000 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017000 0x100>; + mclk_only = "okay"; + pin { + mclk = <11>; + }; + }; + i2s@40017100 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017100 0x100>; + mclk_only = "disable"; + pin { + bclk = <12>; + fs = <29>; + do = <30>; + di = <31>; + }; + }; + }; + i2c { + #address-cells = <1>; + #size-cells = <1>; + i2c@40011000 { + status = "okay"; + compatible = "bl602_i2c"; + reg = <0x40011000 0x100>; + pin { + scl = <32>; + sda = <13>; + }; + devices { + list_addr = <0x18 0x21>; + list_driver = "i2c_es8311", "i2c_gc0308>"; + }; + }; + i2c@40011100 { + status = "disable"; + compatible = "bl602_i2c"; + reg = <0x40011100 0x100>; + pin { + /*empty here*/ + }; + }; + }; + timer { + #address-cells = <1>; + #size-cells = <1>; + timer@40014000 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014000 0x100>; + }; + timer@40014100 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014100 0x100>; + }; + }; + pwm { + #address-cells = <1>; + #size-cells = <1>; + pwm@4000A420 { + status = "okay"; + compatible = "bl602_pwm"; + reg = <0x4000A420 0x20>; + path = "/dev/pwm0"; + id = <0>; + pin = <0>; + freq = <800000>; + duty = <50>; + }; + pwm@4000A440 { + status = "disable"; + reg = <0x4000A440 0x20>; + path = "/dev/pwm1"; + id = <1>; + pin = <1>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A460 { + status = "disable"; + reg = <0x4000A460 0x20>; + path = "/dev/pwm2"; + id = <2>; + pin = <2>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A480 { + status = "disable"; + reg = <0x4000A480 0x20>; + path = "/dev/pwm3"; + id = <3>; + pin = <3>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A4A0 { + status = "disable"; + reg = <0x4000A4A0 0x20>; + path = "/dev/pwm4"; + id = <4>; + pin = <4>; + freq = <5000>; + duty = <50>; + }; + }; + ir { + #address-cells = <1>; + #size-cells = <1>; + ctrltype = <0>; + tx { + status = "disable"; + pin = <11>; // only support 11 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + interval = <100>; // ms + active_mode = "Hi"; //Hi,Lo + }; + rx { + status = "okay"; + pin = <12>; // only support 12 13 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + active_mode = "Hi"; //Hi,Lo + data_check = <2>; //bit 0:check cmd, bit 1:check addr + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl602_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <7>; + tx = <16>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "okay"; + id = <1>; + compatible = "bl602_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + spi { + #address-cells = <1>; + #size-cells = <1>; + spi@4000F000 { + status = "okay"; /* okay disable */ + mode = "master"; + reg = <0x4000F000 0x100>; /* 4KB */ + path = "/dev/spi0"; + port = <0>; + polar_phase = <1>; /* 0,1,2,3 */ + freq = <6000000>; + pin { + clk = <3>; + cs = <2>; + mosi = <1>; + miso = <0>; + }; + dma_cfg { + tx_dma_ch = <2>; + rx_dma_ch = <3>; + }; + }; + }; + gpip { + #address-cells = <1>; + #size-cells = <1>; + adc_key { + status = "disable"; + pin = <9>; + interrupt = <3>; + key_vol = <0 100 400 300 500>; + key_pcb = "SW1", "SW2", "SW3", "SW4","SW5"; + key_event = "Usr1", "Usr2", "Start", "Up", "Down"; + key_raw = <1 2 3 4 5>; + }; + }; + qspi { + #address-cells = <1>; + #size-cells = <1>; + qspi@4000A000 { + status = "disable"; + reg = <0x4000A000 0x1000>;/* 4KB */ + }; + }; + wifi { + #address-cells = <1>; + #size-cells = <1>; + region { + country_code = <86>; + }; + mac { + mode = "MBF"; + sta_mac_addr = [C8 43 57 82 73 40]; + ap_mac_addr = [C8 43 57 82 73 02]; + }; + sta { + ssid = "yourssid"; + pwd = "yourapssword"; + auto_connect_enable = <0>; + }; + ap { + ssid = "bl_test_005"; + pwd = "12345678"; + ap_channel = <11>; + auto_chan_detect = "disable"; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + /* + pwr_table = < 4 3 3 186 + 4 3 4 176 + 4 3 5 167 + 3 3 0 159 + 3 3 1 149 + 3 3 2 140 + 3 3 3 129 + 3 3 4 119 + 3 3 5 110 + 2 3 0 101 + 2 3 1 91 + 2 3 2 82 + 2 3 3 72 + 2 3 4 62 + 2 3 5 52 + 1 3 3 10>; + */ + pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode + pwr_table_11b = <20 20 20 18>;//1Mbps 2Mbps 5.5Mbps 11Mbps + pwr_table_11g = <18 18 18 18 18 18 14 14>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps + pwr_table_11n = <18 18 18 18 18 16 14 14>; //MCS0 MCS1 MCS2 MCS3 MCS4 MCS5 MCS6 MCS7 + pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 10. so 8 represents -2; 10 represents 0; 13 represents 3 + }; + rf_temp { + en_tcal = <0>; + linear_or_follow = <1>; + Tchannels = <2412 2427 2442 2457 2472>; + Tchannel_os = <180 168 163 160 157>; + Tchannel_os_low = <199 186 170 165 160>; + Troom_os = <255>; + //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256 + }; + }; + bluetooth { + #address-cells = <1>; + #size-cells = <1>; + brd_rf { + pwr_table_ble = <13>; //range:-3~15dbm; if set -3, please set 253 here + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_40M.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_40M.dts new file mode 100644 index 0000000000000000000000000000000000000000..560aaa08f19a91f15f72ea5bf0a1c41485d82afc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_40M.dts @@ -0,0 +1,348 @@ +/dts-v1/; +/include/ "bl602_base.dtsi"; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl602 IOT board"; + compatible = "bl,bl602-sample", "bl,bl602-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <5>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio2 { + status = "okay"; + pin = <2>; + feature = "button"; + active = "Hi"; + mode = "multipress"; + button { + debounce = <10>; + short_press_ms { + start = <100>; + end = <3000>; + kevent = <2>; + }; + long_press_ms { + start = <6000>; + end = <10000>; + kevent = <3>; + }; + longlong_press_ms { + start = <15000>; + kevent = <4>; + }; + trig_level = "Hi"; + }; + hbn_use = "disable"; + }; + }; + i2s { + #address-cells = <1>; + #size-cells = <1>; + i2s@40017000 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017000 0x100>; + mclk_only = "okay"; + pin { + mclk = <11>; + }; + }; + i2s@40017100 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017100 0x100>; + mclk_only = "disable"; + pin { + bclk = <12>; + fs = <29>; + do = <30>; + di = <31>; + }; + }; + }; + i2c { + #address-cells = <1>; + #size-cells = <1>; + i2c@40011000 { + status = "okay"; + compatible = "bl602_i2c"; + reg = <0x40011000 0x100>; + pin { + scl = <32>; + sda = <13>; + }; + devices { + list_addr = <0x18 0x21>; + list_driver = "i2c_es8311", "i2c_gc0308>"; + }; + }; + i2c@40011100 { + status = "disable"; + compatible = "bl602_i2c"; + reg = <0x40011100 0x100>; + pin { + /*empty here*/ + }; + }; + }; + timer { + #address-cells = <1>; + #size-cells = <1>; + timer@40014000 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014000 0x100>; + }; + timer@40014100 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014100 0x100>; + }; + }; + pwm { + #address-cells = <1>; + #size-cells = <1>; + pwm@4000A420 { + status = "okay"; + compatible = "bl602_pwm"; + reg = <0x4000A420 0x20>; + path = "/dev/pwm0"; + id = <0>; + pin = <0>; + freq = <800000>; + duty = <50>; + }; + pwm@4000A440 { + status = "disable"; + reg = <0x4000A440 0x20>; + path = "/dev/pwm1"; + id = <1>; + pin = <1>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A460 { + status = "disable"; + reg = <0x4000A460 0x20>; + path = "/dev/pwm2"; + id = <2>; + pin = <2>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A480 { + status = "disable"; + reg = <0x4000A480 0x20>; + path = "/dev/pwm3"; + id = <3>; + pin = <3>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A4A0 { + status = "disable"; + reg = <0x4000A4A0 0x20>; + path = "/dev/pwm4"; + id = <4>; + pin = <4>; + freq = <5000>; + duty = <50>; + }; + }; + ir { + #address-cells = <1>; + #size-cells = <1>; + ctrltype = <0>; + tx { + status = "disable"; + pin = <11>; // only support 11 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + interval = <100>; // ms + active_mode = "Hi"; //Hi,Lo + }; + rx { + status = "okay"; + pin = <12>; // only support 12 13 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + active_mode = "Hi"; //Hi,Lo + data_check = <2>; //bit 0:check cmd, bit 1:check addr + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl602_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <7>; + tx = <16>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "okay"; + id = <1>; + compatible = "bl602_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + spi { + #address-cells = <1>; + #size-cells = <1>; + spi@4000F000 { + status = "okay"; /* okay disable */ + mode = "master"; + reg = <0x4000F000 0x100>; /* 4KB */ + path = "/dev/spi0"; + port = <0>; + polar_phase = <1>; /* 0,1,2,3 */ + freq = <6000000>; + pin { + clk = <3>; + cs = <2>; + mosi = <1>; + miso = <0>; + }; + dma_cfg { + tx_dma_ch = <2>; + rx_dma_ch = <3>; + }; + }; + }; + gpip { + #address-cells = <1>; + #size-cells = <1>; + adc_key { + status = "disable"; + pin = <9>; + interrupt = <3>; + key_vol = <0 100 400 300 500>; + key_pcb = "SW1", "SW2", "SW3", "SW4","SW5"; + key_event = "Usr1", "Usr2", "Start", "Up", "Down"; + key_raw = <1 2 3 4 5>; + }; + }; + qspi { + #address-cells = <1>; + #size-cells = <1>; + qspi@4000A000 { + status = "disable"; + reg = <0x4000A000 0x1000>;/* 4KB */ + }; + }; + wifi { + #address-cells = <1>; + #size-cells = <1>; + region { + country_code = <86>; + }; + mac { + mode = "MBF"; + sta_mac_addr = [C8 43 57 82 73 40]; + ap_mac_addr = [C8 43 57 82 73 02]; + }; + sta { + ssid = "yourssid"; + pwd = "yourapssword"; + auto_connect_enable = <0>; + }; + ap { + ssid = "bl_test_005"; + pwd = "12345678"; + ap_channel = <11>; + auto_chan_detect = "disable"; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + /* + pwr_table = < 4 3 3 186 + 4 3 4 176 + 4 3 5 167 + 3 3 0 159 + 3 3 1 149 + 3 3 2 140 + 3 3 3 129 + 3 3 4 119 + 3 3 5 110 + 2 3 0 101 + 2 3 1 91 + 2 3 2 82 + 2 3 3 72 + 2 3 4 62 + 2 3 5 52 + 1 3 3 10>; + */ + pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode + pwr_table_11b = <20 20 20 18>;//1Mbps 2Mbps 5.5Mbps 11Mbps + pwr_table_11g = <18 18 18 18 18 18 14 14>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps + pwr_table_11n = <18 18 18 18 18 16 14 14>; //MCS0 MCS1 MCS2 MCS3 MCS4 MCS5 MCS6 MCS7 + pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 10. so 8 represents -2; 10 represents 0; 13 represents 3 + }; + rf_temp { + en_tcal = <0>; + linear_or_follow = <1>; + Tchannels = <2412 2427 2442 2457 2472>; + Tchannel_os = <180 168 163 160 157>; + Tchannel_os_low = <199 186 170 165 160>; + Troom_os = <255>; + //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256 + }; + }; + bluetooth { + #address-cells = <1>; + #size-cells = <1>; + brd_rf { + pwr_table_ble = <13>; //range:-3~15dbm; if set -3, please set 253 here + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_None.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_None.dts new file mode 100644 index 0000000000000000000000000000000000000000..560aaa08f19a91f15f72ea5bf0a1c41485d82afc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_None.dts @@ -0,0 +1,348 @@ +/dts-v1/; +/include/ "bl602_base.dtsi"; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl602 IOT board"; + compatible = "bl,bl602-sample", "bl,bl602-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <5>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio2 { + status = "okay"; + pin = <2>; + feature = "button"; + active = "Hi"; + mode = "multipress"; + button { + debounce = <10>; + short_press_ms { + start = <100>; + end = <3000>; + kevent = <2>; + }; + long_press_ms { + start = <6000>; + end = <10000>; + kevent = <3>; + }; + longlong_press_ms { + start = <15000>; + kevent = <4>; + }; + trig_level = "Hi"; + }; + hbn_use = "disable"; + }; + }; + i2s { + #address-cells = <1>; + #size-cells = <1>; + i2s@40017000 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017000 0x100>; + mclk_only = "okay"; + pin { + mclk = <11>; + }; + }; + i2s@40017100 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017100 0x100>; + mclk_only = "disable"; + pin { + bclk = <12>; + fs = <29>; + do = <30>; + di = <31>; + }; + }; + }; + i2c { + #address-cells = <1>; + #size-cells = <1>; + i2c@40011000 { + status = "okay"; + compatible = "bl602_i2c"; + reg = <0x40011000 0x100>; + pin { + scl = <32>; + sda = <13>; + }; + devices { + list_addr = <0x18 0x21>; + list_driver = "i2c_es8311", "i2c_gc0308>"; + }; + }; + i2c@40011100 { + status = "disable"; + compatible = "bl602_i2c"; + reg = <0x40011100 0x100>; + pin { + /*empty here*/ + }; + }; + }; + timer { + #address-cells = <1>; + #size-cells = <1>; + timer@40014000 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014000 0x100>; + }; + timer@40014100 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014100 0x100>; + }; + }; + pwm { + #address-cells = <1>; + #size-cells = <1>; + pwm@4000A420 { + status = "okay"; + compatible = "bl602_pwm"; + reg = <0x4000A420 0x20>; + path = "/dev/pwm0"; + id = <0>; + pin = <0>; + freq = <800000>; + duty = <50>; + }; + pwm@4000A440 { + status = "disable"; + reg = <0x4000A440 0x20>; + path = "/dev/pwm1"; + id = <1>; + pin = <1>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A460 { + status = "disable"; + reg = <0x4000A460 0x20>; + path = "/dev/pwm2"; + id = <2>; + pin = <2>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A480 { + status = "disable"; + reg = <0x4000A480 0x20>; + path = "/dev/pwm3"; + id = <3>; + pin = <3>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A4A0 { + status = "disable"; + reg = <0x4000A4A0 0x20>; + path = "/dev/pwm4"; + id = <4>; + pin = <4>; + freq = <5000>; + duty = <50>; + }; + }; + ir { + #address-cells = <1>; + #size-cells = <1>; + ctrltype = <0>; + tx { + status = "disable"; + pin = <11>; // only support 11 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + interval = <100>; // ms + active_mode = "Hi"; //Hi,Lo + }; + rx { + status = "okay"; + pin = <12>; // only support 12 13 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + active_mode = "Hi"; //Hi,Lo + data_check = <2>; //bit 0:check cmd, bit 1:check addr + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl602_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <7>; + tx = <16>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "okay"; + id = <1>; + compatible = "bl602_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + spi { + #address-cells = <1>; + #size-cells = <1>; + spi@4000F000 { + status = "okay"; /* okay disable */ + mode = "master"; + reg = <0x4000F000 0x100>; /* 4KB */ + path = "/dev/spi0"; + port = <0>; + polar_phase = <1>; /* 0,1,2,3 */ + freq = <6000000>; + pin { + clk = <3>; + cs = <2>; + mosi = <1>; + miso = <0>; + }; + dma_cfg { + tx_dma_ch = <2>; + rx_dma_ch = <3>; + }; + }; + }; + gpip { + #address-cells = <1>; + #size-cells = <1>; + adc_key { + status = "disable"; + pin = <9>; + interrupt = <3>; + key_vol = <0 100 400 300 500>; + key_pcb = "SW1", "SW2", "SW3", "SW4","SW5"; + key_event = "Usr1", "Usr2", "Start", "Up", "Down"; + key_raw = <1 2 3 4 5>; + }; + }; + qspi { + #address-cells = <1>; + #size-cells = <1>; + qspi@4000A000 { + status = "disable"; + reg = <0x4000A000 0x1000>;/* 4KB */ + }; + }; + wifi { + #address-cells = <1>; + #size-cells = <1>; + region { + country_code = <86>; + }; + mac { + mode = "MBF"; + sta_mac_addr = [C8 43 57 82 73 40]; + ap_mac_addr = [C8 43 57 82 73 02]; + }; + sta { + ssid = "yourssid"; + pwd = "yourapssword"; + auto_connect_enable = <0>; + }; + ap { + ssid = "bl_test_005"; + pwd = "12345678"; + ap_channel = <11>; + auto_chan_detect = "disable"; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + /* + pwr_table = < 4 3 3 186 + 4 3 4 176 + 4 3 5 167 + 3 3 0 159 + 3 3 1 149 + 3 3 2 140 + 3 3 3 129 + 3 3 4 119 + 3 3 5 110 + 2 3 0 101 + 2 3 1 91 + 2 3 2 82 + 2 3 3 72 + 2 3 4 62 + 2 3 5 52 + 1 3 3 10>; + */ + pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode + pwr_table_11b = <20 20 20 18>;//1Mbps 2Mbps 5.5Mbps 11Mbps + pwr_table_11g = <18 18 18 18 18 18 14 14>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps + pwr_table_11n = <18 18 18 18 18 16 14 14>; //MCS0 MCS1 MCS2 MCS3 MCS4 MCS5 MCS6 MCS7 + pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 10. so 8 represents -2; 10 represents 0; 13 represents 3 + }; + rf_temp { + en_tcal = <0>; + linear_or_follow = <1>; + Tchannels = <2412 2427 2442 2457 2472>; + Tchannel_os = <180 168 163 160 157>; + Tchannel_os_low = <199 186 170 165 160>; + Troom_os = <255>; + //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256 + }; + }; + bluetooth { + #address-cells = <1>; + #size-cells = <1>; + brd_rf { + pwr_table_ble = <13>; //range:-3~15dbm; if set -3, please set 253 here + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_RC32M.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_RC32M.dts new file mode 100644 index 0000000000000000000000000000000000000000..560aaa08f19a91f15f72ea5bf0a1c41485d82afc --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/device_tree/bl_factory_params_IoTKitA_RC32M.dts @@ -0,0 +1,348 @@ +/dts-v1/; +/include/ "bl602_base.dtsi"; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl602 IOT board"; + compatible = "bl,bl602-sample", "bl,bl602-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <5>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat + time = <100>; //duration for this mode + }; + gpio2 { + status = "okay"; + pin = <2>; + feature = "button"; + active = "Hi"; + mode = "multipress"; + button { + debounce = <10>; + short_press_ms { + start = <100>; + end = <3000>; + kevent = <2>; + }; + long_press_ms { + start = <6000>; + end = <10000>; + kevent = <3>; + }; + longlong_press_ms { + start = <15000>; + kevent = <4>; + }; + trig_level = "Hi"; + }; + hbn_use = "disable"; + }; + }; + i2s { + #address-cells = <1>; + #size-cells = <1>; + i2s@40017000 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017000 0x100>; + mclk_only = "okay"; + pin { + mclk = <11>; + }; + }; + i2s@40017100 { + status = "okay"; + compatible = "bl602_i2s"; + reg = <0x40017100 0x100>; + mclk_only = "disable"; + pin { + bclk = <12>; + fs = <29>; + do = <30>; + di = <31>; + }; + }; + }; + i2c { + #address-cells = <1>; + #size-cells = <1>; + i2c@40011000 { + status = "okay"; + compatible = "bl602_i2c"; + reg = <0x40011000 0x100>; + pin { + scl = <32>; + sda = <13>; + }; + devices { + list_addr = <0x18 0x21>; + list_driver = "i2c_es8311", "i2c_gc0308>"; + }; + }; + i2c@40011100 { + status = "disable"; + compatible = "bl602_i2c"; + reg = <0x40011100 0x100>; + pin { + /*empty here*/ + }; + }; + }; + timer { + #address-cells = <1>; + #size-cells = <1>; + timer@40014000 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014000 0x100>; + }; + timer@40014100 { + status = "disable"; + compatible = "bl602_timer"; + reg = <0x40014100 0x100>; + }; + }; + pwm { + #address-cells = <1>; + #size-cells = <1>; + pwm@4000A420 { + status = "okay"; + compatible = "bl602_pwm"; + reg = <0x4000A420 0x20>; + path = "/dev/pwm0"; + id = <0>; + pin = <0>; + freq = <800000>; + duty = <50>; + }; + pwm@4000A440 { + status = "disable"; + reg = <0x4000A440 0x20>; + path = "/dev/pwm1"; + id = <1>; + pin = <1>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A460 { + status = "disable"; + reg = <0x4000A460 0x20>; + path = "/dev/pwm2"; + id = <2>; + pin = <2>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A480 { + status = "disable"; + reg = <0x4000A480 0x20>; + path = "/dev/pwm3"; + id = <3>; + pin = <3>; + freq = <5000>; + duty = <50>; + }; + pwm@4000A4A0 { + status = "disable"; + reg = <0x4000A4A0 0x20>; + path = "/dev/pwm4"; + id = <4>; + pin = <4>; + freq = <5000>; + duty = <50>; + }; + }; + ir { + #address-cells = <1>; + #size-cells = <1>; + ctrltype = <0>; + tx { + status = "disable"; + pin = <11>; // only support 11 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + interval = <100>; // ms + active_mode = "Hi"; //Hi,Lo + }; + rx { + status = "okay"; + pin = <12>; // only support 12 13 + mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM + active_mode = "Hi"; //Hi,Lo + data_check = <2>; //bit 0:check cmd, bit 1:check addr + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl602_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <7>; + tx = <16>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "okay"; + id = <1>; + compatible = "bl602_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + buf_size { + rx_size = <512>; + tx_size = <512>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + spi { + #address-cells = <1>; + #size-cells = <1>; + spi@4000F000 { + status = "okay"; /* okay disable */ + mode = "master"; + reg = <0x4000F000 0x100>; /* 4KB */ + path = "/dev/spi0"; + port = <0>; + polar_phase = <1>; /* 0,1,2,3 */ + freq = <6000000>; + pin { + clk = <3>; + cs = <2>; + mosi = <1>; + miso = <0>; + }; + dma_cfg { + tx_dma_ch = <2>; + rx_dma_ch = <3>; + }; + }; + }; + gpip { + #address-cells = <1>; + #size-cells = <1>; + adc_key { + status = "disable"; + pin = <9>; + interrupt = <3>; + key_vol = <0 100 400 300 500>; + key_pcb = "SW1", "SW2", "SW3", "SW4","SW5"; + key_event = "Usr1", "Usr2", "Start", "Up", "Down"; + key_raw = <1 2 3 4 5>; + }; + }; + qspi { + #address-cells = <1>; + #size-cells = <1>; + qspi@4000A000 { + status = "disable"; + reg = <0x4000A000 0x1000>;/* 4KB */ + }; + }; + wifi { + #address-cells = <1>; + #size-cells = <1>; + region { + country_code = <86>; + }; + mac { + mode = "MBF"; + sta_mac_addr = [C8 43 57 82 73 40]; + ap_mac_addr = [C8 43 57 82 73 02]; + }; + sta { + ssid = "yourssid"; + pwd = "yourapssword"; + auto_connect_enable = <0>; + }; + ap { + ssid = "bl_test_005"; + pwd = "12345678"; + ap_channel = <11>; + auto_chan_detect = "disable"; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + /* + pwr_table = < 4 3 3 186 + 4 3 4 176 + 4 3 5 167 + 3 3 0 159 + 3 3 1 149 + 3 3 2 140 + 3 3 3 129 + 3 3 4 119 + 3 3 5 110 + 2 3 0 101 + 2 3 1 91 + 2 3 2 82 + 2 3 3 72 + 2 3 4 62 + 2 3 5 52 + 1 3 3 10>; + */ + pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode + pwr_table_11b = <20 20 20 18>;//1Mbps 2Mbps 5.5Mbps 11Mbps + pwr_table_11g = <18 18 18 18 18 18 14 14>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps + pwr_table_11n = <18 18 18 18 18 16 14 14>; //MCS0 MCS1 MCS2 MCS3 MCS4 MCS5 MCS6 MCS7 + pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 10. so 8 represents -2; 10 represents 0; 13 represents 3 + }; + rf_temp { + en_tcal = <0>; + linear_or_follow = <1>; + Tchannels = <2412 2427 2442 2457 2472>; + Tchannel_os = <180 168 163 160 157>; + Tchannel_os_low = <199 186 170 165 160>; + Troom_os = <255>; + //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256 + }; + }; + bluetooth { + #address-cells = <1>; + #size-cells = <1>; + brd_rf { + pwr_table_ble = <13>; //range:-3~15dbm; if set -3, please set 253 here + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/eflash_loader/eflash_loader_cfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/eflash_loader/eflash_loader_cfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..52b3f924485cf1ed979910c8cdd25095b50fa779 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/eflash_loader/eflash_loader_cfg.conf @@ -0,0 +1,57 @@ +[LOAD_CFG] +#jlink or uart +interface = uart +device = COM1 +speed_uart_boot = 500000 +speed_uart_load = 500000 +speed_jlink = 2000 +#eg: rv_dbg_plus, ft2232hl, ft2232d +openocd_config = rv_dbg_plus +#0:without load, 1:eflash_loader load +load_function = 1 +auto_burn = false +do_reset = true +#reset retry+reset hold time +reset_hold_time = 5 +shake_hand_delay = 100 +reset_revert = false +#cutoff revert+cutoff time +cutoff_time = 100 +shake_hand_retry = 2 +flash_burn_retry = 1 +checksum_err_retry = 3 +iap_shakehand_timeout = 0 +#1:24M, 2:32M, 3:38.4M, 4:40M, 5:26M, 6:RC32M +#xtal_type = 4 +erase_time_out = 15000 +#chiptype=602 +eflash_loader_file = chips/bl602/eflash_loader/eflash_loader_40m.bin +check_mac = false +#0:no erase,1:programmed section erase,2:chip erase +erase = 1 +# switch eflash_loader command log save +local_log = false +#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus) +verify = 0 +tx_size = 2056 +cpu_reset_after_load = false + +[FLASH_CFG] +flash_id = ef4015 +flash_clock_cfg = 1 +#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO +flash_io_mode = 1 +#empty: auto,0: internal flash with io switch,1: internal flash no io switch,2: GPIO 17-22,3: GPIO 0-2&20-22 +flash_pin = "" +#empty for auto, otherwise specified para file path: eg: chips/bl602/efuse_bootheader/flash_para.bin +flash_para = chips/bl602/efuse_bootheader/flash_para.bin +decompress_write = true +file = chips/bl602/img_create/bootinfo_boot2.bin chips/bl602/img_create/img_boot2.bin chips/bl602/partition/partition.bin chips/bl602/partition/partition.bin +address = 00000000 00002000 e000 f000 + +[EFUSE_CFG] +burn_en = true +factory_mode = false +security_write = false +file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin +maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/efuse_bootheader/efuse_bootheader_cfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/efuse_bootheader/efuse_bootheader_cfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..3ee8bc737f8565c7b3f9562a9b2ae4e15309055d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/efuse_bootheader/efuse_bootheader_cfg.conf @@ -0,0 +1,196 @@ +[EFUSE_CFG] +######################################################################## +#2bits +ef_sf_aes_mode = 0 +#2bits +ef_sboot_sign_mode = 0 +#2bits +ef_sboot_en = 0 +#2bits +ef_dbg_jtag_dis = 0 +#4bits +ef_dbg_mode = 0 +#32bits +ef_dbg_pwd_low = 0 +#32bits +ef_dbg_pwd_high = 0 +#2bits +flash_pwr_delay = 0 +################################################################### +ef_key_slot_2_w0 = 0 +ef_key_slot_2_w1 = 0 +ef_key_slot_2_w2 = 0 +ef_key_slot_2_w3 = 0 +ef_key_slot_3_w0 = 0 +ef_key_slot_3_w1 = 0 +ef_key_slot_3_w2 = 0 +ef_key_slot_3_w3 = 0 +ef_key_slot_4_w0 = 0 +ef_key_slot_4_w1 = 0 +ef_key_slot_4_w2 = 0 +ef_key_slot_4_w3 = 0 + +wr_lock_key_slot_4_l = 0 +wr_lock_dbg_pwd = 0 +wr_lock_key_slot_2 = 0 +wr_lock_key_slot_3 = 0 +wr_lock_key_slot_4_h = 0 +rd_lock_dbg_pwd = 0 +rd_lock_key_slot_2 = 0 +rd_lock_key_slot_3 = 0 +rd_lock_key_slot_4 = 0 + +[BOOTHEADER_CFG] +magic_code = 0x504e4642 +revision = 0x01 +#########################flash cfg############################# +flashcfg_magic_code = 0x47464346 +#flashcfg_magic_code=0 +io_mode = 4 +cont_read_support = 1 +#0.5T sfctrl_clk_delay=0 sfctrl_clk_invert=3 +#1 T sfctrl_clk_delay=1 sfctrl_clk_invert=1 +#1.5T sfctrl_clk_delay=1 sfctrl_clk_invert=3 +sfctrl_clk_delay = 1 +sfctrl_clk_invert = 0x01 + +reset_en_cmd = 0x66 +reset_cmd = 0x99 +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 + +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 + +sector_size = 4 +mfg_id = 0xc8 +page_size = 256 + +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 + +write_enable_cmd = 0x06 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 + +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 + +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 + +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 + +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 + +wel_reg_index = 0 +qe_reg_index = 1 +busy_reg_index = 0 +wel_bit_pos = 1 + +qe_bit_pos = 1 +busy_bit_pos = 0 +wel_reg_write_len = 2 +wel_reg_read_len = 1 + +qe_reg_write_len = 2 +qe_reg_read_len = 1 +release_power_down = 0xab +busy_reg_read_len = 1 + +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 + +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 + +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +cont_read_code = 0xa0 +cont_read_exit_code = 0xff + +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 + +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 + +sector_erase_time = 300 +blk32k_erase_time = 1200 + +blk64k_erase_time = 1200 +page_prog_time = 5 + +chip_erase_time = 200000 +power_down_delay = 20 +qe_data = 0 + +flashcfg_crc32 = 0 + +#########################clk cfg#################################### +clkcfg_magic_code = 0x47464350 +#clkcfg_magic_code=0 + +#0:Not use XTAL to set PLL,1:XTAL is 24M ,2:XTAL is 32M ,3:XTAL is 38.4M +#4:XTAL is 40M,5:XTAL is 26M,6:XTAL is RC32M +xtal_type = 4 +#0:RC32M,1:XTAL,2:PLL 48M,3:PLL 120M,4:PLL 160M,5:PLL 192M +pll_clk = 4 +hclk_div = 0 +bclk_div = 1 +#0:120M,1:XCLK(RC32M or XTAL),2:48M,3:80M,4:BCLK,5:96M +flash_clk_type = 3 +flash_clk_div = 1 +clkcfg_crc32 = 0 + +########################boot cfg#################################### +#1:ECC +sign = 0 +#1:AES128,2:AES256,3:AES192 +encrypt_type = 0 +key_sel = 0 +no_segment = 1 +cache_enable = 1 +notload_in_bootrom = 0 +aes_region_lock = 0 +cache_way_disable = 0x03 +crc_ignore = 0 +hash_ignore = 0 + +########################image cfg#################################### +#total image len or segment count +img_len = 0x100 +bootentry = 0 +#img RAM address or flash offset +img_start = 0x2000 + +#img hash +hash_0 = 0xdeadbeef +hash_1 = 0 +hash_2 = 0 +hash_3 = 0 +hash_4 = 0 +hash_5 = 0 +hash_6 = 0 +hash_7 = 0 + +crc32 = 0xdeadbeef diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..a24f92e8e902d01fc98b72c58891e8989d0d5866 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg.conf @@ -0,0 +1,15 @@ +[Img_Cfg] +boot_header_file = +efuse_file = +efuse_mask_file = +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = img_create/aesiv_cpu0.bin +publickey_file = img_create/publickey_uecc.pem +privatekey_file_uecc = img_create/privatekey_uecc.pem +segheader_file = img_create/segheader.bin +segdata_file = +bootinfo_file = +img_file = +whole_img_file = +aes_key_org = 00000000000000000000000000000000 +aes_iv = 00000000000000000000000000000000 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg_boot2.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg_boot2.conf new file mode 100644 index 0000000000000000000000000000000000000000..b71edcb63df4d9bcf3766647fa840a145ae489af --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg_boot2.conf @@ -0,0 +1,15 @@ +[Img_Cfg] +boot_header_file = +efuse_file = +efuse_mask_file = +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = img_create/aesiv.bin +publickey_file = img_create/publickey_uecc.pem +privatekey_file_uecc = img_create/privatekey_uecc.pem +segheader_file = img_create/segheader.bin +segdata_file = +bootinfo_file = +img_file = +whole_img_file = +aes_key_org = 11 +aes_iv = 11 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg_mfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg_mfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..20e9f51751bcb6ab5b1512f294d873d08f708452 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_iot/img_create_cfg_mfg.conf @@ -0,0 +1,13 @@ +[Img_Cfg] +boot_header_file = ./efuse_bootheader/bootheader.bin +efuse_file = ./efuse_bootheader/efusedata.bin +efuse_mask_file = ./efuse_bootheader/efusedata_mask.bin +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = ./img_create/aesiv.bin +publickey_file = ./img_create/publickey_uecc.pem +privatekey_file_uecc = ./img_create/privatekey_uecc.pem +segheader_file = ./img_create/segheader.bin +segdata_file = +bootinfo_file = ./img_create/bootinfo_mfg.bin +img_file = ./img_create/img_mfg.bin +whole_img_file = ./img_create/wholeimg_mfg_if.bin diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..a24f92e8e902d01fc98b72c58891e8989d0d5866 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg.conf @@ -0,0 +1,15 @@ +[Img_Cfg] +boot_header_file = +efuse_file = +efuse_mask_file = +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = img_create/aesiv_cpu0.bin +publickey_file = img_create/publickey_uecc.pem +privatekey_file_uecc = img_create/privatekey_uecc.pem +segheader_file = img_create/segheader.bin +segdata_file = +bootinfo_file = +img_file = +whole_img_file = +aes_key_org = 00000000000000000000000000000000 +aes_iv = 00000000000000000000000000000000 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg_boot2.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg_boot2.conf new file mode 100644 index 0000000000000000000000000000000000000000..b71edcb63df4d9bcf3766647fa840a145ae489af --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg_boot2.conf @@ -0,0 +1,15 @@ +[Img_Cfg] +boot_header_file = +efuse_file = +efuse_mask_file = +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = img_create/aesiv.bin +publickey_file = img_create/publickey_uecc.pem +privatekey_file_uecc = img_create/privatekey_uecc.pem +segheader_file = img_create/segheader.bin +segdata_file = +bootinfo_file = +img_file = +whole_img_file = +aes_key_org = 11 +aes_iv = 11 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg_mfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg_mfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..20e9f51751bcb6ab5b1512f294d873d08f708452 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/img_create_mcu/img_create_cfg_mfg.conf @@ -0,0 +1,13 @@ +[Img_Cfg] +boot_header_file = ./efuse_bootheader/bootheader.bin +efuse_file = ./efuse_bootheader/efusedata.bin +efuse_mask_file = ./efuse_bootheader/efusedata_mask.bin +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = ./img_create/aesiv.bin +publickey_file = ./img_create/publickey_uecc.pem +privatekey_file_uecc = ./img_create/privatekey_uecc.pem +segheader_file = ./img_create/segheader.bin +segdata_file = +bootinfo_file = ./img_create/bootinfo_mfg.bin +img_file = ./img_create/img_mfg.bin +whole_img_file = ./img_create/wholeimg_mfg_if.bin diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_1M.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_1M.toml new file mode 100644 index 0000000000000000000000000000000000000000..bc50db4d43db17d081e16d95b914c60c4cafe55a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_1M.toml @@ -0,0 +1,94 @@ +[pt_table] +#partition table is 4K in size +address0 = 0xE000 +address1 = 0xF000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x010000 +size0 = 0xE7000 +address1 = 0x000 +size1 = 0x000 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 2 +name = "mfg" +device = 0 +address0 = 0x000 +size0 = 0x000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0x0F7000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 4 +name = "PSM" +device = 0 +address0 = 0x0F9000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 5 +name = "KEY" +device = 0 +address0 = 0x0000 +size0 = 0x000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 6 +name = "DATA" +device = 0 +address0 = 0x0000 +size0 = 0x000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + + +[[pt_entry]] +type = 7 +name = "factory" +device = 0 +address0 = 0x0FB000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +#if user want to put RF calibration data on flash, uncomment following pt entry +#[[pt_entry]] +#type = 8 +#name = "rf_para" +#device = 0 +#address0 = 0x1FF000 +#size0 = 0x1000 +#address1 = 0 +#size1 = 0 +## compressed image must set len,normal image can left it to 0 +#len = 0 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_1M_ota.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_1M_ota.toml new file mode 100644 index 0000000000000000000000000000000000000000..fddfcbb10f4536be8311140b9d895c66b50ffd9b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_1M_ota.toml @@ -0,0 +1,94 @@ +[pt_table] +#partition table is 4K in size +address0 = 0xE000 +address1 = 0xF000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x010000 +size0 = 0x96000 +address1 = 0xA6000 +size1 = 0x50000 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 2 +name = "mfg" +device = 0 +address0 = 0x000 +size0 = 0x000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0x0F6000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 4 +name = "PSM" +device = 0 +address0 = 0x0F8000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 5 +name = "KEY" +device = 0 +address0 = 0x0000 +size0 = 0x000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 6 +name = "DATA" +device = 0 +address0 = 0x0000 +size0 = 0x000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + + +[[pt_entry]] +type = 7 +name = "factory" +device = 0 +address0 = 0x0FC000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +#if user want to put RF calibration data on flash, uncomment following pt entry +#[[pt_entry]] +#type = 8 +#name = "rf_para" +#device = 0 +#address0 = 0x1FF000 +#size0 = 0x1000 +#address1 = 0 +#size1 = 0 +## compressed image must set len,normal image can left it to 0 +#len = 0 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_2M.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_2M.toml new file mode 100644 index 0000000000000000000000000000000000000000..29de67e07ff1f6028a23f99e6dc713ace847883c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl602/partition/partition_cfg_2M.toml @@ -0,0 +1,94 @@ +[pt_table] +#partition table is 4K in size +address0 = 0xE000 +address1 = 0xF000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x10000 +size0 = 0xC8000 +address1 = 0xD8000 +size1 = 0x88000 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 2 +name = "mfg" +device = 0 +address0 = 0x160000 +size0 = 0x32000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0x192000 +size0 = 0x57000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 4 +name = "PSM" +device = 0 +address0 = 0x1E9000 +size0 = 0x8000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 5 +name = "KEY" +device = 0 +address0 = 0x1F1000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +[[pt_entry]] +type = 6 +name = "DATA" +device = 0 +address0 = 0x1F3000 +size0 = 0x5000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + + +[[pt_entry]] +type = 7 +name = "factory" +device = 0 +address0 = 0x1F8000 +size0 = 0x7000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 + +#if user want to put RF calibration data on flash, uncomment following pt entry +#[[pt_entry]] +#type = 8 +#name = "rf_para" +#device = 0 +#address0 = 0x1FF000 +#size0 = 0x1000 +#address1 = 0 +#size1 = 0 +## compressed image must set len,normal image can left it to 0 +#len = 0 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/conf/ota.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/conf/ota.toml new file mode 100644 index 0000000000000000000000000000000000000000..5e298fdf1625932dbb2cde4d973b79b17a8e2435 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/conf/ota.toml @@ -0,0 +1,5 @@ +[ota] +#max length of version_hardware is 15 bytes +version_hardware = "BFL_Module_v1.1" +#max length of version_software is 15 bytes +version_software = "EVENT_V1.1.1" diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_32M.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_32M.dts new file mode 100644 index 0000000000000000000000000000000000000000..502024f63ca1d6d708c9b8946d3718fcc307ebf7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_32M.dts @@ -0,0 +1,86 @@ +/dts-v1/; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl702 AVB board"; + compatible = "bl,bl702-sample", "bl,bl702-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <22>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "onoff"; //blink or hearbeat or onoff + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat or onoff + time = <100>; //duration for this mode + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl702_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <15>; + tx = <14>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "disable"; + id = <1>; + compatible = "bl702_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + wireless { + #address-cells = <1>; + #size-cells = <1>; + mac { + mode = "MBF"; // 'M': manufacture; 'B': efuse; 'F': flash + mac_addr = [C8 43 57 82 73 40 88 88]; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + pwr = <14>; + }; + rf_temp { + en_tcal = <0>; + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_None.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_None.dts new file mode 100644 index 0000000000000000000000000000000000000000..502024f63ca1d6d708c9b8946d3718fcc307ebf7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_None.dts @@ -0,0 +1,86 @@ +/dts-v1/; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl702 AVB board"; + compatible = "bl,bl702-sample", "bl,bl702-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <22>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "onoff"; //blink or hearbeat or onoff + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat or onoff + time = <100>; //duration for this mode + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl702_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <15>; + tx = <14>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "disable"; + id = <1>; + compatible = "bl702_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + wireless { + #address-cells = <1>; + #size-cells = <1>; + mac { + mode = "MBF"; // 'M': manufacture; 'B': efuse; 'F': flash + mac_addr = [C8 43 57 82 73 40 88 88]; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + pwr = <14>; + }; + rf_temp { + en_tcal = <0>; + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_RC32M.dts b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_RC32M.dts new file mode 100644 index 0000000000000000000000000000000000000000..502024f63ca1d6d708c9b8946d3718fcc307ebf7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/device_tree/bl_factory_params_IoTKitA_RC32M.dts @@ -0,0 +1,86 @@ +/dts-v1/; +// version: 17 +// last_comp_version: 16 +// boot_cpuid_phys: 0x0 + +/ { + model = "bl bl702 AVB board"; + compatible = "bl,bl702-sample", "bl,bl702-common"; + #address-cells = <0x1>; + #size-cells = <0x1>; + gpio { + #address-cells = <1>; + #size-cells = <1>; + max_num = <40>; + gpio0 { + status = "okay"; + pin = <22>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "onoff"; //blink or hearbeat or onoff + time = <100>; //duration for this mode + }; + gpio1 { + status = "disable"; + pin = <6>; + feature = "led"; + active = "Hi"; //Hi or Lo + mode = "blink"; //blink or hearbeat or onoff + time = <100>; //duration for this mode + }; + }; + uart { + #address-cells = <1>; + #size-cells = <1>; + uart@4000A000 { + status = "okay"; + id = <0>; + compatible = "bl702_uart"; + path = "/dev/ttyS0"; + baudrate = <2000000>; + pin { + rx = <15>; + tx = <14>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + uart@4000A100 { + status = "disable"; + id = <1>; + compatible = "bl702_uart"; + path = "/dev/ttyS1"; + baudrate = <115200>; + pin { + rx = <3>; + tx = <4>; + }; + feature { + tx = "okay"; + rx = "okay"; + cts = "disable"; + rts = "disable"; + }; + }; + }; + wireless { + #address-cells = <1>; + #size-cells = <1>; + mac { + mode = "MBF"; // 'M': manufacture; 'B': efuse; 'F': flash + mac_addr = [C8 43 57 82 73 40 88 88]; + }; + brd_rf { + xtal_mode = "MF"; + xtal = <36 36 0 60 60>; + pwr = <14>; + }; + rf_temp { + en_tcal = <0>; + }; + }; +}; diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/eflash_loader/eflash_loader_cfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/eflash_loader/eflash_loader_cfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..5bd453ad969ec8cc719767e448dfcf34358cce7a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/eflash_loader/eflash_loader_cfg.conf @@ -0,0 +1,58 @@ +[LOAD_CFG] +#jlink or uart +interface = uart +device = COM1 +speed_uart_boot = 500000 +speed_uart_load = 500000 +#eg: rv_dbg_plus, ft2232hl, ft2232d +openocd_config = rv_dbg_plus +auto_burn = false +speed_jlink = 2000 +#0:without load, 1:eflash_loader load +load_function = 1 +do_reset = true +#reset retry+hold time +reset_hold_time = 50 +shake_hand_delay = 100 +reset_revert = false +cutoff_time = 50 +shake_hand_retry = 3 +flash_burn_retry = 1 +checksum_err_retry = 3 +iap_shakehand_timeout = 0 +#1: 32M, 2: RC32M +#xtal_type = 2 +erase_time_out = 15000 +#chiptype=702 +eflash_loader_file=chips/bl702/eflash_loader/eflash_loader_32m.bin +check_mac = false +#0:no erase,1:programmed section erase,2:chip erase +erase = 1 +# switch eflash_loader command log save +local_log = false +#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus) +verify = 0 +tx_size = 2056 +cpu_reset_after_load = false + +[FLASH_CFG] +flash_id = c84015 +flash_clock_cfg = 1 +#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO +flash_io_mode = 1 +#flash_pin value: +#bit 0-1 = flash_cfg: 0: external gpio 23-28, 1: internal 512K, 2: internal 1M, 3: external gpio 17-22 +#bit 2-3 = swap_cfg: 0: do not swap, 1: swap cs&io2, 2: swap io0&io3, 3: swap cs&io2 io0&io3 both +flash_pin = "" +#empty for auto, otherwise specified para file path: eg: chips/bl702/efuse_bootheader/flash_para.bin +flash_para = chips/bl702/efuse_bootheader/flash_para.bin +decompress_write = false +file = chips/bl702/img_create/bootinfo_boot2.bin chips/bl702/img_create/img_boot2.bin chips/bl702/partition/partition.bin chips/bl702/partition/partition.bin +address = 00000000 00002000 e000 f000 + +[EFUSE_CFG] +burn_en = true +factory_mode = false +security_write = false +file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin +maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/efuse_bootheader/efuse_bootheader_cfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/efuse_bootheader/efuse_bootheader_cfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..fc91e7b55baf3d4a1b8ed55d11129db8dacb6091 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/efuse_bootheader/efuse_bootheader_cfg.conf @@ -0,0 +1,196 @@ +[EFUSE_CFG] +######################################################################## +#2bits +ef_sf_aes_mode = 0 +#2bits +ef_sboot_sign_mode = 0 +#2bits +ef_sboot_en = 0 +#2bits +ef_dbg_jtag_dis = 0 +#4bits +ef_dbg_mode = 0 +#32bits +ef_dbg_pwd_low = 0 +#32bits +ef_dbg_pwd_high = 0 +################################################################### +ef_key_slot_2_w0 = 0 +ef_key_slot_2_w1 = 0 +ef_key_slot_2_w2 = 0 +ef_key_slot_2_w3 = 0 +ef_key_slot_3_w0 = 0 +ef_key_slot_3_w1 = 0 +ef_key_slot_3_w2 = 0 +ef_key_slot_3_w3 = 0 +ef_key_slot_4_w0 = 0 +ef_key_slot_4_w1 = 0 +ef_key_slot_4_w2 = 0 +ef_key_slot_4_w3 = 0 + +wr_lock_key_slot_4_l = 0 +wr_lock_dbg_pwd = 0 +wr_lock_key_slot_2 = 0 +wr_lock_key_slot_3 = 0 +wr_lock_key_slot_4_h = 0 +rd_lock_dbg_pwd = 0 +rd_lock_key_slot_2 = 0 +rd_lock_key_slot_3 = 0 +rd_lock_key_slot_4 = 0 + +[BOOTHEADER_CFG] +magic_code = 0x504e4642 +revision = 0x01 +#########################flash cfg############################# +flashcfg_magic_code = 0x47464346 +#flashcfg_magic_code=0 +io_mode = 0x11 +cont_read_support = 0 +sfctrl_clk_delay = 1 +sfctrl_clk_invert = 0x01 + +reset_en_cmd = 0x66 +reset_cmd = 0x99 +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 + +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 + +sector_size = 4 +mfg_id = 0xc8 +page_size = 256 + +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 + +write_enable_cmd = 0x06 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 + +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 + +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 + +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 + +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 + +wel_reg_index = 0 +qe_reg_index = 1 +busy_reg_index = 0 +wel_bit_pos = 1 + +qe_bit_pos = 1 +busy_bit_pos = 0 +wel_reg_write_len = 2 +wel_reg_read_len = 1 + +qe_reg_write_len = 2 +qe_reg_read_len = 1 +release_power_down = 0xab +busy_reg_read_len = 1 + +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 + +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 + +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +cont_read_code = 0xa0 +cont_read_exit_code = 0xff + +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 + +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 + +sector_erase_time = 300 +blk32k_erase_time = 1200 + +blk64k_erase_time = 1200 +page_prog_time = 5 + +chip_erase_time = 200000 +power_down_delay = 20 +qe_data = 0 + +flashcfg_crc32 = 0 + +#########################clk cfg#################################### +clkcfg_magic_code = 0x47464350 +#clkcfg_magic_code=0 + +#0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M +xtal_type = 1 +#0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M +pll_clk = 1 +hclk_div = 0 +bclk_div = 0 +#0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M +flash_clk_type = 1 +flash_clk_div = 0 +clkcfg_crc32 = 0 + +########################boot cfg#################################### +#1:ECC +sign = 0 +#1:AES128,2:AES256,3:AES192 +encrypt_type = 0 +key_sel = 1 +no_segment = 1 +cache_enable = 1 +notload_in_bootrom = 0 +aes_region_lock = 0 +cache_way_disable = 0x00 +crc_ignore = 0 +hash_ignore = 0 +boot2_enable=1 +boot2_rollback=0 + +########################image cfg#################################### +#total image len or segment count +img_len = 0x100 +bootentry = 0 +#img RAM address or flash offset +img_start = 0x2000 + +#img hash +hash_0 = 0xdeadbeef +hash_1 = 0 +hash_2 = 0 +hash_3 = 0 +hash_4 = 0 +hash_5 = 0 +hash_6 = 0 +hash_7 = 0 + +#address of partition tables for boot2 in bootrom +boot2_pt_table_0=0x1000 +boot2_pt_table_1=0x2000 + +crc32 = 0xdeadbeef diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..03388306c30cf39742081c478ebc0cf7a7c85f4f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg.conf @@ -0,0 +1,15 @@ +[Img_Cfg] +boot_header_file = +efuse_file = +efuse_mask_file = +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = img_create/aesiv_cpu0.bin +publickey_file = img_create/publickey_uecc.pem +privatekey_file_uecc = img_create/privatekey_uecc.pem +segheader_file = img_create/segheader.bin +segdata_file = +bootinfo_file = +img_file = +whole_img_file = +aes_key_org = 00000000000000000000000000000000 +aes_iv = 00000000000000000000000000000000 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg_boot2.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg_boot2.conf new file mode 100644 index 0000000000000000000000000000000000000000..483386fc6bd944f01b834283229deeb4868cb011 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg_boot2.conf @@ -0,0 +1,15 @@ +[Img_Cfg] +boot_header_file = +efuse_file = +efuse_mask_file = +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = img_create/aesiv.bin +publickey_file = img_create/publickey_uecc.pem +privatekey_file_uecc = img_create/privatekey_uecc.pem +segheader_file = img_create/segheader.bin +segdata_file = +bootinfo_file = +img_file = +whole_img_file = +aes_key_org = 11 +aes_iv = 11 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg_mfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg_mfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..20e9f51751bcb6ab5b1512f294d873d08f708452 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_iot/img_create_cfg_mfg.conf @@ -0,0 +1,13 @@ +[Img_Cfg] +boot_header_file = ./efuse_bootheader/bootheader.bin +efuse_file = ./efuse_bootheader/efusedata.bin +efuse_mask_file = ./efuse_bootheader/efusedata_mask.bin +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = ./img_create/aesiv.bin +publickey_file = ./img_create/publickey_uecc.pem +privatekey_file_uecc = ./img_create/privatekey_uecc.pem +segheader_file = ./img_create/segheader.bin +segdata_file = +bootinfo_file = ./img_create/bootinfo_mfg.bin +img_file = ./img_create/img_mfg.bin +whole_img_file = ./img_create/wholeimg_mfg_if.bin diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..03388306c30cf39742081c478ebc0cf7a7c85f4f --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg.conf @@ -0,0 +1,15 @@ +[Img_Cfg] +boot_header_file = +efuse_file = +efuse_mask_file = +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = img_create/aesiv_cpu0.bin +publickey_file = img_create/publickey_uecc.pem +privatekey_file_uecc = img_create/privatekey_uecc.pem +segheader_file = img_create/segheader.bin +segdata_file = +bootinfo_file = +img_file = +whole_img_file = +aes_key_org = 00000000000000000000000000000000 +aes_iv = 00000000000000000000000000000000 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg_boot2.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg_boot2.conf new file mode 100644 index 0000000000000000000000000000000000000000..483386fc6bd944f01b834283229deeb4868cb011 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg_boot2.conf @@ -0,0 +1,15 @@ +[Img_Cfg] +boot_header_file = +efuse_file = +efuse_mask_file = +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = img_create/aesiv.bin +publickey_file = img_create/publickey_uecc.pem +privatekey_file_uecc = img_create/privatekey_uecc.pem +segheader_file = img_create/segheader.bin +segdata_file = +bootinfo_file = +img_file = +whole_img_file = +aes_key_org = 11 +aes_iv = 11 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg_mfg.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg_mfg.conf new file mode 100644 index 0000000000000000000000000000000000000000..20e9f51751bcb6ab5b1512f294d873d08f708452 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/img_create_mcu/img_create_cfg_mfg.conf @@ -0,0 +1,13 @@ +[Img_Cfg] +boot_header_file = ./efuse_bootheader/bootheader.bin +efuse_file = ./efuse_bootheader/efusedata.bin +efuse_mask_file = ./efuse_bootheader/efusedata_mask.bin +encrypt_key_org = 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F +aesiv_file = ./img_create/aesiv.bin +publickey_file = ./img_create/publickey_uecc.pem +privatekey_file_uecc = ./img_create/privatekey_uecc.pem +segheader_file = ./img_create/segheader.bin +segdata_file = +bootinfo_file = ./img_create/bootinfo_mfg.bin +img_file = ./img_create/img_mfg.bin +whole_img_file = ./img_create/wholeimg_mfg_if.bin diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_1M.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_1M.toml new file mode 100644 index 0000000000000000000000000000000000000000..b7e364c904cf4e5805efb3472fe498f0dea9ffcf --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_1M.toml @@ -0,0 +1,70 @@ +[pt_table] +#partition table is 4K in size +address0 = 0x1000 +address1 = 0x2000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x3000 +size0 = 0x90000 +address1 = 0x93000 +size1 = 0x66000 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 1 +name = "mfg" +device = 0 +address0 = 0x93000 +size0 = 0x66000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 2 +name = "PSM" +device = 0 +address0 = 0xF9000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0xFB000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 4 +name = "factory" +device = 0 +address0 = 0xFF000 +size0 = 0x1000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_1M_FW1.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_1M_FW1.toml new file mode 100644 index 0000000000000000000000000000000000000000..aa36f08fab122240bb4dc83ef2c9efb8d598027b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_1M_FW1.toml @@ -0,0 +1,70 @@ +[pt_table] +#partition table is 4K in size +address0 = 0x1000 +address1 = 0x2000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x3000 +size0 = 0x90000 +address1 = 0x93000 +size1 = 0x66000 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 1 +age = 0 + +[[pt_entry]] +type = 1 +name = "mfg" +device = 0 +address0 = 0x93000 +size0 = 0x66000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 2 +name = "PSM" +device = 0 +address0 = 0xF9000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0xFB000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 4 +name = "factory" +device = 0 +address0 = 0xFF000 +size0 = 0x1000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_2M.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_2M.toml new file mode 100644 index 0000000000000000000000000000000000000000..4187ef946035d0a6e0e5d81a59b0602c8813d3fa --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_2M.toml @@ -0,0 +1,70 @@ +[pt_table] +#partition table is 4K in size +address0 = 0x1000 +address1 = 0x2000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x3000 +size0 = 0x127000 +address1 = 0x12A000 +size1 = 0xCF000 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 1 +name = "mfg" +device = 0 +address0 = 0x12A000 +size0 = 0xCF000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 2 +name = "PSM" +device = 0 +address0 = 0x1F9000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0x1FB000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 4 +name = "factory" +device = 0 +address0 = 0x1FF000 +size0 = 0x1000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_2M_FW1.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_2M_FW1.toml new file mode 100644 index 0000000000000000000000000000000000000000..0882a6420599c66db2dd769ddfc4017cc33fb4be --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_2M_FW1.toml @@ -0,0 +1,70 @@ +[pt_table] +#partition table is 4K in size +address0 = 0x1000 +address1 = 0x2000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x3000 +size0 = 0x127000 +address1 = 0x12A000 +size1 = 0xCF000 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 1 +age = 0 + +[[pt_entry]] +type = 1 +name = "mfg" +device = 0 +address0 = 0x12A000 +size0 = 0xCF000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 2 +name = "PSM" +device = 0 +address0 = 0x1F9000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0x1FB000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 4 +name = "factory" +device = 0 +address0 = 0x1FF000 +size0 = 0x1000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_512K.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_512K.toml new file mode 100644 index 0000000000000000000000000000000000000000..0dea54f35d5db5db6b074eb3ccc63d0b05e1fa71 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_512K.toml @@ -0,0 +1,70 @@ +[pt_table] +#partition table is 4K in size +address0 = 0x1000 +address1 = 0x2000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x3000 +size0 = 0x45000 +address1 = 0x48000 +size1 = 0x31000 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 1 +name = "mfg" +device = 0 +address0 = 0x48000 +size0 = 0x31000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 2 +name = "PSM" +device = 0 +address0 = 0x79000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0x7B000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 4 +name = "factory" +device = 0 +address0 = 0x7F000 +size0 = 0x1000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_512K_FW1.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_512K_FW1.toml new file mode 100644 index 0000000000000000000000000000000000000000..a069c28fbd6d24cc8713d8545366e6af455c6790 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_512K_FW1.toml @@ -0,0 +1,70 @@ +[pt_table] +#partition table is 4K in size +address0 = 0x1000 +address1 = 0x2000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x3000 +size0 = 0x45000 +address1 = 0x48000 +size1 = 0x31000 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 1 +age = 0 + +[[pt_entry]] +type = 1 +name = "mfg" +device = 0 +address0 = 0x48000 +size0 = 0x31000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 2 +name = "PSM" +device = 0 +address0 = 0x79000 +size0 = 0x2000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 3 +name = "media" +device = 0 +address0 = 0x7B000 +size0 = 0x4000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + +[[pt_entry]] +type = 4 +name = "factory" +device = 0 +address0 = 0x7F000 +size0 = 0x1000 +address1 = 0 +size1 = 0 +# compressed image must set len,normal image can left it to 0 +len = 0 +activeindex = 0 +age = 0 + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_mcu.toml b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_mcu.toml new file mode 100644 index 0000000000000000000000000000000000000000..a4665c9500f5a812bdf6a9fea1192a529232eb2c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/chips/bl702/partition/partition_cfg_mcu.toml @@ -0,0 +1,15 @@ +[pt_table] +#partition table is 4K in size +address0 = 0xE000 +address1 = 0xF000 + +[[pt_entry]] +type = 0 +name = "FW" +device = 0 +address0 = 0x010000 +size0 = 0x30000 +address1 = 0x40000 +size1 = 0x30000 +# compressed image must set len,normal image can left it to 0 +len = 0 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/clear.bat b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/clear.bat new file mode 100644 index 0000000000000000000000000000000000000000..43a09c615c9b6d1692ccbf095cd44ca991c5dbed --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/clear.bat @@ -0,0 +1,38 @@ +del /a /f /s /q "*.log" +del /a /f /s /q "*.ini" +del /a /f /s /q "iot.toml" +del /a /f /s /q "mcu.toml" +del /a /f /s /q "storage.toml" +del /a /f /s /q "partition.bin" +del /a /f /s /q "ro_params.dtb" +del /a /f /s /q "flash_para.bin" +del /a /f /s /q .\chips\bl602\img_create_iot\*.bin +del /a /f /s /q .\chips\bl702\img_create_iot\*.bin +del /a /f /s /q .\chips\bl56x\img_create_iot\*.bin +del /a /f /s /q .\chips\bl60x\img_create_iot\*.bin +del /a /f /s /q .\chips\bl606p\img_create_iot\*.bin +del /a /f /s /q .\chips\bl602u\img_create_iot\*.bin +del /a /f /s /q .\chips\bl808\img_create_iot\*.bin +del /a /f /s /q .\chips\bl602\img_create_mcu\*.bin +del /a /f /s /q .\chips\bl702\img_create_mcu\*.bin +del /a /f /s /q .\chips\bl56x\img_create_mcu\*.bin +del /a /f /s /q .\chips\bl60x\img_create_mcu\*.bin +del /a /f /s /q .\chips\bl606p\img_create_mcu\*.bin +del /a /f /s /q .\chips\bl602u\img_create_mcu\*.bin +del /a /f /s /q .\chips\bl808\img_create_mcu\*.bin +del /a /f /s /q .\chips\bl602\efuse_bootheader\*.bin +del /a /f /s /q .\chips\bl702\efuse_bootheader\*.bin +del /a /f /s /q .\chips\bl56x\efuse_bootheader\*.bin +del /a /f /s /q .\chips\bl60x\efuse_bootheader\*.bin +del /a /f /s /q .\chips\bl606p\efuse_bootheader\*.bin +del /a /f /s /q .\chips\bl602u\efuse_bootheader\*.bin +del /a /f /s /q .\chips\bl808\efuse_bootheader\*.bin +del /a /f /s /q .\chips\*.pack +rd /s /Q .\chips\bl602\ota +rd /s /Q .\chips\bl702\ota +rd /s /Q .\chips\bl56x\ota +rd /s /Q .\chips\bl60x\ota +rd /s /Q .\chips\bl606p\ota +rd /s /Q .\chips\bl602u\ota +rd /s /Q .\chips\bl808\ota +pause \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25128BS_684018.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25128BS_684018.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e71c5feab4a4e428f9d27577ed1c7fe403f3c0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25128BS_684018.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x68 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q16BS_684015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q16BS_684015.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e71c5feab4a4e428f9d27577ed1c7fe403f3c0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q16BS_684015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x68 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q32BS_684016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q32BS_684016.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e71c5feab4a4e428f9d27577ed1c7fe403f3c0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q32BS_684016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x68 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q64BS_684017.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q64BS_684017.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e71c5feab4a4e428f9d27577ed1c7fe403f3c0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/BY25Q64BS_684017.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x68 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/FM25Q08_a14014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/FM25Q08_a14014.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f9eb8cecb61233459227f8947d532f16dd49169 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/FM25Q08_a14014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 800 +blk32k_erase_time = 3000 +blk64k_erase_time = 4000 +page_prog_time = 10 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/FTVQ80_5e6014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/FTVQ80_5e6014.conf new file mode 100644 index 0000000000000000000000000000000000000000..3fec9fa91accdcc69e51999367c92714acc475a7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/FTVQ80_5e6014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LE16C_c86015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LE16C_c86015.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LE16C_c86015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LQ32D_c86016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LQ32D_c86016.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LQ32D_c86016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LQ80C_c86014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LQ80C_c86014.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25LQ80C_c86014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q16E_c84015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q16E_c84015.conf new file mode 100644 index 0000000000000000000000000000000000000000..8141fcfa8f0e8d1413a0e37fdcbe2c8d12948fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q16E_c84015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q32C_c84016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q32C_c84016.conf new file mode 100644 index 0000000000000000000000000000000000000000..ce6e80245b436dbfa5a4af4db68840be8eda4b54 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q32C_c84016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q64E_c84017.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q64E_c84017.conf new file mode 100644 index 0000000000000000000000000000000000000000..ce6e80245b436dbfa5a4af4db68840be8eda4b54 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q64E_c84017.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q80E_c84014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q80E_c84014.conf new file mode 100644 index 0000000000000000000000000000000000000000..8141fcfa8f0e8d1413a0e37fdcbe2c8d12948fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25Q80E_c84014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ16E_c86515.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ16E_c86515.conf new file mode 100644 index 0000000000000000000000000000000000000000..6121a716464fb559a704072fd9f7cca74ad2cdf0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ16E_c86515.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 4 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 1 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 4 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0x12 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ32E_c86516.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ32E_c86516.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ32E_c86516.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ80E_c86514.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ80E_c86514.conf new file mode 100644 index 0000000000000000000000000000000000000000..6121a716464fb559a704072fd9f7cca74ad2cdf0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/GD25WQ80E_c86514.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 4 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 1 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 4 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0x12 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP016D_9d6015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP016D_9d6015.conf new file mode 100644 index 0000000000000000000000000000000000000000..812b7d70fe0d6a10709cbfcf5f7a04551f9c2bad --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP016D_9d6015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x9d +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x00 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x06 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 5 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP032D_9d6016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP032D_9d6016.conf new file mode 100644 index 0000000000000000000000000000000000000000..812b7d70fe0d6a10709cbfcf5f7a04551f9c2bad --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP032D_9d6016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x9d +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x00 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x06 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 5 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP080D_9d6014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP080D_9d6014.conf new file mode 100644 index 0000000000000000000000000000000000000000..812b7d70fe0d6a10709cbfcf5f7a04551f9c2bad --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/IS25LP080D_9d6014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x9d +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x00 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x06 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 5 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V16_c22015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V16_c22015.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e5d87e8e399ee3ced6220f09ef88f9c3144403e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V16_c22015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x00 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x00 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0x00 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V40_c22013.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V40_c22013.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e5d87e8e399ee3ced6220f09ef88f9c3144403e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V40_c22013.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x00 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x00 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0x00 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V80_c22014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V80_c22014.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e5d87e8e399ee3ced6220f09ef88f9c3144403e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/KH25V80_c22014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x00 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x00 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0x00 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MD25D40_514013.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MD25D40_514013.conf new file mode 100644 index 0000000000000000000000000000000000000000..8512eb5d1e16a7c39e9abd5b86f599ce9ab168e3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MD25D40_514013.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x51 +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V1633FM_c22535.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V1633FM_c22535.conf new file mode 100644 index 0000000000000000000000000000000000000000..696e96a7b20dac727d181f1135333f0fa7e48bb1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V1633FM_c22535.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x10 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa5 +burst_wrap_cmd = 0xc0 +burst_wrap_dmy_clk = 0x00 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x02 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 45 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V3233FM_c22536.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V3233FM_c22536.conf new file mode 100644 index 0000000000000000000000000000000000000000..696e96a7b20dac727d181f1135333f0fa7e48bb1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V3233FM_c22536.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x10 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa5 +burst_wrap_cmd = 0xc0 +burst_wrap_dmy_clk = 0x00 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x02 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 45 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V8035F_c22534.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V8035F_c22534.conf new file mode 100644 index 0000000000000000000000000000000000000000..696e96a7b20dac727d181f1135333f0fa7e48bb1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/MX25V8035F_c22534.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x10 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa5 +burst_wrap_cmd = 0xc0 +burst_wrap_dmy_clk = 0x00 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x02 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 45 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q16H_856015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q16H_856015.conf new file mode 100644 index 0000000000000000000000000000000000000000..a3334e05cd96848a8137507a58174443ea69a45a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q16H_856015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x85 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q32H_856016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q32H_856016.conf new file mode 100644 index 0000000000000000000000000000000000000000..5c330509aff5f3c2d9571579fca74400af57774d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q32H_856016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x85 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q64H_856017.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q64H_856017.conf new file mode 100644 index 0000000000000000000000000000000000000000..5c330509aff5f3c2d9571579fca74400af57774d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q64H_856017.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x85 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q80H_856014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q80H_856014.conf new file mode 100644 index 0000000000000000000000000000000000000000..a3334e05cd96848a8137507a58174443ea69a45a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/P25Q80H_856014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x85 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/TH25Q16HB_eb6015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/TH25Q16HB_eb6015.conf new file mode 100644 index 0000000000000000000000000000000000000000..503da191c4c02619d558d8ae982745f028c4887e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/TH25Q16HB_eb6015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xeb +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 800 +blk32k_erase_time = 3000 +blk64k_erase_time = 4000 +page_prog_time = 10 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q128FW_ef6018.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q128FW_ef6018.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q128FW_ef6018.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16FW_ef6015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16FW_ef6015.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16FW_ef6015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16JV_ef4015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16JV_ef4015.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16JV_ef4015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16JV_ef7015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16JV_ef7015.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q16JV_ef7015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32FV_ef4016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32FV_ef4016.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32FV_ef4016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32FW_ef6016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32FW_ef6016.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32FW_ef6016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32JW_ef8016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32JW_ef8016.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q32JW_ef8016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q80DV_ef4014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q80DV_ef4014.conf new file mode 100644 index 0000000000000000000000000000000000000000..9112a7af0929b397c34dc641b92dafbda47ca6aa --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q80DV_ef4014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xA0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q80EW_ef6014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q80EW_ef6014.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/W25Q80EW_ef6014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XM25QH16_204015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XM25QH16_204015.conf new file mode 100644 index 0000000000000000000000000000000000000000..cab51a4cc77d682090d596af2a840b4d07162242 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XM25QH16_204015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x20 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XM25QH64_204017.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XM25QH64_204017.conf new file mode 100644 index 0000000000000000000000000000000000000000..cab51a4cc77d682090d596af2a840b4d07162242 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XM25QH64_204017.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x20 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F16B_0b4015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F16B_0b4015.conf new file mode 100644 index 0000000000000000000000000000000000000000..37142692c152df358fa466b3f893150137d2b2d0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F16B_0b4015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F32B_0b4016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F32B_0b4016.conf new file mode 100644 index 0000000000000000000000000000000000000000..37142692c152df358fa466b3f893150137d2b2d0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F32B_0b4016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F64B_0b4017.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F64B_0b4017.conf new file mode 100644 index 0000000000000000000000000000000000000000..37142692c152df358fa466b3f893150137d2b2d0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25F64B_0b4017.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25Q32B_0b6016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25Q32B_0b6016.conf new file mode 100644 index 0000000000000000000000000000000000000000..86d3af2bb48b5407e248bf696931af9356d121ec --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25Q32B_0b6016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 6000 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25Q80B_0b6014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25Q80B_0b6014.conf new file mode 100644 index 0000000000000000000000000000000000000000..37142692c152df358fa466b3f893150137d2b2d0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/XT25Q80B_0b6014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25D40B_5e3213.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25D40B_5e3213.conf new file mode 100644 index 0000000000000000000000000000000000000000..4bf6fc9c02e1872fadfff589a4dc200f6197ab70 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25D40B_5e3213.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x5e +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 33000 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25D80B_5e3214.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25D80B_5e3214.conf new file mode 100644 index 0000000000000000000000000000000000000000..4bf6fc9c02e1872fadfff589a4dc200f6197ab70 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25D80B_5e3214.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x5e +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 33000 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25Q16B_5e4015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25Q16B_5e4015.conf new file mode 100644 index 0000000000000000000000000000000000000000..8f3e289a63594ff30859bd3f87816d5795218e1c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25Q16B_5e4015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x5e +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 33000 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25Q32B_5e4016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25Q32B_5e4016.conf new file mode 100644 index 0000000000000000000000000000000000000000..8f3e289a63594ff30859bd3f87816d5795218e1c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZB25Q32B_5e4016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x5e +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 33000 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBVQ16_5e6015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBVQ16_5e6015.conf new file mode 100644 index 0000000000000000000000000000000000000000..7423f4262b7053731086faac58eb4e781af0de24 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBVQ16_5e6015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x5e +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 400 +blk32k_erase_time = 1600 +blk64k_erase_time = 2000 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBVQ64_5e4017.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBVQ64_5e4017.conf new file mode 100644 index 0000000000000000000000000000000000000000..f1d79ceef0649f88111f57a6083d247de391cb5d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBVQ64_5e4017.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x5e +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBWQ16A_5e3415.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBWQ16A_5e3415.conf new file mode 100644 index 0000000000000000000000000000000000000000..8f3e289a63594ff30859bd3f87816d5795218e1c --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZBWQ16A_5e3415.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x5e +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 33000 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZD25Q16B_ba6015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZD25Q16B_ba6015.conf new file mode 100644 index 0000000000000000000000000000000000000000..b561cfe0d3dd037bff4a9f2f34da31bed342d085 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl602/ZD25Q16B_ba6015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xba +io_mode = 0x14 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25128BS_684018.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25128BS_684018.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e71c5feab4a4e428f9d27577ed1c7fe403f3c0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25128BS_684018.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x68 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q16BS_684015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q16BS_684015.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e71c5feab4a4e428f9d27577ed1c7fe403f3c0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q16BS_684015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x68 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q32BS_684016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q32BS_684016.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e71c5feab4a4e428f9d27577ed1c7fe403f3c0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q32BS_684016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x68 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q64BS_684017.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q64BS_684017.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e71c5feab4a4e428f9d27577ed1c7fe403f3c0b --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/BY25Q64BS_684017.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x68 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/FM25Q08_a14014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/FM25Q08_a14014.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/FM25Q08_a14014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/FTVQ80_5e6014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/FTVQ80_5e6014.conf new file mode 100644 index 0000000000000000000000000000000000000000..3fec9fa91accdcc69e51999367c92714acc475a7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/FTVQ80_5e6014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LE16C_c86015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LE16C_c86015.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LE16C_c86015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LQ32D_c86016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LQ32D_c86016.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LQ32D_c86016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LQ80C_c86014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LQ80C_c86014.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25LQ80C_c86014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q16E_c84015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q16E_c84015.conf new file mode 100644 index 0000000000000000000000000000000000000000..8141fcfa8f0e8d1413a0e37fdcbe2c8d12948fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q16E_c84015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q32C_c84016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q32C_c84016.conf new file mode 100644 index 0000000000000000000000000000000000000000..ce6e80245b436dbfa5a4af4db68840be8eda4b54 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q32C_c84016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q80E_c84014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q80E_c84014.conf new file mode 100644 index 0000000000000000000000000000000000000000..8141fcfa8f0e8d1413a0e37fdcbe2c8d12948fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25Q80E_c84014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ16E_c86515.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ16E_c86515.conf new file mode 100644 index 0000000000000000000000000000000000000000..6121a716464fb559a704072fd9f7cca74ad2cdf0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ16E_c86515.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 4 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 1 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 4 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0x12 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ32E_c86516.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ32E_c86516.conf new file mode 100644 index 0000000000000000000000000000000000000000..7f39f229a2aa27f1647e0b8ff71a236fcc7a452a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ32E_c86516.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ80E_c86514.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ80E_c86514.conf new file mode 100644 index 0000000000000000000000000000000000000000..6121a716464fb559a704072fd9f7cca74ad2cdf0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/GD25WQ80E_c86514.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc8 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 4 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 1 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 4 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0x12 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP016D_9d6015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP016D_9d6015.conf new file mode 100644 index 0000000000000000000000000000000000000000..812b7d70fe0d6a10709cbfcf5f7a04551f9c2bad --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP016D_9d6015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x9d +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x00 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x06 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 5 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP032D_9d6016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP032D_9d6016.conf new file mode 100644 index 0000000000000000000000000000000000000000..812b7d70fe0d6a10709cbfcf5f7a04551f9c2bad --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP032D_9d6016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x9d +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x00 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x06 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 5 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP080D_9d6014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP080D_9d6014.conf new file mode 100644 index 0000000000000000000000000000000000000000..812b7d70fe0d6a10709cbfcf5f7a04551f9c2bad --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/IS25LP080D_9d6014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x9d +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x00 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x06 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 5 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V16_c22015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V16_c22015.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e5d87e8e399ee3ced6220f09ef88f9c3144403e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V16_c22015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x00 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x00 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0x00 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V40_c22013.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V40_c22013.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e5d87e8e399ee3ced6220f09ef88f9c3144403e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V40_c22013.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x00 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x00 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0x00 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V80_c22014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V80_c22014.conf new file mode 100644 index 0000000000000000000000000000000000000000..8e5d87e8e399ee3ced6220f09ef88f9c3144403e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/KH25V80_c22014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x00 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x00 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0x00 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MD25D40_514013.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MD25D40_514013.conf new file mode 100644 index 0000000000000000000000000000000000000000..8512eb5d1e16a7c39e9abd5b86f599ce9ab168e3 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MD25D40_514013.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x51 +io_mode = 0x11 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 0 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V1633FM_c22535.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V1633FM_c22535.conf new file mode 100644 index 0000000000000000000000000000000000000000..696e96a7b20dac727d181f1135333f0fa7e48bb1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V1633FM_c22535.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x10 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa5 +burst_wrap_cmd = 0xc0 +burst_wrap_dmy_clk = 0x00 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x02 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 45 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V3233FM_c22536.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V3233FM_c22536.conf new file mode 100644 index 0000000000000000000000000000000000000000..696e96a7b20dac727d181f1135333f0fa7e48bb1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V3233FM_c22536.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x10 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa5 +burst_wrap_cmd = 0xc0 +burst_wrap_dmy_clk = 0x00 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x02 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 45 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V8035F_c22534.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V8035F_c22534.conf new file mode 100644 index 0000000000000000000000000000000000000000..696e96a7b20dac727d181f1135333f0fa7e48bb1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/MX25V8035F_c22534.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xc2 +io_mode = 4 +de_burst_wrap_cmd = 0xc0 +de_burst_wrap_cmd_dmy_clk = 0x00 +de_burst_wrap_code_mode = 0 +de_burst_wrap_code = 0x10 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 0 +qe_bit_pos = 6 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa5 +burst_wrap_cmd = 0xc0 +burst_wrap_dmy_clk = 0x00 +burst_wrap_data_mode = 0 +burst_wrap_code = 0x02 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 45 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q16H_856015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q16H_856015.conf new file mode 100644 index 0000000000000000000000000000000000000000..a3334e05cd96848a8137507a58174443ea69a45a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q16H_856015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x85 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q32H_856016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q32H_856016.conf new file mode 100644 index 0000000000000000000000000000000000000000..5c330509aff5f3c2d9571579fca74400af57774d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q32H_856016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x85 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q80H_856014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q80H_856014.conf new file mode 100644 index 0000000000000000000000000000000000000000..a3334e05cd96848a8137507a58174443ea69a45a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/P25Q80H_856014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x85 +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q128FW_ef6018.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q128FW_ef6018.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q128FW_ef6018.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16FW_ef6015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16FW_ef6015.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16FW_ef6015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16JV_ef4015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16JV_ef4015.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16JV_ef4015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16JV_ef7015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16JV_ef7015.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q16JV_ef7015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32FV_ef4016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32FV_ef4016.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32FV_ef4016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32FW_ef6016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32FW_ef6016.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32FW_ef6016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32JW_ef8016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32JW_ef8016.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q32JW_ef8016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q80DV_ef4014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q80DV_ef4014.conf new file mode 100644 index 0000000000000000000000000000000000000000..9112a7af0929b397c34dc641b92dafbda47ca6aa --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q80DV_ef4014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xA0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q80EW_ef6014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q80EW_ef6014.conf new file mode 100644 index 0000000000000000000000000000000000000000..0f45c05144da30e17b4aa03c2ecd428ed2bf9fa7 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/W25Q80EW_ef6014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0xef +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 3 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25F16B_0b4015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25F16B_0b4015.conf new file mode 100644 index 0000000000000000000000000000000000000000..37142692c152df358fa466b3f893150137d2b2d0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25F16B_0b4015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25F32B_0b4016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25F32B_0b4016.conf new file mode 100644 index 0000000000000000000000000000000000000000..37142692c152df358fa466b3f893150137d2b2d0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25F32B_0b4016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25Q32B_0b6016.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25Q32B_0b6016.conf new file mode 100644 index 0000000000000000000000000000000000000000..86d3af2bb48b5407e248bf696931af9356d121ec --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25Q32B_0b6016.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 6000 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25Q80B_0b6014.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25Q80B_0b6014.conf new file mode 100644 index 0000000000000000000000000000000000000000..37142692c152df358fa466b3f893150137d2b2d0 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/XT25Q80B_0b6014.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x0b +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 2 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x01 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0xa0 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 20 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/ZBVQ16_5e6015.conf b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/ZBVQ16_5e6015.conf new file mode 100644 index 0000000000000000000000000000000000000000..f1d79ceef0649f88111f57a6083d247de391cb5d --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/flash-conf/bl702/ZBVQ16_5e6015.conf @@ -0,0 +1,73 @@ +[FLASH_CFG] +exit_contread_cmd = 0xff +exit_contread_cmd_size = 3 +mfg_id = 0x5e +io_mode = 4 +de_burst_wrap_cmd = 0x77 +de_burst_wrap_cmd_dmy_clk = 0x03 +de_burst_wrap_code_mode = 2 +de_burst_wrap_code = 0xF0 +write_enable_cmd = 0x06 +wel_reg_index = 0 +wel_bit_pos = 1 +wel_reg_read_len = 1 +wel_reg_write_len = 2 +qe_reg_index = 1 +qe_bit_pos = 1 +qe_reg_write_len = 1 +qe_reg_read_len = 1 +busy_reg_index = 0 +busy_bit_pos = 0 +busy_reg_read_len = 1 +release_power_down = 0xab +reg_read_cmd0 = 0x05 +reg_read_cmd1 = 0x35 +reg_write_cmd0 = 0x01 +reg_write_cmd1 = 0x31 +fast_read_qio_cmd = 0xeb +fast_read_qio_dmy_clk = 2 +cont_read_support = 1 +cont_read_code = 0x20 +burst_wrap_cmd = 0x77 +burst_wrap_dmy_clk = 0x03 +burst_wrap_data_mode = 2 +burst_wrap_code = 0x40 +chip_erase_cmd = 0xc7 +sector_erase_cmd = 0x20 +blk32k_erase_cmd = 0x52 +blk64k_erase_cmd = 0xd8 +page_prog_cmd = 0x02 +qpage_prog_cmd = 0x32 +qual_page_prog_addr_mode = 0 +reset_en_cmd = 0x66 +reset_cmd = 0x99 +cont_read_exit_code = 0xff +jedecid_cmd = 0x9f +jedecid_cmd_dmy_clk = 0 +qpi_jedecid_cmd = 0x9f +qpi_jedecid_dmy_clk = 0 +sector_size = 4 +page_size = 256 +fast_read_cmd = 0x0b +fast_read_dmy_clk = 1 +qpi_fast_read_cmd = 0x0b +qpi_fast_read_dmy_clk = 1 +fast_read_do_cmd = 0x3b +fast_read_do_dmy_clk = 1 +fast_read_dio_cmd = 0xbb +fast_read_dio_dmy_clk = 0 +fast_read_qo_cmd = 0x6b +fast_read_qo_dmy_clk = 1 +qpi_fast_read_qio_cmd = 0xeb +qpi_fast_read_qio_dmy_clk = 2 +qpi_page_prog_cmd = 0x02 +write_vreg_enable_cmd = 0x50 +enter_qpi_cmd = 0x38 +exit_qpi_cmd = 0xff +sector_erase_time = 300 +blk32k_erase_time = 1200 +blk64k_erase_time = 1200 +page_prog_time = 5 +chip_erase_time = 65535 +power_down_delay = 8 +qe_data = 0 \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/cygwin1.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/cygwin1.dll new file mode 100644 index 0000000000000000000000000000000000000000..5aa99284bdb34d6c30ec9900aeb47541c6dd8ebb Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/cygwin1.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/genromfs_amd64 b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/genromfs_amd64 new file mode 100644 index 0000000000000000000000000000000000000000..2f139f10680110e23e152376cbf9a28c9f5a5f74 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/genromfs_amd64 differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/genromfs_armel b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/genromfs_armel new file mode 100644 index 0000000000000000000000000000000000000000..631c0b6983c4ef9293f016e79d8f30788b60d312 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/genromfs/genromfs_armel differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/jlink/JLinkARM.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/jlink/JLinkARM.dll new file mode 100644 index 0000000000000000000000000000000000000000..8700ffcc47f53728cca2c37eabd578ba9bc6ed6f Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/jlink/JLinkARM.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/jlink/JLink_x64.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/jlink/JLink_x64.dll new file mode 100644 index 0000000000000000000000000000000000000000..4df244214487818cbea00842c1dfe6de96dbf6ee Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/jlink/JLink_x64.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/99-openocd.rules b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/99-openocd.rules new file mode 100644 index 0000000000000000000000000000000000000000..f6dc01ee3466a4743a8cc09efa0749a2024199aa --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/99-openocd.rules @@ -0,0 +1,3 @@ +# Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC +SUBSYSTEM=="tty", ATTRS{idVendor}=="0403",ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev" +SUBSYSTEM=="usb", ATTR{idVendor} =="0403",ATTR{idProduct} =="6010", MODE="664", GROUP="plugdev" \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/if_bflb_dbg.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/if_bflb_dbg.cfg new file mode 100644 index 0000000000000000000000000000000000000000..ddcea93d486713f935293b19b36c7816e3d6f4d4 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/if_bflb_dbg.cfg @@ -0,0 +1,16 @@ +# BouffaloLab USB-JTAG/TTL adapter +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_channel 1 +ftdi_tdo_sample_edge falling +transport select jtag +adapter speed 10000 + +ftdi_layout_init 0x00f8 0x00fb +#ftdi_layout_signal nTRST -data 0x0400 +#ftdi_layout_signal nSRST -ndata 0x0020 + +#reset_config srst_only srst_push_pull +#adapter_nsrst_delay 100 +#adapter_nsrst_assert_width 100 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/if_rv_dbg_plus.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/if_rv_dbg_plus.cfg new file mode 100644 index 0000000000000000000000000000000000000000..aa60aa840833d48e0f219fd9442665a4002ae6ba --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/if_rv_dbg_plus.cfg @@ -0,0 +1,16 @@ +# BouffaloLab USB-JTAG/TTL adapter +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_channel 0 +#ftdi_tdo_sample_edge falling +transport select jtag +adapter speed 4000 + +ftdi_layout_init 0x00f8 0x00fb +#ftdi_layout_signal nTRST -data 0x0400 +#ftdi_layout_signal nSRST -ndata 0x0020 + +#reset_config srst_only srst_push_pull +#adapter_nsrst_delay 100 +#adapter_nsrst_assert_width 100 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/image-loader.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/image-loader.cfg new file mode 100644 index 0000000000000000000000000000000000000000..689ad2404c3678937a72d7fc45ab6c7a7243aca5 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/image-loader.cfg @@ -0,0 +1,22 @@ +# image loader + +proc install_bin {} { +# mww 0x21000000 0x55aaaa55 +# sleep 1000 + init + reset init + #reg pc 0x22010000 + #eflash_loader_openocd.bin no bootheader + load_image bl602/eflash_loader/eflash_loader_openocd.bin 0x22010000 bin + sleep 500 + reg pc 0x22010000 + reg mstatus 0x80000000 + sleep 500 + resume + shutdown +} + +echo "Ready for Remote Connections" + +#init +install_bin diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libftdi1.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libftdi1.dll new file mode 100644 index 0000000000000000000000000000000000000000..95c7c33b8d236b97405d1505a05bc3b03ce45895 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libftdi1.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb-0-1-4.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb-0-1-4.dll new file mode 100644 index 0000000000000000000000000000000000000000..d7988bb885a5e0485a18bd2f2df9713af0871308 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb-0-1-4.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb-1.0.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb-1.0.dll new file mode 100644 index 0000000000000000000000000000000000000000..c6f52123eed12fe8f3cc6b577f27d89c83c00ac6 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb-1.0.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb0.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb0.dll new file mode 100644 index 0000000000000000000000000000000000000000..28122e14fc06a2405942068d2d588e1741559aa4 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/libusb0.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/openocd b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/openocd new file mode 100644 index 0000000000000000000000000000000000000000..3dd3aa5d844ccb8929d2f08e2eb8f14f73042679 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/openocd differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/openocd-usb-sipeed.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/openocd-usb-sipeed.cfg new file mode 100644 index 0000000000000000000000000000000000000000..7ef76f455d94a3a59eddb5b6923dc35027d94834 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/openocd-usb-sipeed.cfg @@ -0,0 +1,25 @@ +# SiPEED USB-JTAG/TTL based on FT2232D +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 +# http://blog.sipeed.com/p/727.html +ftdi_channel 0 +transport select jtag +adapter speed 8000 + +ftdi_layout_init 0x0508 0x0f1b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400 + +set _CHIPNAME riscv +#jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x0 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +#$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 +#$_TARGETNAME.0 configure -work-area-phys 0x50000000 -work-area-size 32768 -work-area-backup 0 +$_TARGETNAME.0 configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 0 +riscv set_reset_timeout_sec 10 +riscv set_prefer_sba on +##riscv set_command_timeout_sec 1000 +echo "SiPEED USB-JTAG/TTL Ready for Remote Connections" diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/tgt_602.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/tgt_602.cfg new file mode 100644 index 0000000000000000000000000000000000000000..e7440763acca6804eb800961ab6d5572dbc7968e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/tgt_602.cfg @@ -0,0 +1,45 @@ +#target chip + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000c05 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1 +#$_TARGETNAME.0 configure -rtos auto + +echo "Ready for Remote Connections" + +$_TARGETNAME.0 configure -event reset-assert-pre { + echo "reset-assert-pre" + adapter speed 100 +} + +$_TARGETNAME.0 configure -event reset-deassert-post { + echo "reset-deassert-post" + adapter speed 4000 + reg mstatus 0x7800 + reg mie 0x0 +# reg pc 0x22008000 +} + +$_TARGETNAME.0 configure -event reset-init { + echo "reset-init" +# 4MHz for FPGA + adapter speed 4000 +} + +gdb_memory_map enable +gdb_flash_program disable + +riscv set_prefer_sba on +riscv set_command_timeout_sec 1 + +init +reset init + +#jtag arp_init + +#resume +#exit + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/tgt_702.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/tgt_702.cfg new file mode 100644 index 0000000000000000000000000000000000000000..1b0834b070c87d4b0875b79f1f9c15e8f68e09b9 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/bflb_flash_tool/utils/openocd/tgt_702.cfg @@ -0,0 +1,45 @@ +#target chip + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1 +#$_TARGETNAME.0 configure -rtos auto + +echo "Ready for Remote Connections" + +$_TARGETNAME.0 configure -event reset-assert-pre { + echo "reset-assert-pre" + adapter speed 100 +} + +$_TARGETNAME.0 configure -event reset-deassert-post { + echo "reset-deassert-post" + adapter speed 4000 + reg mstatus 0x7800 + reg mie 0x0 +# reg pc 0x22008000 +} + +$_TARGETNAME.0 configure -event reset-init { + echo "reset-init" +# 4MHz for FPGA + adapter speed 4000 +} + +gdb_memory_map enable +gdb_flash_program disable + +riscv set_prefer_sba on +riscv set_command_timeout_sec 1 + +init +reset init + +#jtag arp_init + +#resume +#exit + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/compiler_flags.cmake b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/compiler_flags.cmake new file mode 100644 index 0000000000000000000000000000000000000000..36361e117f9acd57612d7db3e5dda974dfeb4030 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/compiler_flags.cmake @@ -0,0 +1,21 @@ +list(APPEND GLOBAL_C_FLAGS -Os -g3) +list(APPEND GLOBAL_C_FLAGS -fshort-enums -fno-common -fms-extensions -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -ffast-math) +list(APPEND GLOBAL_C_FLAGS -Wall -Wshift-negative-value -Wchar-subscripts -Wformat -Wuninitialized -Winit-self -Wignored-qualifiers -Wunused -Wundef) +list(APPEND GLOBAL_C_FLAGS -msmall-data-limit=4) + +list(APPEND GLOBAL_LD_FLAGS -Wl,--cref -Wl,--gc-sections -nostartfiles -g3) +list(APPEND GLOBAL_LD_FLAGS -fms-extensions -ffunction-sections -fdata-sections) +list(APPEND GLOBAL_LD_FLAGS -Wall -Wchar-subscripts -std=c99) +list(APPEND GLOBAL_LD_FLAGS --specs=nano.specs) + + +if("${SUPPORT_FLOAT}" STREQUAL "y") +list(APPEND GLOBAL_LD_FLAGS -u _printf_float) +endif() + +# if(${SUPPORT_BACKTRACE} STREQUAL "y") +# list(APPEND GLOBAL_C_FLAGS -fno-omit-frame-pointer) +# endif() + + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/riscv64-unknown-elf-gcc.cmake b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/riscv64-unknown-elf-gcc.cmake new file mode 100644 index 0000000000000000000000000000000000000000..1565166834d0c753720069cf9970b91a823f95e1 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/riscv64-unknown-elf-gcc.cmake @@ -0,0 +1,40 @@ +SET(CMAKE_SYSTEM_NAME Generic) +SET(CMAKE_SYSTEM_VERSION 1) +set(CMAKE_SYSTEM_PROCESSOR RISCV) + +if(MINGW OR CYGWIN OR WIN32) + set(WHERE_CMD where) + set(TOOLCHAIN_SUFFIX ".exe") +elseif(UNIX OR APPLE) + set(WHERE_CMD which) + set(TOOLCHAIN_SUFFIX "") +endif() + +set(TOOLCHAIN_PREFIX riscv64-unknown-elf-) + +execute_process( + COMMAND ${WHERE_CMD} ${TOOLCHAIN_PREFIX}gcc + OUTPUT_VARIABLE TOOLCHAIN_PATH + OUTPUT_STRIP_TRAILING_WHITESPACE +) + +message(STATUS "TOOLCHAIN_PATH:${TOOLCHAIN_PATH}") +# specify cross compilers and tools +SET(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc${TOOLCHAIN_SUFFIX} CACHE INTERNAL "") +SET(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++${TOOLCHAIN_SUFFIX} CACHE INTERNAL "") +set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}gcc${TOOLCHAIN_SUFFIX} CACHE INTERNAL "") +set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}ld${TOOLCHAIN_SUFFIX} CACHE INTERNAL "") +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy CACHE INTERNAL "") +set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}objdump CACHE INTERNAL "") +set(SIZE ${TOOLCHAIN_PREFIX}size CACHE INTERNAL "") + +set(CMAKE_C_COMPILER_WORKS 1) +set(CMAKE_CXX_COMPILER_WORKS 1) + +set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_PATH}) +# search for programs in the build host directories +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +# for libraries and headers in the target directories +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/tools.cmake b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/tools.cmake new file mode 100644 index 0000000000000000000000000000000000000000..722cc4ebe90fb5aed63a316ae552a46f4023cd45 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/cmake/tools.cmake @@ -0,0 +1,261 @@ +function(generate_library) + get_filename_component(library_name ${CMAKE_CURRENT_LIST_DIR} NAME) + message(STATUS "[register library component: ${library_name}], path:${CMAKE_CURRENT_LIST_DIR}") + + add_library(${library_name}) + + # Add src to lib + if(ADD_SRCS) + target_sources(${library_name} PRIVATE ${ADD_SRCS}) + endif() + + # Add global config include + if(ADD_INCLUDE) + foreach(include_dir ${ADD_INCLUDE}) + get_filename_component(abs_dir ${include_dir} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_LIST_DIR}) + if(NOT IS_DIRECTORY ${abs_dir}) + message(FATAL_ERROR "${CMAKE_CURRENT_LIST_FILE}: ${include_dir} not found!") + endif() + target_include_directories(${library_name} PUBLIC ${abs_dir}) + endforeach() + endif() + + # Add private include + if(ADD_PRIVATE_INCLUDE) + foreach(include_dir ${ADD_PRIVATE_INCLUDE}) + get_filename_component(abs_dir ${include_dir} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_LIST_DIR}) + if(NOT IS_DIRECTORY ${abs_dir}) + message(FATAL_ERROR "${CMAKE_CURRENT_LIST_FILE}: ${include_dir} not found!") + endif() + target_include_directories(${library_name} PRIVATE ${abs_dir}) + endforeach() + endif() + + # Add definitions public + if(ADD_DEFINITIONS) + target_compile_options(${library_name} PUBLIC ${ADD_DEFINITIONS}) + endif() + + # Add definitions private + if(ADD_PRIVATE_DEFINITIONS) + target_compile_options(${library_name} PRIVATE ${ADD_DEFINITIONS_PRIVATE}) + endif() + + # Add requirements + if(ADD_REQUIREMENTS) + foreach(lib ${ADD_REQUIREMENTS}) + if(TARGET ${lib}) + add_dependencies(${library_name} ${lib}) + target_link_libraries(${library_name} ${lib}) + else() + message(FATAL_ERROR "${lib} is not a target") + endif() + endforeach() + endif() + + # Add static lib + if(ADD_STATIC_LIB) + foreach(lib ${ADD_STATIC_LIB}) + if(NOT EXISTS "${lib}") + message(FATAL_ERROR "Can not find ${lib}") + endif() + get_filename_component(static_lib_relative_dir ${lib} DIRECTORY) + get_filename_component(static_lib_name ${lib} NAME) + target_link_directories(${library_name} PUBLIC ${static_lib_relative_dir}) + target_link_libraries(${library_name} ${static_lib_name}) + endforeach() + endif() + + # Add dynamic lib + if(ADD_DYNAMIC_LIB) + foreach(lib ${ADD_DYNAMIC_LIB}) + if(NOT EXISTS "${lib}") + message(FATAL_ERROR "Can not find ${lib}") + endif() + get_filename_component(dynamic_lib_relative_dir ${lib} DIRECTORY) + get_filename_component(dynamic_lib_name ${lib} NAME) + target_link_directories(${library_name} PUBLIC ${dynamic_lib_relative_dir}) + target_link_libraries(${library_name} ${dynamic_lib_name}) + endforeach() + endif() +endfunction() + +function(generate_bin) + + get_filename_component(current_dir_name ${CMAKE_CURRENT_LIST_DIR} NAME) + string(REGEX REPLACE "(.*)/${current_dir_name}$" "\\1" above_absolute_dir ${CMAKE_CURRENT_LIST_DIR}) + get_filename_component(above_dir_name ${above_absolute_dir} NAME) + + execute_process( + COMMAND git submodule status + OUTPUT_VARIABLE GIT_SUBMODULE_INFO + OUTPUT_STRIP_TRAILING_WHITESPACE) + + # Add common options + add_compile_options(${GLOBAL_C_FLAGS}) + add_compile_options(-D${BOARD}) + add_compile_options($<$:-std=c99>) + add_compile_options($<$:-std=c++11>) + add_compile_options($<$:-nostdlib>) + add_compile_options($<$:-fno-rtti>) + add_compile_options($<$:-fno-exceptions>) + + # add basic library which is built by add_library + check_add_library(common ${CMAKE_SOURCE_DIR}/common) + check_add_library(${CHIP}_driver ${CMAKE_SOURCE_DIR}/drivers/${CHIP}_driver) + + # add other libraries which are target or extern library + if(TARGET_REQUIRED_LIBS) + file(GLOB_RECURSE lib_cmakelists_files ${CMAKE_SOURCE_DIR}/components/CMakeLists.txt) + foreach(lib ${TARGET_REQUIRED_LIBS}) + if(${lib} MATCHES "lib.*") + get_filename_component(exlib_absolute_dir ${lib} DIRECTORY) + get_filename_component(exlibrary_name ${lib} NAME_WE) + message(STATUS "[register extern library component: ${exlibrary_name}], path:${exlib_absolute_dir}") + elseif(lib_cmakelists_files) + + foreach(lib_cmakelists_file ${lib_cmakelists_files}) + get_filename_component(lib_absolute_dir ${lib_cmakelists_file} DIRECTORY) + get_filename_component(lib_absolute_dir_name ${lib_absolute_dir} NAME) + + if(${lib_absolute_dir_name} STREQUAL "${lib}") + check_add_library(${lib} ${lib_absolute_dir}) + endif() + endforeach() + else() + message(FATAL_ERROR "${lib} is not a target or a extern library") + endif() + endforeach() + endif() + + # list mains to execute,now is executing one elf + foreach(mainfile IN LISTS mains) + # Get file name without directory + get_filename_component(mainname ${mainfile} NAME_WE) + + if(DEFINED OUTPUT) + set(OUTPUT_DIR ${OUTPUT}) + set(target_name firmware) + else() + string(REPLACE "." ":" dot2colon ${APP_DIR}) + if(${dot2colon} MATCHES "::/") #if demo is not in sdk path + string(REPLACE "../" "" relative_dir ${APP_DIR}) + set(OUTPUT_DIR ${CMAKE_SOURCE_DIR}/out/${relative_dir}/${current_dir_name}) + elseif(${dot2colon} MATCHES ":")#if demo is in sdk peer path + set(OUTPUT_DIR ${CMAKE_SOURCE_DIR}/out/${current_dir_name}) + else() #if demo is in sdk path not in peer path + if(${APP_DIR} MATCHES ${above_dir_name}) #if demo has one-Layer Catalog + set(OUTPUT_DIR ${CMAKE_SOURCE_DIR}/out/${APP_DIR}/${current_dir_name}) + else() #if demo has Two-Layer Catalog + set(OUTPUT_DIR ${CMAKE_SOURCE_DIR}/out/${APP_DIR}/${above_dir_name}/${current_dir_name}) + endif() + + endif() + + file(WRITE ${CMAKE_CURRENT_SOURCE_DIR}/submodule_commit_info.txt ${GIT_SUBMODULE_INFO}) + set(target_name ${current_dir_name}) + endif() + + file(MAKE_DIRECTORY ${OUTPUT_DIR}) + set(HEX_FILE ${OUTPUT_DIR}/${target_name}.hex) + set(BIN_FILE ${OUTPUT_DIR}/${target_name}.bin) + set(MAP_FILE ${OUTPUT_DIR}/${target_name}.map) + set(ASM_FILE ${OUTPUT_DIR}/${target_name}.asm) + + if(TARGET_REQUIRED_SRCS) + foreach(src ${TARGET_REQUIRED_SRCS}) + if((NOT EXISTS ${src}) AND (NOT EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${src})) + message(FATAL_ERROR "${src} not exist,maybe you should autocomplete your path\r\n") + endif() + list(APPEND SRCS ${src}) + endforeach() + + endif() + + list(APPEND SRCS ${CMAKE_SOURCE_DIR}/bsp/bsp_common/platform/bflb_platform.c) + list(APPEND SRCS ${CMAKE_SOURCE_DIR}/bsp/bsp_common/platform/syscalls.c) + list(APPEND SRCS ${CMAKE_SOURCE_DIR}/bsp/board/${CHIP}/board.c) + + add_executable(${target_name}.elf ${mainfile} ${SRCS}) + target_link_options(${target_name}.elf PRIVATE ${GLOBAL_LD_FLAGS}) + set_target_properties(${target_name}.elf PROPERTIES LINK_FLAGS "-T${LINKER_SCRIPT} -Wl,-Map=${MAP_FILE}") + set_target_properties(${target_name}.elf PROPERTIES LINK_DEPENDS ${LINKER_SCRIPT}) + + set_target_properties(${target_name}.elf PROPERTIES RUNTIME_OUTPUT_DIRECTORY "${OUTPUT_DIR}") + + # Add private include + foreach(include_dir ${TARGET_REQUIRED_PRIVATE_INCLUDE}) + get_filename_component(abs_dir ${include_dir} ABSOLUTE BASE_DIR ${CMAKE_SOURCE_DIR}) + if(NOT IS_DIRECTORY ${abs_dir}) + message(FATAL_ERROR "${CMAKE_CURRENT_LIST_FILE}: ${include_dir} not found!") + endif() + target_include_directories(${target_name}.elf PRIVATE ${abs_dir}) + endforeach() + + # Add definitions private + if(TARGET_REQUIRED_PRIVATE_OPTIONS) + target_compile_options(${target_name}.elf PRIVATE ${TARGET_REQUIRED_PRIVATE_OPTIONS}) + endif() + + add_dependencies(${target_name}.elf ${CHIP}_driver) + # Add libs + target_link_libraries(${target_name}.elf ${CHIP}_driver c) + + if(TARGET_REQUIRED_LIBS) + target_link_libraries(${target_name}.elf ${TARGET_REQUIRED_LIBS}) + endif() + + target_link_libraries(${target_name}.elf m) + + add_custom_command(TARGET ${target_name}.elf POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${BIN_FILE} + COMMAND ${CMAKE_OBJDUMP} -d -S $ >${ASM_FILE} + # COMMAND ${CMAKE_OBJCOPY} -Oihex $ ${HEX_FILE} + COMMAND ${CMAKE_COMMAND} -E copy ${BIN_FILE} ${CMAKE_SOURCE_DIR}/tools/bflb_flash_tool/img/project.bin + COMMENT "Generate ${BIN_FILE}\r\nCopy ${BIN_FILE} into download path") + endforeach() +endfunction(generate_bin) + +function(search_application component_path) + +if(DEFINED APP) + + # find CMakeLists in ${component_path}/${APP}/,${APP} is the first directory + file(GLOB_RECURSE first_dir_cmakelists ${component_path}/${APP}/CMakeLists.txt) + + if(first_dir_cmakelists) + list(APPEND cmakelists_files ${first_dir_cmakelists}) + endif() + + # find CMakeLists in ${component_path}/*/${APP}*/,${APP} is the second directory + file(GLOB_RECURSE second_dir_cmakelists ${component_path}/*/${APP}*/CMakeLists.txt) + + if(second_dir_cmakelists) + list(APPEND cmakelists_files ${second_dir_cmakelists}) + endif() + + list(REMOVE_DUPLICATES cmakelists_files) + + if(cmakelists_files) + #build app finding + foreach(cmakelists_file IN LISTS cmakelists_files) + get_filename_component(app_absolute_dir ${cmakelists_file} DIRECTORY) + get_filename_component(app_absolute_dir_name ${app_absolute_dir} NAME) + message(STATUS "[run app:${app_absolute_dir_name}], path:${app_absolute_dir}") + add_subdirectory(${app_absolute_dir} ${CMAKE_SOURCE_DIR}/build/samples/${app_absolute_dir_name}) + endforeach() + else() + message(FATAL_ERROR "can not find ${APP} in the first or second directory under the path:${component_path}") + endif() + +else() +add_subdirectory($ENV{PROJECT_DIR}/src src) +endif() + +endfunction() + +function(check_add_library target_name directory) + if(NOT TARGET ${target_name}) + add_subdirectory(${directory} ${CMAKE_SOURCE_DIR}/build/libraries/${target_name}) + endif() +endfunction() \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/602.init b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/602.init new file mode 100644 index 0000000000000000000000000000000000000000..76910ed8741d72735d7ef594c2130ba482a29f8a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/602.init @@ -0,0 +1,15 @@ +set architecture riscv:rv32 +#target remote :3333 +#set disassemble-next-line on +set mem inaccessible-by-default off +#gdb_breakpoint_override [hard|soft|disable] + +mem 0x22008000 0x22014000 rw +mem 0x42008000 0x42014000 rw +mem 0x22014000 0x22020000 rw +mem 0x42014000 0x42020000 rw +mem 0x22020000 0x22030000 rw +mem 0x42020000 0x42030000 rw +mem 0x22030000 0x2204C000 rw +mem 0x42030000 0x4204C000 rw +mem 0x23000000 0x23400000 ro diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/602.svd b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/602.svd new file mode 100644 index 0000000000000000000000000000000000000000..63f23bc7ff96e10d819892f66fdb1ac468cb43bb --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/602.svd @@ -0,0 +1,236 @@ + + + bouffalolab + bouffalolab + 602 + WiFi BT + + high-performance, 32-bit RV32IMAFC core + + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + 602 + little + + + + + + CLINT + Core Local Interruptor. + 0x02000000 + CLINT + 32 + read-write + + + 0 + 0x10000 + registers + + + + + + MSIP + Machine Software Interrupt Pending Register. + 0x0000 + + + + MTIMECMP_LO + Machine Timer Compare Register Low. + 0x4000 + + + + MTIMECMP_HI + Machine Timer Compare Register High. + 0x4004 + + + + MTIME_LO + Machine Timer Register Low. + 0xBFF8 + + + + MTIME_HI + Machine Timer Register High. + 0xBFFC + + + + + + + CLIC + Core Local Interrupter controller. + 0x02800000 + CLIC + 8 + read-write + + + 0 + 0x10000 + registers + + + + + + 128 + 1 + PENDING[%s] + CLIC Interrupt Pending Registers. + 0x0000 + + PENDING00 + + + + + 128 + 1 + ENABLE[%s] + CLIC Interrupt enable Registers. + 0x0400 + + ENABLE00 + + + + + 128 + 1 + INTCFG[%s] + CLIC Interrupt config Registers. + 0x0800 + + INTCFG37 + + + + + clic_cfg + clic_cfg. + 0x0C00 + + nvbits00 + nlbits13 + nmbits45 + + + + + + + + GLB + GLB. + 0x40000000 + GLB + 32 + read-write + + + 0 + 0x1000 + registers + + + + + + clk_cfg0 + clk_cfg0. + 0x0000 + + pll_en00 + fclk_en11 + hclk_en22 + bclk_en33 + pll_set45 + hbn_root_clk_set67 + hclk_div815 + bclk_div1623 + fclk_sw_state2426 + chip_rdy2727 + glb_id2831 + + + + + + + + + eFuse + eFuse Programmable Memory. + 0x40007000 + eFuse + 32 + read-only + + + 0 + 0x1000 + registers + + + + + + ef_cfg_0 + ef_cfg_0. + 0x0000 + + ef_sboot_en45 + ef_boot_sel811 + ef_cpu0_enc_en77 + ef_cpu1_enc_en66 + ef_sboot_en45 + ef_sboot_sign_mode23 + ef_sf_aes_mode01 + + + + + ef_wifi_mac_low + ef_wifi_mac_low. + 0x0014 + + mac_addr1031 + + + + + ef_wifi_mac_high + ef_wifi_mac_high. + 0x0018 + + dev_info73131 + dev_info63030 + dev_info52929 + dev_info4_32728 + dev_info2_02426 + cust_id1_02223 + mac_addr1_crc5_01621 + mac_addr1015 + + + + + + + + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/702.init b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/702.init new file mode 100644 index 0000000000000000000000000000000000000000..76910ed8741d72735d7ef594c2130ba482a29f8a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/702.init @@ -0,0 +1,15 @@ +set architecture riscv:rv32 +#target remote :3333 +#set disassemble-next-line on +set mem inaccessible-by-default off +#gdb_breakpoint_override [hard|soft|disable] + +mem 0x22008000 0x22014000 rw +mem 0x42008000 0x42014000 rw +mem 0x22014000 0x22020000 rw +mem 0x42014000 0x42020000 rw +mem 0x22020000 0x22030000 rw +mem 0x42020000 0x42030000 rw +mem 0x22030000 0x2204C000 rw +mem 0x42030000 0x4204C000 rw +mem 0x23000000 0x23400000 ro diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/99-openocd.rules b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/99-openocd.rules new file mode 100644 index 0000000000000000000000000000000000000000..f6dc01ee3466a4743a8cc09efa0749a2024199aa --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/99-openocd.rules @@ -0,0 +1,3 @@ +# Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC +SUBSYSTEM=="tty", ATTRS{idVendor}=="0403",ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev" +SUBSYSTEM=="usb", ATTR{idVendor} =="0403",ATTR{idProduct} =="6010", MODE="664", GROUP="plugdev" \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/bl70x_gdb.init b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/bl70x_gdb.init new file mode 100644 index 0000000000000000000000000000000000000000..86565d8e3c1fcbb45c0b617ee16c7ca9a8056c5a --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/bl70x_gdb.init @@ -0,0 +1,21 @@ +set mem inaccessible-by-default off +set architecture riscv:rv32 +set remotetimeout 250 + +mon reset + +set $pc=0x21000000 +set $mie=0 +set $mstatus=0x1880 + +mem 0x22008000 0x22014000 rw +mem 0x42008000 0x42014000 rw +mem 0x22014000 0x22020000 rw +mem 0x42014000 0x42020000 rw +mem 0x22020000 0x22030000 rw +mem 0x42020000 0x42030000 rw +mem 0x22030000 0x2204C000 rw +mem 0x42030000 0x4204C000 rw +mem 0x23000000 0x23400000 ro + + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/if_bflb_dbg.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/if_bflb_dbg.cfg new file mode 100644 index 0000000000000000000000000000000000000000..ddcea93d486713f935293b19b36c7816e3d6f4d4 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/if_bflb_dbg.cfg @@ -0,0 +1,16 @@ +# BouffaloLab USB-JTAG/TTL adapter +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_channel 1 +ftdi_tdo_sample_edge falling +transport select jtag +adapter speed 10000 + +ftdi_layout_init 0x00f8 0x00fb +#ftdi_layout_signal nTRST -data 0x0400 +#ftdi_layout_signal nSRST -ndata 0x0020 + +#reset_config srst_only srst_push_pull +#adapter_nsrst_delay 100 +#adapter_nsrst_assert_width 100 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/if_rv_dbg_plus.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/if_rv_dbg_plus.cfg new file mode 100644 index 0000000000000000000000000000000000000000..aa60aa840833d48e0f219fd9442665a4002ae6ba --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/if_rv_dbg_plus.cfg @@ -0,0 +1,16 @@ +# BouffaloLab USB-JTAG/TTL adapter +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_channel 0 +#ftdi_tdo_sample_edge falling +transport select jtag +adapter speed 4000 + +ftdi_layout_init 0x00f8 0x00fb +#ftdi_layout_signal nTRST -data 0x0400 +#ftdi_layout_signal nSRST -ndata 0x0020 + +#reset_config srst_only srst_push_pull +#adapter_nsrst_delay 100 +#adapter_nsrst_assert_width 100 diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libftdi1.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libftdi1.dll new file mode 100644 index 0000000000000000000000000000000000000000..95c7c33b8d236b97405d1505a05bc3b03ce45895 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libftdi1.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb-0-1-4.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb-0-1-4.dll new file mode 100644 index 0000000000000000000000000000000000000000..d7988bb885a5e0485a18bd2f2df9713af0871308 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb-0-1-4.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb-1.0.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb-1.0.dll new file mode 100644 index 0000000000000000000000000000000000000000..c6f52123eed12fe8f3cc6b577f27d89c83c00ac6 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb-1.0.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb0.dll b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb0.dll new file mode 100644 index 0000000000000000000000000000000000000000..28122e14fc06a2405942068d2d588e1741559aa4 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/libusb0.dll differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/openocd b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/openocd new file mode 100644 index 0000000000000000000000000000000000000000..3dd3aa5d844ccb8929d2f08e2eb8f14f73042679 Binary files /dev/null and b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/openocd differ diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/tgt_602.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/tgt_602.cfg new file mode 100644 index 0000000000000000000000000000000000000000..e7440763acca6804eb800961ab6d5572dbc7968e --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/tgt_602.cfg @@ -0,0 +1,45 @@ +#target chip + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000c05 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1 +#$_TARGETNAME.0 configure -rtos auto + +echo "Ready for Remote Connections" + +$_TARGETNAME.0 configure -event reset-assert-pre { + echo "reset-assert-pre" + adapter speed 100 +} + +$_TARGETNAME.0 configure -event reset-deassert-post { + echo "reset-deassert-post" + adapter speed 4000 + reg mstatus 0x7800 + reg mie 0x0 +# reg pc 0x22008000 +} + +$_TARGETNAME.0 configure -event reset-init { + echo "reset-init" +# 4MHz for FPGA + adapter speed 4000 +} + +gdb_memory_map enable +gdb_flash_program disable + +riscv set_prefer_sba on +riscv set_command_timeout_sec 1 + +init +reset init + +#jtag arp_init + +#resume +#exit + diff --git a/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/tgt_702.cfg b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/tgt_702.cfg new file mode 100644 index 0000000000000000000000000000000000000000..1b0834b070c87d4b0875b79f1f9c15e8f68e09b9 --- /dev/null +++ b/bsp/bouffalolab/libraries/bl_mcu_sdk/tools/openocd/tgt_702.cfg @@ -0,0 +1,45 @@ +#target chip + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1 +#$_TARGETNAME.0 configure -rtos auto + +echo "Ready for Remote Connections" + +$_TARGETNAME.0 configure -event reset-assert-pre { + echo "reset-assert-pre" + adapter speed 100 +} + +$_TARGETNAME.0 configure -event reset-deassert-post { + echo "reset-deassert-post" + adapter speed 4000 + reg mstatus 0x7800 + reg mie 0x0 +# reg pc 0x22008000 +} + +$_TARGETNAME.0 configure -event reset-init { + echo "reset-init" +# 4MHz for FPGA + adapter speed 4000 +} + +gdb_memory_map enable +gdb_flash_program disable + +riscv set_prefer_sba on +riscv set_command_timeout_sec 1 + +init +reset init + +#jtag arp_init + +#resume +#exit + diff --git a/bsp/bouffalolab/libraries/drivers/board.c b/bsp/bouffalolab/libraries/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..2b62715732eb8c3c969a5745cd6c9d63aef17192 --- /dev/null +++ b/bsp/bouffalolab/libraries/drivers/board.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include "board.h" +#include "hal_uart.h" +#include "ring_buffer.h" +#include "shell.h" + +#define UART_RX_SIZE 256 +uint8_t uart_rx_mem[UART_RX_SIZE]; +Ring_Buffer_Type uart_rx_rb; +static struct rt_semaphore shell_rx_sem; /* 定义一个静态信号量 */ + +void shell_irq_callback(struct device *dev, void *args, uint32_t size, uint32_t state) +{ + Ring_Buffer_Write_Byte(&uart_rx_rb, *(uint8_t *)args); + rt_sem_release(&shell_rx_sem); +} + +void systick_isr() +{ + rt_interrupt_enter(); + rt_tick_increase(); + rt_interrupt_leave(); +} + +void rt_hw_console_output(const char *str) +{ + rt_size_t i = 0, size = 0; + char a = '\r'; + + struct device *uart = device_find("debug_log"); + + size = rt_strlen(str); + for (i = 0; i < size; i++) { + if (*(str + i) == '\n') { + device_write(uart, 0, (uint8_t *)&a, 1); + } + device_write(uart, 0, (uint8_t *)(str + i), 1); + } +} + +char rt_hw_console_getchar(void) +{ + char ch = 0; + /* 从 ringbuffer 中拿出数据 */ + while (Ring_Buffer_Read_Byte(&uart_rx_rb, (rt_uint8_t *)&ch) != 1) { + rt_sem_take(&shell_rx_sem, RT_WAITING_FOREVER); + } + return ch; +} + +void rt_hw_board_init(void) +{ + bflb_platform_init(0); + + bflb_platform_set_alarm_time(RT_TICK_PER_SECOND, systick_isr); + +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_DEVICE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + return; +} + +void uart_shell_init(void) +{ + struct device *uart = device_find("debug_log"); + if (uart) { + Ring_Buffer_Init(&uart_rx_rb, uart_rx_mem, UART_RX_SIZE, NULL, NULL); + device_set_callback(uart, shell_irq_callback); + device_control(uart, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT)); + } + rt_sem_init(&(shell_rx_sem), "shell_rx", 0, 0); + finsh_system_init(); +} \ No newline at end of file diff --git a/bsp/bouffalolab/libraries/drivers/board.h b/bsp/bouffalolab/libraries/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..6aac94ca9588049627f0f4395bc7ba9c2cc44bfb --- /dev/null +++ b/bsp/bouffalolab/libraries/drivers/board.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __BOARD__ +#define __BOARD__ + +#endif